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authorSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>2019-03-28 23:11:49 +0300
committerMarek Vasut <marex@denx.de>2019-04-25 01:00:49 +0300
commit4e829e9841f80c540150a14b4d12169139a0b7b9 (patch)
treee9611d73f0f3752dda794df85b59d9c6e8131e3b /drivers
parent36821b3f55adc26c593520d8c207eea36c5c264a (diff)
downloadu-boot-4e829e9841f80c540150a14b4d12169139a0b7b9.tar.xz
rtc: m41t62: add compatible for m41t82
This adds a compatible string for m41t82. This ensures that this driver can be used for m41t82 in DM mode, too (asit was usable for this model in non-DM mode before). In addition, the HT bit has to be reset during probe, since the m41t82 chip sets it when entering battery standby mode. This patch ensures this driver works on socfpga_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/rtc/m41t62.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c
index 2ee7e00b02..6161b76712 100644
--- a/drivers/rtc/m41t62.c
+++ b/drivers/rtc/m41t62.c
@@ -155,6 +155,15 @@ static int m41t62_rtc_reset(struct udevice *dev)
return ret;
}
+/*
+ * Make sure HT bit is cleared. This bit is set on entering battery backup
+ * mode, so do this before the first read access.
+ */
+static int m41t62_rtc_probe(struct udevice *dev)
+{
+ return m41t62_rtc_reset(dev);
+}
+
static const struct rtc_ops m41t62_rtc_ops = {
.get = m41t62_rtc_get,
.set = m41t62_rtc_set,
@@ -163,6 +172,7 @@ static const struct rtc_ops m41t62_rtc_ops = {
static const struct udevice_id m41t62_rtc_ids[] = {
{ .compatible = "st,m41t62" },
+ { .compatible = "st,m41t82" },
{ .compatible = "microcrystal,rv4162" },
{ }
};
@@ -172,6 +182,7 @@ U_BOOT_DRIVER(rtc_m41t62) = {
.id = UCLASS_RTC,
.of_match = m41t62_rtc_ids,
.ops = &m41t62_rtc_ops,
+ .probe = &m41t62_rtc_probe,
};
#else /* NON DM RTC code - will be removed */