Merge git://git.denx.de/u-boot-x86

3 files changed, 46 insertions, 21 deletions

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 1cd1e409e3..46e9c71bdf 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -810,8 +810,8 @@ error:
 	return ret;
 }
 
-static int decode_regions(struct pci_controller *hose, ofnode parent_node,
-			  ofnode node)
+static void decode_regions(struct pci_controller *hose, ofnode parent_node,
+			   ofnode node)
 {
 	int pci_addr_cells, addr_cells, size_cells;
 	int cells_per_record;
@@ -820,8 +820,11 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
 	int i;
 
 	prop = ofnode_get_property(node, "ranges", &len);
-	if (!prop)
-		return -EINVAL;
+	if (!prop) {
+		debug("%s: Cannot decode regions\n", __func__);
+		return;
+	}
+
 	pci_addr_cells = ofnode_read_simple_addr_cells(node);
 	addr_cells = ofnode_read_simple_addr_cells(parent_node);
 	size_cells = ofnode_read_simple_size_cells(node);
@@ -883,7 +886,7 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
 	bd_t *bd = gd->bd;
 
 	if (!bd)
-		return 0;
+		return;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
 		if (bd->bi_dram[i].size) {
@@ -908,13 +911,12 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
 			base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 #endif
 
-	return 0;
+	return;
 }
 
 static int pci_uclass_pre_probe(struct udevice *bus)
 {
 	struct pci_controller *hose;
-	int ret;
 
 	debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
 	      bus->parent->name);
@@ -923,12 +925,7 @@ static int pci_uclass_pre_probe(struct udevice *bus)
 	/* For bridges, use the top-level PCI controller */
 	if (!device_is_on_pci_bus(bus)) {
 		hose->ctlr = bus;
-		ret = decode_regions(hose, dev_ofnode(bus->parent),
-				     dev_ofnode(bus));
-		if (ret) {
-			debug("%s: Cannot decode regions\n", __func__);
-			return ret;
-		}
+		decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
 	} else {
 		struct pci_controller *parent_hose;
 
@@ -1185,6 +1182,11 @@ static int _dm_pci_bus_to_phys(struct udevice *ctlr,
 	struct pci_region *res;
 	int i;
 
+	if (hose->region_count == 0) {
+		*pa = bus_addr;
+		return 0;
+	}
+
 	for (i = 0; i < hose->region_count; i++) {
 		res = &hose->regions[i];
 
@@ -1248,6 +1250,11 @@ int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
 	ctlr = pci_get_controller(dev);
 	hose = dev_get_uclass_priv(ctlr);
 
+	if (hose->region_count == 0) {
+		*ba = phys_addr;
+		return 0;
+	}
+
 	for (i = 0; i < hose->region_count; i++) {
 		res = &hose->regions[i];
 
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index c7fefd2031..cf869998bf 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -21,6 +21,17 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static unsigned long cpu_mhz_from_cpuid(void)
+{
+	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+		return 0;
+
+	if (cpuid_eax(0) < 0x16)
+		return 0;
+
+	return cpuid_eax(0x16);
+}
+
 /*
  * According to Intel 64 and IA-32 System Programming Guide,
  * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
@@ -343,13 +354,21 @@ static void tsc_timer_ensure_setup(void)
 	if (!gd->arch.clock_rate) {
 		unsigned long fast_calibrate;
 
+		fast_calibrate = cpu_mhz_from_cpuid();
+		if (fast_calibrate)
+			goto done;
+
 		fast_calibrate = cpu_mhz_from_msr();
-		if (!fast_calibrate) {
-			fast_calibrate = quick_pit_calibrate();
-			if (!fast_calibrate)
-				panic("TSC frequency is ZERO");
-		}
+		if (fast_calibrate)
+			goto done;
+
+		fast_calibrate = quick_pit_calibrate();
+		if (fast_calibrate)
+			goto done;
+
+		panic("TSC frequency is ZERO");
 
+done:
 		gd->arch.clock_rate = fast_calibrate * 1000000;
 	}
 }
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index e8fd6bf6ae..b995aef997 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -23,9 +23,8 @@ static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
 	hcor = (struct xhci_hcor *)((uintptr_t) hccr +
 			HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
 
-	debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
-	      (u32)hccr, (u32)hcor,
-	      (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
+	debug("XHCI-PCI init hccr %p and hcor %p hc_length %d\n",
+	      hccr, hcor, (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
 
 	*ret_hccr = hccr;
 	*ret_hcor = hcor;