Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a
- lx2-watchdog support
- layerscape: pci-endpoint support, spin table relocation fixes and
  cleanups
- fsl-crypto: RNG support and bug fixes

30 files changed, 1464 insertions, 687 deletions

diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 181a1e5e99..5ed6140da3 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -45,3 +45,17 @@ config SYS_FSL_SEC_COMPAT
 
 config SYS_FSL_SEC_LE
 	bool "Little-endian access to Freescale Secure Boot"
+
+if FSL_CAAM
+
+config FSL_CAAM_RNG
+	bool "Enable Random Number Generator support"
+	depends on DM_RNG
+	default y
+	help
+	  Enable support for the hardware based random number generator
+	  module of the CAAM. The random data is fetched from the DRGB
+	  using the prediction resistance flag which means the DRGB is
+	  reseeded from the TRNG every time random data is generated.
+
+endif
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index cfb36f3bb9..a5e8d38e38 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
 obj-$(CONFIG_CMD_BLOB) += fsl_blob.o
 obj-$(CONFIG_CMD_DEKBLOB) += fsl_blob.o
 obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
+obj-$(CONFIG_FSL_CAAM_RNG) += rng.o
diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h
index 11ad506829..3589e6ea02 100644
--- a/drivers/crypto/fsl/desc.h
+++ b/drivers/crypto/fsl/desc.h
@@ -520,6 +520,8 @@
 #define OP_ALG_ICV_OFF		(0 << OP_ALG_ICV_SHIFT)
 #define OP_ALG_ICV_ON		(1 << OP_ALG_ICV_SHIFT)
 
+#define OP_ALG_PR_ON		0x02
+
 #define OP_ALG_DIR_SHIFT	0
 #define OP_ALG_DIR_MASK		1
 #define OP_ALG_DECRYPT		0
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index cb112283ac..b82ba83e73 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -36,19 +36,16 @@
 			       (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
 
 #ifdef CONFIG_PHYS_64BIT
-union ptr_addr_t {
-	u64 m_whole;
-	struct {
+struct ptr_addr_t {
 #ifdef CONFIG_SYS_FSL_SEC_LE
-		u32 low;
-		u32 high;
+	u32 low;
+	u32 high;
 #elif defined(CONFIG_SYS_FSL_SEC_BE)
-		u32 high;
-		u32 low;
+	u32 high;
+	u32 low;
 #else
 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
 #endif
-	} m_halfs;
 };
 #endif
 
@@ -57,9 +54,10 @@ static inline void pdb_add_ptr(dma_addr_t *offset, dma_addr_t ptr)
 #ifdef CONFIG_PHYS_64BIT
 	/* The Position of low and high part of 64 bit address
 	 * will depend on the endianness of CAAM Block */
-	union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
-	ptr_addr->m_halfs.high = (u32)(ptr >> 32);
-	ptr_addr->m_halfs.low = (u32)ptr;
+	struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset;
+
+	ptr_addr->high = (u32)(ptr >> 32);
+	ptr_addr->low = (u32)ptr;
 #else
 	*offset = ptr;
 #endif
@@ -111,9 +109,10 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
 #ifdef CONFIG_PHYS_64BIT
 	/* The Position of low and high part of 64 bit address
 	 * will depend on the endianness of CAAM Block */
-	union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
-	ptr_addr->m_halfs.high = (u32)(ptr >> 32);
-	ptr_addr->m_halfs.low = (u32)ptr;
+	struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset;
+
+	ptr_addr->high = (u32)(ptr >> 32);
+	ptr_addr->low = (u32)ptr;
 #else
 	*offset = ptr;
 #endif
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index 953deec9ff..61f953e8a6 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -86,7 +86,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
 			    unsigned int size, int is_last,
 			    enum caam_hash_algos caam_algo)
 {
-	uint32_t final = 0;
+	uint32_t final;
 	phys_addr_t addr = virt_to_phys((void *)buf);
 	struct sha_ctx *ctx = hash_ctx;
 
diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c
index 2f35e0c90b..fbc1aeddee 100644
--- a/drivers/crypto/fsl/jobdesc.c
+++ b/drivers/crypto/fsl/jobdesc.c
@@ -102,8 +102,8 @@ int caam_page_alloc(uint8_t page_num, uint8_t partition_num)
 
 	/* if the page is not owned => problem */
 	if ((temp_reg & SMCSJR_PO) != PAGE_OWNED) {
-		printf("Allocation of page %d in partition %d failed 0x%X\n",
-		       temp_reg, page_num, partition_num);
+		printf("Allocation of page %u in partition %u failed 0x%X\n",
+		       page_num, partition_num, temp_reg);
 
 		return ERROR_IN_PAGE_ALLOC;
 	}
@@ -258,7 +258,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
  * Descriptor to instantiate RNG State Handle 0 in normal mode and
  * load the JDKEK, TDKEK and TDSK registers
  */
-void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc, int handle)
+void inline_cnstr_jobdesc_rng_instantiation(u32 *desc, int handle, int do_sk)
 {
 	u32 *jump_cmd;
 
@@ -266,10 +266,11 @@ void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc, int handle)
 
 	/* INIT RNG in non-test mode */
 	append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
-			(handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT);
+			 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT |
+			 OP_ALG_PR_ON);
 
 	/* For SH0, Secure Keys must be generated as well */
-	if (handle == 0) {
+	if (!handle && do_sk) {
 		/* wait for done */
 		jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
 		set_jump_tgt_here(desc, jump_cmd);
@@ -286,6 +287,25 @@ void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc, int handle)
 	}
 }
 
+/* Descriptor for deinstantiation of the RNG block. */
+void inline_cnstr_jobdesc_rng_deinstantiation(u32 *desc, int handle)
+{
+	init_job_desc(desc, 0);
+
+	append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
+			 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
+}
+
+void inline_cnstr_jobdesc_rng(u32 *desc, void *data_out, u32 size)
+{
+	dma_addr_t dma_data_out = virt_to_phys(data_out);
+
+	init_job_desc(desc, 0);
+	append_operation(desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG |
+			 OP_ALG_PR_ON);
+	append_fifo_store(desc, dma_data_out, size, FIFOST_TYPE_RNGSTORE);
+}
+
 /* Change key size to bytes form bits in calling function*/
 void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
 				      struct pk_in_params *pkin, uint8_t *out,
diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h
index d782c46b9d..c4501abd26 100644
--- a/drivers/crypto/fsl/jobdesc.h
+++ b/drivers/crypto/fsl/jobdesc.h
@@ -39,9 +39,14 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
 				     uint8_t *enc_blob, uint8_t *plain_txt,
 				     uint32_t out_sz);
 
-void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc, int handle);
+void inline_cnstr_jobdesc_rng_instantiation(u32 *desc, int handle, int do_sk);
+
+void inline_cnstr_jobdesc_rng_deinstantiation(u32 *desc, int handle);
+
+void inline_cnstr_jobdesc_rng(u32 *desc, void *data_out, u32 size);
 
 void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
 				      struct pk_in_params *pkin, uint8_t *out,
 				      uint32_t out_siz);
+
 #endif
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index e2d9216cfc..44273c345f 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <cpu_func.h>
+#include <linux/kernel.h>
 #include <log.h>
 #include <malloc.h>
 #include "fsl_sec.h"
@@ -19,6 +20,7 @@
 #include <asm/cache.h>
 #include <asm/fsl_pamu.h>
 #endif
+#include <dm/lists.h>
 
 #define CIRC_CNT(head, tail, size)	(((head) - (tail)) & (size - 1))
 #define CIRC_SPACE(head, tail, size)	CIRC_CNT((tail), (head) + 1, (size))
@@ -446,7 +448,52 @@ int sec_reset(void)
 	return sec_reset_idx(0);
 }
 #ifndef CONFIG_SPL_BUILD
-static int instantiate_rng(uint8_t sec_idx)
+static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
+{
+	u32 *desc;
+	int sh_idx, ret = 0;
+	int desc_size = ALIGN(sizeof(u32) * 2, ARCH_DMA_MINALIGN);
+
+	desc = memalign(ARCH_DMA_MINALIGN, desc_size);
+	if (!desc) {
+		debug("cannot allocate RNG init descriptor memory\n");
+		return -ENOMEM;
+	}
+
+	for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
+		/*
+		 * If the corresponding bit is set, then it means the state
+		 * handle was initialized by us, and thus it needs to be
+		 * deinitialized as well
+		 */
+
+		if (state_handle_mask & RDSTA_IF(sh_idx)) {
+			/*
+			 * Create the descriptor for deinstantating this state
+			 * handle.
+			 */
+			inline_cnstr_jobdesc_rng_deinstantiation(desc, sh_idx);
+			flush_dcache_range((unsigned long)desc,
+					   (unsigned long)desc + desc_size);
+
+			ret = run_descriptor_jr_idx(desc, sec_idx);
+			if (ret) {
+				printf("SEC%u:  RNG4 SH%d deinstantiation failed with error 0x%x\n",
+				       sec_idx, sh_idx, ret);
+				ret = -EIO;
+				break;
+			}
+
+			printf("SEC%u:  Deinstantiated RNG4 SH%d\n",
+			       sec_idx, sh_idx);
+		}
+	}
+
+	free(desc);
+	return ret;
+}
+
+static int instantiate_rng(u8 sec_idx, int gen_sk)
 {
 	u32 *desc;
 	u32 rdsta_val;
@@ -466,11 +513,20 @@ static int instantiate_rng(uint8_t sec_idx)
 		 * If the corresponding bit is set, this state handle
 		 * was initialized by somebody else, so it's left alone.
 		 */
-		rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
-		if (rdsta_val & (1 << sh_idx))
-			continue;
+		rdsta_val = sec_in32(&rng->rdsta);
+		if (rdsta_val & (RDSTA_IF(sh_idx))) {
+			if (rdsta_val & RDSTA_PR(sh_idx))
+				continue;
+
+			printf("SEC%u:  RNG4 SH%d was instantiated w/o prediction resistance. Tearing it down\n",
+			       sec_idx, sh_idx);
 
-		inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx);
+			ret = deinstantiate_rng(sec_idx, RDSTA_IF(sh_idx));
+			if (ret)
+				break;
+		}
+
+		inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx, gen_sk);
 		size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
 		flush_dcache_range((unsigned long)desc,
 				   (unsigned long)desc + size);
@@ -478,11 +534,11 @@ static int instantiate_rng(uint8_t sec_idx)
 		ret = run_descriptor_jr_idx(desc, sec_idx);
 
 		if (ret)
-			printf("RNG: Instantiation failed with error 0x%x\n",
-			       ret);
+			printf("SEC%u:  RNG4 SH%d instantiation failed with error 0x%x\n",
+			       sec_idx, sh_idx, ret);
 
-		rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
-		if (!(rdsta_val & (1 << sh_idx))) {
+		rdsta_val = sec_in32(&rng->rdsta);
+		if (!(rdsta_val & RDSTA_IF(sh_idx))) {
 			free(desc);
 			return -1;
 		}
@@ -498,9 +554,17 @@ static int instantiate_rng(uint8_t sec_idx)
 static u8 get_rng_vid(uint8_t sec_idx)
 {
 	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
-	u32 cha_vid = sec_in32(&sec->chavid_ls);
+	u8 vid;
+
+	if (caam_get_era() < 10) {
+		vid = (sec_in32(&sec->chavid_ls) & SEC_CHAVID_RNG_LS_MASK)
+		       >> SEC_CHAVID_LS_RNG_SHIFT;
+	} else {
+		vid = (sec_in32(&sec->vreg.rng) & CHA_VER_VID_MASK)
+		       >> CHA_VER_VID_SHIFT;
+	}
 
-	return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
+	return vid;
 }
 
 /*
@@ -538,14 +602,15 @@ static void kick_trng(int ent_delay, uint8_t sec_idx)
 
 static int rng_init(uint8_t sec_idx)
 {
-	int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
+	int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
 	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 	u32 inst_handles;
 
+	gen_sk = !(sec_in32(&rng->rdsta) & RDSTA_SKVN);
 	do {
-		inst_handles = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
+		inst_handles = sec_in32(&rng->rdsta) & RDSTA_MASK;
 
 		/*
 		 * If either of the SH's were instantiated by somebody else
@@ -566,10 +631,10 @@ static int rng_init(uint8_t sec_idx)
 		 * interval, leading to a sucessful initialization of
 		 * the RNG.
 		 */
-		ret = instantiate_rng(sec_idx);
+		ret = instantiate_rng(sec_idx, gen_sk);
 	} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 	if (ret) {
-		printf("RNG: Failed to instantiate RNG\n");
+		printf("SEC%u:  Failed to instantiate RNG\n", sec_idx);
 		return ret;
 	}
 
@@ -592,7 +657,7 @@ int sec_init_idx(uint8_t sec_idx)
 #endif
 
 	if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
-		printf("SEC initialization failed\n");
+		printf("SEC%u:  initialization failed\n", sec_idx);
 		return -1;
 	}
 
@@ -640,7 +705,7 @@ int sec_init_idx(uint8_t sec_idx)
 
 	ret = jr_init(sec_idx);
 	if (ret < 0) {
-		printf("SEC initialization failed\n");
+		printf("SEC%u:  initialization failed\n", sec_idx);
 		return -1;
 	}
 
@@ -654,10 +719,18 @@ int sec_init_idx(uint8_t sec_idx)
 #ifndef CONFIG_SPL_BUILD
 	if (get_rng_vid(sec_idx) >= 4) {
 		if (rng_init(sec_idx) < 0) {
-			printf("SEC%u: RNG instantiation failed\n", sec_idx);
+			printf("SEC%u:  RNG instantiation failed\n", sec_idx);
 			return -1;
 		}
-		printf("SEC%u: RNG instantiated\n", sec_idx);
+
+		if (IS_ENABLED(CONFIG_DM_RNG)) {
+			ret = device_bind_driver(NULL, "caam-rng", "caam-rng",
+						 NULL);
+			if (ret)
+				printf("Couldn't bind rng driver (%d)\n", ret);
+		}
+
+		printf("SEC%u:  RNG instantiated\n", sec_idx);
 	}
 #endif
 	return ret;
diff --git a/drivers/crypto/fsl/rng.c b/drivers/crypto/fsl/rng.c
new file mode 100644
index 0000000000..3c0c2b067f
--- /dev/null
+++ b/drivers/crypto/fsl/rng.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 Michael Walle <michael@walle.cc>
+ *
+ * Driver for Freescale Cryptographic Accelerator and Assurance
+ * Module (CAAM) hardware random number generator.
+ */
+
+#include <asm/cache.h>
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <rng.h>
+#include <linux/kernel.h>
+#include "desc_constr.h"
+#include "jobdesc.h"
+#include "jr.h"
+
+#define CAAM_RNG_MAX_FIFO_STORE_SIZE 16
+#define CAAM_RNG_DESC_LEN (3 * CAAM_CMD_SZ + CAAM_PTR_SZ)
+
+struct caam_rng_priv {
+	u32 desc[CAAM_RNG_DESC_LEN / 4];
+	u8 data[CAAM_RNG_MAX_FIFO_STORE_SIZE] __aligned(ARCH_DMA_MINALIGN);
+};
+
+static int caam_rng_read_one(struct caam_rng_priv *priv)
+{
+	int size = ALIGN(CAAM_RNG_MAX_FIFO_STORE_SIZE, ARCH_DMA_MINALIGN);
+	int ret;
+
+	ret = run_descriptor_jr(priv->desc);
+	if (ret < 0)
+		return -EIO;
+
+	invalidate_dcache_range((unsigned long)priv->data,
+				(unsigned long)priv->data + size);
+
+	return 0;
+}
+
+static int caam_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	struct caam_rng_priv *priv = dev_get_priv(dev);
+	u8 *buffer = data;
+	size_t size;
+	int ret;
+
+	while (len) {
+		ret = caam_rng_read_one(priv);
+		if (ret)
+			return ret;
+
+		size = min(len, (size_t)CAAM_RNG_MAX_FIFO_STORE_SIZE);
+
+		memcpy(buffer, priv->data, size);
+		buffer += size;
+		len -= size;
+	}
+
+	return 0;
+}
+
+static int caam_rng_probe(struct udevice *dev)
+{
+	struct caam_rng_priv *priv = dev_get_priv(dev);
+	ulong size = ALIGN(CAAM_RNG_DESC_LEN, ARCH_DMA_MINALIGN);
+
+	inline_cnstr_jobdesc_rng(priv->desc, priv->data,
+				 CAAM_RNG_MAX_FIFO_STORE_SIZE);
+	flush_dcache_range((unsigned long)priv->desc,
+			   (unsigned long)priv->desc + size);
+
+	return 0;
+}
+
+static const struct dm_rng_ops caam_rng_ops = {
+	.read = caam_rng_read,
+};
+
+U_BOOT_DRIVER(caam_rng) = {
+	.name = "caam-rng",
+	.id = UCLASS_RNG,
+	.ops = &caam_rng_ops,
+	.probe = caam_rng_probe,
+	.priv_auto_alloc_size = sizeof(struct caam_rng_priv),
+	.flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c
index a2c0bfaf44..f0a4a63d88 100644
--- a/drivers/crypto/fsl/sec.c
+++ b/drivers/crypto/fsl/sec.c
@@ -98,7 +98,15 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
 		       fdt_strerror(err));
 }
 #elif CONFIG_SYS_FSL_SEC_COMPAT >= 4  /* SEC4 */
-static u8 caam_get_era(void)
+/**
+ * caam_get_era() - fetch the CAAM's era
+ *
+ * The SEC module povides an "Era" which can be used to differentiate
+ * between different revisions.
+ *
+ * Return: era of the SEC.
+ */
+u8 caam_get_era(void)
 {
 	static const struct {
 		u16 ip_id;
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 1a1de67252..e3d980a9df 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -4,6 +4,7 @@
  *
  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright 2020 NXP
  *
  * Based on i2c-imx.c from linux kernel:
  *  Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
@@ -341,6 +342,57 @@ static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
 	return 0;
 }
 
+#if !defined(I2C2_BASE_ADDR)
+#define I2C2_BASE_ADDR	0
+#endif
+
+#if !defined(I2C3_BASE_ADDR)
+#define I2C3_BASE_ADDR	0
+#endif
+
+#if !defined(I2C4_BASE_ADDR)
+#define I2C4_BASE_ADDR	0
+#endif
+
+#if !defined(I2C5_BASE_ADDR)
+#define I2C5_BASE_ADDR 0
+#endif
+
+#if !defined(I2C6_BASE_ADDR)
+#define I2C6_BASE_ADDR 0
+#endif
+
+#if !defined(I2C7_BASE_ADDR)
+#define I2C7_BASE_ADDR 0
+#endif
+
+#if !defined(I2C8_BASE_ADDR)
+#define I2C8_BASE_ADDR 0
+#endif
+
+static struct mxc_i2c_bus mxc_i2c_buses[] = {
+#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
+	defined(CONFIG_FSL_LAYERSCAPE)
+	{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
+	{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
+	{ 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
+	{ 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
+	{ 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
+	{ 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
+	{ 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
+	{ 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
+#else
+	{ 0, I2C1_BASE_ADDR, 0 },
+	{ 1, I2C2_BASE_ADDR, 0 },
+	{ 2, I2C3_BASE_ADDR, 0 },
+	{ 3, I2C4_BASE_ADDR, 0 },
+	{ 4, I2C5_BASE_ADDR, 0 },
+	{ 5, I2C6_BASE_ADDR, 0 },
+	{ 6, I2C7_BASE_ADDR, 0 },
+	{ 7, I2C8_BASE_ADDR, 0 },
+#endif
+};
+
 #ifndef CONFIG_DM_I2C
 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
 {
@@ -434,6 +486,24 @@ exit:
 	return ret;
 }
 #endif
+/*
+ * Early init I2C for prepare read the clk through I2C.
+ */
+void i2c_early_init_f(void)
+{
+	ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+	bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+					& I2C_QUIRK_FLAG ? true : false;
+	int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+	/* Set I2C divider value */
+	writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+	/* Reset module */
+	writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+	writeb(0, base + (I2SR << reg_shift));
+	/* Enable I2C */
+	writeb(I2CR_IEN, base + (I2CR << reg_shift));
+}
 
 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
 			     u32 addr, int alen)
@@ -662,57 +732,6 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
 	return ret;
 }
 
-#if !defined(I2C2_BASE_ADDR)
-#define I2C2_BASE_ADDR	0
-#endif
-
-#if !defined(I2C3_BASE_ADDR)
-#define I2C3_BASE_ADDR	0
-#endif
-
-#if !defined(I2C4_BASE_ADDR)
-#define I2C4_BASE_ADDR	0
-#endif
-
-#if !defined(I2C5_BASE_ADDR)
-#define I2C5_BASE_ADDR 0
-#endif
-
-#if !defined(I2C6_BASE_ADDR)
-#define I2C6_BASE_ADDR 0
-#endif
-
-#if !defined(I2C7_BASE_ADDR)
-#define I2C7_BASE_ADDR 0
-#endif
-
-#if !defined(I2C8_BASE_ADDR)
-#define I2C8_BASE_ADDR 0
-#endif
-
-static struct mxc_i2c_bus mxc_i2c_buses[] = {
-#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
-	defined(CONFIG_FSL_LAYERSCAPE)
-	{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
-	{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
-	{ 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
-	{ 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
-	{ 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
-	{ 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
-	{ 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
-	{ 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
-#else
-	{ 0, I2C1_BASE_ADDR, 0 },
-	{ 1, I2C2_BASE_ADDR, 0 },
-	{ 2, I2C3_BASE_ADDR, 0 },
-	{ 3, I2C4_BASE_ADDR, 0 },
-	{ 4, I2C5_BASE_ADDR, 0 },
-	{ 5, I2C6_BASE_ADDR, 0 },
-	{ 6, I2C7_BASE_ADDR, 0 },
-	{ 7, I2C8_BASE_ADDR, 0 },
-#endif
-};
-
 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
 {
 	return &mxc_i2c_buses[adap->hwadapnr];
@@ -778,24 +797,7 @@ void bus_i2c_init(int index, int speed, int unused,
 	bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
 }
 
-/*
- * Early init I2C for prepare read the clk through I2C.
- */
-void i2c_early_init_f(void)
-{
-	ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
-	bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
-					& I2C_QUIRK_FLAG ? true : false;
-	int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 
-	/* Set I2C divider value */
-	writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
-	/* Reset module */
-	writeb(I2CR_IDIS, base + (I2CR << reg_shift));
-	writeb(0, base + (I2SR << reg_shift));
-	/* Enable I2C */
-	writeb(I2CR_IEN, base + (I2CR << reg_shift));
-}
 
 /*
  * Init I2C Bus
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index f6e0d43057..de9fe01bc5 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -671,45 +671,6 @@ static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 }
 
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
-void mmc_adapter_card_type_ident(void)
-{
-	u8 card_id;
-	u8 value;
-
-	card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
-	gd->arch.sdhc_adapter = card_id;
-
-	switch (card_id) {
-	case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
-		value = QIXIS_READ(brdcfg[5]);
-		value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
-		QIXIS_WRITE(brdcfg[5], value);
-		break;
-	case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
-		value = QIXIS_READ(pwr_ctl[1]);
-		value |= QIXIS_EVDD_BY_SDHC_VS;
-		QIXIS_WRITE(pwr_ctl[1], value);
-		break;
-	case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
-		value = QIXIS_READ(brdcfg[5]);
-		value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
-		QIXIS_WRITE(brdcfg[5], value);
-		break;
-	case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
-		break;
-	case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
-		break;
-	case QIXIS_ESDHC_ADAPTER_TYPE_SD:
-		break;
-	case QIXIS_ESDHC_NO_ADAPTER:
-		break;
-	default:
-		break;
-	}
-}
-#endif
-
 #ifdef CONFIG_OF_LIBFDT
 __weak int esdhc_status_fixup(void *blob, const char *compat)
 {
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index c5b7872900..90690c8d1e 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015 Google, Inc
+ * Copyright 2020 NXP
  * Written by Simon Glass <sjg@chromium.org>
  */
 
@@ -309,9 +310,6 @@ void mmc_do_preinit(void)
 
 		if (!m)
 			continue;
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
-		mmc_set_preinit(m, 1);
-#endif
 		if (m->preinit)
 			mmc_start_init(m);
 	}
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f36d11ddc8..d79cdef62e 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2008, Freescale Semiconductor, Inc
+ * Copyright 2020 NXP
  * Andy Fleming
  *
  * Based vaguely on the Linux code
@@ -2789,9 +2790,6 @@ int mmc_get_op_cond(struct mmc *mmc)
 	if (mmc->has_init)
 		return 0;
 
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
-	mmc_adapter_card_type_ident();
-#endif
 	err = mmc_power_init(mmc);
 	if (err)
 		return err;
@@ -3073,9 +3071,6 @@ int mmc_init_device(int num)
 	m = mmc_get_mmc_dev(dev);
 	if (!m)
 		return 0;
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
-	mmc_set_preinit(m, 1);
-#endif
 	if (m->preinit)
 		mmc_start_init(m);
 
diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c
index 2bb12ceeaf..a05da6c2e8 100644
--- a/drivers/mmc/mmc_legacy.c
+++ b/drivers/mmc/mmc_legacy.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2016 Google, Inc
+ * Copyright 2020 NXP
  * Written by Simon Glass <sjg@chromium.org>
  */
 
@@ -23,9 +24,6 @@ struct mmc *find_mmc_device(int dev_num)
 void mmc_do_preinit(void)
 {
 	struct mmc *m = &mmc_static;
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
-	mmc_set_preinit(m, 1);
-#endif
 	if (m->preinit)
 		mmc_start_init(m);
 }
@@ -77,9 +75,6 @@ void mmc_do_preinit(void)
 	list_for_each(entry, &mmc_devices) {
 		m = list_entry(entry, struct mmc, link);
 
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
-		mmc_set_preinit(m, 1);
-#endif
 		if (m->preinit)
 			mmc_start_init(m);
 	}
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 35170d03ab..a0900e8cad 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2008,2010 Freescale Semiconductor, Inc
+ * Copyright 2020 NXP
  * Andy Fleming
  *
  * Based (loosely) on the Linux code
@@ -16,9 +17,6 @@ int mmc_send_status(struct mmc *mmc, unsigned int *status);
 int mmc_poll_for_busy(struct mmc *mmc, int timeout);
 
 int mmc_set_blocklen(struct mmc *mmc, int len);
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
-void mmc_adapter_card_type_ident(void);
-#endif
 
 #if CONFIG_IS_ENABLED(BLK)
 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
index 718e24f14d..e49bf4a6f3 100644
--- a/drivers/net/pfe_eth/pfe_eth.c
+++ b/drivers/net/pfe_eth/pfe_eth.c
@@ -33,7 +33,7 @@ struct gemac_s gem_info[] = {
 
 		/* phy iface */
 		.phy_address = CONFIG_PFE_EMAC2_PHY_ADDR,
-		.phy_mode = PHY_INTERFACE_MODE_RGMII_TXID,
+		.phy_mode = PHY_INTERFACE_MODE_RGMII_ID,
 	},
 };
 
diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
index 0493cfe872..55e661c0e1 100644
--- a/drivers/net/pfe_eth/pfe_firmware.c
+++ b/drivers/net/pfe_eth/pfe_firmware.c
@@ -16,13 +16,14 @@
 #include <linux/bitops.h>
 #include <net/pfe_eth/pfe_eth.h>
 #include <net/pfe_eth/pfe_firmware.h>
+#include <spi_flash.h>
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include <fsl_validate.h>
 #endif
 
 #define PFE_FIRMWARE_FIT_CNF_NAME	"config@1"
 
-static const void *pfe_fit_addr = (void *)CONFIG_SYS_LS_PFE_FW_ADDR;
+static const void *pfe_fit_addr;
 
 /*
  * PFE elf firmware loader.
@@ -163,6 +164,44 @@ static int pfe_fit_check(void)
 	return ret;
 }
 
+int pfe_spi_flash_init(void)
+{
+	struct spi_flash *pfe_flash;
+	int ret = 0;
+	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+
+#ifdef CONFIG_DM_SPI_FLASH
+	struct udevice *new;
+
+	/* speed and mode will be read from DT */
+	ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
+				     CONFIG_ENV_SPI_CS, 0, 0, &new);
+
+	pfe_flash = dev_get_uclass_priv(new);
+#else
+	pfe_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+				    CONFIG_ENV_SPI_CS,
+				    CONFIG_ENV_SPI_MAX_HZ,
+				    CONFIG_ENV_SPI_MODE);
+#endif
+	if (!pfe_flash) {
+		printf("SF: probe for pfe failed\n");
+		return -ENODEV;
+	}
+
+	ret = spi_flash_read(pfe_flash,
+			     CONFIG_SYS_LS_PFE_FW_ADDR,
+			     CONFIG_SYS_QE_FMAN_FW_LENGTH,
+			     addr);
+	if (ret)
+		printf("SF: read for pfe failed\n");
+
+	pfe_fit_addr = addr;
+	spi_flash_free(pfe_flash);
+
+	return ret;
+}
+
 /*
  * PFE firmware initialization.
  * Loads different firmware files from FIT image.
@@ -187,6 +226,10 @@ int pfe_firmware_init(void)
 	int ret = 0;
 	int fw_count;
 
+	ret = pfe_spi_flash_init();
+	if (ret)
+		goto err;
+
 	ret = pfe_fit_check();
 	if (ret)
 		goto err;
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ff974e5d74..91065e67f1 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -128,12 +128,29 @@ config PCI_XILINX
 	  which can be used on some generations of Xilinx FPGAs.
 
 config PCIE_LAYERSCAPE
-	bool "Layerscape PCIe support"
+	bool
+	default n
+
+config PCIE_LAYERSCAPE_RC
+	bool "Layerscape PCIe Root Complex mode support"
+	depends on DM_PCI
+	select PCIE_LAYERSCAPE
+	help
+	  Enable Layerscape PCIe Root Complex mode driver support. The Layerscape
+	  SoC may have one or several PCIe controllers. Each controller can be
+	  configured to Root Complex mode by clearing the corresponding bit of
+	  RCW[HOST_AGT_PEX].
+
+config PCIE_LAYERSCAPE_EP
+	bool "Layerscape PCIe Endpoint mode support"
 	depends on DM_PCI
+	select PCIE_LAYERSCAPE
+	select PCI_ENDPOINT
 	help
-	  Support Layerscape PCIe. The Layerscape SoC may have one or several
-	  PCIe controllers. The PCIe may works in RC or EP mode according to
-	  RCW[HOST_AGT_PEX] setting.
+	  Enable Layerscape PCIe Endpoint mode driver support. The Layerscape
+	  SoC may have one or several PCIe controllers. Each controller can be
+	  configured to Endpoint mode by setting the corresponding bit of
+	  RCW[HOST_AGT_PEX].
 
 config PCIE_LAYERSCAPE_GEN4
 	bool "Layerscape Gen4 PCIe support"
@@ -145,7 +162,7 @@ config PCIE_LAYERSCAPE_GEN4
 
 config FSL_PCIE_COMPAT
 	string "PCIe compatible of Kernel DT"
-	depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
+	depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
 	default "fsl,ls1012a-pcie" if ARCH_LS1012A
 	default "fsl,ls1028a-pcie" if ARCH_LS1028A
 	default "fsl,ls1043a-pcie" if ARCH_LS1043A
@@ -160,7 +177,7 @@ config FSL_PCIE_COMPAT
 
 config FSL_PCIE_EP_COMPAT
 	string "PCIe EP compatible of Kernel DT"
-	depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
+	depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
 	default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
 	default "fsl,ls-pcie-ep"
 	help
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 6378821aaf..9faebffa48 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -34,7 +34,10 @@ obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
 obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
 obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
-obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o pcie_layerscape_fixup_common.o
+obj-$(CONFIG_PCIE_LAYERSCAPE_RC) += pcie_layerscape_rc.o \
+				pcie_layerscape_fixup.o \
+				pcie_layerscape_fixup_common.o
+obj-$(CONFIG_PCIE_LAYERSCAPE_EP) += pcie_layerscape_ep.o
 obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
 				pcie_layerscape_gen4_fixup.o \
 				pcie_layerscape_fixup_common.o
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 39b6d40802..25b5272d4e 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,18 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  */
 
 #include <common.h>
 #include <log.h>
-#include <asm/arch/fsl_serdes.h>
-#include <pci.h>
 #include <asm/io.h>
 #include <errno.h>
 #include <malloc.h>
-#include <dm.h>
 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
 	defined(CONFIG_ARM)
 #include <asm/arch/clock.h>
@@ -23,18 +20,17 @@ DECLARE_GLOBAL_DATA_PTR;
 
 LIST_HEAD(ls_pcie_list);
 
-static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
+unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
 {
 	return in_le32(pcie->dbi + offset);
 }
 
-static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
-		       unsigned int offset)
+void dbi_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset)
 {
 	out_le32(pcie->dbi + offset, value);
 }
 
-static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
+unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
 {
 	if (pcie->big_endian)
 		return in_be32(pcie->ctrl + offset);
@@ -42,8 +38,8 @@ static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
 		return in_le32(pcie->ctrl + offset);
 }
 
-static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
-			unsigned int offset)
+void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
+		 unsigned int offset)
 {
 	if (pcie->big_endian)
 		out_be32(pcie->ctrl + offset, value);
@@ -51,6 +47,26 @@ static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
 		out_le32(pcie->ctrl + offset, value);
 }
 
+void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie)
+{
+	u32 reg, val;
+
+	reg = PCIE_MISC_CONTROL_1_OFF;
+	val = dbi_readl(pcie, reg);
+	val |= PCIE_DBI_RO_WR_EN;
+	dbi_writel(pcie, val, reg);
+}
+
+void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie)
+{
+	u32 reg, val;
+
+	reg = PCIE_MISC_CONTROL_1_OFF;
+	val = dbi_readl(pcie, reg);
+	val &= ~PCIE_DBI_RO_WR_EN;
+	dbi_writel(pcie, val, reg);
+}
+
 static int ls_pcie_ltssm(struct ls_pcie *pcie)
 {
 	u32 state;
@@ -67,7 +83,7 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie)
 	return state;
 }
 
-static int ls_pcie_link_up(struct ls_pcie *pcie)
+int ls_pcie_link_up(struct ls_pcie *pcie)
 {
 	int ltssm;
 
@@ -78,22 +94,8 @@ static int ls_pcie_link_up(struct ls_pcie *pcie)
 	return 1;
 }
 
-static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
-	dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
-		   PCIE_ATU_VIEWPORT);
-	dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
-	dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
-		   PCIE_ATU_VIEWPORT);
-	dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
-				      u64 phys, u64 bus_addr, pci_size_t size)
+void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
+			      u64 phys, u64 bus_addr, u64 size)
 {
 	dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
 	dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
@@ -106,459 +108,41 @@ static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
 }
 
 /* Use bar match mode and MEM type as default */
-static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
-				     int bar, u64 phys)
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
+			     int type, int idx, int bar, u64 phys)
 {
 	dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
 	dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
 	dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
-	dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
+	dbi_writel(pcie, type | PCIE_ATU_FUNC_NUM(pf), PCIE_ATU_CR1);
 	dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
+		   (vf_flag ? PCIE_ATU_FUNC_NUM_MATCH_EN : 0) |
+		   (vf_flag ? PCIE_ATU_VFBAR_MATCH_MODE_EN : 0) |
 		   PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
 }
 
-static void ls_pcie_dump_atu(struct ls_pcie *pcie)
+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type)
 {
-	int i;
+	int win_idx;
 
-	for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
-		dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
-			   PCIE_ATU_VIEWPORT);
-		debug("iATU%d:\n", i);
+	for (win_idx = 0; win_idx < win_num; win_idx++) {
+		dbi_writel(pcie, type | win_idx, PCIE_ATU_VIEWPORT);
+		debug("iATU%d:\n", win_idx);
 		debug("\tLOWER PHYS 0x%08x\n",
 		      dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
 		debug("\tUPPER PHYS 0x%08x\n",
 		      dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
-		debug("\tLOWER BUS  0x%08x\n",
-		      dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
-		debug("\tUPPER BUS  0x%08x\n",
-		      dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
-		debug("\tLIMIT      0x%08x\n",
-		      readl(pcie->dbi + PCIE_ATU_LIMIT));
+		if (type == PCIE_ATU_REGION_OUTBOUND) {
+			debug("\tLOWER BUS  0x%08x\n",
+			      dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
+			debug("\tUPPER BUS  0x%08x\n",
+			      dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
+			debug("\tLIMIT      0x%08x\n",
+			      dbi_readl(pcie, PCIE_ATU_LIMIT));
+		}
 		debug("\tCR1        0x%08x\n",
 		      dbi_readl(pcie, PCIE_ATU_CR1));
 		debug("\tCR2        0x%08x\n",
 		      dbi_readl(pcie, PCIE_ATU_CR2));
 	}
 }
-
-static void ls_pcie_setup_atu(struct ls_pcie *pcie)
-{
-	struct pci_region *io, *mem, *pref;
-	unsigned long long offset = 0;
-	int idx = 0;
-	uint svr;
-
-	svr = get_svr();
-	if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
-		offset = LS1021_PCIE_SPACE_OFFSET +
-			 LS1021_PCIE_SPACE_SIZE * pcie->idx;
-	}
-
-	/* ATU 0 : OUTBOUND : CFG0 */
-	ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
-				 PCIE_ATU_TYPE_CFG0,
-				 pcie->cfg_res.start + offset,
-				 0,
-				 fdt_resource_size(&pcie->cfg_res) / 2);
-	/* ATU 1 : OUTBOUND : CFG1 */
-	ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
-				 PCIE_ATU_TYPE_CFG1,
-				 pcie->cfg_res.start + offset +
-				 fdt_resource_size(&pcie->cfg_res) / 2,
-				 0,
-				 fdt_resource_size(&pcie->cfg_res) / 2);
-
-	pci_get_regions(pcie->bus, &io, &mem, &pref);
-	idx = PCIE_ATU_REGION_INDEX1 + 1;
-
-	/* Fix the pcie memory map for LS2088A series SoCs */
-	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
-	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
-	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
-		if (io)
-			io->phys_start = (io->phys_start &
-					 (PCIE_PHYS_SIZE - 1)) +
-					 LS2088A_PCIE1_PHYS_ADDR +
-					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
-		if (mem)
-			mem->phys_start = (mem->phys_start &
-					 (PCIE_PHYS_SIZE - 1)) +
-					 LS2088A_PCIE1_PHYS_ADDR +
-					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
-		if (pref)
-			pref->phys_start = (pref->phys_start &
-					 (PCIE_PHYS_SIZE - 1)) +
-					 LS2088A_PCIE1_PHYS_ADDR +
-					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
-	}
-
-	if (io)
-		/* ATU : OUTBOUND : IO */
-		ls_pcie_atu_outbound_set(pcie, idx++,
-					 PCIE_ATU_TYPE_IO,
-					 io->phys_start + offset,
-					 io->bus_start,
-					 io->size);
-
-	if (mem)
-		/* ATU : OUTBOUND : MEM */
-		ls_pcie_atu_outbound_set(pcie, idx++,
-					 PCIE_ATU_TYPE_MEM,
-					 mem->phys_start + offset,
-					 mem->bus_start,
-					 mem->size);
-
-	if (pref)
-		/* ATU : OUTBOUND : pref */
-		ls_pcie_atu_outbound_set(pcie, idx++,
-					 PCIE_ATU_TYPE_MEM,
-					 pref->phys_start + offset,
-					 pref->bus_start,
-					 pref->size);
-
-	ls_pcie_dump_atu(pcie);
-}
-
-/* Return 0 if the address is valid, -errno if not valid */
-static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
-{
-	struct udevice *bus = pcie->bus;
-
-	if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
-		return -ENODEV;
-
-	if (!pcie->enabled)
-		return -ENXIO;
-
-	if (PCI_BUS(bdf) < bus->seq)
-		return -EINVAL;
-
-	if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
-		return -EINVAL;
-
-	if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
-		return -EINVAL;
-
-	return 0;
-}
-
-int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
-			 uint offset, void **paddress)
-{
-	struct ls_pcie *pcie = dev_get_priv(bus);
-	u32 busdev;
-
-	if (ls_pcie_addr_valid(pcie, bdf))
-		return -EINVAL;
-
-	if (PCI_BUS(bdf) == bus->seq) {
-		*paddress = pcie->dbi + offset;
-		return 0;
-	}
-
-	busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) |
-		 PCIE_ATU_DEV(PCI_DEV(bdf)) |
-		 PCIE_ATU_FUNC(PCI_FUNC(bdf));
-
-	if (PCI_BUS(bdf) == bus->seq + 1) {
-		ls_pcie_cfg0_set_busdev(pcie, busdev);
-		*paddress = pcie->cfg0 + offset;
-	} else {
-		ls_pcie_cfg1_set_busdev(pcie, busdev);
-		*paddress = pcie->cfg1 + offset;
-	}
-	return 0;
-}
-
-static int ls_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
-			       uint offset, ulong *valuep,
-			       enum pci_size_t size)
-{
-	return pci_generic_mmap_read_config(bus, ls_pcie_conf_address,
-					    bdf, offset, valuep, size);
-}
-
-static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
-				uint offset, ulong value,
-				enum pci_size_t size)
-{
-	return pci_generic_mmap_write_config(bus, ls_pcie_conf_address,
-					     bdf, offset, value, size);
-}
-
-/* Clear multi-function bit */
-static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
-{
-	writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
-}
-
-/* Fix class value */
-static void ls_pcie_fix_class(struct ls_pcie *pcie)
-{
-	writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
-}
-
-/* Drop MSG TLP except for Vendor MSG */
-static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
-{
-	u32 val;
-
-	val = dbi_readl(pcie, PCIE_STRFMR1);
-	val &= 0xDFFFFFFF;
-	dbi_writel(pcie, val, PCIE_STRFMR1);
-}
-
-/* Disable all bars in RC mode */
-static void ls_pcie_disable_bars(struct ls_pcie *pcie)
-{
-	dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
-	dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
-	dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
-}
-
-static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
-{
-	ls_pcie_setup_atu(pcie);
-
-	dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
-	ls_pcie_fix_class(pcie);
-	ls_pcie_clear_multifunction(pcie);
-	ls_pcie_drop_msg_tlp(pcie);
-	dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
-
-	ls_pcie_disable_bars(pcie);
-	pcie->stream_id_cur = 0;
-}
-
-static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
-{
-	u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
-
-	/* ATU 0 : INBOUND : map BAR0 */
-	ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
-	/* ATU 1 : INBOUND : map BAR1 */
-	phys += PCIE_BAR1_SIZE;
-	ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
-	/* ATU 2 : INBOUND : map BAR2 */
-	phys += PCIE_BAR2_SIZE;
-	ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
-	/* ATU 3 : INBOUND : map BAR4 */
-	phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
-	ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
-
-	/* ATU 0 : OUTBOUND : map MEM */
-	ls_pcie_atu_outbound_set(pcie, 0,
-				 PCIE_ATU_TYPE_MEM,
-				 pcie->cfg_res.start,
-				 0,
-				 CONFIG_SYS_PCI_MEMORY_SIZE);
-}
-
-/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
-static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
-{
-	/* The least inbound window is 4KiB */
-	if (size < 4 * 1024)
-		return;
-
-	switch (bar) {
-	case 0:
-		writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
-		break;
-	case 1:
-		writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
-		break;
-	case 2:
-		writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
-		writel(0, bar_base + PCI_BASE_ADDRESS_3);
-		break;
-	case 4:
-		writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
-		writel(0, bar_base + PCI_BASE_ADDRESS_5);
-		break;
-	default:
-		break;
-	}
-}
-
-static void ls_pcie_ep_setup_bars(void *bar_base)
-{
-	/* BAR0 - 32bit - 4K configuration */
-	ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
-	/* BAR1 - 32bit - 8K MSIX*/
-	ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
-	/* BAR2 - 64bit - 4K MEM desciptor */
-	ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
-	/* BAR4 - 64bit - 1M MEM*/
-	ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
-}
-
-static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
-{
-	u32 config;
-
-	config = ctrl_readl(pcie,  PCIE_PF_CONFIG);
-	config |= PCIE_CONFIG_READY;
-	ctrl_writel(pcie, config, PCIE_PF_CONFIG);
-}
-
-static void ls_pcie_setup_ep(struct ls_pcie *pcie)
-{
-	u32 sriov;
-
-	sriov = readl(pcie->dbi + PCIE_SRIOV);
-	if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
-		int pf, vf;
-
-		for (pf = 0; pf < PCIE_PF_NUM; pf++) {
-			for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
-				ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
-					    PCIE_PF_VF_CTRL);
-
-				ls_pcie_ep_setup_bars(pcie->dbi);
-				ls_pcie_ep_setup_atu(pcie);
-			}
-		}
-		/* Disable CFG2 */
-		ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
-	} else {
-		ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
-		ls_pcie_ep_setup_atu(pcie);
-	}
-
-	ls_pcie_ep_enable_cfg(pcie);
-}
-
-static int ls_pcie_probe(struct udevice *dev)
-{
-	struct ls_pcie *pcie = dev_get_priv(dev);
-	const void *fdt = gd->fdt_blob;
-	int node = dev_of_offset(dev);
-	u16 link_sta;
-	uint svr;
-	int ret;
-	fdt_size_t cfg_size;
-
-	pcie->bus = dev;
-
-	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
-				     "dbi", &pcie->dbi_res);
-	if (ret) {
-		printf("ls-pcie: resource \"dbi\" not found\n");
-		return ret;
-	}
-
-	pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
-
-	list_add(&pcie->list, &ls_pcie_list);
-
-	pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
-	if (!pcie->enabled) {
-		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
-		return 0;
-	}
-
-	pcie->dbi = map_physmem(pcie->dbi_res.start,
-				fdt_resource_size(&pcie->dbi_res),
-				MAP_NOCACHE);
-
-	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
-				     "lut", &pcie->lut_res);
-	if (!ret)
-		pcie->lut = map_physmem(pcie->lut_res.start,
-					fdt_resource_size(&pcie->lut_res),
-					MAP_NOCACHE);
-
-	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
-				     "ctrl", &pcie->ctrl_res);
-	if (!ret)
-		pcie->ctrl = map_physmem(pcie->ctrl_res.start,
-					 fdt_resource_size(&pcie->ctrl_res),
-					 MAP_NOCACHE);
-	if (!pcie->ctrl)
-		pcie->ctrl = pcie->lut;
-
-	if (!pcie->ctrl) {
-		printf("%s: NOT find CTRL\n", dev->name);
-		return -1;
-	}
-
-	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
-				     "config", &pcie->cfg_res);
-	if (ret) {
-		printf("%s: resource \"config\" not found\n", dev->name);
-		return ret;
-	}
-
-	/*
-	 * Fix the pcie memory map address and PF control registers address
-	 * for LS2088A series SoCs
-	 */
-	svr = get_svr();
-	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
-	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
-	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
-		cfg_size = fdt_resource_size(&pcie->cfg_res);
-		pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
-					LS2088A_PCIE_PHYS_SIZE * pcie->idx;
-		pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
-		pcie->ctrl = pcie->lut + 0x40000;
-	}
-
-	pcie->cfg0 = map_physmem(pcie->cfg_res.start,
-				 fdt_resource_size(&pcie->cfg_res),
-				 MAP_NOCACHE);
-	pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
-
-	pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
-
-	debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
-	      dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
-	      (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
-	      pcie->big_endian);
-
-	pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
-
-	if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
-		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
-			ls_pcie_setup_ep(pcie);
-	} else {
-		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
-			ls_pcie_setup_ctrl(pcie);
-	}
-
-	if (!ls_pcie_link_up(pcie)) {
-		/* Let the user know there's no PCIe link */
-		printf(": no link\n");
-		return 0;
-	}
-
-	/* Print the negotiated PCIe link width */
-	link_sta = readw(pcie->dbi + PCIE_LINK_STA);
-	printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
-	       link_sta & PCIE_LINK_SPEED_MASK);
-
-	return 0;
-}
-
-static const struct dm_pci_ops ls_pcie_ops = {
-	.read_config	= ls_pcie_read_config,
-	.write_config	= ls_pcie_write_config,
-};
-
-static const struct udevice_id ls_pcie_ids[] = {
-	{ .compatible = "fsl,ls-pcie" },
-	{ }
-};
-
-U_BOOT_DRIVER(pci_layerscape) = {
-	.name = "pci_layerscape",
-	.id = UCLASS_PCI,
-	.of_match = ls_pcie_ids,
-	.ops = &ls_pcie_ops,
-	.probe	= ls_pcie_probe,
-	.priv_auto_alloc_size = sizeof(struct ls_pcie),
-};
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 95454bc188..593798e3e3 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  */
@@ -9,6 +9,7 @@
 #define _PCIE_LAYERSCAPE_H_
 #include <pci.h>
 #include <dm.h>
+#include <linux/sizes.h>
 
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
 #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
@@ -19,7 +20,7 @@
 #endif
 
 #ifndef CONFIG_SYS_PCI_MEMORY_SIZE
-#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
+#define CONFIG_SYS_PCI_MEMORY_SIZE SZ_4G
 #endif
 
 #ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
@@ -39,14 +40,18 @@
 #define PCIE_ATU_REGION_INDEX2		(0x2 << 0)
 #define PCIE_ATU_REGION_INDEX3		(0x3 << 0)
 #define PCIE_ATU_REGION_NUM		6
+#define PCIE_ATU_REGION_NUM_SRIOV	24
 #define PCIE_ATU_CR1			0x904
 #define PCIE_ATU_TYPE_MEM		(0x0 << 0)
 #define PCIE_ATU_TYPE_IO		(0x2 << 0)
 #define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
 #define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
+#define PCIE_ATU_FUNC_NUM(pf)		((pf) << 20)
 #define PCIE_ATU_CR2			0x908
 #define PCIE_ATU_ENABLE			(0x1 << 31)
 #define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
+#define PCIE_ATU_FUNC_NUM_MATCH_EN	BIT(19)
+#define PCIE_ATU_VFBAR_MATCH_MODE_EN	BIT(26)
 #define PCIE_ATU_BAR_NUM(bar)		((bar) << 8)
 #define PCIE_ATU_LOWER_BASE		0x90C
 #define PCIE_ATU_UPPER_BASE		0x910
@@ -60,7 +65,8 @@
 /* DBI registers */
 #define PCIE_SRIOV		0x178
 #define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
-#define PCIE_DBI_RO_WR_EN	0x8bc
+#define PCIE_DBI_RO_WR_EN		BIT(0)
+#define PCIE_MISC_CONTROL_1_OFF         0x8BC
 
 #define PCIE_LINK_CAP		0x7c
 #define PCIE_LINK_SPEED_MASK	0xf
@@ -82,14 +88,19 @@
 				 PCIE_LCTRL0_CFG2_ENABLE)
 
 #define PCIE_NO_SRIOV_BAR_BASE	0x1000
-
+#define FSL_PCIE_EP_MIN_APERTURE        4096     /* 4 Kbytes */
 #define PCIE_PF_NUM		2
 #define PCIE_VF_NUM		64
+#define BAR_NUM			8
+
+#define PCIE_BAR0_SIZE		SZ_4K
+#define PCIE_BAR1_SIZE		SZ_8K
+#define PCIE_BAR2_SIZE		SZ_4K
+#define PCIE_BAR4_SIZE		SZ_1M
+
+#define PCIE_SRIOV_VFBAR0	0x19C
 
-#define PCIE_BAR0_SIZE		(4 * 1024) /* 4K */
-#define PCIE_BAR1_SIZE		(8 * 1024) /* 8K for MSIX */
-#define PCIE_BAR2_SIZE		(4 * 1024) /* 4K */
-#define PCIE_BAR4_SIZE		(1 * 1024 * 1024) /* 1M */
+#define PCIE_MASK_OFFSET(flag, pf, off) ((flag) ? 0 : (0x1000 + (off) * (pf)))
 
 /* LUT registers */
 #define PCIE_LUT_UDR(n)		(0x800 + (n) * 8)
@@ -128,26 +139,62 @@
 #define LS1021_PEXMSCPORTSR(pex_idx)	(0x94 + (pex_idx) * 4)
 #define LS1021_LTSSM_STATE_SHIFT	20
 
+/* LX2160a PF1 offset */
+#define LX2160_PCIE_PF1_OFFSET	0x8000
+
+/* layerscape PF1 offset */
+#define LS_PCIE_PF1_OFFSET	0x20000
+
 struct ls_pcie {
+	void __iomem *dbi;
+	void __iomem *lut;
+	void __iomem *ctrl;
 	int idx;
+	bool big_endian;
+	int mode;
+};
+
+struct ls_pcie_rc {
+	struct ls_pcie *pcie;
 	struct list_head list;
 	struct udevice *bus;
 	struct fdt_resource dbi_res;
 	struct fdt_resource lut_res;
 	struct fdt_resource ctrl_res;
 	struct fdt_resource cfg_res;
-	void __iomem *dbi;
-	void __iomem *lut;
-	void __iomem *ctrl;
 	void __iomem *cfg0;
 	void __iomem *cfg1;
-	bool big_endian;
 	bool enabled;
 	int next_lut_index;
 	int stream_id_cur;
-	int mode;
+};
+
+struct ls_pcie_ep {
+	struct fdt_resource addr_res;
+	struct ls_pcie *pcie;
+	struct udevice *bus;
+	void __iomem *addr;
+	u32 cfg2_flag;
+	u32 sriov_flag;
+	u32 pf1_offset;
+	u32 num_ib_wins;
+	u32 num_ob_wins;
+	u8 max_functions;
 };
 
 extern struct list_head ls_pcie_list;
 
+unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset);
+void dbi_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset);
+unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset);
+void ctrl_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset);
+void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
+			      u64 phys, u64 bus_addr, u64 size);
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
+			     int type, int idx, int bar, u64 phys);
+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type);
+int ls_pcie_link_up(struct ls_pcie *pcie);
+void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
+void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie);
+
 #endif /* _PCIE_LAYERSCAPE_H_ */
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
new file mode 100644
index 0000000000..eba230e3a5
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -0,0 +1,332 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ * Layerscape PCIe EP driver
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/devres.h>
+#include <errno.h>
+#include <pci_ep.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <linux/log2.h>
+#include "pcie_layerscape.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ls_pcie_ep_enable_cfg(struct ls_pcie_ep *pcie_ep)
+{
+	struct ls_pcie *pcie = pcie_ep->pcie;
+	u32 config;
+
+	config = ctrl_readl(pcie,  PCIE_PF_CONFIG);
+	config |= PCIE_CONFIG_READY;
+	ctrl_writel(pcie, config, PCIE_PF_CONFIG);
+}
+
+static int ls_ep_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
+{
+	struct ls_pcie_ep *pcie_ep = dev_get_priv(dev);
+	struct ls_pcie *pcie = pcie_ep->pcie;
+	dma_addr_t bar_phys = ep_bar->phys_addr;
+	enum pci_barno bar = ep_bar->barno;
+	u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+	int flags = ep_bar->flags;
+	int type, idx;
+	u64 size;
+
+	idx  = bar;
+	/* BAR size is 2^(aperture + 11) */
+	size = max_t(size_t, ep_bar->size, FSL_PCIE_EP_MIN_APERTURE);
+
+	if (!(flags & PCI_BASE_ADDRESS_SPACE))
+		type = PCIE_ATU_TYPE_MEM;
+	else
+		type = PCIE_ATU_TYPE_IO;
+
+	ls_pcie_atu_inbound_set(pcie, fn, 0, type, idx, bar, bar_phys);
+
+	dbi_writel(pcie, lower_32_bits(size - 1), reg + PCIE_NO_SRIOV_BAR_BASE);
+	dbi_writel(pcie, flags, reg);
+
+	if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
+		dbi_writel(pcie, upper_32_bits(size - 1),
+			   reg + 4 + PCIE_NO_SRIOV_BAR_BASE);
+		dbi_writel(pcie, 0, reg + 4);
+	}
+
+	return 0;
+}
+
+static struct pci_ep_ops ls_pcie_ep_ops = {
+	.set_bar = ls_ep_set_bar,
+};
+
+static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf)
+{
+	struct ls_pcie *pcie = pcie_ep->pcie;
+	u32 vf_flag = 0;
+	u64 phys = 0;
+
+	phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
+
+	phys = ALIGN(phys, PCIE_BAR0_SIZE);
+	/* ATU 0 : INBOUND : map BAR0 */
+	ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+				0 + pf * BAR_NUM, 0, phys);
+	/* ATU 1 : INBOUND : map BAR1 */
+	phys = ALIGN(phys + PCIE_BAR0_SIZE, PCIE_BAR1_SIZE);
+	ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+				1 + pf * BAR_NUM, 1, phys);
+	/* ATU 2 : INBOUND : map BAR2 */
+	phys = ALIGN(phys + PCIE_BAR1_SIZE, PCIE_BAR2_SIZE);
+	ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+				2 + pf * BAR_NUM, 2, phys);
+	/* ATU 3 : INBOUND : map BAR2 */
+	phys = ALIGN(phys + PCIE_BAR2_SIZE, PCIE_BAR4_SIZE);
+	ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+				3 + pf * BAR_NUM, 4, phys);
+
+	if (pcie_ep->sriov_flag) {
+		vf_flag = 1;
+		/* ATU 4 : INBOUND : map BAR0 */
+		phys = ALIGN(phys + PCIE_BAR4_SIZE, PCIE_BAR0_SIZE);
+		ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+					4 + pf * BAR_NUM, 0, phys);
+		/* ATU 5 : INBOUND : map BAR1 */
+		phys = ALIGN(phys + PCIE_BAR0_SIZE * PCIE_VF_NUM,
+			     PCIE_BAR1_SIZE);
+		ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+					5 + pf * BAR_NUM, 1, phys);
+		/* ATU 6 : INBOUND : map BAR2 */
+		phys = ALIGN(phys + PCIE_BAR1_SIZE * PCIE_VF_NUM,
+			     PCIE_BAR2_SIZE);
+		ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+					6 + pf * BAR_NUM, 2, phys);
+		/* ATU 7 : INBOUND : map BAR4 */
+		phys = ALIGN(phys + PCIE_BAR2_SIZE * PCIE_VF_NUM,
+			     PCIE_BAR4_SIZE);
+		ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+					7 + pf * BAR_NUM, 4, phys);
+	}
+
+	/* ATU: OUTBOUND : map MEM */
+	ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
+				 (u64)pcie_ep->addr_res.start +
+				 pf * CONFIG_SYS_PCI_MEMORY_SIZE,
+				 0, CONFIG_SYS_PCI_MEMORY_SIZE);
+}
+
+/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
+static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
+{
+	u32 mask;
+
+	/* The least inbound window is 4KiB */
+	if (size < SZ_4K)
+		mask = 0;
+	else
+		mask = size - 1;
+
+	switch (bar) {
+	case 0:
+		writel(mask, bar_base + PCI_BASE_ADDRESS_0);
+		break;
+	case 1:
+		writel(mask, bar_base + PCI_BASE_ADDRESS_1);
+		break;
+	case 2:
+		writel(mask, bar_base + PCI_BASE_ADDRESS_2);
+		writel(0, bar_base + PCI_BASE_ADDRESS_3);
+		break;
+	case 4:
+		writel(mask, bar_base + PCI_BASE_ADDRESS_4);
+		writel(0, bar_base + PCI_BASE_ADDRESS_5);
+		break;
+	default:
+		break;
+	}
+}
+
+static void ls_pcie_ep_setup_bars(void *bar_base)
+{
+	/* BAR0 - 32bit - MEM */
+	ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
+	/* BAR1 - 32bit - MEM*/
+	ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
+	/* BAR2 - 64bit - MEM */
+	ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
+	/* BAR4 - 64bit - MEM */
+	ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
+}
+
+static void ls_pcie_ep_setup_vf_bars(void *bar_base)
+{
+	/* VF BAR0 MASK register at offset 0x19c*/
+	bar_base += PCIE_SRIOV_VFBAR0 - PCI_BASE_ADDRESS_0;
+
+	/* VF-BAR0 - 32bit - MEM */
+	ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
+	/* VF-BAR1 - 32bit - MEM*/
+	ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
+	/* VF-BAR2 - 64bit - MEM */
+	ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
+	/* VF-BAR4 - 64bit - MEM */
+	ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
+}
+
+static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
+{
+	u32 sriov;
+	u32 pf, vf;
+	void *bar_base = NULL;
+	struct ls_pcie *pcie = pcie_ep->pcie;
+
+	sriov = readl(pcie->dbi + PCIE_SRIOV);
+	if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
+		pcie_ep->sriov_flag = 1;
+		for (pf = 0; pf < PCIE_PF_NUM; pf++) {
+			/*
+			 * The VF_BARn_REG register's Prefetchable and Type bit
+			 * fields are overwritten by a write to VF's BAR Mask
+			 * register. Before writing to the VF_BARn_MASK_REG
+			 * register, write 0b to the PCIE_MISC_CONTROL_1_OFF
+			 * register.
+			 */
+			writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
+
+			bar_base = pcie->dbi +
+				   PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf,
+						    pcie_ep->pf1_offset);
+
+			if (pcie_ep->cfg2_flag) {
+				ctrl_writel(pcie,
+					    PCIE_LCTRL0_VAL(pf, 0),
+					    PCIE_PF_VF_CTRL);
+				ls_pcie_ep_setup_bars(bar_base);
+
+				for (vf = 1; vf <= PCIE_VF_NUM; vf++) {
+					ctrl_writel(pcie,
+						    PCIE_LCTRL0_VAL(pf, vf),
+						    PCIE_PF_VF_CTRL);
+					ls_pcie_ep_setup_vf_bars(bar_base);
+				}
+			} else {
+				ls_pcie_ep_setup_bars(bar_base);
+				ls_pcie_ep_setup_vf_bars(bar_base);
+			}
+
+			ls_pcie_ep_setup_atu(pcie_ep, pf);
+		}
+
+		if (pcie_ep->cfg2_flag)  /* Disable CFG2 */
+			ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
+	} else {
+		ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
+		ls_pcie_ep_setup_atu(pcie_ep, 0);
+	}
+
+	ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM_SRIOV,
+			 PCIE_ATU_REGION_INBOUND);
+
+	ls_pcie_ep_enable_cfg(pcie_ep);
+}
+
+static int ls_pcie_ep_probe(struct udevice *dev)
+{
+	struct ls_pcie_ep *pcie_ep = dev_get_priv(dev);
+	struct ls_pcie *pcie;
+	u16 link_sta;
+	int ret;
+	u32 svr;
+
+	pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
+	if (!pcie)
+		return -ENOMEM;
+
+	pcie_ep->pcie = pcie;
+
+	pcie->dbi = (void __iomem *)devfdt_get_addr_index(dev, 0);
+	if (!pcie->dbi)
+		return -ENOMEM;
+
+	pcie->ctrl = (void __iomem *)devfdt_get_addr_index(dev, 1);
+	if (!pcie->ctrl)
+		return -ENOMEM;
+
+	ret = fdt_get_named_resource(gd->fdt_blob, dev_of_offset(dev),
+				     "reg", "reg-names",
+				     "addr_space", &pcie_ep->addr_res);
+	if (ret) {
+		printf("%s: resource \"addr_space\" not found\n", dev->name);
+		return ret;
+	}
+
+	pcie->idx = ((unsigned long)pcie->dbi - PCIE_SYS_BASE_ADDR) /
+		    PCIE_CCSR_SIZE;
+
+	pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
+					   "big-endian");
+
+	svr = SVR_SOC_VER(get_svr());
+
+	if (svr == SVR_LX2160A)
+		pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET;
+	else
+		pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET;
+
+	if (svr == SVR_LS2080A || svr == SVR_LS2085A)
+		pcie_ep->cfg2_flag = 1;
+	else
+		pcie_ep->cfg2_flag = 0;
+
+	pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
+	if (pcie->mode != PCI_HEADER_TYPE_NORMAL)
+		return 0;
+
+	pcie_ep->max_functions = fdtdec_get_int(gd->fdt_blob,
+						dev_of_offset(dev),
+						"max-functions", 1);
+	pcie_ep->num_ib_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+					      "num-ib-windows", 8);
+	pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+					      "num-ob-windows", 8);
+
+	printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+	ls_pcie_setup_ep(pcie_ep);
+
+	if (!ls_pcie_link_up(pcie)) {
+		/* Let the user know there's no PCIe link */
+		printf(": no link\n");
+		return 0;
+	}
+
+	/* Print the negotiated PCIe link width */
+	link_sta = readw(pcie->dbi + PCIE_LINK_STA);
+	printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
+	       link_sta & PCIE_LINK_SPEED_MASK);
+
+	return 0;
+}
+
+static int ls_pcie_ep_remove(struct udevice *dev)
+{
+	return 0;
+}
+
+const struct udevice_id ls_pcie_ep_ids[] = {
+	{ .compatible = "fsl,ls-pcie-ep" },
+	{ }
+};
+
+U_BOOT_DRIVER(pci_layerscape_ep) = {
+	.name = "pci_layerscape_ep",
+	.id	= UCLASS_PCI_EP,
+	.of_match = ls_pcie_ep_ids,
+	.ops = &ls_pcie_ep_ops,
+	.probe = ls_pcie_ep_probe,
+	.remove = ls_pcie_ep_remove,
+	.priv_auto_alloc_size = sizeof(struct ls_pcie_ep),
+};
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 76e680481a..94de4edaf4 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -25,17 +25,19 @@
 /*
  * Return next available LUT index.
  */
-static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
+static int ls_pcie_next_lut_index(struct ls_pcie_rc *pcie_rc)
 {
-	if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
-		return pcie->next_lut_index++;
+	if (pcie_rc->next_lut_index < PCIE_LUT_ENTRY_COUNT)
+		return pcie_rc->next_lut_index++;
 	else
 		return -ENOSPC;  /* LUT is full */
 }
 
-static void lut_writel(struct ls_pcie *pcie, unsigned int value,
+static void lut_writel(struct ls_pcie_rc *pcie_rc, unsigned int value,
 		       unsigned int offset)
 {
+	struct ls_pcie *pcie = pcie_rc->pcie;
+
 	if (pcie->big_endian)
 		out_be32(pcie->lut + offset, value);
 	else
@@ -45,12 +47,12 @@ static void lut_writel(struct ls_pcie *pcie, unsigned int value,
 /*
  * Program a single LUT entry
  */
-static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
-				    u32 streamid)
+static void ls_pcie_lut_set_mapping(struct ls_pcie_rc *pcie_rc, int index,
+				    u32 devid, u32 streamid)
 {
 	/* leave mask as all zeroes, want to match all bits */
-	lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
-	lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
+	lut_writel(pcie_rc, devid << 16, PCIE_LUT_UDR(index));
+	lut_writel(pcie_rc, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
 }
 
 /*
@@ -61,7 +63,8 @@ static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
  *      msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
  *                 [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
  */
-static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
+static void fdt_pcie_set_msi_map_entry_ls(void *blob,
+					  struct ls_pcie_rc *pcie_rc,
 					  u32 devid, u32 streamid)
 {
 	u32 *prop;
@@ -69,10 +72,11 @@ static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
 	int nodeoffset;
 	uint svr;
 	char *compat = NULL;
+	struct ls_pcie *pcie = pcie_rc->pcie;
 
 	/* find pci controller node */
 	nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
-						   pcie->dbi_res.start);
+						   pcie_rc->dbi_res.start);
 	if (nodeoffset < 0) {
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
@@ -84,7 +88,7 @@ static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
 			compat = CONFIG_FSL_PCIE_COMPAT;
 		if (compat)
 			nodeoffset = fdt_node_offset_by_compat_reg(blob,
-					compat, pcie->dbi_res.start);
+					compat, pcie_rc->dbi_res.start);
 #endif
 		if (nodeoffset < 0)
 			return;
@@ -114,7 +118,8 @@ static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
  *      iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
  *                 [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
  */
-static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
+static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
+					    struct ls_pcie_rc *pcie_rc,
 					    u32 devid, u32 streamid)
 {
 	u32 *prop;
@@ -123,10 +128,11 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
 	int lenp;
 	uint svr;
 	char *compat = NULL;
+	struct ls_pcie *pcie = pcie_rc->pcie;
 
 	/* find pci controller node */
 	nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
-						   pcie->dbi_res.start);
+						   pcie_rc->dbi_res.start);
 	if (nodeoffset < 0) {
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
@@ -139,7 +145,7 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
 
 		if (compat)
 			nodeoffset = fdt_node_offset_by_compat_reg(blob,
-						compat, pcie->dbi_res.start);
+						compat, pcie_rc->dbi_res.start);
 #endif
 		if (nodeoffset < 0)
 			return;
@@ -170,7 +176,7 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
 static void fdt_fixup_pcie_ls(void *blob)
 {
 	struct udevice *dev, *bus;
-	struct ls_pcie *pcie;
+	struct ls_pcie_rc *pcie_rc;
 	int streamid;
 	int index;
 	pci_dev_t bdf;
@@ -181,17 +187,18 @@ static void fdt_fixup_pcie_ls(void *blob)
 	     pci_find_next_device(&dev)) {
 		for (bus = dev; device_is_on_pci_bus(bus);)
 			bus = bus->parent;
-		pcie = dev_get_priv(bus);
+		pcie_rc = dev_get_priv(bus);
 
-		streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
+		streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
+					      pcie_rc->pcie->idx);
 		if (streamid < 0) {
 			debug("ERROR: no stream ids free\n");
 			continue;
 		} else {
-			pcie->stream_id_cur++;
+			pcie_rc->stream_id_cur++;
 		}
 
-		index = ls_pcie_next_lut_index(pcie);
+		index = ls_pcie_next_lut_index(pcie_rc);
 		if (index < 0) {
 			debug("ERROR: no LUT indexes free\n");
 			continue;
@@ -200,27 +207,28 @@ static void fdt_fixup_pcie_ls(void *blob)
 		/* the DT fixup must be relative to the hose first_busno */
 		bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
 		/* map PCI b.d.f to streamID in LUT */
-		ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
+		ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8,
 					streamid);
 		/* update msi-map in device tree */
-		fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
+		fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8,
 					      streamid);
 		/* update iommu-map in device tree */
-		fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
+		fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8,
 						streamid);
 	}
 	pcie_board_fix_fdt(blob);
 }
 #endif
 
-static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
 {
 	int off;
 	uint svr;
 	char *compat = NULL;
+	struct ls_pcie *pcie = pcie_rc->pcie;
 
 	off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
-					    pcie->dbi_res.start);
+					    pcie_rc->dbi_res.start);
 	if (off < 0) {
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
@@ -232,46 +240,47 @@ static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
 			compat = CONFIG_FSL_PCIE_COMPAT;
 		if (compat)
 			off = fdt_node_offset_by_compat_reg(blob,
-					compat, pcie->dbi_res.start);
+					compat, pcie_rc->dbi_res.start);
 #endif
 		if (off < 0)
 			return;
 	}
 
-	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
+	if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
 		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
 	else
 		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 }
 
-static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_ep_fix(void *blob, struct ls_pcie_rc *pcie_rc)
 {
 	int off;
+	struct ls_pcie *pcie = pcie_rc->pcie;
 
 	off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
-					    pcie->dbi_res.start);
+					    pcie_rc->dbi_res.start);
 	if (off < 0)
 		return;
 
-	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
+	if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
 		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
 	else
 		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 }
 
-static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc *pcie_rc)
 {
-	ft_pcie_ep_fix(blob, pcie);
-	ft_pcie_rc_fix(blob, pcie);
+	ft_pcie_ep_fix(blob, pcie_rc);
+	ft_pcie_rc_fix(blob, pcie_rc);
 }
 
 /* Fixup Kernel DT for PCIe */
 void ft_pci_setup_ls(void *blob, struct bd_info *bd)
 {
-	struct ls_pcie *pcie;
+	struct ls_pcie_rc *pcie_rc;
 
-	list_for_each_entry(pcie, &ls_pcie_list, list)
-		ft_pcie_ls_setup(blob, pcie);
+	list_for_each_entry(pcie_rc, &ls_pcie_list, list)
+		ft_pcie_ls_setup(blob, pcie_rc);
 
 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
 	fdt_fixup_pcie_ls(blob);
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
new file mode 100644
index 0000000000..25c6ddebce
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ * Layerscape PCIe driver
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <malloc.h>
+#include <dm.h>
+#include <dm/devres.h>
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
+	defined(CONFIG_ARM)
+#include <asm/arch/clock.h>
+#endif
+#include "pcie_layerscape.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
+{
+	struct ls_pcie *pcie = pcie_rc->pcie;
+
+	dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
+		   PCIE_ATU_VIEWPORT);
+	dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
+}
+
+static void ls_pcie_cfg1_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
+{
+	struct ls_pcie *pcie = pcie_rc->pcie;
+
+	dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
+		   PCIE_ATU_VIEWPORT);
+	dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
+}
+
+static void ls_pcie_setup_atu(struct ls_pcie_rc *pcie_rc)
+{
+	struct pci_region *io, *mem, *pref;
+	unsigned long long offset = 0;
+	struct ls_pcie *pcie = pcie_rc->pcie;
+	int idx = 0;
+	uint svr;
+
+	svr = get_svr();
+	if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
+		offset = LS1021_PCIE_SPACE_OFFSET +
+			 LS1021_PCIE_SPACE_SIZE * pcie->idx;
+	}
+
+	/* ATU 0 : OUTBOUND : CFG0 */
+	ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
+				 PCIE_ATU_TYPE_CFG0,
+				 pcie_rc->cfg_res.start + offset,
+				 0,
+				 fdt_resource_size(&pcie_rc->cfg_res) / 2);
+	/* ATU 1 : OUTBOUND : CFG1 */
+	ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
+				 PCIE_ATU_TYPE_CFG1,
+				 pcie_rc->cfg_res.start + offset +
+				 fdt_resource_size(&pcie_rc->cfg_res) / 2,
+				 0,
+				 fdt_resource_size(&pcie_rc->cfg_res) / 2);
+
+	pci_get_regions(pcie_rc->bus, &io, &mem, &pref);
+	idx = PCIE_ATU_REGION_INDEX1 + 1;
+
+	/* Fix the pcie memory map for LS2088A series SoCs */
+	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
+		if (io)
+			io->phys_start = (io->phys_start &
+					 (PCIE_PHYS_SIZE - 1)) +
+					 LS2088A_PCIE1_PHYS_ADDR +
+					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+		if (mem)
+			mem->phys_start = (mem->phys_start &
+					 (PCIE_PHYS_SIZE - 1)) +
+					 LS2088A_PCIE1_PHYS_ADDR +
+					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+		if (pref)
+			pref->phys_start = (pref->phys_start &
+					 (PCIE_PHYS_SIZE - 1)) +
+					 LS2088A_PCIE1_PHYS_ADDR +
+					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+	}
+
+	if (io)
+		/* ATU : OUTBOUND : IO */
+		ls_pcie_atu_outbound_set(pcie, idx++,
+					 PCIE_ATU_TYPE_IO,
+					 io->phys_start + offset,
+					 io->bus_start,
+					 io->size);
+
+	if (mem)
+		/* ATU : OUTBOUND : MEM */
+		ls_pcie_atu_outbound_set(pcie, idx++,
+					 PCIE_ATU_TYPE_MEM,
+					 mem->phys_start + offset,
+					 mem->bus_start,
+					 mem->size);
+
+	if (pref)
+		/* ATU : OUTBOUND : pref */
+		ls_pcie_atu_outbound_set(pcie, idx++,
+					 PCIE_ATU_TYPE_MEM,
+					 pref->phys_start + offset,
+					 pref->bus_start,
+					 pref->size);
+
+	ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM, PCIE_ATU_REGION_OUTBOUND);
+}
+
+/* Return 0 if the address is valid, -errno if not valid */
+static int ls_pcie_addr_valid(struct ls_pcie_rc *pcie_rc, pci_dev_t bdf)
+{
+	struct udevice *bus = pcie_rc->bus;
+	struct ls_pcie *pcie = pcie_rc->pcie;
+
+	if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
+		return -ENODEV;
+
+	if (!pcie_rc->enabled)
+		return -ENXIO;
+
+	if (PCI_BUS(bdf) < bus->seq)
+		return -EINVAL;
+
+	if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
+		return -EINVAL;
+
+	if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
+		return -EINVAL;
+
+	return 0;
+}
+
+int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
+			 uint offset, void **paddress)
+{
+	struct ls_pcie_rc *pcie_rc = dev_get_priv(bus);
+	struct ls_pcie *pcie = pcie_rc->pcie;
+	u32 busdev;
+
+	if (ls_pcie_addr_valid(pcie_rc, bdf))
+		return -EINVAL;
+
+	if (PCI_BUS(bdf) == bus->seq) {
+		*paddress = pcie->dbi + offset;
+		return 0;
+	}
+
+	busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) |
+		 PCIE_ATU_DEV(PCI_DEV(bdf)) |
+		 PCIE_ATU_FUNC(PCI_FUNC(bdf));
+
+	if (PCI_BUS(bdf) == bus->seq + 1) {
+		ls_pcie_cfg0_set_busdev(pcie_rc, busdev);
+		*paddress = pcie_rc->cfg0 + offset;
+	} else {
+		ls_pcie_cfg1_set_busdev(pcie_rc, busdev);
+		*paddress = pcie_rc->cfg1 + offset;
+	}
+	return 0;
+}
+
+static int ls_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
+			       uint offset, ulong *valuep,
+			       enum pci_size_t size)
+{
+	return pci_generic_mmap_read_config(bus, ls_pcie_conf_address,
+					    bdf, offset, valuep, size);
+}
+
+static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
+				uint offset, ulong value,
+				enum pci_size_t size)
+{
+	return pci_generic_mmap_write_config(bus, ls_pcie_conf_address,
+					     bdf, offset, value, size);
+}
+
+/* Clear multi-function bit */
+static void ls_pcie_clear_multifunction(struct ls_pcie_rc *pcie_rc)
+{
+	struct ls_pcie *pcie = pcie_rc->pcie;
+
+	writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
+}
+
+/* Fix class value */
+static void ls_pcie_fix_class(struct ls_pcie_rc *pcie_rc)
+{
+	struct ls_pcie *pcie = pcie_rc->pcie;
+
+	writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
+}
+
+/* Drop MSG TLP except for Vendor MSG */
+static void ls_pcie_drop_msg_tlp(struct ls_pcie_rc *pcie_rc)
+{
+	struct ls_pcie *pcie = pcie_rc->pcie;
+	u32 val;
+
+	val = dbi_readl(pcie, PCIE_STRFMR1);
+	val &= 0xDFFFFFFF;
+	dbi_writel(pcie, val, PCIE_STRFMR1);
+}
+
+/* Disable all bars in RC mode */
+static void ls_pcie_disable_bars(struct ls_pcie_rc *pcie_rc)
+{
+	struct ls_pcie *pcie = pcie_rc->pcie;
+
+	dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
+	dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
+	dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
+}
+
+static void ls_pcie_setup_ctrl(struct ls_pcie_rc *pcie_rc)
+{
+	struct ls_pcie *pcie = pcie_rc->pcie;
+
+	ls_pcie_setup_atu(pcie_rc);
+
+	ls_pcie_dbi_ro_wr_en(pcie);
+	ls_pcie_fix_class(pcie_rc);
+	ls_pcie_clear_multifunction(pcie_rc);
+	ls_pcie_drop_msg_tlp(pcie_rc);
+	ls_pcie_dbi_ro_wr_dis(pcie);
+
+	ls_pcie_disable_bars(pcie_rc);
+	pcie_rc->stream_id_cur = 0;
+}
+
+static int ls_pcie_probe(struct udevice *dev)
+{
+	struct ls_pcie_rc *pcie_rc = dev_get_priv(dev);
+	const void *fdt = gd->fdt_blob;
+	int node = dev_of_offset(dev);
+	struct ls_pcie *pcie;
+	u16 link_sta;
+	uint svr;
+	int ret;
+	fdt_size_t cfg_size;
+
+	pcie_rc->bus = dev;
+
+	pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
+	if (!pcie)
+		return -ENOMEM;
+
+	pcie_rc->pcie = pcie;
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "dbi", &pcie_rc->dbi_res);
+	if (ret) {
+		printf("ls-pcie: resource \"dbi\" not found\n");
+		return ret;
+	}
+
+	pcie->idx = (pcie_rc->dbi_res.start - PCIE_SYS_BASE_ADDR) /
+		    PCIE_CCSR_SIZE;
+
+	list_add(&pcie_rc->list, &ls_pcie_list);
+
+	pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
+	if (!pcie_rc->enabled) {
+		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+		return 0;
+	}
+
+	pcie->dbi = map_physmem(pcie_rc->dbi_res.start,
+				fdt_resource_size(&pcie_rc->dbi_res),
+				MAP_NOCACHE);
+
+	pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
+	if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
+		return 0;
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "lut", &pcie_rc->lut_res);
+	if (!ret)
+		pcie->lut = map_physmem(pcie_rc->lut_res.start,
+					fdt_resource_size(&pcie_rc->lut_res),
+					MAP_NOCACHE);
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "ctrl", &pcie_rc->ctrl_res);
+	if (!ret)
+		pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
+					 fdt_resource_size(&pcie_rc->ctrl_res),
+					 MAP_NOCACHE);
+	if (!pcie->ctrl)
+		pcie->ctrl = pcie->lut;
+
+	if (!pcie->ctrl) {
+		printf("%s: NOT find CTRL\n", dev->name);
+		return -1;
+	}
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "config", &pcie_rc->cfg_res);
+	if (ret) {
+		printf("%s: resource \"config\" not found\n", dev->name);
+		return ret;
+	}
+
+	/*
+	 * Fix the pcie memory map address and PF control registers address
+	 * for LS2088A series SoCs
+	 */
+	svr = get_svr();
+	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
+		cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
+		pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
+					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+		pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
+		pcie->ctrl = pcie->lut + 0x40000;
+	}
+
+	pcie_rc->cfg0 = map_physmem(pcie_rc->cfg_res.start,
+				    fdt_resource_size(&pcie_rc->cfg_res),
+				    MAP_NOCACHE);
+	pcie_rc->cfg1 = pcie_rc->cfg0 +
+			fdt_resource_size(&pcie_rc->cfg_res) / 2;
+
+	pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
+
+	debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
+	      dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
+	      (unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
+	      pcie->big_endian);
+
+	printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+	ls_pcie_setup_ctrl(pcie_rc);
+
+	if (!ls_pcie_link_up(pcie)) {
+		/* Let the user know there's no PCIe link */
+		printf(": no link\n");
+		return 0;
+	}
+
+	/* Print the negotiated PCIe link width */
+	link_sta = readw(pcie->dbi + PCIE_LINK_STA);
+	printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
+	       link_sta & PCIE_LINK_SPEED_MASK);
+
+	return 0;
+}
+
+static const struct dm_pci_ops ls_pcie_ops = {
+	.read_config	= ls_pcie_read_config,
+	.write_config	= ls_pcie_write_config,
+};
+
+static const struct udevice_id ls_pcie_ids[] = {
+	{ .compatible = "fsl,ls-pcie" },
+	{ }
+};
+
+U_BOOT_DRIVER(pci_layerscape) = {
+	.name = "pci_layerscape",
+	.id = UCLASS_PCI,
+	.of_match = ls_pcie_ids,
+	.ops = &ls_pcie_ops,
+	.probe	= ls_pcie_probe,
+	.priv_auto_alloc_size = sizeof(struct ls_pcie_rc),
+};
diff --git a/drivers/pci_endpoint/pci_ep-uclass.c b/drivers/pci_endpoint/pci_ep-uclass.c
index 9f53a9a9b9..38a5f08376 100644
--- a/drivers/pci_endpoint/pci_ep-uclass.c
+++ b/drivers/pci_endpoint/pci_ep-uclass.c
@@ -209,3 +209,14 @@ UCLASS_DRIVER(pci_ep) = {
 	.name		= "pci_ep",
 	.flags		= DM_UC_FLAG_SEQ_ALIAS,
 };
+
+void pci_ep_init(void)
+{
+	struct udevice *dev;
+
+	for (uclass_first_device_check(UCLASS_PCI_EP, &dev);
+	     dev;
+	     uclass_next_device_check(&dev)) {
+		;
+	}
+}
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 9396c3826f..b22c9b3a09 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -9,6 +9,7 @@
  * Haikun Wang (B53464@freescale.com)
  */
 
+#include <linux/math64.h>
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
@@ -25,6 +26,9 @@
 #include <linux/bitops.h>
 #include <linux/delay.h>
 
+/* linux/include/time.h */
+#define NSEC_PER_SEC	1000000000L
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /* fsl_dspi_platdata flags */
@@ -379,6 +383,40 @@ static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
 	return -EINVAL;
 }
 
+static void ns_delay_scale(unsigned char *psc, unsigned char *sc, int delay_ns,
+			   unsigned long clkrate)
+{
+	int scale_needed, scale, minscale = INT_MAX;
+	int pscale_tbl[4] = {1, 3, 5, 7};
+	u32 remainder;
+	int i, j;
+
+	scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
+				   &remainder);
+	if (remainder)
+		scale_needed++;
+
+	for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
+		for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) {
+			scale = pscale_tbl[i] * (2 << j);
+			if (scale >= scale_needed) {
+				if (scale < minscale) {
+					minscale = scale;
+					*psc = i;
+					*sc = j;
+				}
+				break;
+			}
+		}
+
+	if (minscale == INT_MAX) {
+		pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
+			delay_ns, clkrate);
+		*psc = ARRAY_SIZE(pscale_tbl) - 1;
+		*sc = DSPI_CTAR_SCALE_BITS;
+	}
+}
+
 static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
 {
 	int ret;
@@ -412,6 +450,9 @@ static int fsl_dspi_child_pre_probe(struct udevice *dev)
 {
 	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 	struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
+	u32 cs_sck_delay = 0, sck_cs_delay = 0;
+	unsigned char pcssck = 0, cssck = 0;
+	unsigned char pasc = 0, asc = 0;
 
 	if (slave_plat->cs >= priv->num_chipselect) {
 		debug("DSPI invalid chipselect number %d(max %d)!\n",
@@ -419,7 +460,18 @@ static int fsl_dspi_child_pre_probe(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE;
+	ofnode_read_u32(dev->node, "fsl,spi-cs-sck-delay", &cs_sck_delay);
+	ofnode_read_u32(dev->node, "fsl,spi-sck-cs-delay", &sck_cs_delay);
+
+	/* Set PCS to SCK delay scale values */
+	ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk);
+
+	/* Set After SCK delay scale values */
+	ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk);
+
+	priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE |
+					 DSPI_CTAR_PCSSCK(pcssck) |
+					 DSPI_CTAR_PASC(pasc);
 
 	debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
 	      slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index bf06180cdd..6d5c4fcfeb 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -163,6 +163,15 @@ config WDT_SANDBOX
 	  can be probed and supports all of the methods of WDT, but does not
 	  really do anything.
 
+config WDT_SBSA
+	bool "SBSA watchdog timer support"
+	depends on WDT
+	help
+	   Select this to enable SBSA watchdog timer.
+	   This driver can operate ARM SBSA Generic Watchdog as a single stage.
+	   In the single stage mode, when the timeout is reached, your system
+	   will be reset by WS1. The first signal (WS0) is ignored.
+
 config WDT_SP805
 	bool "SP805 watchdog timer support"
 	depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 519bbd3a40..0f0b2eb5bc 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
 obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
 obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
 obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
+obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
 obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
 obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
 obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c
new file mode 100644
index 0000000000..2eae431ba6
--- /dev/null
+++ b/drivers/watchdog/sbsa_gwdt.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Watchdog driver for SBSA
+ *
+ * Copyright 2020 NXP
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm/device.h>
+#include <dm/fdtaddr.h>
+#include <dm/read.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <watchdog.h>
+#include <wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* SBSA Generic Watchdog register definitions */
+/* refresh frame */
+#define SBSA_GWDT_WRR		0x000
+
+/* control frame */
+#define SBSA_GWDT_WCS		0x000
+#define SBSA_GWDT_WOR		0x008
+#define SBSA_GWDT_WCV		0x010
+
+/* refresh/control frame */
+#define SBSA_GWDT_W_IIDR	0xfcc
+#define SBSA_GWDT_IDR		0xfd0
+
+/* Watchdog Control and Status Register */
+#define SBSA_GWDT_WCS_EN	BIT(0)
+#define SBSA_GWDT_WCS_WS0	BIT(1)
+#define SBSA_GWDT_WCS_WS1	BIT(2)
+
+struct sbsa_gwdt_priv {
+	void __iomem *reg_refresh;
+	void __iomem *reg_control;
+};
+
+static int sbsa_gwdt_reset(struct udevice *dev)
+{
+	struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
+
+	writel(0, priv->reg_refresh + SBSA_GWDT_WRR);
+
+	return 0;
+}
+
+static int sbsa_gwdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+	struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
+	u32 clk;
+
+	/*
+	 * it work in the single stage mode in u-boot,
+	 * The first signal (WS0) is ignored,
+	 * the timeout is (WOR * 2), so the WOR should be configured
+	 * to half value of timeout.
+	 */
+	clk = get_tbclk();
+	writel(clk / 2 * timeout,
+	       priv->reg_control + SBSA_GWDT_WOR);
+
+	/* writing WCS will cause an explicit watchdog refresh */
+	writel(SBSA_GWDT_WCS_EN, priv->reg_control + SBSA_GWDT_WCS);
+
+	return 0;
+}
+
+static int sbsa_gwdt_stop(struct udevice *dev)
+{
+	struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
+
+	writel(0, priv->reg_control + SBSA_GWDT_WCS);
+
+	return 0;
+}
+
+static int sbsa_gwdt_expire_now(struct udevice *dev, ulong flags)
+{
+	sbsa_gwdt_start(dev, 0, flags);
+
+	return 0;
+}
+
+static int sbsa_gwdt_probe(struct udevice *dev)
+{
+	debug("%s: Probing wdt%u (sbsa-gwdt)\n", __func__, dev->seq);
+
+	return 0;
+}
+
+static int sbsa_gwdt_ofdata_to_platdata(struct udevice *dev)
+{
+	struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
+
+	priv->reg_control = (void __iomem *)dev_read_addr_index(dev, 0);
+	if (IS_ERR(priv->reg_control))
+		return PTR_ERR(priv->reg_control);
+
+	priv->reg_refresh = (void __iomem *)dev_read_addr_index(dev, 1);
+	if (IS_ERR(priv->reg_refresh))
+		return PTR_ERR(priv->reg_refresh);
+
+	return 0;
+}
+
+static const struct wdt_ops sbsa_gwdt_ops = {
+	.start = sbsa_gwdt_start,
+	.reset = sbsa_gwdt_reset,
+	.stop = sbsa_gwdt_stop,
+	.expire_now = sbsa_gwdt_expire_now,
+};
+
+static const struct udevice_id sbsa_gwdt_ids[] = {
+	{ .compatible = "arm,sbsa-gwdt" },
+	{}
+};
+
+U_BOOT_DRIVER(sbsa_gwdt) = {
+	.name = "sbsa_gwdt",
+	.id = UCLASS_WDT,
+	.of_match = sbsa_gwdt_ids,
+	.probe = sbsa_gwdt_probe,
+	.priv_auto_alloc_size = sizeof(struct sbsa_gwdt_priv),
+	.ofdata_to_platdata = sbsa_gwdt_ofdata_to_platdata,
+	.ops = &sbsa_gwdt_ops,
+};