diff options
author | Tom Rini <trini@konsulko.com> | 2021-02-08 18:55:28 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2021-02-08 18:55:28 +0300 |
commit | a10d06add73ec0bd9e93b4b517fa2068ef1ca132 (patch) | |
tree | d2680808bc08a9f2e2a46b100c4d5fbd0812aedd /drivers | |
parent | 88262788fe8b82935648797d17250439e1fa0739 (diff) | |
parent | 5e7a207ebf8501b4ab1c6a081b7b806698ce0f6d (diff) | |
download | u-boot-a10d06add73ec0bd9e93b4b517fa2068ef1ca132.tar.xz |
Merge git://git.denx.de/u-boot-fsl-qoriq
Layerscape: Enable gpio
Bug fixes & updates related to dspi, qspi, pciep, SVR mask,
stream-id, env variables, mdio for LAyerscape Platforms
Add SATA, network variant 1, 2 support on sl28
powerpc: T1042: drop CONFIG_VIDEO, Add kmcent2 board supporrt, keymile
Bug fixes and updates for keymile, Kontron
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpio/mpc8xxx_gpio.c | 47 | ||||
-rw-r--r-- | drivers/mtd/spi/Kconfig | 10 | ||||
-rw-r--r-- | drivers/mtd/spi/spi-nor-core.c | 9 | ||||
-rw-r--r-- | drivers/net/dwc_eth_qos.c | 2 | ||||
-rw-r--r-- | drivers/net/fm/memac_phy.c | 76 | ||||
-rw-r--r-- | drivers/pci/Kconfig | 5 | ||||
-rw-r--r-- | drivers/pci/pcie_layerscape.h | 12 | ||||
-rw-r--r-- | drivers/spi/fsl_qspi.c | 12 |
8 files changed, 89 insertions, 84 deletions
diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index a964347fa3..c733603289 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -6,7 +6,7 @@ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is * * Copyright 2010 eXMeritus, A Boeing Company - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ #include <common.h> @@ -16,16 +16,6 @@ #include <asm/io.h> #include <dm/of_access.h> -struct ccsr_gpio { - u32 gpdir; - u32 gpodr; - u32 gpdat; - u32 gpier; - u32 gpimr; - u32 gpicr; - u32 gpibe; -}; - struct mpc8xxx_gpio_data { /* The bank's register base in memory */ struct ccsr_gpio __iomem *base; @@ -187,32 +177,11 @@ static int mpc8xxx_gpio_of_to_plat(struct udevice *dev) { struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev); struct mpc8xxx_gpio_data *data = dev_get_priv(dev); - fdt_addr_t addr; - u32 i; - u32 reg[4]; - if (ofnode_read_bool(dev_ofnode(dev), "little-endian")) + if (dev_read_bool(dev, "little-endian")) data->little_endian = true; - if (data->little_endian) - dev_read_u32_array(dev, "reg", reg, 4); - else - dev_read_u32_array(dev, "reg", reg, 2); - - if (data->little_endian) { - for (i = 0; i < 2; i++) - reg[i] = be32_to_cpu(reg[i]); - } - - addr = dev_translate_address(dev, reg); - - plat->addr = addr; - - if (data->little_endian) - plat->size = reg[3]; - else - plat->size = reg[1]; - + plat->addr = (ulong)dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size); plat->ngpios = dev_read_u32_default(dev, "ngpios", 32); return 0; @@ -257,11 +226,11 @@ static int mpc8xxx_gpio_probe(struct udevice *dev) if (!str) return -ENOMEM; - if (ofnode_device_is_compatible(dev_ofnode(dev), "fsl,qoriq-gpio")) { - unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio) - - sizeof(u32); - - out_be32((unsigned int *)gpibe, 0xffffffff); + if (device_is_compatible(dev, "fsl,qoriq-gpio")) { + if (data->little_endian) + out_le32(&data->base->gpibe, 0xffffffff); + else + out_be32(&data->base->gpibe, 0xffffffff); } uc_priv->bank_name = str; diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index ea444436ad..f8db8e5213 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -95,6 +95,16 @@ config SPI_FLASH_BAR Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. +config SPI_FLASH_UNLOCK_ALL + bool "Unlock the entire SPI flash on u-boot startup" + default y + help + Some flashes tend to power up with the software write protection + bits set. If this option is set, the whole flash will be unlocked. + + For legacy reasons, this option default to y. But if you intend to + actually use the software protection bits you should say n here. + config SF_DUAL_FLASH bool "SPI DUAL flash memory support" help diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e16b0e1462..ef426dac02 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2443,10 +2443,11 @@ static int spi_nor_init(struct spi_nor *nor) * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up * with the software protection bits set */ - if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || - JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || - JEDEC_MFR(nor->info) == SNOR_MFR_SST || - nor->info->flags & SPI_NOR_HAS_LOCK) { + if (IS_ENABLED(CONFIG_SPI_FLASH_UNLOCK_ALL) && + (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || + JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || + JEDEC_MFR(nor->info) == SNOR_MFR_SST || + nor->info->flags & SPI_NOR_HAS_LOCK)) { write_enable(nor); write_sr(nor, 0); spi_nor_wait_till_ready(nor); diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 944412958d..e8242ca4e1 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -2127,7 +2127,7 @@ static struct eqos_ops eqos_imx_ops = { struct eqos_config __maybe_unused eqos_imx_config = { .reg_access_always_ok = false, - .mdio_wait = 10000, + .mdio_wait = 10, .swr_wait = 50, .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 8bd32b0ab7..72b500a6d1 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -28,6 +28,8 @@ struct fm_mdio_priv { }; #endif +#define MAX_NUM_RETRIES 1000 + static u32 memac_in_32(u32 *reg) { #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN @@ -38,6 +40,42 @@ static u32 memac_in_32(u32 *reg) } /* + * Wait until the MDIO bus is free + */ +static int memac_wait_until_free(struct memac_mdio_controller *regs) +{ + unsigned int timeout = MAX_NUM_RETRIES; + + while ((memac_in_32(®s->mdio_stat) & MDIO_STAT_BSY) && timeout--) + ; + + if (!timeout) { + printf("timeout waiting for MDIO bus to be free\n"); + return -ETIMEDOUT; + } + + return 0; +} + +/* + * Wait till the MDIO read or write operation is complete + */ +static int memac_wait_until_done(struct memac_mdio_controller *regs) +{ + unsigned int timeout = MAX_NUM_RETRIES; + + while ((memac_in_32(®s->mdio_data) & MDIO_DATA_BSY) && timeout--) + ; + + if (!timeout) { + printf("timeout waiting for MDIO operation to complete\n"); + return -ETIMEDOUT; + } + + return 0; +} + +/* * Write value to the PHY for this device to the register at regnum, waiting * until the write is done before it returns. All PHY configuration has to be * done through the TSEC1 MIIM regs @@ -48,6 +86,7 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, struct memac_mdio_controller *regs; u32 mdio_ctl; u32 c45 = 1; /* Default to 10G interface */ + int err; #ifndef CONFIG_DM_ETH regs = bus->priv; @@ -69,9 +108,9 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, } else memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Set the port and dev addr */ mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); @@ -81,16 +120,16 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, if (c45) memac_out_32(®s->mdio_addr, regnum & 0xffff); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Write the value to the register */ memac_out_32(®s->mdio_data, MDIO_DATA(value)); - /* Wait till the MDIO write is complete */ - while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY) - ; + err = memac_wait_until_done(regs); + if (err) + return err; return 0; } @@ -106,6 +145,7 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, struct memac_mdio_controller *regs; u32 mdio_ctl; u32 c45 = 1; + int err; #ifndef CONFIG_DM_ETH regs = bus->priv; @@ -129,9 +169,9 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, } else memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Set the Port and Device Addrs */ mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); @@ -141,17 +181,17 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, if (c45) memac_out_32(®s->mdio_addr, regnum & 0xffff); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Initiate the read */ mdio_ctl |= MDIO_CTL_READ; memac_out_32(®s->mdio_ctl, mdio_ctl); - /* Wait till the MDIO write is complete */ - while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY) - ; + err = memac_wait_until_done(regs); + if (err) + return err; /* Return all Fs if nothing was there */ if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index b1de38f766..ba41787f64 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -219,7 +219,8 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A - default "fsl,lx2160a-pcie" if ARCH_LX2160A || ARCH_LX2162A + default "fsl,lx2160a-pcie" if ARCH_LX2160A + default "fsl,ls2088a-pcie" if ARCH_LX2162A default "fsl,ls1021a-pcie" if ARCH_LS1021A help This compatible is used to find pci controller node in Kernel DT @@ -228,7 +229,7 @@ config FSL_PCIE_COMPAT config FSL_PCIE_EP_COMPAT string "PCIe EP compatible of Kernel DT" depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4 - default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A || ARCH_LX2162A + default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A default "fsl,ls-pcie-ep" help This compatible is used to find pci controller ep node in Kernel DT diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 0124e8e051..8cdf516d9f 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -10,6 +10,8 @@ #include <pci.h> #include <linux/sizes.h> +#include <asm/arch-fsl-layerscape/svr.h> +#include <asm/arch-ls102xa/svr.h> #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE @@ -121,16 +123,6 @@ /* CS2 */ #define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */ -#define SVR_LS102XA 0 -#define SVR_VAR_PER_SHIFT 8 -#define SVR_LS102XA_MASK 0x700 -#define SVR_LS2088A 0x870900 -#define SVR_LS2084A 0x870910 -#define SVR_LS2048A 0x870920 -#define SVR_LS2044A 0x870930 -#define SVR_LS2081A 0x870918 -#define SVR_LS2041A 0x870914 - /* LS1021a PCIE space */ #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL #define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 8bc7038a82..f965301d6a 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -259,14 +259,6 @@ static const struct fsl_qspi_devtype_data ls1021a_data = { .little_endian = false, }; -static const struct fsl_qspi_devtype_data ls1088a_data = { - .rxfifo = SZ_128, - .txfifo = SZ_128, - .ahb_buf_size = SZ_1K, - .quirks = QUADSPI_QUIRK_TKT253890, - .little_endian = true, -}; - static const struct fsl_qspi_devtype_data ls2080a_data = { .rxfifo = SZ_128, .txfifo = SZ_64, @@ -409,7 +401,7 @@ static bool fsl_qspi_supports_op(struct spi_slave *slave, op->data.nbytes > q->devtype_data->txfifo) return false; - return true; + return spi_mem_default_supports_op(slave, op); } static void fsl_qspi_prepare_lut(struct fsl_qspi *q, @@ -877,7 +869,7 @@ static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, }, { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, }, { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, }, - { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, }, + { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls2080a_data, }, { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, }, { } }; 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