Merge tag 'u-boot-imx-20210125' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Changes for 2020.04
-------------------

- new board:
	Phytec phyCORE-i.MX8MP
	i.MX8MN Beacon EmbeddedWorks devkit

- Fixes:
	several nanbcb fixes
	fix for imx8mm_beacon
- further switch to distro boot commands
- DM:
	DM Ether for MX6UL

CI:

https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6013

7 files changed, 136 insertions, 7 deletions

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index e29d902544..e398d7de02 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -105,6 +105,20 @@ static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sy
 static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
 					   "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
 
+#if CONFIG_IS_ENABLED(DM_SPI)
+static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+					   "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+					   "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+					   "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+					   "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+					   "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+					   "sys_pll2_250m", "audio_pll2_out", };
+#endif
+
 static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
 					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
 
@@ -440,6 +454,21 @@ static int imx8mn_clk_probe(struct udevice *dev)
 	       base + 0x40a0, 0));
 #endif
 
+#if CONFIG_IS_ENABLED(DM_SPI)
+	clk_dm(IMX8MN_CLK_ECSPI1,
+	       imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
+	clk_dm(IMX8MN_CLK_ECSPI2,
+	       imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
+	clk_dm(IMX8MN_CLK_ECSPI3,
+	       imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
+	clk_dm(IMX8MN_CLK_ECSPI1_ROOT,
+	       imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+	clk_dm(IMX8MN_CLK_ECSPI2_ROOT,
+	       imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+	clk_dm(IMX8MN_CLK_ECSPI3_ROOT,
+	       imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+#endif
+
 	return 0;
 }
 
diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index 99a67edfb0..b70bcc383f 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -235,8 +235,6 @@ int ddr_init(struct dram_timing_info *dram_timing)
 
 	/* Step26: Set back register in Step4 to the original values if desired */
 	reg32_write(DDRC_RFSHCTL3(0), 0x0000000);
-	/* enable selfref_en by default */
-	setbits_le32(DDRC_PWRCTL(0), 0x1);
 
 	/* enable port 0 */
 	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
@@ -244,6 +242,9 @@ int ddr_init(struct dram_timing_info *dram_timing)
 
 	board_dram_ecc_scrub();
 
+	/* enable selfref_en by default */
+	setbits_le32(DDRC_PWRCTL(0), 0x1);
+
 	/* save the dram timing config into memory */
 	dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
 
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index f47a095c50..8ac859797f 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -790,7 +790,9 @@ static int esdhc_set_voltage(struct mmc *mmc)
 {
 	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
 	struct fsl_esdhc *regs = priv->esdhc_regs;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
 	int ret;
+#endif
 
 	priv->signal_voltage = mmc->signal_voltage;
 	switch (mmc->signal_voltage) {
diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c
index 5a0455e119..b67ac2f027 100644
--- a/drivers/power/power_i2c.c
+++ b/drivers/power/power_i2c.c
@@ -23,7 +23,7 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
 
 	if (check_reg(p, reg))
 		return -EINVAL;
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
 	struct udevice *dev;
 	int ret;
 
@@ -67,7 +67,7 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
 		return -EINVAL;
 	}
 
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
 	return dm_i2c_write(dev, reg, buf, pmic_i2c_tx_num);
 #else
 	return i2c_write(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num);
@@ -83,7 +83,7 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
 	if (check_reg(p, reg))
 		return -EINVAL;
 
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
 	struct udevice *dev;
 
 	ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr,
@@ -131,7 +131,7 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
 int pmic_probe(struct pmic *p)
 {
 	debug("Bus: %d PMIC:%s probed!\n", p->bus, p->name);
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
 	struct udevice *dev;
 	int ret;
 
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index c5ffad80fb..553a0315df 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <log.h>
 #include <malloc.h>
@@ -20,6 +21,82 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* MX35 and older is CSPI */
+#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35)
+#define MXC_CSPI
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+	u32 test;
+};
+
+#define MXC_CSPICTRL_EN			BIT(0)
+#define MXC_CSPICTRL_MODE		BIT(1)
+#define MXC_CSPICTRL_XCH		BIT(2)
+#define MXC_CSPICTRL_SMC		BIT(3)
+#define MXC_CSPICTRL_POL		BIT(4)
+#define MXC_CSPICTRL_PHA		BIT(5)
+#define MXC_CSPICTRL_SSCTL		BIT(6)
+#define MXC_CSPICTRL_SSPOL		BIT(7)
+#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
+#define MXC_CSPICTRL_RXOVF		BIT(6)
+#define MXC_CSPIPERIOD_32KHZ		BIT(15)
+#define MAX_SPI_BYTES			4
+#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_TC			BIT(7)
+#define MXC_CSPICTRL_MAXBITS		0xfff
+#else	/* MX31 */
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_TC			BIT(8)
+#define MXC_CSPICTRL_MAXBITS		0x1f
+#endif
+
+#else	/* MX51 and newer is ECSPI */
+#define MXC_ECSPI
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 cfg;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+};
+
+#define MXC_CSPICTRL_EN			BIT(0)
+#define MXC_CSPICTRL_MODE		BIT(1)
+#define MXC_CSPICTRL_XCH		BIT(2)
+#define MXC_CSPICTRL_MODE_MASK		(0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x)		(((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)		(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)		(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS		0xfff
+#define MXC_CSPICTRL_TC			BIT(7)
+#define MXC_CSPICTRL_RXOVF		BIT(6)
+#define MXC_CSPIPERIOD_32KHZ		BIT(15)
+#define MAX_SPI_BYTES			32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN	18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA		0  /* SCLK phase control */
+#define MXC_CSPICON_POL		4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL	12 /* SS polarity */
+#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
+#endif
+
 #ifdef CONFIG_MX27
 /* i.MX27 has a completely wrong register layout and register definitions in the
  * datasheet, the correct one is in the Freescale's Linux driver */
@@ -541,8 +618,19 @@ static int mxc_spi_probe(struct udevice *bus)
 	if (mxcs->base == FDT_ADDR_T_NONE)
 		return -ENODEV;
 
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk clk;
+	ret = clk_get_by_index(bus, 0, &clk);
+	if (ret)
+		return ret;
+
+	clk_enable(&clk);
+
+	mxcs->max_hz = clk_get_rate(&clk);
+#else
 	mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
 				      20000000);
+#endif
 
 	return 0;
 }
diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c
index 006dd04b9e..012f304595 100644
--- a/drivers/spi/nxp_fspi.c
+++ b/drivers/spi/nxp_fspi.c
@@ -320,6 +320,14 @@ static const struct nxp_fspi_devtype_data lx2160a_data = {
 	.little_endian = true,  /* little-endian    */
 };
 
+static const struct nxp_fspi_devtype_data imx8mm_data = {
+	.rxfifo = SZ_512,       /* (64  * 64 bits)  */
+	.txfifo = SZ_1K,        /* (128 * 64 bits)  */
+	.ahb_buf_size = SZ_2K,  /* (256 * 64 bits)  */
+	.quirks = 0,
+	.little_endian = true,  /* little-endian    */
+};
+
 struct nxp_fspi {
 	struct udevice *dev;
 	void __iomem *iobase;
@@ -985,6 +993,7 @@ static const struct dm_spi_ops nxp_fspi_ops = {
 
 static const struct udevice_id nxp_fspi_ids[] = {
 	{ .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
+	{ .compatible = "nxp,imx8mm-fspi", .data = (ulong)&imx8mm_data, },
 	{ }
 };
 
diff --git a/drivers/w1/mxc_w1.c b/drivers/w1/mxc_w1.c
index 3637febc0c..b96c1a00bf 100644
--- a/drivers/w1/mxc_w1.c
+++ b/drivers/w1/mxc_w1.c
@@ -17,8 +17,8 @@
  * Martin Fuzzey <martin.fuzzey@flowbird.group>
  */
 
-#include <asm/arch/clock.h>
 #include <common.h>
+#include <asm/arch/clock.h>
 #include <dm.h>
 #include <dm/device_compat.h>
 #include <linux/bitops.h>