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| author | Tom Rini <trini@konsulko.com> | 2019-03-20 02:58:48 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-03-20 02:58:48 +0300 |
| commit | a00d15757d7a513e410f15f2f910cb52333361a3 (patch) | |
| tree | aa848993b137f22cd7c7aa66a21e175bab570fda /drivers | |
| parent | 810ae23fbc57346508690425a785d44117e91182 (diff) | |
| parent | 599f7aa541bb5a658cbfd2af73bd9d2f6e828d43 (diff) | |
| download | u-boot-a00d15757d7a513e410f15f2f910cb52333361a3.tar.xz | |
Merge git://git.denx.de/u-boot-marvell
- Enable network interface on clearfog_gt_8k (Baruch)
- Fix dreamplug boot by adding an spi0 alias to the DT (Chris)
- Fix / enhance Marvell ddr3 setup / parameters (Chris)
- Change CONFIG_SYS_MALLOC_F_LEN to 0x2000 on db-88f6820-amc (Chris)
- Enable SPL_FLASH_BAR on db-88f6820-amc (Chris)
- Use correct pcie controller name in Armada-38x dts files (Chris)
- Disable d-cache on Kirkwood platforms as currently needed (Chris)
- Add a more descriptive comment to pci_mvebu.c (Stefan)
- Update Marvell maintainers entry (Stefan)
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_db.c | 8 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 3 | ||||
| -rw-r--r-- | drivers/pci/pci_mvebu.c | 6 |
3 files changed, 12 insertions, 5 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c index 111a8586c6..b2f11a8399 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_db.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c @@ -420,13 +420,13 @@ unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_dd result = speed_bin_table_t_rcd_t_rp[index]; break; case SPEED_BIN_TRAS: - if (index < SPEED_BIN_DDR_1066G) + if (index <= SPEED_BIN_DDR_1066G) result = 37500; - else if (index < SPEED_BIN_DDR_1333J) + else if (index <= SPEED_BIN_DDR_1333J) result = 36000; - else if (index < SPEED_BIN_DDR_1600K) + else if (index <= SPEED_BIN_DDR_1600K) result = 35000; - else if (index < SPEED_BIN_DDR_1866M) + else if (index <= SPEED_BIN_DDR_1866M) result = 34000; else result = 33000; diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index db0f8ad7fb..df832ac6dc 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -50,6 +50,7 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) int max_phase = MIN_VALUE, current_phase; enum hws_access_type access_type = ACCESS_TYPE_UNICAST; u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); + unsigned int max_cs = mv_ddr_cs_num_get(); CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG, @@ -59,7 +60,7 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) data_read, MASK_ALL_BITS)); val = data_read[if_id]; - for (cs_num = 0; cs_num < MAX_CS_NUM; cs_num++) { + for (cs_num = 0; cs_num < max_cs; cs_num++) { read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num); /* find maximum of read_samples */ diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 6026fa67f9..e21dc10c2f 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -369,6 +369,12 @@ static int mvebu_get_tgt_attr(ofnode node, int devfn, if (!range) return -EINVAL; + /* + * Linux uses of_n_addr_cells() to get the number of address cells + * here. Currently this function is only available in U-Boot when + * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in + * general, lets't hardcode the "pna" value in the U-Boot code. + */ pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */ rangesz = pna + na + ns; nranges = rlen / sizeof(__be32) / rangesz; |