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authorTom Rini <trini@konsulko.com>2019-09-16 20:13:45 +0300
committerTom Rini <trini@konsulko.com>2019-09-16 20:13:45 +0300
commita9fa70b7b7167487affc5d919e541872c99e814b (patch)
treeffe16fdcecb3afe742d730f3c6aa87a3caf8647c /drivers
parent0d6160a340cee36813438484dd9f5766c250f22e (diff)
parent737c016d25d6c45e9c003fca9df2ca75f0b1e772 (diff)
downloadu-boot-a9fa70b7b7167487affc5d919e541872c99e814b.tar.xz
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Add emmc hs200 support - Few bug fixes related to serdes, I2C, ethernet, etc
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mmc/Kconfig10
-rw-r--r--drivers/mmc/fsl_esdhc.c34
-rw-r--r--drivers/watchdog/sp805_wdt.c10
3 files changed, 37 insertions, 17 deletions
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 8fb2bfa444..7361bcaf8e 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -167,7 +167,6 @@ config MMC_HS200_SUPPORT
The HS200 mode is support by some eMMC. The bus frequency is up to
200MHz. This mode requires tuning the IO.
-
config SPL_MMC_HS200_SUPPORT
bool "enable HS200 support in SPL"
help
@@ -695,10 +694,19 @@ endif
config FSL_ESDHC
bool "Freescale/NXP eSDHC controller support"
+ select FSL_ESDHC_USE_PERIPHERAL_CLK if MMC_HS200_SUPPORT || MMC_UHS_SUPPORT
help
This selects support for the eSDHC (Enhanced Secure Digital Host
Controller) found on numerous Freescale/NXP SoCs.
+config FSL_ESDHC_USE_PERIPHERAL_CLK
+ bool "enable ESDHC peripheral clock support"
+ depends on FSL_ESDHC
+ help
+ eSDHC supports two reference clocks (platform clock and peripheral clock).
+ Peripheral clock which could provide higher clock frequency is required to
+ be used for tuning of SD UHS mode and eMMC HS200/HS400 modes.
+
config FSL_ESDHC_IMX
bool "Freescale/NXP i.MX eSDHC controller support"
help
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 07318472a7..28d2312ef7 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -395,10 +395,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
esdhc_write32(&regs->cmdarg, cmd->cmdarg);
esdhc_write32(&regs->xfertyp, xfertyp);
- if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
- (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
- flags = IRQSTAT_BRR;
-
/* Wait for the command to complete */
start = get_timer(0);
while (!(esdhc_read32(&regs->irqstat) & flags)) {
@@ -458,12 +454,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
esdhc_pio_read_write(priv, data);
#else
- flags = DATA_COMPLETE;
- if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
- (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
- flags = IRQSTAT_BRR;
- }
-
do {
irqstat = esdhc_read32(&regs->irqstat);
@@ -476,7 +466,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
err = -ECOMM;
goto out;
}
- } while ((irqstat & flags) != flags);
+ } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
/*
* Need invalidate the dcache here again to avoid any
@@ -517,7 +507,9 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
int div = 1;
int pre_div = 2;
int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
- int sdhc_clk = priv->sdhc_clk;
+ unsigned int sdhc_clk = priv->sdhc_clk;
+ u32 time_out;
+ u32 value;
uint clk;
if (clock < mmc->cfg->f_min)
@@ -538,11 +530,18 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
- udelay(10000);
+ time_out = 20;
+ value = PRSSTAT_SDSTB;
+ while (!(esdhc_read32(&regs->prsstat) & value)) {
+ if (time_out == 0) {
+ printf("fsl_esdhc: Internal clock never stabilised.\n");
+ break;
+ }
+ time_out--;
+ mdelay(1);
+ }
esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
-
- priv->clock = clock;
}
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
@@ -1024,6 +1023,8 @@ static int fsl_esdhc_probe(struct udevice *dev)
return ret;
}
+ mmc_of_parse(dev, &plat->cfg);
+
mmc = &plat->mmc;
mmc->cfg = &plat->cfg;
mmc->dev = dev;
@@ -1081,6 +1082,9 @@ static const struct dm_mmc_ops fsl_esdhc_ops = {
.get_cd = fsl_esdhc_get_cd,
.send_cmd = fsl_esdhc_send_cmd,
.set_ios = fsl_esdhc_set_ios,
+#ifdef MMC_SUPPORTS_TUNING
+ .execute_tuning = fsl_esdhc_execute_tuning,
+#endif
};
#endif
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 966128216f..f1e781e4e6 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -87,9 +87,16 @@ static int sp805_wdt_stop(struct udevice *dev)
return 0;
}
+static int sp805_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ sp805_wdt_start(dev, 0, flags);
+
+ return 0;
+}
+
static int sp805_wdt_probe(struct udevice *dev)
{
- debug("%s: Probing wdt%u\n", __func__, dev->seq);
+ debug("%s: Probing wdt%u (sp805-wdt)\n", __func__, dev->seq);
return 0;
}
@@ -109,6 +116,7 @@ static const struct wdt_ops sp805_wdt_ops = {
.start = sp805_wdt_start,
.reset = sp805_wdt_reset,
.stop = sp805_wdt_stop,
+ .expire_now = sp805_wdt_expire_now,
};
static const struct udevice_id sp805_wdt_ids[] = {