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| author | Siva Durga Prasad Paladugu <sivadur@xilinx.com> | 2019-07-01 09:49:25 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2019-10-08 10:41:27 +0300 |
| commit | bc493d911e8c4e59ddaf0def0d35f1e2db0899ab (patch) | |
| tree | f374be8c2fc31e7477219d8a31313cbf330532ee /drivers | |
| parent | 95105089afe2a204883e9c0f4c2c694469ec31d1 (diff) | |
| download | u-boot-bc493d911e8c4e59ddaf0def0d35f1e2db0899ab.tar.xz | |
net: zynq_gem: Remove check for Versal
This patch removes check for Versal platform
in gem driver as it now supports clock setting
through clock framework.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/zynq_gem.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index a35ecab79e..a7a6ce987f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -463,7 +463,6 @@ static int zynq_gem_init(struct udevice *dev) break; } -#if !defined(CONFIG_ARCH_VERSAL) ret = clk_set_rate(&priv->clk, clk_rate); if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { dev_err(dev, "failed to set tx clock rate\n"); @@ -475,9 +474,6 @@ static int zynq_gem_init(struct udevice *dev) dev_err(dev, "failed to enable tx clock\n"); return ret; } -#else - debug("requested clk_rate %ld\n", clk_rate); -#endif setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); |