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| author | Olliver Schinagl <oliver@schinagl.nl> | 2018-11-21 21:05:30 +0300 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2018-12-07 19:54:33 +0300 |
| commit | 61436d502b33854ddf33797670d4e25c0d79d540 (patch) | |
| tree | 70f553589997700d9d66b7cc513efe5a89a42627 /include/axp209.h | |
| parent | 3f7d76a7ed92e75ff30c7e6287eca71f09da0bcf (diff) | |
| download | u-boot-61436d502b33854ddf33797670d4e25c0d79d540.tar.xz | |
power: axp209: Add support for voltage rate control on LDO3
The AXP209 LDO3 regulator supports voltage rate control, or can set a
slew rate.
This allows for the power to gradually rise up to the desired voltage,
instead of spiking up as fast as possible. Reason to have this can be
to reduce the inrush currents for example.
There are 3 slopes to choose from, the default, 'none' is a voltage rise
of 0.0167 V/uS, a 1.6 mV/uS and a 0.8 mV/uS voltage rise.
In ideal world (where vendors follow the recommended design guidelines)
this setting should not be enabled by default. Unless of course AXP209
crashes instead of reporting overcurrent condition as it normally should
do in this case.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Priit Laes <plaes@plaes.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'include/axp209.h')
| -rw-r--r-- | include/axp209.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/include/axp209.h b/include/axp209.h index dc27d65a43..f4f1b2fe56 100644 --- a/include/axp209.h +++ b/include/axp209.h @@ -10,6 +10,7 @@ enum axp209_reg { AXP209_CHIP_VERSION = 0x03, AXP209_OUTPUT_CTRL = 0x12, AXP209_DCDC2_VOLTAGE = 0x23, + AXP209_VRC_DCDC2_LDO3 = 0x25, AXP209_DCDC3_VOLTAGE = 0x27, AXP209_LDO24_VOLTAGE = 0x28, AXP209_LDO3_VOLTAGE = 0x29, @@ -34,6 +35,26 @@ enum axp209_reg { #define AXP209_OUTPUT_CTRL_DCDC2 BIT(4) #define AXP209_OUTPUT_CTRL_LDO3 BIT(6) +/* + * AXP209 datasheet contains wrong information about LDO3 VRC: + * - VRC is actually enabled when BIT(1) is True + * - VRC is actually not enabled by default (BIT(3) = 0 after reset) + */ +#define AXP209_VRC_LDO3_EN BIT(3) +#define AXP209_VRC_DCDC2_EN BIT(2) +#define AXP209_VRC_LDO3_800uV_uS (BIT(1) | AXP209_VRC_LDO3_EN) +#define AXP209_VRC_LDO3_1600uV_uS AXP209_VRC_LDO3_EN +#define AXP209_VRC_DCDC2_800uV_uS (BIT(0) | AXP209_VRC_DCDC2_EN) +#define AXP209_VRC_DCDC2_1600uV_uS AXP209_VRC_DCDC2_EN +#define AXP209_VRC_LDO3_MASK 0xa +#define AXP209_VRC_DCDC2_MASK 0x5 +#define AXP209_VRC_DCDC2_SLOPE_SET(reg, cfg) \ + (((reg) & ~AXP209_VRC_DCDC2_MASK) | \ + ((cfg) & AXP209_VRC_DCDC2_MASK)) +#define AXP209_VRC_LDO3_SLOPE_SET(reg, cfg) \ + (((reg) & ~AXP209_VRC_LDO3_MASK) | \ + ((cfg) & AXP209_VRC_LDO3_MASK)) + #define AXP209_LDO24_LDO2_MASK 0xf0 #define AXP209_LDO24_LDO4_MASK 0x0f #define AXP209_LDO24_LDO2_SET(reg, cfg) \ |