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author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-10-16 17:01:15 +0400 |
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committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 23:54:03 +0400 |
commit | 6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch) | |
tree | ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /include/configs/davinci_sffsdr.h | |
parent | 71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff) | |
download | u-boot-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.xz |
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'include/configs/davinci_sffsdr.h')
-rw-r--r-- | include/configs/davinci_sffsdr.h | 78 |
1 files changed, 39 insertions, 39 deletions
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 39fb2a5603..e9cd5a6621 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -26,45 +26,45 @@ /* Board */ #define SFFSDR -#define CFG_NAND_LARGEPAGE -#define CFG_USE_NAND -#define CFG_USE_DSPLINK /* This is to prevent U-Boot from +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_SYS_USE_NAND +#define CONFIG_SYS_USE_DSPLINK /* This is to prevent U-Boot from * powering ON the DSP. */ /* SoC Configuration */ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ -#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CFG_HZ 1000 +#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CONFIG_SYS_HZ 1000 /* EEPROM definitions for Atmel 24LC64 EEPROM chip */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 /* Memory Info */ -#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ -#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ -#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ -#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ +#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define CONFIG_STACKSIZE (256*1024) /* regular stack */ #define PHYS_SDRAM_1 0x80000000 /* DDR Start */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ #define DDR_4BANKS /* 4-bank DDR2 (128MB) */ /* Serial Driver info */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ -#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ -#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* I2C Configuration */ #define CONFIG_HARD_I2C #define CONFIG_DRIVER_DAVINCI_I2C -#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /* Network & Ethernet Configuration */ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII @@ -76,41 +76,41 @@ #define CONFIG_OVERWRITE_ETHADDR_ONCE /* Flash & Environment */ #undef CONFIG_ENV_IS_IN_FLASH -#define CFG_NO_FLASH +#define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ #define CONFIG_ENV_SIZE SZ_128K #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ -#define CFG_NAND_BASE 0x02000000 -#define CFG_NAND_HW_ECC -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_SYS_NAND_BASE 0x02000000 +#define CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ /* I2C switch definitions for PCA9543 chip */ -#define CFG_I2C_PCA9543_ADDR 0x70 -#define CFG_I2C_PCA9543_ADDR_LEN 0 /* Single register. */ -#define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ +#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70 +#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */ +#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ /* U-Boot general configuration */ #undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ #define CONFIG_MISC_INIT_R #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CFG_PBSIZE \ - (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print buffer size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x80700000 /* Default Linux kernel +#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel * load address. */ #define CONFIG_VERSION_VARIABLE #define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, * may be later */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_CMDLINE_EDITING -#define CFG_LONGHELP +#define CONFIG_SYS_LONGHELP #define CONFIG_CRC32_VERIFY #define CONFIG_MX_CYCLIC /* Linux Information */ |