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authorTom Rini <trini@konsulko.com>2022-03-31 01:07:23 +0300
committerTom Rini <trini@konsulko.com>2022-04-08 17:46:22 +0300
commit55b3ba4c2ba4c464491604c5da63debae72aa5c6 (patch)
treed9c1f95b2ba4e6b44b917431a764afcced7fe72b /include/configs/k2g_evm.h
parent5d14c336b21da34d07e93b5689ccffd52b8cc658 (diff)
downloadu-boot-55b3ba4c2ba4c464491604c5da63debae72aa5c6.tar.xz
spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig
This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include/configs/k2g_evm.h')
-rw-r--r--include/configs/k2g_evm.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 294ce4662e..887fda90d6 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -59,10 +59,6 @@
#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CQSPI_REF_CLK 384000000
-#endif
-
#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS
#include <configs/ti_armv7_keystone2.h>