diff options
| author | Teresa Remmet <t.remmet@phytec.de> | 2021-01-13 18:28:09 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-01-23 13:30:32 +0300 |
| commit | c661c511e9cfc86f18b1326b0f0d1e338a8c442a (patch) | |
| tree | ddfd4ea167f447ecce01c2f3fb772019778c9cba /include/configs/phycore_imx8mp.h | |
| parent | 3f832699ff0be590422ac32e409320d684c25ab9 (diff) | |
| download | u-boot-c661c511e9cfc86f18b1326b0f0d1e338a8c442a.tar.xz | |
board: phytec: imx8mp: Add PHYTEC phyCORE-i.MX8MP support
Add initial support PHYTEC phyCORE-i.MX8MP SOM.
Supported features:
- 2GB LPDDR4 RAM
- eMMC
- external SD
- debug UART2
- watchdog
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'include/configs/phycore_imx8mp.h')
| -rw-r--r-- | include/configs/phycore_imx8mp.h | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h new file mode 100644 index 0000000000..889dd36e6e --- /dev/null +++ b/include/configs/phycore_imx8mp.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +#ifndef __PHYCORE_IMX8MP_H +#define __PHYCORE_IMX8MP_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#define CONFIG_SPL_MAX_SIZE (152 * SZ_1K) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x960000 +#define CONFIG_SPL_BSS_START_ADDR 0x98FC00 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PCA9450 + +#undef CONFIG_DM_I2C +#define CONFIG_SYS_I2C + +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr=0x48000000\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=2\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi;\0 " \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 + +/* UART */ +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* USDHC */ +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* I2C */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#endif /* __PHYCORE_IMX8MP_H */ |