diff options
| author | Pragnesh Patel <pragnesh.patel@sifive.com> | 2021-01-17 15:41:25 +0300 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2021-01-18 06:06:32 +0300 |
| commit | bc8d12bfd8750de265b742f2ab9cdde2726ea85f (patch) | |
| tree | 2bbdf6fd3df17150cba305c93de6c906043d8dea /include/configs/qemu-riscv.h | |
| parent | a80f85138c9457141c799c022b5c924252031512 (diff) | |
| download | u-boot-bc8d12bfd8750de265b742f2ab9cdde2726ea85f.tar.xz | |
riscv: timer: Add support for an early timer
Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'include/configs/qemu-riscv.h')
| -rw-r--r-- | include/configs/qemu-riscv.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index a2f33587c2..5291de83f8 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -29,6 +29,11 @@ #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 +#define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMER_FREQ 1000000 + +#define RISCV_SMODE_TIMER_FREQ 1000000 + /* Environment options */ #ifndef CONFIG_SPL_BUILD |