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| author | Tom Rini <trini@konsulko.com> | 2021-11-14 02:10:40 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-12-01 18:58:10 +0300 |
| commit | c7fad78ec0ee41b72a58bebb61959570eb937ab1 (patch) | |
| tree | 3306bef438e84d7f3bad8c9a18db549f992779ca /include/configs/socrates.h | |
| parent | 970bf8603b877e2b66170290f751f9c23c120838 (diff) | |
| download | u-boot-c7fad78ec0ee41b72a58bebb61959570eb937ab1.tar.xz | |
Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_BR0_PRELIM
CONFIG_SYS_OR1_PRELIM
CONFIG_SYS_BR1_PRELIM
CONFIG_SYS_OR2_PRELIM
CONFIG_SYS_BR2_PRELIM
CONFIG_SYS_OR2_PRELIM
CONFIG_SYS_BR3_PRELIM
CONFIG_SYS_OR3_PRELIM
CONFIG_SYS_BR4_PRELIM
CONFIG_SYS_OR4_PRELIM
CONFIG_SYS_BR5_PRELIM
CONFIG_SYS_OR5_PRELIM
CONFIG_SYS_BR6_PRELIM
CONFIG_SYS_OR6_PRELIM
CONFIG_SYS_BR7_PRELIM
CONFIG_SYS_OR7_PRELIM
This also introduces CONFIG_SYS_BR0_PRELIM_BOOL as not all platforms
that can set these values do so. Add the relevant SYS_BRx_PRELIM_BOOL
to platforms that had not been previously migrated.
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include/configs/socrates.h')
| -rw-r--r-- | include/configs/socrates.h | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 68bd2548ca..b7296daa37 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -97,11 +97,6 @@ #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ -#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ -#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ -#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ -#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ - #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM @@ -128,8 +123,6 @@ #define CONFIG_SYS_FPGA_BASE 0xc0000000 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ #define CONFIG_SYS_HMI_BASE 0xc0010000 -#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ -#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -137,8 +130,6 @@ /* LIME GDC */ #define CONFIG_SYS_LIME_BASE 0xc8000000 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ -#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ #define CONFIG_SYS_SPD_BUS_NUM 0 |