diff options
| author | Yangbo Lu <yangbo.lu@nxp.com> | 2020-10-20 06:04:52 +0300 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2020-11-28 05:39:44 +0300 |
| commit | 8ee802f899efb422cbd5dc51a734d735320e9999 (patch) | |
| tree | 0535a2e17bf25b4d0f368f16ad533606ca373acb /include/fsl_esdhc.h | |
| parent | 263ddfc3454ead3a988adef39b962479adce2b28 (diff) | |
| download | u-boot-8ee802f899efb422cbd5dc51a734d735320e9999.tar.xz | |
mmc: fsl_esdhc: make sure delay chain locked for HS400
For eMMC HS400 mode, the DLL reset is a required step for mmc rescan.
This step has not been documented in reference manual, but the RM will
be fixed sooner or later.
In previous commit to support eMMC HS400,
db8f936 mmc: fsl_esdhc: support eMMC HS400 mode
the steps to configure DLL could be found in commit message,
13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
14. Wait for delay chain to lock.
these would be fixed as,
13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
13.1 Write DLLCFG0[DLL_RESET] to 1 and wait for 1us,
then write DLLCFG0[DLL_RESET]
14. Wait for delay chain to lock.
This patch is to add the step of DLL reset, and make sure delay chain
locked for HS400.
Fixes: db8f93672b42 ("mmc: fsl_esdhc: support eMMC HS400 mode")
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Diffstat (limited to 'include/fsl_esdhc.h')
| -rw-r--r-- | include/fsl_esdhc.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index e6f1c75e27..850a304bd7 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -187,8 +187,12 @@ /* DLL config 0 register */ #define DLL_ENABLE 0x80000000 +#define DLL_RESET 0x40000000 #define DLL_FREQ_SEL 0x08000000 +/* DLL status 0 register */ +#define DLL_STS_SLV_LOCK 0x08000000 + #define MAX_TUNING_LOOP 40 #define HOSTVER_VENDOR(x) (((x) >> 8) & 0xff) |