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| author | Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com> | 2017-10-30 00:08:58 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2017-11-07 12:26:27 +0300 |
| commit | bcfb36537552441faeceb6b0089ab40a29b9dff3 (patch) | |
| tree | 1270d542e8e13e1399be7a4e7cc42ebf2ef29c31 /include/fsl_esdhc.h | |
| parent | cc65e354feb6f13fb4d7c910edaddf805fe08c71 (diff) | |
| download | u-boot-bcfb36537552441faeceb6b0089ab40a29b9dff3.tar.xz | |
mmc: fsl_esdhc: Fix PIO timeout
The following error has been observed on i.MX25 with a high-speed SDSC
card:
Data Write Failed in PIO Mode.
It was caused by the timeout set on PRSSTAT.BWEN, which was triggered
because this bit takes 15 ms to be set after writing the first block to
DATPORT with this card. Without this timeout, all the blocks are
properly written.
This timeout was implemented by decrementing a variable, so it was
depending on the CPU frequency. Fix this issue by setting this timeout
to a long enough absolute duration (500 ms).
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'include/fsl_esdhc.h')
| -rw-r--r-- | include/fsl_esdhc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 02b362d5e3..de1f5e7d9f 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -130,7 +130,7 @@ #define XFERTYP_DMAEN 0x00000001 #define CINS_TIMEOUT 1000 -#define PIO_TIMEOUT 100000 +#define PIO_TIMEOUT 500 #define DSADDR 0x2e004 |