diff options
| author | Michael Walle <michael@walle.cc> | 2020-10-12 11:07:14 +0300 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2020-10-14 09:00:44 +0300 |
| commit | 361a422b905052dcbcba61fc1e0d8d804fdca433 (patch) | |
| tree | 2a6feb8bed00d12d568db596f276263ea3a854ad /include/fsl_esdhc.h | |
| parent | 52faec31827ec1a1837977e29c067424426634c5 (diff) | |
| download | u-boot-361a422b905052dcbcba61fc1e0d8d804fdca433.tar.xz | |
mmc: fsl_esdhc: add ADMA2 support
Newer eSDHC controllers support ADMA2 descriptor tables which support
64bit DMA addresses. One notable user of addresses in the upper memory
segment is the EFI loader.
If support is enabled, but the controller doesn't support ADMA2, we
will fall back to SDMA (and thus 32 bit DMA addresses only).
Signed-off-by: Michael Walle <michael@walle.cc>
Diffstat (limited to 'include/fsl_esdhc.h')
| -rw-r--r-- | include/fsl_esdhc.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index cc119668d6..e6f1c75e27 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -97,6 +97,10 @@ #define PROCTL_DTW_4 0x00000002 #define PROCTL_DTW_8 0x00000004 #define PROCTL_D3CD 0x00000008 +#define PROCTL_DMAS_MASK 0x00000300 +#define PROCTL_DMAS_SDMA 0x00000000 +#define PROCTL_DMAS_ADMA1 0x00000100 +#define PROCTL_DMAS_ADMA2 0x00000300 #define PROCTL_VOLT_SEL 0x00000400 #define CMDARG 0x0002e008 @@ -187,6 +191,16 @@ #define MAX_TUNING_LOOP 40 +#define HOSTVER_VENDOR(x) (((x) >> 8) & 0xff) +#define VENDOR_V_10 0x00 +#define VENDOR_V_20 0x10 +#define VENDOR_V_21 0x11 +#define VENDOR_V_22 0x12 +#define VENDOR_V_23 0x13 +#define VENDOR_V_30 0x20 +#define VENDOR_V_31 0x21 +#define VENDOR_V_32 0x22 + struct fsl_esdhc_cfg { phys_addr_t esdhc_base; u32 sdhc_clk; |