diff options
| author | Yangbo Lu <yangbo.lu@nxp.com> | 2020-09-01 11:58:05 +0300 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2020-10-12 10:46:34 +0300 |
| commit | db8f93672b42411856b11cf294a6f9c25482179c (patch) | |
| tree | a3a17eedf5c2999323a3ed7b9b6c9008884b8313 /include/fsl_esdhc.h | |
| parent | d271e10581e7f15451e9d4c3cdd39044440a848a (diff) | |
| download | u-boot-db8f93672b42411856b11cf294a6f9c25482179c.tar.xz | |
mmc: fsl_esdhc: support eMMC HS400 mode
The process for eMMC HS400 mode for eSDHC is,
1. Perform the Tuning Process at the HS400 target operating frequency.
Latched the clock division value.
2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG].
3. Switch to High Speed mode and then set the card clock frequency to
a value not greater than 52Mhz
4. Clear TBCTL[TB_EN],tuning block enable bit.
5. Change to 8 bit DDR Mode
6. Switch the card to HS400 mode.
7. Set TBCTL[TB_EN], tuning block enable bit.
8. Clear SYSCTL[SDCLKEN]
9. Wait for PRSSTAT[SDSTB] to be set
10. Change the clock division to latched value.Set TBCTL[HS 400 mode]
and Set SDCLKCTL[CMD_CLK_CTRL]
11. Set SYSCTL[SDCLKEN]
12. Wait for PRSSTAT[SDSTB] to be set
13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
14. Wait for delay chain to lock.
15. Set TBCTL[HS400_WNDW_ADJUST]
16. Again clear SYSCTL[SDCLKEN]
17. Wait for PRSSTAT[SDSTB] to be set
18. Set ESDHCCTL[FAF]
19. Wait for ESDHCCTL[FAF] to be cleared
20. Set SYSCTL[SDCLKEN]
21. Wait for PRSSTAT[SDSTB] to be set.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Diffstat (limited to 'include/fsl_esdhc.h')
| -rw-r--r-- | include/fsl_esdhc.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 0a426e1471..cc119668d6 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -172,6 +172,18 @@ /* Tuning block control register */ #define TBCTL_TB_EN 0x00000004 +#define HS400_MODE 0x00000010 +#define HS400_WNDW_ADJUST 0x00000040 + +/* SD clock control register */ +#define CMD_CLK_CTL 0x00008000 + +/* SD timing control register */ +#define FLW_CTL_BG 0x00008000 + +/* DLL config 0 register */ +#define DLL_ENABLE 0x80000000 +#define DLL_FREQ_SEL 0x08000000 #define MAX_TUNING_LOOP 40 |