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| author | Oleksandr Suvorov <oleksandr.suvorov@foundries.io> | 2021-09-08 21:56:43 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-10-07 22:58:49 +0300 |
| commit | fa0223a75946ad3aec2596dac34d88f2dcca7baa (patch) | |
| tree | 83a9de28154eee826825b5d1e8ca5271a7dce70d /include/fsl_esdhc_imx.h | |
| parent | c1412cbb17b2f6cd6c2301d7102346bec3a260d6 (diff) | |
| download | u-boot-fa0223a75946ad3aec2596dac34d88f2dcca7baa.tar.xz | |
mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP
Import HS400 support for iMX7ULP B0 from the Linux kernel:
2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP")
According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET
before any setting of STROBE_DLL_CTRL register.
USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL)
for slave sel value. If this register bits value is 0, it needs
256 ref_clk cycles to update slave sel value. IC suggest to set
bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave
sel value. This will short the lock time of slave.
i.MX7ULP B0 will need more time to lock the REF and SLV, so change
to add 5us delay.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Diffstat (limited to 'include/fsl_esdhc_imx.h')
| -rw-r--r-- | include/fsl_esdhc_imx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index 45ed635a77..12e9163382 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -194,6 +194,7 @@ #define ESDHC_STROBE_DLL_CTRL_RESET BIT(1) #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 +#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) #define ESDHC_STROBE_DLL_STATUS 0x74 #define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1) |