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| author | Laurentiu Tudor <laurentiu.tudor@nxp.com> | 2019-02-26 14:18:32 +0300 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-03-03 19:31:04 +0300 |
| commit | d8d5fdb7b2ab9154beee2936082bfb65bf4d9209 (patch) | |
| tree | bfb41a059399d83eb579695134b487fedf7f3ea3 /include/fsl_sec.h | |
| parent | 910e8fdaac3896792512451c9d8323de3e86b1c0 (diff) | |
| download | u-boot-d8d5fdb7b2ab9154beee2936082bfb65bf4d9209.tar.xz | |
fsl_sec: fix register layout on Layerscape architectures
On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'include/fsl_sec.h')
| -rw-r--r-- | include/fsl_sec.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 16e3fcb5a1..be08a2b88b 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -121,10 +121,18 @@ typedef struct ccsr_sec { u32 chanum_ls; /* CHA Number Register, LS */ u32 secvid_ms; /* SEC Version ID Register, MS */ u32 secvid_ls; /* SEC Version ID Register, LS */ +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + u8 res9[0x6f020]; +#else u8 res9[0x6020]; +#endif u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + u8 res10[0x8ffd8]; +#else u8 res10[0x8fd8]; +#endif } ccsr_sec_t; #define SEC_CTPR_MS_AXI_LIODN 0x08000000 |