diff options
| author | Suman Anna <s-anna@ti.com> | 2021-09-08 01:16:58 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-09-17 21:47:03 +0300 |
| commit | cfd50dfb729ab2268a5a44eaeea00ffa557919cd (patch) | |
| tree | ddfdeb97acd204dc5ddc0dfbb7b10579b7396a7b /include/k3-clk.h | |
| parent | d3c56e2a823caa1e2d09daccd1b0d8a529d8df69 (diff) | |
| download | u-boot-cfd50dfb729ab2268a5a44eaeea00ffa557919cd.tar.xz | |
clk: ti: k3: Update driver to account for divider flags
The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
turn serve as inputs to other HSDIV output clocks. These clocks use
the actual value to compute the divider clock rate, and need to be
registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
driver and data lacks the infrastructure to pass in divider flags.
Update the driver and data to account for these divider flags.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Diffstat (limited to 'include/k3-clk.h')
| -rw-r--r-- | include/k3-clk.h | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/include/k3-clk.h b/include/k3-clk.h index 0735228579..59c76db86e 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com + * (C) Copyright 2020-2021 Texas Instruments Incorporated - http://www.ti.com * Tero Kristo <t-kristo@ti.com> */ @@ -54,6 +54,7 @@ struct div_data { u32 flags; int shift; int width; + u32 div_flags; }; struct hfosc_data { @@ -105,20 +106,23 @@ struct clk_data { .width = _width, .flags = _flags } \ } -#define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags) \ - { \ - .type = CLK_TYPE_DIV, \ - .clk.div = {.name = _name, .parent = _parent, .reg = _reg, .shift = _shift, .width = _width, .flags = _flags } \ +#define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags, _div_flags) \ + { \ + .type = CLK_TYPE_DIV, \ + .clk.div = { \ + .name = _name, .parent = _parent, .reg = _reg, \ + .shift = _shift, .width = _width, \ + .flags = _flags, .div_flags = _div_flags } \ } -#define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _freq) \ - { \ - .type = CLK_TYPE_DIV, \ - .default_freq = _freq, \ - .clk.div = { \ - .name = _name, .parent = _parent, \ - .reg = _reg, .shift = _shift, \ - .width = _width, .flags = _flags } \ +#define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _div_flags, _freq) \ + { \ + .type = CLK_TYPE_DIV, \ + .default_freq = _freq, \ + .clk.div = { \ + .name = _name, .parent = _parent, .reg = _reg, \ + .shift = _shift, .width = _width, \ + .flags = _flags, .div_flags = _div_flags } \ } #define CLK_PLL(_name, _parent, _reg, _flags) \ |