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| author | Mario Six <mario.six@gdsys.cc> | 2018-08-06 11:23:30 +0300 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2018-09-18 09:01:18 +0300 |
| commit | e40615565d68465284b3c6a5fc4147f662824a88 (patch) | |
| tree | 8654ebc0d143eed7c33e69db4b2a584e44359570 /include/mpc83xx.h | |
| parent | 0f1caa98807901a2d94cdda891d8380c4dc69063 (diff) | |
| download | u-boot-e40615565d68465284b3c6a5fc4147f662824a88.tar.xz | |
ram: Add driver for MPC83xx
Add a RAM driver for the MPC83xx architecture.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include/mpc83xx.h')
| -rw-r--r-- | include/mpc83xx.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h index e1e50ab6b5..a4c5bd3837 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1110,6 +1110,8 @@ #define CSBNDS_EA 0x000000FF #define CSBNDS_EA_SHIFT 24 +#ifndef CONFIG_MPC83XX_SDRAM + /* * CSn_CONFIG - Chip Select Configuration Register */ @@ -1407,6 +1409,8 @@ #define ECC_ERROR_MAN_SBEC (0xff000000 >> 24) #define ECC_ERROR_MAN_SBEC_SHIFT 0 +#endif /* !CONFIG_MPC83XX_SDRAM */ + /* * CONFIG_ADDRESS - PCI Config Address Register */ @@ -1510,6 +1514,7 @@ */ #define PMCCR1_POWER_OFF 0x00000020 +#ifndef CONFIG_RAM /* * DDRCDR - DDR Control Driver Register */ @@ -1531,6 +1536,7 @@ #define DDRCDR_DDR_CFG 0x00040000 #define DDRCDR_M_ODR 0x00000002 #define DDRCDR_Q_DRN 0x00000001 +#endif /* !CONFIG_RAM */ /* * PCIE Bridge Register |