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authorSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>2019-04-09 22:02:03 +0300
committerMarek Vasut <marex@denx.de>2019-04-25 01:00:49 +0300
commit798baf7ca35f81eab27dc49289745b19bde3cd39 (patch)
tree97c336cbebc1b951e04f89be886fd96dea01aa4c /include
parentac1ec53e26d68493f01b0adf44e45a995da640df (diff)
downloadu-boot-798baf7ca35f81eab27dc49289745b19bde3cd39.tar.xz
arm: socfpga: fix comment about SPL memory layout
The comment about SPL memory layout for socfpga gen5 is outdated: the initial malloc memory is now at the end of the SRAM, gd is below it (see board_init_f_alloc_reserve). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'include')
-rw-r--r--include/configs/socfpga_common.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index f9e2cdc1b3..32ee7426b6 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -236,9 +236,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
*
* 0xFFFF_0000 ...... Start of SRAM
* 0xFFFF_xxxx ...... Top of stack (grows down)
- * 0xFFFF_yyyy ...... Malloc area
- * 0xFFFF_zzzz ...... Global Data
- * 0xFFFF_FF00 ...... End of SRAM
+ * 0xFFFF_yyyy ...... Global Data
+ * 0xFFFF_zzzz ...... Malloc area
+ * 0xFFFF_FFFF ...... End of SRAM
*
* SRAM Memory layout for Arria 10:
* 0xFFE0_0000 ...... Start of SRAM (bottom)