Merge branch 'next-socfpga' of https://github.com/tienfong/uboot_mainline

3 files changed, 117 insertions, 2 deletions

diff --git a/include/configs/socfpga_n5x_socdk.h b/include/configs/socfpga_n5x_socdk.h
new file mode 100644
index 0000000000..c295e91e3d
--- /dev/null
+++ b/include/configs/socfpga_n5x_socdk.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_N5X_H__
+#define __CONFIG_SOCFGPA_N5X_H__
+
+#include <configs/socfpga_soc64_common.h>
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"bootfile=" CONFIG_BOOTFILE "\0" \
+	"fdt_addr=1100000\0" \
+	"fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"booti ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootfile};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"bootm ${loadaddr}\0" \
+	"mmcfitload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootfile}\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS";" \
+		"booti ${loadaddr} - ${fdt_addr}\0" \
+	"linux_qspi_enable=if sf probe; then " \
+		"echo Enabling QSPI at Linux DTB...;" \
+		"fdt addr ${fdt_addr}; fdt resize;" \
+		"fdt set /soc/spi@ff8d2000 status okay;" \
+		"if fdt set /soc/clocks/qspi-clk clock-frequency" \
+		" ${qspi_clock}; then" \
+		" else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+		" ${qspi_clock}; fi; fi\0" \
+	"scriptaddr=0x02100000\0" \
+	"scriptfile=u-boot.scr\0" \
+	"fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+		   "then source ${scriptaddr}; fi\0"
+
+#endif	/* __CONFIG_SOCFGPA_N5X_H__ */
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 38fd775b5b..a0453e562f 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -7,7 +7,7 @@
 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
 
-#include <asm/arch/base_addr_s10.h>
+#include <asm/arch/base_addr_soc64.h>
 #include <asm/arch/handoff_soc64.h>
 #include <linux/stringify.h>
 
@@ -20,7 +20,6 @@
 #define CONFIG_REMAKE_ELF
 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
 #define CPU_RELEASE_ADDR		0xFFD12210
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
 /*
  * U-Boot console configurations
diff --git a/include/dt-bindings/clock/n5x-clock.h b/include/dt-bindings/clock/n5x-clock.h
new file mode 100644
index 0000000000..a56e4dba77
--- /dev/null
+++ b/include/dt-bindings/clock/n5x-clock.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021, Intel Corporation
+ */
+
+#ifndef __N5X_CLOCK_H
+#define __N5X_CLOCK_H
+
+/* fixed rate clocks */
+#define N5X_OSC1					0
+#define N5X_CB_INTOSC_HS_DIV2_CLK		1
+#define N5X_CB_INTOSC_LS_CLK			2
+#define N5X_L4_SYS_FREE_CLK			3
+#define N5X_F2S_FREE_CLK				4
+
+/* PLL clocks */
+#define N5X_MAIN_PLL_CLK				5
+#define N5X_MAIN_PLL_C0_CLK			6
+#define N5X_MAIN_PLL_C1_CLK			7
+#define N5X_MAIN_PLL_C2_CLK			8
+#define N5X_MAIN_PLL_C3_CLK			9
+#define N5X_PERIPH_PLL_CLK			10
+#define N5X_PERIPH_PLL_C0_CLK			11
+#define N5X_PERIPH_PLL_C1_CLK			12
+#define N5X_PERIPH_PLL_C2_CLK			13
+#define N5X_PERIPH_PLL_C3_CLK			14
+#define N5X_MPU_FREE_CLK				15
+#define N5X_MPU_CCU_CLK				16
+#define N5X_BOOT_CLK				17
+
+/* fixed factor clocks */
+#define N5X_L3_MAIN_FREE_CLK			18
+#define N5X_NOC_FREE_CLK				19
+#define N5X_S2F_USR0_CLK				20
+#define N5X_NOC_CLK				21
+#define N5X_EMAC_A_FREE_CLK			22
+#define N5X_EMAC_B_FREE_CLK			23
+#define N5X_EMAC_PTP_FREE_CLK			24
+#define N5X_GPIO_DB_FREE_CLK			25
+#define N5X_SDMMC_FREE_CLK			26
+#define N5X_S2F_USER0_FREE_CLK			27
+#define N5X_S2F_USER1_FREE_CLK			28
+#define N5X_PSI_REF_FREE_CLK			29
+
+/* Gate clocks */
+#define N5X_MPU_CLK				30
+#define N5X_MPU_PERIPH_CLK			31
+#define N5X_L4_MAIN_CLK				32
+#define N5X_L4_MP_CLK				33
+#define N5X_L4_SP_CLK				34
+#define N5X_CS_AT_CLK				35
+#define N5X_CS_TRACE_CLK				36
+#define N5X_CS_PDBG_CLK				37
+#define N5X_CS_TIMER_CLK				38
+#define N5X_S2F_USER0_CLK			39
+#define N5X_EMAC0_CLK				40
+#define N5X_EMAC1_CLK				41
+#define N5X_EMAC2_CLK				42
+#define N5X_EMAC_PTP_CLK				43
+#define N5X_GPIO_DB_CLK				44
+#define N5X_NAND_CLK				45
+#define N5X_PSI_REF_CLK				46
+#define N5X_S2F_USER1_CLK			47
+#define N5X_SDMMC_CLK				48
+#define N5X_SPI_M_CLK				49
+#define N5X_USB_CLK				50
+#define N5X_NAND_X_CLK				51
+#define N5X_NAND_ECC_CLK				52
+#define N5X_NUM_CLKS				53
+
+#endif	/* __N5X_CLOCK_H */