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authorPali Rohár <pali@kernel.org>2021-07-31 15:22:53 +0300
committerStefan Roese <sr@denx.de>2021-08-11 09:42:26 +0300
commit2ddf554b8648d892efc5733e7486cec5e93dc269 (patch)
tree657272fc09b52c05a4fa88d1d569690adee12eaf /include
parent29795302b942e6ee41c9d95f7e6e29f57d108d42 (diff)
downloadu-boot-2ddf554b8648d892efc5733e7486cec5e93dc269.tar.xz
arm: mvebu: a37x: Detect CONFIG_SYS_TCLK from SAR register
Bit 20 in SAR register specifies if TCLK is running at 200 MHz or 166 MHz. Use this information instead of manual configuration in every board file. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
-rw-r--r--include/configs/db-88f6720.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h
index 410a40af3e..18f4707e6b 100644
--- a/include/configs/db-88f6720.h
+++ b/include/configs/db-88f6720.h
@@ -15,7 +15,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
-#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
/* I2C */
#define CONFIG_SYS_I2C_LEGACY