Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell

- Various improvements to Keymile boards - mostly DT conversation
  (Pascal & Holger)
- Removal of now unsupported Keymile boards (Pascal & Holger)
- Small MVEBU PCI fix (Marek)
- Turris Omnia defconfig update (Marek)
- Misc Allied Telesis defconfig updates (Chris)

8 files changed, 392 insertions, 595 deletions

diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index a83782e1cf..8433d8e568 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_KEYMILE_H
 #define __CONFIG_KEYMILE_H
 
-#undef	CONFIG_WATCHDOG		/* disable platform specific watchdog */
-
 /*
  * Miscellaneous configurable options
  */
@@ -27,12 +25,6 @@
 #define CONFIG_LOADS_ECHO
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 
-
-/* Support the IVM EEprom */
-#define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
-#define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
-#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN	0x100
-
 /*
  * BOOTP options
  */
diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
index 455e5236de..c06143c68b 100644
--- a/include/configs/km/km-mpc83xx.h
+++ b/include/configs/km/km-mpc83xx.h
@@ -3,8 +3,6 @@
  */
 #define BOOTFLASH_START	0xF0000000
 
-#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
-
 /*
  * DDR Setup
  */
@@ -89,8 +87,6 @@
 		{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 		{1, {I2C_NULL_HOP} } }
 
-#define CONFIG_KM_IVM_BUS		2	/* I2C2 (Mux-Port 1)*/
-
 #if defined(CONFIG_CMD_NAND)
 #define CONFIG_NAND_KMETER1
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h
index 16b11d82a2..20b596f541 100644
--- a/include/configs/km/km-powerpc.h
+++ b/include/configs/km/km-powerpc.h
@@ -11,9 +11,6 @@
 
 #define CONFIG_JFFS2_CMDLINE
 
-/* standard km ethernet_present for piggy */
-#define CONFIG_KM_COMMON_ETH_INIT
-
 /* EEprom support 24C08, 24C16, 24C64 */
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3  /* 8 Byte write page */
@@ -45,20 +42,10 @@
 
 /* size of rootfs in RAM */
 #define CONFIG_KM_ROOTFSSIZE	0x0
-/* pseudo-non volatile RAM [hex] */
-#define CONFIG_KM_PNVRAM	0x80000
-/* physical RAM MTD size [hex] */
-#define CONFIG_KM_PHRAM		0x100000
-/* resereved pram area at the end of memroy [hex] */
-#define CONFIG_KM_RESERVED_PRAM	0x0
 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
  * is not valid yet, which is the case for when u-boot copies itself to RAM */
 #define CONFIG_PRAM		((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
 
-#define CONFIG_KM_CRAMFS_ADDR	0xC00000
-#define CONFIG_KM_KERNEL_ADDR	0x400000	/* 7680Kbytes */
-#define CONFIG_KM_FDT_ADDR	0xB80000	/* 512Kbytes */
-
 /* architecture specific default bootargs */
 #define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
 
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index a381a98470..d12d18770d 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -32,8 +32,6 @@
 /* include common defines/options for all Keymile boards */
 #include "keymile-common.h"
 
-/* SPI NOR Flash default params, used by sf commands */
-
 /* Reserve 4 MB for malloc */
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 
@@ -43,15 +41,6 @@
 #define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
 #define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
 
-/* pseudo-non volatile RAM [hex] */
-#define CONFIG_KM_PNVRAM	0x80000
-/* physical RAM MTD size [hex] */
-#define CONFIG_KM_PHRAM		0x17F000
-
-#define CONFIG_KM_CRAMFS_ADDR	0x2400000
-#define CONFIG_KM_KERNEL_ADDR	0x2000000	/* 3098KBytes */
-#define CONFIG_KM_FDT_ADDR	0x23E0000	/*  128KBytes */
-
 /* architecture specific default bootargs */
 #define CONFIG_KM_DEF_BOOT_ARGS_CPU					\
 		"bootcountaddr=${bootcountaddr} ${mtdparts}"		\
@@ -72,26 +61,10 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
 
 /*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2		KW_UART1_BASE
-
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-/*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_BOOTMAPSZ	(8 << 20)	/* Initial Memmap for Linux */
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
 #define CONFIG_INITRD_TAG		/* enable INITRD tag */
 #define CONFIG_SETUP_MEMORY_TAGS	/* enable memory tag */
@@ -101,30 +74,17 @@
  */
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 
-#define BOOTFLASH_START		0x0
-
-/* Kirkwood has two serial IF */
-#if (CONFIG_CONS_INDEX == 2)
-#define CONFIG_KM_CONSOLE_TTY	"ttyS1"
-#else
-#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
-#endif
-
 /*
  * Other required minimal configurations
  */
 #define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
 
 /*
  * Ethernet Driver configuration
  */
-#define CONFIG_NETCONSOLE	/* include NetConsole support   */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer autoneg timeout */
 #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
 #define CONFIG_PHY_BASE_ADR	0
-#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
-#define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */
 
 /*
  * I2C related stuff
@@ -238,19 +198,9 @@ int get_scl(void);
 	"arch=arm\0"							\
 	""
 
-#if !defined(CONFIG_MTD_NOR_FLASH)
-#undef	CONFIG_JFFS2_CMDLINE
-#endif
-
 /* additions for new relocation code, must be added to all boards */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* Do early setups now in board_init_f() */
 
-/*
- * resereved pram area at the end of memroy [hex]
- * 8Mbytes for switch + 4Kbytes for bootcount
- */
-#define CONFIG_KM_RESERVED_PRAM 0x801000
 /* address for the bootcount (taken from end of RAM) */
 #define BOOTCOUNT_ADDR          (CONFIG_KM_RESERVED_PRAM)
 
@@ -259,6 +209,4 @@ int get_scl(void);
 #define CONFIG_POST_SKIP_ENV_FLAGS
 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
 
-/* we do the whole PCIe FPGA config stuff here */
-
 #endif /* _CONFIG_KM_ARM_H */
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
deleted file mode 100644
index 3eff38017f..0000000000
--- a/include/configs/km/kmp204x-common.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- */
-
-#ifndef _CONFIG_KMP204X_H
-#define _CONFIG_KMP204X_H
-
-#define CONFIG_KM_DEF_NETDEV	"netdev=eth0\0"
-
-/* an additionnal option is required for UBI as subpage access is
- * supported in u-boot */
-#define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
-
-#define CONFIG_NAND_ECC_BCH
-
-/* common KM defines */
-#include "keymile-common.h"
-
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
-#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
-
-#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1			/* PCIE controller 1 */
-#define CONFIG_PCIE3			/* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_DPAA_RMAN		/* RMan */
-
-/* Environment in SPI Flash */
-#define CONFIG_ENV_OFFSET               0x100000	/* 1MB for u-boot */
-#define CONFIG_ENV_SIZE			0x004000	/* 16K env */
-#define CONFIG_ENV_SECT_SIZE            0x010000
-#define CONFIG_ENV_OFFSET_REDUND	0x110000
-#define CONFIG_ENV_TOTAL_SIZE		0x020000
-
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
-#define CONFIG_BTB			/* toggle branch predition */
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
-
-#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS	/* POST memory regions test */
-
-/*
- *  Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
-		CONFIG_RAMBOOT_TEXT_BASE)
-#define CONFIG_SYS_L3_SIZE		(1024 << 10)
-#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
-
-#define CONFIG_SYS_DCSRBAR		0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-
-#define CONFIG_SYS_SPD_BUS_NUM	0
-#define SPD_EEPROM_ADDRESS	0x54
-#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
-
-/******************************************************************************
- * (PRAM usage)
- * ... -------------------------------------------------------
- * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
- * ... |<------------------- pram -------------------------->|
- * ... -------------------------------------------------------
- * @END_OF_RAM:
- * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
- * @CONFIG_KM_PHRAM: address for /var
- * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
- * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
- */
-
-/* size of rootfs in RAM */
-#define CONFIG_KM_ROOTFSSIZE	0x0
-/* pseudo-non volatile RAM [hex] */
-#define CONFIG_KM_PNVRAM	0x80000
-/* physical RAM MTD size [hex] */
-#define CONFIG_KM_PHRAM		0x100000
-/* reserved pram area at the end of memory [hex]
- * u-boot reserves some memory for the MP boot page */
-#define CONFIG_KM_RESERVED_PRAM	0x1000
-/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
- * is not valid yet, which is the case for when u-boot copies itself to RAM */
-#define CONFIG_PRAM		((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
-
-#define CONFIG_KM_CRAMFS_ADDR	0x2000000
-#define CONFIG_KM_KERNEL_ADDR	0x1000000	/* max kernel size 15.5Mbytes */
-#define CONFIG_KM_FDT_ADDR	0x1F80000	/* max dtb    size  0.5Mbytes */
-
-/*
- * Local Bus Definitions
- */
-
-/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
-#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_8 | LCRR_EADC_2)
-
-/* Nand Flash */
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE		0xffa00000
-#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
-
-#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-			       | BR_PS_8	       /* Port Size = 8 bit */ \
-			       | BR_MS_FCM	       /* MSEL = FCM */ \
-			       | BR_V)		       /* valid */
-
-#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB	      /* length 256K */ \
-			       | OR_FCM_BCTLD	/* LBCTL not ass */	\
-			       | OR_FCM_SCY_1	/* 1 clk wait cycle */	\
-			       | OR_FCM_RST	/* 1 clk read setup */	\
-			       | OR_FCM_PGS	/* Large page size */	\
-			       | OR_FCM_CST)	/* 0.25 command setup */
-
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* QRIO FPGA */
-#define CONFIG_SYS_QRIO_BASE		0xfb000000
-#define CONFIG_SYS_QRIO_BASE_PHYS	0xffb000000ull
-
-#define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
-				| BR_PS_8	/* Port Size 8 bits */ \
-				| BR_DECC_OFF	/* no error corr */ \
-				| BR_MS_GPCM	/* MSEL = GPCM */ \
-				| BR_V)		/* valid */
-
-#define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB	/* length 64K */ \
-				| OR_GPCM_BCTLD /* no LCTL assert */ \
-				| OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
-				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
-				| OR_GPCM_TRLX /* relaxed tmgs */ \
-				| OR_GPCM_EAD) /* extra bus clk cycles */
-
-#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
-#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
-
-#define CONFIG_MISC_INIT_F
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
-
-#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
-
-/* I2C */
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED		100000 /* deblocking */
-#define CONFIG_SYS_NUM_I2C_BUSES	3
-#define CONFIG_SYS_I2C_MAX_HOPS		1
-#define CONFIG_SYS_I2C_FSL		/* Use FSL I2C driver */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
-#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
-					{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
-					{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
-				}
-#ifndef __ASSEMBLY__
-void set_sda(int state);
-void set_scl(int state);
-int get_sda(void);
-int get_scl(void);
-#endif
-
-#define CONFIG_KM_IVM_BUS		1	/* I2C1 (Mux-Port 1)*/
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8010000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-
-/* Qman/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS	10
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS	10
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-/* Default address of microcode for the Linux Fman driver
- * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
- * ucode is stored after env, so we got 0x120000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR	0x120000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
-#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-
-#define CONFIG_PHYLIB_10G
-
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x11
-#define CONFIG_SYS_TBIPA_VALUE	8
-#define CONFIG_ETHPRIME		"FM1@DTSEC5"
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO		/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
-
-/*
- * Hardware Watchdog
- */
-#define CONFIG_WATCHDOG			/* enable CPU watchdog */
-#define CONFIG_WATCHDOG_PRESC 34	/* wdog prescaler 2^(64-34) (~10min) */
-#define CONFIG_WATCHDOG_RC WRC_CHIP	/* reset chip on watchdog event */
-
-
-/*
- * additionnal command line configuration.
- */
-
-/* we don't need flash support */
-#undef CONFIG_JFFS2_CMDLINE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-#define __USB_PHY_TYPE	utmi
-#define CONFIG_USB_EHCI_FSL
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
-#define CONFIG_KM_DEF_ENV "km-common=empty\0"
-#endif
-
-/* architecture specific default bootargs */
-#define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
-
-/* FIXME: FDT_ADDR is unspecified */
-#define CONFIG_KM_DEF_ENV_CPU						\
-	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
-	"cramfsloadfdt="						\
-		"cramfsload ${fdt_addr_r} "				\
-		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
-	"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"		\
-	"u-boot="CONFIG_HOSTNAME "/u-boot.pbl\0"		\
-	"update="							\
-		"sf probe 0;sf erase 0 +${filesize};"			\
-		"sf write ${load_addr_r} 0 ${filesize};\0"		\
-	"set_fdthigh=true\0"						\
-	"checkfdt=true\0"						\
-	""
-
-#define CONFIG_HW_ENV_SETTINGS						\
-	"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"			\
-	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
-	"usb_dr_mode=host\0"
-
-#define CONFIG_KM_NEW_ENV						\
-	"newenv=sf probe 0;"						\
-		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
-		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
-
-/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
-#ifndef CONFIG_KM_DEF_ARCH
-#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_KM_DEF_ENV						\
-	CONFIG_KM_DEF_ARCH						\
-	CONFIG_KM_NEW_ENV						\
-	CONFIG_HW_ENV_SETTINGS						\
-	"EEprom_ivm=pca9547:70:9\0"					\
-	""
-
-#endif /* _CONFIG_KMP204X_H */
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index e7b12d0dca..6fce83cfcd 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -24,13 +24,10 @@
 #if defined(CONFIG_KM_KIRKWOOD)
 #define CONFIG_HOSTNAME			"km_kirkwood"
 #define CONFIG_KM_DISABLE_PCIE
-#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 
 /* KM_KIRKWOOD_PCI */
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
 #define CONFIG_HOSTNAME			"km_kirkwood_pci"
-#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
-#define CONFIG_KM_FPGA_CONFIG
 #define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
 #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
 
@@ -40,11 +37,9 @@
 #undef CONFIG_SYS_KWD_CONFIG
 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
 #define CONFIG_KM_DISABLE_PCIE
-#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 
 /* KM_NUSA / KM_SUGP1 */
 #elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
-#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 
 # if defined(CONFIG_KM_NUSA)
 #define CONFIG_HOSTNAME			"kmnusa"
@@ -55,48 +50,27 @@
 
 #undef CONFIG_SYS_KWD_CONFIG
 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
-#define CONFIG_KM_ENV_IS_IN_SPI_NOR
-#define CONFIG_KM_FPGA_CONFIG
-#define CONFIG_KM_PIGGY4_88E6352
-#define CONFIG_MV88E6352_SWITCH
-#define CONFIG_KM_MVEXTSW_ADDR		0x10
 
 /* KM_MGCOGE3UN */
 #elif defined(CONFIG_KM_MGCOGE3UN)
 #define CONFIG_HOSTNAME			"mgcoge3un"
-#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 #undef CONFIG_SYS_KWD_CONFIG
 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
 #define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
-#define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
 #define CONFIG_KM_DISABLE_PCIE
-#define CONFIG_KM_PIGGY4_88E6061
 
 /* KMCOGE5UN */
 #elif defined(CONFIG_KM_COGE5UN)
-#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 #undef	CONFIG_SYS_KWD_CONFIG
 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
-#define CONFIG_KM_ENV_IS_IN_SPI_NOR
-#define CONFIG_PIGGY_MAC_ADRESS_OFFSET	3
 #define CONFIG_HOSTNAME			"kmcoge5un"
 #define CONFIG_KM_DISABLE_PCIE
-#define CONFIG_KM_PIGGY4_88E6352
-
-/* KM_PORTL2 */
-#elif defined(CONFIG_KM_PORTL2)
-#define CONFIG_HOSTNAME			"portl2"
-#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
-#define CONFIG_KM_PIGGY4_88E6061
 
 /* KM_SUV31 */
 #elif defined(CONFIG_KM_SUV31)
-#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 #define CONFIG_HOSTNAME			"kmsuv31"
 #undef CONFIG_SYS_KWD_CONFIG
 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
-#define CONFIG_KM_ENV_IS_IN_SPI_NOR
-#define CONFIG_KM_FPGA_CONFIG
 #define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
 #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
 #else
@@ -166,7 +140,7 @@
 	MVGBE_SET_MII_SPEED_TO_100)
 #endif
 
-#ifdef CONFIG_KM_DISABLE_PCI
+#ifdef CONFIG_KM_DISABLE_PCIE
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
 #endif
 
diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h
index c50026d71e..75480a8a58 100644
--- a/include/configs/kmp204x.h
+++ b/include/configs/kmp204x.h
@@ -7,13 +7,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* KMLION1 */
-#if defined(CONFIG_KMLION1)
-#define CONFIG_HOSTNAME		"kmlion1"
-#define CONFIG_KM_BOARD_NAME	"kmlion1"
-
-/* KMCOGE4 */
-#elif defined(CONFIG_KMCOGE4)
+#if defined(CONFIG_KMCOGE4)
 #define CONFIG_HOSTNAME		"kmcoge4"
 #define CONFIG_KM_BOARD_NAME	"kmcoge4"
 
@@ -23,31 +17,407 @@
 
 #define CONFIG_KMP204X
 
-#include "km/kmp204x-common.h"
+#define CONFIG_KM_DEF_NETDEV	"netdev=eth0\0"
+
+/* an additionnal option is required for UBI as subpage access is
+ * supported in u-boot
+ */
+#define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
+
+#define CONFIG_NAND_ECC_BCH
+
+/* common KM defines */
+#include "km/keymile-common.h"
+
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+
+/* Environment in SPI Flash */
+#define CONFIG_ENV_OFFSET               0x100000	/* 1MB for u-boot */
+#define CONFIG_ENV_SIZE			0x004000	/* 16K env */
+#define CONFIG_ENV_SECT_SIZE            0x010000
+#define CONFIG_ENV_OFFSET_REDUND	0x110000
+#define CONFIG_ENV_TOTAL_SIZE		0x020000
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS	/* POST memory regions test */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
+		CONFIG_RAMBOOT_TEXT_BASE)
+#define CONFIG_SYS_L3_SIZE		(1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
-#if defined(CONFIG_KMLION1)
-/* App1 Local bus */
-#define CONFIG_SYS_LBAPP1_BASE		0xD0000000
-#define CONFIG_SYS_LBAPP1_BASE_PHYS	0xFD0000000ull
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
-#define CONFIG_SYS_LBAPP1_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP1_BASE_PHYS) \
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x54
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE	0x0
+/* pseudo-non volatile RAM [hex] */
+#define CONFIG_KM_PNVRAM	0x80000
+/* physical RAM MTD size [hex] */
+#define CONFIG_KM_PHRAM		0x100000
+/* reserved pram area at the end of memory [hex]
+ * u-boot reserves some memory for the MP boot page
+ */
+#define CONFIG_KM_RESERVED_PRAM	0x1000
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM
+ */
+#define CONFIG_PRAM		((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
+
+#define CONFIG_KM_CRAMFS_ADDR	0x2000000
+#define CONFIG_KM_KERNEL_ADDR	0x1000000	/* max kernel size 15.5Mbytes */
+#define CONFIG_KM_FDT_ADDR	0x1F80000	/* max dtb    size  0.5Mbytes */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
+#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_8 | LCRR_EADC_2)
+
+/* Nand Flash */
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+
+#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+
+#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB	      /* length 256K */ \
+			       | OR_FCM_BCTLD	/* LBCTL not ass */	\
+			       | OR_FCM_SCY_1	/* 1 clk wait cycle */	\
+			       | OR_FCM_RST	/* 1 clk read setup */	\
+			       | OR_FCM_PGS	/* Large page size */	\
+			       | OR_FCM_CST)	/* 0.25 command setup */
+
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* QRIO FPGA */
+#define CONFIG_SYS_QRIO_BASE		0xfb000000
+#define CONFIG_SYS_QRIO_BASE_PHYS	0xffb000000ull
+
+#define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
 				| BR_PS_8	/* Port Size 8 bits */ \
 				| BR_DECC_OFF	/* no error corr */ \
 				| BR_MS_GPCM	/* MSEL = GPCM */ \
 				| BR_V)		/* valid */
 
-#define CONFIG_SYS_LBAPP1_OR_PRELIM (OR_AM_256MB	/* length 256MB */ \
-				| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
-				| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
+#define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB	/* length 64K */ \
+				| OR_GPCM_BCTLD /* no LCTL assert */ \
+				| OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
 				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
 				| OR_GPCM_TRLX /* relaxed tmgs */ \
 				| OR_GPCM_EAD) /* extra bus clk cycles */
-/* Local bus app1 Base Address */
-#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_LBAPP1_BR_PRELIM
-/* Local bus app1 Options */
-#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_LBAPP1_OR_PRELIM
+
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
+
+#define CONFIG_MISC_INIT_F
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0) / 2)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR + 0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR + 0x11D600)
+
+#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
+
+/* I2C */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED		100000 /* deblocking */
+#define CONFIG_SYS_NUM_I2C_BUSES	3
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_FSL		/* Use FSL I2C driver */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
+				}
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
 #endif
 
+#define CONFIG_KM_IVM_BUS		1	/* I2C1 (Mux-Port 1)*/
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver
+ * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
+ * ucode is stored after env, so we got 0x120000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0x120000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#define CONFIG_PHYLIB_10G
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x11
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_ETHPRIME		"FM1@DTSEC5"
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Hardware Watchdog
+ */
+#define CONFIG_WATCHDOG			/* enable CPU watchdog */
+#define CONFIG_WATCHDOG_PRESC 34	/* wdog prescaler 2^(64-34) (~10min) */
+#define CONFIG_WATCHDOG_RC WRC_CHIP	/* reset chip on watchdog event */
+
+/*
+ * additionnal command line configuration.
+ */
+
+/* we don't need flash support */
+#undef CONFIG_JFFS2_CMDLINE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+#define __USB_PHY_TYPE	utmi
+#define CONFIG_USB_EHCI_FSL
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
+
+/* FIXME: FDT_ADDR is unspecified */
+#define CONFIG_KM_DEF_ENV_CPU						\
+	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
+	"cramfsloadfdt="						\
+		"cramfsload ${fdt_addr_r} "				\
+		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
+	"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"		\
+	"u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0"		\
+	"update="							\
+		"sf probe 0;sf erase 0 +${filesize};"			\
+		"sf write ${load_addr_r} 0 ${filesize};\0"		\
+	"set_fdthigh=true\0"						\
+	"checkfdt=true\0"						\
+	""
+
+#define CONFIG_HW_ENV_SETTINGS						\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"			\
+	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
+	"usb_dr_mode=host\0"
+
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=sf probe 0;"						\
+		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
+		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
+
+/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_KM_DEF_ARCH						\
+	CONFIG_KM_NEW_ENV						\
+	CONFIG_HW_ENV_SETTINGS						\
+	"EEprom_ivm=pca9547:70:9\0"					\
+	""
+
 /* App2 Local bus */
 #define CONFIG_SYS_LBAPP2_BASE		0xE0000000
 #define CONFIG_SYS_LBAPP2_BASE_PHYS	0xFE0000000ull
diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h
deleted file mode 100644
index 6e5d50700c..0000000000
--- a/include/configs/kmvect1.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *                    Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- *                    Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- *                    Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_HOSTNAME		"kmvect1"
-#define CONFIG_KM_BOARD_NAME   "kmvect1"
-/* at end of uboot partition, before env */
-#define CONFIG_SYS_QE_FW_ADDR   0xF00B0000
-
-/* include common defines/options for all Keymile boards */
-#include "km/keymile-common.h"
-#include "km/km-powerpc.h"
-#include "km/km-mpc83xx.h"
-#include "km/km-mpc8309.h"
-
-#define CONFIG_SYS_MAMR	(MxMR_GPL_x4DIS | \
-			 0x0000c000 | \
-			 MxMR_WLFx_2X)
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_MV88E6352_SWITCH
-#define CONFIG_KM_MVEXTSW_ADDR		0x10
-
-/* ethernet port connected to simple switch 88e6122 (UEC0) */
-#define CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM		0	/* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
-#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
-
-#define CONFIG_FIXED_PHY		0xFFFFFFFF
-#define CONFIG_SYS_FIXED_PHY_ADDR	0x1E	/* unused address */
-#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
-		{devnum, speed, duplex}
-#define CONFIG_SYS_FIXED_PHY_PORTS \
-		CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
-
-#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR	CONFIG_SYS_FIXED_PHY_ADDR
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
-
-#endif /* __CONFIG_H */