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| author | Tom Rini <trini@konsulko.com> | 2022-07-11 17:18:13 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-07-11 21:58:57 +0300 |
| commit | 36b661dc919da318c163a45f4a220d2e3d9db608 (patch) | |
| tree | 268703050f58280feb3287d48eb0cedc974730e1 /include | |
| parent | e092e3250270a1016c877da7bdd9384f14b1321e (diff) | |
| parent | 05a4859637567b13219efd6f1707fb236648b1b7 (diff) | |
| download | u-boot-36b661dc919da318c163a45f4a220d2e3d9db608.tar.xz | |
Merge branch 'next'
Diffstat (limited to 'include')
575 files changed, 1171 insertions, 10055 deletions
diff --git a/include/SA-1100.h b/include/SA-1100.h deleted file mode 100644 index 7589df238a..0000000000 --- a/include/SA-1100.h +++ /dev/null @@ -1,2833 +0,0 @@ -/* - * FILE SA-1100.h - * - * Version 1.2 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date January 1998 (April 1997) - * System StrongARM SA-1100 - * Language C or ARM Assembly - * Purpose Definition of constants related to the StrongARM - * SA-1100 microprocessor (Advanced RISC Machine (ARM) - * architecture version 4). This file is based on the - * StrongARM SA-1100 data sheet version 2.2. - * - * Language-specific definitions are selected by the - * macro "LANGUAGE", which should be defined as either - * "C" (default) or "Assembly". - */ - - -#ifndef LANGUAGE -# ifdef __ASSEMBLY__ -# define LANGUAGE Assembly -# else -# define LANGUAGE C -# endif -#endif - -#ifndef io_p2v -#define io_p2v(PhAdd) (PhAdd) -#endif - -#include <asm/arch-sa1100/bitfield.h> - -#define C 0 -#define Assembly 1 - - -#if LANGUAGE == C -typedef unsigned short Word16 ; -typedef unsigned int Word32 ; -typedef Word32 Word ; -typedef Word Quad [4] ; -typedef void *Address ; -typedef void (*ExcpHndlr) (void) ; -#endif /* LANGUAGE == C */ - - -/* - * Memory - */ - -#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */ - -#define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */ -#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */ - /* [byte] */ -#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */ - /* [byte] */ -#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */ - /* [byte] */ -#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */ - /* [byte] */ - -#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */ -#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */ -#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */ -#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */ -#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */ - -#define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */ - -#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ - (0x00000000 + (Nb)*StMemBnkSp) -#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */ -#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */ -#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */ -#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */ - -#if LANGUAGE == C -typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; -#define StMemBnk /* Static Memory Bank [0..3] */ \ - ((StMemBnkType *) io_p2v (_StMemBnk (0))) -#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */ -#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */ -#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */ -#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */ -#endif /* LANGUAGE == C */ - -#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ - (0xC0000000 + (Nb)*DRAMBnkSp) -#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */ -#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */ -#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */ -#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */ - -#if LANGUAGE == C -typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ; -#define DRAMBnk /* DRAM Bank [0..3] */ \ - ((DRAMBnkType *) io_p2v (_DRAMBnk (0))) -#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */ -#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */ -#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */ -#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */ -#endif /* LANGUAGE == C */ - -#define _ZeroMem 0xE0000000 /* Zero Memory bank */ - -#if LANGUAGE == C -typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; -#define ZeroMem /* Zero Memory bank */ \ - (*((ZeroMemType *) io_p2v (_ZeroMem))) -#endif /* LANGUAGE == C */ - - -/* - * Personal Computer Memory Card International Association (PCMCIA) sockets - */ - -#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ -#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ -#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ -#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ -#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ - -#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ -#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ -#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ -#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ - -#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ -#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ -#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ -#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ - -#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ - (0x20000000 + (Nb)*PCMCIASp) -#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ -#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ - (_PCMCIA (Nb) + 2*PCMCIAPrtSp) -#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ - (_PCMCIA (Nb) + 3*PCMCIAPrtSp) - -#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ -#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ -#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ -#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ - -#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ -#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ -#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ -#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ - -#if LANGUAGE == C - -typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ; -typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; - -#define PCMCIA0 /* PCMCIA 0 */ \ - (*((PCMCIAType *) io_p2v (_PCMCIA0))) -#define PCMCIA0IO /* PCMCIA 0 I/O */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO))) -#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr))) -#define PCMCIA0Mem /* PCMCIA 0 Memory */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem))) - -#define PCMCIA1 /* PCMCIA 1 */ \ - (*((PCMCIAType *) io_p2v (_PCMCIA1))) -#define PCMCIA1IO /* PCMCIA 1 I/O */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO))) -#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr))) -#define PCMCIA1Mem /* PCMCIA 1 Memory */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem))) - -#endif /* LANGUAGE == C */ - - -/* - * Universal Serial Bus (USB) Device Controller (UDC) control registers - * - * Registers - * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control Register (read/write). - * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Address Register (read/write). - * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Output Maximum Packet size register - * (read/write). - * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Input Maximum Packet size register - * (read/write). - * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 0 - * (read/write). - * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 1 - * (output, read/write). - * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 2 - * (input, read/write). - * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Data register end-point 0 - * (read/write). - * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Write Count register end-point 0 - * (read). - * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Data Register (read/write). - * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Status Register (read/write). - */ - -#define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */ -#define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */ -#define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */ - /* Packet size reg. */ -#define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */ - /* Packet size reg. */ -#define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 0 */ -#define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 1 (output) */ -#define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 2 (input) */ -#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */ - /* end-point 0 */ -#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */ - /* reg. end-point 0 */ -#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */ -#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */ - -#if LANGUAGE == C -#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCCR))) -#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCAR))) -#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \ - /* Packet size reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCOMP))) -#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \ - /* Packet size reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCIMP))) -#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 0 */ \ - (*((volatile Word *) io_p2v (_Ser0UDCCS0))) -#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 1 (output) */ \ - (*((volatile Word *) io_p2v (_Ser0UDCCS1))) -#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 2 (input) */ \ - (*((volatile Word *) io_p2v (_Ser0UDCCS2))) -#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \ - /* end-point 0 */ \ - (*((volatile Word *) io_p2v (_Ser0UDCD0))) -#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \ - /* reg. end-point 0 */ \ - (*((volatile Word *) io_p2v (_Ser0UDCWC))) -#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCDR))) -#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCSR))) -#endif /* LANGUAGE == C */ - -#define UDCCR_UDD 0x00000001 /* UDC Disable */ -#define UDCCR_UDA 0x00000002 /* UDC Active (read) */ -#define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ -#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ - /* (disable) */ -#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ - /* (disable) */ -#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ - /* (disable) */ -#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ - /* (disable) */ -#define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ -#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ - -#define UDCAR_ADD Fld (7, 0) /* function ADDress */ - -#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ - /* [byte] */ -#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ - /* [1..256 byte] */ \ - (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) - -#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ - /* [byte] */ -#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ - /* [1..256 byte] */ \ - (((Size) - 1) << FShft (UDCIMP_INMAXP)) - -#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ -#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ -#define UDCCS0_SST 0x00000004 /* Sent STall */ -#define UDCCS0_FST 0x00000008 /* Force STall */ -#define UDCCS0_DE 0x00000010 /* Data End */ -#define UDCCS0_SE 0x00000020 /* Setup End (read) */ -#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ - /* (write) */ -#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ - -#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ - /* Service request (read) */ -#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ -#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ -#define UDCCS1_SST 0x00000008 /* Sent STall */ -#define UDCCS1_FST 0x00000010 /* Force STall */ -#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ - -#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ - /* Service request (read) */ -#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ -#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ -#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ -#define UDCCS2_SST 0x00000010 /* Sent STall */ -#define UDCCS2_FST 0x00000020 /* Force STall */ - -#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ - -#define UDCWC_WC Fld (4, 0) /* Write Count */ - -#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ - -#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ -#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ -#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ -#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ -#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ -#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ - - -/* - * Universal Asynchronous Receiver/Transmitter (UART) control registers - * - * Registers - * Ser1UTCR0 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser1UTCR1 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser1UTCR2 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser1UTCR3 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser1UTDR Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser1UTSR0 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser1UTSR1 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). - * - * Ser2UTCR0 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser2UTCR1 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser2UTCR2 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser2UTCR3 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser2UTCR4 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 4 - * (read/write). - * Ser2UTDR Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser2UTSR0 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser2UTSR1 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). - * - * Ser3UTCR0 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser3UTCR1 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser3UTCR2 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser3UTCR3 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser3UTDR Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser3UTSR0 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser3UTSR1 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). - * - * Clocks - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fua, Tua Frequency, period of the UART communication. - */ - -#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ - (0x80010000 + ((Nb) - 1)*0x00020000) -#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ - (0x80010004 + ((Nb) - 1)*0x00020000) -#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ - (0x80010008 + ((Nb) - 1)*0x00020000) -#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ - (0x8001000C + ((Nb) - 1)*0x00020000) -#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ - (0x80010010 + ((Nb) - 1)*0x00020000) -#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ - (0x80010014 + ((Nb) - 1)*0x00020000) -#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ - (0x8001001C + ((Nb) - 1)*0x00020000) -#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ - (0x80010020 + ((Nb) - 1)*0x00020000) - -#define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ -#define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ -#define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ -#define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ -#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ -#define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ -#define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ - -#define _Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ -#define _Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ -#define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ -#define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ -#define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ -#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ -#define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ -#define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ - -#define _Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ -#define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ -#define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ -#define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ -#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ -#define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ -#define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ - -#if LANGUAGE == C - -#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser1UTCR0))) -#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser1UTCR1))) -#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser1UTCR2))) -#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_Ser1UTCR3))) -#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser1UTDR))) -#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser1UTSR0))) -#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser1UTSR1))) - -#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR0))) -#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR1))) -#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR2))) -#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR3))) -#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR4))) -#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser2UTDR))) -#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser2UTSR0))) -#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser2UTSR1))) - -#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser3UTCR0))) -#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser3UTCR1))) -#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser3UTCR2))) -#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_Ser3UTCR3))) -#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser3UTDR))) -#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser3UTSR0))) -#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser3UTSR1))) - -#elif LANGUAGE == Assembly -#define Ser1UTCR0 ( io_p2v (_Ser1UTCR0)) -#define Ser1UTCR1 ( io_p2v (_Ser1UTCR1)) -#define Ser1UTCR2 ( io_p2v (_Ser1UTCR2)) -#define Ser1UTCR3 ( io_p2v (_Ser1UTCR3)) -#define Ser1UTDR ( io_p2v (_Ser1UTDR)) -#define Ser1UTSR0 ( io_p2v (_Ser1UTSR0)) -#define Ser1UTSR1 ( io_p2v (_Ser1UTSR1)) - -#define Ser2UTCR0 ( io_p2v (_Ser2UTCR0)) -#define Ser2UTCR1 ( io_p2v (_Ser2UTCR1)) -#define Ser2UTCR2 ( io_p2v (_Ser2UTCR2)) -#define Ser2UTCR3 ( io_p2v (_Ser2UTCR3)) -#define Ser2UTCR4 ( io_p2v (_Ser2UTCR4)) -#define Ser2UTDR ( io_p2v (_Ser2UTDR)) -#define Ser2UTSR0 ( io_p2v (_Ser2UTSR0)) -#define Ser2UTSR1 ( io_p2v (_Ser2UTSR1)) - -#define Ser3UTCR0 ( io_p2v (_Ser3UTCR0)) -#define Ser3UTCR1 ( io_p2v (_Ser3UTCR1)) -#define Ser3UTCR2 ( io_p2v (_Ser3UTCR2)) -#define Ser3UTCR3 ( io_p2v (_Ser3UTCR3)) -#define Ser3UTDR ( io_p2v (_Ser3UTDR)) -#define Ser3UTSR0 ( io_p2v (_Ser3UTSR0)) -#define Ser3UTSR1 ( io_p2v (_Ser3UTSR1)) - -#endif /* LANGUAGE == C */ - -#define UTCR0_PE 0x00000001 /* Parity Enable */ -#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ -#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ -#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ -#define UTCR0_SBS 0x00000004 /* Stop Bit Select */ -#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ -#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ -#define UTCR0_DSS 0x00000008 /* Data Size Select */ -#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ -#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ -#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ - /* (ser. port 1: GPIO [18], */ - /* ser. port 3: GPIO [20]) */ -#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ -#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ -#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ -#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ -#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ -#define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ -#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ - (UTCR0_1StpBit + UTCR0_8BitData) - -#define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ -#define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ - /* fua = fxtl/(16*(BRD[11:0] + 1)) */ - /* Tua = 16*(BRD [11:0] + 1)*Txtl */ -#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ - FShft (UTCR1_BRD)) -#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ - FShft (UTCR2_BRD)) - /* fua = fxtl/(16*Floor (Div/16)) */ - /* Tua = 16*Floor (Div/16)*Txtl */ -#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ - FShft (UTCR1_BRD)) -#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ - FShft (UTCR2_BRD)) - /* fua = fxtl/(16*Ceil (Div/16)) */ - /* Tua = 16*Ceil (Div/16)*Txtl */ - -#define UTCR3_RXE 0x00000001 /* Receive Enable */ -#define UTCR3_TXE 0x00000002 /* Transmit Enable */ -#define UTCR3_BRK 0x00000004 /* BReaK mode */ -#define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Interrupt Enable */ -#define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define UTCR3_LBM 0x00000020 /* Look-Back Mode */ -#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ - /* TIE, LBM can be set or cleared) */ \ - (UTCR3_RXE + UTCR3_TXE) - -#define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ - /* (HP-SIR) modulation Enable */ -#define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ -#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ -#define UTCR4_LPM 0x00000002 /* Low-Power Mode */ -#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ -#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ - -#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ -#define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ -#define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ -#define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ -#endif /* 0 */ - -#define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ -#define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Service request (read) */ -#define UTSR0_RID 0x00000004 /* Receiver IDle */ -#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ -#define UTSR0_REB 0x00000010 /* Receive End of Break */ -#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ - -#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ -#define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ -#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ -#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ -#define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ -#define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ - - -/* - * Synchronous Data Link Controller (SDLC) control registers - * - * Registers - * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 0 (read/write). - * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 1 (read/write). - * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 2 (read/write). - * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 3 (read/write). - * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 4 (read/write). - * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) - * Data Register (read/write). - * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) - * Status Register 0 (read/write). - * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) - * Status Register 1 (read/write). - * - * Clocks - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fsd, Tsd Frequency, period of the SDLC communication. - */ - -#define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */ -#define _Ser1SDCR1 0x80020064 /* Ser. port 1 SDLC Control Reg. 1 */ -#define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */ -#define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */ -#define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */ -#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */ -#define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */ -#define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */ - -#if LANGUAGE == C -#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR0))) -#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR1))) -#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR2))) -#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR3))) -#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR4))) -#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser1SDDR))) -#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser1SDSR0))) -#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser1SDSR1))) -#endif /* LANGUAGE == C */ - -#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ -#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ -#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ -#define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ -#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ -#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ -#define SDCR0_LBM 0x00000004 /* Look-Back Mode */ -#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ -#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ -#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ -#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ -#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ - /* (GPIO [16]) */ -#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ -#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ -#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ -#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ -#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ -#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ -#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ -#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ - -#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ - /* (GPIO [17]) */ -#define SDCR1_TXE 0x00000002 /* Transmit Enable */ -#define SDCR1_RXE 0x00000004 /* Receive Enable */ -#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Interrupt Enable */ -#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define SDCR1_AME 0x00000020 /* Address Match Enable */ -#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ -#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ -#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ -#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ - -#define SDCR2_AMV Fld (8, 0) /* Address Match Value */ - -#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ -#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ - /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ - /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ -#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ - FShft (SDCR3_BRD)) -#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ - FShft (SDCR4_BRD)) - /* fsd = fxtl/(16*Floor (Div/16)) */ - /* Tsd = 16*Floor (Div/16)*Txtl */ -#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ - FShft (SDCR3_BRD)) -#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ - FShft (SDCR4_BRD)) - /* fsd = fxtl/(16*Ceil (Div/16)) */ - /* Tsd = 16*Ceil (Div/16)*Txtl */ - -#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ -#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ -#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ -#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ -#endif /* 0 */ - -#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ -#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ -#define SDSR0_RAB 0x00000004 /* Receive ABort */ -#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ -#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Service request (read) */ - -#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ -#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ -#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ -#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ -#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ -#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ -#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ -#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ - - -/* - * High-Speed Serial to Parallel controller (HSSP) control registers - * - * Registers - * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 0 (read/write). - * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 1 (read/write). - * Ser2HSDR Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Data Register (read/write). - * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Status Register 0 (read/write). - * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Status Register 1 (read). - * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 2 (read/write). - * [The HSCR2 register is only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] - */ - -#define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */ -#define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */ -#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */ -#define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */ -#define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */ -#define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */ - -#if LANGUAGE == C -#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser2HSCR0))) -#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser2HSCR1))) -#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser2HSDR))) -#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser2HSSR0))) -#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser2HSSR1))) -#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser2HSCR2))) -#endif /* LANGUAGE == C */ - -#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ -#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ -#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ -#define HSCR0_LBM 0x00000002 /* Look-Back Mode */ -#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ -#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ -#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ -#define HSCR0_TXE 0x00000008 /* Transmit Enable */ -#define HSCR0_RXE 0x00000010 /* Receive Enable */ -#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ - /* more Interrupt Enable */ -#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define HSCR0_AME 0x00000080 /* Address Match Enable */ - -#define HSCR1_AMV Fld (8, 0) /* Address Match Value */ - -#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ -#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ -#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ -#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ -#endif /* 0 */ - -#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ -#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ -#define HSSR0_RAB 0x00000004 /* Receive ABort */ -#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ -#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ - /* more Service request (read) */ -#define HSSR0_FRE 0x00000020 /* receive FRaming Error */ - -#define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ -#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ -#define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ -#define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ -#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ -#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ -#define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ - -#define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ -#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ - /* (inverted) */ -#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ - /* (non-inverted) */ -#define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ -#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ - /* (inverted) */ -#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ - /* (non-inverted) */ - - -/* - * Multi-media Communications Port (MCP) control registers - * - * Registers - * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) - * Control Register 0 (read/write). - * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 0 (audio, read/write). - * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 1 (telecom, read/write). - * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 2 (CODEC registers, read/write). - * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) - * Status Register (read/write). - * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) - * Control Register 1 (read/write). - * [The MCCR1 register is only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] - * - * Clocks - * fmc, Tmc Frequency, period of the MCP communication (10 MHz, - * 12 MHz, or GPIO [21]). - * faud, Taud Frequency, period of the audio sampling. - * ftcm, Ttcm Frequency, period of the telecom sampling. - */ - -#define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */ -#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */ - /* (audio) */ -#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */ - /* (telecom) */ -#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */ - /* (CODEC reg.) */ -#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */ -#define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */ - -#if LANGUAGE == C -#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser4MCCR0))) -#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \ - /* (audio) */ \ - (*((volatile Word *) io_p2v (_Ser4MCDR0))) -#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \ - /* (telecom) */ \ - (*((volatile Word *) io_p2v (_Ser4MCDR1))) -#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \ - /* (CODEC reg.) */ \ - (*((volatile Word *) io_p2v (_Ser4MCDR2))) -#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \ - (*((volatile Word *) io_p2v (_Ser4MCSR))) -#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser4MCCR1))) -#endif /* LANGUAGE == C */ - -#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ - /* [6..127] */ - /* faud = fmc/(32*ASD) */ - /* Taud = 32*ASD*Tmc */ -#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ - /* [192..4064] */ \ - ((Div)/32 << FShft (MCCR0_ASD)) - /* faud = fmc/(32*Floor (Div/32)) */ - /* Taud = 32*Floor (Div/32)*Tmc */ -#define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ - (((Div) + 31)/32 << FShft (MCCR0_ASD)) - /* faud = fmc/(32*Ceil (Div/32)) */ - /* Taud = 32*Ceil (Div/32)*Tmc */ -#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ - /* Divisor/32 [16..127] */ - /* ftcm = fmc/(32*TSD) */ - /* Ttcm = 32*TSD*Tmc */ -#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ - /* [512..4064] */ \ - ((Div)/32 << FShft (MCCR0_TSD)) - /* ftcm = fmc/(32*Floor (Div/32)) */ - /* Ttcm = 32*Floor (Div/32)*Tmc */ -#define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ - (((Div) + 31)/32 << FShft (MCCR0_TSD)) - /* ftcm = fmc/(32*Ceil (Div/32)) */ - /* Ttcm = 32*Ceil (Div/32)*Tmc */ -#define MCCR0_MCE 0x00010000 /* MCP Enable */ -#define MCCR0_ECS 0x00020000 /* External Clock Select */ -#define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ -#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ -#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ - /* sampling/storing Mode */ -#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ -#define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ -#define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ - /* or less interrupt Enable */ -#define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ - /* or more interrupt Enable */ -#define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ - /* or less interrupt Enable */ -#define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ - /* more interrupt Enable */ -#define MCCR0_LBM 0x00800000 /* Look-Back Mode */ -#define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ -#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ - (((Div) - 1) << FShft (MCCR0_ECP)) - -#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ - /* FIFOs */ - -#define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ - /* FIFOs */ - - /* receive/transmit CODEC reg. */ - /* FIFOs: */ -#define MCDR2_DATA Fld (16, 0) /* reg. DATA */ -#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ -#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ -#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ -#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ - -#define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ - /* or less Service request (read) */ -#define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ - /* more Service request (read) */ -#define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ - /* or less Service request (read) */ -#define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ - /* or more Service request (read) */ -#define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ -#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ -#define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ -#define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ -#define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ - /* (read) */ -#define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ - /* (read) */ -#define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ - /* (read) */ -#define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ - /* (read) */ -#define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ - /* (read) */ -#define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ - /* (read) */ -#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ -#define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ - -#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ -#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ - /* (11.981 MHz) */ -#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ - /* (9.585 MHz) */ - - -/* - * Synchronous Serial Port (SSP) control registers - * - * Registers - * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control - * Register 0 (read/write). - * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control - * Register 1 (read/write). - * [Bits SPO and SP are only implemented in versions 2.0 - * (rev. = 8) and higher of the StrongARM SA-1100.] - * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data - * Register (read/write). - * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status - * Register (read/write). - * - * Clocks - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fss, Tss Frequency, period of the SSP communication. - */ - -#define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */ -#define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */ -#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */ -#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */ - -#if LANGUAGE == C -#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser4SSCR0))) -#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser4SSCR1))) -#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser4SSDR))) -#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \ - (*((volatile Word *) io_p2v (_Ser4SSSR))) -#endif /* LANGUAGE == C */ - -#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ -#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ - (((Size) - 1) << FShft (SSCR0_DSS)) -#define SSCR0_FRF Fld (2, 4) /* FRame Format */ -#define SSCR0_Motorola /* Motorola Serial Peripheral */ \ - /* Interface (SPI) format */ \ - (0 << FShft (SSCR0_FRF)) -#define SSCR0_TI /* Texas Instruments Synchronous */ \ - /* Serial format */ \ - (1 << FShft (SSCR0_FRF)) -#define SSCR0_National /* National Microwire format */ \ - (2 << FShft (SSCR0_FRF)) -#define SSCR0_SSE 0x00000080 /* SSP Enable */ -#define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ - /* fss = fxtl/(2*(SCR + 1)) */ - /* Tss = 2*(SCR + 1)*Txtl */ -#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ - (((Div) - 2)/2 << FShft (SSCR0_SCR)) - /* fss = fxtl/(2*Floor (Div/2)) */ - /* Tss = 2*Floor (Div/2)*Txtl */ -#define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ - (((Div) - 1)/2 << FShft (SSCR0_SCR)) - /* fss = fxtl/(2*Ceil (Div/2)) */ - /* Tss = 2*Ceil (Div/2)*Txtl */ - -#define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ - /* Interrupt Enable */ -#define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define SSCR1_LBM 0x00000004 /* Look-Back Mode */ -#define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ -#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ -#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ -#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ -#define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ - /* after frame (SFRM, 1st edge) */ -#define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ - /* after frame (SFRM, 1st edge) */ -#define SSCR1_ECS 0x00000020 /* External Clock Select */ -#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ -#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ - -#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ - -#define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ -#define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ -#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ -#define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ -#define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ - /* Service request (read) */ -#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ - - -/* - * Operating System (OS) timer control registers - * - * Registers - * OSMR0 Operating System (OS) timer Match Register 0 - * (read/write). - * OSMR1 Operating System (OS) timer Match Register 1 - * (read/write). - * OSMR2 Operating System (OS) timer Match Register 2 - * (read/write). - * OSMR3 Operating System (OS) timer Match Register 3 - * (read/write). - * OSCR Operating System (OS) timer Counter Register - * (read/write). - * OSSR Operating System (OS) timer Status Register - * (read/write). - * OWER Operating System (OS) timer Watch-dog Enable Register - * (read/write). - * OIER Operating System (OS) timer Interrupt Enable Register - * (read/write). - */ - -#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ - (0x90000000 + (Nb)*4) -#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */ -#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */ -#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */ -#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */ -#define _OSCR 0x90000010 /* OS timer Counter Reg. */ -#define _OSSR 0x90000014 /* OS timer Status Reg. */ -#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */ -#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */ - -#if LANGUAGE == C -#define OSMR /* OS timer Match Reg. [0..3] */ \ - ((volatile Word *) io_p2v (_OSMR (0))) -#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */ -#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */ -#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */ -#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */ -#define OSCR /* OS timer Counter Reg. */ \ - (*((volatile Word *) io_p2v (_OSCR))) -#define OSSR /* OS timer Status Reg. */ \ - (*((volatile Word *) io_p2v (_OSSR))) -#define OWER /* OS timer Watch-dog Enable Reg. */ \ - (*((volatile Word *) io_p2v (_OWER))) -#define OIER /* OS timer Interrupt Enable Reg. */ \ - (*((volatile Word *) io_p2v (_OIER))) -#endif /* LANGUAGE == C */ - -#define OSSR_M(Nb) /* Match detected [0..3] */ \ - (0x00000001 << (Nb)) -#define OSSR_M0 OSSR_M (0) /* Match detected 0 */ -#define OSSR_M1 OSSR_M (1) /* Match detected 1 */ -#define OSSR_M2 OSSR_M (2) /* Match detected 2 */ -#define OSSR_M3 OSSR_M (3) /* Match detected 3 */ - -#define OWER_WME 0x00000001 /* Watch-dog Match Enable */ - /* (set only) */ - -#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ - (0x00000001 << (Nb)) -#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ -#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ -#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ -#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ - - -/* - * Real-Time Clock (RTC) control registers - * - * Registers - * RTAR Real-Time Clock (RTC) Alarm Register (read/write). - * RCNR Real-Time Clock (RTC) CouNt Register (read/write). - * RTTR Real-Time Clock (RTC) Trim Register (read/write). - * RTSR Real-Time Clock (RTC) Status Register (read/write). - * - * Clocks - * frtx, Trtx Frequency, period of the real-time clock crystal - * (32.768 kHz nominal). - * frtc, Trtc Frequency, period of the real-time clock counter - * (1 Hz nominal). - */ - -#define _RTAR 0x90010000 /* RTC Alarm Reg. */ -#define _RCNR 0x90010004 /* RTC CouNt Reg. */ -#define _RTTR 0x90010008 /* RTC Trim Reg. */ -#define _RTSR 0x90010010 /* RTC Status Reg. */ - -#if LANGUAGE == C -#define RTAR /* RTC Alarm Reg. */ \ - (*((volatile Word *) io_p2v (_RTAR))) -#define RCNR /* RTC CouNt Reg. */ \ - (*((volatile Word *) io_p2v (_RCNR))) -#define RTTR /* RTC Trim Reg. */ \ - (*((volatile Word *) io_p2v (_RTTR))) -#define RTSR /* RTC Status Reg. */ \ - (*((volatile Word *) io_p2v (_RTSR))) -#endif /* LANGUAGE == C */ - -#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ -#define RTTR_D Fld (10, 16) /* trim Delete count */ - /* frtc = (1023*(C + 1) - D)*frtx/ */ - /* (1023*(C + 1)^2) */ - /* Trtc = (1023*(C + 1)^2)*Trtx/ */ - /* (1023*(C + 1) - D) */ - -#define RTSR_AL 0x00000001 /* ALarm detected */ -#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ -#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ -#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ - - -/* - * Power Manager (PM) control registers - * - * Registers - * PMCR Power Manager (PM) Control Register (read/write). - * PSSR Power Manager (PM) Sleep Status Register (read/write). - * PSPR Power Manager (PM) Scratch-Pad Register (read/write). - * PWER Power Manager (PM) Wake-up Enable Register - * (read/write). - * PCFR Power Manager (PM) general ConFiguration Register - * (read/write). - * PPCR Power Manager (PM) Phase-Locked Loop (PLL) - * Configuration Register (read/write). - * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) - * Sleep state Register (read/write, see GPIO pins). - * POSR Power Manager (PM) Oscillator Status Register (read). - * - * Clocks - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - */ - -#define _PMCR 0x90020000 /* PM Control Reg. */ -#define _PSSR 0x90020004 /* PM Sleep Status Reg. */ -#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */ -#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */ -#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */ -#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */ -#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */ -#define _POSR 0x9002001C /* PM Oscillator Status Reg. */ - -#if LANGUAGE == C -#define PMCR /* PM Control Reg. */ \ - (*((volatile Word *) io_p2v (_PMCR))) -#define PSSR /* PM Sleep Status Reg. */ \ - (*((volatile Word *) io_p2v (_PSSR))) -#define PSPR /* PM Scratch-Pad Reg. */ \ - (*((volatile Word *) io_p2v (_PSPR))) -#define PWER /* PM Wake-up Enable Reg. */ \ - (*((volatile Word *) io_p2v (_PWER))) -#define PCFR /* PM general ConFiguration Reg. */ \ - (*((volatile Word *) io_p2v (_PCFR))) -#define PPCR /* PM PLL Configuration Reg. */ \ - (*((volatile Word *) io_p2v (_PPCR))) -#define PGSR /* PM GPIO Sleep state Reg. */ \ - (*((volatile Word *) io_p2v (_PGSR))) -#define POSR /* PM Oscillator Status Reg. */ \ - (*((volatile Word *) io_p2v (_POSR))) - -#elif LANGUAGE == Assembly -#define PMCR (io_p2v (_PMCR)) -#define PSSR (io_p2v (_PSSR)) -#define PSPR (io_p2v (_PSPR)) -#define PWER (io_p2v (_PWER)) -#define PCFR (io_p2v (_PCFR)) -#define PPCR (io_p2v (_PPCR)) -#define PGSR (io_p2v (_PGSR)) -#define POSR (io_p2v (_POSR)) - -#endif /* LANGUAGE == C */ - -#define PMCR_SF 0x00000001 /* Sleep Force (set only) */ - -#define PSSR_SS 0x00000001 /* Software Sleep */ -#define PSSR_BFS 0x00000002 /* Battery Fault Status */ - /* (BATT_FAULT) */ -#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ -#define PSSR_DH 0x00000008 /* DRAM control Hold */ -#define PSSR_PH 0x00000010 /* Peripheral control Hold */ - -#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ -#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ -#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ -#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ -#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ -#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ -#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ -#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ -#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ -#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ -#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ -#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ -#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ -#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ -#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ -#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ -#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ -#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ -#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ -#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ -#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ -#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ -#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ -#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ -#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ -#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ -#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ -#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ -#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ -#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ - -#define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ -#define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ -#define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ -#define PCFR_FP 0x00000002 /* Float PCMCIA pins */ -#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ -#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ -#define PCFR_FS 0x00000004 /* Float Static memory pins */ -#define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ -#define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ -#define PCFR_FO 0x00000008 /* Force RTC oscillator */ - /* (32.768 kHz) enable On */ - -#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ -#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ - (0x00 << FShft (PPCR_CCF)) -#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ - (0x01 << FShft (PPCR_CCF)) -#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ - (0x02 << FShft (PPCR_CCF)) -#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ - (0x03 << FShft (PPCR_CCF)) -#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ - (0x04 << FShft (PPCR_CCF)) -#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ - (0x05 << FShft (PPCR_CCF)) -#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ - (0x06 << FShft (PPCR_CCF)) -#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ - (0x07 << FShft (PPCR_CCF)) -#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ - (0x08 << FShft (PPCR_CCF)) -#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ - (0x09 << FShft (PPCR_CCF)) -#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ - (0x0A << FShft (PPCR_CCF)) -#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ - (0x0B << FShft (PPCR_CCF)) -#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ - (0x0C << FShft (PPCR_CCF)) -#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ - (0x0D << FShft (PPCR_CCF)) -#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ - (0x0E << FShft (PPCR_CCF)) -#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ - (0x0F << FShft (PPCR_CCF)) - /* 3.6864 MHz crystal (fxtl): */ -#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ -#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ -#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ -#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ -#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ -#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ -#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ -#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ -#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ -#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ -#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ -#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ -#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ -#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ -#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ -#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ - /* 3.5795 MHz crystal (fxtl): */ -#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ -#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ -#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ -#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ -#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ -#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ -#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ -#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ -#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ -#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ -#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ -#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ -#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ -#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ -#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ -#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ - -#define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ - - -/* - * Reset Controller (RC) control registers - * - * Registers - * RSRR Reset Controller (RC) Software Reset Register - * (read/write). - * RCSR Reset Controller (RC) Status Register (read/write). - */ - -#define _RSRR 0x90030000 /* RC Software Reset Reg. */ -#define _RCSR 0x90030004 /* RC Status Reg. */ - -#if LANGUAGE == C -#define RSRR /* RC Software Reset Reg. */ \ - (*((volatile Word *) io_p2v (_RSRR))) -#define RCSR /* RC Status Reg. */ \ - (*((volatile Word *) io_p2v (_RCSR))) -#endif /* LANGUAGE == C */ - -#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ - -#define RCSR_HWR 0x00000001 /* HardWare Reset */ -#define RCSR_SWR 0x00000002 /* SoftWare Reset */ -#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ -#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ - - -/* - * Test unit control registers - * - * Registers - * TUCR Test Unit Control Register (read/write). - */ - -#define _TUCR 0x90030008 /* Test Unit Control Reg. */ - -#if LANGUAGE == C -#define TUCR /* Test Unit Control Reg. */ \ - (*((volatile Word *) io_p2v (_TUCR))) -#endif /* LANGUAGE == C */ - -#define TUCR_TIC 0x00000040 /* TIC mode */ -#define TUCR_TTST 0x00000080 /* Trim TeST mode */ -#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ - /* Check */ -#define TUCR_PMD 0x00000200 /* Power Management Disable */ -#define TUCR_MR 0x00000400 /* Memory Request mode */ -#define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ -#define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ - /* grant (MBGNT) on GPIO [22:21] */ -#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ -#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ -#define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ -#define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ -#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ -#define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ -#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ - (0 << FShft (TUCR_TSEL)) -#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ - (1 << FShft (TUCR_TSEL)) -#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ - (2 << FShft (TUCR_TSEL)) -#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ - (3 << FShft (TUCR_TSEL)) -#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ - /* Clocks on GPIO [26:27] */ \ - (4 << FShft (TUCR_TSEL)) -#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ - /* (Alternative) */ \ - (5 << FShft (TUCR_TSEL)) -#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ - (6 << FShft (TUCR_TSEL)) -#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ - (7 << FShft (TUCR_TSEL)) - - -/* - * General-Purpose Input/Output (GPIO) control registers - * - * Registers - * GPLR General-Purpose Input/Output (GPIO) Pin Level - * Register (read). - * GPDR General-Purpose Input/Output (GPIO) Pin Direction - * Register (read/write). - * GPSR General-Purpose Input/Output (GPIO) Pin output Set - * Register (write). - * GPCR General-Purpose Input/Output (GPIO) Pin output Clear - * Register (write). - * GRER General-Purpose Input/Output (GPIO) Rising-Edge - * detect Register (read/write). - * GFER General-Purpose Input/Output (GPIO) Falling-Edge - * detect Register (read/write). - * GEDR General-Purpose Input/Output (GPIO) Edge Detect - * status Register (read/write). - * GAFR General-Purpose Input/Output (GPIO) Alternate - * Function Register (read/write). - * - * Clock - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - */ - -#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */ -#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */ -#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */ -#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */ -#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */ -#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */ -#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */ -#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */ - -#if LANGUAGE == C -#define GPLR /* GPIO Pin Level Reg. */ \ - (*((volatile Word *) io_p2v (_GPLR))) -#define GPDR /* GPIO Pin Direction Reg. */ \ - (*((volatile Word *) io_p2v (_GPDR))) -#define GPSR /* GPIO Pin output Set Reg. */ \ - (*((volatile Word *) io_p2v (_GPSR))) -#define GPCR /* GPIO Pin output Clear Reg. */ \ - (*((volatile Word *) io_p2v (_GPCR))) -#define GRER /* GPIO Rising-Edge detect Reg. */ \ - (*((volatile Word *) io_p2v (_GRER))) -#define GFER /* GPIO Falling-Edge detect Reg. */ \ - (*((volatile Word *) io_p2v (_GFER))) -#define GEDR /* GPIO Edge Detect status Reg. */ \ - (*((volatile Word *) io_p2v (_GEDR))) -#define GAFR /* GPIO Alternate Function Reg. */ \ - (*((volatile Word *) io_p2v (_GAFR))) -#elif LANGUAGE == Assembly - -#define GPLR (io_p2v (_GPLR)) -#define GPDR (io_p2v (_GPDR)) -#define GPSR (io_p2v (_GPSR)) -#define GPCR (io_p2v (_GPCR)) -#define GRER (io_p2v (_GRER)) -#define GFER (io_p2v (_GFER)) -#define GEDR (io_p2v (_GEDR)) -#define GAFR (io_p2v (_GAFR)) - -#endif /* LANGUAGE == C */ - -#define GPIO_MIN (0) -#define GPIO_MAX (27) - -#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ - (0x00000001 << (Nb)) -#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ -#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ -#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ -#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ -#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ -#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ -#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ -#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ -#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ -#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ -#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ -#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ -#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ -#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ -#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ -#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ -#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ -#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ -#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ -#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ -#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ -#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ -#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ -#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ -#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ -#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ -#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ -#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ - -#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ - GPIO_GPIO ((Nb) - 6) -#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ -#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ -#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ -#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ -#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ -#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ -#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ -#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ - /* ser. port 4: */ -#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ -#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ -#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ -#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ - /* ser. port 1: */ -#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ -#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ -#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ -#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ -#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ - /* ser. port 4: */ -#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ - /* ser. port 3: */ -#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ - /* ser. port 4: */ -#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ - /* test controller: */ -#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ -#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ -#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ -#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ -#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ -#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ -#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ -#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ - -#define GPDR_In 0 /* Input */ -#define GPDR_Out 1 /* Output */ - - -/* - * Interrupt Controller (IC) control registers - * - * Registers - * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) - * Pending register (read). - * ICMR Interrupt Controller (IC) Mask Register (read/write). - * ICLR Interrupt Controller (IC) Level Register (read/write). - * ICCR Interrupt Controller (IC) Control Register - * (read/write). - * [The ICCR register is only implemented in versions 2.0 - * (rev. = 8) and higher of the StrongARM SA-1100.] - * ICFP Interrupt Controller (IC) Fast Interrupt reQuest - * (FIQ) Pending register (read). - * ICPR Interrupt Controller (IC) Pending Register (read). - * [The ICPR register is active low (inverted) in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it is active high (non-inverted) in - * versions 2.0 (rev. = 8) and higher.] - */ - -#define _ICIP 0x90050000 /* IC IRQ Pending reg. */ -#define _ICMR 0x90050004 /* IC Mask Reg. */ -#define _ICLR 0x90050008 /* IC Level Reg. */ -#define _ICCR 0x9005000C /* IC Control Reg. */ -#define _ICFP 0x90050010 /* IC FIQ Pending reg. */ -#define _ICPR 0x90050020 /* IC Pending Reg. */ - -#if LANGUAGE == C -#define ICIP /* IC IRQ Pending reg. */ \ - (*((volatile Word *) io_p2v (_ICIP))) -#define ICMR /* IC Mask Reg. */ \ - (*((volatile Word *) io_p2v (_ICMR))) -#define ICLR /* IC Level Reg. */ \ - (*((volatile Word *) io_p2v (_ICLR))) -#define ICCR /* IC Control Reg. */ \ - (*((volatile Word *) io_p2v (_ICCR))) -#define ICFP /* IC FIQ Pending reg. */ \ - (*((volatile Word *) io_p2v (_ICFP))) -#define ICPR /* IC Pending Reg. */ \ - (*((volatile Word *) io_p2v (_ICPR))) -#endif /* LANGUAGE == C */ - -#define IC_GPIO(Nb) /* GPIO [0..10] */ \ - (0x00000001 << (Nb)) -#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ -#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ -#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ -#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ -#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ -#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ -#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ -#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ -#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ -#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ -#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ -#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ -#define IC_LCD 0x00001000 /* LCD controller */ -#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ -#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ -#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ -#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ -#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ -#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ -#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ -#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ - (0x00100000 << (Nb)) -#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ -#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ -#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ -#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ -#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ -#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ -#define IC_OST(Nb) /* OS Timer match [0..3] */ \ - (0x04000000 << (Nb)) -#define IC_OST0 IC_OST (0) /* OS Timer match 0 */ -#define IC_OST1 IC_OST (1) /* OS Timer match 1 */ -#define IC_OST2 IC_OST (2) /* OS Timer match 2 */ -#define IC_OST3 IC_OST (3) /* OS Timer match 3 */ -#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ -#define IC_RTCAlrm 0x80000000 /* RTC Alarm */ - -#define ICLR_IRQ 0 /* Interrupt ReQuest */ -#define ICLR_FIQ 1 /* Fast Interrupt reQuest */ - -#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ - /* Mask */ -#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ - /* (ICMR ignored) */ -#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ - /* enable (ICMR used) */ - - -/* - * Peripheral Pin Controller (PPC) control registers - * - * Registers - * PPDR Peripheral Pin Controller (PPC) Pin Direction - * Register (read/write). - * PPSR Peripheral Pin Controller (PPC) Pin State Register - * (read/write). - * PPAR Peripheral Pin Controller (PPC) Pin Assignment - * Register (read/write). - * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin - * Direction Register (read/write). - * PPFR Peripheral Pin Controller (PPC) Pin Flag Register - * (read). - */ - -#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */ -#define _PPSR 0x90060004 /* PPC Pin State Reg. */ -#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */ -#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */ - /* Reg. */ -#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */ - -#if LANGUAGE == C -#define PPDR /* PPC Pin Direction Reg. */ \ - (*((volatile Word *) io_p2v (_PPDR))) -#define PPSR /* PPC Pin State Reg. */ \ - (*((volatile Word *) io_p2v (_PPSR))) -#define PPAR /* PPC Pin Assignment Reg. */ \ - (*((volatile Word *) io_p2v (_PPAR))) -#define PSDR /* PPC Sleep-mode pin Direction */ \ - /* Reg. */ \ - (*((volatile Word *) io_p2v (_PSDR))) -#define PPFR /* PPC Pin Flag Reg. */ \ - (*((volatile Word *) io_p2v (_PPFR))) -#endif /* LANGUAGE == C */ - -#define PPC_LDD(Nb) /* LCD Data [0..7] */ \ - (0x00000001 << (Nb)) -#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ -#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ -#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ -#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ -#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ -#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ -#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ -#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ -#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ -#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ -#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ -#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ - /* ser. port 1: */ -#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ -#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ - /* ser. port 2: */ -#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ -#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ - /* ser. port 3: */ -#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ -#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ - /* ser. port 4: */ -#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ -#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ -#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ -#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ - -#define PPDR_In 0 /* Input */ -#define PPDR_Out 1 /* Output */ - - /* ser. port 1: */ -#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ -#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ -#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ - /* ser. port 4: */ -#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ -#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ - /* & SFRM_C */ -#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ - -#define PSDR_OutL 0 /* Output Low in sleep mode */ -#define PSDR_Flt 1 /* Floating (input) in sleep mode */ - -#define PPFR_LCD 0x00000001 /* LCD controller */ -#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ -#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ -#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ -#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ -#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ -#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ -#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ -#define PPFR_PerEn 0 /* Peripheral Enabled */ -#define PPFR_PPCEn 1 /* PPC Enabled */ - - -/* - * Dynamic Random-Access Memory (DRAM) control registers - * - * Registers - * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) - * CoNFiGuration register (read/write). - * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 0 - * (read/write). - * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 1 - * (read/write). - * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 2 - * (read/write). - * - * Clocks - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). - * fcas, Tcas Frequency, period of the DRAM CAS shift registers. - */ - - /* Memory system: */ -#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */ -#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ - (0xA0000004 + (Nb)*4) -#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */ -#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */ -#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */ - -#if LANGUAGE == C - /* Memory system: */ -#define MDCNFG /* DRAM CoNFiGuration reg. */ \ - (*((volatile Word *) io_p2v (_MDCNFG))) -#define MDCAS /* DRAM CAS shift reg. [0..3] */ \ - ((volatile Word *) io_p2v (_MDCAS (0))) -#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */ -#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */ -#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */ - -#elif LANGUAGE == Assembly - -#define MDCNFG (io_p2v(_MDCNFG)) - -#endif /* LANGUAGE == C */ - -/* SA1100 MDCNFG values */ -#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ - (0x00000001 << (Nb)) -#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ -#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ -#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ -#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ -#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ -#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ - (((Add) - 9) << FShft (MDCNFG_DRAC)) -#define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ - /* (fcas = fcpu/2) */ -#define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ -#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ - (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) -#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ - (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) -#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ -#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ - (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) -#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ - (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) -#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ -#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ - ((Tcpu) << FShft (MDCNFG_TDL)) -#define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ - /* [Tmem] */ -#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ - /* [0..262136 Tcpu] */ \ - ((Tcpu)/8 << FShft (MDCNFG_DRI)) - -/* SA1110 MDCNFG values */ -#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ -#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ -#define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ -#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ -#define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ - /* bank 0/1 */ -#define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ -#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ -#define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ - /* deassertion 0/1 */ -#define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ -#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ -#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ -#define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ -#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ -#define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ - /* bank 0/1 */ -#define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ -#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ -#define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ - /* deassertion 0/1 */ -#define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ - - -/* - * Static memory control registers - * - * Registers - * MSC0 Memory system: Static memory Control register 0 - * (read/write). - * MSC1 Memory system: Static memory Control register 1 - * (read/write). - * - * Clocks - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). - */ - - /* Memory system: */ -#define _MSC(Nb) /* Static memory Control reg. */ \ - /* [0..1] */ \ - (0xA0000010 + (Nb)*4) -#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */ -#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */ -#define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */ - -#if LANGUAGE == C - /* Memory system: */ -#define MSC /* Static memory Control reg. */ \ - /* [0..1] */ \ - ((volatile Word *) io_p2v (_MSC (0))) -#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */ -#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */ -#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */ - -#elif LANGUAGE == Assembly - -#define MSC0 io_p2v(0xa0000010) -#define MSC1 io_p2v(0xa0000014) -#define MSC2 io_p2v(0xa000002c) - -#endif /* LANGUAGE == C */ - -#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ - Fld (16, ((Nb) Modulo 2)*16) -#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ -#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ -#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ -#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ - -#define MSC_RT Fld (2, 0) /* ROM/static memory Type */ -#define MSC_NonBrst /* Non-Burst static memory */ \ - (0 << FShft (MSC_RT)) -#define MSC_SRAM /* 32-bit byte-writable SRAM */ \ - (1 << FShft (MSC_RT)) -#define MSC_Brst4 /* Burst-of-4 static memory */ \ - (2 << FShft (MSC_RT)) -#define MSC_Brst8 /* Burst-of-8 static memory */ \ - (3 << FShft (MSC_RT)) -#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ -#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ -#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ -#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ - /* First access - 1(.5) [Tmem] */ -#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ - /* static memory) [3..65 Tcpu] */ \ - ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) -#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) -#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ - /* static memory) [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) -#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) -#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ - /* Next access - 1 [Tmem] */ -#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ - /* static memory) [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) -#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) -#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ - /* static memory) [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) -#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) -#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ - /* time/2 [Tmem] */ -#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ - (((Tcpu)/4) << FShft (MSC_RRR)) -#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ - ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) - - -/* - * Personal Computer Memory Card International Association (PCMCIA) control - * register - * - * Register - * MECR Memory system: Expansion memory bus (PCMCIA) - * Configuration Register (read/write). - * - * Clocks - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). - * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). - */ - - /* Memory system: */ -#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */ - /* Configuration Reg. */ - -#if LANGUAGE == C - /* Memory system: */ -#define MECR /* Expansion memory bus (PCMCIA) */ \ - /* Configuration Reg. */ \ - (*((volatile Word *) io_p2v (_MECR))) -#endif /* LANGUAGE == C */ - -#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ - Fld (15, (Nb)*16) -#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ -#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ - -#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ -#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) -#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) -#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ - /* [Tmem] */ -#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) -#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) -#define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ -#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) -#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) - -/* - * On SA1110 only - */ - -#define _MDREFR 0xA000001C - -#if LANGUAGE == C - /* Memory system: */ -#define MDREFR \ - (*((volatile Word *) io_p2v (_MDREFR))) - -#elif LANGUAGE == Assembly - -#define MDREFR (io_p2v(_MDREFR)) - -#endif /* LANGUAGE == C */ - -#define MDREFR_TRASR Fld (4, 0) -#define MDREFR_DRI Fld (12, 4) -#define MDREFR_E0PIN (1 << 16) -#define MDREFR_K0RUN (1 << 17) -#define MDREFR_K0DB2 (1 << 18) -#define MDREFR_E1PIN (1 << 20) -#define MDREFR_K1RUN (1 << 21) -#define MDREFR_K1DB2 (1 << 22) -#define MDREFR_K2RUN (1 << 25) -#define MDREFR_K2DB2 (1 << 26) -#define MDREFR_EAPD (1 << 28) -#define MDREFR_KAPD (1 << 29) -#define MDREFR_SLFRSH (1 << 31) - - -/* - * Direct Memory Access (DMA) control registers - * - * Registers - * DDAR0 Direct Memory Access (DMA) Device Address Register - * channel 0 (read/write). - * DCSR0 Direct Memory Access (DMA) Control and Status - * Register channel 0 (read/write). - * DBSA0 Direct Memory Access (DMA) Buffer Start address - * register A channel 0 (read/write). - * DBTA0 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 0 (read/write). - * DBSB0 Direct Memory Access (DMA) Buffer Start address - * register B channel 0 (read/write). - * DBTB0 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 0 (read/write). - * - * DDAR1 Direct Memory Access (DMA) Device Address Register - * channel 1 (read/write). - * DCSR1 Direct Memory Access (DMA) Control and Status - * Register channel 1 (read/write). - * DBSA1 Direct Memory Access (DMA) Buffer Start address - * register A channel 1 (read/write). - * DBTA1 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 1 (read/write). - * DBSB1 Direct Memory Access (DMA) Buffer Start address - * register B channel 1 (read/write). - * DBTB1 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 1 (read/write). - * - * DDAR2 Direct Memory Access (DMA) Device Address Register - * channel 2 (read/write). - * DCSR2 Direct Memory Access (DMA) Control and Status - * Register channel 2 (read/write). - * DBSA2 Direct Memory Access (DMA) Buffer Start address - * register A channel 2 (read/write). - * DBTA2 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 2 (read/write). - * DBSB2 Direct Memory Access (DMA) Buffer Start address - * register B channel 2 (read/write). - * DBTB2 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 2 (read/write). - * - * DDAR3 Direct Memory Access (DMA) Device Address Register - * channel 3 (read/write). - * DCSR3 Direct Memory Access (DMA) Control and Status - * Register channel 3 (read/write). - * DBSA3 Direct Memory Access (DMA) Buffer Start address - * register A channel 3 (read/write). - * DBTA3 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 3 (read/write). - * DBSB3 Direct Memory Access (DMA) Buffer Start address - * register B channel 3 (read/write). - * DBTB3 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 3 (read/write). - * - * DDAR4 Direct Memory Access (DMA) Device Address Register - * channel 4 (read/write). - * DCSR4 Direct Memory Access (DMA) Control and Status - * Register channel 4 (read/write). - * DBSA4 Direct Memory Access (DMA) Buffer Start address - * register A channel 4 (read/write). - * DBTA4 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 4 (read/write). - * DBSB4 Direct Memory Access (DMA) Buffer Start address - * register B channel 4 (read/write). - * DBTB4 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 4 (read/write). - * - * DDAR5 Direct Memory Access (DMA) Device Address Register - * channel 5 (read/write). - * DCSR5 Direct Memory Access (DMA) Control and Status - * Register channel 5 (read/write). - * DBSA5 Direct Memory Access (DMA) Buffer Start address - * register A channel 5 (read/write). - * DBTA5 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 5 (read/write). - * DBSB5 Direct Memory Access (DMA) Buffer Start address - * register B channel 5 (read/write). - * DBTB5 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 5 (read/write). - */ - -#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ - -#define _DDAR(Nb) /* DMA Device Address Reg. */ \ - /* channel [0..5] */ \ - (0xB0000000 + (Nb)*DMASp) -#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ - /* channel [0..5] (write) */ \ - (0xB0000004 + (Nb)*DMASp) -#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ - /* channel [0..5] (write) */ \ - (0xB0000008 + (Nb)*DMASp) -#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ - /* channel [0..5] (read) */ \ - (0xB000000C + (Nb)*DMASp) -#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ - /* channel [0..5] */ \ - (0xB0000010 + (Nb)*DMASp) -#define _DBTA(Nb) /* DMA Buffer Transfer count */ \ - /* reg. A channel [0..5] */ \ - (0xB0000014 + (Nb)*DMASp) -#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ - /* channel [0..5] */ \ - (0xB0000018 + (Nb)*DMASp) -#define _DBTB(Nb) /* DMA Buffer Transfer count */ \ - /* reg. B channel [0..5] */ \ - (0xB000001C + (Nb)*DMASp) - -#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */ - /* channel 0 */ -#define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */ - /* channel 0 (write) */ -#define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */ - /* channel 0 (write) */ -#define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */ - /* channel 0 (read) */ -#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */ - /* channel 0 */ -#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */ - /* reg. A channel 0 */ -#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */ - /* channel 0 */ -#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */ - /* reg. B channel 0 */ - -#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */ - /* channel 1 */ -#define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */ - /* channel 1 (write) */ -#define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */ - /* channel 1 (write) */ -#define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */ - /* channel 1 (read) */ -#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */ - /* channel 1 */ -#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */ - /* reg. A channel 1 */ -#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */ - /* channel 1 */ -#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */ - /* reg. B channel 1 */ - -#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */ - /* channel 2 */ -#define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */ - /* channel 2 (write) */ -#define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */ - /* channel 2 (write) */ -#define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */ - /* channel 2 (read) */ -#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */ - /* channel 2 */ -#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */ - /* reg. A channel 2 */ -#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */ - /* channel 2 */ -#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */ - /* reg. B channel 2 */ - -#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */ - /* channel 3 */ -#define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */ - /* channel 3 (write) */ -#define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */ - /* channel 3 (write) */ -#define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */ - /* channel 3 (read) */ -#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */ - /* channel 3 */ -#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */ - /* reg. A channel 3 */ -#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */ - /* channel 3 */ -#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */ - /* reg. B channel 3 */ - -#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */ - /* channel 4 */ -#define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */ - /* channel 4 (write) */ -#define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */ - /* channel 4 (write) */ -#define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */ - /* channel 4 (read) */ -#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */ - /* channel 4 */ -#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */ - /* reg. A channel 4 */ -#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */ - /* channel 4 */ -#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */ - /* reg. B channel 4 */ - -#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */ - /* channel 5 */ -#define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */ - /* channel 5 (write) */ -#define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */ - /* channel 5 (write) */ -#define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */ - /* channel 5 (read) */ -#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */ - /* channel 5 */ -#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */ - /* reg. A channel 5 */ -#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */ - /* channel 5 */ -#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */ - /* reg. B channel 5 */ - -#if LANGUAGE == C - -#define DDAR0 /* DMA Device Address Reg. */ \ - /* channel 0 */ \ - (*((volatile Word *) io_p2v (_DDAR0))) -#define SetDCSR0 /* Set DMA Control & Status Reg. */ \ - /* channel 0 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR0))) -#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \ - /* channel 0 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR0))) -#define RdDCSR0 /* Read DMA Control & Status Reg. */ \ - /* channel 0 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR0))) -#define DBSA0 /* DMA Buffer Start address reg. A */ \ - /* channel 0 */ \ - (*((volatile Address *) io_p2v (_DBSA0))) -#define DBTA0 /* DMA Buffer Transfer count */ \ - /* reg. A channel 0 */ \ - (*((volatile Word *) io_p2v (_DBTA0))) -#define DBSB0 /* DMA Buffer Start address reg. B */ \ - /* channel 0 */ \ - (*((volatile Address *) io_p2v (_DBSB0))) -#define DBTB0 /* DMA Buffer Transfer count */ \ - /* reg. B channel 0 */ \ - (*((volatile Word *) io_p2v (_DBTB0))) - -#define DDAR1 /* DMA Device Address Reg. */ \ - /* channel 1 */ \ - (*((volatile Word *) io_p2v (_DDAR1))) -#define SetDCSR1 /* Set DMA Control & Status Reg. */ \ - /* channel 1 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR1))) -#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \ - /* channel 1 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR1))) -#define RdDCSR1 /* Read DMA Control & Status Reg. */ \ - /* channel 1 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR1))) -#define DBSA1 /* DMA Buffer Start address reg. A */ \ - /* channel 1 */ \ - (*((volatile Address *) io_p2v (_DBSA1))) -#define DBTA1 /* DMA Buffer Transfer count */ \ - /* reg. A channel 1 */ \ - (*((volatile Word *) io_p2v (_DBTA1))) -#define DBSB1 /* DMA Buffer Start address reg. B */ \ - /* channel 1 */ \ - (*((volatile Address *) io_p2v (_DBSB1))) -#define DBTB1 /* DMA Buffer Transfer count */ \ - /* reg. B channel 1 */ \ - (*((volatile Word *) io_p2v (_DBTB1))) - -#define DDAR2 /* DMA Device Address Reg. */ \ - /* channel 2 */ \ - (*((volatile Word *) io_p2v (_DDAR2))) -#define SetDCSR2 /* Set DMA Control & Status Reg. */ \ - /* channel 2 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR2))) -#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \ - /* channel 2 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR2))) -#define RdDCSR2 /* Read DMA Control & Status Reg. */ \ - /* channel 2 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR2))) -#define DBSA2 /* DMA Buffer Start address reg. A */ \ - /* channel 2 */ \ - (*((volatile Address *) io_p2v (_DBSA2))) -#define DBTA2 /* DMA Buffer Transfer count */ \ - /* reg. A channel 2 */ \ - (*((volatile Word *) io_p2v (_DBTA2))) -#define DBSB2 /* DMA Buffer Start address reg. B */ \ - /* channel 2 */ \ - (*((volatile Address *) io_p2v (_DBSB2))) -#define DBTB2 /* DMA Buffer Transfer count */ \ - /* reg. B channel 2 */ \ - (*((volatile Word *) io_p2v (_DBTB2))) - -#define DDAR3 /* DMA Device Address Reg. */ \ - /* channel 3 */ \ - (*((volatile Word *) io_p2v (_DDAR3))) -#define SetDCSR3 /* Set DMA Control & Status Reg. */ \ - /* channel 3 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR3))) -#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \ - /* channel 3 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR3))) -#define RdDCSR3 /* Read DMA Control & Status Reg. */ \ - /* channel 3 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR3))) -#define DBSA3 /* DMA Buffer Start address reg. A */ \ - /* channel 3 */ \ - (*((volatile Address *) io_p2v (_DBSA3))) -#define DBTA3 /* DMA Buffer Transfer count */ \ - /* reg. A channel 3 */ \ - (*((volatile Word *) io_p2v (_DBTA3))) -#define DBSB3 /* DMA Buffer Start address reg. B */ \ - /* channel 3 */ \ - (*((volatile Address *) io_p2v (_DBSB3))) -#define DBTB3 /* DMA Buffer Transfer count */ \ - /* reg. B channel 3 */ \ - (*((volatile Word *) io_p2v (_DBTB3))) - -#define DDAR4 /* DMA Device Address Reg. */ \ - /* channel 4 */ \ - (*((volatile Word *) io_p2v (_DDAR4))) -#define SetDCSR4 /* Set DMA Control & Status Reg. */ \ - /* channel 4 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR4))) -#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \ - /* channel 4 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR4))) -#define RdDCSR4 /* Read DMA Control & Status Reg. */ \ - /* channel 4 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR4))) -#define DBSA4 /* DMA Buffer Start address reg. A */ \ - /* channel 4 */ \ - (*((volatile Address *) io_p2v (_DBSA4))) -#define DBTA4 /* DMA Buffer Transfer count */ \ - /* reg. A channel 4 */ \ - (*((volatile Word *) io_p2v (_DBTA4))) -#define DBSB4 /* DMA Buffer Start address reg. B */ \ - /* channel 4 */ \ - (*((volatile Address *) io_p2v (_DBSB4))) -#define DBTB4 /* DMA Buffer Transfer count */ \ - /* reg. B channel 4 */ \ - (*((volatile Word *) io_p2v (_DBTB4))) - -#define DDAR5 /* DMA Device Address Reg. */ \ - /* channel 5 */ \ - (*((volatile Word *) io_p2v (_DDAR5))) -#define SetDCSR5 /* Set DMA Control & Status Reg. */ \ - /* channel 5 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR5))) -#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \ - /* channel 5 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR5))) -#define RdDCSR5 /* Read DMA Control & Status Reg. */ \ - /* channel 5 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR5))) -#define DBSA5 /* DMA Buffer Start address reg. A */ \ - /* channel 5 */ \ - (*((volatile Address *) io_p2v (_DBSA5))) -#define DBTA5 /* DMA Buffer Transfer count */ \ - /* reg. A channel 5 */ \ - (*((volatile Word *) io_p2v (_DBTA5))) -#define DBSB5 /* DMA Buffer Start address reg. B */ \ - /* channel 5 */ \ - (*((volatile Address *) io_p2v (_DBSB5))) -#define DBTB5 /* DMA Buffer Transfer count */ \ - /* reg. B channel 5 */ \ - (*((volatile Word *) io_p2v (_DBTB5))) - -#endif /* LANGUAGE == C */ - -#define DDAR_RW 0x00000001 /* device data Read/Write */ -#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ - /* (memory -> device) */ -#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ - /* (device -> memory) */ -#define DDAR_E 0x00000002 /* big/little Endian device */ -#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ -#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ -#define DDAR_BS 0x00000004 /* device Burst Size */ -#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ -#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ -#define DDAR_DW 0x00000008 /* device Data Width */ -#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ -#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ -#define DDAR_DS Fld (4, 4) /* Device Select */ -#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ - (0x0 << FShft (DDAR_DS)) -#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ - (0x1 << FShft (DDAR_DS)) -#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ - (0x2 << FShft (DDAR_DS)) -#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ - (0x3 << FShft (DDAR_DS)) -#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ - (0x4 << FShft (DDAR_DS)) -#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ - (0x5 << FShft (DDAR_DS)) -#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ - (0x6 << FShft (DDAR_DS)) -#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ - (0x7 << FShft (DDAR_DS)) -#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ - (0x8 << FShft (DDAR_DS)) -#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ - (0x9 << FShft (DDAR_DS)) -#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ - /* (audio) */ \ - (0xA << FShft (DDAR_DS)) -#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ - /* (audio) */ \ - (0xB << FShft (DDAR_DS)) -#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ - /* (telecom) */ \ - (0xC << FShft (DDAR_DS)) -#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ - /* (telecom) */ \ - (0xD << FShft (DDAR_DS)) -#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ - (0xE << FShft (DDAR_DS)) -#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ - (0xF << FShft (DDAR_DS)) -#define DDAR_DA Fld (24, 8) /* Device Address */ -#define DDAR_DevAdd(Add) /* Device Address */ \ - (((Add) & 0xF0000000) | \ - (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) -#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ - (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR)) -#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ - (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR)) -#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR)) -#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR)) -#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR)) -#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR)) -#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR)) -#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR)) -#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ - (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR)) -#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ - (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR)) -#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR)) -#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR)) -#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0)) -#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0)) -#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ - /* (telecom) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1)) -#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ - /* (telecom) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1)) -#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR)) -#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR)) - -#define DCSR_RUN 0x00000001 /* DMA RUNing */ -#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ -#define DCSR_ERROR 0x00000004 /* DMA ERROR */ -#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ -#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ -#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ -#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ -#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ -#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ -#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ - -#define DBT_TC Fld (13, 0) /* Transfer Count */ -#define DBTA_TCA DBT_TC /* Transfer Count buffer A */ -#define DBTB_TCB DBT_TC /* Transfer Count buffer B */ - - -/* - * Liquid Crystal Display (LCD) control registers - * - * Registers - * LCCR0 Liquid Crystal Display (LCD) Control Register 0 - * (read/write). - * [Bits LDM, BAM, and ERM are only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] - * LCSR Liquid Crystal Display (LCD) Status Register - * (read/write). - * [Bit LDD can be only read in versions 1.0 (rev. = 1) - * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be - * read and written (cleared) in versions 2.0 (rev. = 8) - * and higher.] - * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Base Address Register channel 1 (read/write). - * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Current Address Register channel 1 (read). - * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Base Address Register channel 2 (read/write). - * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Current Address Register channel 2 (read). - * LCCR1 Liquid Crystal Display (LCD) Control Register 1 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher.] - * LCCR2 Liquid Crystal Display (LCD) Control Register 2 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher.] - * LCCR3 Liquid Crystal Display (LCD) Control Register 3 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher. Bit PCP is only - * implemented in versions 2.0 (rev. = 8) and higher of - * the StrongARM SA-1100.] - * - * Clocks - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). - * fpix, Tpix Frequency, period of the pixel clock. - * fln, Tln Frequency, period of the line clock. - * fac, Tac Frequency, period of the AC bias clock. - */ - -#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ -#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ - /* [byte] */ \ - (16*LCD_PEntrySp) -#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ - /* [byte] */ \ - (256*LCD_PEntrySp) -#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ - /* dummy-Palette Space [byte] */ \ - (16*LCD_PEntrySp) - -#define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ -#define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ -#define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ -#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ -#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ -#define LCD_4Bit /* LCD 4-Bit pixel mode */ \ - (0 << FShft (LCD_PBS)) -#define LCD_8Bit /* LCD 8-Bit pixel mode */ \ - (1 << FShft (LCD_PBS)) -#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ - (2 << FShft (LCD_PBS)) - -#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ -#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ -#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ -#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ -#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ -#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ -#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ -#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ -#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ -#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ -#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ -#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ -#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ -#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ -#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ -#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ - /* (Alternative) */ - -#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */ -#define _LCSR 0xB0100004 /* LCD Status Reg. */ -#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */ - /* channel 1 */ -#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */ - /* channel 1 */ -#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */ - /* channel 2 */ -#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */ - /* channel 2 */ -#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */ -#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */ -#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */ - -#if LANGUAGE == C -#define LCCR0 /* LCD Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_LCCR0))) -#define LCSR /* LCD Status Reg. */ \ - (*((volatile Word *) io_p2v (_LCSR))) -#define DBAR1 /* LCD DMA Base Address Reg. */ \ - /* channel 1 */ \ - (*((volatile Address *) io_p2v (_DBAR1))) -#define DCAR1 /* LCD DMA Current Address Reg. */ \ - /* channel 1 */ \ - (*((volatile Address *) io_p2v (_DCAR1))) -#define DBAR2 /* LCD DMA Base Address Reg. */ \ - /* channel 2 */ \ - (*((volatile Address *) io_p2v (_DBAR2))) -#define DCAR2 /* LCD DMA Current Address Reg. */ \ - /* channel 2 */ \ - (*((volatile Address *) io_p2v (_DCAR2))) -#define LCCR1 /* LCD Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_LCCR1))) -#define LCCR2 /* LCD Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_LCCR2))) -#define LCCR3 /* LCD Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_LCCR3))) -#endif /* LANGUAGE == C */ - -#define LCCR0_LEN 0x00000001 /* LCD ENable */ -#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ -#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ -#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ -#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ - /* Select */ -#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ -#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ -#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ - /* interrupt Mask (disable) */ -#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ - /* interrupt Mask (disable) */ -#define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ - /* IUU, OOL, OUL, OOU, and OUU) */ - /* interrupt Mask (disable) */ -#define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ -#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ -#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ -#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ -#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ -#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ -#define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ - /* display mode) */ -#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ - /* display */ -#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ - /* display */ -#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ - /* [Tmem] */ -#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ - /* [0..510 Tcpu] */ \ - ((Tcpu)/2 << FShft (LCCR0_PDD)) - -#define LCSR_LDD 0x00000001 /* LCD Disable Done */ -#define LCSR_BAU 0x00000002 /* Base Address Update (read) */ -#define LCSR_BER 0x00000004 /* Bus ERror */ -#define LCSR_ABC 0x00000008 /* AC Bias clock Count */ -#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ - /* panel */ -#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ - /* panel */ -#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ - /* panel */ -#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ - /* panel */ -#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ - /* panel */ -#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ - /* panel */ -#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ - /* panel */ -#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ - /* panel */ - -#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ -#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ - (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ - /* pulse Width - 2 [Tpix] (L_LCLK) */ -#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [2..65 Tpix] */ \ - (((Tpix) - 2) << FShft (LCCR1_HSW)) -#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ -#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_ELW)) -#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ -#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_BLW)) - -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ -#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ - (((Line) - 1) << FShft (LCCR2_LPP)) -#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ -#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ - (((Tln) - 1) << FShft (LCCR2_VSW)) -#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ -#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_EFW)) -#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ -#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_BFW)) - -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ - /* [1..255] (L_PCLK) */ - /* fpix = fcpu/(2*(PCD + 2)) */ - /* Tpix = 2*(PCD + 2)*Tcpu */ -#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ - (((Div) - 4)/2 << FShft (LCCR3_PCD)) - /* fpix = fcpu/(2*Floor (Div/2)) */ - /* Tpix = 2*Floor (Div/2)*Tcpu */ -#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ - (((Div) - 3)/2 << FShft (LCCR3_PCD)) - /* fpix = fcpu/(2*Ceil (Div/2)) */ - /* Tpix = 2*Ceil (Div/2)*Tcpu */ -#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ - /* [Tln] (L_BIAS) */ -#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ - (((Div) - 2)/2 << FShft (LCCR3_ACB)) - /* fac = fln/(2*Floor (Div/2)) */ - /* Tac = 2*Floor (Div/2)*Tln */ -#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ - (((Div) - 1)/2 << FShft (LCCR3_ACB)) - /* fac = fln/(2*Ceil (Div/2)) */ - /* Tac = 2*Ceil (Div/2)*Tln */ -#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ - /* Interrupt */ -#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ - /* Off */ \ - (0 << FShft (LCCR3_API)) -#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ - /* [1..15] */ \ - ((Trans) << FShft (LCCR3_API)) -#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ - /* Polarity (L_FCLK) */ -#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ -#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ -#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ - /* pulse Polarity (L_LCLK) */ -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ - /* pulse active Low */ -#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ -#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ -#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ -#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ - /* active display mode) */ -#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ -#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ - - -#undef C -#undef Assembly diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 1becc669ae..70303acd55 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -48,7 +48,6 @@ struct bd_info { #endif unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ unsigned long bi_ip_addr; /* IP Address */ - unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ diff --git a/include/binman_sym.h b/include/binman_sym.h index 72e6765fe5..528d7e4e90 100644 --- a/include/binman_sym.h +++ b/include/binman_sym.h @@ -11,9 +11,11 @@ #ifndef __BINMAN_SYM_H #define __BINMAN_SYM_H +/* BSYM in little endian, keep in sync with tools/binman/elf.py */ +#define BINMAN_SYM_MAGIC_VALUE (0x4d595342UL) #define BINMAN_SYM_MISSING (-1UL) -#ifdef CONFIG_BINMAN +#if CONFIG_IS_ENABLED(BINMAN_SYMBOLS) /** * binman_symname() - Internal function to get a binman symbol name @@ -63,6 +65,37 @@ section(".binman_sym"))) /** + * _binman_sym_magic - Internal magic symbol for validity checks + * + * When building images, binman fills in this symbol with the magic + * value #defined above. This is used to check at runtime if the + * symbol values were filled in and are OK to use. + */ +extern ulong _binman_sym_magic; + +/** + * DECLARE_BINMAN_MAGIC_SYM - Declare the internal magic symbol + * + * This macro declares the _binman_sym_magic symbol so that it exists. + * Declaring it here would cause errors during linking due to multiple + * definitions of the symbol. + */ +#define DECLARE_BINMAN_MAGIC_SYM \ + ulong _binman_sym_magic \ + __attribute__((aligned(4), section(".binman_sym"))) + +/** + * BINMAN_SYMS_OK - Check if the symbol values are valid + * + * This macro checks if the magic symbol's value is filled properly, + * which indicates that other symbols are OK to use as well. + * + * Return: 1 if binman symbol values are usable, 0 if not + */ +#define BINMAN_SYMS_OK \ + (*(ulong *)&_binman_sym_magic == BINMAN_SYM_MAGIC_VALUE) + +/** * binman_sym() - Access a previously declared symbol * * This is used to get the value of a symbol. E.g.: @@ -72,12 +105,16 @@ * @_type: Type f the symbol (e.g. unsigned long) * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl') * @_prop_name: Property value to get from that entry (e.g. 'pos') - * @returns value of that property (filled in by binman) + * + * Return: value of that property (filled in by binman), or + * BINMAN_SYM_MISSING if the value is unavailable */ #define binman_sym(_type, _entry_name, _prop_name) \ - (*(_type *)&binman_symname(_entry_name, _prop_name)) + (BINMAN_SYMS_OK ? \ + (*(_type *)&binman_symname(_entry_name, _prop_name)) : \ + BINMAN_SYM_MISSING) -#else /* !BINMAN */ +#else /* !CONFIG_IS_ENABLED(BINMAN_SYMBOLS) */ #define binman_sym_declare(_type, _entry_name, _prop_name) @@ -85,8 +122,12 @@ #define binman_sym_extern(_type, _entry_name, _prop_name) +#define DECLARE_BINMAN_MAGIC_SYM + +#define BINMAN_SYMS_OK (0) + #define binman_sym(_type, _entry_name, _prop_name) BINMAN_SYM_MISSING -#endif /* BINMAN */ +#endif /* CONFIG_IS_ENABLED(BINMAN_SYMBOLS) */ #endif diff --git a/include/bloblist.h b/include/bloblist.h index d0e128acf1..9684bfd5f4 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -3,8 +3,66 @@ * This provides a standard way of passing information between boot phases * (TPL -> SPL -> U-Boot proper.) * - * A list of blobs of data, tagged with their owner. The list resides in memory - * and can be updated by SPL, U-Boot, etc. + * It consists of a list of blobs of data, tagged with their owner / contents. + * The list resides in memory and can be updated by SPL, U-Boot, etc. + * + * Design goals for bloblist: + * + * 1. Small and efficient structure. This avoids UUIDs or 16-byte name fields, + * since a 32-bit tag provides enough space for all the tags we will even need. + * If UUIDs are desired, they can be added inside a particular blob. + * + * 2. Avoids use of pointers, so the structure can be relocated in memory. The + * data in each blob is inline, rather than using pointers. + * + * 3. Bloblist is designed to start small in TPL or SPL, when only a few things + * are needed, like the memory size or whether console output should be enabled. + * Then it can grow in U-Boot proper, e.g. to include space for ACPI tables. + * + * 4. The bloblist structure is simple enough that it can be implemented in a + * small amount of C code. The API does not require use of strings or UUIDs, + * which would add to code size. For Thumb-2 the code size needed in SPL is + * approximately 940 bytes (e.g. for chromebook_bob). + * + * 5. Bloblist uses 16-byte alignment internally and is designed to start on a + * 16-byte boundary. Its headers are multiples of 16 bytes. This makes it easier + * to deal with data structures which need this level of alignment, such as ACPI + * tables. For use in SPL and TPL the alignment can be relaxed, since it can be + * relocated to an aligned address in U-Boot proper. + * + * 6. Bloblist is designed to be passed to Linux as reserved memory. While linux + * doesn't understand the bloblist header, it can be passed the indivdual blobs. + * For example, ACPI tables can reside in a blob and the address of those is + * passed to Linux, without Linux ever being away of the existence of a + * bloblist. Having all the blobs contiguous in memory simplifies the + * reserved-memory space. + * + * 7. Bloblist tags are defined in the enum below. There is an area for + * project-specific stuff (e.g. U-Boot, TF-A) and vendor-specific stuff, e.g. + * something used only on a particular SoC. There is also a private area for + * temporary, local use. + * + * 8. Bloblist includes a simple checksum, so that each boot phase can update + * this and allow the next phase to check that all is well. While the bloblist + * is small, this is quite cheap to calculate. When it grows (e.g. in U-Boot\ + * proper), the CPU is likely running faster, so it is not prohibitive. Having + * said that, U-Boot is often the last phase that uses bloblist, so calculating + * the checksum there may not be necessary. + * + * 9. It would be possible to extend bloblist to support a non-contiguous + * structure, e.g. by creating a blob type that points to the next bloblist. + * This does not seem necessary for now. It adds complexity and code. We can + * always just copy it. + * + * 10. Bloblist is designed for simple structures, those that can be defined by + * a single C struct. More complex structures should be passed in a device tree. + * There are some exceptions, chiefly the various binary structures that Intel + * is fond of creating. But device tree provides a dictionary-type format which + * is fairly efficient (for use in U-Boot proper and Linux at least), along with + * a schema and a good set of tools. New formats should be designed around + * device tree rather than creating new binary formats, unless they are needed + * early in boot (where libfdt's 3KB of overhead is too large) and are trival + * enough to be described by a C struct. * * Copyright 2018 Google, Inc * Written by Simon Glass <sjg@chromium.org> diff --git a/include/bootcount.h b/include/bootcount.h index fccee7e15b..bfa5d46427 100644 --- a/include/bootcount.h +++ b/include/bootcount.h @@ -72,14 +72,6 @@ ulong bootcount_load(void); #if defined(CONFIG_SPL_BOOTCOUNT_LIMIT) || defined(CONFIG_TPL_BOOTCOUNT_LIMIT) || defined(CONFIG_BOOTCOUNT_LIMIT) -#if !defined(CONFIG_SYS_BOOTCOUNT_LE) && !defined(CONFIG_SYS_BOOTCOUNT_BE) -# if __BYTE_ORDER == __LITTLE_ENDIAN -# define CONFIG_SYS_BOOTCOUNT_LE -# else -# define CONFIG_SYS_BOOTCOUNT_BE -# endif -#endif - #ifdef CONFIG_SYS_BOOTCOUNT_LE static inline void raw_bootcount_store(volatile u32 *addr, u32 data) { diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index c55023889c..c6e9c49741 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -70,18 +70,23 @@ #ifdef CONFIG_CMD_UBIFS #define BOOTENV_SHARED_UBIFS \ "ubifs_boot=" \ - "env exists bootubipart || " \ - "env set bootubipart UBI; " \ - "env exists bootubivol || " \ - "env set bootubivol boot; " \ "if ubi part ${bootubipart} && " \ - "ubifsmount ubi${devnum}:${bootubivol}; " \ + "ubifsmount ubi0:${bootubivol}; " \ "then " \ "devtype=ubi; " \ + "devnum=ubi0; " \ + "bootfstype=ubifs; " \ + "distro_bootpart=${bootubivol}; " \ "run scan_dev_for_boot; " \ + "ubifsumount; " \ "fi\0" -#define BOOTENV_DEV_UBIFS BOOTENV_DEV_BLKDEV -#define BOOTENV_DEV_NAME_UBIFS BOOTENV_DEV_NAME_BLKDEV +#define BOOTENV_DEV_UBIFS(devtypeu, devtypel, instance, bootubipart, bootubivol) \ + "bootcmd_ubifs" #instance "=" \ + "bootubipart=" #bootubipart "; " \ + "bootubivol=" #bootubivol "; " \ + "run ubifs_boot\0" +#define BOOTENV_DEV_NAME_UBIFS(devtypeu, devtypel, instance, bootubipart, bootubivol) \ + #devtypel #instance " " #else #define BOOTENV_SHARED_UBIFS #define BOOTENV_DEV_UBIFS \ @@ -411,13 +416,13 @@ BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE #endif -#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance) \ - BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance) +#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance, ...) \ + BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance, ## __VA_ARGS__) #define BOOTENV_BOOT_TARGETS \ "boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0" -#define BOOTENV_DEV(devtypeu, devtypel, instance) \ - BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance) +#define BOOTENV_DEV(devtypeu, devtypel, instance, ...) \ + BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance, ## __VA_ARGS__) #define BOOTENV \ BOOTENV_SHARED_HOST \ BOOTENV_SHARED_MMC \ diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 167d44e400..17c76bcf3d 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -9,41 +9,16 @@ #ifndef __CONFIG_FALLBACKS_H #define __CONFIG_FALLBACKS_H -#ifdef CONFIG_SPL #ifdef CONFIG_SPL_PAD_TO #ifdef CONFIG_SPL_MAX_SIZE #if CONFIG_SPL_PAD_TO && CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE #error CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE #endif #endif -#else -#ifdef CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE -#else -#define CONFIG_SPL_PAD_TO 0 -#endif -#endif #endif #ifndef CONFIG_SYS_BAUDRATE_TABLE #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #endif -/* Console I/O Buffer Size */ -#ifndef CONFIG_SYS_CBSIZE -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif -#endif - -#ifndef CONFIG_SYS_PBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#endif - -#ifndef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 16 -#endif - #endif /* __CONFIG_FALLBACKS_H */ diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 3922241be0..380c906ba8 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -10,10 +10,6 @@ #ifdef CONFIG_CHAIN_OF_TRUST -#ifndef CONFIG_EXTRA_ENV -#define CONFIG_EXTRA_ENV "" -#endif - /* * Control should not reach back to uboot after validation of images * for secure boot flow and therefore bootscript should have @@ -21,43 +17,22 @@ * after validating images, core should just spin. */ -/* - * Define the key hash for boot script here if public/private key pair used to - * sign bootscript are different from the SRK hash put in the fuse - * Example of defining KEY_HASH is - * #define CONFIG_BOOTSCRIPT_KEY_HASH \ - * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" - */ - #ifdef CONFIG_USE_BOOTARGS -#define CONFIG_SET_BOOTARGS "setenv bootargs \'" CONFIG_BOOTARGS" \';" +#define SET_BOOTARGS "setenv bootargs \'" CONFIG_BOOTARGS" \';" #else -#define CONFIG_SET_BOOTARGS "setenv bootargs \'root=/dev/ram " \ +#define SET_BOOTARGS "setenv bootargs \'root=/dev/ram " \ "rw console=ttyS0,115200 ramdisk_size=600000\';" #endif - -#ifdef CONFIG_BOOTSCRIPT_KEY_HASH -#define CONFIG_SECBOOT \ +#define SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - CONFIG_SET_BOOTARGS \ - CONFIG_EXTRA_ENV \ - "esbc_validate $bs_hdraddr " \ - __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ - "source $img_addr;" \ - "esbc_halt\0" -#else -#define CONFIG_SECBOOT \ - "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - CONFIG_SET_BOOTARGS \ - CONFIG_EXTRA_ENV \ + SET_BOOTARGS \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt\0" -#endif #ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BS_COPY_ENV \ +#define BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ "setenv bs_hdr_device " __stringify(CONFIG_BS_HDR_ADDR_DEVICE)";" \ "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ @@ -68,33 +43,28 @@ /* For secure boot flow, default environment used will be used */ #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_NAND_BOOT) || \ defined(CONFIG_SD_BOOT) -#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_NAND_BOOT) -#define CONFIG_BS_COPY_CMD \ +#if defined(CONFIG_NAND_BOOT) +#define BS_COPY_CMD \ "nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ "nand read $bs_ram $bs_device $bs_size ;" #elif defined(CONFIG_SD_BOOT) -#define CONFIG_BS_COPY_CMD \ +#define BS_COPY_CMD \ "mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ "mmc read $bs_ram $bs_device $bs_size ;" #endif #else -#define CONFIG_BS_COPY_CMD \ +#define BS_COPY_CMD \ "cp.b $bs_hdr_device $bs_hdr_ram $bs_hdr_size ;" \ "cp.b $bs_device $bs_ram $bs_size ;" #endif +#else /* !CONFIG_BOOTSCRIPT_COPY_RAM */ +#define BS_COPY_ENV +#define BS_COPY_CMD #endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ -#ifndef CONFIG_BS_COPY_ENV -#define CONFIG_BS_COPY_ENV -#endif - -#ifndef CONFIG_BS_COPY_CMD -#define CONFIG_BS_COPY_CMD -#endif - -#define CONFIG_CHAIN_BOOT_CMD CONFIG_BS_COPY_ENV \ - CONFIG_BS_COPY_CMD \ - CONFIG_SECBOOT +#define CHAIN_BOOT_CMD BS_COPY_ENV \ + BS_COPY_CMD \ + SECBOOT #endif #endif diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index 9db0f0efb1..2d52dc6f66 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -19,7 +19,6 @@ /* * CFI Flash */ -#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 275fb5665f..c773164c86 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -17,15 +17,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* I2C */ #ifdef CONFIG_MCFFEC @@ -65,8 +56,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Start addresses for the final memory configuration @@ -83,20 +72,16 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /* FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ #endif diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 13743dab52..79448cf440 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -22,15 +22,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* I2C */ #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) @@ -75,8 +66,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x21 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -88,8 +77,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -97,18 +84,12 @@ */ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -#ifdef CONFIG_NORFLASH_PS32BIT -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#else -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#endif # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ #endif diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index f68eb979bd..1889a235a2 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -44,8 +44,6 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ @@ -65,7 +63,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data @@ -80,7 +77,6 @@ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ # define CONFIG_SYS_FLASH_CHECKSUM # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 079675be5b..cac9b24ead 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -19,12 +19,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text*); -#ifdef CONFIG_IDE -/* ATA */ -# define CONFIG_IDE_PREINIT 1 -# undef CONFIG_LBA48 -#endif - #ifdef CONFIG_DRIVER_DM9000 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) # define DM9000_IO CONFIG_DM9000_BASE @@ -79,8 +73,6 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Start addresses for the final memory configuration @@ -91,7 +83,6 @@ #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) /* * For booting Linux, the board info and command line data @@ -99,7 +90,6 @@ * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /* FLASH organization */ #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) @@ -116,7 +106,6 @@ * 0x30 is block erase in SST */ # define CONFIG_SYS_FLASH_SIZE 0x800000 -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_FLASH_CFI_LEGACY #else # define CONFIG_SYS_SST_SECT 2048 diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index b8918680c1..2fa1e4356e 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -32,15 +32,6 @@ env/embedded.o(.text); #ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#ifdef CONFIG_MCFFEC # define CONFIG_IPADDR 192.162.1.2 # define CONFIG_NETMASK 255.255.255.0 # define CONFIG_SERVERIP 192.162.1.1 @@ -76,8 +67,6 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -89,7 +78,6 @@ #define CONFIG_SYS_FLASH_BASE 0xffe00000 #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data @@ -103,7 +91,6 @@ */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ #endif diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 68e3c89a1c..292578fc15 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -33,15 +33,6 @@ /* Available command configuration */ -#ifdef CONFIG_MCFFEC -#define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -#ifndef CONFIG_SYS_DISCOVER_PHY -#define FECDUPLEX FULL -#define FECSPEED _100BASET -#endif -#endif - /* I2C */ #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) @@ -78,8 +69,6 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -91,7 +80,6 @@ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data @@ -99,7 +87,6 @@ * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index b6e569d820..9f06f41ce1 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -30,15 +30,6 @@ env/embedded.o(.text*); #ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#ifdef CONFIG_MCFFEC # define CONFIG_IPADDR 192.162.1.2 # define CONFIG_NETMASK 255.255.255.0 # define CONFIG_SERVERIP 192.162.1.1 @@ -77,8 +68,6 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -92,7 +81,6 @@ #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data @@ -107,7 +95,6 @@ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ # define CONFIG_SYS_FLASH_CHECKSUM # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 34b5ceb20c..4d8f752777 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -22,18 +22,9 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 -#define CONFIG_SYS_UNIFY_CACHE - #ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_TX_ETH_BUFFER 8 # define CONFIG_SYS_FEC_BUF_USE_SRAM - -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ #endif #define CONFIG_SYS_RTC_CNT (0x8000) @@ -79,8 +70,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Start addresses for the final memory configuration @@ -97,15 +86,12 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization @@ -113,7 +99,6 @@ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_FLASH_SPANSION_S29WS_N 1 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ #endif diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 673b0dc2e8..87d3e8fb15 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -22,17 +22,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ -#define CONFIG_SYS_UNIFY_CACHE - -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* I2C */ #ifdef CONFIG_MCFFEC @@ -75,8 +64,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -93,22 +80,18 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ #endif diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 4c9fc43fd6..d920587c37 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -24,17 +24,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ -#define CONFIG_SYS_UNIFY_CACHE - -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* I2C */ #ifdef CONFIG_MCFFEC @@ -77,8 +66,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -95,22 +82,18 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ #endif diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 01b33c77a8..41ab860850 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -86,7 +86,6 @@ /* environment is in FLASH */ /* Ethernet configuration part */ -#define CONFIG_SYS_DISCOVER_PHY 1 /* NAND configuration part */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index eb4ccb17ea..d56d60306a 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -61,7 +61,6 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 -#define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) @@ -127,12 +126,6 @@ * The reserved memory */ -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ /* @@ -141,8 +134,6 @@ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * FLASH on the Local Bus @@ -200,43 +191,15 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 - -#ifdef CONFIG_PCI -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ /* * TSEC @@ -257,7 +220,6 @@ #ifdef CONFIG_TSEC2 #define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 #define TSEC2_PHY_ADDR 0x1c #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define TSEC2_PHYIDX 0 @@ -265,22 +227,6 @@ #endif /* - * SATA - */ -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#ifdef CONFIG_FSL_SATA -#define CONFIG_LBA48 -#endif - -/* * Environment */ @@ -302,15 +248,11 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration */ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - #define CONFIG_NETDEV "eth1" #define CONFIG_HOSTNAME "mpc837x_rdb" diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 244f811ff6..c3c68071f2 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -16,10 +16,6 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_PCI1 /* PCI controller 1 */ -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#undef CONFIG_PCI2 - #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #ifndef __ASSEMBLY__ @@ -34,7 +30,6 @@ /* * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_ENABLE_36BIT_PHYS 1 #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR @@ -244,8 +239,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) @@ -265,8 +259,6 @@ */ #if !CONFIG_IS_ENABLED(DM_I2C) #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } -#else -#define CONFIG_SYS_SPD_BUS_NUM 0 #endif /* EEPROM */ @@ -320,10 +312,6 @@ #endif #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ -#if defined(CONFIG_PCI) -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - #if defined(CONFIG_TSEC_ENET) #define CONFIG_TSEC1 1 @@ -368,7 +356,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 0c19b92940..12a78eac17 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -16,18 +16,10 @@ #include <asm/config_mpc85xx.h> #ifdef CONFIG_SDCARD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif #endif #ifdef CONFIG_SPIFLASH @@ -35,65 +27,32 @@ #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #else -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif #endif #endif #ifdef CONFIG_MTD_RAW_NAND #ifdef CONFIG_NXP_ESBC -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #else #ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) #elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_NAND_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_MAX_SIZE 8192 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 -#else -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif #endif -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#endif #endif #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ -#define CONFIG_RAMBOOT_NAND #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif @@ -104,9 +63,6 @@ /* High Level Configuration Options */ #if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ - /* * PCI Windows * Memory space is mapped 1-1, but I/O space must start from 0. @@ -138,8 +94,6 @@ #else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif #define CONFIG_HWCONFIG @@ -148,12 +102,7 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ - -#define CONFIG_ENABLE_36BIT_PHYS - /* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -169,7 +118,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 @@ -206,11 +154,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -/* Don't relocate CCSRBAR while in NAND_SPL */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - /* * Memory map * @@ -398,20 +341,11 @@ extern unsigned long get_sdram_size(void); FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ - defined(CONFIG_RAMBOOT_NAND) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -424,29 +358,17 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) #else #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) -#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) #endif #endif #endif @@ -456,7 +378,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) +#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) #define CONFIG_NS16550_MIN_FUNCTIONS #endif @@ -524,46 +446,16 @@ extern unsigned long get_sdram_size(void); #endif /* CONFIG_TSEC_ENET */ -/* SATA */ -#define CONFIG_FSL_SATA_V2 - -#ifdef CONFIG_FSL_SATA -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif /* #ifdef CONFIG_FSL_SATA */ - #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #endif -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - /* * Environment */ -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#elif defined(CONFIG_MTD_RAW_NAND) +#if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) -#else -#if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ -#elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ -#endif #endif #endif @@ -584,7 +476,6 @@ extern unsigned long get_sdram_size(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 3d9e3e1c78..2d552835b7 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -25,17 +25,12 @@ #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ @@ -43,11 +38,6 @@ #define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_DPAA_RMAN /* RMan */ -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) - #define CONFIG_FSL_FIXED_MMC_LOCATION -#endif - #ifndef __ASSEMBLY__ #include <linux/stringify.h> #endif @@ -55,11 +45,8 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* @@ -91,7 +78,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -141,10 +127,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_BASE 0xffa00000 @@ -196,9 +178,7 @@ #endif #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -334,24 +314,6 @@ #define CONFIG_SYS_DPAA_PME #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#define CONFIG_FSL_SATA_V2 - -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 @@ -375,16 +337,6 @@ #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_HAS_FSL_MPH_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT @@ -400,7 +352,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index f1417b1bfc..bc8aa3ce05 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -9,9 +9,6 @@ */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE3 -#define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN #define CONFIG_SYS_SRIO diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 8a0c7039f6..6375c65d48 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -9,10 +9,6 @@ */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ -#define CONFIG_PCIE3 - -#define CONFIG_LBA48 - #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h index fc2a07b974..fb73f0b953 100644 --- a/include/configs/P5040DS.h +++ b/include/configs/P5040DS.h @@ -9,8 +9,6 @@ */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ -#define CONFIG_PCIE3 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 8114373655..e42e6d5653 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -9,10 +9,6 @@ /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - /* * NS16550 Configuration */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index b70829c09d..8926c26b0b 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -9,10 +9,6 @@ /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - /* * NS16550 Configuration */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e7cc39e78a..c90ffe048c 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -14,43 +14,25 @@ #include <linux/stringify.h> /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SDCARD @@ -59,9 +41,6 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -116,7 +95,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -127,11 +105,7 @@ */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE (256 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 @@ -149,11 +123,9 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_SDRAM_SIZE 2048 #endif @@ -313,10 +285,6 @@ #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -337,9 +305,7 @@ #endif #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -379,9 +345,6 @@ * General PCIe * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ @@ -407,18 +370,11 @@ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ /* * USB */ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif /* * SDHC @@ -500,7 +456,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index de31f695c6..56486cf5c9 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -15,14 +15,6 @@ #include <asm/config_mpc85xx.h> #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 @@ -40,21 +32,14 @@ #endif #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SDCARD @@ -63,46 +48,26 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_MTD_RAW_NAND) -#ifdef CONFIG_NXP_ESBC -#define CONFIG_RAMBOOT_NAND -#define CONFIG_BOOTSCRIPT_COPY_RAM -#endif -#endif /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - /* * Config the L3 Cache as L3 SRAM */ @@ -114,11 +79,7 @@ */ #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE 256 << 10 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -130,7 +91,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -297,10 +257,6 @@ #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -315,9 +271,7 @@ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -401,30 +355,11 @@ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -/* SATA */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - /* * USB */ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR @@ -511,7 +446,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Dynamic MTD Partition support with mtdparts diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 82e0fc46c7..710254a8fb 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -15,50 +15,31 @@ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #if defined(CONFIG_ARCH_T2080) -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SDCARD @@ -67,9 +48,6 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -90,7 +68,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -100,11 +77,7 @@ */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE (512 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -119,7 +92,6 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -293,10 +265,6 @@ #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -310,9 +278,7 @@ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* @@ -395,10 +361,6 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull @@ -422,10 +384,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN #define CONFIG_SYS_BMAN_NUM_PORTALS 18 @@ -474,25 +432,8 @@ #endif /* - * SATA - */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#define CONFIG_LBA48 -#endif - -/* * USB */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB -#endif /* * SDHC @@ -522,7 +463,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 9438544325..8ade2e3c82 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -14,46 +14,27 @@ #include <linux/stringify.h> #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#define CONFIG_FSL_SATA_V2 /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SDCARD @@ -62,9 +43,6 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -85,7 +63,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -95,11 +72,7 @@ */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE (512 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -114,7 +87,6 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -252,10 +224,6 @@ #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -269,9 +237,7 @@ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* @@ -348,10 +314,6 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull @@ -375,10 +337,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN #define CONFIG_SYS_BMAN_NUM_PORTALS 18 @@ -430,25 +388,8 @@ #endif /* - * SATA - */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#define CONFIG_LBA48 -#endif - -/* * USB */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB -#endif /* * SDHC @@ -476,7 +417,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 834855c336..653483cc99 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -12,9 +12,6 @@ #include <linux/stringify.h> -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE4 - #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #ifdef CONFIG_RAMBOOT_PBL @@ -22,9 +19,6 @@ #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #else -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 @@ -34,53 +28,32 @@ #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif #endif #endif /* CONFIG_RAMBOOT_PBL */ /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - /* * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE (512 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -112,9 +85,7 @@ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -164,22 +135,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - /* * Environment */ @@ -196,7 +151,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration @@ -211,7 +165,6 @@ /* * DDR Setup */ -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x52 #define SPD_EEPROM_ADDRESS2 0x54 #define SPD_EEPROM_ADDRESS3 0x56 @@ -365,10 +318,6 @@ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - /* I2C */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ @@ -448,23 +397,9 @@ #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR #endif -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - /* * USB */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR diff --git a/include/configs/alt.h b/include/configs/alt.h index 090bee7d2d..fe303fda78 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -11,10 +11,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -38,8 +37,4 @@ "bootm_size=0x10000000\0" \ "usb_pgood_delay=2000\0" -/* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 - #endif /* __ALT_H */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index fd5b209a52..4b59759f81 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -19,22 +19,18 @@ #include <configs/ti_am335x_common.h> #include <linux/sizes.h> -#define CONFIG_SYS_BOOTM_LEN SZ_16M - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) #ifdef CONFIG_MTD_RAW_NAND #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ @@ -172,14 +168,6 @@ /* PMIC support */ #define CONFIG_POWER_TPS65910 -/* SPL */ -#ifndef CONFIG_NOR_BOOT -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE - -/* USB gadget RNDIS */ -#endif - #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ @@ -193,10 +181,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -/* NAND: SPL related configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ -#endif #endif /* !CONFIG_MTD_RAW_NAND */ /* USB Device Firmware Update support */ @@ -241,7 +225,6 @@ #if defined(CONFIG_NOR) #define CONFIG_SYS_MAX_FLASH_SECT 128 #define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_SIZE 0x01000000 #endif /* NOR support */ diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index b92703205c..7fa1847c1f 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -12,8 +12,6 @@ #include <configs/ti_am335x_common.h> -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -29,7 +27,7 @@ "ramdisk_addr_r=0x88080000\0" \ #define BOOT_TARGET_DEVICES(func) \ - func(UBIFS, ubifs, 0) + func(UBIFS, ubifs, 0, UBI, rootfs) #define AM335XX_BOARD_FDTFILE "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" @@ -52,9 +50,7 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV \ GUARDIAN_DEFAULT_PROD_ENV \ - "autoload=no\0" \ "backlight_brightness=50\0" \ - "bootubivol=rootfs\0" \ "distro_bootcmd=" \ "setenv rootflags \"bulk_read,chk_data_crc\"; " \ "setenv ethact usb_ether; " \ @@ -94,9 +90,6 @@ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_LE - #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h index 2cf77a67c0..3952783ee1 100644 --- a/include/configs/am335x_igep003x.h +++ b/include/configs/am335x_igep003x.h @@ -20,7 +20,6 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "bootdir=/boot\0" \ @@ -55,8 +54,6 @@ "bootz ${loadaddr} - ${fdtaddr};" \ "fi;" \ "fi;\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=1\0" \ "nandrootfstype=ubifs rootwait\0" \ "nandload=ubi part UBI; " \ @@ -89,7 +86,6 @@ "setenv fdtfile am335x-igep-base0040-lite.dtb; fi; " \ "if test ${fdtfile} = ''; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" -#endif /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 5964ccc74c..08bae9b886 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -16,8 +16,6 @@ /* settings we don;t want on this board */ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index a57d551bcf..7df5f14055 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -10,14 +10,10 @@ #include <configs/ti_am335x_common.h> -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD - #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x80000000\0" \ "pxefile_addr_r=0x80100000\0" \ @@ -39,8 +35,6 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV -#endif - /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ @@ -54,9 +48,6 @@ /* SPL */ -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* Network. */ #endif /* ! __CONFIG_AM335X_SL50_H */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index b872ade144..93beed4ad7 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -28,7 +28,6 @@ #define CONFIG_SYS_NAND_MAX_OOBFREE 2 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 /* NAND block size is 128 KiB. Synchronize these values with * corresponding Device Tree entries in Linux: * MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000 @@ -50,8 +49,6 @@ "bootenv=uEnv.txt\0" \ "cmdline=\0" \ "optargs=\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ @@ -86,20 +83,8 @@ /* Miscellaneous configurable options */ -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* memtest works on */ -/* Physical Memory Map */ -#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) - /* FLASH and environment organization */ /* **** PISMO SUPPORT *** */ @@ -113,8 +98,4 @@ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -/* Defines for SPL */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - #endif /* __CONFIG_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 5057441f75..87d3a27099 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -27,8 +27,6 @@ #define CONFIG_POWER_TPS62362 /* SPL defines. */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 << 20)) /* Enabling L2 Cache */ #define CONFIG_SYS_L2_PL310 @@ -50,12 +48,6 @@ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -/* SPL USB Support */ - -#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 -#endif - #ifndef CONFIG_SPL_BUILD /* USB Device Firmware Update support */ #define DFUARGS \ @@ -153,20 +145,13 @@ } #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 26 -/* NAND: SPL related configs */ -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */ -#endif #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index c36311e06d..d8b0531673 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -16,8 +16,6 @@ #define CONFIG_IODELAY_RECALIBRATION -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h new file mode 100644 index 0000000000..78201adc07 --- /dev/null +++ b/include/configs/am62x_evm.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 AM625 SoC family + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Suman Anna <s-anna@ti.com> + */ + +#ifndef __CONFIG_AM625_EVM_H +#define __CONFIG_AM625_EVM_H + +#include <config_distro_bootcmd.h> +#include <environment/ti/mmc.h> + +/* DDR Configuration */ +#define CONFIG_SYS_SDRAM_BASE1 0x880000000 + +#define PARTS_DEFAULT \ + /* Linux partitions */ \ + "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" + +/* U-Boot general configuration */ +#define EXTRA_ENV_AM625_BOARD_SETTINGS \ + "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "findfdt=" \ + "setenv name_fdt ${default_device_tree};" \ + "setenv fdtfile ${name_fdt}\0" \ + "name_kern=Image\0" \ + "console=ttyS2,115200n8\0" \ + "args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 " \ + "${mtdparts}\0" \ + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" + +/* U-Boot MMC-specific configuration */ +#define EXTRA_ENV_AM625_BOARD_SETTINGS_MMC \ + "boot=mmc\0" \ + "mmcdev=1\0" \ + "bootpart=1:2\0" \ + "bootdir=/boot\0" \ + "rd_spec=-\0" \ + "init_mmc=run args_all args_mmc\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \ + "fdt apply ${dtboaddr};" \ + "done;\0" \ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" \ + "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \ + "${bootdir}/${name_fit}\0" \ + "partitions=" PARTS_DEFAULT + +/* Incorporate settings into the U-Boot environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + EXTRA_ENV_AM625_BOARD_SETTINGS \ + EXTRA_ENV_AM625_BOARD_SETTINGS_MMC + +/* Now for the remaining common defines */ +#include <configs/ti_armv7_common.h> + +#endif /* __CONFIG_AM625_EVM_H */ diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index d84a8db97e..140940730d 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -18,37 +18,6 @@ /* DDR Configuration */ #define CONFIG_SYS_SDRAM_BASE1 0x880000000 -#ifdef CONFIG_SYS_K3_SPL_ATF -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" -#endif - -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE -#if defined(CONFIG_TARGET_AM642_A53_EVM) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) -#else -/* - * Maximum size in memory allocated to the SPL BSS. Keep it as tight as - * possible (to allow the build to go through), as this directly affects - * our memory footprint. The less we use for BSS the more we have available - * for everything else. - */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x4000 -/* - * Link BSS to be within SPL in a dedicated region located near the top of - * the MCU SRAM, this way making it available also before relocation. Note - * that we are not using the actual top of the MCU SRAM as there is a memory - * location filled in by the boot ROM that we want to read out without any - * interference from the C context. - */ -#define CONFIG_SPL_BSS_START_ADDR (TI_SRAM_SCRATCH_BOARD_EEPROM_START -\ - CONFIG_SPL_BSS_MAX_SIZE) -/* Set the stack right below the SPL BSS section */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR -/* Configure R5 SPL post-relocation malloc pool in DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -#endif - #define PARTS_DEFAULT \ /* Linux partitions */ \ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" @@ -137,6 +106,4 @@ /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> -#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 - #endif /* __CONFIG_AM642_EVM_H */ diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index b1f9050f3f..0345160787 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -17,41 +17,6 @@ /* DDR Configuration */ #define CONFIG_SYS_SDRAM_BASE1 0x880000000 -/* SPL Loader Configuration */ -#ifdef CONFIG_TARGET_AM654_A53_EVM -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) -#else -/* - * Maximum size in memory allocated to the SPL BSS. Keep it as tight as - * possible (to allow the build to go through), as this directly affects - * our memory footprint. The less we use for BSS the more we have available - * for everything else. - */ -#define CONFIG_SPL_BSS_MAX_SIZE 0xc00 -/* - * Link BSS to be within SPL in a dedicated region located near the top of - * the MCU SRAM, this way making it available also before relocation. Note - * that we are not using the actual top of the MCU SRAM as there is a memory - * location filled in by the boot ROM that we want to read out without any - * interference from the C context. - */ -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ - CONFIG_SPL_BSS_MAX_SIZE) -/* Set the stack right below the SPL BSS section */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR -/* Configure R5 SPL post-relocation malloc pool in DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -#endif - -#ifdef CONFIG_SYS_K3_SPL_ATF -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" -#endif - -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define PARTS_DEFAULT \ /* Linux partitions */ \ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" @@ -98,14 +63,6 @@ "0 /lib/firmware/am65x-mcu-r5f0_0-fw " \ "1 /lib/firmware/am65x-mcu-r5f0_1-fw " -#ifdef CONFIG_TARGET_AM654_A53_EVM -#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD -#endif - #define EXTRA_ENV_AM65X_BOARD_SETTINGS_UBI \ "init_ubi=run args_all args_ubi; sf probe; " \ "ubi part ospi.rootfs; ubifsmount ubi:rootfs;\0" \ @@ -137,14 +94,11 @@ DEFAULT_FIT_TI_ARGS \ EXTRA_ENV_AM65X_BOARD_SETTINGS \ EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \ - EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD \ EXTRA_ENV_AM65X_BOARD_SETTINGS_UBI \ EXTRA_ENV_RPROC_SETTINGS \ EXTRA_ENV_DFUARGS \ BOOTENV -#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 - /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 898978eb96..3c9267b14e 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -32,9 +32,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* size of internal SRAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_SIZE 0x1000000 @@ -46,7 +43,6 @@ #define CONFIG_SYS_WRITE_SWAPPED_DATA /* reserve 128-4KB */ #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) #define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ diff --git a/include/configs/ap121.h b/include/configs/ap121.h index e1c2e06613..099aac5421 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -9,14 +9,10 @@ #define CONFIG_SYS_MHZ 200 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) /* Miscellaneous configurable options */ diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 37fc196514..60b9e779fa 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -9,14 +9,10 @@ #define CONFIG_SYS_MHZ 325 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) /* * Serial Port diff --git a/include/configs/ap152.h b/include/configs/ap152.h index 9f47633371..d165ead7bb 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -9,14 +9,10 @@ #define CONFIG_SYS_MHZ 375 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) /* * Serial Port diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index c8422264b7..c9f876f5da 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -60,24 +60,13 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - /* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ #define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ #define PHYS_SDRAM_2_SIZE SZ_2G /* 2 GB */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #endif /* __APALIS_IMX8_H */ diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index face78e1dd..6a4092a83e 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -19,12 +19,6 @@ #define FDT_MODULE "apalis-v1.2" #define FDT_MODULE_V1_0 "apalis" -/* PCI host support */ -#undef CONFIG_PCI_SCAN_SHOW - -/* PCI networking support */ -#define CONFIG_E1000_NO_NVM - /* * Custom Distro Boot configuration: * 1. 8bit SD port (MMC1) @@ -89,18 +83,6 @@ "source ${loadaddr}\0" \ "vidargs=fbcon=map:1\0" -/* Increase console I/O buffer size */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -/* Increase arguments buffer size */ -#undef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Increase maximum number of arguments */ -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 32 - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index aa93d10f85..4922b06330 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -25,20 +25,11 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_LBA48 -#endif - /* Network */ #define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */ /* USB Configs */ /* Host */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 /* Client */ @@ -56,7 +47,6 @@ #undef CONFIG_SERVERIP #define CONFIG_SERVERIP 192.168.10.1 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ @@ -66,9 +56,6 @@ #include <config_distro_bootcmd.h> #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START "" -#else /* CONFIG_SPL_BUILD */ -#define BOOTENV -#endif /* CONFIG_SPL_BUILD */ #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ @@ -119,10 +106,6 @@ "vidargs=mxc_hdmi.only_cea=1 fbmem=32M\0" /* Miscellaneous configurable options */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 48 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -131,9 +114,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #endif /* __CONFIG_H */ diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index d1d518a534..84bd88f835 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -23,21 +23,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* PCI networking support */ -#define CONFIG_E1000_NO_NVM - -/* Increase console I/O buffer size */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -/* Increase arguments buffer size */ -#undef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Increase maximum number of arguments */ -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 32 - #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ "uboot_blk=0\0" \ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 8ee97f1d4e..8997c6a0ea 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -14,10 +14,8 @@ #define CONFIG_HOSTNAME "aristainetos2" #if (CONFIG_SYS_BOARD_VERSION == 5) -#define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" #elif (CONFIG_SYS_BOARD_VERSION == 6) -#define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" #endif @@ -112,9 +110,6 @@ "splashpos=m,m\0" \ "console=" CONSOLE_DEV "\0" \ "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ - "mtdids=nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor)\0" \ "mk_fitfile_path=setenv fit_file /${sysnum}/system.itb\0" \ "mk_rescue_fitfile_path=setenv rescue_fit_file /${rescue_sysnum}/system.itb\0" \ "mk_uboot_path=setenv uboot /${sysnum}/u-boot.imx\0" \ @@ -417,17 +412,11 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define CONFIG_SYS_FSL_USDHC_NUM 2 /* DMA stuff, needed for GPMI/MXS NAND support */ /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index acd140ee35..1c7494183a 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -20,16 +20,14 @@ #define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4) /* STACK */ -#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000 #define STACK_AREA_SIZE 0xC000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define ARMADILLO_800EVA_SDRAM_BASE 0x40000000 #define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024) -#define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ @@ -48,7 +46,6 @@ #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_MAX_FLASH_SECT 512 #define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 5109f7de53..7a244769e3 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -14,16 +14,9 @@ #include "exynos5250-common.h" #include <configs/exynos5-common.h> -/* MMC SPL */ -#define CONFIG_EXYNOS_SPL - /* Miscellaneous configurable options */ -#define CONFIG_IRAM_STACK 0x02050000 - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK -#define CONFIG_S5P_PA_SYSRAM 0x02020000 -#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM +#define CONFIG_SMP_PEN_ADDR 0x02020000 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index 0954bc02aa..5c9005805e 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -24,11 +24,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE) #endif -#define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \ - + CONFIG_SYS_INIT_RAM_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \ - - GENERATED_GBL_DATA_SIZE) - /* * NS16550 Configuration */ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 9d1203f397..a8265e961a 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -65,8 +65,6 @@ #define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 #define CONFIG_SYS_CORE_SRAM 0x80000000 -#define CONFIG_SYS_UNIFY_CACHE - /* * Define baudrate for UART1 (console output, tftp, ...) * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud @@ -133,7 +131,6 @@ * it needs non-blocking CFI routines. */ -#define CONFIG_FPGA_COUNT 1 #define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_WAIT 1000 @@ -162,9 +159,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Start addresses for the final memory configuration @@ -204,8 +198,6 @@ /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index f5cc0b2b91..ef9335c523 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -34,17 +34,11 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ +#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #ifdef CONFIG_AT91SAM9XE -# define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM #else -# define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 #endif /* NAND flash */ @@ -59,12 +53,6 @@ #endif /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 2089fe52e4..12726c10bd 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -26,8 +26,8 @@ /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -51,16 +51,6 @@ #define CONFIG_DM9000_NO_SROM /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ -#ifdef CONFIG_AT91SAM9G10EK -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10" -#else -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" -#endif -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index b63cd4bb83..9497f05503 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -33,8 +33,8 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NOR flash, if populated */ #ifdef CONFIG_SYS_USE_NORFLASH @@ -173,12 +173,6 @@ #endif /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 38b9061080..b55d2e3925 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -23,9 +23,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x70000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -40,23 +37,10 @@ #endif -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE 0x010000 -#define CONFIG_SPL_STACK 0x310000 - #define CONFIG_SYS_MONITOR_LEN 0x80000 #ifdef CONFIG_SD_BOOT - -#define CONFIG_SPL_BSS_START_ADDR 0x70000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 -#define CONFIG_SYS_SPL_MALLOC_START 0x70080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - #elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 #define CONFIG_SYS_NAND_ECCSIZE 256 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 7d378177b0..4d492988eb 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -22,14 +22,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ -# define CONFIG_SYS_INIT_SP_ADDR \ - (0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - /* DataFlash */ /* NAND flash */ @@ -44,29 +36,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" -/* USB host */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x6000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) @@ -75,8 +48,4 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index e0aeae88d1..e418edddfb 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -22,15 +22,13 @@ /* LCD */ #define LCD_BPP LCD_COLOR8 -/* Let board_init_f handle the framebuffer allocation */ -#undef CONFIG_FB_ADDR /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 013c7cfc59..0e7665843d 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -23,9 +23,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - /* DataFlash */ /* NAND flash */ @@ -41,27 +38,7 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#ifndef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#endif -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x6000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) @@ -70,8 +47,4 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index ba314026ce..daa5cdf5b2 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -7,16 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_SPL -#define CONFIG_SPL_MAX_SIZE 0x00100000 -#define CONFIG_SPL_BSS_START_ADDR 0x04000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 - -#ifdef CONFIG_SPL_MMC -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" -#endif -#endif - #define RISCV_MMODE_TIMERBASE 0xe6000000 #define RISCV_MMODE_TIMER_FREQ 60000000 @@ -29,26 +19,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* - * Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* - * max number of command args - */ -#define CONFIG_SYS_MAXARGS 16 - -/* - * Boot Argument Buffer Size - */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* DT blob (fdt) address */ -#define CONFIG_SYS_FDT_BASE 0x800f0000 /* * Physical Memory Map @@ -70,13 +40,6 @@ #define CONFIG_SYS_NS16550_CLK 19660800 /* Init Stack Pointer */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \ - GENERATED_GBL_DATA_SIZE) - -/* use CFI framework */ - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* support JEDEC */ #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ @@ -110,7 +73,6 @@ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Increase max gunzip size */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Support autoboot from RAM (kernel image is loaded via debug port) */ #define KERNEL_IMAGE_ADDR "0x2000000 " diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index cb400be77a..f2357b5785 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -23,11 +23,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_512M -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_128M - /* * UART configuration */ @@ -42,8 +37,6 @@ /* * USB 1.1 configuration */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 /* * Environment settings diff --git a/include/configs/baltos.h b/include/configs/baltos.h index b881d8c03f..266b2ae04b 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -24,20 +24,17 @@ #define V_SCLK (V_OSCK) /* FIT support */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M #ifdef CONFIG_MTD_RAW_NAND #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "${mtdparts} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=5\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "setenv loadaddr 0x84000000; " \ @@ -52,7 +49,6 @@ #define NANDARGS "" #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "boot_fdt=try\0" \ @@ -183,7 +179,6 @@ "findfdt=setenv fdtfile am335x-baltos.dtb\0" \ NANDARGS /*DFUARGS*/ -#endif /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ diff --git a/include/configs/bcm947622.h b/include/configs/bcm947622.h new file mode 100644 index 0000000000..d0c46a2c82 --- /dev/null +++ b/include/configs/bcm947622.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2022 Broadcom Ltd. + */ + +#ifndef __BCM947622_H +#define __BCM947622_H + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +#define COUNTER_FREQUENCY 50000000 +#endif diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 81b4218c88..795de46938 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -23,23 +23,15 @@ * Just before re-loaction, new SP is updated and re-location happens. * So pointing the initial SP to end of 2GB DDR is not a problem */ -#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x80000000) /* 12MB Malloc size */ /* console configuration */ #define CONFIG_SYS_NS16550_CLK 25000000 -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* * Increase max uncompressed/gunzip size, keeping size same as EMMC linux * partition. */ -#define CONFIG_SYS_BOOTM_LEN 0x01800000 /* Access eMMC Boot_1 and Boot_2 partitions */ diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 98c815961c..134a3ec289 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -83,20 +83,14 @@ extern phys_addr_t prior_stage_fdt_address; */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) /* * CONFIG_SYS_LOAD_ADDR - 1 MiB. */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 32 /* * Large kernel image bootm configuration. */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* * NS16550 configuration. diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h index 2bcd0e1a98..829e816ad6 100644 --- a/include/configs/bitmain_antminer_s9.h +++ b/include/configs/bitmain_antminer_s9.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_SDRAM_SIZE 0x40000000 #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ "pxefile_addr_r=0x2000000\0" \ "scriptaddr=0x3000000\0" \ "kernel_addr_r=0x2000000\0" \ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index bd07b4b031..925a68787c 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -67,7 +67,6 @@ /* Extra env settings (including the target-defined ones if any) */ #define CONFIG_EXTRA_ENV_SETTINGS \ BK4_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "blimg_file=u-boot.vyb\0" \ @@ -81,7 +80,6 @@ "nfs_root=/path/to/nfs/root\0" \ "tftptimeout=1000\0" \ "tftptimeoutcountmax=1000000\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "ipaddr=192.168.0.60\0" \ "serverip=192.168.0.1\0" \ "bootargs_base=setenv bootargs rw " \ @@ -213,9 +211,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #endif /* __CONFIG_H */ diff --git a/include/configs/blanche.h b/include/configs/blanche.h index 4f8da59404..25b6e7005e 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -12,10 +12,9 @@ #include "rcar-gen2-common.h" /* STACK */ -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -28,7 +27,6 @@ #if !defined(CONFIG_MTD_NOR_FLASH) #define CONFIG_SH_QSPI_BASE 0xE6B10000 #else -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index 412471a4aa..55c1d439d5 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index 8caddf3846..f046b7e662 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index 892a3e2c41..7e488072ed 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index af1c3673fb..f704fe26ca 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -14,13 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index 6cb09492aa..9aaa694cad 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index 92ab0ba7a2..34e542544c 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index 8a22dc1a3c..0319124a0e 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 899a538082..7e358a6314 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -12,9 +12,4 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K -#define CONFIG_SYS_CBSIZE SZ_512 - #endif /* __CONFIG_BMIPS_COMMON_H */ diff --git a/include/configs/boston.h b/include/configs/boston.h index 3bf85b6c28..8b04492753 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -9,7 +9,6 @@ /* * General board configuration */ -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* * CPU diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h index 5aa784d88c..0c8d352be9 100644 --- a/include/configs/broadcom_bcm963158.h +++ b/include/configs/broadcom_bcm963158.h @@ -13,8 +13,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } /* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_BOOTM_LEN (16 * 1024 * 1024) /* * 63158 @@ -24,7 +22,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* U-Boot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/broadcom_bcm96753ref.h b/include/configs/broadcom_bcm96753ref.h index c002985cf4..33c70c73c1 100644 --- a/include/configs/broadcom_bcm96753ref.h +++ b/include/configs/broadcom_bcm96753ref.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } /* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 /* * 6853 @@ -23,7 +22,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* U-Boot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/broadcom_bcm968360bg.h b/include/configs/broadcom_bcm968360bg.h index 01bab046dd..8a80235712 100644 --- a/include/configs/broadcom_bcm968360bg.h +++ b/include/configs/broadcom_bcm968360bg.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } /* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 /* * 6858 @@ -23,7 +22,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* U-Boot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h index ebfc2ecc0b..abc2da3d1f 100644 --- a/include/configs/broadcom_bcm968580xref.h +++ b/include/configs/broadcom_bcm968580xref.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } /* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 /* * 6858 @@ -23,7 +22,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* U-Boot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 769b3f073a..789e6a4c9d 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -16,7 +16,6 @@ #include <linux/stringify.h> /* ------------------------------------------------------------------------- */ /* memory */ -#define CONFIG_SYS_BOOTM_LEN SZ_32M /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ @@ -29,16 +28,8 @@ */ #ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 - /* RAW SD card / eMMC */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ -/* NAND */ -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000 -#endif /* CONFIG_MTD_RAW_NAND */ #endif /* CONFIG_SPL_OS_BOOT */ #ifdef CONFIG_MTD_RAW_NAND @@ -47,8 +38,6 @@ #ifdef CONFIG_MTD_RAW_NAND #define NANDTGTS \ -"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ -"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \ " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \ "nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \ @@ -107,11 +96,9 @@ MMCSPI_TGTS \ #define LOAD_OFFSET(x) 0x8##x -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ "verify=no\0" \ -"autoload=0\0" \ "scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \ "cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \ "dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \ @@ -131,7 +118,6 @@ NANDTGTS \ "b_default=run b_deftgts; for target in ${b_tgts};"\ " do echo \"### booting ${target} ###\"; run b_${target};" \ " if test ${b_break} = 1; then; exit; fi; done\0" -#endif /* !CONFIG_SPL_BUILD*/ #ifdef CONFIG_MTD_RAW_NAND /* diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 92f69ba9b0..adaba410ce 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -29,7 +29,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ -"autoload=0\0" \ "cfgaddr=0x106F0000\0" \ "scraddr=0x10700000\0" \ "loadaddr=0x10800000\0" \ @@ -81,16 +80,11 @@ BUR_COMMON_ENV \ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Ethernet */ #define CONFIG_FEC_FIXED_SPEED _1000BASET /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) /* SPL */ diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h index f1e6dbf613..f9908352b0 100644 --- a/include/configs/brsmarc1.h +++ b/include/configs/brsmarc1.h @@ -18,18 +18,14 @@ /* ------------------------------------------------------------------------- */ /* memory */ -#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD - /* Default environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ -"autoload=0\0" \ "scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "cfgscr=mw ${dtbaddr} 0;" \ " sf probe && sf read ${scradr} 0xC0000 0x10000 && source ${scradr};" \ @@ -56,7 +52,6 @@ BUR_COMMON_ENV \ " fdt boardsetup\0" \ "startsys=run vxargs && mw 0x80001100 0 && run vxfdt &&" \ " bootm ${loadaddr} - ${dtbaddr}\0" -#endif /* !CONFIG_SPL_BUILD*/ /* SPI Flash */ diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index d34d69778f..4d91a776ba 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -23,12 +23,9 @@ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD - /* Default environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ -"autoload=0\0" \ "scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootaddr=0x80001100\0" \ "bootdev=cpsw(0,0)\0" \ @@ -51,7 +48,6 @@ BUR_COMMON_ENV \ "b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}\0" \ "b_default=run b_deftgts; for target in ${b_tgts};"\ " do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" -#endif /* !CONFIG_SPL_BUILD*/ /* Environment */ diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 5fc8ce622b..a6de28a42b 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -24,7 +24,6 @@ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include <asm/arch/omap.h> @@ -37,8 +36,6 @@ * Y-MODEM to load u-boot.img, when booted over UART. We must also include * the scratch space that U-Boot uses in SRAM. */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) /* * Since SPL did pll and ddr initialization for us, @@ -51,8 +48,6 @@ * and we place the initial stack pointer in our SRAM. */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) /* * Our platforms make use of SPL to initalize the hardware (primarily @@ -73,11 +68,6 @@ * * ---------------------------------------------------------------------------- */ -#define CONFIG_SPL_BSS_START_ADDR 0x80A00000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN /* General parts of the framework, required. */ diff --git a/include/configs/bur_cfg_common.h b/include/configs/bur_cfg_common.h index 6985011763..304abc6d2e 100644 --- a/include/configs/bur_cfg_common.h +++ b/include/configs/bur_cfg_common.h @@ -27,10 +27,4 @@ /* As stated above, the following choices are optional. */ -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 - #endif /* __BUR_CFG_COMMON_H__ */ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 364bd50b59..6b1e82ad3b 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -15,36 +15,22 @@ /* SPL config */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SPL_STACK 0x013E000 -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ #define CONFIG_MALLOC_F_ADDR 0x00120000 -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE - #endif /* CONFIG_SPL_BUILD */ -#define CONFIG_FACTORYSET - /* ENET1 connects to base board and MUX with ESAI */ #define CONFIG_FEC_ENET_DEV 1 #define CONFIG_FEC_MXC_PHYADDR 0x0 -/* I2C Configuration */ -#ifndef CONFIG_SPL_BUILD /* EEPROM */ #define EEPROM_I2C_BUS 0 /* I2C0 */ #define EEPROM_I2C_ADDR 0x50 /* PCA9552 */ #define PCA9552_1_I2C_BUS 1 /* I2C1 */ #define PCA9552_1_I2C_ADDR 0x60 -#endif /* !CONFIG_SPL_BUILD */ /* AHAB */ #ifdef CONFIG_AHAB_BOOT @@ -106,7 +92,6 @@ ENV_NET /* Default location for tftp and bootm */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 /* On CCP board, USDHC1 is for eMMC */ @@ -117,11 +102,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ -/* Console buffer and boot args */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - #define BOOTAUX_RESERVED_MEM_BASE 0x88000000 #define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 4c04bbf644..6ac8487851 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -12,20 +12,11 @@ #include <asm/arch/imx-regs.h> #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SPL_STACK 0x013E000 -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_MALLOC_F_ADDR 0x00120000 -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE - -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* Flat Device Tree Definitions */ @@ -120,8 +111,6 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - #define CONFIG_SYS_FSL_USDHC_NUM 3 #define CONFIG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index 82acda595f..965eba58b3 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -13,14 +13,12 @@ #define V_SCLK (V_OSCK) #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} ${optargs} " \ "${mtdparts} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${fdt_addr} NAND.u-boot-spl-os; " \ @@ -107,8 +105,6 @@ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* SPL */ -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE /* NAND: device related configs */ /* NAND: driver related configs */ diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 96d5cf1a33..0787359674 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -15,6 +15,4 @@ #include <configs/x86-common.h> #include <configs/x86-chromebook.h> -#define CONFIG_SPL_BOARD_LOAD_IMAGE - #endif /* __CONFIG_H */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h index cc70a59e72..192da015e1 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -15,7 +15,6 @@ /* Memory configuration */ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 @@ -28,22 +27,6 @@ #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE + 2) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - /* Miscellaneous configuration options */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - -/* SPL */ -#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */ - -#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00) - -#define CONFIG_SPL_BSS_START_ADDR 0xf4004000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */ - -#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx" #endif /* __CONFIG_CI20_H__ */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 4b494d8aee..1043eb7506 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -26,13 +26,9 @@ #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } -#undef CONFIG_SYS_AUTOLOAD #undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_SYS_AUTOLOAD "no" - #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=off\0" \ "script=boot.scr\0" \ "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \ "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \ @@ -90,11 +86,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* SPI Flash support */ /* FLASH and environment organization */ @@ -107,10 +98,8 @@ #endif /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* SPL */ #include "imx7_spl.h" diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 871e87c26d..9c9e9506dc 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -18,8 +18,6 @@ * U-Boot into it. */ -#define CONFIG_ENV_MIN_ENTRIES 128 - /* Environment in MMC */ /* * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC @@ -30,39 +28,11 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* SPL */ - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA) -/* SPL related MMC defines */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -#endif -#endif - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -70,8 +40,6 @@ #include "mv-common.h" /* Include the common distro boot environment */ -#ifndef CONFIG_SPL_BUILD - #ifdef CONFIG_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) #else @@ -148,6 +116,4 @@ "console=ttyS0,115200\0" \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ - #endif /* _CONFIG_CLEARFOG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 600999b8e7..cbba726440 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -24,17 +24,12 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Serial console */ #define CONFIG_MXC_UART_BASE UART4_BASE /* Environment */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -48,7 +43,6 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" \ "panel=HDMI\0" \ - "autoload=no\0" \ "uImage=uImage-cm-fx6\0" \ "zImage=zImage-cm-fx6\0" \ "kernel=uImage-cm-fx6\0" \ @@ -59,8 +53,6 @@ "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ "doboot=bootm ${kernel_addr_r}\0" \ "doloadfdt=false\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "setboottypez=setenv kernel ${zImage};" \ "setenv doboot bootz ${kernel_addr_r} - ${fdt_addr_r};" \ "setenv doloadfdt true;\0" \ @@ -134,16 +126,11 @@ func(SATA, sata, 0) #include <config_distro_bootcmd.h> -#else -#define CONFIG_EXTRA_ENV_SETTINGS -#endif /* NAND */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* APBH DMA is required for NAND support */ -#endif /* Ethernet */ #define CONFIG_FEC_MXC_PHYADDR 0 @@ -151,13 +138,6 @@ /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ - -/* SATA */ -#define CONFIG_LBA48 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR /* Boot */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index ad2e881890..4baf7f7e24 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -19,7 +19,6 @@ #define V_OSCK 25000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD #define MMCARGS \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ @@ -32,8 +31,6 @@ "bootm ${loadaddr}\0" #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandroot=ubi0:rootfs rw\0" \ "nandrootfstype=ubifs\0" \ "nandargs=setenv bootargs console=${console} " \ @@ -55,9 +52,6 @@ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ MMCARGS \ NANDARGS -#endif /* CONFIG_SPL_BUILD */ - -#define CONFIG_SYS_AUTOLOAD "no" /* Serial console configuration */ @@ -86,9 +80,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000 -#endif /* GPIO pin + bank to pin ID mapping */ #define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin) @@ -98,7 +89,6 @@ /* EEPROM */ -#ifndef CONFIG_SPL_BUILD /* * Enable PCA9555 at I2C0-0x26. * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command. @@ -106,6 +96,5 @@ #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_ADDR 0x26 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} } -#endif /* CONFIG_SPL_BUILD */ #endif /* __CONFIG_CM_T335_H */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index eb015e1b20..07c5cb8ded 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -56,7 +56,6 @@ "loadaddr=0x80200000\0" \ "fdtaddr=0x81200000\0" \ "bootm_size=0x8000000\0" \ - "autoload=no\0" \ "console=ttyO0,115200n8\0" \ "fdtfile=am437x-sb-som-t43.dtb\0" \ "kernel=zImage-cm-t43\0" \ @@ -76,7 +75,6 @@ "bootz ${loadaddr} - ${fdtaddr}\0" /* SPL defines. */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* EEPROM */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 1822ce5120..dd7b6c0873 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -85,15 +85,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text); -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* *----------------------------------------------------------------------------- * Define user parameters that have to be customized most likely @@ -157,7 +148,6 @@ enter a valid image address in flash */ * --- */ -#define CONFIG_SYS_DISCOVER_PHY #define CONFIG_SYS_ENET_BD_BASE 0x780000 /*----------------------------------------------------------------------- @@ -165,8 +155,6 @@ enter a valid image address in flash */ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -190,7 +178,6 @@ enter a valid image address in flash */ #define CONFIG_SYS_FLASH_BASE 0xffe00000 #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 9e5212acb2..04cde9530a 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -65,7 +65,6 @@ #define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5" #define MODULE_EXTRA_ENV_SETTINGS \ "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ UBI_BOOTCMD #else #define MODULE_EXTRA_ENV_SETTINGS "" @@ -91,7 +90,6 @@ UBI_BOOTCMD \ UBOOT_UPDATE \ "boot_script_dhcp=boot.scr\0" \ - "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=user_debug=30\0" \ "fdt_board=eval-v3\0" \ @@ -122,16 +120,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#if defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SIZE) -#endif - #ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -140,11 +128,9 @@ #endif /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USBD_HS diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 3ed89c2776..5d6449c7f7 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -91,28 +91,17 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - /* Environment in eMMC, before config block at the end of 1st "boot sector" */ /* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ #define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - /* Generic Timer Definitions */ #define BOOTAUX_RESERVED_MEM_BASE 0x88000000 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 9ca6bef192..3c220e0d6e 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -27,8 +27,6 @@ /* USB Configs */ /* Host */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 /* Client */ @@ -46,7 +44,6 @@ #undef CONFIG_SERVERIP #define CONFIG_SERVERIP 192.168.10.1 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ @@ -55,9 +52,6 @@ #include <config_distro_bootcmd.h> #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START "" -#else /* CONFIG_SPL_BUILD */ -#define BOOTENV -#endif /* CONFIG_SPL_BUILD */ #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ @@ -106,10 +100,6 @@ "vidargs=fbmem=8M\0" /* Miscellaneous configurable options */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 48 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -118,9 +108,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 3dba7bcef2..9543e0233e 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -102,7 +102,6 @@ #if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) #define MODULE_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ UBI_BOOTCMD #elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) #define MODULE_EXTRA_ENV_SETTINGS \ @@ -131,7 +130,6 @@ UBOOT_UPDATE \ "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ - "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=\0" \ "fdt_board=eval-v3\0" \ @@ -166,16 +164,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#if defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SIZE) -#endif - #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -184,11 +172,9 @@ #endif /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USBD_HS diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index f6b3ab1b04..73d1844421 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -25,21 +25,8 @@ /* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ #define BOARD_EXTRA_ENV_SETTINGS \ "boot_script_dhcp=boot.scr\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ UBOOT_UPDATE -/* Increase console I/O buffer size */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -/* Increase arguments buffer size */ -#undef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Increase maximum number of arguments */ -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 32 - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index 1ce0def4dd..c9d384e2bd 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -24,18 +24,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* Increase console I/O buffer size */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -/* Increase arguments buffer size */ -#undef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Increase maximum number of arguments */ -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 32 - #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ "uboot_blk=0\0" \ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 99b0cbb342..268afbb7fa 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -68,7 +68,6 @@ "fdt_board=eval-v3\0" \ "fdt_fixup=;\0" \ "kernel_image=zImage\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "setsdupdate=mmc rescan && set interface mmc && " \ "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ @@ -82,8 +81,6 @@ "video-mode=dcufb:640x480-16@60,monitor=lcd\0" /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Physical memory map */ #define PHYS_SDRAM (0x80000000) @@ -93,19 +90,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_RANGE (4 * 64 * 2048) -#endif - /* USB Host Support */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* USB DFU */ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index b499d7085f..5da2778b67 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -17,49 +17,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* SPL */ -/* - * Select the boot device here - * - * Currently supported are: - * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash - * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) - */ -#define SPL_BOOT_SPI_NOR_FLASH 1 -#define SPL_BOOT_SDIO_MMC_CARD 2 -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (160 << 10) - -#if defined(CONFIG_SECURED_MODE_IMAGE) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614) -#else -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30) -#endif - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD -/* SPL related MMC defines */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -#endif -#endif - /* * Environment Configuration */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 121963fe5c..4eeca47c25 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -15,17 +15,8 @@ #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL -#ifdef CONFIG_NXP_ESBC #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_RAMBOOT_NAND -#endif -#define CONFIG_BOOTSCRIPT_COPY_RAM -#else -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -37,33 +28,21 @@ #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#endif /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* @@ -94,7 +73,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ @@ -139,10 +117,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_BASE 0xffa00000 @@ -194,8 +168,7 @@ #endif #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -334,22 +307,6 @@ #define CONFIG_SYS_DPAA_PME #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d @@ -372,16 +329,6 @@ #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_HAS_FSL_MPH_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT @@ -397,7 +344,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h new file mode 100644 index 0000000000..38d7fe8d0d --- /dev/null +++ b/include/configs/corstone1000.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2022 ARM Limited + * (C) Copyright 2022 Linaro + * Rui Miguel Silva <rui.silva@linaro.org> + * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> + * + * Configuration for Corstone1000. Parts were derived from other ARM + * configurations. + */ + +#ifndef __CORSTONE1000_H +#define __CORSTONE1000_H + +#include <linux/sizes.h> + +#define V2M_BASE 0x80000000 + +#define CONFIG_PL011_CLOCK 50000000 + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 (V2M_BASE) +#define PHYS_SDRAM_1_SIZE 0x80000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#endif diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 4809b59ecc..698da6b6da 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -35,9 +35,6 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE) - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -57,14 +54,7 @@ /* bootstrap + u-boot + env in nandflash */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (12 * SZ_1K) -#define CONFIG_SPL_STACK (SZ_16K) - -#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K) -#define CONFIG_SPL_NAND_RAW_ONLY -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE @@ -81,7 +71,4 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO - #endif diff --git a/include/configs/crs3xx-98dx3236.h b/include/configs/crs3xx-98dx3236.h index 4dbc758266..25bcc2a684 100644 --- a/include/configs/crs3xx-98dx3236.h +++ b/include/configs/crs3xx-98dx3236.h @@ -10,8 +10,6 @@ * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* 64 MB */ - /* Environment in SPI NOR flash */ /* Keep device tree and initrd in lower memory so the kernel can access them */ @@ -24,7 +22,5 @@ * to enable certain macros */ #include "mv-common.h" -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 96 #endif /* _CONFIG_CRS3XX_98DX3236_H */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 855711e629..3db97205da 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -32,8 +32,6 @@ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ -#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE -#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 /* memtest start addr */ /* memtest will be run on 16MB */ @@ -103,9 +101,7 @@ /* * I2C Configuration */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 -#endif /* * Flash & Environment @@ -148,8 +144,6 @@ /* * U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ /* * Linux Information @@ -176,21 +170,8 @@ "console=ttyS2,115200n8\0" \ "hwconfig=dsp:wake=yes" -/* USB Configs */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -#ifndef CONFIG_MTD_NOR_FLASH -#define CONFIG_SPL_PAD_TO 32768 -#endif - #ifdef CONFIG_SPL_BUILD /* defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SPL_STACK 0x8001ff00 -#define CONFIG_SPL_MAX_FOOTPRINT 32768 #endif @@ -199,13 +180,6 @@ /* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) -#endif /* CONFIG_MTD_NOR_FLASH */ - #include <asm/arch/hardware.h> #endif /* __CONFIG_H */ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index ad28fa0120..36052fe7d8 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -49,16 +49,9 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 16c83a88da..ef9c457e10 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -20,7 +20,6 @@ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ @@ -34,16 +33,5 @@ /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) #endif /* _CONFIG_DB_88F6720_H */ diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index 6538e66052..b9d03d253d 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -14,11 +14,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* NAND */ /* Keep device tree and initrd in lower memory so the kernel can access them */ @@ -26,39 +21,10 @@ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* SPL */ -/* - * Select the boot device here - * - * Currently supported are: - * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash - * - * MMC is not populated on this board. - * NAND support may be added in the future. - */ -#define SPL_BOOT_SPI_NOR_FLASH 1 -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros */ #include "mv-common.h" -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 96 #endif /* _CONFIG_DB_88F6820_AMC_H */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 8dc73e8b1c..bba2b607aa 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -17,49 +17,11 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* SPL */ -/* - * Select the boot device here - * - * Currently supported are: - * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash - * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) - */ -#define SPL_BOOT_SPI_NOR_FLASH 1 -#define SPL_BOOT_SDIO_MMC_CARD 2 -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD -/* SPL related MMC defines */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -#endif -#endif - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index d6850bd32e..7b305955c9 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -16,20 +16,11 @@ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* SATA support */ -#define CONFIG_LBA48 - -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* NAND */ /* @@ -53,17 +44,6 @@ /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_SPD_EEPROM 0x4e diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h index 1d242bf4e6..84ea1baa99 100644 --- a/include/configs/db-xc3-24g4xg.h +++ b/include/configs/db-xc3-24g4xg.h @@ -20,7 +20,5 @@ * to enable certain macros */ #include "mv-common.h" -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 96 #endif /* _CONFIG_DB_XC3_24G4G_H */ diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index bc5282a489..328e4958f8 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -18,9 +18,6 @@ #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_64M -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ - - GENERATED_GBL_DATA_SIZE) - /* * DMA */ @@ -58,14 +55,11 @@ /* * USB */ -#define CONFIG_USB_OHCI_LPC32XX #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d /* * U-Boot General Configurations */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* * Pass open firmware flat tree @@ -76,7 +70,6 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ "ethaddr=00:01:90:00:C0:81\0" \ "dtbaddr=0x81000000\0" \ "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ @@ -87,26 +80,6 @@ * U-Boot Commands */ -/* - * SPL specific defines - */ -/* SPL will be executed at offset 0 */ - -/* SPL will use SRAM as stack */ -#define CONFIG_SPL_STACK 0x0000FFF8 - -/* Use the framework and generic lib */ - -/* SPL will use serial */ - -/* SPL loads an image from NAND */ -#define CONFIG_SPL_NAND_RAW_ONLY - -#define CONFIG_SPL_NAND_SOFTECC - -#define CONFIG_SPL_MAX_SIZE 0x20000 -#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE - /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 5dbd126a2a..d45115bdf6 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -14,23 +14,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ - -#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - -/* Physical Memory Map */ - #include <configs/ti_omap3_common.h> /* Hardware drivers */ @@ -46,9 +29,12 @@ /* BOOTP/DHCP options */ +#define MEM_LAYOUT_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV + /* Environment information */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ + MEM_LAYOUT_ENV_SETTINGS \ "console=ttyO2,115200n8\0" \ "mmcdev=0\0" \ "vram=12M\0" \ @@ -111,8 +97,6 @@ "fi; " \ "else run nandboot; fi\0" -/* Boot Argument Buffer Size */ - /* Defines for SPL */ /* NAND boot config */ @@ -124,15 +108,4 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 -/* SPL OS boot options */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 - -#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR -#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ - -#undef CONFIG_SYS_SPL_ARGS_ADDR -#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) - #endif /* __CONFIG_H */ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 178f5a6e7d..79424647f6 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -23,29 +23,20 @@ /* SPL */ #include "imx6_spl.h" /* common IMX6 SPL configuration */ -#define CONFIG_SPL_TARGET "u-boot-with-spl.imx" /* Miscellaneous configurable options */ -/* Bootcounter */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 -/* SATA Configs */ -#define CONFIG_LBA48 - /* UART */ #define CONFIG_MXC_UART_BASE UART1_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ /* USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) @@ -57,7 +48,6 @@ #endif #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_addr=0x18000000\0" \ @@ -82,7 +72,6 @@ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -91,12 +80,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment */ #endif /* __DH_IMX6_CONFIG_H */ diff --git a/include/configs/display5.h b/include/configs/display5.h index 7bd653364d..c23a57ee7a 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -10,12 +10,8 @@ #include "mx6_common.h" /* Falcon Mode */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 /* Falcon Mode - MMC support */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x3F00 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS \ - (CONFIG_CMD_SPL_WRITE_SIZE / 512) /* * display5 SPI-NOR memory layout @@ -284,14 +280,6 @@ "\0" \ /* Miscellaneous configurable options */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 2048 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_STANDALONE_LOAD_ADDR 0x10001000 @@ -302,11 +290,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* ENV config */ #ifdef CONFIG_ENV_IS_IN_SPI_FLASH /* The 0x120000 value corresponds to above SPI-NOR memory MAP */ diff --git a/include/configs/dns325.h b/include/configs/dns325.h index 0590704000..015bc78648 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -40,9 +40,7 @@ "stdout=serial\0" \ "stderr=serial\0" \ "loadaddr=0x800000\0" \ - "autoload=no\0" \ "console=ttyS0,115200\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ "optargs=\0" \ "bootenv=uEnv.txt\0" \ "importbootenv=echo Importing environment ...; " \ diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 381a189149..33ae7d654b 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -24,8 +24,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/uImage\0" \ "initrd=/boot/uInitrd\0" \ "bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0" diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index e16af8824b..9247720f8b 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -84,18 +84,12 @@ 50, 51, 52, 53, 54, 55, 56, 57, } #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -/* NAND: SPL related configs */ -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ -#endif #endif /* !CONFIG_MTD_RAW_NAND */ /* Parallel NOR Support */ #if defined(CONFIG_NOR) /* NOR: device related configs */ #define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ #define CONFIG_SYS_FLASH_BASE (0x08000000) /* Reduce SPL size by removing unlikey targets */ diff --git a/include/configs/draak.h b/include/configs/draak.h index 476b4c3710..a38e486348 100644 --- a/include/configs/draak.h +++ b/include/configs/draak.h @@ -15,7 +15,6 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/draco.h b/include/configs/draco.h index d305608101..4869008da4 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -27,13 +27,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -#define CONFIG_FACTORYSET - -/* Define own nand partitions */ -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - -#ifndef CONFIG_SPL_BUILD - /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=draco\0" \ @@ -45,8 +38,4 @@ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif -#endif /* CONFIG_SPL_BUILD */ #endif /* ! __CONFIG_DRACO_H */ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 14ba52a2eb..c37b4c635b 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -18,15 +18,8 @@ /* Note: 8 MiB (0x86000000 - 0x86800000) are reserved for tz/smem/hyp/rmtfs/rfsa */ #define PHYS_SDRAM_1_SIZE SZ_1G #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -/* UART */ - -/* Fixup - in init code we switch from device to host mode, - * it has to be done after each HCD reset */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +/* Environment */ #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 1) \ @@ -35,47 +28,6 @@ #include <config_distro_bootcmd.h> -/* Does what recovery does */ -#define REFLASH(file, part) \ -"part start mmc 0 "#part" start && "\ -"part size mmc 0 "#part" size && "\ -"tftp $loadaddr "#file" && " \ -"mmc write $loadaddr $start $size && " - -#define CONFIG_ENV_REFLASH \ -"mmc dev 0 && "\ -"usb start && "\ -"dhcp && "\ -"tftp $loadaddr dragonboard/rescue/gpt_both0.bin && "\ -"mmc write $loadaddr 0 43 && " \ -"mmc rescan && "\ -REFLASH(dragonboard/rescue/NON-HLOS.bin, 1)\ -REFLASH(dragonboard/rescue/sbl1.mbn, 2)\ -REFLASH(dragonboard/rescue/rpm.mbn, 3)\ -REFLASH(dragonboard/rescue/tz.mbn, 4)\ -REFLASH(dragonboard/rescue/hyp.mbn, 5)\ -REFLASH(dragonboard/rescue/sec.dat, 6)\ -REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7)\ -REFLASH(dragonboard/u-boot.img, 8)\ -"usb stop &&"\ -"echo Reflash completed" - -/* Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "reflash="CONFIG_ENV_REFLASH"\0"\ - "loadaddr=0x81000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "linux_image=Image\0" \ - "kernel_addr_r=0x81000000\0"\ - "fdtfile=qcom/apq8016-sbc.dtb\0" \ - "fdt_addr_r=0x83000000\0"\ - "ramdisk_addr_r=0x84000000\0"\ - "scriptaddr=0x90000000\0"\ - "pxefile_addr_r=0x90100000\0"\ - BOOTENV - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ +#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV #endif diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index 1e2b15b33f..1fa5d05e7b 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -20,12 +20,8 @@ #define PHYS_SDRAM_2_SIZE 0x5ea4ffff #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#ifndef CONFIG_SPL_BUILD #include <config_distro_bootcmd.h> -#endif #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) @@ -43,8 +39,4 @@ "pxefile_addr_r=0x90100000\0"\ BOOTENV -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 64 - #endif diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 07e2b8781f..fbd83d629c 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -30,9 +30,4 @@ #define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ #define CONFIG_PHY_BASE_ADR 0 -/* - * SATA Driver configuration - */ -#define CONFIG_LBA48 - #endif /* _CONFIG_DREAMPLUG_H */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index dbccd46bbd..f8273a92f1 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -19,11 +19,6 @@ /* I2C */ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -45,17 +40,6 @@ /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* Default Environment */ diff --git a/include/configs/durian.h b/include/configs/durian.h index f0789d5fb3..8f0e8be433 100644 --- a/include/configs/durian.h +++ b/include/configs/durian.h @@ -13,13 +13,7 @@ #define PHYS_SDRAM_1_SIZE 0x7B000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (0x88000000 - 0x100000) - -/* PCI CONFIG */ -#define CONFIG_PCI_SCAN_SHOW - /* BOOT */ -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) #define CONFIG_EXTRA_ENV_SETTINGS \ "load_kernel=ext4load scsi 0:1 0x90100000 uImage-2004\0" \ diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h index 2d0e787879..1d655292d7 100644 --- a/include/configs/ea-lpc3250devkitv2.h +++ b/include/configs/ea-lpc3250devkitv2.h @@ -18,7 +18,6 @@ /* * cmd */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE) /* * SoC-specific config diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 28bf35ca98..6e444c4789 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -29,9 +29,6 @@ * Environment is in the second sector of the first 256k of flash * *----------------------------------------------------------------------*/ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /*#define CONFIG_SYS_DRAM_TEST 1 */ #undef CONFIG_SYS_DRAM_TEST @@ -50,7 +47,6 @@ *----------------------------------------------------------------------*/ #ifdef CONFIG_MCFFEC -#define CONFIG_SYS_DISCOVER_PHY #define CONFIG_OVERWRITE_ETHADDR_ONCE #endif @@ -68,9 +64,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -84,7 +77,6 @@ #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data @@ -106,7 +98,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 #define CONFIG_SYS_FLASH_SIZE 16*1024*1024 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index 3adc4180ef..3dc111f524 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -18,7 +18,6 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/edison.h b/include/configs/edison.h index 70cccc6fe6..34536ecf85 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -10,10 +10,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 128 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - #define CONFIG_SYS_STACK_SIZE (32 * 1024) #define CONFIG_SYS_MONITOR_LEN (256 * 1024) diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 8e2c24594f..8625701682 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -15,12 +15,6 @@ * SPL */ -#define CONFIG_SPL_MAX_SIZE 0x0000fff0 -#define CONFIG_SPL_STACK 0x00020000 -#define CONFIG_SPL_BSS_START_ADDR 0x00020000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff -#define CONFIG_SYS_SPL_MALLOC_START 0x00040000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff #define CONFIG_SYS_UBOOT_BASE 0xfff90000 #define CONFIG_SYS_UBOOT_START 0x00800000 @@ -90,8 +84,6 @@ /* auto boot */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - /* * Network */ @@ -109,8 +101,6 @@ #define __io /* Data, registers and alternate blocks are at the same offset */ /* Each 8-bit ATA register is aligned to a 4-bytes address */ -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 /* A single bus, a single device */ /* ATA registers base is at SATA controller base */ /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ @@ -141,7 +131,5 @@ /* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) #endif /* _CONFIG_EDMINIV2_H */ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index bcd7b84cf3..7fc3459ef2 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -58,11 +58,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #endif /* __EL6Q_COMMON_CONFIG_H */ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 1bf564c360..7526d3b0f5 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -18,7 +18,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 @@ -32,11 +31,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ #if defined(CONFIG_ENV_IS_IN_MMC) @@ -58,12 +52,6 @@ #ifdef CONFIG_SPL #include "imx6_spl.h" /* RiOTboard */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000 -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6dl-riotboard.dtb" - -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* offset 69KB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* offset 69KB */ #endif diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h index a560673512..60fab0419f 100644 --- a/include/configs/emsdp.h +++ b/include/configs/emsdp.h @@ -11,8 +11,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x10000000 #define CONFIG_SYS_SDRAM_SIZE SZ_16M -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M) - /* * Environment */ diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h index d936b7f09f..2f067a4424 100644 --- a/include/configs/espresso7420.h +++ b/include/configs/espresso7420.h @@ -10,11 +10,7 @@ #include <configs/exynos7420-common.h> -#define CONFIG_ESPRESSO7420 - #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SPL_STACK CONFIG_IRAM_END -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_END /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 9cf93924df..3acc62d9e1 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -75,20 +75,8 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_FACTORYSET - -/* use both define to compile a SPL compliance test */ -/* -#define CONFIG_SPL_CMT -#define CONFIG_SPL_CMT_DEBUG -*/ - /* nedded by compliance test in read mode */ -/* Define own nand partitions */ -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - - #undef COMMON_ENV_DFU_ARGS #define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \ "setenv bootargs ${bootargs};" \ @@ -113,7 +101,7 @@ "nand_active_ubi_vol=rootfs_a\0" \ "rootfs_name=rootfs\0" \ "kernel_name=uImage\0"\ - "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_root_fs_type=ubifs rootwait\0" \ "nand_args=run bootargs_defaults;" \ "mtdparts default;" \ "setenv ${partitionset_active} true;" \ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 3231f3cc03..88a702f1af 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -22,10 +22,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ /* 32kB internal SRAM */ -#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ -#define CONFIG_SRAM_SIZE (32 << 10) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */ +#define CONFIG_SYS_INIT_RAM_SIZE (32 << 10) /* 128MB SDRAM in 1 bank */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 @@ -34,7 +32,6 @@ /* 512kB on-chip NOR flash */ # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ # define CONFIG_SYS_MAX_FLASH_SECT 32 -# define CONFIG_EFLASH_PROTSECTORS 1 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -62,17 +59,6 @@ #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif - /* RTC */ #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) #define CONFIG_SYS_I2C_RTC_ADDR 0x51 @@ -101,11 +87,6 @@ #define I2C_DELAY udelay(100) #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) -/* DHCP/BOOTP options */ -#ifdef CONFIG_CMD_DHCP -#define CONFIG_SYS_AUTOLOAD "n" -#endif - /* File systems */ /* Boot command */ diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index 492b7b4df1..b7e850370b 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -15,7 +15,4 @@ #define SDRAM_BANK_SIZE (2UL << 30) -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - #endif diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index dd1cbd7ab8..246aa9b7ab 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -8,10 +8,6 @@ #ifndef __EXYNOS_COMMON_H #define __EXYNOS_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ - #include <asm/arch/cpu.h> /* get chip and board defs */ #include <linux/sizes.h> #include <linux/stringify.h> @@ -22,14 +18,6 @@ /* select serial console configuration */ -/* PWM */ -#define CONFIG_PWM - /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #endif /* __CONFIG_H */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 4202c62612..054cb5309e 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -8,8 +8,6 @@ #ifndef __CONFIG_EXYNOS4_COMMON_H #define __CONFIG_EXYNOS4_COMMON_H -#define CONFIG_EXYNOS4 /* Exynos4 Family */ - #include "exynos-common.h" /* SD/MMC configuration */ @@ -25,8 +23,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - /* Common environment variables */ #define ENV_ITB \ "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 7ab821d08c..44f5cb1e83 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -8,15 +8,8 @@ #ifndef __CONFIG_EXYNOS5_COMMON_H #define __CONFIG_EXYNOS5_COMMON_H -#define CONFIG_EXYNOS5 /* Exynos5 Family */ - #include "exynos-common.h" -#define CONFIG_EXYNOS_SPL - -/* Enable ACE acceleration for SHA1 and SHA256 */ -#define CONFIG_EXYNOS_ACE_SHA - /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 @@ -31,9 +24,6 @@ /* select serial console configuration */ #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -/* Thermal Management Unit */ -#define CONFIG_EXYNOS_TMU - /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index bcbdfa7ae3..a94f5a15f0 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -15,17 +15,8 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" -#define CONFIG_EXYNOS5_DT - #define CONFIG_SYS_SPI_BASE 0x12D30000 #define FLASH_SIZE (4 << 20) #define CONFIG_SPI_BOOTING -/* Display */ -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_BPP LCD_COLOR16 -#endif - #endif diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 36c3a613eb..8e2f135f93 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -9,21 +9,8 @@ #ifndef __CONFIG_5250_H #define __CONFIG_5250_H -#define CONFIG_EXYNOS5250 - #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_IRAM_STACK 0x02050000 - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK - -/* USB */ -#define CONFIG_USB_EHCI_EXYNOS - -#define CONFIG_USB_XHCI_EXYNOS - /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 51f9f22174..7a9307ccc3 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -8,27 +8,16 @@ #ifndef __CONFIG_EXYNOS5420_H #define __CONFIG_EXYNOS5420_H -#define CONFIG_EXYNOS5420 - -#define CONFIG_EXYNOS5_DT - #define CONFIG_VAR_SIZE_SPL #define CONFIG_IRAM_TOP 0x02074000 -#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) - #define CONFIG_PHY_IRAM_BASE 0x02020000 -/* Address for relocating helper code (Last 4 KB of IRAM) */ -#define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) - /* * Low Power settings */ #define CONFIG_LOWPOWER_FLAG 0x02020028 #define CONFIG_LOWPOWER_ADDR 0x0202002C -#define CONFIG_USB_XHCI_EXYNOS - #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index 5658da474c..a8bef860c2 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -8,19 +8,10 @@ #ifndef __CONFIG_EXYNOS7420_COMMON_H #define __CONFIG_EXYNOS7420_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P - #include <asm/arch/cpu.h> /* get chip and board defs */ #include <linux/sizes.h> /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* select serial console configuration */ diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h index ec43e133dd..b05846d0b9 100644 --- a/include/configs/exynos78x0-common.h +++ b/include/configs/exynos78x0-common.h @@ -11,19 +11,10 @@ #ifndef __CONFIG_EXYNOS78x0_COMMON_H #define __CONFIG_EXYNOS78x0_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P - #include <asm/arch/cpu.h> /* get chip and board defs */ #include <linux/sizes.h> /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CPU_RELEASE_ADDR secondary_boot_addr @@ -31,8 +22,6 @@ {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600} #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_BOOTM_LEN SZ_32M /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE diff --git a/include/configs/galileo.h b/include/configs/galileo.h index c50ecf27e4..49f57dda58 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -21,9 +21,6 @@ "stdout=serial\0" \ "stderr=serial\0" -/* 10/100M Ethernet support */ -#define CONFIG_DW_ALTDESCRIPTOR - /* Environment configuration */ #endif /* __CONFIG_H */ diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index 5e6a8ee770..331e9ca8ba 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -21,9 +21,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - /* NAND flash */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 @@ -36,13 +33,6 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x7000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) @@ -51,12 +41,8 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#define CONFIG_SPL_NAND_RAW_ONLY #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO - #endif diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 269bb93272..d21a9b9383 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -17,10 +17,6 @@ /* SPL */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x80010000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_PAD_TO 0 /* Dummy value */ #define CONFIG_SYS_UBOOT_BASE 0 @@ -39,11 +35,6 @@ /* RAM */ -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_CBSIZE 512 - /* Environment settings */ #endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */ diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 6b910d5519..25095e192f 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -33,8 +33,6 @@ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * FLASH on the Local Bus @@ -58,13 +56,6 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* * For booting Linux, the board info and command line data * have to be in the first 256 MB of memory, since this is diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index b4f94992e6..95ba20c686 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -13,7 +13,6 @@ #include "mx6_common.h" #include "imx6_spl.h" -#define CONFIG_SPL_TARGET "u-boot-with-spl.imx" /* PWM */ #define CONFIG_IMX6_PWM_PER_CLK 66000000 @@ -30,10 +29,8 @@ #endif /* USB */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ #define CONFIG_USBD_HS /* Video */ @@ -47,11 +44,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Command definition */ #define CONFIG_EXTRA_ENV_SETTINGS \ "image=/boot/fitImage\0" \ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index c80a07655e..ad00769bde 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -17,13 +17,6 @@ #include "mx6_common.h" #include <linux/sizes.h> -/* SATA Configs */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - #ifdef CONFIG_CMD_NFS #define NETWORKBOOT \ "setnetworkboot=" \ @@ -105,11 +98,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #define CONFIG_SYS_FSL_USDHC_NUM 3 @@ -121,7 +109,4 @@ #define CONFIG_IMX6_PWM_PER_CLK 66000000 -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX - #endif /* __GE_BX50V3_CONFIG_H */ diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 832441a7b7..66eed9e14f 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -33,8 +33,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/uImage\0" \ "bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0" @@ -44,7 +42,4 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -/* SATA driver configuration */ -#define CONFIG_LBA48 - #endif /* _CONFIG_GOFLEXHOME_H */ diff --git a/include/configs/gose.h b/include/configs/gose.h index 4ffa5bea8f..d1fe375a2c 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -10,10 +10,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -33,8 +32,4 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 - #endif /* __GOSE_H */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 347845f1d5..fb69716bcb 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -11,13 +11,10 @@ /* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ /* Miscellaneous */ -#define CONFIG_SYS_PBSIZE 256 /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) diff --git a/include/configs/gru.h b/include/configs/gru.h index b1084bb21d..be2dc79968 100644 --- a/include/configs/gru.h +++ b/include/configs/gru.h @@ -13,7 +13,4 @@ #include <configs/rk3399_common.h> -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - #endif diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index d5655e4ada..4954c5ca08 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -26,7 +26,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/zImage\0" \ "fdt=/boot/guruplug-server-plus.dtb\0" \ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 86d0fb60f1..82076ff74f 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -10,14 +10,8 @@ /* Location in NAND to read U-Boot from */ /* Falcon Mode */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - -/* Falcon Mode - NAND support: args@17MB kernel@18MB */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS (18 * SZ_1M) /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" @@ -28,27 +22,12 @@ /* NAND */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#undef CONFIG_SYS_BOOTM_LEN -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA - #define CONFIG_DWC_AHSATA_PORT_ID 0 - #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR - #define CONFIG_LBA48 -#endif - -/* * PCI express */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX -#endif /* * PMIC @@ -61,7 +40,6 @@ /* Various command support */ /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USBD_HS @@ -82,11 +60,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* * MTD Command for mtdparts */ @@ -97,154 +70,4 @@ #define CONFIG_IPADDR 192.168.1.1 #define CONFIG_SERVERIP 192.168.1.146 -#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "usb_pgood_delay=2000\0" \ - "console=ttymxc1\0" \ - "bootdevs=usb mmc sata flash\0" \ - "hwconfig=_UNKNOWN_\0" \ - "video=\0" \ - \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "disk=0\0" \ - "part=1\0" \ - \ - "fdt_high=0xffffffff\0" \ - "fdt_addr=0x18000000\0" \ - "initrd_high=0xffffffff\0" \ - "fixfdt=" \ - "fdt addr ${fdt_addr}\0" \ - "bootdir=boot\0" \ - "loadfdt=" \ - "if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file}; " \ - "run fixfdt; " \ - "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file1}; " \ - "run fixfdt; " \ - "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file2}; " \ - "run fixfdt; " \ - "fi\0" \ - \ - "fs=ext4\0" \ - "script=6x_bootscript-ventana\0" \ - "loadscript=" \ - "if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \ - "source ${loadaddr}; " \ - "fi\0" \ - \ - "uimage=uImage\0" \ - "mmc_root=mmcblk0p1\0" \ - "mmc_boot=" \ - "setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \ - "mmc dev ${disk} && mmc rescan && " \ - "setenv dtype mmc; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/${mmc_root} rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" \ - \ - "sata_boot=" \ - "setenv fsload \"${fs}load sata ${disk}:${part}\"; " \ - "sata init && " \ - "setenv dtype sata; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/sda1 rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" \ - "usb_boot=" \ - "setenv fsload \"${fs}load usb ${disk}:${part}\"; " \ - "usb start && usb dev ${disk} && " \ - "setenv dtype usb; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/sda1 rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" - -#ifdef CONFIG_SPI_FLASH - #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \ - "image_uboot=ventana/u-boot_spi.imx\0" \ - \ - "spi_koffset=0x90000\0" \ - "spi_klen=0x200000\0" \ - \ - "spi_updateuboot=echo Updating uboot from " \ - "${serverip}:${image_uboot}...; " \ - "tftpboot ${loadaddr} ${image_uboot} && " \ - "sf probe && sf erase 0 80000 && " \ - "sf write ${loadaddr} 400 ${filesize}\0" \ - "spi_update=echo Updating OS from ${serverip}:${image_os} " \ - "to ${spi_koffset} ...; " \ - "tftp ${loadaddr} ${image_os} && " \ - "sf probe && " \ - "sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \ - \ - "flash_boot=" \ - "if sf probe && " \ - "sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/mtdblock3 " \ - "rootfstype=squashfs,jffs2 " \ - "${video} ${extra}; " \ - "bootm; " \ - "fi\0" -#else - #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - \ - "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ - "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ - "tftp ${loadaddr} ${image_rootfs} && " \ - "nand erase.part rootfs && " \ - "nand write ${loadaddr} rootfs ${filesize}\0" \ - \ - "flash_boot=" \ - "setenv fsload 'ubifsload'; " \ - "ubi part rootfs; " \ - "if ubi check boot; then " \ - "ubifsmount ubi0:boot; " \ - "setenv root ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=squashfs,ubifs; " \ - "setenv bootdir; " \ - "elif ubi check rootfs; then " \ - "ubifsmount ubi0:rootfs; " \ - "setenv root ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=ubifs; " \ - "fi; " \ - "setenv dtype nand; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=${root} ${video} ${extra}; " \ - "if run loadfdt; then " \ - "ubifsumount; " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "ubifsumount; bootm; " \ - "fi; " \ - "fi\0" -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/gxp.h b/include/configs/gxp.h new file mode 100644 index 0000000000..e3c97b20d5 --- /dev/null +++ b/include/configs/gxp.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * GXP board + * + * (C) Copyright 2022 Hewlett Packard Enterprise Development LP. + * Author: Nick Hawkins <nick.hawkins@hpe.com> + * Author: Jean-Marie Verdun <verdun@hpe.com> + */ + +#ifndef _GXP_H_ +#define _GXP_H_ + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +#endif diff --git a/include/configs/helios4.h b/include/configs/helios4.h index 151ab66f4c..fc32487e1c 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -18,8 +18,6 @@ * U-Boot into it. */ -#define CONFIG_ENV_MIN_ENTRIES 128 - /* Environment in MMC */ /* * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC @@ -30,39 +28,11 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* SPL */ - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA) -/* SPL related MMC defines */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -#endif -#endif - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -70,8 +40,6 @@ #include "mv-common.h" /* Include the common distro boot environment */ -#ifndef CONFIG_SPL_BUILD - #ifdef CONFIG_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) #else @@ -149,6 +117,4 @@ "console=ttyS0,115200\0" \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ - #endif /* _CONFIG_HELIOS4_H */ diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 0ff70fdc66..bb6cc95726 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -14,15 +14,9 @@ #define CONFIG_PL011_CLOCK 150000000 -#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_64BIT_LBA /* Environment data setup */ @@ -30,7 +24,6 @@ #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x01000000 #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x20000000\0" \ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 19d5b6261f..5be6eb4e76 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -15,8 +15,6 @@ #define CONFIG_POWER_HI6553 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Physical Memory Map */ /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ @@ -30,8 +28,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xf6801000 #define GICC_BASE 0xf6802000 @@ -61,8 +57,4 @@ /* Preserve environment on eMMC */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - #endif /* __HIKEY_H */ diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index c088f2f2b6..ad070439d0 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -9,8 +9,6 @@ #include <linux/sizes.h> -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Physical Memory Map */ /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ @@ -22,8 +20,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xe82b1000 #define GICC_BASE 0xe82b2000 diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index d3d8896ecf..4af845ea9c 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -25,11 +25,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_1G -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_128M - /* * UART configuration */ @@ -42,12 +37,6 @@ */ /* - * USB 1.1 configuration - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -/* * Environment settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -105,7 +94,6 @@ setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" */ /* Cli configuration */ -#define CONFIG_SYS_CBSIZE SZ_2K /* * Callback configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 64dce52105..0ce65e7755 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -24,11 +24,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_1G -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_128M - /* * UART configuration */ @@ -41,12 +36,6 @@ */ /* - * USB 1.1 configuration - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -/* * Environment settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -100,7 +89,6 @@ setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \ setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" /* Cli configuration */ -#define CONFIG_SYS_CBSIZE SZ_2K /* * Callback configuration diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index aff948cfe7..05192218d2 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -20,8 +20,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/zImage\0" \ "fdt=/boot/ib62x0.dtb\0" \ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index cb4cf9beb7..f2e3608d3a 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -13,8 +13,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/uImage\0" \ "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 356bf6c636..a8bb2090ec 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -28,10 +28,6 @@ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Internal Definitions @@ -108,7 +104,6 @@ /* * NOR FLASH setup */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #define CONFIG_FLASH_SHOW_PROGRESS 50 #define CONFIG_SYS_FLASH_BASE 0xFF800000 @@ -169,7 +164,6 @@ #ifdef CONFIG_TSEC2 #define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 #define TSEC2_PHY_ADDR 0x3 #define TSEC2_FLAGS TSEC_GIGABIT #define TSEC2_PHYIDX 0 @@ -187,7 +181,6 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) -#define CONFIG_HAS_FSL_DR_USB #define CONFIG_SYS_SCCR_USBDRCM 3 /* @@ -216,8 +209,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_LOADS_ECHO #undef CONFIG_SYS_LOADS_BAUD_CHANGE @@ -252,8 +243,6 @@ "${netmask}:${hostname}:${netdev}:off " \ "console=${console},${baudrate} ${othbootargs}\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "\0" /* UBI Support */ diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h index edd24a4b55..599b0c50de 100644 --- a/include/configs/imgtec_xilfpga.h +++ b/include/configs/imgtec_xilfpga.h @@ -25,8 +25,6 @@ /* SDRAM Configuration (for final code, data, stack, heap) */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000) /*---------------------------------------------------------------------- * Commands @@ -35,7 +33,6 @@ /*------------------------------------------------------------ * Console Configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /* ------------------------------------------------- * Environment diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 6790053bb8..17430f15d1 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -106,10 +106,6 @@ /* * U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -136,11 +132,7 @@ " +${filesize};cp.b ${fileaddr} " \ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ "upd=run load update\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ /* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) #endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 26d7a88ebd..a2d5080a10 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -113,11 +113,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_SP_OFFSET) - /* UART */ #ifdef CONFIG_MXC_UART # ifdef CONFIG_MX6UL @@ -140,13 +135,7 @@ /* Falcon Mode */ #ifdef CONFIG_SPL_OS_BOOT -# define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -# define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -# define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - /* MMC support: args@1MB kernel@2MB */ -# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif /* Framebuffer */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 65f8944cca..2913549c88 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -113,34 +113,21 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000 /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif /* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif /* __IMX6LOGIC_CONFIG_H */ diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 234aacb3b9..488b2f1696 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -8,51 +8,6 @@ #ifdef CONFIG_SPL -#ifdef CONFIG_MX6_OCRAM_256KB -/* - * see Figure 8.4.1 in IMX6DQ Reference manuals: - * - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF - * - BOOT ROM stack is at 0x0093FFB8 - * - if icache/dcache is enabled (eFuse/strapping controlled) then the - * IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to - * fit between 0x00907000 and 0x00938000. - * - Additionally the BOOT ROM loads what they consider the firmware image - * which consists of a 4K header in front of us that contains the IVT, DCD - * and some padding thus 'our' max size is really 0x00908000 - 0x00938000 - * or 192KB - */ -#define CONFIG_SPL_MAX_SIZE 0x30000 -#define CONFIG_SPL_STACK 0x0093FFB8 -/* - * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the - * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a - * boot media (given that boot media specific offset is configured properly). - */ -#define CONFIG_SPL_PAD_TO 0x31000 -#else -/* - * see Figure 8-3 in IMX6SDL Reference manuals: - * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF - * - BOOT ROM stack is at 0x0091FFB8 - * - if icache/dcache is enabled (eFuse/strapping controlled) then the - * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to - * fit between 0x00907000 and 0x00918000. - * - Additionally the BOOT ROM loads what they consider the firmware image - * which consists of a 4K header in front of us that contains the IVT, DCD - * and some padding thus 'our' max size is really 0x00908000 - 0x00918000 - * or 64KB - */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_STACK 0x0091FFB8 -/* - * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the - * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a - * boot media (given that boot media specific offset is configured properly). - */ -#define CONFIG_SPL_PAD_TO 0x11000 - -#endif - /* MMC support */ #if defined(CONFIG_SPL_MMC) #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ @@ -60,31 +15,9 @@ /* SATA support */ #if defined(CONFIG_SPL_SATA) -#define CONFIG_SPL_SATA_BOOT_DEVICE 0 #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 #endif -/* Define the payload for FAT/EXT support */ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) -# ifdef CONFIG_OF_CONTROL -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -# else -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -# endif -#endif - -#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \ - defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) -#define CONFIG_SPL_BSS_START_ADDR 0x88200000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x88300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ -#else -#define CONFIG_SPL_BSS_START_ADDR 0x18200000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x18300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ -#endif #endif #endif diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index ba79e1bccf..909453cd66 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -20,7 +20,6 @@ /* Environment in MMC */ #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x14000000\0" \ "fdt_addr_r=0x13000000\0" \ @@ -34,7 +33,6 @@ func(MMC, mmc, 2) #include <config_distro_bootcmd.h> -#endif /* UART */ #define CONFIG_MXC_UART_BASE UART3_BASE @@ -45,19 +43,12 @@ #define CONFIG_FEC_MXC_PHYADDR 1 /* USB */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Falcon */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000 /* MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) /* Miscellaneous configurable options */ @@ -68,11 +59,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_SP_OFFSET) - /* SPL */ #include "imx6_spl.h" diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 6d362557ac..201684ba80 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -89,9 +89,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* SPL */ #ifdef CONFIG_SPL #include "imx6_spl.h" @@ -114,9 +111,7 @@ #endif #endif -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif /* __IMX6Q_ACC_H */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 2d9f8bb510..f0f800b840 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -12,7 +12,6 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -#undef CONFIG_SYS_AUTOLOAD #undef CONFIG_EXTRA_ENV_SETTINGS /* @@ -74,11 +73,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h index 128f612392..5900c05db1 100644 --- a/include/configs/imx7_spl.h +++ b/include/configs/imx7_spl.h @@ -11,52 +11,12 @@ #define __IMX7_SPL_CONFIG_H #ifdef CONFIG_SPL -/* - * see figure 6-22 in i.MX 7Dual/Solo Reference manuals: - * - IMX7D/S OCRAM free area RAM (OCRAM) is from 0x00910000 to - * 0x00946C00. - * - Set the stack at the end of the free area section, at 0x00946BB8. - * - The BOOT ROM loads what they consider the firmware image - * which consists of a 4K header in front of us that contains the IVT, DCD - * and some padding. However, the manual also states that the ROM uses the - * OCRAM_EPCD and OCRAM_PXP areas for itself. While the SPL is free to use - * this range for stack and malloc, the SPL itself must fit below 0x920000, - * or the image will be truncated in at least some boot modes like USB SDP. - * Thus our max size is really 0x00920000 - 0x00912000. If necessary, - * CONFIG_SPL_TEXT_BASE could be moved to 0x00911000 to gain 4KB of space - * for the SPL, but 56KB should be more than enough for the SPL. - */ -#define CONFIG_SPL_MAX_SIZE 0xE000 -#define CONFIG_SPL_STACK 0x00946BB8 -/* - * Pad SPL to 68KB (4KB header + 56KB max size + 8KB extra padding) - * The extra padding could be removed, but this value was used historically - * based on an incorrect CONFIG_SPL_MAX_SIZE definition. - * This allows to write the SPL/U-Boot combination generated with - * u-boot-with-spl.imx directly to a boot media (given that boot media specific - * offset is configured properly). - */ -#define CONFIG_SPL_PAD_TO 0x11000 /* MMC support */ #if defined(CONFIG_SPL_MMC) #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ #endif -/* Define the payload for FAT/EXT support */ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) -# ifdef CONFIG_OF_CONTROL -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -# else -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -# endif -#endif - -#define CONFIG_SPL_BSS_START_ADDR 0x88200000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x88300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - #endif /* CONFIG_SPL */ #endif /* __IMX7_SPL_CONFIG_H */ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 8d9212ec64..c69f2fa19f 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -11,23 +11,14 @@ #include <asm/arch/imx-regs.h> #include <config_distro_bootcmd.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x912000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif @@ -135,25 +126,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - /* USDHC */ #define CONFIG_SYS_FSL_USDHC_NUM 2 @@ -162,8 +140,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /*__IMX8MM_CL_IOT_GATE_H*/ diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 573ddaf295..79ed397122 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -9,22 +9,14 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif @@ -82,21 +74,9 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) #endif diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 419258f949..a5b7e9f5b6 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -10,43 +10,24 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN SZ_128M - -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_1M -#define CONFIG_SPL_STACK 0x920000 #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 kiB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M /* 16 MiB */ - #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* Link Definitions */ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR /* PHY needs a longer autonegotiation timeout after reset */ #define PHY_ANEG_TIMEOUT 20000 @@ -55,8 +36,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#if !defined(CONFIG_SPL_BUILD) - #define CONFIG_EXTRA_ENV_SETTINGS \ "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ "bootlimit=3\0" \ @@ -102,5 +81,3 @@ "fi" #endif - -#endif diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 5e8f19c43f..5e9e3e800d 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -10,34 +10,23 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -58,25 +47,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_FEC_MXC_PHYADDR 0 #endif diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index b9b24a8c51..6b7f3af53a 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -10,32 +10,20 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -# define CONFIG_SPL_STACK 0x920000 -# define CONFIG_SPL_BSS_START_ADDR 0x910000 -# define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -# define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -# define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ # define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -# define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* CONFIG_SPL_BUILD */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 2) \ func(MMC, mmc, 0) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_addr_r=0x44000000\0" \ @@ -53,27 +41,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -#define CONFIG_SYS_BOOTM_LEN SZ_256M - -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) /* USDHC */ #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 9836d5b73c..1301560450 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -9,22 +9,14 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif @@ -36,7 +28,6 @@ "kernel_comp_addr_r=0x40200000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ @@ -44,9 +35,6 @@ func(USB, usb, 1) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -89,26 +77,15 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_4G -#define CONFIG_SYS_BOOTM_LEN SZ_256M - -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) +/* FEC */ +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC #endif diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 79c6b1076f..6faecbde77 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -9,23 +9,15 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x0095e000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x184000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* CONFIG_SPL_BUILD */ @@ -94,10 +86,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 @@ -107,12 +95,4 @@ #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ #endif -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) #endif diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h index d09c2ab016..c6b2962814 100644 --- a/include/configs/imx8mn_bsh_smm_s2.h +++ b/include/configs/imx8mn_bsh_smm_s2.h @@ -14,15 +14,13 @@ #include <config_distro_bootcmd.h> #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandargs=setenv bootargs " \ + "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "mtdparts=${mtdparts} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:root rw ubi.mtd=nandrootfs\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${fdt_addr_r} nanddtb; " \ diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 6387576c2d..a371c5b383 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -10,21 +10,10 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define CONFIG_SPL_STACK 0x980000 -#define CONFIG_SPL_BSS_START_ADDR 0x950000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - - - #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ @@ -37,23 +26,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 -#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* I2C */ - #endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */ diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 805ae2a751..ae7fcb1027 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -10,33 +10,16 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x980000 -#define CONFIG_SPL_BSS_START_ADDR 0x950000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - -/* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE - -#endif - -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ /* see include/configs/ti_armv7_common.h */ @@ -65,23 +48,10 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #endif diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index 00358892b2..c8604e0de5 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -10,19 +10,10 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define CONFIG_SPL_STACK 0x980000 -#define CONFIG_SPL_BSS_START_ADDR 0x950000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ @@ -55,24 +46,11 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(4) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - /* USDHC */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 3cbe11a903..c43c4da6fb 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -9,20 +9,12 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x980000 -#define CONFIG_SPL_BSS_START_ADDR 0x950000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #define MEM_LAYOUT_ENV_SETTINGS \ @@ -33,16 +25,12 @@ "kernel_comp_addr_r=0x40200000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -85,26 +73,15 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_4G -#define CONFIG_SYS_BOOTM_LEN SZ_256M - -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) +/* FEC */ +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC #endif diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index 7d5403fa9f..4b4731c303 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -10,30 +10,11 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN SZ_128M - -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_1M -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x96FC00 -#define CONFIG_SPL_BSS_START_ADDR 0x0096FC00 -#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KiB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x4c000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 kiB */ - -/* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE - -#endif - /* Link Definitions */ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 @@ -41,13 +22,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* PHY needs a longer autonegotiation timeout after reset */ #define PHY_ANEG_TIMEOUT 20000 #define FEC_QUIRK_ENET_MAC @@ -56,8 +30,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#if !defined(CONFIG_SPL_BUILD) - #define CONFIG_EXTRA_ENV_SETTINGS \ "altbootcmd=run bootcmd ; reset\0" \ "bootlimit=3\0" \ @@ -109,5 +81,3 @@ #include <config_distro_bootcmd.h> #endif - -#endif diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 1e7c44c42a..5581c0fac0 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -10,21 +10,12 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (152 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x960000 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PCA9450 @@ -39,13 +30,11 @@ #endif -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -66,10 +55,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Totally 6GB DDR */ @@ -79,13 +64,4 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #endif diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 52e8ea8f86..17e00f958b 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -12,9 +12,6 @@ #include <asm/arch/imx-regs.h> #include <config_distro_bootcmd.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (152 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) @@ -28,18 +25,11 @@ 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x960000 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - #define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \ * GD_FLG_FULL_MALLOC_INIT \ * set \ */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #if defined(CONFIG_NAND_BOOT) #define CONFIG_SPL_NAND_MXS @@ -149,10 +139,6 @@ /* Link Definitions */ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Totally 6GB or 4G DDR */ @@ -168,12 +154,7 @@ #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ #endif -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 4120e4cc6b..9f4c1b161f 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -9,20 +9,12 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SPL_MAX_SIZE (152 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x960000 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #define MEM_LAYOUT_ENV_SETTINGS \ @@ -33,16 +25,12 @@ "kernel_comp_addr_r=0x40200000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -85,27 +73,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_4G -#define CONFIG_SYS_BOOTM_LEN SZ_256M - -/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) /* FEC */ #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 6eecfc813a..ab74d5b26b 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -10,37 +10,26 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* ENET Config */ /* ENET1 */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -61,10 +50,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -73,13 +58,6 @@ #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index e31f4135ae..ea4305667f 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -10,24 +10,15 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 @@ -39,14 +30,12 @@ #define CONFIG_FEC_MXC_PHYADDR 0 #endif -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -67,10 +56,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -79,13 +64,6 @@ #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 57e45b0447..97bd504450 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -9,22 +9,15 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SPL_MAX_SIZE (172 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* ENET Config */ @@ -95,10 +88,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -107,13 +96,6 @@ #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 61d56e269a..5f9d06e0f6 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -10,23 +10,12 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) - #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SPL_STACK 0x013E000 -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_MALLOC_F_ADDR 0x00120000 -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE - -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #ifdef CONFIG_AHAB_BOOT @@ -112,8 +101,6 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - /* Default environment is in SD */ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 81ab5d8caa..308f17fd59 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -10,18 +10,12 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SPL_MAX_SIZE (124 * 1024) -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ - #define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 #define USDHC3_BASE_ADDR 0x5B030000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* FUSE command */ /* Boot M4 */ @@ -108,8 +102,6 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board, * USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND, * USDHC2 is for SD, USDHC3 is for SD on base board diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 26dc4ded03..f8ec16ebb1 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -11,20 +11,11 @@ #include <asm/arch/imx-regs.h> #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SPL_STACK 0x013E000 -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_MALLOC_F_ADDR 0x00120000 -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE - -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #ifdef CONFIG_AHAB_BOOT @@ -110,8 +101,6 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - /* Default environment is in SD */ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ @@ -128,8 +117,5 @@ #endif /* Misc configuration */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #endif /* __IMX8QXP_MEK_H */ diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 05df43b39b..ebfc166b4d 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -9,21 +9,12 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (SZ_64M) -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x22050000 -#define CONFIG_SPL_BSS_START_ADDR 0x22048000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x22040000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x8000 /* 32 KB */ - #define CONFIG_MALLOC_F_ADDR 0x22040000 -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ #endif @@ -62,20 +53,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG3_RBASE #endif diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h index 79feab389e..a2c004880a 100644 --- a/include/configs/imxrt1020-evk.h +++ b/include/configs/imxrt1020-evk.h @@ -9,8 +9,6 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_INIT_SP_ADDR 0x20240000 - #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 #define PHYS_SDRAM 0x80000000 @@ -24,12 +22,6 @@ * Configuration of the external SDRAM memory */ -/* For SPL */ -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_LEN 0x00008000 #define CONFIG_SYS_UBOOT_START 0x800023FD -#endif -/* For SPL ends */ #endif /* __IMXRT1020_EVK_H */ diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index 5c2f975ba7..e36718dc82 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -9,8 +9,6 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_INIT_SP_ADDR 0x20280000 - #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 #define PHYS_SDRAM 0x80000000 @@ -31,12 +29,6 @@ * Configuration of the external SDRAM memory */ -/* For SPL */ -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_LEN 0x00008000 #define CONFIG_SYS_UBOOT_START 0x800023FD -#endif -/* For SPL ends */ #endif /* __IMXRT1050_EVK_H */ diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index d578b02460..34eec5a33d 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -31,11 +31,6 @@ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET /* * FLASH and environment organization diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h index 91ed76bb40..0f6150fc9c 100644 --- a/include/configs/iot2050.h +++ b/include/configs/iot2050.h @@ -14,19 +14,11 @@ #include <linux/sizes.h> /* SPL Loader Configuration */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ - CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) - -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE - -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* U-Boot general configuration */ #define EXTRA_ENV_IOT2050_BOARD_SETTINGS \ "usb_pgood_delay=900\0" -#ifndef CONFIG_SPL_BUILD - #if CONFIG_IS_ENABLED(CMD_USB) # define BOOT_TARGET_USB(func) \ func(USB, usb, 0) \ @@ -48,8 +40,6 @@ #include <config_distro_bootcmd.h> -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ BOOTENV \ diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h index 56a67f2891..a2e50c3b8d 100644 --- a/include/configs/iot_devkit.h +++ b/include/configs/iot_devkit.h @@ -30,12 +30,12 @@ * : : | * : : CONFIG_SYS_MALLOC_LEN * : : - * : Specified explicitly by CONFIG_SYS_INIT_SP_ADDR + * : Specified explicitly by CONFIG_CUSTOM_SYS_INIT_SP_ADDR * : * Specified explicitly by CONFIG_SYS_SDRAM_BASE * * NOTES: - * - Stack starts from CONFIG_SYS_INIT_SP_ADDR and grows down, + * - Stack starts from CONFIG_CUSTOM_SYS_INIT_SP_ADDR and grows down, * i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing * that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on * stack any longer and values popped from stack will contain garbage @@ -53,16 +53,12 @@ #define CONFIG_SYS_SDRAM_BASE DCCM_BASE #define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) - -#define CONFIG_SYS_BOOTM_LEN SZ_128K - #define ROM_BASE CONFIG_SYS_MONITOR_BASE #define ROM_SIZE SZ_256K -#define RAM_DATA_BASE CONFIG_SYS_INIT_SP_ADDR +#define RAM_DATA_BASE SYS_INIT_SP_ADDR #define RAM_DATA_SIZE CONFIG_SYS_SDRAM_SIZE - \ - (CONFIG_SYS_INIT_SP_ADDR - \ + (SYS_INIT_SP_ADDR - \ CONFIG_SYS_SDRAM_BASE) - \ CONFIG_SYS_MALLOC_LEN - \ CONFIG_ENV_SIZE diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 2590ee6b01..9f54f25999 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -17,46 +17,17 @@ /* DDR Configuration */ #define CONFIG_SYS_SDRAM_BASE1 0x880000000 +/* FLASH Configuration */ +#define CONFIG_SYS_FLASH_BASE 0x000000000 /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) #define CONFIG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else #define CONFIG_SYS_UBOOT_BASE 0x50080000 -/* - * Maximum size in memory allocated to the SPL BSS. Keep it as tight as - * possible (to allow the build to go through), as this directly affects - * our memory footprint. The less we use for BSS the more we have available - * for everything else. - */ -#define CONFIG_SPL_BSS_MAX_SIZE 0xA000 -/* - * Link BSS to be within SPL in a dedicated region located near the top of - * the MCU SRAM, this way making it available also before relocation. Note - * that we are not using the actual top of the MCU SRAM as there is a memory - * location filled in by the boot ROM that we want to read out without any - * interference from the C context. - */ -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ - CONFIG_SPL_BSS_MAX_SIZE) -/* Set the stack right below the SPL BSS section */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR -/* Configure R5 SPL post-relocation malloc pool in DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -/* Image load address in RAM for DFU boot*/ -#endif - -#ifdef CONFIG_SYS_K3_SPL_ATF -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" #endif -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* HyperFlash related configuration */ /* U-Boot general configuration */ @@ -178,14 +149,6 @@ DFU_ALT_INFO_RAM \ DFU_ALT_INFO_OSPI -#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD -#endif - #if CONFIG_IS_ENABLED(CMD_PXE) # define BOOT_TARGET_PXE(func) func(PXE, pxe, na) #else @@ -216,7 +179,6 @@ EXTRA_ENV_RPROC_SETTINGS \ EXTRA_ENV_DFUARGS \ DEFAULT_UFS_TI_ARGS \ - EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \ EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \ BOOTENV diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index a5505f079b..932d7d3c8c 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -21,43 +21,12 @@ /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) #define CONFIG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else #define CONFIG_SYS_UBOOT_BASE 0x50080000 -/* - * Maximum size in memory allocated to the SPL BSS. Keep it as tight as - * possible (to allow the build to go through), as this directly affects - * our memory footprint. The less we use for BSS the more we have available - * for everything else. - */ -#define CONFIG_SPL_BSS_MAX_SIZE 0xA000 -/* - * Link BSS to be within SPL in a dedicated region located near the top of - * the MCU SRAM, this way making it available also before relocation. Note - * that we are not using the actual top of the MCU SRAM as there is a memory - * location filled in by the boot ROM that we want to read out without any - * interference from the C context. - */ -#define CONFIG_SPL_BSS_START_ADDR (0x41c80000 -\ - CONFIG_SPL_BSS_MAX_SIZE) -/* Set the stack right below the SPL BSS section */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR -/* Configure R5 SPL post-relocation malloc pool in DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -/* Image load address in RAM for DFU boot*/ -#endif - -#ifdef CONFIG_SYS_K3_SPL_ATF -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" #endif -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* U-Boot general configuration */ #define EXTRA_ENV_J721S2_BOARD_SETTINGS \ "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ @@ -157,14 +126,6 @@ DFU_ALT_INFO_RAM \ DFU_ALT_INFO_OSPI -#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD -#endif - /* Incorporate settings into the U-Boot environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ @@ -175,7 +136,6 @@ EXTRA_ENV_RPROC_SETTINGS \ EXTRA_ENV_DFUARGS \ DEFAULT_UFS_TI_ARGS \ - EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \ EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY /* Now for the remaining common defines */ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 85cf516e16..1bfc89bf44 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -12,15 +12,6 @@ /* * Miscellaneous configurable options */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_HUSH_INIT_VAR #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } @@ -180,8 +171,6 @@ "init=/sbin/init-overlay.sh\0" \ "load_addr_r=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ "load=tftpboot ${load_addr_r} ${u-boot}\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "" #endif /* CONFIG_KM_DEF_ENV */ diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index e1c161586b..9f76f48a5c 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -25,10 +25,6 @@ */ #define CONFIG_SYS_FLASH_BASE 0xF0000000 -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - /* Reserve 768 kB for Mon */ #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -38,8 +34,6 @@ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) /* * Init Local Bus Memory Controller: * @@ -83,10 +77,6 @@ * Environment */ -#ifndef CONFIG_SYS_RAMBOOT -/* Address and size of Redundant Environment Sector */ -#endif /* CFG_SYS_RAMBOOT */ - /* * Environment Configuration */ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index a9a6a41f6b..6becd7cd31 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE /* Increase max size of compressed kernel */ -#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ /****************************************************************************** * (PRAM usage) diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index a485c3ac6d..eee71db37c 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -25,7 +25,6 @@ #include "keymile-common.h" /* Increase max size of compressed kernel */ -#define CONFIG_SYS_BOOTM_LEN (32 << 20) #include "asm/arch/config.h" diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index dca5589a3e..f837390135 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 /* POST memory regions test */ @@ -174,7 +173,6 @@ {1, {I2C_NULL_HOP} }, \ } -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG @@ -187,15 +185,8 @@ #define CONFIG_LS102XA_STREAM_ID -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* * Environment */ @@ -258,7 +249,6 @@ "ethrotate=no\0" \ "" -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ #endif diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index e58a69501b..01482d5319 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -23,7 +23,6 @@ /* KM_KIRKWOOD */ #if defined(CONFIG_KM_KIRKWOOD) #define CONFIG_HOSTNAME "km_kirkwood" -#define CONFIG_KM_DISABLE_PCIE /* KM_KIRKWOOD_PCI */ #elif defined(CONFIG_KM_KIRKWOOD_PCI) @@ -34,7 +33,6 @@ /* KM_KIRKWOOD_128M16 */ #elif defined(CONFIG_KM_KIRKWOOD_128M16) #define CONFIG_HOSTNAME "km_kirkwood_128m16" -#define CONFIG_KM_DISABLE_PCIE /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) @@ -44,7 +42,6 @@ /* KMCOGE5UN */ #elif defined(CONFIG_KM_COGE5UN) #define CONFIG_HOSTNAME "kmcoge5un" -#define CONFIG_KM_DISABLE_PCIE /* KM_SUSE2 */ #elif defined(CONFIG_KM_SUSE2) @@ -118,8 +115,4 @@ MVGBE_SET_MII_SPEED_TO_100) #endif -#ifdef CONFIG_KM_DISABLE_PCIE -#undef CONFIG_KIRKWOOD_PCIE_INIT -#endif - #endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index dc45d16bfe..b389229b75 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -133,14 +133,11 @@ #define KM_I2C_DEBLOCK_SDA 21 /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ /* Environment in parallel NOR-Flash */ #define CONFIG_ENV_TOTAL_SIZE 0x040000 @@ -149,11 +146,8 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_ENABLE_36BIT_PHYS - /* POST memory regions test */ #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS @@ -173,7 +167,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -339,9 +332,7 @@ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */ @@ -417,7 +408,6 @@ int get_scl(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 8f4685c271..b9d20c9c8e 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -35,12 +35,6 @@ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10) -/* - * BFTIC3 on the local bus CS4 - */ -#define CONFIG_SYS_BFTIC3_BASE 0xB0000000 -#define CONFIG_SYS_BFTIC3_SIZE 256 - /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index c0997aa3dd..736865ad80 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -10,10 +10,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -34,7 +33,5 @@ "bootm_size=0x10000000\0" /* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 #endif /* __KOELSCH_H */ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 7bc402d578..7aac5d3f5a 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -22,11 +22,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE /* Board and environment settings */ @@ -34,25 +29,19 @@ #define CONFIG_HOSTNAME "kontron-mx6ul" #ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* Boot order for distro boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, UBI, boot) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif /* MMC Configs */ #ifdef CONFIG_FSL_USDHC diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 231571b05e..622ab59762 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -22,20 +22,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Board and environment settings */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) #define CONFIG_HOSTNAME "kontron-mx8mm" #ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* GUID for capsule updatable firmware image */ @@ -43,7 +35,6 @@ EFI_GUID(0xd488e45a, 0x4929, 0x4b55, 0x8c, 0x14, \ 0x86, 0xce, 0xa2, 0xcd, 0x66, 0x29) -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ @@ -53,19 +44,8 @@ /* Do not try to probe USB net adapters for net boot */ #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START -#else -#define BOOTENV -#endif - -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x91fff0 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 #endif diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 1834991ac3..d77e4b4e10 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -7,9 +7,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (124 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K) /* GUID for capsule updatable firmware image */ @@ -18,17 +15,11 @@ 0x40, 0xd4, 0x5c, 0xca, 0x13, 0x99) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PFUZE100 @@ -74,10 +65,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index c47b5940fb..2373abf3e3 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __SL28_H -#define __SL28_H +#ifndef __SL28_CONFIG_H +#define __SL28_CONFIG_H #include <asm/arch/stream_id_lsch3.h> #include <asm/arch/config.h> @@ -26,7 +26,6 @@ #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 /* early stack pointer */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0) /* SMP */ #define CPU_RELEASE_ADDR secondary_boot_addr @@ -42,13 +41,7 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) /* SPL */ -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SPL_MAX_SIZE 0x20000 -#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) /* GUID for capsule updatable firmware image */ @@ -87,4 +80,4 @@ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV -#endif /* __SL28_H */ +#endif /* __SL28_CONFIG_H */ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 534263f62b..c401fd3216 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -61,7 +61,6 @@ #include <config_distro_bootcmd.h> /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR @@ -72,11 +71,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #endif /* __CONFIG_H_ */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 7d879477d7..1823a79398 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -21,13 +21,10 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_addr=0x18000000\0" \ @@ -88,7 +85,6 @@ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -97,12 +93,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment */ #endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */ diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h index 75fc03f147..fea7c835fd 100644 --- a/include/configs/kylin_rk3036.h +++ b/include/configs/kylin_rk3036.h @@ -9,10 +9,4 @@ #include <linux/sizes.h> #include <configs/rk3036_common.h> -#ifndef CONFIG_SPL_BUILD - -/* Store env in emmc */ - -#endif - #endif diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 7e99490e52..e084f87d14 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -19,11 +19,9 @@ /* NOR Flash */ #define KZM_FLASH_BASE (0x00000000) #define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) -#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) #define CONFIG_SYS_MAX_FLASH_SECT (512) /* prompt */ -#define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ @@ -33,9 +31,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ #define CONFIG_SYS_INIT_RAM_SIZE (0x10000) #define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) #define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) #define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 0a988e2fad..9b70eed46f 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -22,18 +22,6 @@ #endif /* - * SATA Driver configuration - */ - -#ifdef CONFIG_SATA -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 -#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \ - defined(CONFIG_NET2BIG_V2) -#endif -#endif /* CONFIG_SATA */ - -/* * Enable GPI0 support */ @@ -69,7 +57,6 @@ "stderr=serial\0" \ "bootfile=uImage\0" \ "loadaddr=0x800000\0" \ - "autoload=no\0" \ "netconsole=" \ "set stdin $stdin,nc; " \ "set stdout $stdout,nc; " \ diff --git a/include/configs/lager.h b/include/configs/lager.h index a5abbaaeab..f3feaa539f 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -11,10 +11,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -35,7 +34,5 @@ "bootm_size=0x10000000\0" /* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 #endif /* __LAGER_H */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 4c132c6851..f0ae9248af 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -42,16 +42,8 @@ #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) /* - * I2C Configuration - */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ - -/* * U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ /* * Linux Information @@ -96,8 +88,6 @@ /* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x80010000 - #include <asm/arch/hardware.h> #endif /* __CONFIG_H */ diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 86bad6fa03..2e077dd516 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -17,10 +17,6 @@ /* SPL */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x80010000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_PAD_TO 0 /* Dummy value */ #define CONFIG_SYS_UBOOT_BASE 0 @@ -40,11 +36,6 @@ /* RAM */ -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_CBSIZE 512 - /* Environment settings */ #endif /* __CONFIG_LINKIT_SMART_7688_H */ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index fdea7241b0..a1fc056c30 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -94,19 +94,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* FLASH and environment organization */ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif #ifdef CONFIG_CMD_NET diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 67da01f5e3..87eb10db19 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -10,20 +10,11 @@ #include <asm/arch/stream_id_lsch2.h> #include <linux/sizes.h> -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif - #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL -/* CSU */ -#define CONFIG_LAYERSCAPE_NS_ACCESS - /*SPI device */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 @@ -42,14 +33,12 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(SCSI, scsi, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -68,12 +57,6 @@ "bootm $kernel_load" #endif -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #include <asm/arch/soc.h> #endif /* __LS1012A_COMMON_H */ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index cb79d6362f..674bcbeb75 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -12,11 +12,9 @@ /* DDR */ #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) -#endif #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index a1d23b6463..a0ff3b8979 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -19,17 +19,11 @@ /* ENV */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) -#endif - -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index b5992366cf..b124ce5262 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -82,10 +82,6 @@ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ DSPI_CTAR_DT(0)) -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index c57b598d70..4f77acdaed 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -36,10 +36,6 @@ #define __PHY_ETH2_MASK 0xFB #define __PHY_ETH1_MASK 0xFD -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 82ae3492a2..ec688741a0 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -42,15 +42,6 @@ #define SDRAM_CFG_BI 0x00000001 #ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif @@ -106,18 +97,9 @@ #define TSEC2_PHYIDX 0 #endif -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ - #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG @@ -136,11 +118,6 @@ #define CONFIG_LS102XA_STREAM_ID -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #include <asm/fsl_secure_boot.h> #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 7b79e0841a..517ade383b 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,40 +11,18 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE #ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN 0xc0000 #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 - -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE @@ -323,16 +301,7 @@ #endif -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG @@ -359,16 +328,10 @@ #define CONFIG_LS102XA_STREAM_ID -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* * Environment */ #include <asm/fsl_secure_boot.h> -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #endif diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 09168a28e7..2fbd495e11 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* XHCI Support - enabled by default */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define DDR_SDRAM_CFG 0x470c0008 #define DDR_CS0_BNDS 0x008000bf @@ -44,16 +43,6 @@ #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) #endif /* ifdef CONFIG_NXP_ESBC */ -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - #ifdef CONFIG_U_BOOT_HDR_SIZE /* * HDR would be appended at end of image and copied to DDR along @@ -91,14 +80,7 @@ #define FSL_QSPI_FLASH_NUM 2 /* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 @@ -176,21 +158,8 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - #define CONFIG_LS102XA_STREAM_ID -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment */ -#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */ - #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b36c8dccf1..1aa29e541e 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -46,16 +46,6 @@ #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) #endif /* ifdef CONFIG_NXP_ESBC */ -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - #ifdef CONFIG_U_BOOT_HDR_SIZE /* * HDR would be appended at end of image and copied to DDR along @@ -181,16 +171,7 @@ #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 1 -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG @@ -338,16 +319,10 @@ #define CONFIG_LS102XA_STREAM_ID -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* * Environment */ #include <asm/fsl_secure_boot.h> -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #endif diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index a98d8dd720..b104524bec 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -11,7 +11,6 @@ #include <asm/arch/soc.h> /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL @@ -58,16 +57,6 @@ "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \ "env exists secureboot && esbc_halt;" -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ - -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #define OCRAM_NONSECURE_SIZE 0x00010000 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 35363ccda1..2539115186 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -60,7 +60,6 @@ /* SATA */ -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 #ifndef SPL_NO_ENV #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -88,7 +87,6 @@ "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ "boot_scripts=ls1028aqds_boot.scr\0" \ "boot_script_hdr=hdr_ls1028aqds_bs.out\0" \ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 91223789b8..e7b2543b73 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -53,7 +53,6 @@ #define SCSI_VEND_ID 0x1b4b #define SCSI_DEV_ID 0x9170 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 /* Initial environment variables */ #ifndef SPL_NO_ENV @@ -83,7 +82,6 @@ "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x20\0" \ "console=ttyS0,115200\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ "boot_scripts=ls1028ardb_boot.scr\0" \ "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 26db8ffe7e..95cbcb036e 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -30,11 +30,6 @@ #include <asm/arch/config.h> /* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 @@ -51,17 +46,6 @@ /* SD boot SPL */ #ifdef CONFIG_SD_BOOT - -#define CONFIG_SPL_MAX_SIZE 0x17000 -#define CONFIG_SPL_STACK 0x1001e000 -#define CONFIG_SPL_PAD_TO 0x1d000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* @@ -78,15 +62,8 @@ /* NAND SPL */ #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PBL_PAD -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) @@ -131,17 +108,6 @@ /* I2C */ -/* PCIe */ -#ifndef SPL_NO_PCIE -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif -#endif - /* DSPI */ /* FMan ucode */ @@ -160,13 +126,11 @@ #define HWCONFIG_BUFFER_SIZE 128 #ifndef SPL_NO_MISC -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -192,7 +156,6 @@ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ "boot_os=y\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ "boot_scripts=ls1043ardb_boot.scr\0" \ "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ @@ -254,13 +217,6 @@ #endif #endif -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #include <asm/arch/soc.h> #endif /* __LS1043A_COMMON_H */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index b4329c2e89..15c3ff53fe 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -8,12 +8,9 @@ #include "ls1043a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -128,7 +125,6 @@ #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif @@ -315,9 +311,6 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - /* * Environment */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 3ac4cb7643..6c33847b27 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -8,23 +8,12 @@ #include "ls1043a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ -#define CONFIG_SYS_SPD_BUS_NUM 0 - #ifndef CONFIG_SPL -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30 -#endif - /* * NOR Flash Definitions */ @@ -101,7 +90,6 @@ #define CONFIG_MTD_NAND_VERIFY_WRITE #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index fb2011aa55..2e48ea0f8a 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -30,11 +30,6 @@ #include <asm/arch/stream_id_lsch2.h> /* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 @@ -51,15 +46,6 @@ /* SD boot SPL */ #ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ -#define CONFIG_SPL_STACK 0x10020000 -#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ -#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* @@ -75,32 +61,14 @@ #endif #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL) -#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl" -#define CONFIG_SPL_MAX_SIZE 0x1f000 -#define CONFIG_SPL_STACK 0x10020000 -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SYS_MONITOR_LEN 0x100000 #endif /* NAND SPL */ #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PBL_PAD - -#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */ -#define CONFIG_SPL_STACK 0x1001f000 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SYS_MONITOR_LEN 0xa0000 #endif @@ -108,15 +76,6 @@ /* I2C */ -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - /* SATA */ #ifndef SPL_NO_SATA #define CONFIG_SYS_SATA AHCI_BASE_ADDR @@ -136,14 +95,12 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(SCSI, scsi, 0) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif #if defined(CONFIG_TARGET_LS1046AFRWY) #define LS1046A_BOOT_SRC_AND_HDR\ @@ -234,13 +191,6 @@ #endif -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #include <asm/arch/soc.h> #endif /* __LS1046A_COMMON_H */ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index d56d0c0294..43717cdd4e 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -8,8 +8,6 @@ #include "ls1046a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - #define CONFIG_SYS_UBOOT_BASE 0x40100000 /* @@ -80,13 +78,11 @@ */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) -#endif /* FMan */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 05aeedc410..36c64db8f5 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -8,12 +8,9 @@ #include "ls1046a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -145,7 +142,6 @@ #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #endif @@ -333,9 +329,6 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - /* * Environment */ diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 3dfbae268e..382d5c7646 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -9,18 +9,14 @@ #include "ls1046a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #if defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_UBOOT_BASE 0x40100000 -#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 #endif #define CONFIG_SYS_NAND_BASE 0x7e800000 @@ -139,8 +135,6 @@ #endif #endif -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - #include <asm/fsl_secure_boot.h> #endif /* __LS1046ARDB_H__ */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 0c73a9e0dc..4b8462da7b 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -25,11 +25,6 @@ #define LS1088ARDB_PB_BOARD 0x4A /* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif /* Link Definitions */ #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 @@ -120,11 +115,6 @@ unsigned long long get_qixis_addr(void); /* Miscellaneous configurable options */ -/* SATA */ -#ifdef CONFIG_SCSI -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#endif - /* Physical Memory Map */ #define CONFIG_HWCONFIG @@ -148,23 +138,7 @@ unsigned long long get_qixis_addr(void); " 0x580e00000 \0" #endif -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - #ifdef CONFIG_SPL -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SPL_MAX_SIZE 0x16000 -#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 - #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* @@ -179,6 +153,5 @@ unsigned long long get_qixis_addr(void); #endif /* ifdef CONFIG_NXP_ESBC */ #endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #endif /* __LS1088_COMMON_H */ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index e532c343f4..debb60d25c 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -16,7 +16,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* @@ -306,10 +305,6 @@ #define CONFIG_FSL_MEMAC -/* MMC */ -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) - #define COMMON_ENV \ "kernelheader_addr_r=0x80200000\0" \ "fdtheader_addr_r=0x80100000\0" \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index c69003018b..c0567c3fe5 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -15,13 +15,8 @@ #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ -#ifdef CONFIG_EMU -#define CONFIG_SYS_FSL_DDR_EMU -#else #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index e77e9b7f37..3e86d1bff2 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -11,20 +11,11 @@ #include <asm/arch/config.h> /* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif /* We need architecture specific misc initializations */ /* Link Definitions */ -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif - #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ #define CONFIG_VERY_BIG_RAM @@ -142,26 +133,12 @@ unsigned long long get_qixis_addr(void); "mcinitcmd=fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SPL_MAX_SIZE 0x16000 -#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #endif -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #include <asm/arch/soc.h> #endif /* __LS2_COMMON_H */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 4975fb782b..9ba7258572 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -24,15 +24,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -/* SATA */ - -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) @@ -191,7 +182,6 @@ #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) #endif #else @@ -249,14 +239,6 @@ #define FSL_QIXIS_BRDCFG9_QSPI 0x1 /* - * MMC - */ -#ifdef CONFIG_MMC -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) -#endif - -/* * RTC configuration */ #define RTC @@ -269,10 +251,6 @@ #define CONFIG_FSL_MEMAC -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS #ifdef CONFIG_NXP_ESBC @@ -416,7 +394,7 @@ "env exists secureboot && esbc_halt;" #endif -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) #define CONFIG_FSL_MEMAC #define SGMII_CARD_PORT1_PHY_ADDR 0x1C #define SGMII_CARD_PORT2_PHY_ADDR 0x1d diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 52a48bd4b8..a504a0ea46 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -29,15 +29,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -/* SATA */ - -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT) @@ -174,7 +165,6 @@ #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SPL_PAD_TO 0x80000 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT @@ -248,10 +238,6 @@ #define CONFIG_FSL_MEMAC -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 0) \ diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 19fd702ab2..81c93375e2 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -94,9 +94,4 @@ #define CONFIG_PHY_BASE_ADR 7 #endif /* CONFIG_CMD_NET */ -#ifdef CONFIG_SATA -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 -#endif - #endif /* _CONFIG_LSXL_H */ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index aaba8fc26d..b754373169 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -12,7 +12,6 @@ #define CONFIG_FSL_MEMAC -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_FLASH_BASE 0x20000000 /* DDR */ @@ -32,7 +31,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_SYS_MONITOR_LEN (936 * 1024) /* Miscellaneous configurable options */ @@ -91,39 +89,13 @@ /* Qixis */ #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -/* PCI */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* SATA */ - -#ifdef CONFIG_SCSI -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 -#endif - /* USB */ -#ifdef CONFIG_USB_HOST -#ifndef CONFIG_TARGET_LX2162AQDS -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif -#endif #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - /* Initial environment variables */ #define XSPI_MC_INIT_CMD \ "sf probe 0:0 && " \ diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index e7aec6bc59..585aab26bf 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -11,16 +11,6 @@ /* RTC */ #define CONFIG_SYS_RTC_BUS_NUM 0 -/* - * MMC - */ -#ifdef CONFIG_MMC -#ifndef __ASSEMBLY__ -u8 qixis_esdhc_detect_quirk(void); -#endif -#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() -#endif - /* MAC/PHY configuration */ /* EEPROM */ diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index 126d226ebc..d1ae403473 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -9,22 +9,10 @@ #include "lx2160a_common.h" /* USB */ -#undef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* RTC */ #define CONFIG_SYS_RTC_BUS_NUM 0 -/* - * MMC - */ -#ifdef CONFIG_MMC -#ifndef __ASSEMBLY__ -u8 qixis_esdhc_detect_quirk(void); -#endif -#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() -#endif - /* EEPROM */ #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 90877f548d..b3348bc63b 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -24,18 +24,9 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* * U-Boot general configurations */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ /* * Serial Driver @@ -60,9 +51,6 @@ #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_MXC_NAND_HWECC - -/* Environment is in NAND */ -#define CONFIG_ENV_RANGE (0x00080000) /* 512 KiB */ #endif /* @@ -92,15 +80,6 @@ #endif /* - * SATA - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* * LCD */ #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) @@ -117,9 +96,6 @@ /* * NAND SPL */ -#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx" -#define CONFIG_SPL_PAD_TO 0x8000 -#define CONFIG_SPL_STACK 0x70004000 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) @@ -136,8 +112,6 @@ "mmcpart=1\0" \ "rootpath=/srv/\0" \ "kernel_addr_r=0x72000000\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "netdev=eth0\0" \ "splashsource=mmc_fs\0" \ "splashfile=boot/usplash.bmp.gz\0" \ diff --git a/include/configs/malta.h b/include/configs/malta.h index 84e5f985b1..c8b230ab21 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -13,9 +13,6 @@ #define CONFIG_MEMSIZE_IN_BYTES -#define CONFIG_PCI_GT64120 -#define CONFIG_PCI_MSC01 - #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 /* @@ -37,9 +34,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) - /* * Serial driver */ diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index e4df9d8dff..db84302231 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -46,22 +46,6 @@ * L2 cache thus cannot be used. */ -/* SPL */ -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -/* SPL related SPI defines */ - /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_SYS_SDRAM_SIZE SZ_1G diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index dcce52eb7d..02a2235187 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -12,16 +12,12 @@ #include "imx6_spl.h" #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 /* * Below defines are set but NOT really used since we by * design force U-Boot run when we boot in development * mode from SD card (SD2) */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800) -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80) -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "fitImage" #define CONFIG_MXC_UART_BASE UART1_BASE @@ -31,7 +27,6 @@ /* NOR 16-bit mode */ #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_FLASH_VERIFY @@ -114,7 +109,6 @@ "fi;" \ "fi;" \ "fi\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "bootdev=1\0" \ "bootpart=1\0" \ "netdev=eth0\0" \ @@ -227,11 +221,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ /* Envs are stored in NOR flash */ diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index ab8fa85f25..c6ce883747 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -21,15 +21,9 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment configs */ /* USB configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 6b6c90eb5e..6b2296788d 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -47,13 +47,8 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 +#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -69,6 +64,4 @@ /* hw-controller addresses */ #define CONFIG_ET1100_BASE 0x70000000 -#define CONFIG_SYS_CBSIZE 512 - #endif diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 196e58ed9a..40803ee9da 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -29,12 +29,7 @@ #define STDIN_CFG "serial" #endif -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_INIT_SP_ADDR 0x20000000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ /* ROM USB boot support, auto-execute boot.scr at scriptaddr */ #define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 663837f33d..73f8492228 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -11,17 +11,11 @@ /* Microblaze is microblaze_0 */ #define XILINX_FSL_NUMBER 3 -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) - /* uart */ /* The following table includes the supported baudrates */ # define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -/* Stack location before relocation */ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_F_LEN) - #ifdef CONFIG_CFI_FLASH /* ?empty sector */ # define CONFIG_SYS_FLASH_EMPTY_INFO 1 @@ -30,15 +24,6 @@ # define CONFIG_SYS_MAX_FLASH_SECT 2048 #endif -#ifndef XILINX_DCACHE_BYTE_SIZE -#define XILINX_DCACHE_BYTE_SIZE 32768 -#endif - -/* size of console buffer */ -#define CONFIG_SYS_CBSIZE 512 -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 15 - #define CONFIG_HOSTNAME "microblaze-generic" /* architecture dependent code */ @@ -120,28 +105,10 @@ #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -/* for booting directly linux */ -#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_TEXT_BASE + \ - 0x40000) - -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ - 0x1000000) - /* SP location before relocation, must use scratch RAM */ /* BRAM start */ #define CONFIG_SYS_INIT_RAM_ADDR 0x0 /* BRAM size - will be generated */ #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 -# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE) - -/* Just for sure that there is a space for stack */ -#define CONFIG_SPL_STACK_SIZE 0x100 - -#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ - CONFIG_SYS_INIT_RAM_ADDR - \ - CONFIG_SYS_MALLOC_F_LEN - \ - CONFIG_SPL_STACK_SIZE) - #endif /* __CONFIG_H */ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 655c8d6af5..4c7cfac8af 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -10,9 +10,6 @@ #include <linux/sizes.h> #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h index 703efcd8f3..049d9a1b55 100644 --- a/include/configs/mt7620.h +++ b/include/configs/mt7620.h @@ -10,24 +10,13 @@ #define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_CBSIZE 1024 - /* SPL */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x80010000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_PAD_TO 0 /* Dummy value */ #define CONFIG_SYS_UBOOT_BASE 0 diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index 97fcf2f87b..78d79b7780 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -11,11 +11,6 @@ #include <linux/sizes.h> -#define CONFIG_SYS_MAXARGS 8 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Uboot definition */ @@ -23,8 +18,6 @@ /* SPL -> Uboot */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) /* DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 6023f8128e..0cd8b08552 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -13,19 +13,11 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MAXARGS 8 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Environment */ /* Preloader -> Uboot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) /* MMC */ #define MMC_SUPPORTS_TUNING diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 1008aaab1d..3680c0fe44 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -10,17 +10,10 @@ #define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x80000 -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_CBSIZE 1024 - /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CONFIG_SYS_NS16550_MEM32 @@ -36,10 +29,6 @@ /* SPL */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x80010000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_PAD_TO 0 /* Dummy value */ #define CONFIG_SYS_UBOOT_BASE 0 diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index c58545be04..22d11d0147 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -13,31 +13,18 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MAXARGS 8 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Environment */ /* Defines for SPL */ -#define CONFIG_SPL_STACK 0x106000 -#define CONFIG_SPL_MAX_SIZE SZ_64K -#define CONFIG_SPL_MAX_FOOTPRINT SZ_64K -#define CONFIG_SPL_PAD_TO 0x10000 #define CONFIG_SPI_ADDR 0x30000000 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) /* SPL -> Uboot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) /* UBoot -> Kernel */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x40000000 /* DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index ee31c02e6e..c93d70ddf1 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -18,11 +18,6 @@ #define CONFIG_SYS_NS16550_COM1 0x11005200 #define CONFIG_SYS_NS16550_CLK 26000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Environment settings */ #include <config_distro_bootcmd.h> diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h index 1af8d2e480..964c957813 100644 --- a/include/configs/mt8512.h +++ b/include/configs/mt8512.h @@ -13,14 +13,8 @@ #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Uboot definition */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + \ - SZ_2M - \ - GENERATED_GBL_DATA_SIZE) #define ENV_BOOT_READ_IMAGE \ "boot_rd_img=mmc dev 0" \ diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index cb2af5843f..7228f3e428 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -18,11 +18,6 @@ #define CONFIG_SYS_NS16550_COM1 0x11005000 #define CONFIG_SYS_NS16550_CLK 26000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Environment settings */ #include <config_distro_bootcmd.h> diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 8ca8d25148..6d4704644e 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -18,12 +18,7 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Uboot definition */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + \ - SZ_2M - \ - GENERATED_GBL_DATA_SIZE) #define ENV_BOOT_READ_IMAGE \ "boot_rd_img=mmc dev 0" \ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index cc3b597f28..384a8f7d1d 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -50,12 +50,9 @@ /* auto boot */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - /* * Other required minimal configurations */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ /* ====> Include platform Common Definitions */ #include <asm/arch/config.h> diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 06882fb51e..51f7e16ece 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -15,8 +15,6 @@ /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - #define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ @@ -25,29 +23,15 @@ 4000000, 4500000, 5000000, 5500000, \ 6000000 } -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - /* * Other required minimal configurations */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -/* End of 16M scrubbed by training in bootrom */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) /* * Environment */ #define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) - -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 8e325e8f4a..5a956f0a3e 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -19,31 +19,17 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - /* * Other required minimal configurations */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -/* End of 16M scrubbed by training in bootrom */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) /* When runtime detection fails this is the default */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) - /* USB ethernet */ /* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - -/* * PCI configuration */ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index ab466b65ac..dd303a17d6 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -15,10 +15,6 @@ /* Status LED */ /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif /* Ethernet */ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 3fb0003107..3507e83fb3 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -20,10 +20,6 @@ /* Environment is in MMC */ /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif /* Framebuffer support */ #ifdef CONFIG_DM_VIDEO diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index fe096d424c..9f3ac48b70 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -15,17 +15,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Environment */ - -/* Environment is in MMC */ - -/* Environment is in NAND */ -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (512 * 1024) -#endif - -/* Environment is in SPI flash */ - /* UBI and NAND partitioning */ /* RTC */ @@ -34,10 +23,6 @@ #endif /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif /* Framebuffer support */ #ifdef CONFIG_DM_VIDEO diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index ccfe292f6c..a423dd28b0 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -117,11 +117,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 #define CONFIG_SYS_MAIN_PWR_ON diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index fafc5f1adc..f1d751f15a 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -16,8 +16,6 @@ #define CONFIG_MXC_UART_BASE UART2_BASE -#define CONFIG_FPGA_COUNT 1 - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_ESDHC_NUM 2 @@ -55,7 +53,6 @@ BOOTENV /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR @@ -68,11 +65,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ /* Framebuffer and LCD */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 8b9f0a2901..9ceed12e48 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -88,7 +88,6 @@ "fi;\0" /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR @@ -101,17 +100,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#ifdef CONFIG_CMD_SATA - #define CONFIG_DWC_AHSATA_PORT_ID 0 - #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR - #define CONFIG_LBA48 -#endif - /* Framebuffer and LCD */ #endif /* __CONFIG_H */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 572261b042..b26613a2ea 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -86,10 +86,6 @@ "lcd:800x480-24@60,monitor=lcd\0" \ /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MAXARGS 48 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ @@ -104,11 +100,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* FLASH and environment organization */ #define CONFIG_FSL_IIM diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 10e46c628d..e416f81e43 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -19,15 +19,11 @@ #endif #define CONFIG_MXC_GPT_HCLK -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - #include <linux/sizes.h> #include <asm/arch/imx-regs.h> #include <asm/mach-imx/gpio.h> /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 32 /* MMC */ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 832f73f05e..cffbb64bcd 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -16,13 +16,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -/* SATA Configuration */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - /* Framebuffer */ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP @@ -34,7 +27,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "som_rev=undefined\0" \ "has_emmc=undefined\0" \ @@ -94,20 +86,11 @@ #include <config_distro_bootcmd.h> -#else -#define CONFIG_EXTRA_ENV_SETTINGS -#endif /* CONFIG_SPL_BUILD */ - /* Physical Memory Map */ #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ #endif /* __MX6CUBOXI_CONFIG_H */ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index 42d5e248ba..ad53f17d67 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -25,8 +25,6 @@ #error please define serial console (CONFIG_SERIAL_CONSOLE_UARTx) #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16) - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -34,11 +32,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index d7408e06a0..bfcab1bed5 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -143,11 +143,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ /* Framebuffer */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index a212652fd7..bc4aa52f5b 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -16,8 +16,6 @@ #define CONSOLE_DEV "ttymxc3" /* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 @@ -28,13 +26,7 @@ /* Falcon Mode */ #ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif #ifdef CONFIG_MTD_NOR_FLASH @@ -42,7 +34,6 @@ #define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #endif #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 5a854b9d19..16f8858abb 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -18,19 +18,12 @@ #include "mx6sabre_common.h" /* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #define CONFIG_SYS_FSL_USDHC_NUM 3 #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif @@ -41,10 +34,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif #endif /* __MX6SABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 3da796d03a..9f890938f9 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -90,19 +90,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #define CONFIG_SYS_FSL_USDHC_NUM 3 diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 1b32f58afc..e9ccb99d3c 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -86,11 +86,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ /* MMC Configs */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 372cf8dd71..c878041400 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -82,11 +82,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR @@ -102,10 +97,8 @@ #define CONFIG_FEC_MXC_PHYADDR 0x0 #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 76e3dc8b38..570e2ce687 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -19,8 +19,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #ifdef CONFIG_IMX_BOOTAUX -/* Set to QSPI2 B flash at default */ -#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 #define UPDATE_M4_ENV \ "m4image=m4_qspi.bin\0" \ @@ -35,7 +33,7 @@ "sf write ${loadaddr} 0x0 ${filesize}; " \ "fi; " \ "fi\0" \ - "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" + "m4boot=sf probe 1:0; bootaux 0x78000000\0" #else #define UPDATE_M4_ENV "" #endif @@ -116,11 +114,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR @@ -129,23 +122,15 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1 #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif -#ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_DM_VIDEO #define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR -#endif -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 03d799ce65..ab56ea0205 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -115,19 +115,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #ifdef CONFIG_CMD_NET @@ -140,10 +133,6 @@ #endif #endif -#ifndef CONFIG_SPL_BUILD -#if defined(CONFIG_DM_VIDEO) #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR -#endif -#endif #endif diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index bc494b46b6..00cc547b90 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -21,14 +21,8 @@ /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* NAND pin conflicts with usdhc2 */ -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#else #define CONFIG_SYS_FSL_USDHC_NUM 2 #endif -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ @@ -112,11 +106,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #define CONFIG_IOMUX_LPSR diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 9f7d60f8fb..4704276a74 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -17,14 +17,10 @@ #define CONFIG_MXC_GPT_HCLK #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - /* Enable iomux-lpsr support */ #define CONFIG_IOMUX_LPSR /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 32 /* UART */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index aaad232f0e..b96341a587 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -12,11 +12,7 @@ #define PHYS_SDRAM_SIZE SZ_1G -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR - #ifdef CONFIG_IMX_BOOTAUX -/* Set to QSPI1 A flash at default */ -#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 #define UPDATE_M4_ENV \ "m4image=m4_qspi.bin\0" \ @@ -31,7 +27,7 @@ "sf write ${loadaddr} 0x0 ${filesize}; " \ "fi; " \ "fi\0" \ - "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" + "m4boot=sf probe 0:0; bootaux 0x60000000\0" #else #define UPDATE_M4_ENV "" #endif @@ -89,11 +85,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ /* diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index f8a5009637..62e8e62991 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -15,8 +15,6 @@ #include "imx7ulp_spl.h" #endif -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE @@ -53,10 +51,5 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE SZ_256K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 7644274d84..e93824928b 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -11,8 +11,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE @@ -23,9 +21,6 @@ #define LPUART_BASE LPUART4_RBASE /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 - -#define CONFIG_SYS_MAXARGS 256 /* Physical Memory Map */ @@ -100,9 +95,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE SZ_256K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #endif /* __CONFIG_H */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 8dcc45c9e5..fc15ed82c6 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -43,11 +43,6 @@ /* Startup hooks */ -/* SPL */ -#ifndef CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#endif - /* Memory sizes */ /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ @@ -59,10 +54,6 @@ #endif /* Point initial SP in SRAM so SPL can use it too. */ -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* * We need to sacrifice first 4 bytes of RAM here to avoid triggering some @@ -78,10 +69,6 @@ */ /* U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ /* * Drivers diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 6801fc109e..4162ee8caa 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -29,25 +29,16 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* NAND */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_addr_r=0x82000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -59,7 +50,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, UBI, boot) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/nas220.h b/include/configs/nas220.h index 815f81f649..1b7eb34334 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -37,13 +37,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=console=ttyS0,115200\0" \ - "mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),"\ - "0x010000@0xa0000(env),"\ - "0x500000@0xc0000(uimage),"\ - "0x1a40000@0x5c0000(rootfs)\0" \ - "mtdids=nand0=orion_nand\0"\ - "autostart=no\0"\ - "autoload=no\0" + "autostart=no\0" /* * Ethernet Driver configuration diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index afa4ca5b5a..2007b48868 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -19,21 +19,10 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 6 /* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 @@ -106,19 +95,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ -/* - * PCI express - */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index f273e243e5..97aafc5f72 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -153,7 +153,6 @@ * This rate is divided by a local divisor. */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* * Physical Memory Map @@ -167,8 +166,6 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Attached kernel image diff --git a/include/configs/novena.h b/include/configs/novena.h index dbde7a0ade..1696aa2852 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -34,17 +34,11 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* SPL */ #include "imx6_spl.h" /* common IMX6 SPL configuration */ /* I2C */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C EEPROM */ @@ -54,8 +48,6 @@ /* PCI express */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) #endif @@ -64,15 +56,11 @@ #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -/* SATA Configs */ -#define CONFIG_LBA48 - /* UART */ #define CONFIG_MXC_UART_BASE UART2_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 /* Gadget part */ @@ -84,7 +72,6 @@ #define CONFIG_IMX_VIDEO_SKIP /* Extra U-Boot environment. */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -155,8 +142,4 @@ #include <config_distro_bootcmd.h> -#else -#define CONFIG_EXTRA_ENV_SETTINGS -#endif /* CONFIG_SPL_BUILD */ - #endif /* __CONFIG_H */ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index c250fa6506..217427a302 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -30,20 +30,13 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* NAND */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #ifdef CONFIG_CMD_NET #define CONFIG_FEC_MXC_PHYADDR 0x1 @@ -55,8 +48,6 @@ "console=ttymxc0,115200n8\0" \ "image=zImage\0" \ "fdtfile=imx6ull-seeed-npi-dev-board.dtb\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_addr_r=0x82000000\0" \ "kernel_addr_r=0x81000000\0" \ "pxefile_addr_r=0x87100000\0" \ @@ -67,7 +58,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, UBI, boot) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index 1e6b8d8b0e..027a47b5a3 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -15,8 +15,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/zImage\0" \ "fdt=/boot/nsa310s.dtb\0" \ "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0" @@ -25,8 +23,4 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 1 -/* Support large HDDs for USB and SATA */ -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - #endif /* _CONFIG_NSA310S_H */ diff --git a/include/configs/nsim.h b/include/configs/nsim.h index de07b6b15f..d469ef83c2 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -16,11 +16,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_256M -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_32M - /* * Console configuration */ diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 7777935ba6..00f7d87127 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -10,8 +10,6 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #if IS_ENABLED(CONFIG_CMD_USB) # define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index 7e71c83887..0fa7490e7d 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -16,6 +16,4 @@ #define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #endif /* __OCTEON_COMMON_H__ */ diff --git a/include/configs/octeon_ebb7304.h b/include/configs/octeon_ebb7304.h index 8c6c57bd54..7035e63134 100644 --- a/include/configs/octeon_ebb7304.h +++ b/include/configs/octeon_ebb7304.h @@ -13,7 +13,6 @@ * CFI flash */ #define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ diff --git a/include/configs/octeon_nic23.h b/include/configs/octeon_nic23.h index 0a7b4d8f93..7d99fd1b01 100644 --- a/include/configs/octeon_nic23.h +++ b/include/configs/octeon_nic23.h @@ -7,15 +7,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -/* - * SATA/SCSI/AHCI configuration - */ -/* AHCI support Definitions */ -/** Enable 48-bit SATA addressing */ -#define CONFIG_LBA48 -/** Enable 64-bit addressing */ -#define CONFIG_SYS_64BIT_LBA - #include "octeon_common.h" #endif /* __CONFIG_H__ */ diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index 6ec2d3e268..2c430e8d37 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -8,25 +8,16 @@ #define __OCTEONTX2_COMMON_H__ /** Maximum size of image supported for bootm (and bootable FIT images) */ -#define CONFIG_SYS_BOOTM_LEN (256 << 20) /** Memory base address */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE /** Stack starting address */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) /** Extra environment settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=20080000\0" \ - "ethrotate=yes\0" \ - "autoload=0\0" - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MAXARGS 64 /** max command args */ + "ethrotate=yes\0" #define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192 diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 81dbff2d67..e7a6bd41db 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -18,7 +18,6 @@ #include <config_distro_bootcmd.h> /* Extra environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=0\0" \ "loadaddr=0x20080000\0" \ "kernel_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x03000000\0" \ @@ -35,30 +34,14 @@ #endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ /** Maximum size of image supported for bootm (and bootable FIT images) */ -#define CONFIG_SYS_BOOTM_LEN (256 << 20) /** Memory base address */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE /** Stack starting address */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) /** Heap size for U-Boot */ -/* AHCI support Definitions */ -#ifdef CONFIG_DM_SCSI -/** Enable 48-bit SATA addressing */ -# define CONFIG_LBA48 -/** Enable 64-bit addressing */ -# define CONFIG_SYS_64BIT_LBA -#endif - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MAXARGS 64 /** max command args */ - #define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192 /** EMMC specific defines */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index b8b47af471..7448cc9520 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -24,9 +24,6 @@ #include <linux/sizes.h> -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - /* Partitions name */ #define PARTS_BOOT "boot" #define PARTS_ROOT "platform" @@ -147,14 +144,6 @@ "kernel_addr_r=0x41000000\0" \ BOOTENV -/* GPT */ - -/* Security subsystem - enable hw_rand() */ -#define CONFIG_EXYNOS_ACE_SHA - -/* USB */ -#define CONFIG_USB_EHCI_EXYNOS - /* * Supported Odroid boards: X3, U3 * TODO: Add Odroid X support diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 360815bc03..1564629742 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -16,11 +16,6 @@ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) - -/* USB */ -#define CONFIG_USB_EHCI_EXYNOS - /* DFU */ #define DFU_DEFAULT_POLL_TIMEOUT 300 #define DFU_MANIFEST_POLL_TIMEOUT 25000 @@ -33,9 +28,6 @@ #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 -/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ -#undef CONFIG_EXYNOS_TMU - #define CONFIG_DFU_ALT_SYSTEM \ "uImage fat 0 1;" \ "zImage fat 0 1;" \ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 158773aced..2cd42e5a1d 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -28,9 +28,6 @@ #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_SYS_ENV_SECT_SIZE SZ_128K /* NAND: SPL falcon mode configs */ -#if defined(CONFIG_SPL_OS_BOOT) -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 -#endif /* CONFIG_SPL_OS_BOOT */ #endif /* CONFIG_MTD_RAW_NAND */ /* Enable Multi Bus support for I2C */ @@ -65,7 +62,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(LEGACY_MMC, legacy_mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, rootfs, rootfs) \ func(NAND, nand, 0) #else /* !CONFIG_MTD_RAW_NAND */ @@ -87,8 +84,6 @@ "bootenv=uEnv.txt\0" \ "bootfile=zImage\0" \ "bootpart=0:2\0" \ - "bootubivol=rootfs\0" \ - "bootubipart=rootfs\0" \ "usbtty=cdc_acm\0" \ "mpurate=auto\0" \ "buddy=none\0" \ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index eeb9ef8c74..2683d4c7ea 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -32,10 +32,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_SYS_ENV_SECT_SIZE SZ_128K -/* NAND: SPL falcon mode configs */ -#if defined(CONFIG_SPL_OS_BOOT) -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 -#endif /* CONFIG_SPL_OS_BOOT */ #endif /* CONFIG_MTD_RAW_NAND */ #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ @@ -60,7 +56,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(LEGACY_MMC, legacy_mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, rootfs, rootfs) \ func(NAND, nand, 0) #else /* !CONFIG_MTD_RAW_NAND */ @@ -80,16 +76,12 @@ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_high=0xffffffff\0" \ "console=ttyO0,115200n8\0" \ "bootdir=/boot\0" \ "bootenv=uEnv.txt\0" \ "bootfile=zImage\0" \ "bootpart=0:2\0" \ - "bootubivol=rootfs\0" \ - "bootubipart=rootfs\0" \ "optargs=\0" \ "nandroot=ubi0:rootfs ubi.mtd=rootfs rw noinitrd\0" \ "nandrootfstype=ubifs rootwait\0" \ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index c1ef040ce3..97f47ea5b7 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -28,8 +28,6 @@ #define GPIO_IGEP00X0_BOARD_DETECTION 28 #define GPIO_IGEP00X0_REVISION_DETECTION 129 -#ifndef CONFIG_SPL_BUILD - /* Environment */ #define ENV_DEVICE_SETTINGS \ "stdin=serial\0" \ @@ -67,10 +65,7 @@ MEM_LAYOUT_SETTINGS \ BOOTENV -#endif - /* OneNAND config */ -#define CONFIG_USE_ONENAND_BOARD_INIT #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index d3839eb122..38dc7ea88f 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -35,8 +35,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "mmcrootfstype=ext4 rootwait\0" \ @@ -87,7 +85,6 @@ "nfsroot=${nfsrootpath} " \ "ip=${ipaddr}:${tftpserver}:${gatewayip}:${netmask}::eth0:off\0" \ "nfsrootpath=/opt/nfs-exports/omap\0" \ - "autoload=no\0" \ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "loadfdt=mmc rescan; " \ "load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \ @@ -154,16 +151,8 @@ #endif #define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_SIZE 0x4000000 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -/* Defines for SPL */ - -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 75e84c35ee..cce5556fe2 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -40,9 +40,6 @@ #define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 -/* USB UHH support options */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - /* Enabled commands */ /* USB Networking options */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 0d69316862..c644768ae7 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -28,9 +28,6 @@ #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ -#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE -#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 - /* memtest start addr */ /* memtest will be run on 16MB */ @@ -102,8 +99,6 @@ /* * I2C Configuration */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 /* @@ -139,14 +134,6 @@ /* * U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ - -/* - * USB Configs - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 /* * Linux Information @@ -174,17 +161,9 @@ /* SD/MMC */ /* defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SPL_STACK 0x8001ff00 -#define CONFIG_SPL_MAX_FOOTPRINT 32768 -#define CONFIG_SPL_PAD_TO 32768 /* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) #include <asm/arch/hardware.h> diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h index 75b48f880a..3ff8187b5d 100644 --- a/include/configs/openpiton-riscv64.h +++ b/include/configs/openpiton-riscv64.h @@ -15,22 +15,6 @@ /* Environment options */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32M) -#define CONFIG_SYS_BOOTM_LEN SZ_256M - -#ifdef CONFIG_SPL -#define CONFIG_SPL_MAX_SIZE 0x00100000 -#define CONFIG_SPL_BSS_START_ADDR 0x82000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0100000 -#define CONFIG_SPL_STACK (0x80000000 + 0x04000000 - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "boot/fw_payload.bin" -#define CONFIG_SPL_GD_ADDR 0x85000000 -#endif /* --------------------------------------------------------------------- * Board boot configuration diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 1f2887105f..3e551e13aa 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -21,158 +21,16 @@ #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* USB */ #ifdef CONFIG_USB_EHCI_MX6 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* LCD */ -#ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_DM_VIDEO #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR -#endif -#endif -/* Environment is stored in the eMMC boot partition */ - -#define CONFIG_ENV_VERSION 100 -#define ACFG_CONSOLE_DEV ttymxc0 -#define CONFIG_SYS_AUTOLOAD "no" #define CONFIG_ROOTPATH "/tftpboot/opos6ul-root" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ - "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ - "board_name=opos6ul\0" \ - "fdt_addr=0x88000000\0" \ - "fdt_high=0xffffffff\0" \ - "fdt_name=opos6uldev\0" \ - "initrd_high=0xffffffff\0" \ - "ip_dyn=yes\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "kernelimg=opos6ul-linux.bin\0" \ - "splashpos=0,0\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \ - "check_env=if test -n ${flash_env_version}; " \ - "then env default env_version; " \ - "else env set flash_env_version ${env_version}; env save; " \ - "fi; " \ - "if itest ${flash_env_version} != ${env_version}; then " \ - "echo \"*** Warning - Environment version" \ - " change suggests: run flash_reset_env; reset\"; " \ - "env default flash_reset_env; " \ - "else exit; fi; \0" \ - "flash_reset_env=env default -f -a && saveenv && " \ - "echo Environment variables erased!\0" \ - "download_uboot_spl=tftpboot ${loadaddr} ${board_name}-u-boot.spl\0" \ - "flash_uboot_spl=" \ - "if mmc dev 0 1; then " \ - "setexpr sz ${filesize} / 0x200; " \ - "setexpr sz ${sz} + 1; " \ - "if mmc write ${loadaddr} 0x2 ${sz}; then " \ - "echo Flashing of U-boot SPL succeed; " \ - "else echo Flashing of U-boot SPL failed; " \ - "fi; " \ - "fi;\0" \ - "download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img\0" \ - "flash_uboot_img=" \ - "if mmc dev 0 1; then " \ - "setexpr sz ${filesize} / 0x200; " \ - "setexpr sz ${sz} + 1; " \ - "if mmc write ${loadaddr} 0x8a ${sz}; then " \ - "echo Flashing of U-boot image succeed; " \ - "else echo Flashing of U-boot image failed; " \ - "fi; " \ - "fi;\0" \ - "update_uboot=run download_uboot_spl flash_uboot_spl " \ - "download_uboot_img flash_uboot_img\0" \ - "download_kernel=tftpboot ${loadaddr} ${kernelimg}\0" \ - "flash_kernel=" \ - "if ext4write mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} ${filesize}; then " \ - "echo kernel update succeed; " \ - "else echo kernel update failed; " \ - "fi;\0" \ - "update_kernel=run download_kernel flash_kernel\0" \ - "download_dtb=tftpboot ${fdt_addr} imx6ul-${fdt_name}.dtb\0" \ - "flash_dtb=" \ - "if ext4write mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb ${filesize}; then " \ - "echo dtb update succeed; " \ - "else echo dtb update in failed; " \ - "fi;\0" \ - "update_dtb=run download_dtb flash_dtb\0" \ - "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ext4\0" \ - "flash_rootfs=" \ - "if mmc dev 0 0; then " \ - "setexpr nbblocks ${filesize} / 0x200; " \ - "setexpr nbblocks ${nbblocks} + 1; " \ - "if mmc write ${loadaddr} 0x40800 ${nbblocks}; then " \ - "echo Flashing of rootfs image succeed; " \ - "else echo Flashing of rootfs image failed; " \ - "fi; " \ - "fi;\0" \ - "update_rootfs=run download_rootfs flash_rootfs\0" \ - "flash_failsafe=" \ - "if mmc dev 0 0; then " \ - "setexpr nbblocks ${filesize} / 0x200; " \ - "setexpr nbblocks ${nbblocks} + 1; " \ - "if mmc write ${loadaddr} 0x800 ${nbblocks}; then " \ - "echo Flashing of rootfs image in failsafe partition succeed; " \ - "else echo Flashing of rootfs image in failsafe partition failed; " \ - "fi; " \ - "fi;\0" \ - "update_failsafe=run download_rootfs flash_failsafe\0" \ - "download_userdata=tftpboot ${loadaddr} ${board_name}-user_data.ext4\0" \ - "flash_userdata=" \ - "if mmc dev 0 0; then " \ - "setexpr nbblocks ${filesize} / 0x200; " \ - "setexpr nbblocks ${nbblocks} + 1; " \ - "if mmc write ${loadaddr} 0 ${nbblocks}; then " \ - "echo Flashing of user_data image succeed; " \ - "else echo Flashing of user_data image failed; " \ - "fi; " \ - "fi;\0" \ - "update_userdata=run download_userdata flash_userdata; mmc rescan\0" \ - "erase_userdata=" \ - "if mmc dev 0 0; then " \ - "echo Erasing eMMC User Data partition, no way out...; " \ - "mw ${loadaddr} 0 0x200000; " \ - "mmc write ${loadaddr} 0 0x1000; " \ - "mmc write ${loadaddr} 0x800 0x1000; " \ - "mmc write ${loadaddr} 0x40800 0x1000; " \ - "mmc write ${loadaddr} 0x440800 0x1000; " \ - "fi;" \ - "mmc rescan\0" \ - "update_all=run update_rootfs update_uboot\0" \ - "initargs=setenv bootargs console=${consoledev},${baudrate} ${extrabootargs}\0" \ - "addipargs=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ - "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ - "addmmcargs=setenv bootargs ${bootargs} root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "emmcboot=run initargs; run addmmcargs; " \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} && " \ - "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb && " \ - "bootz ${loadaddr} - ${fdt_addr};\0" \ - "emmcsafeboot=setenv mmcpart 1; setenv mmcroot /dev/mmcblk0p1 ro; run emmcboot;\0" \ - "addnfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "nfsboot=run initargs; run addnfsargs addipargs; " \ - "nfs ${loadaddr} ${serverip}:${rootpath}/boot/${kernelimg} && " \ - "nfs ${fdt_addr} ${serverip}:${rootpath}/boot/imx6ul-${fdt_name}.dtb && " \ - "bootz ${loadaddr} - ${fdt_addr};\0" - #endif /* __OPOS6ULDEV_CONFIG_H */ diff --git a/include/configs/origen.h b/include/configs/origen.h index c4f5997c3d..36aaa7c14f 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -10,10 +10,6 @@ #include <configs/exynos4-common.h> -/* High Level Configuration Options */ -#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ -#define CONFIG_ORIGEN 1 /* working with ORIGEN*/ - /* ORIGEN has 4 bank of DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE @@ -48,8 +44,4 @@ #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_SYS_INIT_SP_ADDR 0x02040000 - #endif /* __CONFIG_H */ diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h index fabbb01e0c..b0233b96b0 100644 --- a/include/configs/owl-common.h +++ b/include/configs/owl-common.h @@ -20,11 +20,7 @@ * image to the top of SDRAM. After relocation u-boot moves the stack to the * proper place. */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00) /* Console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #endif diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h new file mode 100644 index 0000000000..13e4fdb4fd --- /dev/null +++ b/include/configs/p1_p2_bootsrc.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + * Copyright 2022 Pali Rohár <pali@kernel.org> + */ + +#include <linux/stringify.h> + +#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR) +#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required" +#endif + +#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1 + +#define __VAR_CMD(var, cmd) __stringify(var=cmd\0) +#define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset) + +#ifdef __SW_NOR_BANK_LO +#define MAP_NOR_LO_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK)) +#else +#define MAP_NOR_LO_CMD(var, ...) "" +#endif + +#ifdef __SW_NOR_BANK_UP +#define MAP_NOR_UP_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK)) +#else +#define MAP_NOR_UP_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_NOR +#define RST_NOR_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)) +#else +#define RST_NOR_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_SPI +#define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK)) +#else +#define RST_SPI_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_SD +#define RST_SD_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD, __SW_BOOT_MASK)) +#else +#define RST_SD_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_NAND +#define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)) +#else +#define RST_NAND_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_PCIE +#define RST_PCIE_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)) +#else +#define RST_PCIE_CMD(var, ...) "" +#endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index f6ecf2a7a8..a0d583040c 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -77,90 +77,41 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif #elif defined(CONFIG_SPIFLASH) -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) #elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_MAX_SIZE 4096 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 -#else -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif /* not CONFIG_TPL_BUILD */ - -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ - -#define CONFIG_LBA48 - #define CONFIG_HWCONFIG /* * These can be toggled for performance analysis, otherwise use default. */ #define CONFIG_L2_CACHE -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k - SPL code*/ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - /* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 #if defined(CONFIG_TARGET_P1020RDB_PD) @@ -181,7 +132,6 @@ #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 @@ -215,7 +165,6 @@ * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable * (early boot only) * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 - * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable @@ -310,9 +259,7 @@ /* Size of used area in RAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -324,14 +271,6 @@ #endif /* CPLD config size: 1Mb */ -#define CONFIG_SYS_PMC_BASE 0xff980000 -#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE -#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ - BR_PS_8 | BR_V) -#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ - OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ - OR_GPCM_EAD) - /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET #define __VSCFW_ADDR "vscfw_addr=ef000000\0" @@ -365,31 +304,15 @@ #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) -#if defined(CONFIG_TARGET_P2020RDB) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) -#else -#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) -#endif #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) #else #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) -#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) #endif /* CONFIG_TPL_BUILD */ #endif #endif @@ -402,7 +325,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) +#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) #define CONFIG_NS16550_MIN_FUNCTIONS #endif @@ -417,8 +340,6 @@ #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } #endif -#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ - /* * I2C2 EEPROM */ @@ -462,8 +383,6 @@ #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) @@ -490,15 +409,10 @@ /* * Environment */ -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) #endif -#elif defined(CONFIG_SYS_RAMBOOT) -#define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #endif #define CONFIG_LOADS_ECHO /* echo on for serial download */ @@ -507,17 +421,6 @@ /* * USB */ -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - -#if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR @@ -533,7 +436,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration @@ -542,31 +444,7 @@ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#ifdef __SW_BOOT_NOR -#define __NOR_RST_CMD \ -norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_SPI -#define __SPI_RST_CMD \ -spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_SD -#define __SD_RST_CMD \ -sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_NAND -#define __NAND_RST_CMD \ -nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_PCIE -#define __PCIE_RST_CMD \ -pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif +#include "p1_p2_bootsrc.h" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -593,13 +471,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset "nandfdtaddr=80000\0" \ "ramdisk_size=120000\0" \ __VSCFW_ADDR \ -"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ -"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ -__stringify(__NOR_RST_CMD)"\0" \ -__stringify(__SPI_RST_CMD)"\0" \ -__stringify(__SD_RST_CMD)"\0" \ -__stringify(__NAND_RST_CMD)"\0" \ -__stringify(__PCIE_RST_CMD)"\0" +MAP_NOR_LO_CMD(map_lowernorbank) \ +MAP_NOR_UP_CMD(map_uppernorbank) \ +RST_NOR_CMD(norboot) \ +RST_SPI_CMD(spiboot) \ +RST_SD_CMD(sdboot) \ +RST_NAND_CMD(nandboot) \ +RST_PCIE_CMD(pciboot) \ +"" #define CONFIG_USB_FAT_BOOT \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 31b7d07a24..6e593da936 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -41,25 +41,16 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* NAND */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_addr_r=0x82000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -71,7 +62,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, UBI, boot) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 068fc7db34..ae81b8e214 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -43,20 +43,13 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* NAND */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 79b69dfe17..a8cfec9659 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -33,7 +33,6 @@ /* Extra env settings (including the target-defined ones if any) */ #define CONFIG_EXTRA_ENV_SETTINGS \ PCM052_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "blimg_file=u-boot.vyb\0" \ @@ -50,7 +49,6 @@ "nfs_root=/path/to/nfs/root\0" \ "tftptimeout=1000\0" \ "tftptimeoutcountmax=1000000\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "bootargs_base=setenv bootargs rw " \ " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \ "console=ttyLP1,115200n8\0" \ @@ -126,11 +124,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #endif diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 4d4185b466..cff71df1c9 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -24,11 +24,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ #define ENV_MMC \ "mmcdev=0\0" \ @@ -42,8 +37,6 @@ "mmcboot=run mmcloadfit;run mmcargs;bootm ${loadaddr}\0" #define ENV_NAND \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandroot=ubi0:root ubi.mtd=rootfs\0" \ "nandrootfstype=ubifs\0" \ "nandargs=setenv bootargs root=${nandroot} " \ diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index 7ab6a89604..ed3201aa3c 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -32,7 +32,6 @@ #define CONSOLE_DEV "ttyO5" #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "fdtfile=am335x-pdu001.dtb\0" \ @@ -49,7 +48,6 @@ "reset;" \ "fi;" \ "\0" -#endif /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 UART0_BASE diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index ba82aaf653..7a8d3c63d4 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -21,14 +21,6 @@ #include <configs/exynos5-common.h> #define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) - -/* Display */ -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_BPP LCD_COLOR16 -#endif #define CONFIG_POWER_TPS65090_EC diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 16fb2f3a0e..2c749ac214 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -21,7 +21,6 @@ #include <configs/exynos5-common.h> #define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index af6f7e14df..f69d8adb91 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -16,8 +16,6 @@ #ifdef CONFIG_MTD_RAW_NAND #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${nandroot} " \ @@ -97,10 +95,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -/* NAND: SPL related configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ -#endif #endif /* !CONFIG_MTD_RAW_NAND */ /* CPU */ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 46fadd5610..049d1d7434 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -11,23 +11,14 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -72,10 +63,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -83,12 +70,4 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - #endif /* __PHYCORE_IMX8MM_H */ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index eb92c42339..df1716106f 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -10,21 +10,11 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -#define CONFIG_SPL_MAX_SIZE (152 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x960000 -#define CONFIG_SPL_BSS_START_ADDR 0x98FC00 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PCA9450 @@ -72,10 +62,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -83,12 +69,4 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - #endif /* __PHYCORE_IMX8MP_H */ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index ef3b0f73d6..0a07c9c29c 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -23,12 +23,9 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 #define CONFIG_SYS_INIT_RAM_ADDR \ (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) /* SDRAM Configuration (for final code, data, stack, heap) */ #define CONFIG_SYS_SDRAM_BASE 0x88000000 -#define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10) #define CONFIG_SYS_MONITOR_LEN (192 << 10) @@ -41,7 +38,6 @@ /*------------------------------------------------------------ * Console Configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /*-------------------------------------------------- * USB Configuration diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index c288908046..df4dc4d496 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -14,13 +14,8 @@ #ifdef CONFIG_SPL_OS_BOOT /* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif #define CONFIG_MXC_UART_BASE UART1_BASE @@ -109,11 +104,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ /* Ethernet Configuration */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 1f111ea306..2ac48c40c9 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -16,13 +16,8 @@ #ifdef CONFIG_SPL_OS_BOOT /* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x88000000 /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif /* Network support */ @@ -35,10 +30,8 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USBD_HS @@ -109,11 +102,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #ifdef CONFIG_DM_VIDEO diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 06fd78f9da..7fbf2c3f55 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -14,13 +14,8 @@ #ifdef CONFIG_SPL_OS_BOOT /* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x88000000 /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR @@ -110,11 +105,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* PMIC */ #define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 @@ -126,9 +116,7 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 1dc7d35259..d1cc1b9d63 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -9,22 +9,15 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* ENET Config */ @@ -74,10 +67,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -86,16 +75,7 @@ #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_BOOTM_LEN SZ_128M - #endif diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h index d478b19917..241dc39be0 100644 --- a/include/configs/pinebook-pro-rk3399.h +++ b/include/configs/pinebook-pro-rk3399.h @@ -16,7 +16,4 @@ #define SDRAM_BANK_SIZE (2UL << 30) -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - #endif diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 1db8279397..7374514698 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -152,17 +152,9 @@ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "partition=nand0,0\0" \ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -179,7 +171,5 @@ "" #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ - GENERATED_GBL_DATA_SIZE) #endif diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 143e9f542a..7a6d817926 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -175,17 +175,9 @@ AT91_MATRIX_SCFG_SLOT_CYCLE(255)) /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "partition=nand0,0\0" \ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -202,7 +194,5 @@ "" #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ - GENERATED_GBL_DATA_SIZE) #endif diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index b858aaa1cc..69f3d06587 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -23,9 +23,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x70000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -46,22 +43,11 @@ #endif /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE 0x010000 -#define CONFIG_SPL_STACK 0x310000 #define CONFIG_SYS_MONITOR_LEN 0x80000 #ifdef CONFIG_SD_BOOT - -#define CONFIG_SPL_BSS_START_ADDR 0x70000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 -#define CONFIG_SYS_SPL_MALLOC_START 0x70080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - #elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 #define CONFIG_SYS_NAND_ECCSIZE 256 diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index cb221501e2..085732214e 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -19,9 +19,6 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \ - "32M(rootfs),-(data)\0"\ - "mtdids=nand0=orion_nand\0"\ "bootargs_console=console=ttyS0,115200\0" \ "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \ "ext2load usb 0:1 0x01100000 /uInitrd\0" diff --git a/include/configs/pogo_v4.h b/include/configs/pogo_v4.h index 3365ebe3d2..7fff78b7b5 100644 --- a/include/configs/pogo_v4.h +++ b/include/configs/pogo_v4.h @@ -26,8 +26,6 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ "dtb_file=/boot/dts/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"\ - "mtdids=nand0=orion_nand\0"\ "bootargs_console=console=ttyS0,115200\0" \ "bootcmd_usb=usb start; load usb 0:1 0x00800000 /boot/uImage; " \ "load usb 0:1 0x01100000 /boot/uInitrd; " \ @@ -39,10 +37,4 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -/* - * Support large disk for SATA and USB - */ -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 - #endif /* _CONFIG_POGO_V4_H */ diff --git a/include/configs/poleg.h b/include/configs/poleg.h index c21b063c05..f1c259f476 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -11,12 +11,8 @@ #define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ #endif -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_BOOTMAPSZ (0x30 << 20) #define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_INIT_SP_ADDR (0x00008000 - GENERATED_GBL_DATA_SIZE) /* Default environemnt variables */ #define CONFIG_SERVERIP 192.168.0.1 diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h index cdd6cdb58d..2e206542f8 100644 --- a/include/configs/pomelo.h +++ b/include/configs/pomelo.h @@ -12,17 +12,13 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* SIZE of malloc pool */ -#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000) /*BOOT*/ -#define CONFIG_SYS_BOOTM_LEN 0x3c00000 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(SCSI, scsi, 0) \ #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/poplar.h b/include/configs/poplar.h index 222a14bc8f..c58105597e 100644 --- a/include/configs/poplar.h +++ b/include/configs/poplar.h @@ -16,13 +16,10 @@ /* DRAM banks */ /* SYS */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SYS_INIT_SP_ADDR 0x200000 /* ATF bl33.bin load address (must match) */ /* USB configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /***************************************************************************** * Initial environment variables @@ -32,9 +29,7 @@ func(USB, usb, 0) \ func(MMC, mmc, 0) \ func(DHCP, dhcp, na) -#ifndef CONFIG_SPL_BUILD #include <config_distro_bootcmd.h> -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "loader_mmc_blknum=0x0\0" \ @@ -49,8 +44,4 @@ "ramdisk_addr_r=0x32400000\0" \ BOOTENV -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 64 - #endif /* _POPLAR_H_ */ diff --git a/include/configs/porter.h b/include/configs/porter.h index bf380ddf05..88fa65e0ff 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -12,10 +12,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -39,7 +38,5 @@ "bootm_size=0x10000000\0" /* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 #endif /* __PORTER_H */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index 1d526a7380..90f548cc6c 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -8,9 +8,6 @@ #ifndef __PRESIDIO_ASIC_H #define __PRESIDIO_ASIC_H -#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 -#define CONFIG_SYS_BOOTM_LEN 0x00c00000 - /* Generic Timer Definitions */ #define CONFIG_SYS_TIMER_RATE 25000000 #define CONFIG_SYS_TIMER_COUNTER 0xf4321008 @@ -42,10 +39,6 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define KSEG1_ATU_XLAT(x) (x) @@ -61,7 +54,6 @@ #define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c /* max command args */ -#define CONFIG_SYS_MAXARGS 64 #define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0" /* nand driver parameters */ diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index a7f5e91165..49d1878ebd 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -8,31 +8,18 @@ #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_NS16550_MEM32 /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ #define CONFIG_IRAM_BASE 0xff020000 -#define CONFIG_SYS_INIT_SP_ADDR 0x00400000 -#define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SPL_MAX_SIZE 0x20000 -#define CONFIG_SPL_BSS_START_ADDR 0x4000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x4000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define GICD_BASE 0xff131000 #define GICC_BASE 0xff132000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ @@ -50,5 +37,3 @@ BOOTENV #endif - -#endif diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 7272470d12..4f24b13f50 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -30,10 +30,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ -#define CONFIG_FACTORYSET - -#ifndef CONFIG_SPL_BUILD - /* Use common default */ /* Default env settings */ @@ -69,9 +65,4 @@ "bootm ${kloadaddr}\0" \ "" -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif -#endif /* CONFIG_SPL_BUILD */ - #endif /* ! __CONFIG_PXM2_H */ diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 550e26f3f1..e9f756b13e 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -12,11 +12,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 -/* The DTB generated by QEMU is placed at start of RAM, stay away from there */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* GUIDs for capsule updatable firmware images */ #define QEMU_ARM_UBOOT_IMAGE_GUID \ EFI_GUID(0xf885b085, 0x99f8, 0x45af, 0x84, 0x7d, \ @@ -79,8 +74,6 @@ "ramdisk_addr_r=0x44000000\0" \ BOOTENV -#define CONFIG_SYS_CBSIZE 512 - #define CONFIG_SYS_MAX_FLASH_SECT 256 /* Sector: 256K, Bank: 64M */ #endif /* __CONFIG_H */ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 136a2dfa71..31e94df84d 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -9,12 +9,6 @@ #ifndef __QEMU_PPCE500_H #define __QEMU_PPCE500_H -#define CONFIG_SYS_MPC85XX_NO_RESETVEC - -#define CONFIG_SYS_RAMBOOT - -#define CONFIG_ENABLE_36BIT_PHYS - /* Needed to fill the ccsrbar pointer */ /* Virtual address to CCSRBAR */ @@ -29,10 +23,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #endif -/* Virtual address range for PCI region maps */ -#define CONFIG_SYS_PCI_MAP_START 0x80000000 -#define CONFIG_SYS_PCI_MAP_END 0xe0000000 - /* Virtual address to a temporary map if we need it (max 128MB) */ #define CONFIG_SYS_TMPVIRT 0xe8000000 @@ -56,14 +46,10 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_LBA48 - /* RTC */ #define CONFIG_RTC_PT7C4338 @@ -83,7 +69,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index f462895fb5..d81e5d6c86 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -8,20 +8,7 @@ #include <linux/sizes.h> -#ifdef CONFIG_SPL - -#define CONFIG_SPL_MAX_SIZE 0x00100000 -#define CONFIG_SPL_BSS_START_ADDR 0x84000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 - -#endif - #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 @@ -32,7 +19,6 @@ /* Environment options */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(QEMU, qemu, na) \ func(VIRTIO, virtio, 0) \ @@ -61,6 +47,5 @@ "pxefile_addr_r=0x8c200000\0" \ "ramdisk_addr_r=0x8c300000\0" \ BOOTENV -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index e9dbd54517..ba843e35a4 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -34,6 +34,4 @@ * - AHCI controller is supported for QEMU '-M q35' target */ -#define CONFIG_SPL_BOARD_LOAD_IMAGE - #endif /* __CONFIG_H */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 54674094e8..409d5af024 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -9,8 +9,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x8C000000 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_PBSIZE 256 - /* Address of u-boot image in Flash */ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) @@ -27,9 +25,4 @@ */ #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ -/* - * SuperH PCI Bridge Configration - */ -#define CONFIG_SH7751_PCI - #endif /* __CONFIG_H */ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 8e20a448d2..49cd11c17b 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -37,13 +37,6 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_FACTORYSET - -/* Define own nand partitions */ -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - -#ifndef CONFIG_SPL_BUILD - /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=rastaban\0" \ @@ -55,8 +48,4 @@ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif -#endif /* CONFIG_SPL_BUILD */ #endif /* ! __CONFIG_RASTABAN_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 9bc2443498..2e54211690 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -10,16 +10,11 @@ #include <asm/arch/rmobile.h> -#ifdef CONFIG_SPL -#define CONFIG_SPL_TARGET "spl/u-boot-spl.srec" -#endif - #ifndef CONFIG_PINCTRL_PFC #define CONFIG_SH_GPIO_PFC #endif /* console */ -#define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } #define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 64743382ed..9efda3eeea 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -11,12 +11,6 @@ #include <asm/arch/rmobile.h> -#ifdef CONFIG_SPL -#define CONFIG_SPL_TARGET "spl/u-boot-spl.scif" -#endif - -#define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K - /* boot option */ /* Generic Interrupt Controller Definitions */ @@ -24,16 +18,12 @@ #define GICC_BASE 0xF1020000 /* console */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MAXARGS 64 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } /* PHY needs a longer autoneg timeout */ #define PHY_ANEG_TIMEOUT 20000 /* MEMORY */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define DRAM_RSV_SIZE 0x08000000 #define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) @@ -42,22 +32,10 @@ #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* ENV setting */ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ -#if defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796) || defined(CONFIG_R8A77965) -#define CONFIG_SPL_BSS_START_ADDR 0xe633f000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 -#else -#define CONFIG_SPL_BSS_START_ADDR 0xe631f000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 -#endif -#define CONFIG_SPL_STACK 0xe6304000 -#define CONFIG_SPL_MAX_SIZE 0x7000 - #endif /* __RCAR_GEN3_COMMON_H */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index f4f6bcab5e..6616396777 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -8,19 +8,12 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_HZ_CLOCK 24000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SPL_STACK 0x10081fff - #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE) -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ @@ -38,6 +31,5 @@ "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV -#endif #endif diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index be7d644e1e..9297184bde 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -9,22 +9,12 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 256 - -#define CONFIG_SYS_INIT_SP_ADDR 0x78000000 - #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SPL_MAX_SIZE 0x32000 - -#define CONFIG_SPL_STACK 0x1008FFFF - #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (1024UL << 20UL) #define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ @@ -42,6 +32,4 @@ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ - #endif diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 8f04e9de5a..12d4bc65d7 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -8,27 +8,15 @@ #include "rockchip-common.h" -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - /* RAW SD card / eMMC locations. */ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_MAX_SIZE 0x80000000 -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -#ifndef CONFIG_SPL_BUILD - /* usb mass storage */ #define ENV_MEM_LAYOUT_SETTINGS \ @@ -46,5 +34,3 @@ BOOTENV #endif - -#endif diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 5c4dfa61e0..6fe1b2d9a2 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -9,25 +9,14 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 - -#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM -/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ -#endif -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 - #define CONFIG_IRAM_BASE 0x10080000 /* spl size 32kb sram - 2kb bootrom */ -#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800) - -#define CONFIG_SPL_STACK 0x10087fff #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0x80000000 -#ifndef CONFIG_SPL_BUILD /* usb otg */ /* usb host support */ @@ -51,6 +40,4 @@ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ - #endif diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index f66a7d23be..4fb86b69a8 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -8,22 +8,14 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define CONFIG_SYS_HZ_CLOCK 24000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x61100000 -#define CONFIG_SPL_MAX_SIZE 0x100000 - #define CONFIG_IRAM_BASE 0x10080000 #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE 0x80000000 -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ @@ -41,6 +33,5 @@ "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV -#endif #endif diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 075623f342..f4b3481115 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -9,33 +9,18 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64MB */ - -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_HZ_CLOCK 24000000 -#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM -/* Bootrom will load u-boot binary to 0x0 once return from SPL */ -#endif -#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 -#define CONFIG_SPL_STACK 0xff718000 - #define CONFIG_IRAM_BASE 0xff700000 /* RAW SD card / eMMC locations. */ -/* FAT sd card locations. */ -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0xfe000000 #define CONFIG_SYS_MONITOR_LEN (600 * 1024) -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00000000\0" \ "pxefile_addr_r=0x00100000\0" \ @@ -55,6 +40,5 @@ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV -#endif #endif diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 44a3e7adf2..200b34b35b 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -8,27 +8,14 @@ #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SPL_MAX_SIZE 0x20000 -#define CONFIG_SPL_BSS_START_ADDR 0x00400000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 - #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_IRAM_BASE 0xfff80000 -#define CONFIG_SYS_INIT_SP_ADDR 0x00800000 -#define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ @@ -44,5 +31,3 @@ BOOTENV #endif - -#endif diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 2b8d77c47e..1e214e4ebe 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -10,22 +10,10 @@ #define CONFIG_IRAM_BASE 0xff090000 -#define CONFIG_SYS_CBSIZE 1024 - -#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 -#define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SPL_MAX_SIZE 0x40000 -#define CONFIG_SPL_BSS_START_ADDR 0x2000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - /* FAT sd card locations. */ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ @@ -41,9 +29,3 @@ BOOTENV #endif - -/* rockchip ohci host driver */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -#endif diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 2f71ce72df..37e0c1d936 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -13,20 +13,9 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#define CONFIG_SYS_CBSIZE 1024 #define CONFIG_IRAM_BASE 0xff8c0000 -#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 - -#define CONFIG_SPL_MAX_SIZE 0x40000 -#define CONFIG_SPL_BSS_START_ADDR 0x400000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x20000 -#define CONFIG_SPL_STACK 0x00188000 - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - -#ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ @@ -42,5 +31,3 @@ BOOTENV #endif - -#endif diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 8e13737666..2f9aee5819 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -8,27 +8,13 @@ #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_IRAM_BASE 0xff8c0000 -#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 - #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) -#define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SPL_MAX_SIZE 0x40000 -#define CONFIG_SPL_BSS_START_ADDR 0x00400000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 #else -#define CONFIG_SPL_STACK 0xff8effff -#define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000 /* BSS setup */ -#define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 #endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - /* MMC/SD IP block */ #define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index e9947ea492..15e8152340 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -8,23 +8,11 @@ #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_IRAM_BASE 0xfdcc0000 -#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 - -#define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SPL_MAX_SIZE 0x20000 -#define CONFIG_SPL_BSS_START_ADDR 0x4000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x4000 - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 -#ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00c00000\0" \ "pxefile_addr_r=0x00e00000\0" \ @@ -39,6 +27,5 @@ "partitions=" PARTS_DEFAULT \ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV -#endif #endif diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h index 2edad71028..6099d2fa55 100644 --- a/include/configs/rock960_rk3399.h +++ b/include/configs/rock960_rk3399.h @@ -14,7 +14,4 @@ #include <configs/rk3399_common.h> #define SDRAM_BANK_SIZE (2UL << 30) - -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 0c08776ae2..4c964cc377 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_NS16550_MEM32 /* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */ -#define CONFIG_SPL_PAD_TO 8355840 #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/rockpro64_rk3399.h b/include/configs/rockpro64_rk3399.h index 903e9df527..9195b9b99e 100644 --- a/include/configs/rockpro64_rk3399.h +++ b/include/configs/rockpro64_rk3399.h @@ -14,7 +14,4 @@ #include <configs/rk3399_common.h> #define SDRAM_BANK_SIZE (2UL << 30) - -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 7a5f0851b5..4f5025d0da 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -32,13 +32,6 @@ * the VC uses. */ #define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_SDRAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#ifdef CONFIG_ARM64 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#endif /* Devices */ /* LCD */ @@ -60,7 +53,6 @@ #endif /* Console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Environment */ diff --git a/include/configs/rut.h b/include/configs/rut.h index b30b12af52..ac48372b6c 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -21,13 +21,9 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ -#define CONFIG_FACTORYSET - /* Watchdog */ #define WATCHDOG_TRIGGER_GPIO 14 -#ifndef CONFIG_SPL_BUILD - /* Use common default */ /* Default env settings */ @@ -61,10 +57,4 @@ "bootm ${kloadaddr}\0" \ "" -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif - -#endif /* CONFIG_SPL_BUILD */ - #endif /* ! __CONFIG_RUT_H */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index d0f70b04e7..83c3167f38 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -10,22 +10,15 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) /* TIMER1,initialized by ddr initialize code */ #define CONFIG_SYS_TIMER_BASE 0x10350020 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SYS_SDRAM_BASE 0x60000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) /* rockchip ohci host driver */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif -#ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "fdt_addr_r=0x61f00000\0" \ @@ -38,4 +31,5 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ BOOTENV + #endif diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index 882d19afbf..43593572d9 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -18,7 +18,6 @@ /*----------------------------------------------------------------------- * System memory Configuration */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MEM_SIZE 0x40000000 #define CONFIG_SYS_SDRAM_BASE 0x71000000 @@ -77,16 +76,6 @@ */ /* board_init_f->init_sequence, call arch_cpu_init */ -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 1024 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /*----------------------------------------------------------------------- * serial console configuration */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 3b4347dd00..712a47a495 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -10,11 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* which is in a S5P Family */ -#define CONFIG_S5PC110 1 /* which is in a S5PC110 */ - #include <linux/sizes.h> #include <asm/arch/cpu.h> /* get chip and board defs */ @@ -26,9 +21,6 @@ /* MMC */ #define SDHCI_MAX_HOSTS 4 -/* PWM */ -#define CONFIG_PWM 1 - /* USB Composite download gadget - g_dnl */ #define DFU_DEFAULT_POLL_TIMEOUT 300 @@ -121,8 +113,6 @@ "opts=always_resume=1\0" \ "dfu_alt_info=" CONFIG_DFU_ALT "\0" -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ - /* Goni has 3 banks of DRAM, but swap the bank */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ #define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */ @@ -136,12 +126,6 @@ /* FLASH and environment organization */ #define CONFIG_MMC_DEFAULT_DEV 0 -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND 1 #define CONFIG_SYS_ONENAND_BASE 0xB0000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) - -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - #endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index ae56c66e15..137537d65f 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -11,8 +11,6 @@ #include <configs/exynos4-common.h> -#define CONFIG_TIZEN /* TIZEN lib */ - /* Keep L2 Cache Disabled */ /* Universal has 2 banks of DRAM */ @@ -21,9 +19,6 @@ #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ #define NORMAL_MTDPARTS_DEFAULT CONFIG_MTDPARTS_DEFAULT @@ -80,7 +75,6 @@ "verify=n\0" \ "rootfstype=ext4\0" \ "console=console=ttySAC1,115200n8\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "mbrparts=" MBRPARTS_DEFAULT \ "meminfo=crashkernel=32M@0x50000000\0" \ "nfsroot=/nfsroot/arm\0" \ @@ -93,12 +87,8 @@ "mmcrootpart=3\0" \ "opts=always_resume=1" -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND #define CONFIG_SYS_ONENAND_BASE 0x0C000000 -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - #ifndef __ASSEMBLY__ void universal_spi_scl(int bit); void universal_spi_sda(int bit); diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index eb00e2b004..4b0f20e89b 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -16,7 +16,6 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index 2708711a4e..afb1e3d0f1 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -20,12 +20,4 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 + CONFIG_SYS_MALLOC_F_LEN - \ - GENERATED_GBL_DATA_SIZE) -#endif - #endif diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index c965fcb4e8..b9b56d9f1a 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -26,10 +26,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 + CONFIG_SYS_MALLOC_F_LEN - \ - GENERATED_GBL_DATA_SIZE) - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index b9144584e3..0eecb56150 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -14,24 +14,8 @@ #undef CONFIG_SYS_AT91_MAIN_CLOCK #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index e611e7b510..178a6ad4ee 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -19,24 +19,8 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index c3a5c2ae32..b18377be66 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -18,13 +18,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - #ifdef CONFIG_SD_BOOT /* u-boot env in sd/mmc card */ #define FAT_ENV_INTERFACE "mmc" @@ -34,16 +27,7 @@ #endif /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h index 1ffe35bd87..3b91e83683 100644 --- a/include/configs/sama5d2_ptc_ek.h +++ b/include/configs/sama5d2_ptc_ek.h @@ -19,9 +19,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - /* NAND Flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index cab6ae5069..bbd72979b5 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -11,24 +11,8 @@ #include "at91-sama5_common.h" -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 68bbe8f29c..fad65cb112 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -27,13 +27,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x318000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -44,42 +37,12 @@ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x18000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* size of u-boot.bin to load */ #define CONFIG_SYS_MONITOR_LEN (2 * SZ_512K) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - /* Falcon boot support on raw MMC */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x100 /* 128 KiB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) /* U-Boot proper stored by default at 0x200 (256 KiB) */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x22000000 - -/* Falcon boot support on FAT on MMC */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" - -/* Falcon boot support on raw NAND */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x1a0000 #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 3be2c83fce..7bc3f91e77 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -38,13 +38,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x318000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* SerialFlash */ /* NAND flash */ @@ -57,27 +50,8 @@ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x18000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index e0e0bc6beb..d5cd45ca5c 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -15,13 +15,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -33,16 +26,7 @@ #endif /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x18000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 2549d4c1a1..411ed29ab3 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -15,13 +15,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -33,16 +26,7 @@ #endif /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x18000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index bca7166cb9..3f905bf2d7 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -11,17 +11,8 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ -#define CONFIG_SYS_BOOTM_LEN SZ_32M /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 + CONFIG_SYS_MALLOC_F_LEN - \ - GENERATED_GBL_DATA_SIZE) -#endif - #endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 7b6db46ee1..5168e2fa35 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -6,14 +6,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifndef CONFIG_SPL_BUILD #define CONFIG_IO_TRACE -#endif #define CONFIG_MALLOC_F_ADDR 0x0010000 -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - /* GUIDs for capsule updatable firmware images */ #define SANDBOX_UBOOT_IMAGE_GUID \ EFI_GUID(0x09d7cf52, 0x0720, 0x4710, 0x91, 0xd1, \ diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h index 835f05d63e..af5fe27e68 100644 --- a/include/configs/sdm845.h +++ b/include/configs/sdm845.h @@ -22,10 +22,5 @@ "bootcmd=source $prevbl_initrd_start_addr:bootscript\0" /* Size of malloc() pool */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 64 #endif diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 58345e4e1b..19701ccce2 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -27,10 +27,4 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -/* - * Support large disk for SATA and USB - */ -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 - #endif /* _CONFIG_SHEEVAPLUG_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 08c4d52d65..d2d4296eed 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -17,24 +17,13 @@ /* commands to include */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_ROOTPATH "/opt/eldk" -#endif - -#define CONFIG_SYS_AUTOLOAD "yes" /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 32 - /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 1024 - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* * memtest works on 8 MB in DRAM after skipping 32MB from @@ -45,11 +34,8 @@ #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ #define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) /* Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_SERIAL @@ -61,13 +47,6 @@ /* I2C Configuration */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ @@ -92,24 +71,18 @@ * header. That is 0x800FFFC0--0x80100000 should not be used for any * other needs. */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#ifndef CONFIG_SPL_BUILD - /* USB DRACO ID as default */ #define CONFIG_USBD_HS /* USB Device Firmware Update support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 -#endif /* CONFIG_SPL_BUILD */ - /* * Default to using SPI for environment, etc. We have multiple copies * of SPL as the ROM will check these locations. @@ -237,7 +210,7 @@ "nand_active_ubi_vol=rootfs_a\0" \ "nand_active_ubi_vol_A=rootfs_a\0" \ "nand_active_ubi_vol_B=rootfs_b\0" \ - "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_root_fs_type=ubifs rootwait\0" \ "nand_src_addr=0x280000\0" \ "nand_src_addr_A=0x280000\0" \ "nand_src_addr_B=0x780000\0" \ @@ -314,7 +287,7 @@ "nand_active_ubi_vol=rootfs_a\0" \ "rootfs_name=rootfs\0" \ "kernel_name=uImage\0"\ - "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_root_fs_type=ubifs rootwait\0" \ "nand_args=run bootargs_defaults;" \ "mtdparts default;" \ "setenv ${partitionset_active} true;" \ diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 96e2eb6798..2e5592cf94 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -11,24 +11,7 @@ #include <linux/sizes.h> -#ifdef CONFIG_SPL - -#define CONFIG_SPL_MAX_SIZE 0x00100000 -#define CONFIG_SPL_BSS_START_ADDR 0x85000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 - -#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ - GENERATED_GBL_DATA_SIZE) - -#endif - #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 @@ -39,7 +22,6 @@ /* Environment options */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(SF, sf, 0) \ @@ -76,6 +58,5 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTENV \ BOOTENV_SF -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index fa734a66be..9923f3d9c3 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -11,30 +11,12 @@ #include <linux/sizes.h> -#ifdef CONFIG_SPL - -#define CONFIG_SPL_MAX_SIZE 0x00100000 -#define CONFIG_SPL_BSS_START_ADDR 0x85000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 - -#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ - GENERATED_GBL_DATA_SIZE) - -#endif - #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 /* Environment options */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(NVME, nvme, 0) \ func(USB, usb, 0) \ @@ -68,7 +50,6 @@ "partitions=" PARTS_DEFAULT "\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ #define CONFIG_SYS_EEPROM_BUS_NUM 0 diff --git a/include/configs/silk.h b/include/configs/silk.h index 574ba228d8..58613effaf 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -12,10 +12,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -39,7 +38,5 @@ "bootm_size=0x10000000\0" /* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 #endif /* __SILK_H */ diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 1cc2992c80..7159fc35d5 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -8,9 +8,6 @@ #include <linux/sizes.h> -/* Start just below the second bank so we don't clobber it during reloc */ -#define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_SIZE SZ_8M diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index e4e15f92d1..1a3ac817fb 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -41,12 +41,6 @@ /* misc settings */ -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 32 - -/* setting board specific options */ -#define CONFIG_SYS_AUTOLOAD "yes" - /* * SDRAM: 1 bank, 64 MB, base address 0x20000000 * Already initialized before u-boot gets started. @@ -72,31 +66,14 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -#if !defined(CONFIG_SPL_BUILD) -/* USB configuration */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - /* USB DFU support */ #define CONFIG_USB_GADGET_AT91 /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 -#endif /* General Boot Parameter */ -#define CONFIG_SYS_CBSIZE 512 - -/* - * The NAND Flash partitions: - */ -#define CONFIG_ENV_RANGE (SZ_512K) /* * Predefined environment variables. @@ -106,32 +83,18 @@ \ "basicargs=console=ttyS0,115200\0" \ \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x301000 -#else /* * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, * leaving the correct space for initial global data structure above that * address while providing maximum stack area below. */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) -#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SZ_4K) - -#define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SPL_BSS_MAX_SIZE (SZ_16K) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) -#define CONFIG_SPL_NAND_RAW_ONLY -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE @@ -150,7 +113,4 @@ #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) #define CONFIG_SYS_AT91_PLLB 0x10483f0e -#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO - #endif /* __CONFIG_H */ diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 1ea3b650cd..c6d2b23197 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -12,7 +12,4 @@ #include <configs/exynos5-dt-common.h> #include <configs/exynos5-common.h> -#undef CONFIG_EXYNOS_FB -#undef CONFIG_EXYNOS_DP - #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index f26995d5c1..12c2e1f615 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -12,16 +12,9 @@ #include <configs/exynos5-dt-common.h> #include <configs/exynos5-common.h> -#undef CONFIG_EXYNOS_FB -#undef CONFIG_EXYNOS_DP - #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) - -/* USB */ -#define CONFIG_USB_XHCI_EXYNOS /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 8eea45450b..1395b8dfe3 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -11,14 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* which is in a S5P Family */ -#define CONFIG_S5PC100 1 /* which is in a S5PC100 */ - #include <asm/arch/cpu.h> /* get chip and board defs */ /* input clock of PLL: SMDKC100 has 12MHz input clock */ @@ -32,9 +24,6 @@ * select serial console configuration */ -/* PWM */ -#define CONFIG_PWM 1 - #define COMMON_BOOT "console=ttySAC0,115200n8" \ " mem=128M " \ " " CONFIG_MTDPARTS_DEFAULT @@ -77,7 +66,6 @@ " console=ttySAC0,115200n8 mem=128M" \ " initrd=0x33000000,8M ramdisk=8192\0" \ "rootfstype=cramfs\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "meminfo=mem=128M\0" \ "nfsroot=/nfsroot/arm\0" \ "bootblock=5\0" \ @@ -87,7 +75,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ @@ -99,26 +86,12 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ -#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000) -#define CONFIG_ENABLE_MMU -#endif - -#ifdef CONFIG_ENABLE_MMU -#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 -#else -#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE -#endif - /*----------------------------------------------------------------------- * Boot configuration */ -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND 1 #define CONFIG_SYS_ONENAND_BASE 0xE7100000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) - /* * Ethernet Contoller driver */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 9ff05fcca7..0b1f0c5f54 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -10,11 +10,7 @@ #include "exynos4-common.h" -#undef CONFIG_USB_GADGET_DWC2_OTG_PHY - /* High Level Configuration Options */ -#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ - #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* Handling Sleep Mode*/ @@ -44,10 +40,6 @@ #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_SYS_INIT_SP_ADDR 0x02040000 - /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_ENV_SROM_BANK 1 diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index a7f7756604..681c831747 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -42,9 +42,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #endif diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index f7ee9dbac3..7adb349f9a 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -23,8 +23,8 @@ /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* Mem test settings */ @@ -37,15 +37,6 @@ #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - /* GPIOs and IO expander */ #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 0e3567f535..59bba7d143 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -23,8 +23,8 @@ /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* Mem test settings */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index ca3da9547c..0187fca5f0 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -16,7 +16,6 @@ */ #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 #define V_NS16550_CLK 48000000 #define V_OSCK 26000000 @@ -34,8 +33,6 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) /* * I2C @@ -51,18 +48,6 @@ * SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024) -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024) -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SYS_CBSIZE 512 - /* * Serial */ diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index c20d54a3c5..f712928d3c 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -32,7 +32,6 @@ */ /* SPL memory allocation configuration, this is for FAT implementation */ -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h index 88fd8ae44c..261ae56c1d 100644 --- a/include/configs/socfpga_arria5_secu1.h +++ b/include/configs/socfpga_arria5_secu1.h @@ -9,7 +9,6 @@ #include <asm/arch/base_addr_ac5.h> #include <linux/stringify.h> -#define CONFIG_HUSH_INIT_VAR /* Eternal oscillator */ #define CONFIG_SYS_TIMER_RATE 40000000 @@ -24,8 +23,6 @@ */ #define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - /* Environment settings */ /* @@ -67,8 +64,6 @@ "fdt_addr=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ "load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp\0" \ "loadaddr=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize}\0" \ "userload=ubi part nand.ubi &&" \ "ubi check rootfs$bootnum &&" \ diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h index 891b762946..75d2081fac 100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@ -7,8 +7,6 @@ #include <asm/arch/base_addr_a10.h> -#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) - /* * U-Boot general configurations */ @@ -35,9 +33,6 @@ /* reload value when timer count to zero */ #define TIMER_LOAD_VAL 0xFFFFFFFF -/* SPL memory allocation configuration, this is for FAT implementation */ -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 5ecd1e6399..4a7da76e51 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -14,18 +14,11 @@ #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE -#define CONFIG_SPL_PAD_TO 0x10000 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 -#define CONFIG_SPL_PAD_TO 0x40000 /* SPL memory allocation configuration, this is for FAT implementation */ -#ifndef CONFIG_SYS_SPL_MALLOC_SIZE -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 -#endif #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ CONFIG_SYS_SPL_MALLOC_SIZE) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE) #endif /* @@ -37,10 +30,6 @@ #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE))) -#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR -#else -#define CONFIG_SPL_STACK \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) #endif /* @@ -48,22 +37,13 @@ * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage * in U-Boot pre-reloc is higher than in SPL. */ -#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR -#else -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK -#endif #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* * U-Boot general configurations */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ /* * Cache @@ -72,20 +52,6 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* - * Ethernet on SoC (EMAC) - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_DW_ALTDESCRIPTOR -#endif - -/* - * FPGA Driver - */ -#ifdef CONFIG_CMD_FPGA -#define CONFIG_FPGA_COUNT 1 -#endif - -/* * L4 OSC1 Timer 0 */ #ifndef CONFIG_TIMER @@ -100,7 +66,6 @@ /* * L4 Watchdog */ -#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #define CONFIG_DW_WDT_CLOCK_KHZ 25000 /* @@ -162,16 +127,6 @@ * 0xFFEz_zzzz ...... Malloc area (grows up to top) * 0xFFE3_FFFF ...... End of SRAM (top) */ -#ifndef CONFIG_SPL_TEXT_BASE -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE -#endif - -/* SPL SDMMC boot support */ -#ifdef CONFIG_SPL_MMC -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif -#endif /* SPL QSPI boot support */ diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h index 468a35d4ff..ad27179120 100644 --- a/include/configs/socfpga_is1.h +++ b/include/configs/socfpga_is1.h @@ -16,9 +16,4 @@ /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> -/* - * Bootcounter - */ -#define CONFIG_SYS_BOOTCOUNT_BE - #endif /* __CONFIG_SOCFPGA_IS1_H__ */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 3447b8f17c..06198ddd82 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -20,50 +20,20 @@ /* * U-Boot console configurations */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) /* * U-Boot run time memory configurations */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ - + CONFIG_SYS_INIT_RAM_SIZE \ - - SOC64_HANDOFF_SIZE) -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \ - + 0x100000) -#endif -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) /* * U-Boot environment configurations */ /* - * QSPI support - */ - #ifdef CONFIG_CADENCE_QSPI -/* Enable it if you want to use dual-stacked mode */ -/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ - -/* Flash device info */ - -#ifndef CONFIG_SPL_BUILD -#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" -#endif /* CONFIG_SPL_BUILD */ - -#endif /* CONFIG_CADENCE_QSPI */ - -/* * Environment variable */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -118,15 +88,9 @@ * Flash configurations */ -/* Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_DW_ALTDESCRIPTOR -#endif /* CONFIG_CMD_NET */ - /* * L4 Watchdog */ -#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); @@ -157,21 +121,5 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) * */ -#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex" -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \ - - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ - - CONFIG_SYS_SPL_MALLOC_SIZE) - -/* SPL SDMMC boot support */ -#ifdef CONFIG_SPL_LOAD_FIT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" -#else -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */ diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index 62c1bc7408..432144cb40 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -18,11 +18,6 @@ /* Enable SPI NOR flash reset, needed for SPI booting */ #define CONFIG_SPI_N25Q256A_RESET -/* - * Bootcounter - */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* Environment setting for SPI flash */ /* The rest of the configuration is shared */ diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index c333c931ab..70d9f3607a 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -11,7 +11,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */ /* Booting Linux */ -#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MiB */ /* Extra Environment */ #define CONFIG_HOSTNAME "socfpga_vining_fpga" diff --git a/include/configs/socrates.h b/include/configs/socrates.h index daba8278c6..5dc8d85598 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -22,7 +22,6 @@ /* * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_ENABLE_36BIT_PHYS 1 /* * sysclk for MPC85xx @@ -103,8 +102,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ @@ -120,15 +118,11 @@ #define CONFIG_SYS_LIME_BASE 0xc8000000 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_SPD_BUS_NUM 0 - /* * General PCI * Memory space is mapped 1-1. */ -/* PCI is clocked by the external source at 33 MHz */ -#define CONFIG_PCI_CLK_FREQ 33000000 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ @@ -228,11 +222,4 @@ /* pass open firmware flat tree */ -/* USB support */ -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_PCI_OHCI 1 -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index d4761296c7..eeee587baf 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -16,7 +16,6 @@ /* SPL options */ #include "imx6_spl.h" -#define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #ifdef CONFIG_FSL_USDHC @@ -62,19 +61,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #ifdef CONFIG_CMD_NET diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index 96e759d99c..71b25c23b1 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -13,8 +13,6 @@ * low-level initialization and rely on configuration provided by the Samsung * bootloader. New images are loaded at the same address for compatibility. */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* FIXME: This should be loaded from device tree... */ #define CONFIG_SYS_L2_PL310 diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 3e6feae1fa..b1a011bacb 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -24,8 +24,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ SZ_256M -#define CONFIG_SYS_BOOTM_LEN SZ_16M - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ @@ -42,17 +40,7 @@ /* Extra Commands */ -#define CONFIG_SYS_GBL_DATA_SIZE 1024 /* Global data structures */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_LEN - \ - CONFIG_SYS_GBL_DATA_SIZE) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - /* USB Configs */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 /* NET Configs */ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 21bab5aafd..18c9e5bfb6 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -9,8 +9,6 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 - /* * Configuration of the external SDRAM memory */ @@ -19,8 +17,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index 4c421b9596..6849477bea 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -14,8 +14,6 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 - /* * Configuration of the external SDRAM memory */ @@ -24,8 +22,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_SYS_CBSIZE 1024 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index e91f8da280..2d8b2d27c9 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -14,8 +14,6 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 - /* * Configuration of the external SDRAM memory */ @@ -24,8 +22,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_SYS_CBSIZE 1024 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index cc3d4b4449..df05ee4892 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M #define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x20050000 /* * Configuration of the external SDRAM memory @@ -21,13 +20,8 @@ #define CONFIG_SYS_MAX_FLASH_SECT 8 -#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8) -#define CONFIG_DW_ALTDESCRIPTOR - #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_SYS_CBSIZE 1024 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) @@ -41,21 +35,10 @@ "ramdisk_addr_r=0xC0438000\0" \ BOOTENV -/* For SPL */ -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_SPL_LEN 0x00008000 #define CONFIG_SYS_UBOOT_START 0x080083FD #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_SPL_LEN) -#define CONFIG_SPL_PAD_TO 0x8000 - -/* DT blob (fdt) address */ -#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ - 0x1C0000) -#endif -/* For SPL ends */ + CONFIG_SPL_PAD_TO) /* For splashcreen */ diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index c43b0d8285..f959fcf26f 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -14,12 +14,9 @@ #define CONFIG_SYS_BOOTMAPSZ SZ_16M #define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_SYS_MAXARGS 16 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index d838449452..c8688e9ca7 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -14,12 +14,9 @@ #define CONFIG_SYS_BOOTMAPSZ SZ_16M #define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_SYS_MAXARGS 16 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h index db17939a8c..f7fa8c51d8 100644 --- a/include/configs/stm32h750-art-pi.h +++ b/include/configs/stm32h750-art-pi.h @@ -14,12 +14,9 @@ #define CONFIG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M) #define CONFIG_SYS_FLASH_BASE 0x90000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_SYS_MAXARGS 16 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h new file mode 100644 index 0000000000..3ca65ea2a3 --- /dev/null +++ b/include/configs/stm32mp13_common.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * Configuration settings for the STM32MP13x CPU + */ + +#ifndef __CONFIG_STM32MP13_COMMMON_H +#define __CONFIG_STM32MP13_COMMMON_H +#include <linux/sizes.h> +#include <asm/arch/stm32.h> + +/* + * Configuration of the external SRAM memory used by U-Boot + */ +#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE + +/* + * For booting Linux, use the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ SZ_256M + +/* Extend size of kernel image for uncompression */ + +/*MMC SD*/ +#define CONFIG_SYS_MMC_MAX_DEVICE 2 + +/* NAND support */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/*****************************************************************************/ +#ifdef CONFIG_DISTRO_DEFAULTS +/*****************************************************************************/ + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0) +#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1) +#else +#define BOOT_TARGET_MMC0(func) +#define BOOT_TARGET_MMC1(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC1(func) \ + BOOT_TARGET_MMC0(func) + +/* + * default bootcmd for stm32mp13: + * for mmc boot (eMMC, SD card), distro boot on the same mmc device + */ +#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ + "echo \"Boot over ${boot_device}${boot_instance}!\";" \ + "run env_check;" \ + "if test ${boot_device} = mmc;" \ + "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ + "run distro_bootcmd;" \ + "fi;\0" + +#define STM32MP_EXTRA \ + "env_check=if env info -p -d -q; then env save; fi\0" \ + "boot_net_usb_start=true\0" + +#ifndef STM32MP_BOARD_EXTRA_ENV +#define STM32MP_BOARD_EXTRA_ENV +#endif + +#include <config_distro_bootcmd.h> + +/* + * memory layout for 32M uncompressed/compressed kernel, + * 1M fdt, 1M script, 1M pxe and 1M for overlay + * and the ramdisk at the end. + */ +#define __KERNEL_ADDR_R __stringify(0xc2000000) +#define __FDT_ADDR_R __stringify(0xc4000000) +#define __SCRIPT_ADDR_R __stringify(0xc4100000) +#define __PXEFILE_ADDR_R __stringify(0xc4200000) +#define __FDTOVERLAY_ADDR_R __stringify(0xc4300000) +#define __RAMDISK_ADDR_R __stringify(0xc4400000) + +#define STM32MP_MEM_LAYOUT \ + "kernel_addr_r=" __KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" __FDT_ADDR_R "\0" \ + "scriptaddr=" __SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \ + "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \ + "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + STM32MP_MEM_LAYOUT \ + STM32MP_BOOTCMD \ + BOOTENV \ + STM32MP_EXTRA \ + STM32MP_BOARD_EXTRA_ENV + +#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ + +#endif /* __CONFIG_STM32MP13_COMMMON_H */ diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h new file mode 100644 index 0000000000..ec64b12f7a --- /dev/null +++ b/include/configs/stm32mp13_st_common.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * Configuration settings for the STMicroelectronics STM32MP13x boards + */ + +#ifndef __CONFIG_STM32MP13_ST_COMMON_H__ +#define __CONFIG_STM32MP13_ST_COMMON_H__ + +#define STM32MP_BOARD_EXTRA_ENV \ + "usb_pgood_delay=1000\0" \ + "console=ttySTM0\0" + +#include <configs/stm32mp13_common.h> + +#endif diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 6b40cdb017..c5412ffeb3 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -14,12 +14,6 @@ * Configuration of the external SRAM memory used by U-Boot */ #define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* - * Console I/O buffer size - */ -#define CONFIG_SYS_CBSIZE SZ_1K /* * For booting Linux, use the first 256 MB of memory, since this is @@ -28,20 +22,7 @@ #define CONFIG_SYS_BOOTMAPSZ SZ_256M /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN SZ_32M - -/* SPL support */ -#ifdef CONFIG_SPL -/* SPL use DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0xC0300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x01D00000 - -/* Restrict SPL to fit within SYSRAM */ -#define STM32_SYSRAM_END (STM32_SYSRAM_BASE + STM32_SYSRAM_SIZE) -#define CONFIG_SPL_MAX_FOOTPRINT (STM32_SYSRAM_END - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_STACK (STM32_SYSRAM_BASE + \ - STM32_SYSRAM_SIZE) -#endif /* #ifdef CONFIG_SPL */ + /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 3 @@ -51,7 +32,6 @@ /* Ethernet need */ #ifdef CONFIG_DWC_ETH_QOS #define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_SYS_AUTOLOAD "no" #endif /*****************************************************************************/ @@ -77,7 +57,7 @@ #endif #ifdef CONFIG_CMD_UBIFS -#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0) +#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot) #else #define BOOT_TARGET_UBIFS(func) #endif @@ -97,7 +77,7 @@ BOOT_TARGET_PXE(func) /* - * default bootcmd for stm32mp1: + * default bootcmd for stm32mp15: * for serial/usb: execute the stm32prog command * for mmc boot (eMMC, SD card), distro boot on the same mmc device * for nand or spi-nand boot, distro boot with ubifs on UBI partition diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index bb95480eeb..910d7ef107 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -33,6 +33,4 @@ #include <configs/stm32mp15_common.h> -#define CONFIG_SPL_TARGET "u-boot.itb" - #endif diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 3c0ffb8f56..37b216e6e9 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -2,7 +2,7 @@ /* * Copyright (C) 2021, STMicroelectronics - All Rights Reserved * - * Configuration settings for the STMicroelectonics STM32MP15x boards + * Configuration settings for the STMicroelectronics STM32MP15x boards */ #ifndef __CONFIG_STM32MP15_ST_COMMON_H__ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index 72f07e1c1c..d8a334868f 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -41,17 +41,8 @@ #define CONFIG_SYS_SBFHDR_SIZE 0x7 /* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK #define CONFIG_PRAM 2048 /* 2048 KB */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_MBAR 0xFC000000 @@ -62,9 +53,8 @@ /* End of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ +#define CONFIG_SYS_INIT_SP_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) /* @@ -81,7 +71,6 @@ #define CONFIG_SERIAL_BOOT #endif -#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) @@ -117,12 +106,4 @@ #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 12) -#ifdef CONFIG_MCFFEC -#define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -#ifndef CONFIG_SYS_DISCOVER_PHY -#define FECDUPLEX FULL -#define FECSPEED _100BASET -#endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif #endif /* __STMARK2_CONFIG_H */ diff --git a/include/configs/stout.h b/include/configs/stout.h index bcc6fcd36b..f49e88cb17 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -13,10 +13,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -43,7 +42,5 @@ "bootm_size=0x10000000\0" /* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 #endif /* __STOUT_H */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 137672909b..567aa1ffe4 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -14,20 +14,11 @@ #define PHYS_SDRAM_1_SIZE 0x00198000 /* user interface */ -#define CONFIG_SYS_CBSIZE 1024 /* MISC */ #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* U-Boot Load Address */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* GMAC related configs */ - -#define CONFIG_DW_ALTDESCRIPTOR /* Misc configuration */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 068340aa96..0f0ef4f64b 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -15,10 +15,6 @@ #include <asm/arch/cpu.h> #include <linux/stringify.h> -#ifdef CONFIG_ARM64 -#define CONFIG_SYS_BOOTM_LEN (32 << 20) -#endif - /* Serial & console */ #define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ @@ -49,20 +45,15 @@ #ifdef CONFIG_MACH_SUN9I #define SDRAM_OFFSET(x) 0x2##x #define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SPL_BSS_START_ADDR 0x2ff80000 #elif defined(CONFIG_MACH_SUNIV) #define SDRAM_OFFSET(x) 0x8##x #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SPL_BSS_START_ADDR 0x81f80000 #else #define SDRAM_OFFSET(x) 0x4##x #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* V3s do not have enough memory to place code at 0x4a000000 */ -#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 #endif -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ - /* * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is * slightly bigger. Note that it is possible to map the first 32 KiB of the @@ -77,18 +68,9 @@ /* FIXME: this may be larger on some SoCs */ #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ -#ifdef CONFIG_AHCI -#define CONFIG_SYS_64BIT_LBA -#endif - #ifdef CONFIG_NAND_SUNXI #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 #define CONFIG_SYS_MAX_NAND_DEVICE 8 @@ -102,8 +84,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ /* standalone support */ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR @@ -117,7 +97,6 @@ * autoconf.mk. */ #if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ #ifdef CONFIG_ARM64 /* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */ #define LOW_LEVEL_SRAM_STACK 0x00054000 @@ -126,33 +105,17 @@ #endif /* !CONFIG_ARM64 */ #elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000 #ifdef CONFIG_MACH_SUN50I_H616 -#define CONFIG_SPL_MAX_SIZE 0xbfa0 /* 48 KiB */ #define LOW_LEVEL_SRAM_STACK 0x58000 #else -#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ /* end of SRAM A2 on H6 for now */ #define LOW_LEVEL_SRAM_STACK 0x00118000 #endif #else -#define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */ #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ #endif -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -#ifndef CONFIG_MACH_SUN50I_H616 -#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ -#endif - /* Ethernet support */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - -#ifndef CONFIG_SPL_BUILD - #ifdef CONFIG_ARM64 /* * Boards seem to come with at least 512MB of DRAM. @@ -345,20 +308,6 @@ "stderr=serial\0" #endif -#ifdef CONFIG_MTDIDS_DEFAULT -#define SUNXI_MTDIDS_DEFAULT \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" -#else -#define SUNXI_MTDIDS_DEFAULT -#endif - -#ifdef CONFIG_MTDPARTS_DEFAULT -#define SUNXI_MTDPARTS_DEFAULT \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define SUNXI_MTDPARTS_DEFAULT -#endif - #define PARTS_DEFAULT \ "name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \ "name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \ @@ -390,16 +339,10 @@ DFU_ALT_INFO_RAM \ "fdtfile=" FDTFILE "\0" \ "console=ttyS0,115200\0" \ - SUNXI_MTDIDS_DEFAULT \ - SUNXI_MTDPARTS_DEFAULT \ "uuid_gpt_esp=" UUID_GPT_ESP "\0" \ "uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \ "partitions=" PARTS_DEFAULT "\0" \ BOOTCMD_SUNXI_COMPAT \ BOOTENV -#else /* ifndef CONFIG_SPL_BUILD */ -#define CONFIG_EXTRA_ENV_SETTINGS -#endif - #endif /* _SUNXI_COMMON_CONFIG_H */ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 5686a5b910..63d897d090 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -22,7 +22,6 @@ /* * Boot info */ -#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */ /* * Hardware drivers support @@ -40,10 +39,6 @@ #define CONFIG_SYS_FLASH_BASE (0x08000000) #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 128 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ #define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ @@ -65,7 +60,6 @@ 0xf0, 0xa3, 0x83, 0x87, 0xe6, 0x30) /* Distro boot settings */ -#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_CMD_USB #define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0) #else @@ -97,9 +91,6 @@ BOOT_TARGET_DEVICE_NVME(func) \ #include <config_distro_bootcmd.h> -#else /* CONFIG_SPL_BUILD */ -#define BOOTENV -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_addr_r=0x9fe00000\0" \ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 77d80bfc98..4758e23f55 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -49,8 +49,8 @@ * leaving the correct space for initial global data structure above * that address while providing maximum stack area below. */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -63,16 +63,7 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 #endif -/* USB */ #if defined(CONFIG_BOARD_TAURUS) -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - /* USB DFU support */ #define CONFIG_USB_GADGET_AT91 @@ -84,13 +75,8 @@ /* SPI EEPROM */ #define TAURUS_SPI_MASK (1 << 4) -#if defined(CONFIG_SPL_BUILD) -/* SPL related */ -#endif - /* bootstrap in spi flash , u-boot + env + linux in nandflash */ -#ifndef CONFIG_SPL_BUILD #if defined(CONFIG_BOARD_AXM) #define CONFIG_EXTRA_ENV_SETTINGS \ "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ @@ -139,21 +125,10 @@ "stdout=serial\0" \ "upgrade_available=0\0" #endif -#endif /* #ifndef CONFIG_SPL_BUILD */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (31 * SZ_512) -#define CONFIG_SPL_STACK (ATMEL_BASE_SRAM1 + SZ_16K) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN - -#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_BSS_MAX_SIZE (3 * SZ_512) #define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) -#define CONFIG_SPL_NAND_RAW_ONLY -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE @@ -172,7 +147,4 @@ #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) #define CONFIG_SYS_AT91_PLLB 0x10193F05 -#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO - #endif diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 09766fea27..16bdc39b75 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -16,11 +16,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_32M - /* * UART configuration */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index b7a94812f3..c93df00d58 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -17,38 +17,20 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_BOOTMAPSZ 0x10000000 -/* Serial console */ -#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ - /* Framebuffer */ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP /* PCI */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #endif -/* SATA */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA -#endif - /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #ifdef CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USBD_HS diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 755a41fef7..c8f9d7cb17 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -9,8 +9,6 @@ #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ -#ifndef CONFIG_SPL_BUILD - #if CONFIG_IS_ENABLED(CMD_USB) # define BOOT_TARGET_USB(func) func(USB, usb, 0) #else @@ -26,9 +24,6 @@ func(DHCP, dhcp, na) #endif #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif #ifdef CONFIG_TEGRA_KEYBOARD #define STDIN_KBD_KBC ",tegra-kbc" diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 99b7bd07aa..159ba093f2 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -35,17 +35,6 @@ */ #define CONFIG_SYS_MMC_MAX_DEVICE 4 -/* - * Increasing the size of the IO buffer as default nfsargs size is more - * than 256 and so it is not possible to edit it - */ -#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - #ifdef CONFIG_ARM64 #define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" #else @@ -65,16 +54,8 @@ #ifndef CONFIG_ARM64 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#endif -#ifndef CONFIG_ARM64 /* Defines for SPL */ -#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 #endif #endif /* _TEGRA_COMMON_H_ */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 0973721180..87ec1f5a99 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -54,10 +54,5 @@ "ramdisk_addr_r=0x83100000\0" /* Defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 -#define CONFIG_SPL_STACK 0x800ffffc - -/* For USB EHCI controller */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index df688dabd1..0485fea6cc 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -56,13 +56,5 @@ "ramdisk_addr_r=0x83100000\0" /* Defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 -#define CONFIG_SPL_STACK 0x800ffffc - -/* For USB EHCI controller */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - -/* GPU needs setup */ -#define CONFIG_TEGRA_GPU #endif /* _TEGRA124_COMMON_H_ */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index fac8692728..71867bb6ba 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -55,8 +55,6 @@ "ramdisk_addr_r=0x03100000\0" /* Defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00090000 -#define CONFIG_SPL_STACK 0x000ffffc /* Align LCD to 1MB boundary */ #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE @@ -71,12 +69,4 @@ #define TEGRA_LP0_VEC #endif -/* - * This parameter affects a TXFILLTUNING field that controls how much data is - * sent to the latency fifo before it is sent to the wire. Without this - * parameter, the default (2) causes occasional Data Buffer Errors in OUT - * packets depending on the buffer address and size. - */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - #endif /* _TEGRA20_COMMON_H_ */ diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 3ba12bec0e..7f361d874a 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -46,10 +46,4 @@ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83420000\0" -/* For USB EHCI controller */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - -/* GPU needs setup */ -#define CONFIG_TEGRA_GPU - #endif /* _TEGRA210_COMMON_H_ */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index b878b1a9e6..04fcf11ed8 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -51,10 +51,5 @@ "ramdisk_addr_r=0x83100000\0" /* Defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 -#define CONFIG_SPL_STACK 0x800ffffc - -/* For USB EHCI controller */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #endif /* _TEGRA30_COMMON_H_ */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index fdf048b27b..655fcb0011 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -29,7 +29,6 @@ #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE /* USB/EHCI configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ @@ -40,12 +39,6 @@ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* SATA support */ -#define CONFIG_LBA48 - -/* FPGA programming support */ -#define CONFIG_FPGA_STRATIX_V - /* * Bootcounter */ @@ -73,17 +66,6 @@ /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_SYS_SDRAM_SIZE SZ_2G diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 3b120073fe..696306e465 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -30,13 +30,6 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_FACTORYSET - -/* Define own nand partitions */ -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - -#ifndef CONFIG_SPL_BUILD - /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=thuban\0" \ @@ -48,8 +41,4 @@ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif -#endif /* CONFIG_SPL_BUILD */ #endif /* ! __CONFIG_THUBAN_H */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 3537ba30e1..cf2efdbe23 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -6,16 +6,11 @@ #ifndef __THUNDERX_88XX_H__ #define __THUNDERX_88XX_H__ -#define CONFIG_THUNDERX - -#define CONFIG_SYS_64BIT - #define MEM_BASE 0x00500000 #define CONFIG_SYS_LOWMEM_BASE MEM_BASE /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) /* SMP Spin Table Definitions */ #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) @@ -47,9 +42,6 @@ /* Do not preserve environment */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ #define PLL_REF_CLK 50000000 /* 50 MHz */ #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 95434aa516..97166e010f 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -62,7 +62,6 @@ /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 /** * Physical Memory Map @@ -71,14 +70,11 @@ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) /** * Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x4802E000 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_SERIAL @@ -89,13 +85,6 @@ /* CPU */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 @@ -105,8 +94,6 @@ * header. That is 0x800FFFC0--0x80800000 should not be used for any * other needs. */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* * Since SPL did pll and ddr initialization for us, diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index c2dfdebcd5..1aca83a9bc 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -13,9 +13,7 @@ #include <asm/arch/omap.h> #define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + DEFAULT_LINUX_BOOT_ENV /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ @@ -28,7 +26,6 @@ * Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x4802E000 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* * NS16550 Configuration @@ -65,7 +62,5 @@ /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) #endif diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index f8bd5558e5..5d5df6b101 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -32,8 +32,6 @@ * supports X-MODEM loading via UART, and we leverage this and then use * Y-MODEM to load u-boot.img, when booted over UART. */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 << 20)) /* Enable the watchdog inside of SPL */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 7483bc821d..2d1f0372ae 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -66,14 +66,6 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) -#endif - -/* Timer information. */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - /* If DM_I2C, enable non-DM I2C support */ /* @@ -88,14 +80,7 @@ /* As stated above, the following choices are optional. */ -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 1024 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* * When we have SPI, NOR or NAND flash we expect to be making use of * mtdparts, both for ease of use in U-Boot and for passing information @@ -128,34 +113,11 @@ * of the BSS area. We suggest that the stack be placed at 32MiB after the * start of DRAM to allow room for all of the above (handled in Kconfig). */ -#ifndef CONFIG_SPL_BSS_START_ADDR -#define CONFIG_SPL_BSS_START_ADDR 0x80a00000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#endif -#ifndef CONFIG_SYS_SPL_MALLOC_START -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_8M -#endif -#ifndef CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) -#endif - - -/* FAT sd card locations. */ -#ifndef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif #ifdef CONFIG_SPL_OS_BOOT /* FAT */ -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" /* RAW SD card / eMMC */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x1500 /* address 0x2A0000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x200 /* 256KiB */ #endif /* General parts of the framework, required. */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 57f013cbf8..29a6038f89 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -12,13 +12,10 @@ /* U-Boot Build Configuration */ /* SoC Configuration */ -#define CONFIG_SPL_TARGET "u-boot-spi.gph" /* Memory Configuration */ #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_ISW_ENTRY_ADDR - \ - GENERATED_GBL_DATA_SIZE) #ifdef CONFIG_SYS_MALLOC_F_LEN #define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN @@ -27,22 +24,10 @@ #endif /* SPL SPI Loader Configuration */ -#define CONFIG_SPL_PAD_TO 65536 -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_ISW_ENTRY_ADDR + \ - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) #define KEYSTONE_SPL_STACK_SIZE (8 * 1024) -#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ - CONFIG_SYS_SPL_MALLOC_SIZE + \ - SPL_MALLOC_F_SIZE + \ - KEYSTONE_SPL_STACK_SIZE - 4) /* SRAM scratch space entries */ -#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8 +#define SRAM_SCRATCH_SPACE_ADDR 0xc0c23fc #define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR) #define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) @@ -74,14 +59,6 @@ #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES -/* I2C Configuration */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ - /* EEPROM definitions */ /* NAND Configuration */ @@ -180,7 +157,7 @@ "sf write ${loadaddr} 0 ${filesize}\0" \ "burn_uboot_nand=nand erase 0 0x100000; " \ "nand write ${loadaddr} 0 ${filesize}\0" \ - "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1 " \ + "args_all=setenv bootargs console=ttyS0,115200n8 rootwait " \ KERNEL_MTD_PARTS \ "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ @@ -199,9 +176,7 @@ "args_ramfs=setenv bootargs ${bootargs} " \ "rdinit=/sbin/init rw root=/dev/ram0 " \ "initrd=0x808080000,80M\0" \ - "no_post=1\0" \ - "mtdparts=mtdparts=davinci_nand.0:" \ - "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" + "no_post=1\0" /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 3d7cb175fa..725a5a62f5 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -55,8 +55,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* SPL */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (64 << 20)) #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_BASE 0x30000000 diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index b5ccfdcc6d..3d78972bfe 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -23,17 +23,6 @@ /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE -/* - * For the DDR timing information we can either dynamically determine - * the timings to use or use pre-determined timings (based on using the - * dynamic method. Default to the static timing infomation. - */ -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - #include <configs/ti_armv7_omap.h> /* @@ -47,9 +36,7 @@ #endif /* TWL6030 */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_TWL6030_POWER 1 -#endif /* * Environment setup @@ -113,8 +100,6 @@ * SPL is overlapped with public stack and breaking non HS devices to boot. * So moving TEXT_BASE down to non-HS limit. */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 << 20)) #ifdef CONFIG_SPL_BUILD /* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 714a1c55c7..24bbf9e7c2 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -19,19 +19,6 @@ /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE -/* - * For the DDR timing information we can either dynamically determine - * the timings to use or use pre-determined timings (based on using the - * dynamic method. Default to the static timing infomation. - */ -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - -#define CONFIG_PALMAS_POWER - #include <linux/stringify.h> #include <asm/arch/cpu.h> @@ -305,7 +292,4 @@ */ #endif -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 << 20)) - #endif /* __CONFIG_TI_OMAP5_COMMON_H */ diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index f859656b39..83abaeddf1 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -16,11 +16,6 @@ /* Fixup settings */ -/* SPL settings */ -#undef CONFIG_SPL_MAX_FOOTPRINT -#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - /* Setup proper boot sequences for Miami boards */ #if defined(CONFIG_USB_HOST) diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index 0324b1e1b2..4fb3d731c6 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -10,9 +10,6 @@ #define __TOTAL_COMPUTE_H /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) #define UART0_BASE 0x7ff80000 @@ -46,16 +43,10 @@ * Else boot FIT image. */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - #define CONFIG_SYS_FLASH_BASE 0x0C000000 /* 256 x 256KiB sectors */ #define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT - #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ #define FLASH_MAX_SECTOR_SIZE 0x00040000 diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 21c351a816..f5466fd509 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -9,14 +9,10 @@ #define CONFIG_SYS_MHZ 280 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - #define CONFIG_SYS_SDRAM_BASE 0xa0000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) /* * Serial Port @@ -27,14 +23,6 @@ * Command */ /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - -/* USB, USB storage, USB ethernet */ -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_EHCI_DESC_BIG_ENDIAN /* * Diagnostics diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index e0cd1ec251..a782e3d02b 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -52,9 +52,6 @@ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ - #if defined(CONFIG_TQMA6X_MMC_BOOT) @@ -286,11 +283,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* * All the defines above are for the TQMa6 SoM * diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 90db96599c..999130600c 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -24,9 +24,6 @@ /* LED */ -/* Bootcounter */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* I2C */ #endif /* __CONFIG_TQMA6_WRU4_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index 910fc150b1..53f5a6996b 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -11,10 +11,6 @@ #include <configs/exynos4-common.h> -#define CONFIG_TRATS - -#define CONFIG_TIZEN /* TIZEN lib */ - #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 @@ -25,9 +21,6 @@ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - /* Tizen - partitions definitions */ #define PARTS_CSA "csa-mmc" #define PARTS_BOOT "boot" @@ -130,13 +123,9 @@ "fdtaddr=40800000\0" \ /* Falcon mode definitions */ -#define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 /* GPT */ -/* Security subsystem - enable hw_rand() */ -#define CONFIG_EXYNOS_ACE_SHA - /* Common misc for Samsung */ #define CONFIG_MISC_COMMON @@ -160,8 +149,6 @@ #define LCD_BPP LCD_COLOR16 /* LCD */ -#define CONFIG_FB_ADDR 0x52504000 -#define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #endif /* __CONFIG_H */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 3e121bc690..b7449dab8b 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -12,8 +12,6 @@ #include <configs/exynos4-common.h> -#define CONFIG_TIZEN /* TIZEN lib */ - #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 @@ -24,9 +22,6 @@ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - /* Tizen - partitions definitions */ #define PARTS_CSA "csa-mmc" #define PARTS_BOOT "boot" @@ -121,9 +116,6 @@ /* GPT */ -/* Security subsystem - enable hw_rand() */ -#define CONFIG_EXYNOS_ACE_SHA - /* Common misc for Samsung */ #define CONFIG_MISC_COMMON @@ -147,8 +139,6 @@ #define LCD_BPP LCD_COLOR16 /* LCD */ -#define CONFIG_FB_ADDR 0x52504000 -#define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #endif /* __CONFIG_H */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 6640ee495d..401627a47a 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -8,11 +8,7 @@ #ifndef _CONFIG_TURRIS_MOX_H #define _CONFIG_TURRIS_MOX_H -#define CONFIG_SYS_BOOTM_LEN (64 << 20) #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 32 #define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ @@ -21,8 +17,6 @@ 4000000, 4500000, 5000000, 5500000, \ 6000000 } -#define CONFIG_USB_MAX_CONTROLLER_COUNT 6 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(NVME, nvme, 0) \ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 8119340b11..9013d9a693 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -26,23 +26,6 @@ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC -/* SPL related MMC defines */ -# ifdef CONFIG_SPL_BUILD -# define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -# endif -#endif - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 4bddc0eca3..03e5c04af6 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -14,9 +14,6 @@ #define CONFIG_MXC_UART_BASE UART2_BASE -/* SATA Configs */ -#define CONFIG_LBA48 - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -58,11 +55,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ #endif /* __CONFIG_H * */ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 3a7cb050b1..e30b6cc82d 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -63,11 +63,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* PMIC */ #define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index 14ea40bee3..578873295f 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -16,7 +16,6 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index f813f88cdd..15ae0844c1 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -10,7 +10,6 @@ #ifndef __CONFIG_UNIPHIER_H__ #define __CONFIG_UNIPHIER_H__ -#ifndef CONFIG_SPL_BUILD #include <config_distro_bootcmd.h> #ifdef CONFIG_CMD_MMC @@ -20,7 +19,7 @@ #endif #ifdef CONFIG_CMD_UBIFS -#define BOOT_TARGET_DEVICE_UBIFS(func) func(UBIFS, ubifs, 0) +#define BOOT_TARGET_DEVICE_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot) #else #define BOOT_TARGET_DEVICE_UBIFS(func) #endif @@ -35,16 +34,9 @@ BOOT_TARGET_DEVICE_MMC(func) \ BOOT_TARGET_DEVICE_UBIFS(func) \ BOOT_TARGET_DEVICE_USB(func) -#else -#define BOOTENV -#endif #define CONFIG_SYS_MONITOR_LEN 0x00200000 /* 2MB */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - #if !defined(CONFIG_ARM64) /* Time clock 1MHz */ #define CONFIG_SYS_TIMER_RATE 1000000 @@ -62,8 +54,6 @@ #define CONFIG_GATEWAYIP 192.168.11.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SYS_BOOTM_LEN (32 << 20) - #if defined(CONFIG_ARM64) /* ARM Trusted Firmware */ #define BOOT_IMAGES \ @@ -177,19 +167,9 @@ #define CONFIG_SYS_BOOTMAPSZ 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) - /* only for SPL */ -#define CONFIG_SPL_STACK (0x00100000) /* subtract sizeof(struct image_header) */ #define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40) -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_MAX_FOOTPRINT 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 - -#define CONFIG_SPL_PAD_TO 0x20000 - #endif /* __CONFIG_UNIPHIER_H__ */ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 2b6078a1cc..e0dde1cc83 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -28,8 +28,8 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -43,18 +43,7 @@ #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif - /* bootstrap + u-boot + env + linux in dataflash on CS0 */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ #endif diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 0faa656bc6..2632d56cb1 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -15,7 +15,6 @@ /* U-Boot environment */ /* U-Boot general configurations */ -#define CONFIG_SYS_CBSIZE 512 /* UART */ #define CONFIG_MXC_UART_BASE UART1_BASE @@ -66,9 +65,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #endif /* __CONFIG_H */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 88c3061db6..78a62a8b02 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -32,18 +32,7 @@ #error Unknown DDR size - please add! #endif -#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) -#define VCOREIII_DEFAULT_MTD_ENV \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ - "mtdids="CONFIG_MTDIDS_DEFAULT"\0" -#else -#define VCOREIII_DEFAULT_MTD_ENV /* Go away */ -#endif - -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ - #define CONFIG_EXTRA_ENV_SETTINGS \ - VCOREIII_DEFAULT_MTD_ENV \ "loadaddr=0x81000000\0" \ "spi_image_off=0x00100000\0" \ "console=ttyS0,115200\0" \ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 558b78115d..5b5fce9bda 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -9,24 +9,14 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #define MEM_LAYOUT_ENV_SETTINGS \ @@ -36,15 +26,11 @@ "scriptaddr=0x46000000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -68,10 +54,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #if defined(CONFIG_ENV_IS_IN_MMC) /* Environment in eMMC, before config block at the end of 1st "boot sector" */ @@ -83,22 +65,10 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - /* ENET */ #define CONFIG_FEC_MXC_PHYADDR 7 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* __VERDIN_IMX8MM_H */ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 52fa2be3ab..fca40beba1 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -9,23 +9,16 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SPL_MAX_SIZE (152 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x960000 -#define CONFIG_SPL_BSS_START_ADDR 0x0098fc00 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x184000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PCA9450 @@ -47,15 +40,11 @@ "scriptaddr=0x46000000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif #if defined(CONFIG_TDX_EASY_INSTALLER) # define BOOT_SCRIPT "boot-tezi.scr" @@ -85,12 +74,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ /* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -99,14 +82,4 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #endif /* __VERDIN_IMX8MP_H */ diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 0632b367ca..3705313aec 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -11,14 +11,10 @@ /* Link Definitions */ #ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) #else /* ATF loads u-boot here for BASE_FVP model */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) #endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - /* CS register bases for the original memory map. */ #ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP #define V2M_DRAM_BASE 0x00000000 @@ -263,10 +259,6 @@ EXTRA_ENV_NAMES \ BOOTENV -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - #ifdef CONFIG_TARGET_VEXPRESS64_JUNO #define CONFIG_SYS_FLASH_BASE 0x08000000 /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ @@ -280,13 +272,6 @@ /* Store environment at top of flash */ #endif -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ #define FLASH_MAX_SECTOR_SIZE 0x00040000 diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 599caaca17..ff7307f090 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -139,10 +139,6 @@ /* additions for new relocation code */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET /* Basic environment settings */ #define BOOT_TARGET_DEVICES(func) \ @@ -197,7 +193,4 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \ CONFIG_SYS_FLASH_BASE1 } -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - #endif /* VEXPRESS_COMMON_H */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index ec9049e1b3..32d9df0a00 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -26,7 +26,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 /* I2C Configs */ -#define CONFIG_SYS_SPD_BUS_NUM 0 /* * We do have 128MB of memory on the Vybrid Tower board. Leave the last @@ -130,13 +129,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_RANGE (512 * 1024) -#endif - #endif diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 74eccfa2e6..a157296761 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -27,9 +27,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x4000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) - /* MMC */ #ifdef CONFIG_CMD_MMC diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index e7d4fd16cc..6eb022f26c 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -31,11 +31,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR @@ -46,14 +41,10 @@ /* Network */ #define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) #endif diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 7e3d589e3f..6a7a0832c9 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -17,10 +17,6 @@ /* SPL */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x80010000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_PAD_TO 0 /* Dummy value */ #define CONFIG_SYS_UBOOT_BASE 0 @@ -33,11 +29,6 @@ /* RAM */ -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_CBSIZE 512 - /* Environment settings */ #endif //__VOCORE2_CONFIG_H__ diff --git a/include/configs/vyasa-rk3288.h b/include/configs/vyasa-rk3288.h index a51b169c61..e8c1013a71 100644 --- a/include/configs/vyasa-rk3288.h +++ b/include/configs/vyasa-rk3288.h @@ -22,13 +22,8 @@ #ifndef CONFIG_TPL_BUILD /* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x0ffe5000 /* Falcon Mode - MMC support: args@16MB kernel@17MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8000 /* 16MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif #endif diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index d44b4a0750..899b8ca470 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -14,14 +14,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE -/* SATA Configs */ - -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - /* MMC Configuration */ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -103,11 +95,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ #endif /* __CONFIG_H * */ diff --git a/include/configs/warp.h b/include/configs/warp.h index 8bdda37708..7cb9743fdd 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -29,20 +29,13 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* VDD voltage 1.65 - 1.95 */ #define CONFIG_SYS_SD_VOLTAGE 0x00000080 /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG2 port enabled */ #endif #define CONFIG_USBD_HS diff --git a/include/configs/warp7.h b/include/configs/warp7.h index b3c9f14c8f..c00ca4a111 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -89,11 +89,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #define CONFIG_SYS_FSL_USDHC_NUM 1 diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 3324537597..8d1eee2fca 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -19,16 +19,11 @@ #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ - - GENERATED_GBL_DATA_SIZE) - #define CONFIG_RTC_DS1374 /* * U-Boot General Configurations */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* * NAND chip timings for FIXME: which one? @@ -65,11 +60,9 @@ /* SPL will be executed at offset 0 */ /* SPL will use SRAM as stack */ -#define CONFIG_SPL_STACK 0x0000FFF8 /* Use the framework and generic lib */ /* SPL will use serial */ /* SPL will load U-Boot from NAND offset 0x40000 */ -#define CONFIG_SPL_PAD_TO 0x20000 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE diff --git a/include/configs/x530.h b/include/configs/x530.h index 67ff01db90..cb126837b9 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -47,11 +47,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* NAND */ #include <asm/arch/config.h> @@ -64,20 +59,4 @@ #define CONFIG_UBI_PART user #define CONFIG_UBIFS_VOLUME user -/* SPL */ - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - #endif /* _CONFIG_X530_H */ diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index b45d2bbd62..4109af7d85 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -12,18 +12,6 @@ #define CONFIG_X86_REFCODE_ADDR 0xffea0000 #define CONFIG_X86_REFCODE_RUN_ADDR 0 -#define CONFIG_PCI_MEM_BUS 0xe0000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_PREF_BUS 0xd0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x1000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xefff - #define VIDEO_IO_OFFSET 0 #define CONFIG_X86EMU_RAW_IO diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index a22f97042f..42b2cb2fc8 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -14,14 +14,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - -/* SATA AHCI storage */ -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - -#endif /* Generic TPM interfaced through LPC bus */ #define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 @@ -40,7 +32,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /*----------------------------------------------------------------------- * CPU Features @@ -53,11 +44,6 @@ */ /*----------------------------------------------------------------------- - * PCI configuration - */ -#define CONFIG_PCI_CONFIG_HOST_BRIDGE - -/*----------------------------------------------------------------------- * USB configuration */ diff --git a/include/configs/xea.h b/include/configs/xea.h index 01942eaf2b..19ccf633c4 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -15,17 +15,11 @@ #include <linux/sizes.h> /* SPL */ -#define CONFIG_SPL_STACK 0x20000 - -#define CONFIG_SYS_SPL_ARGS_ADDR 0x44000000 #define CONFIG_SYS_SPI_KERNEL_OFFS SZ_1M #define CONFIG_SYS_SPI_ARGS_OFFS SZ_512K #define CONFIG_SYS_SPI_ARGS_SIZE SZ_32K -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (SZ_512K / 0x200) -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (SZ_32K / 0x200) - /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h index 408c7b5dd6..364dae0cd9 100644 --- a/include/configs/xenguest_arm64.h +++ b/include/configs/xenguest_arm64.h @@ -13,13 +13,6 @@ #undef CONFIG_SYS_SDRAM_BASE -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "loadimage=ext4load pvblock 0 0x90000000 /boot/Image;\0" \ diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index b78c242948..971bd69dec 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -14,8 +14,6 @@ #define GICD_BASE 0xF9000000 #define GICR_BASE 0xF9080000 -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - /* Serial setup */ #define CONFIG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } @@ -27,11 +25,7 @@ /* Miscellaneous configurable options */ -/* Monitor Command Prompt */ /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MAXARGS 64 #if defined(CONFIG_CMD_DFU) #define DFU_DEFAULT_POLL_TIMEOUT 300 @@ -43,8 +37,6 @@ # define PHY_ANEG_TIMEOUT 20000 #endif -#define CONFIG_SYS_BOOTM_LEN (100 * 1024 * 1024) - #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_addr_r=0x40000000\0" \ "fdt_size_r=0x400000\0" \ diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index a94ab1fd20..e1f95de3c3 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -17,7 +17,4 @@ /* Undef unneeded configs */ #undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - #endif /* __CONFIG_VERSAL_MINI_H */ diff --git a/include/configs/xilinx_versal_mini_qspi.h b/include/configs/xilinx_versal_mini_qspi.h index 8572b8b3d2..e2f2df2935 100644 --- a/include/configs/xilinx_versal_mini_qspi.h +++ b/include/configs/xilinx_versal_mini_qspi.h @@ -12,7 +12,4 @@ #include <configs/xilinx_versal_mini.h> -#undef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) - #endif /* __CONFIG_VERSAL_MINI_QSPI_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index f25d796a1e..f72f3e6447 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -14,8 +14,6 @@ #define GICD_BASE 0xF9010000 #define GICC_BASE 0xF9020000 -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - /* Serial setup */ #define CONFIG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } @@ -39,31 +37,23 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_THOR_RESET_OFF -#ifndef CONFIG_SPL_BUILD # define PARTS_DEFAULT \ "partitions=uuid_disk=${uuid_gpt_disk};" \ "name=""boot"",size=16M,uuid=${uuid_gpt_boot};" \ "name=""Linux"",size=-M,uuid=${uuid_gpt_Linux}\0" #endif -#endif #if !defined(PARTS_DEFAULT) # define PARTS_DEFAULT #endif -/* Monitor Command Prompt */ /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MAXARGS 64 /* Ethernet driver */ #if defined(CONFIG_ZYNQ_GEM) # define PHY_ANEG_TIMEOUT 20000 #endif -#define CONFIG_SYS_BOOTM_LEN (100 * 1024 * 1024) - #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_addr_r=0x40000000\0" \ "fdt_size_r=0x400000\0" \ @@ -205,13 +195,6 @@ "dfu_bufsiz=0x1000\0" #endif -#define CONFIG_SPL_STACK 0xfffffffc -#define CONFIG_SPL_MAX_SIZE 0x40000 - -/* Just random location in OCM */ -#define CONFIG_SPL_BSS_START_ADDR 0x0 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - #if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) # define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 # define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 @@ -219,28 +202,8 @@ #endif /* u-boot is like dtb */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000 /* ATF is my kernel image */ -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf-uboot.ub" - -/* MMC support */ -# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */ -# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */ -# if defined(CONFIG_SPL_LOAD_FIT) -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" -# else -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -# endif - -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) -# define CONFIG_SPL_HASH -# define CONFIG_ENV_MAX_ENTRIES 10 -#endif - -#define CONFIG_SYS_SPL_MALLOC_START 0x20000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x1000000 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index baef561c0b..1c0ab25c64 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -16,9 +16,5 @@ /* Undef unneeded configs */ #undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_INIT_SP_ADDR - -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 #endif /* __CONFIG_ZYNQMP_MINI_H */ diff --git a/include/configs/xilinx_zynqmp_mini_emmc.h b/include/configs/xilinx_zynqmp_mini_emmc.h index 57c40d6102..f423ddd08e 100644 --- a/include/configs/xilinx_zynqmp_mini_emmc.h +++ b/include/configs/xilinx_zynqmp_mini_emmc.h @@ -12,6 +12,4 @@ #include <configs/xilinx_zynqmp_mini.h> -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - #endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */ diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h index 782e696168..d2c0e91b32 100644 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ b/include/configs/xilinx_zynqmp_mini_nand.h @@ -14,6 +14,5 @@ #define CONFIG_SYS_SDRAM_SIZE 0x1000000 #define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000) #endif /* __CONFIG_ZYNQMP_MINI_NAND_H */ diff --git a/include/configs/xilinx_zynqmp_mini_qspi.h b/include/configs/xilinx_zynqmp_mini_qspi.h index 3091bae051..5bea1c9908 100644 --- a/include/configs/xilinx_zynqmp_mini_qspi.h +++ b/include/configs/xilinx_zynqmp_mini_qspi.h @@ -12,6 +12,4 @@ #include <configs/xilinx_zynqmp_mini.h> -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) - #endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */ diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index 3ec99e062d..b6bc402a7e 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -15,15 +15,9 @@ /* Boot configuration */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index bd39b328a6..0e43b37364 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -28,18 +28,11 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment is in stored in the eMMC boot partition */ /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_FEC_ENET_DEV 0 #define CONFIG_FEC_MXC_PHYADDR 0x0 diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 92e5b436a3..f1ea476546 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -16,12 +16,6 @@ * differences. */ -/*=====================*/ -/* Board and Processor */ -/*=====================*/ - -#define CONFIG_XTFPGA - /*===================*/ /* RAM Layout */ /*===================*/ @@ -62,9 +56,6 @@ # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ #endif -/* Linux boot param area in RAM (used only when booting linux) */ -#define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) - /* Memory test is destructive so default must not overlap vectors or U-Boot*/ /* Load address for stand-alone applications. @@ -98,10 +89,6 @@ /*==============================*/ /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 1024 - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /*==============================*/ /* U-Boot autoboot configuration */ /*==============================*/ @@ -177,7 +164,6 @@ /* Flash & Environment */ /*=====================*/ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #ifdef CONFIG_XTFPGA_LX60 # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ # define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index bd88b59f24..1fdde90654 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -199,36 +199,18 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ - #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) /* Boot FreeBSD/vxWorks from an ELF image */ #define CONFIG_SYS_MMC_MAX_DEVICE 1 -/* MMC support */ -#ifdef CONFIG_MMC_SDHCI_ZYNQ -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - /* Address in RAM where the parameters must be copied by SPL. */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000 - -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "system.dtb" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" /* Not using MMC raw mode - just for compilation purpose */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* qspi mode is working fine */ #ifdef CONFIG_ZYNQ_QSPI @@ -241,21 +223,13 @@ /* SP location before relocation, must use scratch RAM */ /* 3 * 64kB blocks of OCM - one is on the top because of bootrom */ -#define CONFIG_SPL_MAX_SIZE 0x30000 /* On the top of OCM space */ -#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SPL_STACK_R_ADDR -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000000 /* * SPL stack position - and stack goes down * 0xfffffe00 is used for putting wfi loop. * Set it up as limit for now. */ -#define CONFIG_SPL_STACK 0xfffffe00 - -/* BSS setup */ -#define CONFIG_SPL_BSS_START_ADDR 0x100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 #endif /* __CONFIG_ZYNQ_COMMON_H */ diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index 7eafdfd9a6..cb982c2e74 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -14,17 +14,9 @@ /* Undef unneeded configs */ #undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_CBSIZE 1024 - #undef CONFIG_SYS_INIT_RAM_ADDR #undef CONFIG_SYS_INIT_RAM_SIZE #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#undef CONFIG_SPL_BSS_START_ADDR -#undef CONFIG_SPL_BSS_MAX_SIZE -#define CONFIG_SPL_BSS_START_ADDR 0x20000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x8000 #endif /* __CONFIG_ZYNQ_CSE_H */ diff --git a/include/dm/device.h b/include/dm/device.h index 5bdb10653f..12c6ba37ff 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -11,6 +11,7 @@ #define _DM_DEVICE_H #include <dm/ofnode.h> +#include <dm/tag.h> #include <dm/uclass-id.h> #include <fdtdec.h> #include <linker_lists.h> @@ -547,6 +548,30 @@ void *dev_get_parent_priv(const struct udevice *dev); void *dev_get_uclass_priv(const struct udevice *dev); /** + * dev_get_attach_ptr() - Get the value of an attached pointed tag + * + * The tag is assumed to hold a pointer, if it exists + * + * @dev: Device to look at + * @tag: Tag to access + * @return value of tag, or NULL if there is no tag of this type + */ +void *dev_get_attach_ptr(const struct udevice *dev, enum dm_tag_t tag); + +/** + * dev_get_attach_size() - Get the size of an attached tag + * + * Core tags have an automatic-allocation mechanism where the allocated size is + * defined by the device, parent or uclass. This returns the size associated + * with a particular tag + * + * @dev: Device to look at + * @tag: Tag to access + * @return size of auto-allocated data, 0 if none + */ +int dev_get_attach_size(const struct udevice *dev, enum dm_tag_t tag); + +/** * dev_get_parent() - Get the parent of a device * * @child: Child to check diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 2c4d72d77f..bb60433124 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -1182,6 +1182,33 @@ int ofnode_write_string(ofnode node, const char *propname, const char *value); int ofnode_set_enabled(ofnode node, bool value); /** + * ofnode_get_phy_node() - Get PHY node for a MAC (if not fixed-link) + * + * This function parses PHY handle from the Ethernet controller's ofnode + * (trying all possible PHY handle property names), and returns the PHY ofnode. + * + * Before this is used, ofnode_phy_is_fixed_link() should be checked first, and + * if the result to that is true, this function should not be called. + * + * @eth_node: ofnode belonging to the Ethernet controller + * Return: ofnode of the PHY, if it exists, otherwise an invalid ofnode + */ +ofnode ofnode_get_phy_node(ofnode eth_node); + +/** + * ofnode_read_phy_mode() - Read PHY connection type from a MAC node + * + * This function parses the "phy-mode" / "phy-connection-type" property and + * returns the corresponding PHY interface type. + * + * @mac_node: ofnode containing the property + * Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NA on + * error + */ +phy_interface_t ofnode_read_phy_mode(ofnode mac_node); + +#if CONFIG_IS_ENABLED(DM) +/** * ofnode_conf_read_bool() - Read a boolean value from the U-Boot config * * This reads a property from the /config node of the devicetree. @@ -1218,30 +1245,21 @@ int ofnode_conf_read_int(const char *prop_name, int default_val); */ const char *ofnode_conf_read_str(const char *prop_name); -/** - * ofnode_get_phy_node() - Get PHY node for a MAC (if not fixed-link) - * - * This function parses PHY handle from the Ethernet controller's ofnode - * (trying all possible PHY handle property names), and returns the PHY ofnode. - * - * Before this is used, ofnode_phy_is_fixed_link() should be checked first, and - * if the result to that is true, this function should not be called. - * - * @eth_node: ofnode belonging to the Ethernet controller - * Return: ofnode of the PHY, if it exists, otherwise an invalid ofnode - */ -ofnode ofnode_get_phy_node(ofnode eth_node); +#else /* CONFIG_DM */ +static inline bool ofnode_conf_read_bool(const char *prop_name) +{ + return false; +} -/** - * ofnode_read_phy_mode() - Read PHY connection type from a MAC node - * - * This function parses the "phy-mode" / "phy-connection-type" property and - * returns the corresponding PHY interface type. - * - * @mac_node: ofnode containing the property - * Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NA on - * error - */ -phy_interface_t ofnode_read_phy_mode(ofnode mac_node); +static inline int ofnode_conf_read_int(const char *prop_name, int default_val) +{ + return default_val; +} + +static inline const char *ofnode_conf_read_str(const char *prop_name) +{ + return NULL; +} +#endif /* CONFIG_DM */ #endif diff --git a/include/dm/platform_data/pxa_mmc_gen.h b/include/dm/platform_data/pxa_mmc_gen.h deleted file mode 100644 index d15c1551f4..0000000000 --- a/include/dm/platform_data/pxa_mmc_gen.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2019 Marcel Ziswiler <marcel.ziswiler@toradex.com> - */ - -#ifndef __PXA_MMC_GEN_H -#define __PXA_MMC_GEN_H - -#include <mmc.h> - -/* - * struct pxa_mmc_plat - information about a PXA MMC controller - * - * @base: MMC controller base register address - */ -struct pxa_mmc_plat { - struct mmc_config cfg; - struct mmc mmc; - struct pxa_mmc_regs *base; -}; - -#endif /* __PXA_MMC_GEN_H */ diff --git a/include/dm/platform_data/serial_pxa.h b/include/dm/platform_data/serial_pxa.h deleted file mode 100644 index 0d7dc4c462..0000000000 --- a/include/dm/platform_data/serial_pxa.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com> - */ - -#ifndef __SERIAL_PXA_H -#define __SERIAL_PXA_H - -/* - * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can - * easily handle enabling of clock. - */ -#ifdef CONFIG_CPU_MONAHANS -#define UART_CLK_BASE CKENA_21_BTUART -#define UART_CLK_REG CKENA -#define BTUART_INDEX 0 -#define FFUART_INDEX 1 -#define STUART_INDEX 2 -#elif CONFIG_CPU_PXA25X -#define UART_CLK_BASE BIT(4) /* HWUART */ -#define UART_CLK_REG CKEN -#define HWUART_INDEX 0 -#define STUART_INDEX 1 -#define FFUART_INDEX 2 -#define BTUART_INDEX 3 -#else /* PXA27x */ -#define UART_CLK_BASE CKEN5_STUART -#define UART_CLK_REG CKEN -#define STUART_INDEX 0 -#define FFUART_INDEX 1 -#define BTUART_INDEX 2 -#endif - -/* - * Only PXA250 has HWUART, to avoid poluting the code with more macros, - * artificially introduce this. - */ -#ifndef CONFIG_CPU_PXA25X -#define HWUART_INDEX 0xff -#endif - -/* - * struct pxa_serial_plat - information about a PXA port - * - * @base: Uart port base register address - * @port: Uart port index, for cpu with pinmux for uart / gpio - * baudrtatre: Uart port baudrate - */ -struct pxa_serial_plat { - struct pxa_uart_regs *base; - int port; - int baudrate; -}; - -#endif /* __SERIAL_PXA_H */ diff --git a/include/dm/root.h b/include/dm/root.h index e888fb993c..b2f30a842f 100644 --- a/include/dm/root.h +++ b/include/dm/root.h @@ -9,12 +9,50 @@ #ifndef _DM_ROOT_H_ #define _DM_ROOT_H_ +#include <dm/tag.h> + struct udevice; /* Head of the uclass list if CONFIG_OF_PLATDATA_INST is enabled */ extern struct list_head uclass_head; /** + * struct dm_stats - Information about driver model memory usage + * + * @total_size: All data + * @dev_count: Number of devices + * @dev_size: Size of all devices (just the struct udevice) + * @dev_name_size: Bytes used by device names + * @uc_count: Number of uclasses + * @uc_size: Size of all uclasses (just the struct uclass) + * @tag_count: Number of tags + * @tag_size: Bytes used by all tags + * @uc_attach_count: Number of uclasses with attached data (priv) + * @uc_attach_size: Total size of that attached data + * @attach_count_total: Total number of attached data items for all udevices and + * uclasses + * @attach_size_total: Total number of bytes of attached data + * @attach_count: Number of devices with attached, for each type + * @attach_size: Total number of bytes of attached data, for each type + */ +struct dm_stats { + int total_size; + int dev_count; + int dev_size; + int dev_name_size; + int uc_count; + int uc_size; + int tag_count; + int tag_size; + int uc_attach_count; + int uc_attach_size; + int attach_count_total; + int attach_size_total; + int attach_count[DM_TAG_ATTACH_COUNT]; + int attach_size[DM_TAG_ATTACH_COUNT]; +}; + +/** * dm_root() - Return pointer to the top of the driver tree * * This function returns pointer to the root node of the driver tree, @@ -141,4 +179,11 @@ static inline int dm_remove_devices_flags(uint flags) { return 0; } */ void dm_get_stats(int *device_countp, int *uclass_countp); +/** + * dm_get_mem() - Get stats on memory usage in driver model + * + * @stats: Place to put the information + */ +void dm_get_mem(struct dm_stats *stats); + #endif diff --git a/include/dm/tag.h b/include/dm/tag.h index 54fc31eb15..745088ffcf 100644 --- a/include/dm/tag.h +++ b/include/dm/tag.h @@ -10,11 +10,23 @@ #include <linux/list.h> #include <linux/types.h> +struct dm_stats; struct udevice; enum dm_tag_t { + /* Types of core tags that can be attached to devices */ + DM_TAG_PLAT, + DM_TAG_PARENT_PLAT, + DM_TAG_UC_PLAT, + + DM_TAG_PRIV, + DM_TAG_PARENT_PRIV, + DM_TAG_UC_PRIV, + DM_TAG_DRIVER_DATA, + DM_TAG_ATTACH_COUNT, + /* EFI_LOADER */ - DM_TAG_EFI = 0, + DM_TAG_EFI = DM_TAG_ATTACH_COUNT, DM_TAG_COUNT, }; @@ -107,4 +119,22 @@ int dev_tag_del(struct udevice *dev, enum dm_tag_t tag); */ int dev_tag_del_all(struct udevice *dev); +/** + * dev_tag_collect_stats() - Collect information on driver model performance + * + * This collects information on how driver model is performing. For now it only + * includes memory usage + * + * @stats: Place to put the collected information + */ +void dev_tag_collect_stats(struct dm_stats *stats); + +/** + * tag_get_name() - Get the name of a tag + * + * @tag: Tag to look up, which must be valid + * Returns: Name of tag + */ +const char *tag_get_name(enum dm_tag_t tag); + #endif /* _DM_TAG_H */ diff --git a/include/dm/test.h b/include/dm/test.h index 4919064cc0..b593750921 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -93,6 +93,13 @@ struct dm_test_uclass_priv { }; /** + * struct dm_test_uclass_plat - private plat data for test uclass + */ +struct dm_test_uclass_plat { + char dummy[32]; +}; + +/** * struct dm_test_parent_data - parent's information on each child * * @sum: Test value used to check parent data works correctly diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 3ba69ad9a0..a432e43871 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -56,6 +56,7 @@ enum uclass_id { UCLASS_ETH, /* Ethernet device */ UCLASS_ETH_PHY, /* Ethernet PHY device */ UCLASS_FIRMWARE, /* Firmware */ + UCLASS_FUZZING_ENGINE, /* Fuzzing engine */ UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ UCLASS_HASH, /* Hash device */ diff --git a/include/dm/util.h b/include/dm/util.h index 4428f045b7..e10c6060ce 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -6,6 +6,8 @@ #ifndef __DM_UTIL_H #define __DM_UTIL_H +struct dm_stats; + #if CONFIG_IS_ENABLED(DM_WARN) #define dm_warn(fmt...) log(LOGC_DM, LOGL_WARNING, ##fmt) #else @@ -25,7 +27,7 @@ struct list_head; int list_count_items(struct list_head *head); /* Dump out a tree of all devices */ -void dm_dump_all(void); +void dm_dump_tree(void); /* Dump out a list of uclasses and their devices */ void dm_dump_uclass(void); @@ -48,6 +50,13 @@ void dm_dump_driver_compat(void); /* Dump out a list of drivers with static platform data */ void dm_dump_static_driver_info(void); +/** + * dm_dump_mem() - Dump stats on memory usage in driver model + * + * @mem: Stats to dump + */ +void dm_dump_mem(struct dm_stats *stats); + #if CONFIG_IS_ENABLED(OF_PLATDATA_INST) && CONFIG_IS_ENABLED(READ_ONLY) void *dm_priv_to_rw(void *priv); #else diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index 63e038e36c..a5204ab91d 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -41,4 +41,7 @@ #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif diff --git a/include/dt-bindings/sound/microchip,pdmc.h b/include/dt-bindings/sound/microchip,pdmc.h new file mode 100644 index 0000000000..96cde94ce7 --- /dev/null +++ b/include/dt-bindings/sound/microchip,pdmc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_MICROCHIP_PDMC_H__ +#define __DT_BINDINGS_MICROCHIP_PDMC_H__ + +/* PDM microphone's pin placement */ +#define MCHP_PDMC_DS0 0 +#define MCHP_PDMC_DS1 1 + +/* PDM microphone clock edge sampling */ +#define MCHP_PDMC_CLK_POSITIVE 0 +#define MCHP_PDMC_CLK_NEGATIVE 1 + +#endif /* __DT_BINDINGS_MICROCHIP_PDMC_H__ */ diff --git a/include/efi_loader.h b/include/efi_loader.h index 11930fbea8..5b41985244 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -591,6 +591,8 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, void efi_save_gd(void); /* Call this to relocate the runtime section to an address space */ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map); +/* Call this to get image parameters */ +void efi_get_image_parameters(void **img_addr, size_t *img_size); /* Add a new object to the object list. */ void efi_add_handle(efi_handle_t obj); /* Create handle */ diff --git a/include/elf.h b/include/elf.h index b04e746d61..aeda159f0c 100644 --- a/include/elf.h +++ b/include/elf.h @@ -188,14 +188,14 @@ typedef struct { #define EM_NDR1 57 /* Denso NDR1 microprocessor */ #define EM_STARCORE 58 /* Motorola Start*Core processor */ #define EM_ME16 59 /* Toyota ME16 processor */ -#define EM_ST100 60 /* STMicroelectronic ST100 processor */ +#define EM_ST100 60 /* STMicroelectronics ST100 processor */ #define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ #define EM_X86_64 62 /* AMD x86-64 */ #define EM_PDSP 63 /* Sony DSP Processor */ /* RESERVED 64,65 for future use */ #define EM_FX66 66 /* Siemens FX66 microcontroller */ #define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ -#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ +#define EM_ST7 68 /* STMicroelectronics ST7 8 bit mc */ #define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ #define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ #define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ diff --git a/include/env_default.h b/include/env_default.h index 7004a6fef2..4e461c815a 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -59,8 +59,8 @@ const char default_environment[] = { #ifdef CONFIG_SERVERIP "serverip=" __stringify(CONFIG_SERVERIP) "\0" #endif -#ifdef CONFIG_SYS_AUTOLOAD - "autoload=" CONFIG_SYS_AUTOLOAD "\0" +#ifdef CONFIG_SYS_DISABLE_AUTOLOAD + "autoload=0\0" #endif #ifdef CONFIG_PREBOOT "preboot=" CONFIG_PREBOOT "\0" @@ -108,10 +108,13 @@ const char default_environment[] = { #if defined(CONFIG_BOOTCOUNT_BOOTLIMIT) && (CONFIG_BOOTCOUNT_BOOTLIMIT > 0) "bootlimit=" __stringify(CONFIG_BOOTCOUNT_BOOTLIMIT)"\0" #endif +#ifdef CONFIG_MTDIDS_DEFAULT + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" +#endif +#ifdef CONFIG_MTDPARTS_DEFAULT + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" +#endif #ifdef CONFIG_EXTRA_ENV_TEXT -# ifdef CONFIG_EXTRA_ENV_SETTINGS -# error "Your board uses a text-file environment, so must not define CONFIG_EXTRA_ENV_SETTINGS" -# endif /* This is created in the Makefile */ CONFIG_EXTRA_ENV_TEXT #endif diff --git a/include/environment/ti/nand.h b/include/environment/ti/nand.h index 11dcefcc41..7d00afa2b1 100644 --- a/include/environment/ti/nand.h +++ b/include/environment/ti/nand.h @@ -14,7 +14,7 @@ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ diff --git a/include/event.h b/include/event.h index 62e72a7bd3..c00c4fb68d 100644 --- a/include/event.h +++ b/include/event.h @@ -144,7 +144,16 @@ int event_register(const char *id, enum event_t type, event_handler_t func, /** event_show_spy_list( - Show a list of event spies */ void event_show_spy_list(void); -#if CONFIG_IS_ENABLED(EVENT) +/** + * event_manual_reloc() - Relocate event handler pointers + * + * Relocate event handler pointers for all static event spies. It is called + * during the generic board init sequence, after relocation. + * + * Return: 0 if OK + */ +int event_manual_reloc(void); + /** * event_notify() - notify spies about an event * @@ -159,6 +168,7 @@ void event_show_spy_list(void); */ int event_notify(enum event_t type, void *data, int size); +#if CONFIG_IS_ENABLED(EVENT) /** * event_notify_null() - notify spies about an event * @@ -169,11 +179,6 @@ int event_notify(enum event_t type, void *data, int size); */ int event_notify_null(enum event_t type); #else -static inline int event_notify(enum event_t type, void *data, int size) -{ - return 0; -} - static inline int event_notify_null(enum event_t type) { return 0; diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h index fb838db0b5..3092a0ea62 100644 --- a/include/fsl_sec_mon.h +++ b/include/fsl_sec_mon.h @@ -23,8 +23,6 @@ #define sec_mon_in16(a) in_be16(a) #define sec_mon_clrbits32 clrbits_be32 #define sec_mon_setbits32 setbits_be32 -#else -#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined #endif struct ccsr_sec_mon_regs { diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h index 613814d905..e7674c1bff 100644 --- a/include/fsl_sfp.h +++ b/include/fsl_sfp.h @@ -24,8 +24,6 @@ #define sfp_in32(a) in_be32(a) #define sfp_out32(a, v) out_be32(a, v) #define sfp_in16(a) in_be16(a) -#else -#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined #endif /* Number of SRKH registers */ diff --git a/include/fuzzing_engine.h b/include/fuzzing_engine.h new file mode 100644 index 0000000000..357346e93d --- /dev/null +++ b/include/fuzzing_engine.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2022 Google, Inc. + * Written by Andrew Scull <ascull@google.com> + */ + +#ifndef __FUZZING_ENGINE_H +#define __FUZZING_ENGINE_H + +struct udevice; + +/** + * dm_fuzzing_engine_get_input() - get an input from the fuzzing engine device + * + * The function will return a pointer to the input data and the size of the + * data pointed to. The pointer will remain valid until the next invocation of + * this function. + * + * @dev: fuzzing engine device + * @data: output pointer to input data + * @size output size of input data + * Return: 0 if OK, -ve on error + */ +int dm_fuzzing_engine_get_input(struct udevice *dev, + const uint8_t **data, + size_t *size); + +/** + * struct dm_fuzzing_engine_ops - operations for the fuzzing engine uclass + * + * This contains the functions implemented by a fuzzing engine device. + */ +struct dm_fuzzing_engine_ops { + /** + * @get_input() - get an input + * + * The function will return a pointer to the input data and the size of + * the data pointed to. The pointer will remain valid until the next + * invocation of this function. + * + * @get_input.dev: fuzzing engine device + * @get_input.data: output pointer to input data + * @get_input.size output size of input data + * @get_input.Return: 0 if OK, -ve on error + */ + int (*get_input)(struct udevice *dev, + const uint8_t **data, + size_t *size); +}; + +#endif /* __FUZZING_ENGINE_H */ diff --git a/include/i2c.h b/include/i2c.h index 22add0b528..e0ee94e550 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -647,9 +647,6 @@ void i2c_early_init_f(void); #if !defined(CONFIG_SYS_RTC_BUS_NUM) #define CONFIG_SYS_RTC_BUS_NUM 0 #endif -#if !defined(CONFIG_SYS_SPD_BUS_NUM) -#define CONFIG_SYS_SPD_BUS_NUM 0 -#endif struct i2c_adapter { void (*init)(struct i2c_adapter *adap, int speed, diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h index 3ad565684f..32dcb03497 100644 --- a/include/i2c_eeprom.h +++ b/include/i2c_eeprom.h @@ -6,6 +6,8 @@ #ifndef __I2C_EEPROM #define __I2C_EEPROM +struct udevice; + struct i2c_eeprom_ops { int (*read)(struct udevice *dev, int offset, uint8_t *buf, int size); int (*write)(struct udevice *dev, int offset, const uint8_t *buf, @@ -20,6 +22,7 @@ struct i2c_eeprom { unsigned long size; }; +#if CONFIG_IS_ENABLED(I2C_EEPROM) /* * i2c_eeprom_read() - read bytes from an I2C EEPROM chip * @@ -42,7 +45,8 @@ int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size); * * Return: 0 on success, -ve on failure */ -int i2c_eeprom_write(struct udevice *dev, int offset, uint8_t *buf, int size); +int i2c_eeprom_write(struct udevice *dev, int offset, const uint8_t *buf, + int size); /* * i2c_eeprom_size() - get size of I2C EEPROM chip @@ -53,4 +57,25 @@ int i2c_eeprom_write(struct udevice *dev, int offset, uint8_t *buf, int size); */ int i2c_eeprom_size(struct udevice *dev); +#else /* !I2C_EEPROM */ + +static inline int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, + int size) +{ + return -ENOSYS; +} + +static inline int i2c_eeprom_write(struct udevice *dev, int offset, + const uint8_t *buf, int size) +{ + return -ENOSYS; +} + +static inline int i2c_eeprom_size(struct udevice *dev) +{ + return -ENOSYS; +} + +#endif /* I2C_EEPROM */ + #endif diff --git a/include/ide.h b/include/ide.h index 2994b7a762..426cef4e39 100644 --- a/include/ide.h +++ b/include/ide.h @@ -33,10 +33,6 @@ ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer); #endif -#ifdef CONFIG_IDE_PREINIT -int ide_preinit(void); -#endif - #if defined(CONFIG_OF_IDE_FIXUP) int ide_device_present(int dev); #endif diff --git a/include/k3-clk.h b/include/k3-clk.h index 31292b59f2..371f077c44 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -174,6 +174,7 @@ struct ti_k3_clk_platdata { extern const struct ti_k3_clk_platdata j721e_clk_platdata; extern const struct ti_k3_clk_platdata j7200_clk_platdata; extern const struct ti_k3_clk_platdata j721s2_clk_platdata; +extern const struct ti_k3_clk_platdata am62x_clk_platdata; struct clk *clk_register_ti_pll(const char *name, const char *parent_name, void __iomem *reg); diff --git a/include/k3-dev.h b/include/k3-dev.h index b46b8c3aab..87e873b9ce 100644 --- a/include/k3-dev.h +++ b/include/k3-dev.h @@ -78,6 +78,7 @@ struct ti_k3_pd_platdata { extern const struct ti_k3_pd_platdata j721e_pd_platdata; extern const struct ti_k3_pd_platdata j7200_pd_platdata; extern const struct ti_k3_pd_platdata j721s2_pd_platdata; +extern const struct ti_k3_pd_platdata am62x_pd_platdata; u8 ti_pd_state(struct ti_pd *pd); u8 lpsc_get_state(struct ti_lpsc *lpsc); diff --git a/include/lcd.h b/include/lcd.h index 51a79317bb..4f18069278 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -40,10 +40,7 @@ ulong lcd_setmem(ulong addr); */ void lcd_set_flush_dcache(int flush); -#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ - defined CONFIG_CPU_MONAHANS -#include <pxa_lcd.h> -#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) +#if defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) #include <atmel_lcd.h> #elif defined(CONFIG_EXYNOS_FB) #include <exynos_lcd.h> diff --git a/include/linker_lists.h b/include/linker_lists.h index 0575164ce4..d3da9d44e8 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -70,7 +70,7 @@ #define ll_entry_declare(_type, _name, _list) \ _type _u_boot_list_2_##_list##_2_##_name __aligned(4) \ __attribute__((unused)) \ - __section(".u_boot_list_2_"#_list"_2_"#_name) + __section("__u_boot_list_2_"#_list"_2_"#_name) /** * ll_entry_declare_list() - Declare a list of link-generated array entries @@ -93,7 +93,7 @@ #define ll_entry_declare_list(_type, _name, _list) \ _type _u_boot_list_2_##_list##_2_##_name[] __aligned(4) \ __attribute__((unused)) \ - __section(".u_boot_list_2_"#_list"_2_"#_name) + __section("__u_boot_list_2_"#_list"_2_"#_name) /* * We need a 0-byte-size type for iterator symbols, and the compiler @@ -110,7 +110,7 @@ * @_list: Name of the list in which this entry is placed * * This function returns ``(_type *)`` pointer to the very first entry of a - * linker-generated array placed into subsection of .u_boot_list section + * linker-generated array placed into subsection of __u_boot_list section * specified by _list argument. * * Since this macro defines an array start symbol, its leftmost index @@ -126,7 +126,7 @@ ({ \ static char start[0] __aligned(CONFIG_LINKER_LIST_ALIGN) \ __attribute__((unused)) \ - __section(".u_boot_list_2_"#_list"_1"); \ + __section("__u_boot_list_2_"#_list"_1"); \ (_type *)&start; \ }) @@ -137,7 +137,7 @@ * (with underscores instead of dots) * * This function returns ``(_type *)`` pointer after the very last entry of - * a linker-generated array placed into subsection of .u_boot_list + * a linker-generated array placed into subsection of __u_boot_list * section specified by _list argument. * * Since this macro defines an array end symbol, its leftmost index @@ -152,7 +152,7 @@ #define ll_entry_end(_type, _list) \ ({ \ static char end[0] __aligned(4) __attribute__((unused)) \ - __section(".u_boot_list_2_"#_list"_3"); \ + __section("__u_boot_list_2_"#_list"_3"); \ (_type *)&end; \ }) /** @@ -161,7 +161,7 @@ * @_list: Name of the list of which the number of elements is computed * * This function returns the number of elements of a linker-generated array - * placed into subsection of .u_boot_list section specified by _list + * placed into subsection of __u_boot_list section specified by _list * argument. The result is of an unsigned int type. * * Example: @@ -246,7 +246,7 @@ #define ll_start(_type) \ ({ \ static char start[0] __aligned(4) __attribute__((unused)) \ - __section(".u_boot_list_1"); \ + __section("__u_boot_list_1"); \ (_type *)&start; \ }) @@ -269,7 +269,7 @@ #define ll_end(_type) \ ({ \ static char end[0] __aligned(4) __attribute__((unused)) \ - __section(".u_boot_list_3"); \ + __section("__u_boot_list_3"); \ (_type *)&end; \ }) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 7f2be23394..e1d09884a1 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -51,6 +51,10 @@ #define ARM_SMCCC_QUIRK_NONE 0 #define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ +#define ARM_SMCCC_ARCH_FEATURES 0x80000001 + +#define ARM_SMCCC_RET_NOT_SUPPORTED ((unsigned long)-1) + #ifndef __ASSEMBLY__ #include <linux/linkage.h> @@ -80,6 +84,22 @@ struct arm_smccc_quirk { }; /** + * struct arm_smccc_feature - Driver registration data for discoverable feature + * @driver_name: name of the driver relate to the SMCCC feature + * @is_supported: callback to test if SMCCC feature is supported + */ +struct arm_smccc_feature { + const char *driver_name; + bool (*is_supported)(void (*invoke_fn)(unsigned long a0, unsigned long a1, unsigned long a2, + unsigned long a3, unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_res *res)); +}; + +#define ARM_SMCCC_FEATURE_DRIVER(__name) \ + ll_entry_declare(struct arm_smccc_feature, __name, arm_smccc_feature) + +/** * __arm_smccc_smc() - make SMC calls * @a0-a7: arguments passed in registers 0 to 7 * @res: result values from registers 0 to 3 diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h index 6079f9e260..1d8a067f17 100644 --- a/include/linux/mtd/fsmc_nand.h +++ b/include/linux/mtd/fsmc_nand.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2010 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. */ #ifndef __FSMC_NAND_H__ diff --git a/include/linux/psci.h b/include/linux/psci.h index c78c1079a8..03e4186343 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -11,6 +11,8 @@ #ifndef _UAPI_LINUX_PSCI_H #define _UAPI_LINUX_PSCI_H +#include <linux/arm-smccc.h> + /* * PSCI v0.1 interface * @@ -115,6 +117,18 @@ #define PSCI_RET_DISABLED -8 #define PSCI_RET_INVALID_ADDRESS -9 +/** + * struct psci_plat_data - PSCI driver platform data + * @method: Selected invocation conduit + */ +struct psci_plat_data { + void (*invoke_fn)(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6, unsigned long arg7, + struct arm_smccc_res *res); +}; + #ifdef CONFIG_ARM_PSCI_FW unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3); diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 1367149c4b..40979f72fc 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -53,21 +53,4 @@ struct fsl_xhci { struct dwc3 *dwc3_reg; }; -#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR -#endif - -#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ - CONFIG_SYS_FSL_XHCI_USB2_ADDR, \ - CONFIG_SYS_FSL_XHCI_USB3_ADDR} #endif /* _ASM_ARCH_XHCI_FSL_H_ */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 2c69a60de6..053b68a10a 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -26,7 +26,7 @@ * Define default values for some CCSR macros to make header files cleaner* * * To completely disable CCSR relocation in a board header file, define - * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS + * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS * to a value that is the same as CONFIG_SYS_CCSRBAR. */ @@ -35,7 +35,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." #endif -#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE) #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH #undef CONFIG_SYS_CCSRBAR_PHYS_LOW #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 diff --git a/include/nvmem.h b/include/nvmem.h new file mode 100644 index 0000000000..822e698bdd --- /dev/null +++ b/include/nvmem.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2022 Sean Anderson <sean.anderson@seco.com> + */ + +#ifndef NVMEM_H +#define NVMEM_H + +/** + * DOC: Design + * + * The NVMEM subsystem is a "meta-uclass" in that it abstracts over several + * different uclasses all with read/write APIs. One approach to implementing + * this could be to add a new sub-device for each nvmem-style device of + * UCLASS_NVMEM. This subsystem has taken the approach of using the existing + * access methods (i2c_eeprom_write, misc_write, etc.) directly. This has the + * advantage of not requiring an extra device/driver, saving on binary size and + * runtime memory usage. On the other hand, it is not idiomatic. Similar + * efforts should generally use a new uclass. + */ + +/** + * struct nvmem_cell - One datum within non-volatile memory + * @nvmem: The backing storage device + * @offset: The offset of the cell from the start of @nvmem + * @size: The size of the cell, in bytes + */ +struct nvmem_cell { + struct udevice *nvmem; + unsigned int offset; + size_t size; +}; + +struct udevice; + +#if CONFIG_IS_ENABLED(NVMEM) + +/** + * nvmem_cell_read() - Read the value of an nvmem cell + * @cell: The nvmem cell to read + * @buf: The buffer to read into + * @size: The size of @buf + * + * Return: + * * 0 on success + * * -EINVAL if @buf is not the same size as @cell. + * * -ENOSYS if CONFIG_NVMEM is disabled + * * A negative error if there was a problem reading the underlying storage + */ +int nvmem_cell_read(struct nvmem_cell *cell, void *buf, size_t size); + +/** + * nvmem_cell_write() - Write a value to an nvmem cell + * @cell: The nvmem cell to write + * @buf: The buffer to write from + * @size: The size of @buf + * + * Return: + * * 0 on success + * * -EINVAL if @buf is not the same size as @cell + * * -ENOSYS if @cell is read-only, or if CONFIG_NVMEM is disabled + * * A negative error if there was a problem writing the underlying storage + */ +int nvmem_cell_write(struct nvmem_cell *cell, const void *buf, size_t size); + +/** + * nvmem_cell_get_by_index() - Get an nvmem cell from a given device and index + * @dev: The device that uses the nvmem cell + * @index: The index of the cell in nvmem-cells + * @cell: The cell to initialize + * + * Look up the nvmem cell referenced by the phandle at @index in nvmem-cells in + * @dev. + * + * Return: + * * 0 on success + * * -EINVAL if the regs property is missing, empty, or undersized + * * -ENODEV if the nvmem device is missing or unimplemented + * * -ENOSYS if CONFIG_NVMEM is disabled + * * A negative error if there was a problem reading nvmem-cells or getting the + * device + */ +int nvmem_cell_get_by_index(struct udevice *dev, int index, + struct nvmem_cell *cell); + +/** + * nvmem_cell_get_by_name() - Get an nvmem cell from a given device and name + * @dev: The device that uses the nvmem cell + * @name: The name of the nvmem cell + * @cell: The cell to initialize + * + * Look up the nvmem cell referenced by @name in the nvmem-cell-names property + * of @dev. + * + * Return: + * * 0 on success + * * -EINVAL if the regs property is missing, empty, or undersized + * * -ENODEV if the nvmem device is missing or unimplemented + * * -ENODATA if @name is not in nvmem-cell-names + * * -ENOSYS if CONFIG_NVMEM is disabled + * * A negative error if there was a problem reading nvmem-cell-names, + * nvmem-cells, or getting the device + */ +int nvmem_cell_get_by_name(struct udevice *dev, const char *name, + struct nvmem_cell *cell); + +#else /* CONFIG_NVMEM */ + +static inline int nvmem_cell_read(struct nvmem_cell *cell, void *buf, int size) +{ + return -ENOSYS; +} + +static inline int nvmem_cell_write(struct nvmem_cell *cell, const void *buf, + int size) +{ + return -ENOSYS; +} + +static inline int nvmem_cell_get_by_index(struct udevice *dev, int index, + struct nvmem_cell *cell) +{ + return -ENOSYS; +} + +static inline int nvmem_cell_get_by_name(struct udevice *dev, const char *name, + struct nvmem_cell *cell) +{ + return -ENOSYS; +} + +#endif /* CONFIG_NVMEM */ + +#endif /* NVMEM_H */ diff --git a/include/os.h b/include/os.h index 10e198cf50..148178787b 100644 --- a/include/os.h +++ b/include/os.h @@ -17,6 +17,13 @@ struct rtc_time; struct sandbox_state; /** + * os_printf() - print directly to OS console + * + * @format: format string + */ +int os_printf(const char *format, ...); + +/** * Access to the OS read() system call * * @fd: File descriptor as returned by os_open() diff --git a/include/power/fg_battery_cell_params.h b/include/power/fg_battery_cell_params.h index b8c895bbab..500c8ea717 100644 --- a/include/power/fg_battery_cell_params.h +++ b/include/power/fg_battery_cell_params.h @@ -7,7 +7,7 @@ #ifndef __FG_BATTERY_CELL_PARAMS_H_ #define __FG_BATTERY_CELL_PARAMS_H_ -#if defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TRATS) +#if defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TARGET_TRATS) /* Cell characteristics - Exynos4 TRATS development board */ /* Shall be written to addr 0x80h */ diff --git a/include/power/stpmic1.h b/include/power/stpmic1.h index d3567df326..201b1df762 100644 --- a/include/power/stpmic1.h +++ b/include/power/stpmic1.h @@ -23,12 +23,9 @@ /* BUCKS_MRST_CR */ #define STPMIC1_MRST_BUCK(buck) BIT(buck) -#define STPMIC1_MRST_BUCK_DEBUG (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \ - STPMIC1_MRST_BUCK(STPMIC1_BUCK3)) /* LDOS_MRST_CR */ #define STPMIC1_MRST_LDO(ldo) BIT(ldo) -#define STPMIC1_MRST_LDO_DEBUG 0 /* BUCKx_MAIN_CR (x=1...4) */ #define STPMIC1_BUCK_ENA BIT(0) diff --git a/include/pxa_lcd.h b/include/pxa_lcd.h deleted file mode 100644 index 11a22abca6..0000000000 --- a/include/pxa_lcd.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * pxa_lcd.h - PXA LCD Controller structures - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#ifndef _PXA_LCD_H_ -#define _PXA_LCD_H_ - -/* - * PXA LCD DMA descriptor - */ -struct pxafb_dma_descriptor { - u_long fdadr; /* Frame descriptor address register */ - u_long fsadr; /* Frame source address register */ - u_long fidr; /* Frame ID register */ - u_long ldcmd; /* Command register */ -}; - -/* - * PXA LCD info - */ -struct pxafb_info { - /* Misc registers */ - u_long reg_lccr3; - u_long reg_lccr2; - u_long reg_lccr1; - u_long reg_lccr0; - u_long fdadr0; - u_long fdadr1; - - /* DMA descriptors */ - struct pxafb_dma_descriptor *dmadesc_fblow; - struct pxafb_dma_descriptor *dmadesc_fbhigh; - struct pxafb_dma_descriptor *dmadesc_palette; - - u_long screen; /* physical address of frame buffer */ - u_long palette; /* physical address of palette memory */ - u_int palette_size; -}; - -/* - * LCD controller stucture for PXA CPU - */ -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ - ushort vl_width; /* Width of display area in millimeters */ - ushort vl_height; /* Height of display area in millimeters */ - - /* LCD configuration register */ - u_char vl_clkp; /* Clock polarity */ - u_char vl_oep; /* Output Enable polarity */ - u_char vl_hsp; /* Horizontal Sync polarity */ - u_char vl_vsp; /* Vertical Sync polarity */ - u_char vl_dp; /* Data polarity */ - u_char vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ - u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ - u_char vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */ - u_char vl_clor; /* Color, 0 = mono, 1 = color */ - u_char vl_tft; /* 0 = passive, 1 = TFT */ - - /* Horizontal control register. Timing from data sheet */ - ushort vl_hpw; /* Horz sync pulse width */ - u_char vl_blw; /* Wait before of line */ - u_char vl_elw; /* Wait end of line */ - - /* Vertical control register. */ - u_char vl_vpw; /* Vertical sync pulse width */ - u_char vl_bfw; /* Wait before of frame */ - u_char vl_efw; /* Wait end of frame */ - - /* PXA LCD controller params */ - struct pxafb_info pxa; -} vidinfo_t; - -#endif diff --git a/include/regmap.h b/include/regmap.h index 8216de015d..e81a3602ae 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -460,7 +460,7 @@ struct reg_field { struct regmap_field; /** - * REG_FIELD() - A convenient way to initialize a 'struct reg_feild'. + * REG_FIELD() - A convenient way to initialize a 'struct reg_field'. * * @_reg: Offset of the register within the regmap bank * @_lsb: lsb of the register field. @@ -519,9 +519,9 @@ void devm_regmap_field_free(struct udevice *dev, struct regmap_field *field); int regmap_field_write(struct regmap_field *field, unsigned int val); /** - * regmap_read() - Read a 32-bit value from a regmap + * regmap_field_read() - Read a 32-bit value from a regmap * - * @field: Regmap field to write to + * @field: Regmap field to read from * @valp: Pointer to the buffer to receive the data read from the regmap * field * diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h index a501d1b482..b1c93532c0 100644 --- a/include/scmi_agent-uclass.h +++ b/include/scmi_agent-uclass.h @@ -7,18 +7,29 @@ struct udevice; struct scmi_msg; +struct scmi_channel; /** * struct scmi_transport_ops - The functions that a SCMI transport layer must implement. */ struct scmi_agent_ops { /* + * of_get_channel - Get SCMI channel from SCMI agent device tree node + * + * @dev: SCMI protocol device using the transport + * @channel: Output reference to SCMI channel upon success + * Return 0 upon success and a negative errno on failure + */ + int (*of_get_channel)(struct udevice *dev, struct scmi_channel **channel); + + /* * process_msg - Request transport to get the SCMI message processed * - * @agent: Agent using the transport + * @dev: SCMI protocol device using the transport * @msg: SCMI message to be transmitted */ - int (*process_msg)(struct udevice *dev, struct scmi_msg *msg); + int (*process_msg)(struct udevice *dev, struct scmi_channel *channel, + struct scmi_msg *msg); }; #endif /* _SCMI_TRANSPORT_UCLASS_H */ diff --git a/include/scmi_agent.h b/include/scmi_agent.h index 18bcd48a9d..ee6286366d 100644 --- a/include/scmi_agent.h +++ b/include/scmi_agent.h @@ -13,6 +13,7 @@ #include <asm/types.h> struct udevice; +struct scmi_channel; /* * struct scmi_msg - Context of a SCMI message sent and the response received @@ -45,6 +46,15 @@ struct scmi_msg { } /** + * devm_scmi_of_get_channel() - Get SCMI channel handle from SCMI agent DT node + * + * @dev: Device requesting a channel + * @channel: Output reference to the SCMI channel upon success + * @return 0 on success and a negative errno on failure + */ +int devm_scmi_of_get_channel(struct udevice *dev, struct scmi_channel **channel); + +/** * devm_scmi_process_msg() - Send and process an SCMI message * * Send a message to an SCMI server through a target SCMI agent device. @@ -52,10 +62,12 @@ struct scmi_msg { * On return, scmi_msg::out_msg_sz stores the response payload size. * * @dev: SCMI device + * @channel: Communication channel for the device * @msg: Message structure reference * Return: 0 on success and a negative errno on failure */ -int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg); +int devm_scmi_process_msg(struct udevice *dev, struct scmi_channel *channel, + struct scmi_msg *msg); /** * scmi_to_linux_errno() - Convert an SCMI error code into a Linux errno code diff --git a/include/spl.h b/include/spl.h index 83ac583e0b..aac6648f94 100644 --- a/include/spl.h +++ b/include/spl.h @@ -288,6 +288,8 @@ binman_sym_extern(ulong, u_boot_any, image_pos); binman_sym_extern(ulong, u_boot_any, size); binman_sym_extern(ulong, u_boot_spl, image_pos); binman_sym_extern(ulong, u_boot_spl, size); +binman_sym_extern(ulong, u_boot_vpl, image_pos); +binman_sym_extern(ulong, u_boot_vpl, size); /** * spl_get_image_pos() - get the image position of the next phase @@ -378,6 +380,22 @@ void preloader_console_init(void); u32 spl_boot_device(void); /** + * spl_spi_boot_bus() - Lookup function for the SPI boot bus source. + * + * This function returns the SF bus to load from. + * If not overridden, it is weakly defined in common/spl/spl_spi.c. + */ +u32 spl_spi_boot_bus(void); + +/** + * spl_spi_boot_cs() - Lookup function for the SPI boot CS source. + * + * This function returns the SF CS to load from. + * If not overridden, it is weakly defined in common/spl/spl_spi.c. + */ +u32 spl_spi_boot_cs(void); + +/** * spl_mmc_boot_mode() - Lookup function for the mode of an MMC boot source. * @boot_device: ID of the device which the MMC driver wants to read * from. Common values are e.g. BOOT_DEVICE_MMC1, diff --git a/include/system-constants.h b/include/system-constants.h new file mode 100644 index 0000000000..83b41b384f --- /dev/null +++ b/include/system-constants.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SYSTEM_CONSTANTS_H__ +#define __SYSTEM_CONSTANTS_H__ + +/* + * The most common case for our initial stack pointer address is to + * say that we have defined a static intiial ram address location and + * size and from that we subtract the generated global data size. + */ +#ifdef CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR +#define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR +#else +#ifdef CONFIG_MIPS +#define SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET) +#else +#define SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#endif +#endif + +/* + * Typically, we have the SPL malloc pool at the end of the BSS area. + */ +#ifdef CONFIG_HAS_CUSTOM_SPL_MALLOC_START +#define SYS_SPL_MALLOC_START CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR +#else +#define SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#endif + +#endif diff --git a/include/test/fuzz.h b/include/test/fuzz.h new file mode 100644 index 0000000000..d4c57540eb --- /dev/null +++ b/include/test/fuzz.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2022 Google, Inc. + * Written by Andrew Scull <ascull@google.com> + */ + +#ifndef __TEST_FUZZ_H +#define __TEST_FUZZ_H + +#include <linker_lists.h> +#include <linux/types.h> + +/** + * struct fuzz_test - Information about a fuzz test + * + * @name: Name of fuzz test + * @func: Function to call to perform fuzz test on an input + * @flags: Flags indicate pre-conditions for fuzz test + */ +struct fuzz_test { + const char *name; + int (*func)(const uint8_t * data, size_t size); + int flags; +}; + +/** + * FUZZ_TEST() - register a fuzz test + * + * The fuzz test function must return 0 as other values are reserved for future + * use. + * + * @_name: the name of the fuzz test function + * @_flags: an integer field that can be evaluated by the fuzzer + * implementation + */ +#define FUZZ_TEST(_name, _flags) \ + ll_entry_declare(struct fuzz_test, _name, fuzz_tests) = { \ + .name = #_name, \ + .func = _name, \ + .flags = _flags, \ + } + +/** Get the start of the list of fuzz tests */ +#define FUZZ_TEST_START() \ + ll_entry_start(struct fuzz_test, fuzz_tests) + +/** Get the number of elements in the list of fuzz tests */ +#define FUZZ_TEST_COUNT() \ + ll_entry_count(struct fuzz_test, fuzz_tests) + +#endif /* __TEST_FUZZ_H */ diff --git a/include/test/suites.h b/include/test/suites.h index ee6858a802..ddb8827fdb 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -39,6 +39,7 @@ int do_ut_compression(struct cmd_tbl *cmdtp, int flag, int argc, int do_ut_dm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_env(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_lib(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_loadm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_log(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); int do_ut_mem(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_optee(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h index 283f103293..09fee594d2 100644 --- a/include/u-boot/sha1.h +++ b/include/u-boot/sha1.h @@ -30,7 +30,7 @@ extern const uint8_t sha1_der_prefix[]; typedef struct { unsigned long total[2]; /*!< number of bytes processed */ - unsigned long state[5]; /*!< intermediate digest state */ + uint32_t state[5]; /*!< intermediate digest state */ unsigned char buffer[64]; /*!< data block being processed */ } sha1_context; diff --git a/include/usb/designware_udc.h b/include/usb/designware_udc.h index f874e5c35c..f716f07dd0 100644 --- a/include/usb/designware_udc.h +++ b/include/usb/designware_udc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. */ #ifndef __DW_UDC_H diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 2cdb3146e8..bc98093458 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -146,21 +146,6 @@ #define MPC83XX_SCCR_USB_DRCM_01 0x00100000 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 -#if defined(CONFIG_MPC83xx) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR -#if defined(CONFIG_ARCH_MPC834X) -#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR -#else -#define CONFIG_SYS_FSL_USB2_ADDR 0 -#endif -#elif defined(CONFIG_MPC85xx) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR -#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR -#elif defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR -#define CONFIG_SYS_FSL_USB2_ADDR 0 -#endif - /* * Increasing TX FIFO threshold value from 2 to 4 decreases * data burst rate with which data packets are posted from the TX diff --git a/include/usb/pxa27x_udc.h b/include/usb/pxa27x_udc.h deleted file mode 100644 index 07d14821c3..0000000000 --- a/include/usb/pxa27x_udc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * PXA27x register declarations and HCD data structures - * - * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it> - * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it> - */ - - -#ifndef __PXA270X_UDC_H__ -#define __PXA270X_UDC_H__ - -#include <asm/byteorder.h> - -/* Endpoint 0 states */ -#define EP0_IDLE 0 -#define EP0_IN_DATA 1 -#define EP0_OUT_DATA 2 -#define EP0_XFER_COMPLETE 3 - - -/* Endpoint parameters */ -#define MAX_ENDPOINTS 4 - -#define EP0_MAX_PACKET_SIZE 16 - -#define UDC_OUT_ENDPOINT 0x02 -#define UDC_IN_ENDPOINT 0x01 -#define UDC_INT_ENDPOINT 0x05 - -#endif diff --git a/include/virtio_ring.h b/include/virtio_ring.h index 6fc0593b14..c77c212cff 100644 --- a/include/virtio_ring.h +++ b/include/virtio_ring.h @@ -55,6 +55,16 @@ struct vring_desc { __virtio16 next; }; +/* Shadow of struct vring_desc in guest byte order. */ +struct vring_desc_shadow { + u64 addr; + u32 len; + u16 flags; + u16 next; + /* Metadata about the descriptor. */ + bool chain_head; +}; + struct vring_avail { __virtio16 flags; __virtio16 idx; @@ -89,6 +99,7 @@ struct vring { * @index: the zero-based ordinal number for this queue * @num_free: number of elements we expect to be able to fit * @vring: actual memory layout for this queue + * @vring_desc_shadow: guest-only copy of descriptors * @event: host publishes avail event idx * @free_head: head of free buffer list * @num_added: number we've added since last sync @@ -102,6 +113,7 @@ struct virtqueue { unsigned int index; unsigned int num_free; struct vring vring; + struct vring_desc_shadow *vring_desc_shadow; bool event; unsigned int free_head; unsigned int num_added; diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 76ec2141ff..6c4fd9a6c5 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -160,6 +160,12 @@ enum dll_reset_type { PM_DLL_RESET_PULSE = 2, }; +enum ospi_mux_select_type { + PM_OSPI_MUX_SEL_DMA, + PM_OSPI_MUX_SEL_LINEAR, + PM_OSPI_MUX_GET_MODE, +}; + enum pm_query_id { PM_QID_INVALID = 0, PM_QID_CLOCK_GET_NAME = 1, @@ -427,6 +433,9 @@ enum pm_gem_config_type { #define ZYNQMP_PM_VERSION_INVALID ~0 #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) +#define PMIO_NODE_ID_BASE 0x1410801B + +#define PMIO_NODE_ID_BASE 0x1410801B /* * Return payload size |