clk: k210: Rewrite to remove CCF

This is effectively a complete rewrite to remove all dependency on CCF.
The code is now smaller, and so is the binary. It also takes up less memory
at runtime (since we don't have to create 40 udevices). In general, I am
much happier with this driver as much of the complexity and late binding
has been removed.

The k210_*_params structs which were previously used to initialize CCF
clocks are now used as the complete configuration. Since we can write our
own division logic, we can now do away with several "half" clocks which
only existed to provide constant factors of two.

The clock IDs have been renumbered to remove unused clocks. This may not be
the last time they are renumbered, since we have diverged with Linux. There
are also still a few clocks left out which may need to be added back in.

In general, I have tried to leave out behavioral changes. However, there is
a small bugfix regarding ACLK. According to the technical reference manual,
its mux comes *after* its divider (which is present only for PLL0). This
would have required yet another intermediate clock to fix with CCF, but
with the new driver it is just 2 lines of code :)

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

2 files changed, 59 insertions, 61 deletions

diff --git a/include/dt-bindings/clock/k210-sysctl.h b/include/dt-bindings/clock/k210-sysctl.h
index fe852bbd92..6b0d5b46f8 100644
--- a/include/dt-bindings/clock/k210-sysctl.h
+++ b/include/dt-bindings/clock/k210-sysctl.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ * Copyright (C) 2019-21 Sean Anderson <seanga2@gmail.com>
  */
 
 #ifndef CLOCK_K210_SYSCTL_H
@@ -9,52 +9,50 @@
 /*
  * Arbitrary identifiers for clocks.
  */
-#define K210_CLK_NONE   0
-#define K210_CLK_IN0_H  1
-#define K210_CLK_PLL0_H 2
-#define K210_CLK_PLL0   3
-#define K210_CLK_PLL1   4
-#define K210_CLK_PLL2   5
-#define K210_CLK_PLL2_H 6
-#define K210_CLK_CPU    7
-#define K210_CLK_SRAM0  8
-#define K210_CLK_SRAM1  9
-#define K210_CLK_APB0   10
-#define K210_CLK_APB1   11
-#define K210_CLK_APB2   12
-#define K210_CLK_ROM    13
-#define K210_CLK_DMA    14
-#define K210_CLK_AI     15
-#define K210_CLK_DVP    16
-#define K210_CLK_FFT    17
-#define K210_CLK_GPIO   18
-#define K210_CLK_SPI0   19
-#define K210_CLK_SPI1   20
-#define K210_CLK_SPI2   21
-#define K210_CLK_SPI3   22
-#define K210_CLK_I2S0   23
-#define K210_CLK_I2S1   24
-#define K210_CLK_I2S2   25
-#define K210_CLK_I2S0_M 26
-#define K210_CLK_I2S1_M 27
-#define K210_CLK_I2S2_M 28
-#define K210_CLK_I2C0   29
-#define K210_CLK_I2C1   30
-#define K210_CLK_I2C2   31
-#define K210_CLK_UART1  32
-#define K210_CLK_UART2  33
-#define K210_CLK_UART3  34
-#define K210_CLK_AES    35
-#define K210_CLK_FPIOA  36
-#define K210_CLK_TIMER0 37
-#define K210_CLK_TIMER1 38
-#define K210_CLK_TIMER2 39
-#define K210_CLK_WDT0   40
-#define K210_CLK_WDT1   41
-#define K210_CLK_SHA    42
-#define K210_CLK_OTP    43
-#define K210_CLK_RTC    44
-#define K210_CLK_ACLK   45
-#define K210_CLK_CLINT  46
+
+#define K210_CLK_PLL0   0
+#define K210_CLK_PLL1   1
+#define K210_CLK_PLL2   2
+#define K210_CLK_CPU    3
+#define K210_CLK_SRAM0  4
+#define K210_CLK_SRAM1  5
+#define K210_CLK_ACLK   6
+#define K210_CLK_CLINT  7
+#define K210_CLK_APB0   8
+#define K210_CLK_APB1   9
+#define K210_CLK_APB2   10
+#define K210_CLK_ROM    11
+#define K210_CLK_DMA    12
+#define K210_CLK_AI     13
+#define K210_CLK_DVP    14
+#define K210_CLK_FFT    15
+#define K210_CLK_GPIO   16
+#define K210_CLK_SPI0   17
+#define K210_CLK_SPI1   18
+#define K210_CLK_SPI2   19
+#define K210_CLK_SPI3   20
+#define K210_CLK_I2S0   21
+#define K210_CLK_I2S1   22
+#define K210_CLK_I2S2   23
+#define K210_CLK_I2S0_M 24
+#define K210_CLK_I2S1_M 25
+#define K210_CLK_I2S2_M 26
+#define K210_CLK_I2C0   27
+#define K210_CLK_I2C1   28
+#define K210_CLK_I2C2   29
+#define K210_CLK_UART1  30
+#define K210_CLK_UART2  31
+#define K210_CLK_UART3  32
+#define K210_CLK_AES    33
+#define K210_CLK_FPIOA  34
+#define K210_CLK_TIMER0 35
+#define K210_CLK_TIMER1 36
+#define K210_CLK_TIMER2 37
+#define K210_CLK_WDT0   38
+#define K210_CLK_WDT1   39
+#define K210_CLK_SHA    40
+#define K210_CLK_OTP    41
+#define K210_CLK_RTC    42
+#define K210_CLK_IN0	43
 
 #endif /* CLOCK_K210_SYSCTL_H */
diff --git a/include/kendryte/pll.h b/include/kendryte/pll.h
index 95b8494f40..16fd5a5b68 100644
--- a/include/kendryte/pll.h
+++ b/include/kendryte/pll.h
@@ -25,16 +25,6 @@
 #define K210_PLL_CLEAR_SLIP 2
 #define K210_PLL_TEST_OUT 3
 
-struct k210_pll {
-	struct clk clk;
-	void __iomem *reg; /* Base PLL register */
-	void __iomem *lock; /* Common PLL lock register */
-	u8 shift; /* Offset of bits in lock register */
-	u8 width; /* Width of lock bits to test against */
-};
-
-#define to_k210_pll(_clk) container_of(_clk, struct k210_pll, clk)
-
 struct k210_pll_config {
 	u8 r;
 	u8 f;
@@ -51,8 +41,18 @@ TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
 
 #endif
 
-extern const struct clk_ops k210_pll_ops;
+/**
+ * struct k210_clk_priv - K210 clock driver private data
+ * @base: The base address of the sysctl device
+ * @in0: The "in0" external oscillator
+ */
+struct k210_clk_priv {
+	void __iomem *base;
+	struct clk in0;
+};
 
-struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
-				     struct k210_pll *pll);
+ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, ulong rate_in);
+ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in);
+int k210_pll_enable(struct k210_clk_priv *priv, int id);
+int k210_pll_disable(struct k210_clk_priv *priv, int id);
 #endif /* K210_PLL_H */