diff options
author | Mario Six <mario.six@gdsys.cc> | 2019-01-21 11:17:25 +0300 |
---|---|---|
committer | Mario Six <mario.six@gdsys.cc> | 2019-05-20 14:50:34 +0300 |
commit | 9403fc41c71fc4146ab0e890ed90b28fc053791f (patch) | |
tree | 476b1573e45ae6c4ff0522442e87a551280f8509 /include | |
parent | 4bc97a3b816914d8b37e3d1ecac464e6193fd230 (diff) | |
download | u-boot-9403fc41c71fc4146ab0e890ed90b28fc053791f.tar.xz |
mpc83xx: Introduce ARCH_MPC831*
Replace CONFIG_MPC833* with proper CONFIG_ARCH_MPC833* Kconfig options.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include')
-rw-r--r-- | include/configs/MPC8313ERDB.h | 2 | ||||
-rw-r--r-- | include/configs/MPC8315ERDB.h | 2 | ||||
-rw-r--r-- | include/configs/ids8313.h | 3 | ||||
-rw-r--r-- | include/configs/ve8313.h | 2 | ||||
-rw-r--r-- | include/mpc83xx.h | 20 |
5 files changed, 10 insertions, 19 deletions
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index cfa5b56524..c5a8065d6a 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -13,8 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC831x 1 -#define CONFIG_MPC8313 1 #define CONFIG_MPC8313ERDB 1 #ifdef CONFIG_NAND diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 0ccf4acb82..b8506321af 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -22,8 +22,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC831x 1 /* MPC831x CPU family */ -#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ /* diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 7e4c497fe0..caa3dd1f1a 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -14,9 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC831x -#define CONFIG_MPC8313 - #define CONFIG_FSL_ELBC #define CONFIG_BOOT_RETRY_TIME 900 diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 85f678e5c4..791eac363b 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -16,8 +16,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC831x 1 -#define CONFIG_MPC8313 1 #define CONFIG_PCI_INDIRECT_BRIDGE 1 #define CONFIG_FSL_ELBC 1 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index e93f50d0b3..0da271b2f3 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -129,7 +129,7 @@ #define SPCR_TSEC2EP 0x00000003 #define SPCR_TSEC2EP_SHIFT (31-31) -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) /* SPCR bits - MPC8308, MPC831x and MPC837x specific */ /* TSEC data priority */ @@ -216,7 +216,7 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000 -#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) /* SICRL bits - MPC8313 specific */ #define SICRL_LBC 0x30000000 #define SICRL_UART 0x0C000000 @@ -248,7 +248,7 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001 -#elif defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8315) /* SICRL bits - MPC8315 specific */ #define SICRL_DMA_CH0 0xc0000000 #define SICRL_DMA_SPI 0x30000000 @@ -639,7 +639,7 @@ #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_2 0x00000000 @@ -765,7 +765,7 @@ #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 @@ -818,7 +818,7 @@ /* * RSR - Reset Status Register */ -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 @@ -965,7 +965,7 @@ #define SCCR_USBCM_2 0x00A00000 #define SCCR_USBCM_3 0x00F00000 -#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) /* TSEC1 bits are for TSEC2 as well */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -986,7 +986,7 @@ #define SCCR_USBDRCM_2 0x00200000 #define SCCR_USBDRCM_3 0x00300000 -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) /* SCCR bits - MPC8315/MPC8308 specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -1117,7 +1117,7 @@ */ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 -#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 @@ -1239,7 +1239,7 @@ #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) #define SDRAM_CFG_DBW_MASK 0x00180000 #define SDRAM_CFG_DBW_16 0x00100000 #define SDRAM_CFG_DBW_32 0x00080000 |