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authorTom Rini <trini@konsulko.com>2023-07-21 16:57:59 +0300
committerTom Rini <trini@konsulko.com>2023-07-21 16:57:59 +0300
commite7f7e2e1e22fd719a8810ba488a9451635b13d1b (patch)
tree0dda2ed98b772b44ae61b041d402f9618cd18670 /include
parente896279ac39ebb97f23e6132bf7668a61e1cd86b (diff)
parenta1190b4d6a9bf3a45038e3eba4a11de4be2b1cca (diff)
downloadu-boot-e7f7e2e1e22fd719a8810ba488a9451635b13d1b.tar.xz
Merge tag 'xilinx-for-v2023.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.10-rc1 v2 axi_emac: - Change return value if RX packet is not ready cadence_qspi: - Enable flash reset for Versal NET dt: - Various DT syncups with Linux kernel - SOM - reserved pmufw memory location fpga: - Add load event mtd: - Add missing dependency for FLASH_CFI_MTD spi/nand: - Minor cleanup in Xilinx drivers versal-net: - Prioritize boot device in boot_targets - Wire mini ospi/qspi/emmc configurations watchdog: - Use new versal-wwdt property xilinx: - fix sparse warnings in various places ps7_init* - add missing headers - consolidate code around zynqmp_mmio_read/write - switch to amd.com email zynqmp_clk: - Add handling for gem rx/tsu clocks zynq_gem: - Configure mdio clock at run time zynq: - Enable fdt overlay support zynq_sdhci: - Call dll reset only for ZynqMP SOCs
Diffstat (limited to 'include')
-rw-r--r--include/configs/xilinx_versal.h2
-rw-r--r--include/configs/xilinx_versal_mini.h4
-rw-r--r--include/configs/xilinx_versal_net.h19
-rw-r--r--include/configs/xilinx_zynqmp.h2
-rw-r--r--include/configs/xilinx_zynqmp_mini.h4
-rw-r--r--include/configs/xilinx_zynqmp_mini_nand.h4
-rw-r--r--include/event.h17
-rw-r--r--include/versalpl.h2
-rw-r--r--include/zynqmp_firmware.h2
-rw-r--r--include/zynqmppl.h2
10 files changed, 41 insertions, 17 deletions
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index e70acd93ba..a403999977 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@ -2,7 +2,7 @@
/*
* Configuration for Xilinx Versal
* (C) Copyright 2016 - 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*
* Based on Configuration for Xilinx ZynqMP
*/
diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h
index 23655a4752..628fd80baa 100644
--- a/include/configs/xilinx_versal_mini.h
+++ b/include/configs/xilinx_versal_mini.h
@@ -3,8 +3,8 @@
* Configuration for Xilinx Versal MINI configuration
*
* (C) Copyright 2018-2019 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
#ifndef __CONFIG_VERSAL_MINI_H
diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h
index 424ead038e..613cce46f9 100644
--- a/include/configs/xilinx_versal_net.h
+++ b/include/configs/xilinx_versal_net.h
@@ -76,20 +76,24 @@
# define BOOT_TARGET_DEVICES_DHCP(func)
#endif
-#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL_NET)
-# define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0)
+#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL)
+# define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0) func(XSPI, xspi, 1)
+# define BOOTENV_DEV_SHARED_XSPI \
+ "xspi_boot=sf probe $devnum_xspi:0 0 0 && " \
+ "sf read $scriptaddr $script_offset_f $script_size_f && " \
+ "echo XSPI: Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0"
#else
# define BOOT_TARGET_DEVICES_XSPI(func)
+# define BOOTENV_DEV_SHARED_XSPI
#endif
#define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \
- "bootcmd_xspi0=sf probe 0 0 0 && " \
- "sf read $scriptaddr $script_offset_f $script_size_f && " \
- "echo XSPI: Trying to boot script at ${scriptaddr} && " \
- "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0"
+ "bootcmd_" #devtypel #instance "=" \
+ "devnum_xspi=" #instance "; run " #devtypel "_boot\0" \
#define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \
- "xspi0 "
+ ""
#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na)
@@ -127,6 +131,7 @@
#define CFG_EXTRA_ENV_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
BOOTENV \
+ BOOTENV_DEV_SHARED_XSPI \
DFU_ALT_INFO
#endif
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 995427db63..74264b7bee 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -2,7 +2,7 @@
/*
* Configuration for Xilinx ZynqMP
* (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*
* Based on Configuration for Versatile Express
*/
diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h
index 9af0545664..8afccb7f73 100644
--- a/include/configs/xilinx_zynqmp_mini.h
+++ b/include/configs/xilinx_zynqmp_mini.h
@@ -3,8 +3,8 @@
* Configuration for Xilinx ZynqMP Flash utility
*
* (C) Copyright 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
#ifndef __CONFIG_ZYNQMP_MINI_H
diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h
index 1b6e26ee39..cf3747aab1 100644
--- a/include/configs/xilinx_zynqmp_mini_nand.h
+++ b/include/configs/xilinx_zynqmp_mini_nand.h
@@ -3,8 +3,8 @@
* Configuration for Xilinx ZynqMP Nand Flash utility
*
* (C) Copyright 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
#ifndef __CONFIG_ZYNQMP_MINI_NAND_H
diff --git a/include/event.h b/include/event.h
index fe41080fa6..daf44bf8a8 100644
--- a/include/event.h
+++ b/include/event.h
@@ -11,6 +11,7 @@
#define __event_h
#include <dm/ofnode_decl.h>
+#include <linux/types.h>
/**
* enum event_t - Types of events supported by U-Boot
@@ -31,6 +32,9 @@ enum event_t {
/* Init hooks */
EVT_MISC_INIT_F,
+ /* Fpga load hook */
+ EVT_FPGA_LOAD,
+
/* Device tree fixups before booting */
EVT_FT_FIXUP,
@@ -60,6 +64,19 @@ union event_data {
} dm;
/**
+ * struct event_fpga_load - fpga load event
+ *
+ * @buf: The buffer that was loaded into the fpga
+ * @bsize: The size of the buffer that was loaded into the fpga
+ * @result: Result of the load operation
+ */
+ struct event_fpga_load {
+ const void *buf;
+ size_t bsize;
+ int result;
+ } fpga_load;
+
+ /**
* struct event_ft_fixup - FDT fixup before booting
*
* @tree: tree to update
diff --git a/include/versalpl.h b/include/versalpl.h
index 0cc101be2f..7dae56b236 100644
--- a/include/versalpl.h
+++ b/include/versalpl.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2019 Xilinx, Inc,
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
#ifndef _VERSALPL_H_
diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
index 1192d5902d..18a87d2749 100644
--- a/include/zynqmp_firmware.h
+++ b/include/zynqmp_firmware.h
@@ -454,6 +454,8 @@ int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
u32 value);
int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
+int zynqmp_mmio_read(const u32 address, u32 *value);
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
/* Type of Config Object */
#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index acf75a8f07..3fd334a54d 100644
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2015 Xilinx, Inc,
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
#ifndef _ZYNQMPPL_H_