diff options
| author | Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> | 2020-07-15 20:19:03 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-07-29 17:37:11 +0300 |
| commit | 3edecba78413c46ccafedfb111f28eafbaf527d1 (patch) | |
| tree | e08013c97aa3194daa7eb1bb238c16d54ce43a23 /include | |
| parent | 3683df97dfba2533489313df3269ed7449123a97 (diff) | |
| download | u-boot-3edecba78413c46ccafedfb111f28eafbaf527d1.tar.xz | |
dt-bindings: memory: ns3: add ddr memory definition
Add ddr memory definitions.
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/memory/bcm-ns3-mc.h | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h index fe669e2f87..84795ec27a 100644 --- a/include/dt-bindings/memory/bcm-ns3-mc.h +++ b/include/dt-bindings/memory/bcm-ns3-mc.h @@ -7,7 +7,8 @@ #define DT_BINDINGS_BCM_NS3_MC_H /* - * Reserved Memory Map : SHMEM & TZDRAM. + * +--------+----------+ 0x8b000000 + * | NITRO CRASH DUMP | 32MB * +--------+----------+ 0x8d000000 * | SHMEM (NS) | 16 MB * +-------------------+ 0x8e000000 @@ -20,6 +21,10 @@ * +-------------------+ 0x8f100000 */ +#define BCM_NS3_MEM_NITRO_CRASH_START 0x8ae00000 +#define BCM_NS3_MEM_NITRO_CRASH_LEN 0x21fffff +#define BCM_NS3_MEM_NITRO_CRASH_SIZE 0x2200000 + #define BCM_NS3_MEM_SHARE_START 0x8d000000 #define BCM_NS3_MEM_SHARE_LEN 0x020fffff @@ -31,4 +36,28 @@ #define BCM_NS3_MEM_CRMU_PT_START 0x880000000 #define BCM_NS3_MEM_CRMU_PT_LEN 0x200000 +/* default memory starting address and length */ +#define BCM_NS3_MEM_START 0x80000000UL +#define BCM_NS3_MEM_LEN 0x80000000UL +#define BCM_NS3_MEM_END (BCM_NS3_MEM_START + BCM_NS3_MEM_LEN) + +/* memory starting address and length for BANK_1 */ +#define BCM_NS3_BANK_1_MEM_START 0x880000000UL +#define BCM_NS3_BANK_1_MEM_LEN 0x180000000UL + +/* memory layout information */ +#define BCM_NS3_DDR_INFO_BASE 0x8f220000 +#define BCM_NS3_DDR_INFO_RSVD_LEN 0x1000 +#define BCM_NS3_DDR_INFO_LEN 73 +#define BCM_NS3_DDR_INFO_SIG 0x42434d44 +#define BCM_NS3_MAX_NR_BANKS 4 + +#define BCM_NS3_GIC_LPI_BASE 0x8ad70000 +#define BCM_NS3_MEM_RSVE_START BCM_NS3_GIC_LPI_BASE +#define BCM_NS3_MEM_RSVE_END ((BCM_NS3_MEM_ELOG_START + \ + BCM_NS3_MEM_ELOG_LEN) - \ + BCM_NS3_MEM_RSVE_START) + +#define BCM_NS3_CRMU_PGT_START 0x880000000UL +#define BCM_NS3_CRMU_PGT_SIZE 0x100000 #endif |