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| author | Tom Rini <trini@konsulko.com> | 2020-08-04 18:07:38 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-08-04 18:07:38 +0300 |
| commit | 4d23857abd1f31b32d9c130697a821556916aec9 (patch) | |
| tree | e4e13165c6df05883fc740b98ed34d8be2d97208 /include | |
| parent | bb3694d5b14c891032864dcd44ae261fe595bb0c (diff) | |
| parent | ed50d3fae49b9dad58674b6609913beeac824e42 (diff) | |
| download | u-boot-4d23857abd1f31b32d9c130697a821556916aec9.tar.xz | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- add DM based reset driver for SiFive SoC's.
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/reset/sifive-fu540-prci.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/sifive-fu540-prci.h b/include/dt-bindings/reset/sifive-fu540-prci.h new file mode 100644 index 0000000000..89aa5b6679 --- /dev/null +++ b/include/dt-bindings/reset/sifive-fu540-prci.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Sifive, Inc. + * Author: Sagar Kadam <sagar.kadam@sifive.com> + */ + +#ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H +#define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H + +/* Reset indexes for use by device tree data and the PRCI driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 + +#endif |