Merge tag 'u-boot-imx-20201105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx for 2021.1
---------------------

- new boards : GE (new B1x5v2), phytec phyCORE-i.MX8MM
- converted doc to reST
- fixes for verdin-imx8mm (Toradex)
- fixes for i.MX thermal driver
- mx7ulp: Align the PLL_USB frequency
- mx53: primary/secondary bmode

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/741465284

2 files changed, 257 insertions, 0 deletions

diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h
new file mode 100644
index 0000000000..7db6afd88c
--- /dev/null
+++ b/include/configs/ge_b1x5v2.h
@@ -0,0 +1,127 @@
+/*
+ * GE B1x5v2
+ *
+ * Copyright 2018-2020 GE Inc.
+ * Copyright 2018-2020 Collabora Ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __GE_B1X5V2_CONFIG_H
+#define __GE_B1X5V2_CONFIG_H
+
+#include "mx6_common.h"
+
+#include "imx6_spl.h"
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.imx"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+/* PWM */
+#define CONFIG_IMX6_PWM_PER_CLK		66000000
+
+/* UART */
+#define CONFIG_MXC_UART_BASE		UART3_BASE
+
+#if CONFIG_MXC_UART_BASE == UART2_BASE
+/* UART2 requires CONFIG_DEBUG_UART_BASE=0x21e8000 */
+#define CONSOLE_DEVICE "ttymxc1" /* System on Module debug connector */
+#else
+/* UART3 requires CONFIG_DEBUG_UART_BASE=0x21ec000 */
+#define CONSOLE_DEVICE "ttymxc2" /* Base board debug connector */
+#endif
+
+/* USB */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
+#define CONFIG_USBD_HS
+
+/* Video */
+#define CONFIG_HIDE_LOGO_VERSION
+#define CONFIG_IMX_VIDEO_SKIP
+
+/* Memory */
+#define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Command definition */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"image=/boot/fitImage\0" \
+	"fdt_addr_r=0x18000000\0" \
+	"splash_addr_r=0x20000000\0" \
+	"mmcdev=2\0" \
+	"mmcpart=1\0" \
+	"console=console="CONSOLE_DEVICE",115200\0" \
+	"quiet=quiet loglevel=0\0" \
+	"rootdev=/dev/mmcblk1p\0" \
+	"setargs=setenv bootargs ${console} ${quiet} ${fsckforcerepair} " \
+		"bootcause=${bootcause} vt.global_cursor_default=0 vt.cur_default=1 " \
+		"root=${rootdev}${mmcpart} video=HDMI-A-1:${resolution} rootwait ro\0" \
+	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"showsplashscreen=load mmc ${mmcdev}:${mmcpart} ${splash_addr_r} /boot/splashscreen-${resolution}.bmp; " \
+		"bmp display ${splash_addr_r};\0" \
+	"setconfidx=" \
+		"if test \"${devicetype}\" = \"B105v2\"; then " \
+			"setenv confidx 1; " \
+		"elif test \"${devicetype}\" = \"B125v2\"; then " \
+			"setenv confidx 2; " \
+		"elif test \"${devicetype}\" = \"B155v2\"; then " \
+			"setenv confidx 3; " \
+		"elif test \"${devicetype}\" = \"B105Pv2\"; then " \
+			"setenv confidx 4; " \
+		"elif test \"${devicetype}\" = \"B125Pv2\"; then " \
+			"setenv confidx 5; " \
+		"fi;\0" \
+	"set_default_type=setenv devicetype B155v2; setenv resolution 1366x768;" \
+		"setenv fdtfile imx6dl-b155v2.dtb; run setconfidx;\0" \
+	"checkconfidx=env exists confidx || run set_default_type;\0" \
+	"checkfsckforcerepair=" \
+		"if test \"${bootcount}\" > \"3\" ; then " \
+			"setenv fsckforcerepair fsck.repair=1; " \
+		"fi;\0" \
+	"helix=run setconfidx; run checkconfidx; run checkfsckforcerepair; run setargs; " \
+		"regulator dev LED_VCC; regulator enable; " \
+		"regulator dev 5V0_AUDIO; regulator enable; " \
+		"bootm ${loadaddr}#conf@${confidx};\0" \
+	"failbootcmd=" \
+		"echo reached failbootcmd;" \
+		"cls; setcurs 5 4; " \
+		"lcdputs \"Monitor failed to start. Try again, or contact GE Service for support.\"; " \
+		"bootcount reset; \0" \
+	"hasfirstboot=" \
+		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+		"/boot/bootcause/firstboot;\0" \
+	"swappartitions=" \
+		"setexpr mmcpart 3 - ${mmcpart};\0" \
+	"doboot=" \
+		"echo Booting from mmc:${mmcdev}:${mmcpart} ...; " \
+		"run helix;\0" \
+	"altbootcmd=" \
+		"setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; " \
+		"run hasfirstboot || setenv mmcpart 0; " \
+		"if test ${mmcpart} != 0; then " \
+			"setenv bootcause REVERT; " \
+			"run swappartitions loadimage doboot; " \
+		"fi; " \
+		"run failbootcmd\0" \
+	"tryboot=" \
+		"setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; " \
+		"run loadimage || run swappartitions && run loadimage || " \
+		"setenv mmcpart 0 && echo MISSING IMAGE;" \
+		"run showsplashscreen; sleep 1; " \
+		"run doboot; run failbootcmd;\0" \
+
+#define CONFIG_BOOTCOMMAND "run tryboot;"
+
+#endif /* __GE_B1X5V2_CONFIG_H */
diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
new file mode 100644
index 0000000000..fd69dc41a8
--- /dev/null
+++ b/include/configs/phycore_imx8mm.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#ifndef __PHYCORE_IMX8MM_H
+#define __PHYCORE_IMX8MM_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+#define CONFIG_SPL_MAX_SIZE		(148 * SZ_1K)
+#define CONFIG_SYS_MONITOR_LEN		SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
+#define CONFIG_SYS_UBOOT_BASE \
+		(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK		0x920000
+#define CONFIG_SPL_BSS_START_ADDR	0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE		SZ_8K
+#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR		0x930000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"image=Image\0" \
+	"console=ttymxc2,115200\0" \
+	"fdt_addr=0x48000000\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"ipaddr=192.168.3.11\0" \
+	"serverip=192.168.3.10\0" \
+	"netmask=255.225.255.0\0" \
+	"ip_dyn=no\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=2\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if run loadfdt; then " \
+			"booti ${loadaddr} - ${fdt_addr}; " \
+		"else " \
+			"echo WARN: Cannot load the DT; " \
+		"fi;\0 " \
+	"nfsroot=/nfs\0" \
+	"netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
+		"nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+			"booti ${loadaddr} - ${fdt_addr}; " \
+		"else " \
+			"echo WARN: Cannot load the DT; " \
+		"fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadimage; then " \
+			"run mmcboot; " \
+		"else run netboot; " \
+		"fi; " \
+	"fi;"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x40480000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE	SZ_512K
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_MMCROOT			"/dev/mmcblk2p2"  /* USDHC3 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		SZ_32M
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+
+#define PHYS_SDRAM			SZ_1G
+#define PHYS_SDRAM_SIZE                 SZ_2G /* 2GB DDR */
+
+/* UART */
+#define CONFIG_MXC_UART_BASE		UART3_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		SZ_2K
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+/* USDHC */
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* I2C */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* ENET1 */
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define FEC_QUIRK_ENET_MAC
+#define IMX_FEC_BASE			0x30BE0000
+
+#endif /* __PHYCORE_IMX8MM_H */