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| author | Sagar Shrikant Kadam <sagar.kadam@sifive.com> | 2020-07-29 12:36:10 +0300 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-08-04 04:19:41 +0300 |
| commit | ef9f65f389de594ac045698004b71df3ab0d0aa7 (patch) | |
| tree | 9cb913215df4975c263416827758adef4307896d /include | |
| parent | 68941e3b2c217907a49aa66af8bb65729b913397 (diff) | |
| download | u-boot-ef9f65f389de594ac045698004b71df3ab0d0aa7.tar.xz | |
dt-bindings: prci: add indexes for reset signals available in prci
Add bit indexes for reset signals within the PRCI module
on FU540-C000 SoC.
The DDR and ethernet sub-system's have reset signals
indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/reset/sifive-fu540-prci.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/sifive-fu540-prci.h b/include/dt-bindings/reset/sifive-fu540-prci.h new file mode 100644 index 0000000000..89aa5b6679 --- /dev/null +++ b/include/dt-bindings/reset/sifive-fu540-prci.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Sifive, Inc. + * Author: Sagar Kadam <sagar.kadam@sifive.com> + */ + +#ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H +#define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H + +/* Reset indexes for use by device tree data and the PRCI driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 + +#endif |