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authorKautuk Consul <kconsul@ventanamicro.com>2022-12-07 14:42:35 +0300
committerLeo Yu-Chi Liang <ycliang@andestech.com>2022-12-08 10:15:58 +0300
commitae3527f088062dc4e117b0c4d4319e068f5e44cd (patch)
treefa08dd5ee80ff563cb71240bafd1ad0b23ff22cd /lib/Kconfig
parent1c03ab9f4bdf19d1ac7afc157788bd0102ccd969 (diff)
downloadu-boot-ae3527f088062dc4e117b0c4d4319e068f5e44cd.tar.xz
arch/riscv: add semihosting support for RISC-V
We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'lib/Kconfig')
-rw-r--r--lib/Kconfig10
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Kconfig b/lib/Kconfig
index b8833e0183..3c5a4ab386 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -73,7 +73,7 @@ config LIB_UUID
config SEMIHOSTING
bool "Support semihosting"
- depends on ARM
+ depends on ARM || RISCV
help
Semihosting is a method for a target to communicate with a host
debugger. It uses special instructions which the debugger will trap
@@ -86,7 +86,7 @@ config SEMIHOSTING
config SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails"
- depends on SEMIHOSTING && ARM64
+ depends on SEMIHOSTING && (ARM64 || RISCV)
default y
help
Normally, if U-Boot makes a semihosting call and no debugger is
@@ -96,7 +96,7 @@ config SEMIHOSTING_FALLBACK
config SPL_SEMIHOSTING
bool "Support semihosting in SPL"
- depends on SPL && ARM
+ depends on SPL && (ARM || RISCV)
help
Semihosting is a method for a target to communicate with a host
debugger. It uses special instructions which the debugger will trap
@@ -109,8 +109,8 @@ config SPL_SEMIHOSTING
config SPL_SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails in SPL"
- depends on SPL_SEMIHOSTING && ARM64
- select ARMV8_SPL_EXCEPTION_VECTORS
+ depends on SPL_SEMIHOSTING && (ARM64 || RISCV)
+ select ARMV8_SPL_EXCEPTION_VECTORS if ARM64
default y
help
Normally, if U-Boot makes a semihosting call and no debugger is