clk: ccf: mux: change the get_rate helper

The previous version of the get_rate helper does not work if the mux
clock parent is changed after the probe. This error has not been
detected because this condition has not been tested. The error occurs
because the set_parent helper does not change the parent of the clock
device but only the clock selection register. Since changing the parent
of a probed device can be tricky, the new version of the get_rate helper
provides the rate of the selected clock and not that of the parent.

Signed-off-by: Dario Binacchi <dariobin@libero.it>

1 files changed, 24 insertions, 0 deletions

diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c
index 242d2d756f..32bc4d2b8a 100644
--- a/test/dm/clk_ccf.c
+++ b/test/dm/clk_ccf.c
@@ -59,6 +59,18 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
 	rate = clk_get_parent_rate(clk);
 	ut_asserteq(rate, 60000000);
 
+	rate = clk_get_rate(clk);
+	ut_asserteq(rate, 60000000);
+
+	ret = clk_get_by_id(SANDBOX_CLK_PLL3_80M, &pclk);
+	ut_assertok(ret);
+
+	ret = clk_set_parent(clk, pclk);
+	ut_assertok(ret);
+
+	rate = clk_get_rate(clk);
+	ut_asserteq(rate, 80000000);
+
 	ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
 	ut_assertok(ret);
 	ut_asserteq_str("usdhc2_sel", clk->dev->name);
@@ -71,6 +83,18 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
 	ut_asserteq_str("pll3_80m", pclk->dev->name);
 	ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);
 
+	rate = clk_get_rate(clk);
+	ut_asserteq(rate, 80000000);
+
+	ret = clk_get_by_id(SANDBOX_CLK_PLL3_60M, &pclk);
+	ut_assertok(ret);
+
+	ret = clk_set_parent(clk, pclk);
+	ut_assertok(ret);
+
+	rate = clk_get_rate(clk);
+	ut_asserteq(rate, 60000000);
+
 	/* Test the composite of CCF */
 	ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
 	ut_assertok(ret);