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| author | Bin Meng <bmeng.cn@gmail.com> | 2018-08-03 11:14:41 +0300 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2018-08-08 14:49:31 +0300 |
| commit | dee4d752be4cbad2216f9285470588004c5d154e (patch) | |
| tree | 804df7b8615f9c498ebdea688da2cd8a711b7702 /test/dm/pci.c | |
| parent | 76330ae67db88350e2938b31d72f57b13f7234d3 (diff) | |
| download | u-boot-dee4d752be4cbad2216f9285470588004c5d154e.tar.xz | |
test: dm: pci: Test more than one PCI host controller
So far there is only one PCI host controller in the sandbox test
configuration. This is normally the case for x86, but it can be
common on other architectures like ARM/PPC to have more than one
PCI host controller in the system.
This updates the case to cover such scenario.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'test/dm/pci.c')
| -rw-r--r-- | test/dm/pci.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/test/dm/pci.c b/test/dm/pci.c index f2bd52a0b0..727ec342e2 100644 --- a/test/dm/pci.c +++ b/test/dm/pci.c @@ -26,6 +26,7 @@ static int dm_test_pci_busdev(struct unit_test_state *uts) struct udevice *bus; struct udevice *emul, *swap; + /* Test bus#0 and its devices */ ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus)); ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, &emul)); @@ -35,6 +36,16 @@ static int dm_test_pci_busdev(struct unit_test_state *uts) ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap)); ut_assert(device_active(swap)); + /* Test bus#1 and its devices */ + ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus)); + + ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 2, &emul)); + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap)); + ut_assert(device_active(swap)); + ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 3, &emul)); + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x0c, 0), &swap)); + ut_assert(device_active(swap)); + return 0; } DM_TEST(dm_test_pci_busdev, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); |