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authorTom Rini <trini@konsulko.com>2020-01-07 01:07:49 +0300
committerTom Rini <trini@konsulko.com>2020-01-07 01:07:49 +0300
commit5a8fa095cb848c60c630a83edf30d4fc46101e90 (patch)
tree66652768520899ddea6a24a608c1be4ed6ecfcde /test
parent0b0c6af38738f2c132cfd41a240889acaa031c8f (diff)
parent8fbbec12f7d2c18f8883f3371cfca74a98b5dd87 (diff)
downloadu-boot-5a8fa095cb848c60c630a83edf30d4fc46101e90.tar.xz
Merge branch 'next'
Bring in the following merges: commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87 Merge: 87f69f467a83 63618e71e89b Author: Tom Rini <trini@konsulko.com> Date: Fri Jan 3 09:48:47 2020 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support commit 87f69f467a8335b171c71bf217d2625d515acd7c Merge: c0912f9bbfb2 4466b9970319 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 24 08:18:19 2019 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next - Enable DM driver on ppc/km boards - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x, T104x, P4080, P2041, P2020, P1020, P3041 - Some updates in mpc85xx-ddr driver, km boards commit c0912f9bbfb26dd03d189953678691b799d35b6e Merge: 533c9f5714bd a1d6dc3f8407 Author: Tom Rini <trini@konsulko.com> Date: Wed Dec 18 07:20:19 2019 -0500 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral commit 533c9f5714bdba79dc6f2629284d4c1a08a611d1 Merge: 553cb0688782 033e18b47bd0 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 17 07:53:08 2019 -0500 Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next i2c: for next - misc: i2c_eeprom: Add partition support and add ability to query size of eeprom device and partitions - i2c common: add support for offset overflow in to address and add sandbox tests for it. commit 553cb06887825314e74a9bdac337467c77d1db88 Merge: f39abbbc531e b4f98b3b16ec Author: Tom Rini <trini@konsulko.com> Date: Thu Dec 12 08:18:59 2019 -0500 Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next buildman improvements including toolchain environment feature sandbox unicode support in serial
Diffstat (limited to 'test')
-rw-r--r--test/dm/Makefile3
-rw-r--r--test/dm/i2c.c113
-rw-r--r--test/dm/irq.c32
-rw-r--r--test/dm/p2sb.c28
-rw-r--r--test/dm/pmc.c33
-rw-r--r--test/py/conftest.py39
6 files changed, 222 insertions, 26 deletions
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 0c2fd5cb5e..a268783169 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o
obj-$(CONFIG_DM_I2C) += i2c.o
obj-$(CONFIG_SOUND) += i2s.o
+obj-y += irq.o
obj-$(CONFIG_LED) += led.o
obj-$(CONFIG_DM_MAILBOX) += mailbox.o
obj-$(CONFIG_DM_MMC) += mmc.o
@@ -32,10 +33,12 @@ obj-y += ofnode.o
obj-$(CONFIG_OSD) += osd.o
obj-$(CONFIG_DM_VIDEO) += panel.o
obj-$(CONFIG_DM_PCI) += pci.o
+obj-$(CONFIG_P2SB) += p2sb.o
obj-$(CONFIG_PCI_ENDPOINT) += pci_ep.o
obj-$(CONFIG_PCH) += pch.o
obj-$(CONFIG_PHY) += phy.o
obj-$(CONFIG_POWER_DOMAIN) += power-domain.o
+obj-$(CONFIG_ACPI_PMC) += pmc.o
obj-$(CONFIG_DM_PWM) += pwm.o
obj-$(CONFIG_RAM) += ram.o
obj-y += regmap.o
diff --git a/test/dm/i2c.c b/test/dm/i2c.c
index cbbd4aa29a..cadbb43b9e 100644
--- a/test/dm/i2c.c
+++ b/test/dm/i2c.c
@@ -15,6 +15,7 @@
#include <dm/test.h>
#include <dm/uclass-internal.h>
#include <dm/util.h>
+#include <hexdump.h>
#include <test/ut.h>
static const int busnum;
@@ -185,39 +186,123 @@ static int dm_test_i2c_offset(struct unit_test_state *uts)
ut_assertok(i2c_set_chip_offset_len(dev, 0));
ut_assertok(dm_i2c_write(dev, 10 /* ignored */, (uint8_t *)"AB", 2));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
- ut_assertok(memcmp(buf, "AB\0\0\0\0", sizeof(buf)));
+ ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
+ ut_asserteq(0, sanbox_i2c_eeprom_get_prev_offset(eeprom));
/* Offset length 1 */
sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
ut_assertok(i2c_set_chip_offset_len(dev, 1));
ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
+ ut_asserteq(2, sanbox_i2c_eeprom_get_prev_offset(eeprom));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
- ut_assertok(memcmp(buf, "ABAB\0", sizeof(buf)));
+ ut_asserteq_mem("ABAB\0", buf, sizeof(buf));
+ ut_asserteq(0, sanbox_i2c_eeprom_get_prev_offset(eeprom));
- /* Offset length 2 */
+ /* Offset length 2 boundary - check model wrapping */
sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
ut_assertok(i2c_set_chip_offset_len(dev, 2));
- ut_assertok(dm_i2c_write(dev, 0x210, (uint8_t *)"AB", 2));
- ut_assertok(dm_i2c_read(dev, 0x210, buf, 5));
- ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf)));
+ ut_assertok(dm_i2c_write(dev, 0xFF, (uint8_t *)"A", 1));
+ ut_asserteq(0xFF, sanbox_i2c_eeprom_get_prev_offset(eeprom));
+ ut_assertok(dm_i2c_write(dev, 0x100, (uint8_t *)"B", 1));
+ ut_asserteq(0x100, sanbox_i2c_eeprom_get_prev_offset(eeprom));
+ ut_assertok(dm_i2c_write(dev, 0x101, (uint8_t *)"C", 1));
+ ut_asserteq(0x101, sanbox_i2c_eeprom_get_prev_offset(eeprom));
+ ut_assertok(dm_i2c_read(dev, 0xFF, buf, 5));
+ ut_asserteq_mem("ABCAB", buf, sizeof(buf));
+ ut_asserteq(0xFF, sanbox_i2c_eeprom_get_prev_offset(eeprom));
- /* Offset length 3 */
+ /* Offset length 2 */
sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
ut_assertok(i2c_set_chip_offset_len(dev, 2));
- ut_assertok(dm_i2c_write(dev, 0x410, (uint8_t *)"AB", 2));
- ut_assertok(dm_i2c_read(dev, 0x410, buf, 5));
- ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf)));
+ ut_assertok(dm_i2c_write(dev, 0x2020, (uint8_t *)"AB", 2));
+ ut_assertok(dm_i2c_read(dev, 0x2020, buf, 5));
+ ut_asserteq_mem("AB\0\0\0", buf, sizeof(buf));
+ ut_asserteq(0x2020, sanbox_i2c_eeprom_get_prev_offset(eeprom));
+
+ /* Offset length 3 */
+ sandbox_i2c_eeprom_set_offset_len(eeprom, 3);
+ ut_assertok(i2c_set_chip_offset_len(dev, 3));
+ ut_assertok(dm_i2c_write(dev, 0x303030, (uint8_t *)"AB", 2));
+ ut_assertok(dm_i2c_read(dev, 0x303030, buf, 5));
+ ut_asserteq_mem("AB\0\0\0", buf, sizeof(buf));
+ ut_asserteq(0x303030, sanbox_i2c_eeprom_get_prev_offset(eeprom));
/* Offset length 4 */
+ sandbox_i2c_eeprom_set_offset_len(eeprom, 4);
+ ut_assertok(i2c_set_chip_offset_len(dev, 4));
+ ut_assertok(dm_i2c_write(dev, 0x40404040, (uint8_t *)"AB", 2));
+ ut_assertok(dm_i2c_read(dev, 0x40404040, buf, 5));
+ ut_asserteq_mem("AB\0\0\0", buf, sizeof(buf));
+ ut_asserteq(0x40404040, sanbox_i2c_eeprom_get_prev_offset(eeprom));
+
+ /* Restore defaults */
+ sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
+
+ return 0;
+}
+DM_TEST(dm_test_i2c_offset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_i2c_addr_offset(struct unit_test_state *uts)
+{
+ struct udevice *eeprom;
+ struct udevice *dev;
+ u8 buf[5];
+
+ ut_assertok(i2c_get_chip_for_busnum(busnum, chip, 1, &dev));
+
+ /* Do a transfer so we can find the emulator */
+ ut_assertok(dm_i2c_read(dev, 0, buf, 5));
+ ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
+
+ /* Offset length 0 */
+ sandbox_i2c_eeprom_set_offset_len(eeprom, 0);
+ sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0x3);
+ ut_assertok(i2c_set_chip_offset_len(dev, 0));
+ ut_assertok(i2c_set_chip_addr_offset_mask(dev, 0x3));
+ ut_assertok(dm_i2c_write(dev, 0x3, (uint8_t *)"AB", 2));
+ ut_assertok(dm_i2c_read(dev, 0x3, buf, 5));
+ ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
+ ut_asserteq(0x3, sanbox_i2c_eeprom_get_prev_offset(eeprom));
+ ut_asserteq(chip | 0x3, sanbox_i2c_eeprom_get_prev_addr(eeprom));
+
+ /* Offset length 1 */
+ sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
+ sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0x3);
+ ut_assertok(i2c_set_chip_offset_len(dev, 1));
+ ut_assertok(i2c_set_chip_addr_offset_mask(dev, 0x3));
+ ut_assertok(dm_i2c_write(dev, 0x310, (uint8_t *)"AB", 2));
+ ut_assertok(dm_i2c_read(dev, 0x310, buf, 5));
+ ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
+ ut_asserteq(0x310, sanbox_i2c_eeprom_get_prev_offset(eeprom));
+ ut_asserteq(chip | 0x3, sanbox_i2c_eeprom_get_prev_addr(eeprom));
+
+ /* Offset length 2 */
sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
+ sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0x3);
ut_assertok(i2c_set_chip_offset_len(dev, 2));
- ut_assertok(dm_i2c_write(dev, 0x420, (uint8_t *)"AB", 2));
- ut_assertok(dm_i2c_read(dev, 0x420, buf, 5));
- ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf)));
+ ut_assertok(i2c_set_chip_addr_offset_mask(dev, 0x3));
+ ut_assertok(dm_i2c_write(dev, 0x32020, (uint8_t *)"AB", 2));
+ ut_assertok(dm_i2c_read(dev, 0x32020, buf, 5));
+ ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
+ ut_asserteq(0x32020, sanbox_i2c_eeprom_get_prev_offset(eeprom));
+ ut_asserteq(chip | 0x3, sanbox_i2c_eeprom_get_prev_addr(eeprom));
+
+ /* Offset length 3 */
+ sandbox_i2c_eeprom_set_offset_len(eeprom, 3);
+ sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0x3);
+ ut_assertok(i2c_set_chip_offset_len(dev, 3));
+ ut_assertok(i2c_set_chip_addr_offset_mask(dev, 0x3));
+ ut_assertok(dm_i2c_write(dev, 0x3303030, (uint8_t *)"AB", 2));
+ ut_assertok(dm_i2c_read(dev, 0x3303030, buf, 5));
+ ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
+ ut_asserteq(0x3303030, sanbox_i2c_eeprom_get_prev_offset(eeprom));
+ ut_asserteq(chip | 0x3, sanbox_i2c_eeprom_get_prev_addr(eeprom));
/* Restore defaults */
sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
+ sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0);
return 0;
}
-DM_TEST(dm_test_i2c_offset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+DM_TEST(dm_test_i2c_addr_offset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/irq.c b/test/dm/irq.c
new file mode 100644
index 0000000000..726189c59f
--- /dev/null
+++ b/test/dm/irq.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for irq uclass
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <irq.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+/* Base test of the irq uclass */
+static int dm_test_irq_base(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_first_device_err(UCLASS_IRQ, &dev));
+
+ ut_asserteq(5, irq_route_pmc_gpio_gpe(dev, 4));
+ ut_asserteq(-ENOENT, irq_route_pmc_gpio_gpe(dev, 14));
+
+ ut_assertok(irq_set_polarity(dev, 4, true));
+ ut_asserteq(-EINVAL, irq_set_polarity(dev, 14, true));
+
+ ut_assertok(irq_snapshot_polarities(dev));
+ ut_assertok(irq_restore_polarities(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_irq_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/p2sb.c b/test/dm/p2sb.c
new file mode 100644
index 0000000000..ccb75cf375
--- /dev/null
+++ b/test/dm/p2sb.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for Primary-to-Sideband bus (P2SB)
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <p2sb.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+/* Base test of the PMC uclass */
+static int dm_test_p2sb_base(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ sandbox_set_enable_memio(true);
+ ut_assertok(uclass_get_device_by_name(UCLASS_AXI, "adder", &dev));
+ ut_asserteq(0x03000004, pcr_read32(dev, 4));
+ ut_asserteq(0x300, pcr_read16(dev, 6));
+ ut_asserteq(4, pcr_read8(dev, 4));
+
+ return 0;
+}
+DM_TEST(dm_test_p2sb_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/pmc.c b/test/dm/pmc.c
new file mode 100644
index 0000000000..1a222838ab
--- /dev/null
+++ b/test/dm/pmc.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for power-management controller uclass (PMC)
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <power/acpi_pmc.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+/* Base test of the PMC uclass */
+static int dm_test_pmc_base(struct unit_test_state *uts)
+{
+ struct acpi_pmc_upriv *upriv;
+ struct udevice *dev;
+
+ ut_assertok(uclass_first_device_err(UCLASS_ACPI_PMC, &dev));
+
+ ut_assertok(pmc_disable_tco(dev));
+ ut_assertok(pmc_init(dev));
+ ut_assertok(pmc_prev_sleep_state(dev));
+
+ /* Check some values to see that I/O works */
+ upriv = dev_get_uclass_priv(dev);
+ ut_asserteq(0x24, upriv->gpe0_sts[1]);
+ ut_asserteq(0x64, upriv->tco1_sts);
+
+ return 0;
+}
+DM_TEST(dm_test_pmc_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/py/conftest.py b/test/py/conftest.py
index bffee6b8a3..472dd0545d 100644
--- a/test/py/conftest.py
+++ b/test/py/conftest.py
@@ -83,6 +83,26 @@ def pytest_configure(config):
Returns:
Nothing.
"""
+ def parse_config(conf_file):
+ """Parse a config file, loading it into the ubconfig container
+
+ Args:
+ conf_file: Filename to load (within build_dir)
+
+ Raises
+ Exception if the file does not exist
+ """
+ dot_config = build_dir + '/' + conf_file
+ if not os.path.exists(dot_config):
+ raise Exception(conf_file + ' does not exist; ' +
+ 'try passing --build option?')
+
+ with open(dot_config, 'rt') as f:
+ ini_str = '[root]\n' + f.read()
+ ini_sio = io.StringIO(ini_str)
+ parser = configparser.RawConfigParser()
+ parser.read_file(ini_sio)
+ ubconfig.buildconfig.update(parser.items('root'))
global log
global console
@@ -157,18 +177,13 @@ def pytest_configure(config):
ubconfig.buildconfig = dict()
- for conf_file in ('.config', 'include/autoconf.mk'):
- dot_config = build_dir + '/' + conf_file
- if not os.path.exists(dot_config):
- raise Exception(conf_file + ' does not exist; ' +
- 'try passing --build option?')
-
- with open(dot_config, 'rt') as f:
- ini_str = '[root]\n' + f.read()
- ini_sio = io.StringIO(ini_str)
- parser = configparser.RawConfigParser()
- parser.read_file(ini_sio)
- ubconfig.buildconfig.update(parser.items('root'))
+ # buildman -k puts autoconf.mk in the rootdir, so handle this as well
+ # as the standard U-Boot build which leaves it in include/autoconf.mk
+ parse_config('.config')
+ if os.path.exists(build_dir + '/' + 'autoconf.mk'):
+ parse_config('autoconf.mk')
+ else:
+ parse_config('include/autoconf.mk')
ubconfig.test_py_dir = test_py_dir
ubconfig.source_dir = source_dir