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-rw-r--r--arch/riscv/dts/jh7100.dtsi14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/riscv/dts/jh7100.dtsi b/arch/riscv/dts/jh7100.dtsi
index 953b35e099..7489b53ea8 100644
--- a/arch/riscv/dts/jh7100.dtsi
+++ b/arch/riscv/dts/jh7100.dtsi
@@ -136,6 +136,20 @@
reg-names = "control";
};
+ wdog: wdog@12480000 {
+ compatible = "starfive,si5-wdt";
+ reg = <0x0 0x12480000 0x0 0x10000>;
+ interrupt-parent = <&plic>;
+ interrupts = <80>;
+ interrupt-names = "wdog";
+ clocks = <&clkgen JH7100_CLK_WDT_CORE>,
+ <&clkgen JH7100_CLK_WDTIMER_APB>;
+ clock-names = "core_clk", "apb_clk";
+ clock-frequency = <50000000>;
+ timeout-sec = <15>;
+ status = "okay";
+ };
+
plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";