diff options
28 files changed, 368 insertions, 186 deletions
@@ -3,7 +3,7 @@ VERSION = 2020 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = NAME = # *DOCUMENTATION* diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi index 7b1a9550e4..956d724979 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi @@ -4,125 +4,133 @@ */ &mu { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &clk { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &iomuxc { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio0 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio3 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio4 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio5 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio6 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio7 { - u-boot,dm-spl; + u-boot,dm-pre-proper; +}; + +&pd_dma { + u-boot,dm-pre-proper; +}; + +&pd_dma_lpuart1 { + u-boot,dm-pre-proper; }; &pd_conn { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_conn_sdch0 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_conn_sdch1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_conn_sdch2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio0 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio3 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio4 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio5 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio6 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio7 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &lpuart0 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &lpuart1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &lpuart2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &lpuart3 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &usdhc1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &usdhc2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &usdhc3 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi index 5b061f94ba..322429a98a 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi @@ -5,113 +5,125 @@ &{/imx8qx-pm} { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &mu { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &clk { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &iomuxc { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio0 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio3 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio4 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio5 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio6 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio7 { - u-boot,dm-spl; + u-boot,dm-pre-proper; +}; + +&pd_dma { + u-boot,dm-pre-proper; +}; + +&pd_dma_lpuart0 { + u-boot,dm-pre-proper; +}; + +&pd_dma_lpuart3 { + u-boot,dm-pre-proper; }; &pd_conn { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_conn_sdch0 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_conn_sdch1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_conn_sdch2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio0 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio3 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio4 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio5 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio6 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio7 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &lpuart3 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &usdhc1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &usdhc2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 80ee9c0a2c..f577d79afb 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -355,7 +355,6 @@ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; - cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; disable-wp; st,sig-dir; st,neg-edge; diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh index ad81d5ecab..dd1ca5ad3f 100755 --- a/arch/arm/mach-imx/mkimage_fit_atf.sh +++ b/arch/arm/mach-imx/mkimage_fit_atf.sh @@ -116,8 +116,8 @@ if [ -f $BL32 ]; then cat << __CONF_SECTION_EOF config@$cnt { description = "$(basename $dtname .dtb)"; - firmware = "atf@1"; - loadables = "uboot@1", "tee@1"; + firmware = "uboot@1"; + loadables = "atf@1", "tee@1"; fdt = "fdt@$cnt"; }; __CONF_SECTION_EOF @@ -125,8 +125,8 @@ else cat << __CONF_SECTION1_EOF config@$cnt { description = "$(basename $dtname .dtb)"; - firmware = "atf@1"; - loadables = "uboot@1"; + firmware = "uboot@1"; + loadables = "atf@1"; fdt = "fdt@$cnt"; }; __CONF_SECTION1_EOF diff --git a/arch/mips/cpu/time.c b/arch/mips/cpu/time.c index a1508e3b88..e0c1868b8c 100644 --- a/arch/mips/cpu/time.c +++ b/arch/mips/cpu/time.c @@ -13,7 +13,7 @@ unsigned long notrace timer_read_counter(void) return read_c0_count(); } -ulong notrace get_tbclk(void) +ulong notrace __weak get_tbclk(void) { return CONFIG_SYS_MIPS_TIMER_FREQ; } diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 589bc651f9..24a72d9c97 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -11,5 +11,6 @@ obj-y += stack.o obj-y += traps.o obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_CMD_GO) += boot.o lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c new file mode 100644 index 0000000000..db862f6379 --- /dev/null +++ b/arch/mips/lib/boot.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Stefan Roese <sr@denx.de> + */ + +#include <common.h> +#include <command.h> +#include <cpu_func.h> + +DECLARE_GLOBAL_DATA_PTR; + +unsigned long do_go_exec(ulong (*entry)(int, char * const []), + int argc, char * const argv[]) +{ + /* + * Flush cache before jumping to application. Let's flush the + * whole SDRAM area, since we don't know the size of the image + * that was loaded. + */ + flush_cache(gd->bd->bi_memstart, gd->ram_top - gd->bd->bi_memstart); + + return entry(argc, argv); +} diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 502956d050..1a8c87d094 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -141,7 +141,7 @@ ops_done: instruction_hazard_barrier(); } -void flush_dcache_range(ulong start_addr, ulong stop) +void __weak flush_dcache_range(ulong start_addr, ulong stop) { unsigned long lsize = dcache_line_size(); unsigned long slsize = scache_line_size(); diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index ac75d51da5..3ee589891b 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -7,6 +7,7 @@ #include <asm/io.h> #include <asm/types.h> +#include <asm/mipsregs.h> #include <mach/tlb.h> #include <mach/ddr.h> @@ -53,7 +54,6 @@ void vcoreiii_tlb_init(void) MMU_REGIO_RW); #endif -#if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO /* * If U-Boot is located in NOR then we want to be able to use * the data cache in order to boot in a decent duration @@ -71,9 +71,10 @@ void vcoreiii_tlb_init(void) create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, MSCC_ATTRIB2); - /* Enable caches by clearing the bit ERL, which is set on reset */ - write_c0_status(read_c0_status() & ~BIT(2)); -#endif /* CONFIG_SYS_TEXT_BASE */ + /* Enable mapping (using TLB) kuseg by clearing the bit ERL, + * which is set on reset. + */ + write_c0_status(read_c0_status() & ~ST0_ERL); } int mach_cpu_init(void) diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c index c43f7a585b..72c70c9e84 100644 --- a/arch/mips/mach-mscc/dram.c +++ b/arch/mips/mach-mscc/dram.c @@ -31,7 +31,7 @@ static inline int vcoreiii_train_bytelane(void) int vcoreiii_ddr_init(void) { - int res; + register int res; if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) & ICPU_MEMCTRL_STAT_INIT_DONE)) { @@ -40,20 +40,19 @@ int vcoreiii_ddr_init(void) if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane()) hal_vcoreiii_ddr_failed(); } -#if (CONFIG_SYS_TEXT_BASE != 0x20000000) + res = dram_check(); if (res == 0) hal_vcoreiii_ddr_verified(); else hal_vcoreiii_ddr_failed(); - /* Clear boot-mode and read-back to activate/verify */ + /* Remap DDR to kuseg: Clear boot-mode */ clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, ICPU_GENERAL_CTRL_BOOT_MODE_ENA); + /* - and read-back to activate/verify */ readl(BASE_CFG + ICPU_GENERAL_CTRL); -#else - res = 0; -#endif + return res; } @@ -66,9 +65,6 @@ int print_cpuinfo(void) int dram_init(void) { - while (vcoreiii_ddr_init()) - ; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; return 0; } diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index d1f4287f65..bf75e52ec3 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -435,16 +435,12 @@ static inline void hal_vcoreiii_ddr_failed(void) reset = KSEG0ADDR(_machine_restart); icache_lock((void *)reset, 128); asm volatile ("jr %0"::"r" (reset)); - - panic("DDR init failed\n"); } #else /* JR2 || ServalT */ static inline void hal_vcoreiii_ddr_failed(void) { writel(0, BASE_CFG + ICPU_RESET); writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST); - - panic("DDR init failed\n"); } #endif diff --git a/arch/mips/mach-mscc/lowlevel_init.S b/arch/mips/mach-mscc/lowlevel_init.S index dfbe06766c..91f29ae252 100644 --- a/arch/mips/mach-mscc/lowlevel_init.S +++ b/arch/mips/mach-mscc/lowlevel_init.S @@ -8,6 +8,7 @@ .set noreorder .extern vcoreiii_tlb_init + .extern vcoreiii_ddr_init #ifdef CONFIG_SOC_LUTON .extern pll_init #endif @@ -17,14 +18,28 @@ LEAF(lowlevel_init) * As we have no stack yet, we can assume the restricted * luxury of the sX-registers without saving them */ - move s0,ra + + /* Modify ra/s0 such we return to physical NOR location */ + li t0, 0x0fffffff + li t1, CONFIG_SYS_TEXT_BASE + and s0, ra, t0 + add s0, s0, t1 jal vcoreiii_tlb_init nop + #ifdef CONFIG_SOC_LUTON jal pll_init nop #endif + + /* Initialize DDR controller to enable stack/gd/heap */ +0: + jal vcoreiii_ddr_init + nop + bnez v0, 0b /* Retry on error */ + nop + jr s0 nop END(lowlevel_init) diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index f04b749311..d11401ecab 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -354,12 +354,15 @@ int board_phy_config(struct phy_device *phydev) int setup_fec(void) { int ret; + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; /* provide the PHY clock from the i.MX 6 */ ret = enable_fec_anatop_clock(0, ENET_50MHZ); if (ret) return ret; + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + return 0; } @@ -41,7 +41,7 @@ static int do_dm_dump_devres(cmd_tbl_t *cmdtp, int flag, int argc, } static int do_dm_dump_drivers(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) + char * const argv[]) { dm_dump_drivers(); @@ -94,5 +94,5 @@ U_BOOT_CMD( "tree Dump driver model tree ('*' = activated)\n" "dm uclass Dump list of instances for each uclass\n" "dm devres Dump list of device resources for each device\n" - "dm drivers Dump list of drivers and their compatible strings\n" + "dm drivers Dump list of drivers and their compatible strings" ); diff --git a/common/usb.c b/common/usb.c index 349e838f1d..686f09a77d 100644 --- a/common/usb.c +++ b/common/usb.c @@ -172,6 +172,12 @@ int usb_detect_change(void) return change; } +/* Lock or unlock async schedule on the controller */ +__weak int usb_lock_async(struct usb_device *dev, int lock) +{ + return 0; +} + /* * disables the asynch behaviour of the control message. This is used for data * transfers that uses the exclusiv access to the control and bulk messages. diff --git a/common/usb_storage.c b/common/usb_storage.c index 097b6729c1..b291ac55d1 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -1157,6 +1157,7 @@ static unsigned long usb_stor_read(struct blk_desc *block_dev, lbaint_t blknr, ss = (struct us_data *)udev->privptr; usb_disable_asynch(1); /* asynch transfer not allowed */ + usb_lock_async(udev, 1); srb->lun = block_dev->lun; buf_addr = (uintptr_t)buffer; start = blknr; @@ -1195,6 +1196,7 @@ retry_it: debug("usb_read: end startblk " LBAF ", blccnt %x buffer %lx\n", start, smallblks, buf_addr); + usb_lock_async(udev, 0); usb_disable_asynch(0); /* asynch transfer allowed */ if (blkcnt >= ss->max_xfer_blk) debug("\n"); @@ -1239,6 +1241,7 @@ static unsigned long usb_stor_write(struct blk_desc *block_dev, lbaint_t blknr, ss = (struct us_data *)udev->privptr; usb_disable_asynch(1); /* asynch transfer not allowed */ + usb_lock_async(udev, 1); srb->lun = block_dev->lun; buf_addr = (uintptr_t)buffer; @@ -1280,6 +1283,7 @@ retry_it: debug("usb_write: end startblk " LBAF ", blccnt %x buffer %lx\n", start, smallblks, buf_addr); + usb_lock_async(udev, 0); usb_disable_asynch(0); /* asynch transfer allowed */ if (blkcnt >= ss->max_xfer_blk) debug("\n"); diff --git a/doc/board/emulation/qemu-mips.rst b/doc/board/emulation/qemu-mips.rst index 529a908b55..f206039f54 100644 --- a/doc/board/emulation/qemu-mips.rst +++ b/doc/board/emulation/qemu-mips.rst @@ -25,37 +25,45 @@ Example usage Using u-boot.bin as ROM (replaces Qemu monitor): -32 bit, big endian:: +32 bit, big endian - # make qemu_mips - # qemu-system-mips -M mips -bios u-boot.bin -nographic +.. code-block:: bash -32 bit, little endian:: + make qemu_mips + qemu-system-mips -M mips -bios u-boot.bin -nographic - # make qemu_mipsel - # qemu-system-mipsel -M mips -bios u-boot.bin -nographic +32 bit, little endian -64 bit, big endian:: +.. code-block:: bash - # make qemu_mips64 - # qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic + make qemu_mipsel + qemu-system-mipsel -M mips -bios u-boot.bin -nographic -64 bit, little endian:: +64 bit, big endian - # make qemu_mips64el - # qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic +.. code-block:: bash + + make qemu_mips64 + qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic + +64 bit, little endian + +.. code-block:: bash + + make qemu_mips64el + qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic or using u-boot.bin from emulated flash: -if you use a qemu version after commit 4224 +if you use a QEMU version after commit 4224 -.. code-block:: none +.. code-block:: bash - create image: - # dd of=flash bs=1k count=4k if=/dev/zero - # dd of=flash bs=1k conv=notrunc if=u-boot.bin - start it (see above): - # qemu-system-mips[64][el] [-cpu MIPS64R2-generic] -M mips -pflash flash -nographic + # create image: + dd of=flash bs=1k count=4k if=/dev/zero + dd of=flash bs=1k conv=notrunc if=u-boot.bin + # start it (see above): + qemu-system-mips[64][el] [-cpu MIPS64R2-generic] -M mips -pflash flash -nographic Download kernel + initrd ^^^^^^^^^^^^^^^^^^^^^^^^ @@ -75,61 +83,63 @@ you can downland:: Generate uImage ^^^^^^^^^^^^^^^ -.. code-block:: none +.. code-block:: bash - # tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage + tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage Copy uImage to Flash ^^^^^^^^^^^^^^^^^^^^ -.. code-block:: none +.. code-block:: bash - # dd if=uImage bs=1k conv=notrunc seek=224 of=flash + dd if=uImage bs=1k conv=notrunc seek=224 of=flash Generate Ide Disk ^^^^^^^^^^^^^^^^^ -.. code-block:: none +.. code-block:: bash - # dd of=ide bs=1k cout=100k if=/dev/zero + dd of=ide bs=1k count=100k if=/dev/zero - # sfdisk -C 261 -d ide - # partition table of ide + # Create partion table + sudo sfdisk ide << EOF + label: dos + label-id: 0x6fe3a999 + device: image unit: sectors - - ide1 : start= 63, size= 32067, Id=83 - ide2 : start= 32130, size= 32130, Id=83 - ide3 : start= 64260, size= 4128705, Id=83 - ide4 : start= 0, size= 0, Id= 0 + image1 : start= 63, size= 32067, Id=83 + image2 : start= 32130, size= 32130, Id=83 + image3 : start= 64260, size= 4128705, Id=83 + EOF Copy to ide ^^^^^^^^^^^ -.. code-block:: none +.. code-block:: bash - # dd if=uImage bs=512 conv=notrunc seek=63 of=ide + dd if=uImage bs=512 conv=notrunc seek=63 of=ide Generate ext2 on part 2 on Copy uImage and initrd.gz ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. code-block:: none +.. code-block:: bash # Attached as loop device ide offset = 32130 * 512 - # losetup -o 16450560 -f ide + sudo losetup -o 16450560 /dev/loop0 ide # Format as ext2 ( arg2 : nb blocks) - # mke2fs /dev/loop0 16065 - # losetup -d /dev/loop0 + sudo mkfs.ext2 /dev/loop0 16065 + sudo losetup -d /dev/loop0 # Mount and copy uImage and initrd.gz to it - # mount -o loop,offset=16450560 -t ext2 ide /mnt - # mkdir /mnt/boot - # cp {initrd.gz,uImage} /mnt/boot/ + sudo mount -o loop,offset=16450560 -t ext2 ide /mnt + sudo mkdir /mnt/boot + cp {initrd.gz,uImage} /mnt/boot/ # Umount it - # umount /mnt + sudo umount /mnt Set Environment ^^^^^^^^^^^^^^^ -.. code-block:: none +.. code-block:: bash setenv rd_start 0x80800000 setenv rd_size 2663940 @@ -157,9 +167,11 @@ Set Environment setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}' setenv bootcmd 'run boot_tftp_flash' -Now you can boot from flash, ide, ide+ext2 and tfp:: +Now you can boot from flash, ide, ide+ext2 and tfp + +.. code-block:: bash - # qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide + qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide How to debug U-Boot @@ -168,9 +180,9 @@ How to debug U-Boot In order to debug U-Boot you need to start qemu with gdb server support (-s) and waiting the connection to start the CPU (-S) -.. code-block:: none +.. code-block:: bash - # qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide + qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide in an other console you start gdb @@ -182,7 +194,7 @@ by connecting to the gdb server localhost:1234 .. code-block:: none - # mipsel-unknown-linux-gnu-gdb u-boot + $ mipsel-unknown-linux-gnu-gdb u-boot GNU gdb 6.6 Copyright (C) 2006 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c index affeb31fc2..b7eed948a5 100644 --- a/drivers/clk/altera/clk-arria10.c +++ b/drivers/clk/altera/clk-arria10.c @@ -274,6 +274,8 @@ static int socfpga_a10_clk_bind(struct udevice *dev) static int socfpga_a10_clk_probe(struct udevice *dev) { struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev); + struct socfpga_a10_clk_platdata *pplat; + struct udevice *pdev; const void *fdt = gd->fdt_blob; int offset = dev_of_offset(dev); @@ -281,6 +283,21 @@ static int socfpga_a10_clk_probe(struct udevice *dev) socfpga_a10_handoff_workaround(dev); + if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) { + plat->regs = devfdt_get_addr(dev); + } else { + pdev = dev_get_parent(dev); + if (!pdev) + return -ENODEV; + + pplat = dev_get_platdata(pdev); + if (!pplat) + return -EINVAL; + + plat->ctl_reg = dev_read_u32_default(dev, "reg", 0x0); + plat->regs = pplat->regs; + } + if (!fdt_node_check_compatible(fdt, offset, "altr,socfpga-a10-pll-clock")) { /* Main PLL has 3 upstream clock */ @@ -304,29 +321,8 @@ static int socfpga_a10_clk_probe(struct udevice *dev) static int socfpga_a10_ofdata_to_platdata(struct udevice *dev) { struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev); - struct socfpga_a10_clk_platdata *pplat; - struct udevice *pdev; - const void *fdt = gd->fdt_blob; unsigned int divreg[3], gatereg[2]; - int ret, offset = dev_of_offset(dev); - u32 regs; - - regs = dev_read_u32_default(dev, "reg", 0x0); - - if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) { - plat->regs = devfdt_get_addr(dev); - } else { - pdev = dev_get_parent(dev); - if (!pdev) - return -ENODEV; - - pplat = dev_get_platdata(pdev); - if (!pplat) - return -EINVAL; - - plat->ctl_reg = regs; - plat->regs = pplat->regs; - } + int ret; plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK; diff --git a/drivers/core/dump.c b/drivers/core/dump.c index e73ebeabcc..cb8a25b9ad 100644 --- a/drivers/core/dump.c +++ b/drivers/core/dump.c @@ -107,11 +107,16 @@ void dm_dump_drivers(void) puts("Driver Compatible\n"); puts("--------------------------------\n"); for (entry = d; entry < d + n_ents; entry++) { - for (match = entry->of_match; match->compatible; match++) - printf("%-20.20s %s\n", - match == entry->of_match ? entry->name : "", - match->compatible); - if (match == entry->of_match) - printf("%-20.20s\n", entry->name); + match = entry->of_match; + + printf("%-20.20s", entry->name); + if (match) { + printf(" %s", match->compatible); + match++; + } + printf("\n"); + + for (; match && match->compatible; match++) + printf("%-20.20s %s\n", "", match->compatible); } } diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 952b296dd8..a9b085db8c 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -370,8 +370,6 @@ step2: debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); #endif /* part 1 of the workaound */ - /* Always start in self-refresh, clear after MEM_EN */ - setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); /* * 500 painful micro-seconds must elapse between @@ -384,6 +382,8 @@ step2: #ifdef CONFIG_DEEP_SLEEP if (is_warm_boot()) { + /* enter self-refresh */ + setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); /* do board specific memory setup */ board_mem_sleep_setup(); temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); @@ -395,10 +395,6 @@ step2: out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("sync;isync"); - /* Exit self-refresh after DDR conf as some ddr memories can fail. */ - clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); - asm volatile("sync;isync"); - total_gb_size_per_controller = 0; for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (!(regs->cs[i].config & 0x80000000)) @@ -548,4 +544,9 @@ step2: clrbits_be32(&ddr->sdram_cfg, 0x2); } #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) + /* exit self-refresh */ + clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); +#endif } diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 1cc02052f5..1edb344d0f 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -298,6 +298,51 @@ static void ehci_update_endpt2_dev_n_port(struct usb_device *udev, QH_ENDPT2_HUBADDR(hubaddr)); } +static int ehci_enable_async(struct ehci_ctrl *ctrl) +{ + u32 cmd; + int ret; + + /* Enable async. schedule. */ + cmd = ehci_readl(&ctrl->hcor->or_usbcmd); + if (cmd & CMD_ASE) + return 0; + + cmd |= CMD_ASE; + ehci_writel(&ctrl->hcor->or_usbcmd, cmd); + + ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS, + 100 * 1000); + if (ret < 0) + printf("EHCI fail timeout STS_ASS set\n"); + + return ret; +} + +static int ehci_disable_async(struct ehci_ctrl *ctrl) +{ + u32 cmd; + int ret; + + if (ctrl->async_locked) + return 0; + + /* Disable async schedule. */ + cmd = ehci_readl(&ctrl->hcor->or_usbcmd); + if (!(cmd & CMD_ASE)) + return 0; + + cmd &= ~CMD_ASE; + ehci_writel(&ctrl->hcor->or_usbcmd, cmd); + + ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0, + 100 * 1000); + if (ret < 0) + printf("EHCI fail timeout STS_ASS reset\n"); + + return ret; +} + static int ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, int length, struct devrequest *req) @@ -311,7 +356,6 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, uint32_t *tdp; uint32_t endpt, maxpacket, token, usbsts, qhtoken; uint32_t c, toggle; - uint32_t cmd; int timeout; int ret = 0; struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); @@ -556,19 +600,9 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, usbsts = ehci_readl(&ctrl->hcor->or_usbsts); ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f)); - /* Enable async. schedule. */ - cmd = ehci_readl(&ctrl->hcor->or_usbcmd); - if (!(cmd & CMD_ASE)) { - cmd |= CMD_ASE; - ehci_writel(&ctrl->hcor->or_usbcmd, cmd); - - ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS, - 100 * 1000); - if (ret < 0) { - printf("EHCI fail timeout STS_ASS set\n"); - goto fail; - } - } + ret = ehci_enable_async(ctrl); + if (ret) + goto fail; /* Wait for TDs to be processed. */ ts = get_timer(0); @@ -611,6 +645,10 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) printf("EHCI timed out on TD - token=%#x\n", token); + ret = ehci_disable_async(ctrl); + if (ret) + goto fail; + if (!(QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_ACTIVE)) { debug("TOKEN=%#x\n", qhtoken); switch (QT_TOKEN_GET_STATUS(qhtoken) & @@ -1512,6 +1550,16 @@ static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe, return result; } +static int _ehci_lock_async(struct ehci_ctrl *ctrl, int lock) +{ + ctrl->async_locked = lock; + + if (lock) + return 0; + + return ehci_disable_async(ctrl); +} + #if !CONFIG_IS_ENABLED(DM_USB) int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int length) @@ -1549,6 +1597,13 @@ int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) { return _ehci_destroy_int_queue(dev, queue); } + +int usb_lock_async(struct usb_device *dev, int lock) +{ + struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); + + return _ehci_lock_async(ctrl, lock); +} #endif #if CONFIG_IS_ENABLED(DM_USB) @@ -1612,6 +1667,13 @@ static int ehci_get_max_xfer_size(struct udevice *dev, size_t *size) return 0; } +static int ehci_lock_async(struct udevice *dev, int lock) +{ + struct ehci_ctrl *ctrl = dev_get_priv(dev); + + return _ehci_lock_async(ctrl, lock); +} + int ehci_register(struct udevice *dev, struct ehci_hccr *hccr, struct ehci_hcor *hcor, const struct ehci_ops *ops, uint tweaks, enum usb_init_type init) @@ -1678,6 +1740,7 @@ struct dm_usb_ops ehci_usb_ops = { .poll_int_queue = ehci_poll_int_queue, .destroy_int_queue = ehci_destroy_int_queue, .get_max_xfer_size = ehci_get_max_xfer_size, + .lock_async = ehci_lock_async, }; #endif diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 6c359af90c..66c1d61dbf 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -255,6 +255,7 @@ struct ehci_ctrl { int periodic_schedules; int ntds; bool has_fsl_erratum_a005275; /* Freescale HS silicon quirk */ + bool async_locked; struct ehci_ops ops; void *priv; /* client's private data */ }; diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index 8521651588..5e423012df 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -22,6 +22,17 @@ struct usb_uclass_priv { int companion_device_count; }; +int usb_lock_async(struct usb_device *udev, int lock) +{ + struct udevice *bus = udev->controller_dev; + struct dm_usb_ops *ops = usb_get_ops(bus); + + if (!ops->lock_async) + return -ENOSYS; + + return ops->lock_async(bus, lock); +} + int usb_disable_asynch(int disable) { int old_value = asynch_allowed; diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index b1726b1d88..e7d35ed648 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -81,8 +81,8 @@ "fdt_addr_r=0x83000000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_addr_r=0x83000000\0" \ - "ramdiskaddr=0x83000000\0" \ + "ramdisk_addr_r=0x83100000\0" \ + "ramdiskaddr=0x83100000\0" \ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ BOOTENV diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index e69456ef7c..6a2f80c2fb 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -39,7 +39,8 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - SZ_4M) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/usb.h b/include/usb.h index efb67ea33f..22f6088fe6 100644 --- a/include/usb.h +++ b/include/usb.h @@ -269,6 +269,7 @@ int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len, int *actual_length, int timeout); int usb_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval, bool nonblock); +int usb_lock_async(struct usb_device *dev, int lock); int usb_disable_asynch(int disable); int usb_maxpacket(struct usb_device *dev, unsigned long pipe); int usb_get_configuration_no(struct usb_device *dev, int cfgno, @@ -791,6 +792,16 @@ struct dm_usb_ops { * in a USB transfer. USB class driver needs to be aware of this. */ int (*get_max_xfer_size)(struct udevice *bus, size_t *size); + + /** + * lock_async() - Keep async schedule after a transfer + * + * It may be desired to keep the asynchronous schedule running even + * after a transfer finishes, usually when doing multiple transfers + * back-to-back. This callback allows signalling the USB controller + * driver to do just that. + */ + int (*lock_async)(struct udevice *udev, int lock); }; #define usb_get_ops(dev) ((struct dm_usb_ops *)(dev)->driver->ops) diff --git a/test/py/tests/test_dm.py b/test/py/tests/test_dm.py new file mode 100644 index 0000000000..f6fbf8ba4c --- /dev/null +++ b/test/py/tests/test_dm.py @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2020 Sean Anderson + +import pytest + +@pytest.mark.buildconfigspec('cmd_dm') +def test_dm_drivers(u_boot_console): + """Test that each driver in `dm tree` is also listed in `dm drivers`.""" + response = u_boot_console.run_command('dm tree') + driver_index = response.find('Driver') + assert driver_index != -1 + drivers = (line[driver_index:].split()[0] + for line in response[:-1].split('\n')[2:]) + + response = u_boot_console.run_command('dm drivers') + for driver in drivers: + assert driver in response |