diff options
| -rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 47 | ||||
| -rw-r--r-- | drivers/clk/starfive/clk-jh7110.c | 631 | ||||
| -rw-r--r-- | include/dt-bindings/clock/starfive-jh7110-clkgen.h | 57 | ||||
| -rw-r--r-- | include/dt-bindings/clock/starfive-jh7110-vout.h | 66 |
4 files changed, 536 insertions, 265 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 0188f89780..fd198d01ac 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -8,7 +8,6 @@ #include "jh7110_clk.dtsi" #include <dt-bindings/reset/starfive-jh7110.h> #include <dt-bindings/clock/starfive-jh7110-clkgen.h> -#include <dt-bindings/clock/starfive-jh7110-vout.h> #include <dt-bindings/clock/starfive-jh7110-isp.h> / { @@ -164,6 +163,52 @@ #clock-cells = <1>; ranges; + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmcounters = <0x5 0x06 0x18 + 0x08 0x09 0x18>; + riscv,event-to-mhpmevent = <0x05 0x00000000 0x4000 + 0x06 0x00000000 0x4001 + 0x08 0x00000000 0x4008 + 0x09 0x00000000 0x4009>; + riscv,raw-event-to-mhpmcounters = + <0x00000000 0x100 0xffffffff 0xffffffff 0x18 + 0x00000000 0x200 0xffffffff 0xffffffff 0x18 + 0x00000000 0x400 0xffffffff 0xffffffff 0x18 + 0x00000000 0x800 0xffffffff 0xffffffff 0x18 + 0x00000000 0x1000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x2000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x4000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x8000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x10000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x20000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x40000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x80000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x100000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x200000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x400000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x800000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x1000000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x2000000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x101 0xffffffff 0xffffffff 0x18 + 0x00000000 0x201 0xffffffff 0xffffffff 0x18 + 0x00000000 0x401 0xffffffff 0xffffffff 0x18 + 0x00000000 0x801 0xffffffff 0xffffffff 0x18 + 0x00000000 0x1001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x2001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x4001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x8001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x10001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x20001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x40001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x102 0xffffffff 0xffffffff 0x18 + 0x00000000 0x202 0xffffffff 0xffffffff 0x18 + 0x00000000 0x402 0xffffffff 0xffffffff 0x18 + 0x00000000 0x802 0xffffffff 0xffffffff 0x18 + 0x00000000 0x1002 0xffffffff 0xffffffff 0x18 + 0x00000000 0x2002 0xffffffff 0xffffffff 0x18>; + }; + cachectrl: cache-controller@2010000 { compatible = "sifive,fu740-c000-ccache", "cache"; reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>; diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index a9eda32612..ec14a91f68 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -22,14 +22,16 @@ #define STARFIVE_CLK_MUX_SHIFT 24 /*[29:24]*/ #define STARFIVE_CLK_DIV_SHIFT 0 /*[23:0]*/ -#define SYS_OFFSET(id) (id * 4) -#define STG_OFFSET(id) ((id - JH7110_CLK_SYS_REG_END) * 4) -#define AON_OFFSET(id) ((id - JH7110_CLK_STG_REG_END) * 4) +#define SYS_OFFSET(id) ((id) * 4) +#define STG_OFFSET(id) (((id) - JH7110_CLK_SYS_REG_END) * 4) +#define AON_OFFSET(id) (((id) - JH7110_CLK_STG_REG_END) * 4) +#define VOUT_OFFSET(id) (((id) - JH7110_CLK_VOUT_START) * 4) struct jh7110_clk_priv { void __iomem *sys; void __iomem *stg; void __iomem *aon; + void __iomem *vout; }; static const char *cpu_root_sels[2] = { @@ -62,6 +64,31 @@ static const char *u0_dw_gmac5_axi64_clk_tx_sels[2] = { [1] = "gmac0_rmii_rtx", }; +static const char *mclk_sels[2] = { + [0] = "mclk_inner", + [1] = "mclk_ext", +}; + +static const char *u0_i2stx_4ch_bclk_sels[2] = { + [0] = "i2stx_4ch0_bclk_mst", + [1] = "i2stx_bclk_ext", +}; + +static const char *u0_dc8200_clk_pix_sels[2] = { + [0] = "dc8200_pix0", + [1] = "hdmitx0_pixelclk", +}; + +static const char *dom_vout_top_lcd_clk_sels[2] = { + [0] = "u0_dc8200_clk_pix0_out", + [1] = "u0_dc8200_clk_pix1_out", +}; + +static const char *u0_cdns_dsitx_clk_sels[2] = { + [0] = "dc8200_pix0", + [1] = "hdmitx0_pixelclk", +}; + static ulong starfive_clk_get_rate(struct clk *clk) { struct clk *c; @@ -310,303 +337,497 @@ static int jh7110_clk_init(struct udevice *dev) pll = starfive_jh7110_pll_get_rate(PLL0, &conf); clk_dm(JH7110_PLL0_OUT, - starfive_clk_fix_factor(priv->sys, - "pll0_out", "osc", conf.fbdiv, conf.prediv * conf.postdiv1)); + starfive_clk_fix_factor(priv->sys, + "pll0_out", "osc", conf.fbdiv, + conf.prediv * conf.postdiv1)); pll = starfive_jh7110_pll_get_rate(PLL1, &conf); clk_dm(JH7110_PLL1_OUT, - starfive_clk_fix_factor(priv->sys, - "pll1_out", "osc", conf.fbdiv, conf.prediv * conf.postdiv1)); + starfive_clk_fix_factor(priv->sys, + "pll1_out", "osc", conf.fbdiv, + conf.prediv * conf.postdiv1)); pll = starfive_jh7110_pll_get_rate(PLL2, &conf); clk_dm(JH7110_PLL2_OUT, - starfive_clk_fix_factor(priv->sys, - "pll2_out", "osc", conf.fbdiv, conf.prediv * conf.postdiv1)); + starfive_clk_fix_factor(priv->sys, + "pll2_out", "osc", conf.fbdiv, + conf.prediv * conf.postdiv1)); /*root*/ clk_dm(JH7110_CPU_ROOT, - starfive_clk_mux(priv->sys, "cpu_root", - SYS_OFFSET(JH7110_CPU_ROOT), 1, - cpu_root_sels, ARRAY_SIZE(cpu_root_sels))); + starfive_clk_mux(priv->sys, "cpu_root", + SYS_OFFSET(JH7110_CPU_ROOT), 1, + cpu_root_sels, ARRAY_SIZE(cpu_root_sels))); clk_dm(JH7110_CPU_CORE, - starfive_clk_divider(priv->sys, - "cpu_core", "cpu_root", - SYS_OFFSET(JH7110_CPU_CORE), 3)); + starfive_clk_divider(priv->sys, + "cpu_core", "cpu_root", + SYS_OFFSET(JH7110_CPU_CORE), 3)); clk_dm(JH7110_CPU_BUS, - starfive_clk_divider(priv->sys, - "cpu_bus", "cpu_core", - SYS_OFFSET(JH7110_CPU_BUS), 2)); + starfive_clk_divider(priv->sys, + "cpu_bus", "cpu_core", + SYS_OFFSET(JH7110_CPU_BUS), 2)); clk_dm(JH7110_DDR_ROOT, - starfive_clk_fix_factor(priv->sys, - "ddr_root", "pll1_out", 1, 1)); + starfive_clk_fix_factor(priv->sys, + "ddr_root", "pll1_out", 1, 1)); clk_dm(JH7110_GMACUSB_ROOT, - starfive_clk_fix_factor(priv->sys, - "gmacusb_root", "pll0_out", 1, 1)); + starfive_clk_fix_factor(priv->sys, + "gmacusb_root", "pll0_out", 1, 1)); clk_dm(JH7110_PERH_ROOT, - starfive_clk_composite(priv->sys, - "perh_root", - perh_root_sels, ARRAY_SIZE(perh_root_sels), - SYS_OFFSET(JH7110_PERH_ROOT), 1, 0, 2)); + starfive_clk_composite(priv->sys, + "perh_root", + perh_root_sels, ARRAY_SIZE(perh_root_sels), + SYS_OFFSET(JH7110_PERH_ROOT), 1, 0, 2)); clk_dm(JH7110_BUS_ROOT, - starfive_clk_mux(priv->sys, "bus_root", - SYS_OFFSET(JH7110_BUS_ROOT), 1, - bus_root_sels, ARRAY_SIZE(bus_root_sels))); + starfive_clk_mux(priv->sys, "bus_root", + SYS_OFFSET(JH7110_BUS_ROOT), 1, + bus_root_sels, ARRAY_SIZE(bus_root_sels))); clk_dm(JH7110_AXI_CFG0, - starfive_clk_divider(priv->sys, - "axi_cfg0", "bus_root", - SYS_OFFSET(JH7110_AXI_CFG0), 2)); + starfive_clk_divider(priv->sys, + "axi_cfg0", "bus_root", + SYS_OFFSET(JH7110_AXI_CFG0), 2)); clk_dm(JH7110_STG_AXIAHB, - starfive_clk_divider(priv->sys, - "stg_axiahb", "axi_cfg0", - SYS_OFFSET(JH7110_STG_AXIAHB), 2)); + starfive_clk_divider(priv->sys, + "stg_axiahb", "axi_cfg0", + SYS_OFFSET(JH7110_STG_AXIAHB), 2)); clk_dm(JH7110_AHB0, - starfive_clk_gate(priv->sys, - "ahb0", "stg_axiahb", - SYS_OFFSET(JH7110_AHB0))); + starfive_clk_gate(priv->sys, + "ahb0", "stg_axiahb", + SYS_OFFSET(JH7110_AHB0))); clk_dm(JH7110_AHB1, - starfive_clk_gate(priv->sys, - "ahb1", "stg_axiahb", - SYS_OFFSET(JH7110_AHB1))); + starfive_clk_gate(priv->sys, + "ahb1", "stg_axiahb", + SYS_OFFSET(JH7110_AHB1))); clk_dm(JH7110_APB_BUS_FUNC, - starfive_clk_divider(priv->sys, - "apb_bus_func", "stg_axiahb", - SYS_OFFSET(JH7110_APB_BUS_FUNC), 4)); + starfive_clk_divider(priv->sys, + "apb_bus_func", "stg_axiahb", + SYS_OFFSET(JH7110_APB_BUS_FUNC), 4)); clk_dm(JH7110_PCLK2_MUX_FUNC_PCLK, - starfive_clk_fix_factor(priv->sys, - "u2_pclk_mux_func_pclk", "apb_bus_func", 1, 1)); + starfive_clk_fix_factor(priv->sys, + "u2_pclk_mux_func_pclk", "apb_bus_func", 1, 1)); clk_dm(JH7110_U2_PCLK_MUX_PCLK, - starfive_clk_fix_factor(priv->sys, - "u2_pclk_mux_pclk", "u2_pclk_mux_func_pclk", 1, 1)); + starfive_clk_fix_factor(priv->sys, + "u2_pclk_mux_pclk", "u2_pclk_mux_func_pclk", 1, 1)); clk_dm(JH7110_APB_BUS, - starfive_clk_fix_factor(priv->sys, - "apb_bus", "u2_pclk_mux_pclk", 1, 1)); + starfive_clk_fix_factor(priv->sys, + "apb_bus", "u2_pclk_mux_pclk", 1, 1)); clk_dm(JH7110_APB0, - starfive_clk_gate(priv->sys, - "apb0", "apb_bus", - SYS_OFFSET(JH7110_APB0))); + starfive_clk_gate(priv->sys, + "apb0", "apb_bus", + SYS_OFFSET(JH7110_APB0))); clk_dm(JH7110_APB12, - starfive_clk_fix_factor(priv->sys, - "apb12", "apb_bus", 1, 1)); + starfive_clk_fix_factor(priv->sys, + "apb12", "apb_bus", 1, 1)); clk_dm(JH7110_AON_APB, - starfive_clk_fix_factor(priv->sys, - "aon_apb", "apb_bus_func", 1, 1)); + starfive_clk_fix_factor(priv->sys, + "aon_apb", "apb_bus_func", 1, 1)); /*QSPI*/ clk_dm(JH7110_QSPI_CLK_AHB, - starfive_clk_gate(priv->sys, - "u0_cdns_qspi_clk_ahb", "ahb1", - SYS_OFFSET(JH7110_QSPI_CLK_AHB))); + starfive_clk_gate(priv->sys, + "u0_cdns_qspi_clk_ahb", "ahb1", + SYS_OFFSET(JH7110_QSPI_CLK_AHB))); clk_dm(JH7110_QSPI_CLK_APB, - starfive_clk_gate(priv->sys, - "u0_cdns_qspi_clk_apb", "apb12", - SYS_OFFSET(JH7110_QSPI_CLK_APB))); + starfive_clk_gate(priv->sys, + "u0_cdns_qspi_clk_apb", "apb12", + SYS_OFFSET(JH7110_QSPI_CLK_APB))); clk_dm(JH7110_QSPI_REF_SRC, - starfive_clk_divider(priv->sys, - "u0_cdns_qspi_ref_src", "gmacusb_root", - SYS_OFFSET(JH7110_QSPI_REF_SRC), 5)); + starfive_clk_divider(priv->sys, + "u0_cdns_qspi_ref_src", "gmacusb_root", + SYS_OFFSET(JH7110_QSPI_REF_SRC), 5)); clk_dm(JH7110_QSPI_CLK_REF, - starfive_clk_composite(priv->sys, - "u0_cdns_qspi_clk_ref", - qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels), - SYS_OFFSET(JH7110_QSPI_CLK_REF), 1, 1, 0)); + starfive_clk_composite(priv->sys, + "u0_cdns_qspi_clk_ref", + qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels), + SYS_OFFSET(JH7110_QSPI_CLK_REF), 1, 1, 0)); /*SDIO*/ clk_dm(JH7110_SDIO0_CLK_AHB, - starfive_clk_gate(priv->sys, - "u0_dw_sdio_clk_ahb", "ahb0", - SYS_OFFSET(JH7110_SDIO0_CLK_AHB))); + starfive_clk_gate(priv->sys, + "u0_dw_sdio_clk_ahb", "ahb0", + SYS_OFFSET(JH7110_SDIO0_CLK_AHB))); clk_dm(JH7110_SDIO1_CLK_AHB, - starfive_clk_gate(priv->sys, - "u1_dw_sdio_clk_ahb", "ahb0", - SYS_OFFSET(JH7110_SDIO1_CLK_AHB))); + starfive_clk_gate(priv->sys, + "u1_dw_sdio_clk_ahb", "ahb0", + SYS_OFFSET(JH7110_SDIO1_CLK_AHB))); clk_dm(JH7110_SDIO0_CLK_SDCARD, - starfive_clk_fix_parent_composite(priv->sys, - "u0_dw_sdio_clk_sdcard", "axi_cfg0", - SYS_OFFSET(JH7110_SDIO0_CLK_SDCARD), 0, 1, 4)); + starfive_clk_fix_parent_composite(priv->sys, + "u0_dw_sdio_clk_sdcard", "axi_cfg0", + SYS_OFFSET(JH7110_SDIO0_CLK_SDCARD), 0, 1, 4)); clk_dm(JH7110_SDIO1_CLK_SDCARD, - starfive_clk_fix_parent_composite(priv->sys, - "u1_dw_sdio_clk_sdcard", "axi_cfg0", - SYS_OFFSET(JH7110_SDIO1_CLK_SDCARD), 0, 1, 4)); + starfive_clk_fix_parent_composite(priv->sys, + "u1_dw_sdio_clk_sdcard", "axi_cfg0", + SYS_OFFSET(JH7110_SDIO1_CLK_SDCARD), 0, 1, 4)); /*STG*/ clk_dm(JH7110_USB_125M, - starfive_clk_divider(priv->sys, - "usb_125m", "gmacusb_root", - SYS_OFFSET(JH7110_USB_125M), 4)); + starfive_clk_divider(priv->sys, + "usb_125m", "gmacusb_root", + SYS_OFFSET(JH7110_USB_125M), 4)); /*GMAC1*/ clk_dm(JH7110_GMAC5_CLK_AHB, - starfive_clk_gate(priv->sys, - "u1_dw_gmac5_axi64_clk_ahb", "ahb0", - SYS_OFFSET(JH7110_GMAC5_CLK_AHB))); + starfive_clk_gate(priv->sys, + "u1_dw_gmac5_axi64_clk_ahb", "ahb0", + SYS_OFFSET(JH7110_GMAC5_CLK_AHB))); clk_dm(JH7110_GMAC5_CLK_AXI, - starfive_clk_gate(priv->sys, - "u1_dw_gmac5_axi64_clk_axi", "stg_axiahb", - SYS_OFFSET(JH7110_GMAC5_CLK_AXI))); + starfive_clk_gate(priv->sys, + "u1_dw_gmac5_axi64_clk_axi", "stg_axiahb", + SYS_OFFSET(JH7110_GMAC5_CLK_AXI))); clk_dm(JH7110_GMAC_SRC, - starfive_clk_divider(priv->sys, - "gmac_src", "gmacusb_root", - SYS_OFFSET(JH7110_GMAC_SRC), 3)); + starfive_clk_divider(priv->sys, + "gmac_src", "gmacusb_root", + SYS_OFFSET(JH7110_GMAC_SRC), 3)); clk_dm(JH7110_GMAC1_GTXCLK, - starfive_clk_divider(priv->sys, - "gmac1_gtxclk", "gmacusb_root", - SYS_OFFSET(JH7110_GMAC1_GTXCLK), 4)); + starfive_clk_divider(priv->sys, + "gmac1_gtxclk", "gmacusb_root", + SYS_OFFSET(JH7110_GMAC1_GTXCLK), 4)); clk_dm(JH7110_GMAC1_GTXC, - starfive_clk_gate(priv->sys, - "gmac1_gtxc", "gmac1_gtxclk", - SYS_OFFSET(JH7110_GMAC1_GTXC))); + starfive_clk_gate(priv->sys, + "gmac1_gtxc", "gmac1_gtxclk", + SYS_OFFSET(JH7110_GMAC1_GTXC))); clk_dm(JH7110_GMAC1_RMII_RTX, - starfive_clk_divider(priv->sys, - "gmac1_rmii_rtx", "gmac1_rmii_refin", - SYS_OFFSET(JH7110_GMAC1_RMII_RTX), 5)); + starfive_clk_divider(priv->sys, + "gmac1_rmii_rtx", "gmac1_rmii_refin", + SYS_OFFSET(JH7110_GMAC1_RMII_RTX), 5)); clk_dm(JH7110_GMAC5_CLK_PTP, - starfive_clk_gate_divider(priv->sys, - "u1_dw_gmac5_axi64_clk_ptp", "gmac_src", - SYS_OFFSET(JH7110_GMAC5_CLK_PTP), 5)); + starfive_clk_gate_divider(priv->sys, + "u1_dw_gmac5_axi64_clk_ptp", "gmac_src", + SYS_OFFSET(JH7110_GMAC5_CLK_PTP), 5)); clk_dm(JH7110_GMAC5_CLK_TX, - starfive_clk_composite(priv->sys, - "u1_dw_gmac5_axi64_clk_tx", - gmac5_tx_sels, ARRAY_SIZE(gmac5_tx_sels), - SYS_OFFSET(JH7110_GMAC5_CLK_TX), 1, 1, 0)); + starfive_clk_composite(priv->sys, + "u1_dw_gmac5_axi64_clk_tx", + gmac5_tx_sels, ARRAY_SIZE(gmac5_tx_sels), + SYS_OFFSET(JH7110_GMAC5_CLK_TX), 1, 1, 0)); /*GMAC0*/ clk_dm(JH7110_AON_AHB, - starfive_clk_fix_factor(priv->sys, "aon_ahb", - "stg_axiahb", 1, 1)); + starfive_clk_fix_factor(priv->sys, "aon_ahb", + "stg_axiahb", 1, 1)); clk_dm(JH7110_GMAC0_GTXCLK, - starfive_clk_gate_divider(priv->sys, "gmac0_gtxclk", - "gmacusb_root", SYS_OFFSET(JH7110_GMAC0_GTXCLK), 4)); + starfive_clk_gate_divider(priv->sys, "gmac0_gtxclk", + "gmacusb_root", SYS_OFFSET(JH7110_GMAC0_GTXCLK), 4)); clk_dm(JH7110_GMAC0_PTP, - starfive_clk_gate_divider(priv->sys, "gmac0_ptp", - "gmac_src", SYS_OFFSET(JH7110_GMAC0_PTP), 5)); + starfive_clk_gate_divider(priv->sys, "gmac0_ptp", + "gmac_src", SYS_OFFSET(JH7110_GMAC0_PTP), 5)); clk_dm(JH7110_GMAC0_GTXC, - starfive_clk_gate(priv->sys, - "gmac0_gtxc", "gmac0_gtxclk", - SYS_OFFSET(JH7110_GMAC0_GTXC))); + starfive_clk_gate(priv->sys, + "gmac0_gtxc", "gmac0_gtxclk", + SYS_OFFSET(JH7110_GMAC0_GTXC))); /*UART0*/ clk_dm(JH7110_UART0_CLK_APB, - starfive_clk_gate(priv->sys, - "u0_dw_uart_clk_apb", "apb0", - SYS_OFFSET(JH7110_UART0_CLK_APB))); + starfive_clk_gate(priv->sys, + "u0_dw_uart_clk_apb", "apb0", + SYS_OFFSET(JH7110_UART0_CLK_APB))); clk_dm(JH7110_UART0_CLK_CORE, - starfive_clk_gate(priv->sys, - "u0_dw_uart_clk_core", "osc", - SYS_OFFSET(JH7110_UART0_CLK_CORE))); + starfive_clk_gate(priv->sys, + "u0_dw_uart_clk_core", "osc", + SYS_OFFSET(JH7110_UART0_CLK_CORE))); /*UART1*/ clk_dm(JH7110_UART1_CLK_APB, - starfive_clk_gate(priv->sys, - "u1_dw_uart_clk_apb", "apb0", - SYS_OFFSET(JH7110_UART1_CLK_APB))); + starfive_clk_gate(priv->sys, + "u1_dw_uart_clk_apb", "apb0", + SYS_OFFSET(JH7110_UART1_CLK_APB))); clk_dm(JH7110_UART1_CLK_CORE, - starfive_clk_gate(priv->sys, - "u1_dw_uart_clk_core", "osc", - SYS_OFFSET(JH7110_UART1_CLK_CORE))); + starfive_clk_gate(priv->sys, + "u1_dw_uart_clk_core", "osc", + SYS_OFFSET(JH7110_UART1_CLK_CORE))); /*UART2*/ clk_dm(JH7110_UART2_CLK_APB, - starfive_clk_gate(priv->sys, - "u2_dw_uart_clk_apb", "apb0", - SYS_OFFSET(JH7110_UART2_CLK_APB))); + starfive_clk_gate(priv->sys, + "u2_dw_uart_clk_apb", "apb0", + SYS_OFFSET(JH7110_UART2_CLK_APB))); clk_dm(JH7110_UART2_CLK_CORE, - starfive_clk_gate(priv->sys, - "u2_dw_uart_clk_core", "osc", - SYS_OFFSET(JH7110_UART2_CLK_CORE))); + starfive_clk_gate(priv->sys, + "u2_dw_uart_clk_core", "osc", + SYS_OFFSET(JH7110_UART2_CLK_CORE))); /*UART3*/ clk_dm(JH7110_UART3_CLK_APB, - starfive_clk_gate(priv->sys, - "u3_dw_uart_clk_apb", "apb0", - SYS_OFFSET(JH7110_UART3_CLK_APB))); + starfive_clk_gate(priv->sys, + "u3_dw_uart_clk_apb", "apb0", + SYS_OFFSET(JH7110_UART3_CLK_APB))); clk_dm(JH7110_UART3_CLK_CORE, - starfive_clk_gate_divider(priv->sys, - "u3_dw_uart_clk_core", "perh_root", - SYS_OFFSET(JH7110_UART3_CLK_CORE), 8)); + starfive_clk_gate_divider(priv->sys, + "u3_dw_uart_clk_core", "perh_root", + SYS_OFFSET(JH7110_UART3_CLK_CORE), 8)); /*UART4*/ clk_dm(JH7110_UART4_CLK_APB, - starfive_clk_gate(priv->sys, - "u4_dw_uart_clk_apb", "apb0", - SYS_OFFSET(JH7110_UART4_CLK_APB))); + starfive_clk_gate(priv->sys, + "u4_dw_uart_clk_apb", "apb0", + SYS_OFFSET(JH7110_UART4_CLK_APB))); clk_dm(JH7110_UART4_CLK_CORE, - starfive_clk_gate_divider(priv->sys, - "u4_dw_uart_clk_core", "perh_root", - SYS_OFFSET(JH7110_UART4_CLK_CORE), 8)); + starfive_clk_gate_divider(priv->sys, + "u4_dw_uart_clk_core", "perh_root", + SYS_OFFSET(JH7110_UART4_CLK_CORE), 8)); /*UART5*/ clk_dm(JH7110_UART5_CLK_APB, - starfive_clk_gate(priv->sys, - "u5_dw_uart_clk_apb", "apb0", - SYS_OFFSET(JH7110_UART5_CLK_APB))); + starfive_clk_gate(priv->sys, + "u5_dw_uart_clk_apb", "apb0", + SYS_OFFSET(JH7110_UART5_CLK_APB))); clk_dm(JH7110_UART5_CLK_CORE, - starfive_clk_gate_divider(priv->sys, - "u5_dw_uart_clk_core", "perh_root", - SYS_OFFSET(JH7110_UART5_CLK_CORE), 8)); + starfive_clk_gate_divider(priv->sys, + "u5_dw_uart_clk_core", "perh_root", + SYS_OFFSET(JH7110_UART5_CLK_CORE), 8)); clk_dm(JH7110_STG_APB, - starfive_clk_fix_factor(priv->stg, - "stg_apb", "apb_bus", 1, 1)); + starfive_clk_fix_factor(priv->stg, + "stg_apb", "apb_bus", 1, 1)); /*USB*/ clk_dm(JH7110_USB0_CLK_USB_APB, - starfive_clk_gate(priv->stg, - "u0_cdn_usb_clk_usb_apb", "stg_apb", - STG_OFFSET(JH7110_USB0_CLK_USB_APB))); + starfive_clk_gate(priv->stg, + "u0_cdn_usb_clk_usb_apb", "stg_apb", + STG_OFFSET(JH7110_USB0_CLK_USB_APB))); clk_dm(JH7110_USB0_CLK_UTMI_APB, - starfive_clk_gate(priv->stg, - "u0_cdn_usb_clk_utmi_apb", "stg_apb", - STG_OFFSET(JH7110_USB0_CLK_UTMI_APB))); + starfive_clk_gate(priv->stg, + "u0_cdn_usb_clk_utmi_apb", "stg_apb", + STG_OFFSET(JH7110_USB0_CLK_UTMI_APB))); clk_dm(JH7110_USB0_CLK_AXI, - starfive_clk_gate(priv->stg, - "u0_cdn_usb_clk_axi", "stg_axiahb", - STG_OFFSET(JH7110_USB0_CLK_AXI))); + starfive_clk_gate(priv->stg, + "u0_cdn_usb_clk_axi", "stg_axiahb", + STG_OFFSET(JH7110_USB0_CLK_AXI))); clk_dm(JH7110_USB0_CLK_LPM, - starfive_clk_gate_divider(priv->stg, - "u0_cdn_usb_clk_lpm", "osc", - STG_OFFSET(JH7110_USB0_CLK_LPM), 2)); + starfive_clk_gate_divider(priv->stg, + "u0_cdn_usb_clk_lpm", "osc", + STG_OFFSET(JH7110_USB0_CLK_LPM), 2)); clk_dm(JH7110_USB0_CLK_STB, - starfive_clk_gate_divider(priv->stg, - "u0_cdn_usb_clk_stb", "osc", - STG_OFFSET(JH7110_USB0_CLK_STB), 3)); + starfive_clk_gate_divider(priv->stg, + "u0_cdn_usb_clk_stb", "osc", + STG_OFFSET(JH7110_USB0_CLK_STB), 3)); clk_dm(JH7110_USB0_CLK_APP_125, - starfive_clk_gate(priv->stg, - "u0_cdn_usb_clk_app_125", "usb_125m", - STG_OFFSET(JH7110_USB0_CLK_APP_125))); + starfive_clk_gate(priv->stg, + "u0_cdn_usb_clk_app_125", "usb_125m", + STG_OFFSET(JH7110_USB0_CLK_APP_125))); clk_dm(JH7110_USB0_REFCLK, - starfive_clk_divider(priv->stg, - "u0_cdn_usb_refclk", "osc", - STG_OFFSET(JH7110_USB0_REFCLK), 2)); + starfive_clk_divider(priv->stg, + "u0_cdn_usb_refclk", "osc", + STG_OFFSET(JH7110_USB0_REFCLK), 2)); /*GMAC1*/ clk_dm(JH7110_U0_GMAC5_CLK_AHB, - starfive_clk_gate(priv->aon, - "u0_dw_gmac5_axi64_clk_ahb", "aon_ahb", - AON_OFFSET(JH7110_U0_GMAC5_CLK_AHB))); + starfive_clk_gate(priv->aon, + "u0_dw_gmac5_axi64_clk_ahb", "aon_ahb", + AON_OFFSET(JH7110_U0_GMAC5_CLK_AHB))); clk_dm(JH7110_U0_GMAC5_CLK_AXI, - starfive_clk_gate(priv->aon, - "u0_dw_gmac5_axi64_clk_axi", "aon_ahb", - AON_OFFSET(JH7110_U0_GMAC5_CLK_AXI))); + starfive_clk_gate(priv->aon, + "u0_dw_gmac5_axi64_clk_axi", "aon_ahb", + AON_OFFSET(JH7110_U0_GMAC5_CLK_AXI))); clk_dm(JH7110_GMAC0_RMII_RTX, - starfive_clk_divider(priv->aon, - "gmac0_rmii_rtx", "gmac0_rmii_refin", - AON_OFFSET(JH7110_GMAC0_RMII_RTX), 5)); + starfive_clk_divider(priv->aon, + "gmac0_rmii_rtx", "gmac0_rmii_refin", + AON_OFFSET(JH7110_GMAC0_RMII_RTX), 5)); clk_dm(JH7110_U0_GMAC5_CLK_PTP, - starfive_clk_fix_factor(priv->aon, - "u0_dw_gmac5_axi64_clk_ptp", - "gmac0_ptp", 1, 1)); + starfive_clk_fix_factor(priv->aon, + "u0_dw_gmac5_axi64_clk_ptp", + "gmac0_ptp", 1, 1)); clk_dm(JH7110_U0_GMAC5_CLK_TX, - starfive_clk_composite(priv->aon, - "u0_dw_gmac5_axi64_clk_tx", - u0_dw_gmac5_axi64_clk_tx_sels, - ARRAY_SIZE(u0_dw_gmac5_axi64_clk_tx_sels), - AON_OFFSET(JH7110_U0_GMAC5_CLK_TX), 1, 1, 0)); + starfive_clk_composite(priv->aon, + "u0_dw_gmac5_axi64_clk_tx", + u0_dw_gmac5_axi64_clk_tx_sels, + ARRAY_SIZE(u0_dw_gmac5_axi64_clk_tx_sels), + AON_OFFSET(JH7110_U0_GMAC5_CLK_TX), 1, 1, 0)); /*otp*/ clk_dm(JH7110_OTPC_CLK_APB, - starfive_clk_gate(priv->aon, - "u0_otpc_clk_apb", "aon_apb", - AON_OFFSET(JH7110_OTPC_CLK_APB))); + starfive_clk_gate(priv->aon, + "u0_otpc_clk_apb", "aon_apb", + AON_OFFSET(JH7110_OTPC_CLK_APB))); + /*vout*/ + clk_dm(JH7110_VOUT_ROOT, + starfive_clk_fix_factor(priv->sys, + "vout_root", "pll2_out", 1, 1)); + clk_dm(JH7110_AUDIO_ROOT, + starfive_clk_divider(priv->sys, + "audio_root", "pll2_out", + SYS_OFFSET(JH7110_AUDIO_ROOT), 5)); + clk_dm(JH7110_VOUT_SRC, + starfive_clk_gate(priv->sys, + "u0_dom_vout_top_clk_vout_src", "vout_root", + SYS_OFFSET(JH7110_VOUT_SRC))); + clk_dm(JH7110_VOUT_AXI, + starfive_clk_divider(priv->sys, + "vout_axi", "vout_root", + SYS_OFFSET(JH7110_VOUT_AXI), 3)); + clk_dm(JH7110_VOUT_TOP_CLK_VOUT_AXI, + starfive_clk_gate(priv->sys, + "u0_dom_vout_top_vout_axi", "vout_axi", + SYS_OFFSET(JH7110_VOUT_TOP_CLK_VOUT_AXI))); + clk_dm(JH7110_NOC_BUS_CLK_DISP_AXI, + starfive_clk_gate(priv->sys, + "u0_sft7110_noc_bus_clk_disp_axi", "vout_axi", + SYS_OFFSET(JH7110_NOC_BUS_CLK_DISP_AXI))); + clk_dm(JH7110_VOUT_TOP_CLK_VOUT_AHB, + starfive_clk_gate(priv->sys, + "u0_dom_vout_top_clk_vout_ahb", "ahb1", + SYS_OFFSET(JH7110_VOUT_TOP_CLK_VOUT_AHB))); + clk_dm(JH7110_MCLK_INNER, + starfive_clk_divider(priv->sys, + "mclk_inner", "audio_root", + SYS_OFFSET(JH7110_MCLK_INNER), 5)); + clk_dm(JH7110_MCLK, + starfive_clk_mux(priv->sys, "mclk", + SYS_OFFSET(JH7110_MCLK), 1, + mclk_sels, ARRAY_SIZE(mclk_sels))); + clk_dm(JH7110_I2STX_4CH0_BCLK_MST, + starfive_clk_gate_divider(priv->sys, + "i2stx_4ch0_bclk_mst", "mclk", + SYS_OFFSET(JH7110_I2STX_4CH0_BCLK_MST), 5)); + clk_dm(JH7110_I2STX0_4CHBCLK, + starfive_clk_mux(priv->sys, "u0_i2stx_4ch_bclk", + SYS_OFFSET(JH7110_I2STX0_4CHBCLK), 1, + u0_i2stx_4ch_bclk_sels, ARRAY_SIZE(u0_i2stx_4ch_bclk_sels))); + clk_dm(JH7110_VOUT_TOP_CLK_HDMITX0_BCLK, + starfive_clk_fix_factor(priv->sys, + "u0_dom_vout_top_clk_hdmitx0_bclk", + "u0_i2stx_4ch_bclk", 1, 1)); + clk_dm(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK, + starfive_clk_gate(priv->sys, + "u0_dom_vout_top_clk_hdmitx0_mclk", "mclk", + SYS_OFFSET(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK))); + clk_dm(JH7110_VOUT_TOP_CLK_MIPIPHY_REF, + starfive_clk_divider(priv->sys, + "u0_dom_vout_top_clk_mipiphy_ref", "osc", + SYS_OFFSET(JH7110_MCLK_INNER), 2)); + + return 0; +} + +static int jh7110_clk_vout_init(struct udevice *dev) +{ + struct jh7110_clk_priv *priv = dev_get_priv(dev); + + clk_dm(JH7110_DISP_ROOT, + starfive_clk_fix_factor(priv->vout, + "disp_root", "u0_dom_vout_top_clk_vout_src", + 1, 1)); + clk_dm(JH7110_DISP_AXI, + starfive_clk_fix_factor(priv->vout, + "disp_axi", "u0_dom_vout_top_vout_axi", + 1, 1)); + clk_dm(JH7110_DISP_AHB, + starfive_clk_fix_factor(priv->vout, + "disp_ahb", "u0_dom_vout_top_clk_vout_ahb", + 1, 1)); + clk_dm(JH7110_HDMITX0_MCLK, + starfive_clk_fix_factor(priv->vout, + "hdmitx0_mclk", "u0_dom_vout_top_clk_hdmitx0_mclk", + 1, 1)); + clk_dm(JH7110_HDMITX0_SCK, + starfive_clk_fix_factor(priv->vout, + "hdmitx0_sck", "u0_dom_vout_top_clk_hdmitx0_bclk", + 1, 1)); + clk_dm(JH7110_APB, + starfive_clk_divider(priv->vout, + "apb", "disp_ahb", + VOUT_OFFSET(JH7110_APB), 5)); + clk_dm(JH7110_U0_PCLK_MUX_FUNC_PCLK, + starfive_clk_fix_factor(priv->vout, + "u0_pclk_mux_func_pclk", "apb", + 1, 1)); + clk_dm(JH7110_DISP_APB, + starfive_clk_fix_factor(priv->vout, + "disp_apb", "u0_pclk_mux_func_pclk", + 1, 1)); + clk_dm(JH7110_TX_ESC, + starfive_clk_divider(priv->vout, + "tx_esc", "disp_ahb", + VOUT_OFFSET(JH7110_TX_ESC), 5)); + clk_dm(JH7110_DC8200_PIX0, + starfive_clk_divider(priv->vout, + "dc8200_pix0", "disp_root", + VOUT_OFFSET(JH7110_DC8200_PIX0), 6)); + clk_dm(JH7110_DSI_SYS, + starfive_clk_divider(priv->vout, + "dsi_sys", "disp_root", + VOUT_OFFSET(JH7110_DSI_SYS), 5)); + clk_dm(JH7110_U0_DC8200_CLK_PIX0, + starfive_clk_composite(priv->vout, + "u0_dc8200_clk_pix0", + u0_dc8200_clk_pix_sels, + ARRAY_SIZE(u0_dc8200_clk_pix_sels), + VOUT_OFFSET(JH7110_U0_DC8200_CLK_PIX0), 1, 1, 0)); + clk_dm(JH7110_U0_DC8200_CLK_PIX1, + starfive_clk_composite(priv->vout, + "u0_dc8200_clk_pix1", + u0_dc8200_clk_pix_sels, + ARRAY_SIZE(u0_dc8200_clk_pix_sels), + VOUT_OFFSET(JH7110_U0_DC8200_CLK_PIX1), 1, 1, 0)); + clk_dm(JH7110_U0_DC8200_CLK_AXI, + starfive_clk_gate(priv->vout, + "u0_dc8200_clk_axi", "disp_axi", + VOUT_OFFSET(JH7110_U0_DC8200_CLK_AXI))); + clk_dm(JH7110_U0_DC8200_CLK_CORE, + starfive_clk_gate(priv->vout, + "u0_dc8200_clk_core", "disp_axi", + VOUT_OFFSET(JH7110_U0_DC8200_CLK_CORE))); + clk_dm(JH7110_U0_DC8200_CLK_AHB, + starfive_clk_gate(priv->vout, + "u0_dc8200_clk_ahb", "disp_ahb", + VOUT_OFFSET(JH7110_U0_DC8200_CLK_AHB))); + clk_dm(JH7110_U0_DC8200_CLK_PIX0_OUT, + starfive_clk_fix_factor(priv->vout, + "u0_dc8200_clk_pix0_out", "u0_dc8200_clk_pix0", + 1, 1)); + clk_dm(JH7110_U0_DC8200_CLK_PIX1_OUT, + starfive_clk_fix_factor(priv->sys, + "u0_dc8200_clk_pix1_out", "u0_dc8200_clk_pix1", + 1, 1)); + clk_dm(JH7110_DOM_VOUT_TOP_LCD_CLK, + starfive_clk_composite(priv->vout, + "dom_vout_top_lcd_clk", + dom_vout_top_lcd_clk_sels, + ARRAY_SIZE(dom_vout_top_lcd_clk_sels), + VOUT_OFFSET(JH7110_DOM_VOUT_TOP_LCD_CLK), 1, 1, 0)); + clk_dm(JH7110_U0_MIPITX_DPHY_CLK_TXESC, + starfive_clk_gate(priv->vout, + "u0_mipitx_dphy_clk_txesc", "tx_esc", + VOUT_OFFSET(JH7110_U0_MIPITX_DPHY_CLK_TXESC))); + clk_dm(JH7110_U0_CDNS_DSITX_CLK_SYS, + starfive_clk_gate(priv->vout, + "u0_cdns_dsiTx_clk_sys", "dsi_sys", + VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_SYS))); + clk_dm(JH7110_U0_CDNS_DSITX_CLK_APB, + starfive_clk_gate(priv->vout, + "u0_cdns_dsiTx_clk_apb", "dsi_sys", + VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_APB))); + clk_dm(JH7110_U0_CDNS_DSITX_CLK_TXESC, + starfive_clk_gate(priv->vout, + "u0_cdns_dsiTx_clk_txesc", "tx_esc", + VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_TXESC))); + clk_dm(JH7110_U0_CDNS_DSITX_CLK_DPI, + starfive_clk_composite(priv->vout, + "u0_cdns_dsitx_clk_api", + u0_cdns_dsitx_clk_sels, + ARRAY_SIZE(u0_cdns_dsitx_clk_sels), + VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_DPI), 1, 1, 0)); + clk_dm(JH7110_U0_HDMI_TX_CLK_SYS, + starfive_clk_gate(priv->vout, + "u0_hdmi_tx_clk_sys", "disp_apb", + VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_SYS))); + clk_dm(JH7110_U0_HDMI_TX_CLK_MCLK, + starfive_clk_gate(priv->vout, + "u0_hdmi_tx_clk_mclk", "hdmitx0_mclk", + VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_MCLK))); + clk_dm(JH7110_U0_HDMI_TX_CLK_BCLK, + starfive_clk_gate(priv->vout, + "u0_hdmi_tx_clk_bclk", "hdmitx0_sck", + VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_BCLK))); return 0; } +static int jh7110_clk_vout_probe(struct udevice *dev) +{ + struct jh7110_clk_priv *priv = dev_get_priv(dev); + + priv->vout = (void __iomem *)dev_read_addr(dev); + if (!priv->vout) + return -EINVAL; + + return jh7110_clk_vout_init(dev); +} + static int jh7110_clk_probe(struct udevice *dev) { struct jh7110_clk_priv *priv = dev_get_priv(dev); @@ -640,3 +861,17 @@ U_BOOT_DRIVER(jh7110_clk) = { .priv_auto = sizeof(struct jh7110_clk_priv), }; +static const struct udevice_id jh7110_clk_vout_of_match[] = { + { .compatible = "starfive,jh7110-clk-vout" }, + { } +}; + +U_BOOT_DRIVER(jh7110_clk_vout) = { + .name = "jh7110_clk_vout", + .id = UCLASS_CLK, + .of_match = jh7110_clk_vout_of_match, + .probe = jh7110_clk_vout_probe, + .ops = &starfive_clk_ops, + .priv_auto = sizeof(struct jh7110_clk_priv), +}; + diff --git a/include/dt-bindings/clock/starfive-jh7110-clkgen.h b/include/dt-bindings/clock/starfive-jh7110-clkgen.h index 1228a8c94b..c2df56f222 100644 --- a/include/dt-bindings/clock/starfive-jh7110-clkgen.h +++ b/include/dt-bindings/clock/starfive-jh7110-clkgen.h @@ -391,4 +391,61 @@ #define JH7110_GMAC0_RGMII_RXIN (JH7110_CLK_END + 13) #define JH7110_CLK_RTC (JH7110_CLK_END + 14) +#define JH7110_CLK_VOUT_START (JH7110_CLK_RTC + 1) + +/* vout regisger */ +#define JH7110_APB (JH7110_CLK_VOUT_START + 0) +#define JH7110_DC8200_PIX0 (JH7110_CLK_VOUT_START + 1) +#define JH7110_DSI_SYS (JH7110_CLK_VOUT_START + 2) +#define JH7110_TX_ESC (JH7110_CLK_VOUT_START + 3) +#define JH7110_U0_DC8200_CLK_AXI (JH7110_CLK_VOUT_START + 4) +#define JH7110_U0_DC8200_CLK_CORE (JH7110_CLK_VOUT_START + 5) +#define JH7110_U0_DC8200_CLK_AHB (JH7110_CLK_VOUT_START + 6) +#define JH7110_U0_DC8200_CLK_PIX0 (JH7110_CLK_VOUT_START + 7) +#define JH7110_U0_DC8200_CLK_PIX1 (JH7110_CLK_VOUT_START + 8) +#define JH7110_DOM_VOUT_TOP_LCD_CLK (JH7110_CLK_VOUT_START + 9) +#define JH7110_U0_CDNS_DSITX_CLK_APB (JH7110_CLK_VOUT_START + 10) +#define JH7110_U0_CDNS_DSITX_CLK_SYS (JH7110_CLK_VOUT_START + 11) +#define JH7110_U0_CDNS_DSITX_CLK_DPI (JH7110_CLK_VOUT_START + 12) +#define JH7110_U0_CDNS_DSITX_CLK_TXESC (JH7110_CLK_VOUT_START + 13) +#define JH7110_U0_MIPITX_DPHY_CLK_TXESC (JH7110_CLK_VOUT_START + 14) +#define JH7110_U0_HDMI_TX_CLK_MCLK (JH7110_CLK_VOUT_START + 15) +#define JH7110_U0_HDMI_TX_CLK_BCLK (JH7110_CLK_VOUT_START + 16) +#define JH7110_U0_HDMI_TX_CLK_SYS (JH7110_CLK_VOUT_START + 17) + +#define JH7110_CLK_VOUT_REG_END (JH7110_CLK_VOUT_START + 18) + +/* vout other */ +#define JH7110_DISP_ROOT (JH7110_CLK_VOUT_START + 18) +#define JH7110_DISP_AXI (JH7110_CLK_VOUT_START + 19) +#define JH7110_DISP_AHB (JH7110_CLK_VOUT_START + 20) +#define JH7110_HDMI_PHY_REF (JH7110_CLK_VOUT_START + 21) +#define JH7110_HDMITX0_MCLK (JH7110_CLK_VOUT_START + 22) +#define JH7110_HDMITX0_SCK (JH7110_CLK_VOUT_START + 23) + +#define JH7110_MIPI_DPHY_REF (JH7110_CLK_VOUT_START + 24) +#define JH7110_U0_PCLK_MUX_BIST_PCLK (JH7110_CLK_VOUT_START + 25) +#define JH7110_DISP_APB (JH7110_CLK_VOUT_START + 26) +#define JH7110_U0_PCLK_MUX_FUNC_PCLK (JH7110_CLK_VOUT_START + 27) +#define JH7110_U0_DOM_VOUT_CRG_PCLK (JH7110_CLK_VOUT_START + 28) +#define JH7110_U0_DOM_VOUT_SYSCON_PCLK (JH7110_CLK_VOUT_START + 29) +#define JH7110_U0_SAIF_AMBA_DOM_VOUT_AHB_DEC_CLK_AHB (JH7110_CLK_VOUT_START + 30) +#define JH7110_U0_AHB2APB_CLK_AHB (JH7110_CLK_VOUT_START + 31) +#define JH7110_U0_P2P_ASYNC_CLK_APBS (JH7110_CLK_VOUT_START + 32) +#define JH7110_U0_CDNS_DSITX_CLK_RXESC (JH7110_CLK_VOUT_START + 33) +#define JH7110_U0_CDNS_DSITX_CLK_TXBYTEHS (JH7110_CLK_VOUT_START + 34) +#define JH7110_U0_MIPITX_DPHY_CLK_SYS (JH7110_CLK_VOUT_START + 35) +#define JH7110_U0_MIPITX_DPHY_CLK_DPHY_REF (JH7110_CLK_VOUT_START + 36) +#define JH7110_U0_MIPITX_APBIF_PCLK (JH7110_CLK_VOUT_START + 37) +#define JH7110_HDMI_TX_CLK_REF (JH7110_CLK_VOUT_START + 38) +#define JH7110_U0_DC8200_CLK_PIX0_OUT (JH7110_CLK_VOUT_START + 39) +#define JH7110_U0_DC8200_CLK_PIX1_OUT (JH7110_CLK_VOUT_START + 40) + +#define JH7110_CLK_VOUT_END (JH7110_CLK_VOUT_START + 41) + +/* vout external clocks */ +#define JH7110_HDMITX0_PIXELCLK (JH7110_CLK_VOUT_END + 0) +#define JH7110_MIPITX_DPHY_RXESC (JH7110_CLK_VOUT_END + 1) +#define JH7110_MIPITX_DPHY_TXBYTEHS (JH7110_CLK_VOUT_END + 2) + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ diff --git a/include/dt-bindings/clock/starfive-jh7110-vout.h b/include/dt-bindings/clock/starfive-jh7110-vout.h deleted file mode 100644 index e76a80a5f1..0000000000 --- a/include/dt-bindings/clock/starfive-jh7110-vout.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -/* - * Copyright 2022 StarFive, Inc <xingyu.wu@starfivetech.com> - */ - -#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_VOUT_H__ -#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_VOUT_H__ - -/* regisger */ -#define JH7110_APB 0 -#define JH7110_DC8200_PIX0 1 -#define JH7110_DSI_SYS 2 -#define JH7110_TX_ESC 3 -#define JH7110_U0_DC8200_CLK_AXI 4 -#define JH7110_U0_DC8200_CLK_CORE 5 -#define JH7110_U0_DC8200_CLK_AHB 6 -#define JH7110_U0_DC8200_CLK_PIX0 7 -#define JH7110_U0_DC8200_CLK_PIX1 8 -#define JH7110_DOM_VOUT_TOP_LCD_CLK 9 -#define JH7110_U0_CDNS_DSITX_CLK_APB 10 -#define JH7110_U0_CDNS_DSITX_CLK_SYS 11 -#define JH7110_U0_CDNS_DSITX_CLK_DPI 12 -#define JH7110_U0_CDNS_DSITX_CLK_TXESC 13 -#define JH7110_U0_MIPITX_DPHY_CLK_TXESC 14 -#define JH7110_U0_HDMI_TX_CLK_MCLK 15 -#define JH7110_U0_HDMI_TX_CLK_BCLK 16 -#define JH7110_U0_HDMI_TX_CLK_SYS 17 - -#define JH7110_CLK_VOUT_REG_END 18 - -/* other */ -#define JH7110_DISP_ROOT 18 -#define JH7110_DISP_AXI 19 -#define JH7110_DISP_AHB 20 -#define JH7110_HDMI_PHY_REF 21 -#define JH7110_HDMITX0_MCLK 22 -#define JH7110_HDMITX0_SCK 23 - -#define JH7110_MIPI_DPHY_REF 24 -#define JH7110_U0_PCLK_MUX_BIST_PCLK 25 -#define JH7110_DISP_APB 26 -#define JH7110_U0_PCLK_MUX_FUNC_PCLK 27 -#define JH7110_U0_DOM_VOUT_CRG_PCLK 28 -#define JH7110_U0_DOM_VOUT_SYSCON_PCLK 29 -#define JH7110_U0_SAIF_AMBA_DOM_VOUT_AHB_DEC_CLK_AHB 30 -#define JH7110_U0_AHB2APB_CLK_AHB 31 -#define JH7110_U0_P2P_ASYNC_CLK_APBS 32 -#define JH7110_U0_CDNS_DSITX_CLK_RXESC 33 -#define JH7110_U0_CDNS_DSITX_CLK_TXBYTEHS 34 -#define JH7110_U0_MIPITX_DPHY_CLK_SYS 35 -#define JH7110_U0_MIPITX_DPHY_CLK_DPHY_REF 36 -#define JH7110_U0_MIPITX_APBIF_PCLK 37 -#define JH7110_HDMI_TX_CLK_REF 38 -#define JH7110_U0_DC8200_CLK_PIX0_OUT 39 -#define JH7110_U0_DC8200_CLK_PIX1_OUT 40 - -#define JH7110_CLK_VOUT_END 41 - -/* external clocks */ -#define JH7110_HDMITX0_PIXELCLK (JH7110_CLK_VOUT_END + 0) -#define JH7110_MIPITX_DPHY_RXESC (JH7110_CLK_VOUT_END + 1) -#define JH7110_MIPITX_DPHY_TXBYTEHS (JH7110_CLK_VOUT_END + 2) - - - -#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ |