diff options
| -rw-r--r-- | board/starfive/evb/starfive_evb.c | 36 | ||||
| -rw-r--r-- | include/configs/starfive-evb.h | 26 |
2 files changed, 62 insertions, 0 deletions
diff --git a/board/starfive/evb/starfive_evb.c b/board/starfive/evb/starfive_evb.c index b3d3a1de9b..e1e3f2dbc4 100644 --- a/board/starfive/evb/starfive_evb.c +++ b/board/starfive/evb/starfive_evb.c @@ -25,8 +25,15 @@ enum chip_type_t { CHIP_MAX, }; +enum cpu_voltage_type_t { + CPU_VOL_1040 = 0xff, + CPU_VOL_1060 = 0xf0, + CPU_VOL_1080 = 0xf1, +}; + #define SYS_CLOCK_ENABLE(clk) \ setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK) +#define CPU_VOL_BINNING_OFFSET 0x7fc static void sys_reset_clear(ulong assert, ulong status, u32 rst) { @@ -192,6 +199,32 @@ static u32 get_chip_type(void) return value; } +#if CONFIG_IS_ENABLED(STARFIVE_OTP) +static void get_cpu_voltage_type(struct udevice *dev) +{ + int ret; + u32 buf = CPU_VOL_1040; + + ret = misc_read(dev, CPU_VOL_BINNING_OFFSET, &buf, sizeof(buf)); + if (ret != sizeof(buf)) + printf("%s: error reading CPU vol from OTP\n", __func__); + else { + switch ((buf & 0xff)) { + case CPU_VOL_1080: + env_set("cpu_max_vol", "1080000"); + break; + case CPU_VOL_1060: + env_set("cpu_max_vol", "1060000"); + break; + case CPU_VOL_1040: + default: + env_set("cpu_max_vol", "1040000"); + break; + } + } +} +#endif + /*enable U74-mc hart1~hart4 prefetcher*/ static void enable_prefetcher(void) { @@ -259,6 +292,9 @@ err: eth_env_set_enetaddr("eth1addr", mac1); chip = get_chip_type(); +#if CONFIG_IS_ENABLED(STARFIVE_OTP) + get_cpu_voltage_type(dev); +#endif jh7110_gmac_init(0, chip); jh7110_gmac_init(1, chip); return 0; diff --git a/include/configs/starfive-evb.h b/include/configs/starfive-evb.h index 8f710a745f..b9587ff043 100644 --- a/include/configs/starfive-evb.h +++ b/include/configs/starfive-evb.h @@ -100,6 +100,28 @@ #define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985" #define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4" +#define CPU_VOL_1040_SET \ + "cpu_vol_1040_set=" \ + "fdt set /opp-table-0/opp-1500000000 opp-microvolt <1040000>;\0" + +#define CPU_VOL_1060_SET \ + "cpu_vol_1060_set=" \ + "fdt set /opp-table-0/opp-1500000000 opp-microvolt <1060000>;\0" + +#define CPU_VOL_1080_SET \ + "cpu_vol_1080_set=" \ + "fdt set /opp-table-0/opp-1500000000 opp-microvolt <1080000>;\0" + +#define CPU_VOL_SET \ + "cpu_vol_set=" \ + "if test ${cpu_max_vol} = 1080000; then " \ + "run cpu_vol_1080_set;" \ + "elif test ${cpu_max_vol} = 1060000; then " \ + "run cpu_vol_1060_set;" \ + "else " \ + "run cpu_vol_1040_set;" \ + "fi; \0" + #define CHIPA_GMAC_SET \ "chipa_gmac_set=" \ "fdt set /soc/ethernet@16030000/ethernet-phy@0 tx_inverted_10 <0x1>;" \ @@ -135,6 +157,10 @@ "ramdisk_addr_r=0x46100000\0" \ CHIPA_GMAC_SET \ CHIPA_SET \ + CPU_VOL_1040_SET \ + CPU_VOL_1060_SET \ + CPU_VOL_1080_SET \ + CPU_VOL_SET \ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ |