diff options
-rw-r--r-- | arch/riscv/Kconfig | 4 | ||||
-rw-r--r-- | arch/riscv/include/asm/arch-jh7110/jh7110-regs.h | 45 | ||||
-rw-r--r-- | board/starfive/visionfive/Kconfig | 52 | ||||
-rw-r--r-- | board/starfive/visionfive/MAINTAINERS | 7 | ||||
-rw-r--r-- | board/starfive/visionfive/Makefile | 9 | ||||
-rw-r--r-- | board/starfive/visionfive/spl.c | 85 | ||||
-rw-r--r-- | board/starfive/visionfive/starfive_visionfive.c | 171 | ||||
-rw-r--r-- | include/configs/starfive-visionfive.h | 145 |
8 files changed, 518 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 52e99e03d3..63b0c328bd 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -23,6 +23,9 @@ config TARGET_SIFIVE_UNLEASHED config TARGET_SIFIVE_UNMATCHED bool "Support SiFive Unmatched Board" +config TARGET_STARFIVE_VISIONFIVE + bool "Support StarFive VisionFive Board" + config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" @@ -65,6 +68,7 @@ source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" +source "board/starfive/visionfive/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h new file mode 100644 index 0000000000..9b17e8bfe6 --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#ifndef __STARFIVE_JH7110_REGS_H +#define __STARFIVE_JH7110_REGS_H + +/*system control register*/ +#define STG_SYSCON_BASE 0x10240000 +#define SYS_SYSCON_BASE 0x13030000 +#define SYS_IOMUX_BASE 0x13040000 +#define AON_SYSCON_BASE 0x17010000 + +/*gmac cfg*/ +#define AON_SYSCFG_12 0xCU +#define SYS_SYSCON_144 0x90U +#define GMAC5_0_SEL_I_SHIFT 0x12U +#define GMAC5_0_SEL_I_MASK 0x1C0000U +#define GMAC5_1_SEL_I_SHIFT 0x2U +#define GMAC5_1_SEL_I_MASK 0x1CU + +/*usb cfg*/ +#define STG_SYSCON_4 0x4U +#define SYS_SYSCON_24 0x18U +#define SYS_IOMUX_32 0x80U +#define USB_MODE_STRAP_SHIFT 0x10U +#define USB_MODE_STRAP_MASK 0x70000U +#define USB_OTG_SUSPENDM_BYPS_SHIFT 0x14U +#define USB_OTG_SUSPENDM_BYPS_MASK 0x100000U +#define USB_OTG_SUSPENDM_SHIFT 0x13U +#define USB_OTG_SUSPENDM_MASK 0x80000U +#define USB_PLL_EN_SHIFT 0x16U +#define USB_PLL_EN_MASK 0x400000U +#define USB_REFCLK_MODE_SHIFT 0x17U +#define USB_REFCLK_MODE_MASK 0x800000U +#define PDRSTN_SPLIT_SHIFT 0x11U +#define PDRSTN_SPLIT_MASK 0x20000U +#define IOMUX_USB_SHIFT 0x10U +#define IOMUX_USB_MASK 0x7F0000U + +#endif /* __STARFIVE_JH7110_REGS_H */ + diff --git a/board/starfive/visionfive/Kconfig b/board/starfive/visionfive/Kconfig new file mode 100644 index 0000000000..d0ed065307 --- /dev/null +++ b/board/starfive/visionfive/Kconfig @@ -0,0 +1,52 @@ +if TARGET_STARFIVE_VISIONFIVE + +config SYS_CPU + default "jh7110" + +config SYS_BOARD + default "visionfive" + +config SYS_VENDOR + default "starfive" + +config SYS_CONFIG_NAME + default "starfive-visionfive" + +config ENV_SIZE + default 0x2000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x140000 if ENV_IS_IN_SPI_FLASH + +config SYS_TEXT_BASE + default 0x40200000 if SPL + default 0x40000000 if !RISCV_SMODE + default 0x40200000 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x08000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x80000000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select STARFIVE_JH7110 + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_GPT + imply PARTITION_TYPE_GUID + imply CMD_NET + imply CMD_PING + imply CMD_SF + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply PHY_LIB + imply PHY_MSCC + +endif diff --git a/board/starfive/visionfive/MAINTAINERS b/board/starfive/visionfive/MAINTAINERS new file mode 100644 index 0000000000..437f6c2d24 --- /dev/null +++ b/board/starfive/visionfive/MAINTAINERS @@ -0,0 +1,7 @@ +STARFIVE JH7110 VISIONFIVE BOARD +M: startfive +S: Maintained +F: arch/riscv/include/asm/arch-jh7110/ +F: board/starfive/visionfive/ +F: include/configs/starfive-visionfive.h +F: configs/starfive_visionfive_defconfig diff --git a/board/starfive/visionfive/Makefile b/board/starfive/visionfive/Makefile new file mode 100644 index 0000000000..739370cb2a --- /dev/null +++ b/board/starfive/visionfive/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Shanghai StarFive Technology Co., Ltd. +# + +obj-y := starfive_visionfive.o + +obj-$(CONFIG_SPL_BUILD) += spl.o + diff --git a/board/starfive/visionfive/spl.c b/board/starfive/visionfive/spl.c new file mode 100644 index 0000000000..d74ecb9690 --- /dev/null +++ b/board/starfive/visionfive/spl.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#include <common.h> +#include <init.h> +#include <spl.h> +#include <log.h> +#include <linux/delay.h> +#include <image.h> +#include <asm/arch/spl.h> +#include <asm/io.h> + +#define MODE_SELECT_REG 0x1702002c + +int spl_board_init_f(void) +{ + int ret; + + ret = spl_soc_init(); + if (ret) { + debug("JH7110 SPL init failed: %d\n", ret); + return ret; + } + + return 0; +} + +u32 spl_boot_device(void) +{ + int boot_mode = 0; + + boot_mode = readl((const volatile void *)MODE_SELECT_REG) & 0xF; + switch (boot_mode) { + case 0: + return BOOT_DEVICE_SPI; + case 1: + return BOOT_DEVICE_MMC2; + case 2: + return BOOT_DEVICE_MMC1; + case 4: + return BOOT_DEVICE_UART; + default: + debug("Unsupported boot device 0x%x.\n", + boot_mode); + return BOOT_DEVICE_NONE; + } +} + +struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) +{ + return (struct image_header *)(STARFIVE_SPL_BOOT_LOAD_ADDR); +} + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed: %d\n", ret); + + arch_cpu_init_dm(); + + preloader_console_init(); + + ret = spl_board_init_f(); + if (ret) { + debug("spl_board_init_f init failed: %d\n", ret); + return; + } +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif + + diff --git a/board/starfive/visionfive/starfive_visionfive.c b/board/starfive/visionfive/starfive_visionfive.c new file mode 100644 index 0000000000..6a8f8319a0 --- /dev/null +++ b/board/starfive/visionfive/starfive_visionfive.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/jh7110-regs.h> +#include <cpu_func.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <env.h> +#include <inttypes.h> +#include <misc.h> +#include <linux/bitops.h> +#include <asm/arch/gpio.h> + +#define SYS_IOMUX_DOEN(gpio, oen) \ + clrsetbits_le32(SYS_IOMUX_BASE+GPIO_OFFSET(gpio), \ + GPIO_DOEN_MASK << GPIO_SHIFT(gpio), \ + (oen) << GPIO_SHIFT(gpio)) + +#define SYS_IOMUX_DOUT(gpio, gpo) \ + clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DOUT + GPIO_OFFSET(gpio),\ + GPIO_DOUT_MASK << GPIO_SHIFT(gpio),\ + ((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio)) + +#define SYS_IOMUX_DIN(gpio, gpi)\ + clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DIN + GPIO_OFFSET(gpi),\ + GPIO_DIN_MASK << GPIO_SHIFT(gpi),\ + ((gpio+2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi)) + +#define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) do {\ + SYS_IOMUX_DOEN(gpio, oen);\ + SYS_IOMUX_DOUT(gpio, gpo);\ + SYS_IOMUX_DIN(gpio, gpi); }while(0) + +static void jh7110_gmac_init(int id) +{ + switch (id) { + case 0: + clrsetbits_le32(AON_SYSCON_BASE + AON_SYSCFG_12, + GMAC5_0_SEL_I_MASK, + BIT(GMAC5_0_SEL_I_SHIFT) & GMAC5_0_SEL_I_MASK); + break; + + case 1: + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_144, + GMAC5_1_SEL_I_MASK, + BIT(GMAC5_1_SEL_I_SHIFT) & GMAC5_1_SEL_I_MASK); + break; + + default: + break; + } +} + +static void jh7110_usb_init(void) +{ + clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4, + USB_MODE_STRAP_MASK, + (2<<USB_MODE_STRAP_SHIFT) & USB_MODE_STRAP_MASK); + clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4, + USB_OTG_SUSPENDM_BYPS_MASK, + BIT(USB_OTG_SUSPENDM_BYPS_SHIFT) + & USB_OTG_SUSPENDM_BYPS_MASK); + + clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4, + USB_OTG_SUSPENDM_MASK, + BIT(USB_OTG_SUSPENDM_SHIFT) & USB_OTG_SUSPENDM_MASK); + clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4, + USB_PLL_EN_MASK, + BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK); + clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4, + USB_REFCLK_MODE_MASK, + BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK); + + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, + PDRSTN_SPLIT_MASK, + BIT(PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK); + clrsetbits_le32(SYS_IOMUX_BASE + SYS_IOMUX_32, + IOMUX_USB_MASK, + BIT(IOMUX_USB_SHIFT) & IOMUX_USB_MASK); +} + +static void jh7110_mmc_init(int id) +{ + if (id == 0) { + SYS_IOMUX_DOEN(62, LOW); + SYS_IOMUX_DOUT(62, 19); + } else { + SYS_IOMUX_DOEN(10, LOW); + SYS_IOMUX_DOUT(10, 55); + SYS_IOMUX_COMPLEX(9, 44, 57, 19); + SYS_IOMUX_COMPLEX(11, 45, 58, 20); + SYS_IOMUX_COMPLEX(12, 46, 59, 21); + SYS_IOMUX_COMPLEX(7, 47, 60, 22); + SYS_IOMUX_COMPLEX(8, 48, 61, 23); + } +} + +/*enable U74-mc hart1~hart4 prefetcher*/ +static void enable_prefetcher(void) +{ + u32 hart; + u32 *reg; +#define L2_PREFETCHER_BASE_ADDR 0x2030000 +#define L2_PREFETCHER_OFFSET 0x2000 + + /*hart1~hart4*/ + for (hart = 1; hart < 5; hart++) { + reg = (u32 *)((u64)(L2_PREFETCHER_BASE_ADDR + + hart*L2_PREFETCHER_OFFSET)); + + mb(); /* memory barrier */ + setbits_le32(reg, 0x1); + mb(); /* memory barrier */ + } +} + +int board_init(void) +{ + enable_caches(); + + /*enable hart1-hart4 prefetcher*/ +// enable_prefetcher(); + + jh7110_gmac_init(0); + jh7110_gmac_init(1); + jh7110_usb_init(); + + jh7110_mmc_init(0); + jh7110_mmc_init(1); + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R + +int misc_init_r(void) +{ + char mac[6] = {0x66, 0x34, 0xb0, 0x6c, 0xde, 0xad }; + +#if CONFIG_IS_ENABLED(STARFIVE_OTP) + struct udevice *dev; + char buf[8]; + int ret; +#define MACADDR_OFFSET 0x8 + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(starfive_otp), &dev); + if (ret) { + debug("%s: could not find otp device\n", __func__); + goto err; + } + + ret = misc_read(dev, MACADDR_OFFSET, buf, sizeof(buf)); + if (ret) + printf("%s: error reading mac from OTP\n", __func__); + else + memcpy(mac, buf, 6); +err: +#endif + eth_env_set_enetaddr("ethaddr", mac); + + return 0; +} +#endif + diff --git a/include/configs/starfive-visionfive.h b/include/configs/starfive-visionfive.h new file mode 100644 index 0000000000..d1f66433f9 --- /dev/null +++ b/include/configs/starfive-visionfive.h @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Shanghai StarFive Technology Co., Ltd. + * YanHong Wang <yanhong.wang@starfivetech.com> + */ + + +#ifndef _STARFIVE_VISIONFIVE_H +#define _STARFIVE_VISIONFIVE_H + +#include <version.h> +#include <linux/sizes.h> + +#ifdef CONFIG_SPL + +#define CONFIG_SPL_MAX_SIZE 0x00040000 +#define CONFIG_SPL_BSS_START_ADDR 0x08040000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 + +#define CONFIG_SPL_STACK (0x08000000 + 0x00180000 - \ + GENERATED_GBL_DATA_SIZE) + +#define STARFIVE_SPL_BOOT_LOAD_ADDR 0xa0000000 +#endif + + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_BOOTM_LEN (32 << 20) /* 32MB */ + +/* + * Print Buffer Size + */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * max number of command args + */ +#define CONFIG_SYS_MAXARGS 16 + +/* + * Boot Argument Buffer Size + */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * Size of malloc() pool + * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough + */ +#define CONFIG_SYS_MALLOC_LEN SZ_8M + +#define CONFIG_NR_DRAM_BANKS 1 + +#define PHYS_SDRAM_0 0x40000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_0_SIZE 0x100000000 /* 8 GB */ + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_0) + + +/* Init Stack Pointer */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_16M) +#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 + +/* + * Ethernet + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_DW_ALTDESCRIPTOR +#define DWC_NET_PHYADDR 0 +#define CONFIG_ARP_TIMEOUT 0x5000 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.120.230 +#define CONFIG_IP_DEFRAG +#ifndef CONFIG_NET_MAXDEFRAG +#define CONFIG_NET_MAXDEFRAG 16384 +#endif +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* HACK these should have '#if defined (stuff) around them like zynqp*/ +#define BOOT_TARGET_DEVICES(func) func(DHCP, dhcp, na) func(MMC, mmc, 0) + +#include <config_distro_bootcmd.h> + + +#include <environment/distro/sf.h> + +#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47" +#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985" +#define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4" + +#define PARTS_DEFAULT \ + "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \ + "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \ + "name=system,size=-,bootable,type=${type_guid_gpt_system};" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x44000000\0" \ + "fdt_addr_r=0x46000000\0" \ + "scriptaddr=0x88100000\0" \ + "script_offset_f=0x1fff000\0" \ + "script_size_f=0x1000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ + "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ + "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ + "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ + "partitions=" PARTS_DEFAULT "\0" \ + BOOTENV \ + BOOTENV_SF + +/* + * memtest works on 1.9 MB in DRAM + */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) + +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600} +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* 6.25MHz RTC clock, StarFive JH7110*/ +#define CONFIG_SYS_HZ_CLOCK 4000000 + +#define __io + +#define memset_io(c, v, l) memset((c), (v), (l)) +#define memcpy_fromio(a, c, l) memcpy((a), (c), (l)) +#define memcpy_toio(c, a, l) memcpy((c), (a), (l)) + +#endif /* _STARFIVE_VISIONFIVE_H */ + |