diff options
| -rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 10 | ||||
| -rw-r--r-- | arch/riscv/dts/starfive_evb.dts | 2 |
2 files changed, 6 insertions, 6 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 415d8995e0..6ab4f48107 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -36,7 +36,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imac"; + riscv,isa = "rv64imacu"; tlb-split; status = "disabled"; @@ -63,7 +63,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdcbsux"; tlb-split; status = "okay"; @@ -90,7 +90,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdcbsux"; tlb-split; status = "okay"; @@ -117,7 +117,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdcbsux"; tlb-split; status = "okay"; @@ -144,7 +144,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdcbsux"; tlb-split; status = "okay"; diff --git a/arch/riscv/dts/starfive_evb.dts b/arch/riscv/dts/starfive_evb.dts index f4b22214fd..619317c3f4 100644 --- a/arch/riscv/dts/starfive_evb.dts +++ b/arch/riscv/dts/starfive_evb.dts @@ -9,7 +9,7 @@ / { #address-cells = <2>; #size-cells = <2>; - model = "StarFive EVB"; + model = "StarFive JH7110 EVB"; compatible = "starfive,jh7110"; aliases { |