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-rw-r--r--arch/riscv/cpu/jh7110/pll.c2
-rw-r--r--board/starfive/evb/spl.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/riscv/cpu/jh7110/pll.c b/arch/riscv/cpu/jh7110/pll.c
index decb0eede8..563259476a 100644
--- a/arch/riscv/cpu/jh7110/pll.c
+++ b/arch/riscv/cpu/jh7110/pll.c
@@ -279,7 +279,7 @@ static u64 pll_get_rate(enum starfive_pll_type pll,
fbdiv = GET_PLL(PLL0, FBDIV);
postdiv1 = 1 << GET_PLL(PLL0, POSTDIV1);
frac = GET_PLL(PLL0, FRAC);
- deffreq = 1250000000;
+ deffreq = 1000000000;
break;
case PLL1:
diff --git a/board/starfive/evb/spl.c b/board/starfive/evb/spl.c
index 8cab704031..8d07122719 100644
--- a/board/starfive/evb/spl.c
+++ b/board/starfive/evb/spl.c
@@ -61,8 +61,8 @@ void board_init_f(ulong dummy)
{
int ret;
- /* Adjust cpu frequency, the default is 1.25GHz */
- starfive_jh7110_pll_set_rate(PLL0, 1250000000);
+ /* Set pll0 cpufreq to 1000M */
+ starfive_jh7110_pll_set_rate(PLL0, 1000000000);
/*change pll2 to 1188MHz*/
starfive_jh7110_pll_set_rate(PLL2, 1188000000);