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-rw-r--r--README4
-rw-r--r--arch/x86/dts/link.dts18
-rw-r--r--board/chromebook-x86/coreboot/Makefile2
-rw-r--r--board/chromebook-x86/coreboot/coreboot.c16
-rw-r--r--drivers/misc/cros_ec_lpc.c4
-rw-r--r--include/configs/coreboot.h22
-rw-r--r--include/fdtdec.h1
-rw-r--r--lib/fdtdec.c1
-rw-r--r--net/tftp.c2
9 files changed, 59 insertions, 11 deletions
diff --git a/README b/README
index 19abe20035..6cf096cdf8 100644
--- a/README
+++ b/README
@@ -2830,10 +2830,6 @@ CBFS (Coreboot Filesystem) support
Enable auto completion of commands using TAB.
- Note that this feature has NOT been implemented yet
- for the "hush" shell.
-
-
CONFIG_SYS_HUSH_PARSER
Define this variable to enable the "hush" shell (from
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index 4a37dac4ea..67ce52a102 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -32,4 +32,22 @@
memory-map = <0xff800000 0x00800000>;
};
};
+
+ lpc {
+ compatible = "intel,lpc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cros-ec@200 {
+ compatible = "google,cros-ec";
+ reg = <0x204 1 0x200 1 0x880 0x80>;
+
+ /* This describes the flash memory within the EC */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash@8000000 {
+ reg = <0x08000000 0x20000>;
+ erase-value = <0xff>;
+ };
+ };
+ };
};
diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile
index 4f2ac898eb..27ebe78eb1 100644
--- a/board/chromebook-x86/coreboot/Makefile
+++ b/board/chromebook-x86/coreboot/Makefile
@@ -12,4 +12,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += coreboot_start.o
+obj-y += coreboot_start.o coreboot.o
diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/chromebook-x86/coreboot/coreboot.c
new file mode 100644
index 0000000000..0240c34581
--- /dev/null
+++ b/board/chromebook-x86/coreboot/coreboot.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+
+int arch_early_init_r(void)
+{
+ if (cros_ec_board_init())
+ return -1;
+
+ return 0;
+}
diff --git a/drivers/misc/cros_ec_lpc.c b/drivers/misc/cros_ec_lpc.c
index 0e02671c93..07624a136f 100644
--- a/drivers/misc/cros_ec_lpc.c
+++ b/drivers/misc/cros_ec_lpc.c
@@ -54,7 +54,7 @@ int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
int csum;
int i;
- if (dout_len > EC_HOST_PARAM_SIZE) {
+ if (dout_len > EC_PROTO2_MAX_PARAM_SIZE) {
debug("%s: Cannot send %d bytes\n", __func__, dout_len);
return -1;
}
@@ -159,7 +159,7 @@ int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob)
byte = 0xff;
byte &= inb(EC_LPC_ADDR_HOST_CMD);
byte &= inb(EC_LPC_ADDR_HOST_DATA);
- for (i = 0; i < EC_HOST_PARAM_SIZE && (byte == 0xff); i++)
+ for (i = 0; i < EC_PROTO2_MAX_PARAM_SIZE && (byte == 0xff); i++)
byte &= inb(EC_LPC_ADDR_HOST_PARAM + i);
if (byte == 0xff) {
debug("%s: CROS_EC device not found on LPC bus\n",
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 936be14511..200b744e4f 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -25,6 +25,7 @@
#define CONFIG_ZBOOT_32
#define CONFIG_PHYSMEM
#define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_LMB
#define CONFIG_OF_LIBFDT
@@ -39,6 +40,7 @@
#define CONFIG_BOOTSTAGE_USER_COUNT 60
#define CONFIG_LZO
+#define CONFIG_FIT
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
@@ -109,7 +111,8 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTOCOMPLETE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SUPPORT_VFAT
/************************************************************
@@ -192,6 +195,7 @@
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_ZBOOT
+#define CONFIG_CMD_ELF
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTARGS \
@@ -208,8 +212,7 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "boot > "
-#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + \
16)
@@ -218,7 +221,7 @@
#define CONFIG_SYS_MEMTEST_START 0x00100000
#define CONFIG_SYS_MEMTEST_END 0x01000000
-#define CONFIG_SYS_LOAD_ADDR 0x100000
+#define CONFIG_SYS_LOAD_ADDR 0x02000000
/*-----------------------------------------------------------------------
* SDRAM Configuration
@@ -283,6 +286,11 @@
*/
#define CONFIG_PCI
+#define CONFIG_CROS_EC
+#define CONFIG_CROS_EC_LPC
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_ARCH_EARLY_INIT_R
+
/*-----------------------------------------------------------------------
* USB configuration
*/
@@ -297,6 +305,12 @@
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_TFTP_TSIZE
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_CMD_USB
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 99cb353804..4ae77be9ba 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -117,6 +117,7 @@ enum fdt_compat_id {
COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */
COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */
COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */
+ COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 4f66ae172f..9714620ab3 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -72,6 +72,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"),
COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
COMPAT(PARADE_PS8625, "parade,ps8625"),
+ COMPAT(COMPAT_INTEL_LPC, "intel,lpc"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
diff --git a/net/tftp.c b/net/tftp.c
index 966d1cfba3..0a2c53302c 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -299,6 +299,8 @@ static void tftp_complete(void)
putc('#');
TftpNumchars++;
}
+ puts(" ");
+ print_size(TftpTsize, "");
#endif
time_start = get_timer(time_start);
if (time_start > 0) {