2356 files changed, 120571 insertions, 32605 deletions

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 3c1846a5bc..53a83eef7d 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -2,7 +2,7 @@ variables:
   windows_vm: windows-2019
   ubuntu_vm: ubuntu-22.04
   macos_vm: macOS-12
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230308-04Apr2023
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230624-20Jul2023
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
@@ -123,7 +123,7 @@ stages:
       options: $(container_option)
     steps:
       - script: |
-          ./tools/buildman/buildman -R
+          ./tools/buildman/buildman --maintainer-check || exit 0
 
   - job: tools_only
     displayName: 'Ensure host tools build'
@@ -162,6 +162,7 @@ stages:
           virtualenv -p /usr/bin/python3 /tmp/venv
           . /tmp/venv/bin/activate
           pip install -r test/py/requirements.txt
+          pip install -r tools/buildman/requirements.txt
           export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
           export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
           export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
@@ -194,7 +195,7 @@ stages:
           ln -s /opt/nokia/libc6_2.5.1-1eglibc27+0m5_armel.deb nokia_rx51_tmp/
           ln -s /opt/nokia/busybox_1.10.2.legal-1osso30+0m5_armel.deb nokia_rx51_tmp/
           ln -s /opt/nokia/qemu-system-arm nokia_rx51_tmp/
-          export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH
+          export PATH=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin:$PATH
           test/nokia_rx51_test.sh
 
   - job: pylint
@@ -209,6 +210,7 @@ stages:
           git config --global --add safe.directory $(work_dir)
           export USER=azure
           pip install -r test/py/requirements.txt
+          pip install -r tools/buildman/requirements.txt
           pip install asteval pylint==2.12.2 pyopenssl
           export PATH=${PATH}:~/.local/bin
           echo "[MASTER]" >> .pylintrc
@@ -391,12 +393,12 @@ stages:
           grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
           grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
           if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
-              wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
-              export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
+              wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
+              export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
           fi
           if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
-              wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
-              export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
+              wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
+              export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
           fi
           # the below corresponds to .gitlab-ci.yml "script"
           cd ${WORK_DIR}
@@ -404,6 +406,7 @@ stages:
           if [ -n "${BUILD_ENV}" ]; then
               export ${BUILD_ENV};
           fi
+          pip install -r tools/buildman/requirements.txt
           tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board ${TEST_PY_BD} ${OVERRIDE}
           cp ~/grub_x86.efi ${UBOOT_TRAVIS_BUILD_DIR}/
           cp ~/grub_x64.efi ${UBOOT_TRAVIS_BUILD_DIR}/
@@ -423,7 +426,7 @@ stages:
               cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
           fi
           if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
-              wget -O - "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
+              wget -O - "https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
               wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >cbfstool;
               chmod a+x cbfstool;
               ./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
@@ -460,6 +463,7 @@ stages:
           fi
           # Some tests using libguestfs-tools need the fuse device to run
           docker run "$@" --device /dev/fuse:/dev/fuse -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/test.sh
+        retryCountOnTaskFailure: 2 # QEMU may be too slow, etc.
 
 - stage: world_build
   jobs:
@@ -471,8 +475,8 @@ stages:
       # Use almost the same target division in .travis.yml, only merged
       # 3 small build jobs (arc/microblaze/xtensa) into one.
       matrix:
-        arc_microblaze_xtensa:
-          BUILDMAN: "arc microblaze xtensa"
+        arc_nios2_m68k_microblaze_xtensa:
+          BUILDMAN: "arc nios2 microblaze m68k xtensa"
         amlogic:
           BUILDMAN: "amlogic"
         arm11_arm7_arm920t_arm946es:
@@ -489,88 +493,64 @@ stages:
           BUILDMAN: "bcm -x mips"
         nxp_arm32:
           BUILDMAN: "freescale -x powerpc,m68k,aarch64,ls101,ls102,ls104,ls108,ls20,lx216"
-        nxp_ls101x:
-          BUILDMAN: "freescale&ls101"
+        nxp_ls101x_ls108x:
+          BUILDMAN: "freescale&ls101 freescale&ls108"
         nxp_ls102x:
-          BUILDMAN: "freescale&ls102"
+          BUILDMAN: "freescale&ls102 -x keymile"
         nxp_ls104x:
           BUILDMAN: "freescale&ls104"
-        nxp_ls108x:
-          BUILDMAN: "freescale&ls108"
-        nxp_ls20xx:
-          BUILDMAN: "freescale&ls20"
-        nxp_lx216x:
-          BUILDMAN: "freescale&lx216"
+        nxp_ls20xx_lx216x:
+          BUILDMAN: "freescale&ls20 freescale&lx216"
         imx6:
           BUILDMAN: "mx6 -x boundary,engicam,freescale,technexion,toradex"
         imx:
           BUILDMAN: "mx -x mx6,imx8,freescale,technexion,toradex"
         imx8_imx9:
-          BUILDMAN: "imx8 imx9"
+          BUILDMAN: "imx8 imx9 -x engicam,technexion,toradex"
+        keymiles_siemens_technexion:
+          BUILDMAN: "keymile siemens technexion"
         keystone2_keystone3:
-          BUILDMAN: "k2 k3"
+          BUILDMAN: "k2 k3 -x siemens,toradex"
         sandbox_asan:
           BUILDMAN: "sandbox"
           OVERRIDE: "-a ASAN"
         sandbox_clang_asan:
           BUILDMAN: "sandbox"
           OVERRIDE: "-O clang-16 -a ASAN"
-        samsung_socfpga:
-          BUILDMAN: "samsung socfpga"
-        sun4i:
-          BUILDMAN: "sun4i"
-        sun5i:
-          BUILDMAN: "sun5i"
-        sun6i:
-          BUILDMAN: "sun6i"
+        samsung_socfpga_renesas:
+          BUILDMAN: "samsung socfpga renesas"
+        sun4i_sun9i:
+          BUILDMAN: "sun4i sun9i"
+        sun5i_sun6i:
+          BUILDMAN: "sun5i sun6i"
         sun7i:
           BUILDMAN: "sun7i"
-        sun8i_32bit:
-          BUILDMAN: "sun8i&armv7"
-        sun8i_64bit:
-          BUILDMAN: "sun8i&aarch64"
-        sun9i:
-          BUILDMAN: "sun9i"
+        sun8i:
+          BUILDMAN: "sun8i"
         sun50i:
           BUILDMAN: "sun50i"
         arm_catch_all:
-          BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,renesas,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rk,toradex,socfpga,k2,k3,zynq"
+          BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,renesas,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,toradex,socfpga,k2,k3,zynq"
         sandbox_x86:
           BUILDMAN: "sandbox x86"
-        technexion:
-          BUILDMAN: "technexion"
-        kirkwood:
-          BUILDMAN: "kirkwood"
-        mvebu:
-          BUILDMAN: "mvebu"
-        m68k:
-          BUILDMAN: "m68k"
+        kirkwood_mvebu_uniphier:
+          BUILDMAN: "kirkwood mvebu uniphier"
         mips:
           BUILDMAN: "mips"
         powerpc:
-          BUILDMAN: "powerpc"
-        siemens:
-          BUILDMAN: "siemens"
+          BUILDMAN: "powerpc -x keymile"
         tegra:
           BUILDMAN: "tegra -x toradex"
-        am33xx_no_siemens:
-          BUILDMAN: "am33xx -x siemens"
-        omap:
-          BUILDMAN: "omap"
-        uniphier:
-          BUILDMAN: "uniphier"
+        am33xx_omap:
+          BUILDMAN: "am33xx omap -x siemens"
         aarch64_catch_all:
           BUILDMAN: "aarch64 -x amlogic,bcm,imx8,imx9,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq"
-        rockchip_32bit:
-          BUILDMAN: "rk -x aarch64"
-        rockchip_64bit:
-          BUILDMAN: "rk&aarch64"
-        renesas:
-          BUILDMAN: "renesas"
-        zynq:
-          BUILDMAN: "zynq&armv7"
-        zynqmp_versal:
-          BUILDMAN: "versal|zynqmp&aarch64"
+        rk_non_rockchip_64bit:
+          BUILDMAN: "rk&aarch64 -x rockchip"
+        rk_rockchip_64bit:
+          BUILDMAN: "rk&aarch64&rockchip"
+        zynq_zynqmp_versal:
+          BUILDMAN: "zynq&armv7 versal zynqmp&aarch64"
         riscv:
           BUILDMAN: "riscv"
     steps:
@@ -581,6 +561,7 @@ stages:
           # make environment variables available as tests are running inside a container
           export BUILDMAN="${BUILDMAN}"
           git config --global --add safe.directory ${WORK_DIR}
+          pip install -r tools/buildman/requirements.txt
           EOF
           cat << "EOF" >> build.sh
           if [[ "${BUILDMAN}" != "" ]]; then
diff --git a/.get_maintainer.ignore b/.get_maintainer.ignore
new file mode 100644
index 0000000000..899a1469b2
--- /dev/null
+++ b/.get_maintainer.ignore
@@ -0,0 +1 @@
+"Pali Rohár" <pali@kernel.org>
diff --git a/.gitignore b/.gitignore
index 3a4d056edf..002f95de4f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -53,6 +53,7 @@ fit-dtb.blob*
 #
 !.gitignore
 !.mailmap
+!.get_maintainer.*
 
 #
 # Generated files
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index e6c6ab3586..1df13261c2 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -10,7 +10,7 @@ default:
 
 # Grab our configured image.  The source for this is found
 # in the u-boot tree at tools/docker/Dockerfile
-image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230308-04Apr2023
+image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230624-20Jul2023
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -20,6 +20,7 @@ stages:
 
 .buildman_and_testpy_template: &buildman_and_testpy_dfn
   stage: test.py
+  retry: 2 # QEMU may be too slow, etc.
   before_script:
     # Clone uboot-test-hooks
     - git config --global --add safe.directory "${CI_PROJECT_DIR}"
@@ -29,12 +30,12 @@ stages:
     - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
     - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
     - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
-        wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
-        export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
+        wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
+        export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
       fi
     - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
-        wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
-        export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
+        wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
+        export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
       fi
 
   after_script:
@@ -68,7 +69,7 @@ stages:
       fi
     - if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
         wget -O -
-          "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |
+          "https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |
           xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
         wget -O -
           "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >
@@ -97,6 +98,7 @@ build all 32bit ARM platforms:
   script:
     - ret=0;
       git config --global --add safe.directory "${CI_PROJECT_DIR}";
+      pip install -r tools/buildman/requirements.txt;
       ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 || ret=$?;
       if [[ $ret -ne 0 ]]; then
         ./tools/buildman/buildman -o /tmp -seP;
@@ -110,6 +112,7 @@ build all 64bit ARM platforms:
     - . /tmp/venv/bin/activate
     - ret=0;
       git config --global --add safe.directory "${CI_PROJECT_DIR}";
+      pip install -r tools/buildman/requirements.txt;
       ./tools/buildman/buildman -o /tmp -PEWM aarch64 || ret=$?;
       if [[ $ret -ne 0 ]]; then
         ./tools/buildman/buildman -o /tmp -seP;
@@ -184,7 +187,7 @@ sloccount:
 Check for configs without MAINTAINERS entry:
   stage: testsuites
   script:
-    - ./tools/buildman/buildman -R
+    - ./tools/buildman/buildman --maintainer-check || exit 0
 
 # Ensure host tools build
 Build tools-only:
@@ -208,6 +211,7 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
       virtualenv -p /usr/bin/python3 /tmp/venv;
       . /tmp/venv/bin/activate;
       pip install -r test/py/requirements.txt;
+      pip install -r tools/buildman/requirements.txt;
       export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl;
       export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
       export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
@@ -231,7 +235,7 @@ Run tests for Nokia RX-51 (aka N900):
       ln -s /opt/nokia/libc6_2.5.1-1eglibc27+0m5_armel.deb nokia_rx51_tmp/;
       ln -s /opt/nokia/busybox_1.10.2.legal-1osso30+0m5_armel.deb nokia_rx51_tmp/;
       ln -s /opt/nokia/qemu-system-arm nokia_rx51_tmp/;
-      export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH;
+      export PATH=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin:$PATH;
       test/nokia_rx51_test.sh
 
 # Check for any pylint regressions
@@ -240,6 +244,7 @@ Run pylint:
   script:
     - git config --global --add safe.directory "${CI_PROJECT_DIR}"
     - pip install -r test/py/requirements.txt
+    - pip install -r tools/buildman/requirements.txt
     - pip install asteval pylint==2.12.2 pyopenssl
     - export PATH=${PATH}:~/.local/bin
     - echo "[MASTER]" >> .pylintrc
diff --git a/.mailmap b/.mailmap
index 312a428dc9..05cb310e41 100644
--- a/.mailmap
+++ b/.mailmap
@@ -65,8 +65,8 @@ Marek Vasut <marex@denx.de> <marek.vasut+renesas@gmail.com>
 Marek Vasut <marex@denx.de> <marek.vasut@gmail.com>
 Marek Vasut <marex@denx.de> <marex at denx.de>
 Markus Klotzbuecher <mk@denx.de>
-Masahiro Yamada <yamada.masahiro@socionext.com> <masahiroy@kernel.org>
-Masahiro Yamada <yamada.masahiro@socionext.com> <yamada.m@jp.panasonic.com>
+Masahiro Yamada <masahiroy@kernel.org> <yamada.masahiro@socionext.com>
+Masahiro Yamada <masahiroy@kernel.org> <yamada.m@jp.panasonic.com>
 Michal Simek <michal.simek@amd.com> <Monstr@seznam.cz>
 Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
 Michal Simek <michal.simek@amd.com> <monstr@monstr.eu>
diff --git a/Kconfig b/Kconfig
index 70efb41cc6..91170bf8d2 100644
--- a/Kconfig
+++ b/Kconfig
@@ -298,7 +298,7 @@ config SYS_MALLOC_LEN
 config SPL_SYS_MALLOC_F_LEN
 	hex "Size of malloc() pool in SPL"
 	depends on SYS_MALLOC_F && SPL
-	default 0 if !SPL_FRAMEWORK
+	default 0x0 if !SPL_FRAMEWORK
 	default 0x2800 if RCAR_GEN3
 	default 0x2000 if IMX8MQ
 	default SYS_MALLOC_F_LEN
diff --git a/MAINTAINERS b/MAINTAINERS
index 228d8af433..84de9de531 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -132,6 +132,7 @@ M:	Tom Rini <trini@konsulko.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-arm.git
 F:	arch/arm/
+F:	arch/arm/dts/Makefile
 F:	cmd/arm/
 
 ARM ALTERA SOCFPGA
@@ -266,12 +267,26 @@ F:	drivers/net/cortina_ni.h
 F:	drivers/net/phy/ca_phy.c
 F:	configs/cortina_presidio-asic-pnand_defconfig
 
+ARM FF-A
+M:	Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+S:	Maintained
+F:	arch/sandbox/include/asm/sandbox_arm_ffa.h
+F:	arch/sandbox/include/asm/sandbox_arm_ffa_priv.h
+F:	cmd/armffa.c
+F:	doc/arch/arm64.ffa.rst
+F:	doc/usage/cmd/armffa.rst
+F:	drivers/firmware/arm-ffa/
+F:	include/arm_ffa.h
+F:	test/cmd/armffa.c
+F:	test/dm/ffa.c
+
 ARM FREESCALE IMX
 M:	Stefano Babic <sbabic@denx.de>
 M:	Fabio Estevam <festevam@gmail.com>
 R:	NXP i.MX U-Boot Team <uboot-imx@nxp.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-imx.git
+F:	arch/Kconfig.nxp
 F:	arch/arm/cpu/arm1136/mx*/
 F:	arch/arm/cpu/arm926ejs/mx*/
 F:	arch/arm/cpu/armv7/vf610/
@@ -282,6 +297,7 @@ F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
 F:	arch/arm/include/asm/mach-imx/
 F:	board/freescale/*mx*/
+F:	board/freescale/common/
 F:	drivers/serial/serial_mxc.c
 
 ARM HISILICON
@@ -343,6 +359,7 @@ F:	drivers/rtc/armada38x.c
 F:	drivers/spi/kirkwood_spi.c
 F:	drivers/spi/mvebu_a3700_spi.c
 F:	drivers/pci/pcie_dw_mvebu.c
+F:	drivers/pci/pcie-xilinx-nwl.c
 F:	drivers/watchdog/armada-37xx-wdt.c
 F:	drivers/watchdog/orion_wdt.c
 F:	include/configs/mv-common.h
@@ -408,14 +425,22 @@ F:	configs/uDPU_defconfig
 ARM MICROCHIP/ATMEL AT91
 M:	Eugen Hristev <eugen.hristev@microchip.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-atmel.git
+T:	git https://source.denx.de/u-boot/custodians/u-boot-at91.git
+F:	arch/arm/dts/at91*
+F:	arch/arm/dts/sam*
 F:	arch/arm/mach-at91/
 F:	board/atmel/
 F:	drivers/cpu/at91_cpu.c
 F:	drivers/memory/atmel-ebi.c
 F:	drivers/misc/microchip_flexcom.c
 F:	drivers/timer/atmel_tcb_timer.c
+F:	include/dt-bindings/clk/at91.h
+F:	include/dt-bindings/clock/at91.h
+F:	include/dt-bindings/dma/at91.h
+F:	include/dt-bindings/mfd/at91-usart.h
 F:	include/dt-bindings/mfd/atmel-flexcom.h
+F:	include/dt-bindings/pinctrl/at91.h
+F:	include/dt-bindings/sound/microchip,pdmc.h
 F:	drivers/timer/mchp-pit64b-timer.c
 
 ARM MSC SM2S IMX8MP SOM
@@ -459,10 +484,30 @@ F:	configs/cubieboard7_defconfig
 
 ARM RENESAS RMOBILE/R-CAR
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-sh.git
 F:	arch/arm/mach-rmobile/
+F:	drivers/clk/renesas/
+F:	drivers/gpio/gpio-rcar.c
+F:	drivers/i2c/rcar_*
+F:	drivers/i2c/sh_i2c.c
+F:	drivers/mmc/renesas-sdhi.c
+F:	drivers/mmc/sh_mmcif*
+F:	drivers/mmc/tmio-common*
+F:	drivers/mtd/renesas_rpc_hf.c
+F:	drivers/net/ravb.c
+F:	drivers/net/rswitch.c
+F:	drivers/net/sh_eth*
+F:	drivers/pci/pci-rcar-*
+F:	drivers/phy/phy-rcar-*
+F:	drivers/phy/renesas/
+F:	drivers/pinctrl/renesas/
+F:	drivers/serial/serial_sh*
+F:	drivers/spi/renesas_rpc_spi.c
+F:	drivers/spi/sh_qspi.c
+F:	drivers/sysinfo/rcar3.c
+F:	drivers/usb/host/xhci-rcar*
 
 ARM ROCKCHIP
 M:	Simon Glass <sjg@chromium.org>
@@ -470,12 +515,24 @@ M:	Philipp Tomsich <philipp.tomsich@vrull.eu>
 M:	Kever Yang <kever.yang@rock-chips.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-rockchip.git
+F:	arch/arm/dts/px30*
 F:	arch/arm/dts/rk3*
 F:	arch/arm/dts/rockchip*
-F:	arch/arm/dts/rv1108*
+F:	arch/arm/dts/rv11*
 F:	arch/arm/include/asm/arch-rockchip/
 F:	arch/arm/mach-rockchip/
+F:	board/amarula/vyasa-rk3288/
+F:	board/anbernic/rgxx3_rk3566/
+F:	board/chipspark/popmetal_rk3288
+F:	board/engicam/px30_core/
+F:	board/firefly/
+F:	board/mqmaker/miqi_rk3288/
+F:	board/phytec/phycore_rk3288
+F:	board/pine64
+F:	board/radxa/
 F:	board/rockchip/
+F:	board/theobroma-systems
+F:	board/vamrs/rock960_rk3399/
 F:	drivers/clk/rockchip/
 F:	drivers/gpio/rk_gpio.c
 F:	drivers/misc/rockchip-efuse.c
@@ -577,6 +634,7 @@ F:	include/dt-bindings/clock/stm32mp*
 F:	include/dt-bindings/pinctrl/stm32-pinfunc.h
 F:	include/dt-bindings/reset/stm32mp*
 F:	include/stm32_rcc.h
+F:	tools/logos/st.bmp
 F:	tools/stm32image.c
 N:	stm
 N:	stm32
@@ -755,6 +813,7 @@ F:	drivers/spi/zynq_qspi.c
 F:	drivers/spi/zynq_spi.c
 F:	drivers/timer/cadence-ttc.c
 F:	drivers/video/seps525.c
+F:	drivers/video/zynqmp/
 F:	drivers/watchdog/cdns_wdt.c
 F:	include/zynqmppl.h
 F:	include/zynqmp_firmware.h
@@ -838,6 +897,13 @@ M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	tools/buildman/
 
+CAAM
+M:	Gaurav Jain <gaurav.jain@nxp.com>
+S:	Maintained
+F:	arch/arm/dts/ls1021a-twr-u-boot.dtsi
+F:	drivers/crypto/fsl/
+F:	include/fsl_sec.h
+
 CAT
 M:	Roger Knecht <rknecht@pm.me>
 S:	Maintained
@@ -865,6 +931,7 @@ S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
 F:	arch/m68k/
 F:	doc/arch/m68k.rst
+F:	drivers/watchdog/mcf_wdt.c
 
 CYCLIC
 M:	Stefan Roese <sr@denx.de>
@@ -1328,7 +1395,7 @@ F:	doc/arch/riscv.rst
 F:	doc/usage/sbi.rst
 F:	drivers/sysreset/sysreset_sbi.c
 F:	drivers/timer/andes_plmt_timer.c
-F:	drivers/timer/sifive_clint_timer.c
+F:	drivers/timer/riscv_aclint_timer.c
 F:	tools/prelink-riscv.c
 
 RISC-V CANAAN KENDRYTE K210
@@ -1532,7 +1599,8 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-ubi.git
 F:	drivers/mtd/ubi/
 
 UFS
-M:	Faiz Abbas <faiz_abbas@ti.com>
+M:	Bhupesh Sharma <bhupesh.sharma@linaro.org>
+M:	Neha Malcom Francis <n-francis@ti.com>
 S:	Maintained
 F:	drivers/ufs/
 
@@ -1553,6 +1621,11 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-usb.git topic-xhci
 F:	drivers/usb/host/xhci*
 F:	include/usb/xhci.h
 
+UUID testing
+M:	Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+S:	Maintained
+F:	test/lib/uuid.c
+
 VIDEO
 M:	Anatolij Gustschin <agust@denx.de>
 S:	Maintained
@@ -1625,10 +1698,3 @@ T:	git https://source.denx.de/u-boot/u-boot.git
 F:	configs/tools-only_defconfig
 F:	*
 F:	*/
-
-CAAM
-M:	Gaurav Jain <gaurav.jain@nxp.com>
-S:	Maintained
-F:	arch/arm/dts/ls1021a-twr-u-boot.dtsi
-F:	drivers/crypto/fsl/
-F:	include/fsl_sec.h
diff --git a/Makefile b/Makefile
index 444baaefd0..3954d86a26 100644
--- a/Makefile
+++ b/Makefile
@@ -1,9 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 VERSION = 2023
-PATCHLEVEL = 07
+PATCHLEVEL = 10
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc2
 NAME =
 
 # *DOCUMENTATION*
@@ -423,7 +423,8 @@ DTC_MIN_VERSION	:= 010406
 CHECK		= sparse
 
 CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
-		  -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
+		  -Wbitwise -Wno-return-void -Wno-unknown-attribute \
+		  -D__CHECK_ENDIAN__ $(CF)
 
 KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__
 
@@ -1032,6 +1033,9 @@ ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),)
 LDFLAGS_u-boot += -Ttext $(CONFIG_TEXT_BASE)
 endif
 
+# make the checker run with the right architecture
+CHECKFLAGS += --arch=$(ARCH)
+
 # insure the checker run with the right endianness
 CHECKFLAGS += $(if $(CONFIG_CPU_BIG_ENDIAN),-mbig-endian,-mlittle-endian)
 
@@ -1324,13 +1328,18 @@ u-boot.ldr:	u-boot
 # Use 'make BINMAN_VERBOSE=3' to set vebosity level
 default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
 
+# Temporary workaround for Venice boards
+ifneq ($(CONFIG_TARGET_IMX8MM_VENICE),$(CONFIG_TARGET_IMX8MN_VENICE),$(CONFIG_TARGET_IMX8MP_VENICE),)
+ignore_dups := --ignore-dup-phandles
+endif
+
 quiet_cmd_binman = BINMAN  $@
 cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
 		$(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \
                 --toolpath $(objtree)/tools \
 		$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
 		build -u -d u-boot.dtb -O . -m \
-		$(if $(BINMAN_ALLOW_MISSING),--allow-missing --ignore-missing) \
+		--allow-missing $(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
 		-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
 		-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
 		$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
@@ -1345,6 +1354,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
 		-a spl-dtb=$(CONFIG_SPL_OF_REAL) \
 		-a tpl-dtb=$(CONFIG_TPL_OF_REAL) \
 		-a pre-load-key-path=${PRE_LOAD_KEY_PATH} \
+		$(ignore_dups) \
 		$(BINMAN_$(@F))
 
 OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
@@ -1808,7 +1818,7 @@ quiet_cmd_gen_envp = ENVP    $@
 		rm -f $@; \
 		touch $@ ; \
 	fi
-include/generated/env.in: include/generated/env.txt FORCE
+include/generated/env.in: include/generated/env.txt
 	$(call cmd,gen_envp)
 
 # Regenerate the environment if it changes
@@ -1826,7 +1836,7 @@ quiet_cmd_envc = ENVC    $@
 		touch $@ ; \
 	fi
 
-include/generated/env.txt: $(wildcard $(ENV_FILE)) FORCE
+include/generated/env.txt: $(wildcard $(ENV_FILE))
 	$(call cmd,envc)
 
 # Write out the resulting environment, converted to a C string
@@ -2148,7 +2158,7 @@ CHANGELOG:
 
 # Directories & files removed with 'make clean'
 CLEAN_DIRS  += $(MODVERDIR) \
-	       $(foreach d, spl tpl, $(patsubst %,$d/%, \
+	       $(foreach d, spl tpl vpl, $(patsubst %,$d/%, \
 			$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
 
 CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
@@ -2163,7 +2173,7 @@ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
 	       idbloader-spi.img lib/efi_loader/helloworld_efi.S
 
 # Directories & files removed with 'make mrproper'
-MRPROPER_DIRS  += include/config include/generated spl tpl \
+MRPROPER_DIRS  += include/config include/generated spl tpl vpl \
 		  .tmp_objdiff doc/output include/asm
 
 # Remove include/asm symlink created by U-Boot before v2014.01
@@ -2440,7 +2450,7 @@ quiet_cmd_genenv = GENENV  $@
 cmd_genenv = \
 	$(objtree)/tools/printinitialenv | \
 	sed -e '/^\s*$$/d' | \
-	sort --field-separator== -k1,1 --stable -o $@
+	sort -t '=' -k 1,1 -s -o $@
 
 u-boot-initial-env: $(env_h) FORCE
 	$(Q)$(MAKE) $(build)=tools $(objtree)/tools/printinitialenv
diff --git a/README b/README
index bbf96e64c8..15a19caf74 100644
--- a/README
+++ b/README
@@ -2430,27 +2430,6 @@ Hit 'q':
 	[q, b, e, ?] ## Application terminated, rc = 0x0
 
 
-Minicom warning:
-================
-
-Over time, many people have reported problems when trying to use the
-"minicom" terminal emulation program for serial download. I (wd)
-consider minicom to be broken, and recommend not to use it. Under
-Unix, I recommend to use C-Kermit for general purpose use (and
-especially for kermit binary protocol download ("loadb" command), and
-use "cu" for S-Record download ("loads" command).  See
-https://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3.
-for help with kermit.
-
-
-Nevertheless, if you absolutely want to use it try adding this
-configuration to your "File transfer protocols" section:
-
-	   Name	   Program			Name U/D FullScr IO-Red. Multi
-	X  kermit  /usr/bin/kermit -i -l %l -s	 Y    U	   Y	   N	  N
-	Y  kermit  /usr/bin/kermit -i -l %l -r	 N    D	   Y	   N	  N
-
-
 Implementation Internals:
 =========================
 
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 6e1c44b7ea..5a8c382ed7 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -45,7 +45,7 @@ config ESBC_HDR_LS
 
 config ESBC_ADDR_64BIT
 	def_bool y
-	depends on ESBC_HDR_LS && FSL_LAYERSCAPE
+	depends on FSL_LAYERSCAPE
 	help
 	  For Layerscape based platforms, ESBC image Address in Header is 64bit.
 
@@ -90,7 +90,7 @@ config SPL_UBOOT_KEY_HASH
 	default ""
 	help
 	  Set the key hash for U-Boot here if public/private key pair used to
-	  sign U-boot are different from the SRK hash put in the fuse.  Example
+	  sign U-Boot are different from the SRK hash put in the fuse.  Example
 	  of a key hash is
 	  41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
 	  Otherwise leave this empty.
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index 6adc0ed42b..c818b8bdae 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -80,7 +80,7 @@ static inline void sync(void)
 
 /*
  * We add memory barriers for __raw_readX / __raw_writeX accessors same way as
- * it is done for readX and writeX accessors as lots of U-boot driver uses
+ * it is done for readX and writeX accessors as lots of U-Boot driver uses
  * __raw_readX / __raw_writeX instead of proper accessor with barrier.
  */
 #define __raw_writeb(v, c)	({ __iowmb(); __arch_putb(v, c); })
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 99264a6478..97c25b4f14 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -357,7 +357,7 @@ config SYS_ARM_ARCH
 
 choice
 	prompt "Select the ARM data write cache policy"
-	default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || TARGET_BCMNS || RZA1
+	default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMNS || RZA1
 	default SYS_ARM_CACHE_WRITEBACK
 
 config SYS_ARM_CACHE_WRITEBACK
@@ -668,19 +668,6 @@ config TARGET_VEXPRESS_CA9X4
 	select CPU_V7A
 	select PL011_SERIAL
 
-config TARGET_BCMCYGNUS
-	bool "Support bcmcygnus"
-	select CPU_V7A
-	select GPIO_EXTRA_HEADER
-	select IPROC
-	imply BCM_SF2_ETH
-	imply BCM_SF2_ETH_GMAC
-	imply CMD_HASH
-	imply CRC32_VERIFY
-	imply FAT_WRITE
-	imply HASH_VERIFY
-	imply NETDEVICES
-
 config TARGET_BCMNS
 	bool "Support Broadcom Northstar"
 	select CPU_V7A
@@ -798,6 +785,8 @@ config ARCH_K3
 	select SPL
 	select SUPPORT_SPL
 	select FIT
+	select REGEX
+	select FIT_SIGNATURE if ARM64
 
 config ARCH_OMAP2PLUS
 	bool "TI OMAP2+"
@@ -882,7 +871,7 @@ config ARCH_IMX8ULP
 	select SUPPORT_SPL
 	select GPIO_EXTRA_HEADER
 	select MISC
-	select IMX_SENTINEL
+	select IMX_ELE
 	imply CMD_DM
 
 config ARCH_IMX9
@@ -894,7 +883,7 @@ config ARCH_IMX9
 	select SUPPORT_SPL
 	select GPIO_EXTRA_HEADER
 	select MISC
-	select IMX_SENTINEL
+	select IMX_ELE
 	imply CMD_DM
 
 config ARCH_IMXRT
@@ -912,14 +901,12 @@ config ARCH_MX23
 	select CPU_ARM926EJS
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
-	select PL011_SERIAL
 	select SUPPORT_SPL
 
 config ARCH_MX28
 	bool "NXP i.MX28 family"
 	select CPU_ARM926EJS
 	select GPIO_EXTRA_HEADER
-	select PL011_SERIAL
 	select MACH_IMX
 	select SUPPORT_SPL
 
diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
index ffe35111d5..1e16b89d00 100644
--- a/arch/arm/cpu/arm11/cpu.c
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -20,6 +20,7 @@
 #include <irq_func.h>
 #include <asm/cache.h>
 #include <asm/system.h>
+#include <asm/arm11.h>
 
 static void cache_flush(void);
 
@@ -43,6 +44,11 @@ int cleanup_before_linux (void)
 	return 0;
 }
 
+void allow_unaligned(void)
+{
+	arm11_arch_cp15_allow_unaligned();
+}
+
 static void cache_flush(void)
 {
 	unsigned long i = 0;
diff --git a/arch/arm/cpu/arm11/sctlr.S b/arch/arm/cpu/arm11/sctlr.S
index 74a7fc4a25..8722f8380c 100644
--- a/arch/arm/cpu/arm11/sctlr.S
+++ b/arch/arm/cpu/arm11/sctlr.S
@@ -8,7 +8,7 @@
 #include <linux/linkage.h>
 
 /*
- * void allow_unaligned(void) - allow unaligned access
+ * void arm11_arch_cp15_allow_unaligned(void) - allow unaligned access
  *
  * This routine sets the enable unaligned data support flag and clears the
  * aligned flag in the system control register.
@@ -16,10 +16,10 @@
  * data abort or undefined behavior but is handled by the CPU.
  * For details see the "ARM Architecture Reference Manual" for ARMv6.
  */
-ENTRY(allow_unaligned)
+ENTRY(arm11_arch_cp15_allow_unaligned)
 	mrc	p15, 0, r0, c1, c0, 0	@ load system control register
 	orr	r0, r0, #1 << 22	@ set unaligned data support flag
 	bic	r0, r0, #2		@ clear aligned flag
 	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
 	bx	lr			@ return
-ENDPROC(allow_unaligned)
+ENDPROC(arm11_arch_cp15_allow_unaligned)
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 763d79e803..5598c552ab 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -128,8 +128,10 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
 
 	mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
 
-	mxs_spl_console_init();
-	debug("SPL: Serial Console Initialised\n");
+	if (!CONFIG_IS_ENABLED(DM_SERIAL)) {
+		mxs_spl_console_init();
+		debug("SPL: Serial Console Initialised\n");
+	}
 
 	mxs_power_init();
 
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index c33170f06d..7ea029e371 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -41,6 +41,29 @@ static void mxs_power_clock2xtal(void)
 		&clkctrl_regs->hw_clkctrl_clkseq_set);
 }
 
+static void mxs_power_regs_dump(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	debug("ctrl:\t\t 0x%x\n", readl(&power_regs->hw_power_ctrl));
+	debug("5vctrl:\t\t 0x%x\n", readl(&power_regs->hw_power_5vctrl));
+	debug("minpwr:\t\t 0x%x\n", readl(&power_regs->hw_power_minpwr));
+	debug("charge:\t\t 0x%x\n", readl(&power_regs->hw_power_charge));
+	debug("vddctrl:\t 0x%x\n", readl(&power_regs->hw_power_vdddctrl));
+	debug("vddactrl:\t 0x%x\n", readl(&power_regs->hw_power_vddactrl));
+	debug("vddioctrl:\t 0x%x\n", readl(&power_regs->hw_power_vddioctrl));
+	debug("vddmemctrl:\t 0x%x\n", readl(&power_regs->hw_power_vddmemctrl));
+	debug("dcdc4p2:\t 0x%x\n", readl(&power_regs->hw_power_dcdc4p2));
+	debug("misc:\t\t 0x%x\n", readl(&power_regs->hw_power_misc));
+	debug("dclimits:\t 0x%x\n", readl(&power_regs->hw_power_dclimits));
+	debug("loopctrl:\t 0x%x\n", readl(&power_regs->hw_power_loopctrl));
+	debug("sts:\t\t 0x%x\n", readl(&power_regs->hw_power_sts));
+	debug("speed:\t\t 0x%x\n", readl(&power_regs->hw_power_speed));
+	debug("battmonitor:\t 0x%x\n",
+	      readl(&power_regs->hw_power_battmonitor));
+}
+
 /**
  * mxs_power_clock2pll() - Switch CPU core clock source to PLL
  *
@@ -752,7 +775,19 @@ static void mxs_batt_boot(void)
 		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 		0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 
-	mxs_power_enable_4p2();
+	if (CONFIG_IS_ENABLED(MXS_PMU_MINIMAL_VDD5V_CURRENT))
+		setbits_le32(&power_regs->hw_power_5vctrl,
+			     POWER_5VCTRL_ILIMIT_EQ_ZERO);
+
+	if (CONFIG_IS_ENABLED(MXS_PMU_DISABLE_BATT_CHARGE)) {
+		writel(POWER_CHARGE_PWD_BATTCHRG,
+		       &power_regs->hw_power_charge_set);
+		writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+		       &power_regs->hw_power_5vctrl_set);
+	}
+
+	if (CONFIG_IS_ENABLED(MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR))
+		mxs_power_enable_4p2();
 }
 
 /**
@@ -1268,6 +1303,7 @@ void mxs_power_init(void)
 		POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 
 	writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
+	mxs_power_regs_dump();
 
 	early_delay(1000);
 }
diff --git a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
index c108736811..cf65e8c462 100644
--- a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
@@ -36,6 +36,7 @@ SECTIONS
 	. = ALIGN(4);
 	__image_copy_end = .;
 	_end = .;
+	_image_binary_end = .;
 
 	.bss :
 	{
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index e33e53636a..ccc2f20867 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -110,7 +110,7 @@ config ARMV7_LPAE
 config ARMV7_SET_CORTEX_SMPEN
 	bool
 	help
-	  Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
+	  Enable the ARM Cortex ACTLR.SMP enable bit in U-Boot.
 
 config SPL_ARMV7_SET_CORTEX_SMPEN
 	bool
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 68807d2099..6259ffa510 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -83,3 +83,8 @@ int cleanup_before_linux(void)
 {
 	return cleanup_before_linux_select(CBL_ALL);
 }
+
+void allow_unaligned(void)
+{
+	v7_arch_cp15_allow_unaligned();
+}
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 6c066e50d9..41428728b7 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -311,11 +311,11 @@ ENTRY(psci_cpu_entry)
 	bl	psci_arch_cpu_entry
 
 	bl	psci_get_cpu_id			@ CPU ID => r0
-	mov	r2, r0				@ CPU ID => r2
 	bl	psci_get_context_id		@ context id => r0
-	mov	r1, r0				@ context id => r1
-	mov	r0, r2				@ CPU ID => r0
+	push	{r0}				@ save context id
+	bl	psci_get_cpu_id			@ CPU ID => r0
 	bl	psci_get_target_pc		@ target PC => r0
+	pop	{r1}				@ context id => r1
 	b	_do_nonsec_entry
 ENDPROC(psci_cpu_entry)
 
diff --git a/arch/arm/cpu/armv7/sctlr.S b/arch/arm/cpu/armv7/sctlr.S
index bd56e41afe..d44b21498f 100644
--- a/arch/arm/cpu/armv7/sctlr.S
+++ b/arch/arm/cpu/armv7/sctlr.S
@@ -8,15 +8,15 @@
 #include <linux/linkage.h>
 
 /*
- * void allow_unaligned(void) - allow unaligned access
+ * void v7_arch_cp15_allow_unaligned(void) - allow unaligned access
  *
  * This routine clears the aligned flag in the system control register.
  * After calling this routine unaligned access does no longer lead to a
  * data abort but is handled by the CPU.
  */
-ENTRY(allow_unaligned)
+ENTRY(v7_arch_cp15_allow_unaligned)
 	mrc	p15, 0, r0, c1, c0, 0	@ load system control register
 	bic	r0, r0, #2		@ clear aligned flag
 	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
 	bx	lr			@ return
-ENDPROC(allow_unaligned)
+ENDPROC(v7_arch_cp15_allow_unaligned)
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
index 306a4ddf3c..fb7a789b28 100644
--- a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
@@ -45,6 +45,7 @@ SECTIONS
 	. = ALIGN(4);
 	__image_copy_end = .;
 	_end = .;
+	_image_binary_end = .;
 
 	.bss :
 	{
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 7d5cf1594d..9f0fb369f7 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -145,7 +145,7 @@ config ARMV8_PSCI
 	bool "Enable PSCI support" if EXPERT
 	help
 	  PSCI is Power State Coordination Interface defined by ARM.
-	  The PSCI in U-boot provides a general framework and each platform
+	  The PSCI in U-Boot provides a general framework and each platform
 	  can implement their own specific PSCI functions.
 	  Say Y here to enable PSCI support on ARMv8 platform.
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index 6f3fe7ca6e..1ddf9473a3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -125,7 +125,7 @@ mcinitcmd:	This environment variable is defined to initiate MC and DPL deploymen
 		from the location where it is stored(NOR, NAND, SD, SATA, USB)during
 		u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR
 		will be null and MC will not be booted and DPL will not be applied
-		during U-boot booting.However the MC, DPC and DPL can be applied from
+		during U-Boot booting.However the MC, DPC and DPL can be applied from
 		console independently.
 		The variable needs to be set from the console once and then on
 		rebooting the parameters set in the variable will automatically be
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 359cbc0430..3bfdc3f774 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -575,11 +575,6 @@ int get_core_volt_from_fuse(void)
 	return vdd;
 }
 
-__weak int board_switch_core_volt(u32 vdd)
-{
-	return 0;
-}
-
 static int setup_core_volt(u32 vdd)
 {
 	return board_setup_core_volt(vdd);
@@ -810,7 +805,7 @@ int qspi_ahb_init(void)
 #ifdef CONFIG_TFABOOT
 #define MAX_BOOTCMD_SIZE	512
 
-int fsl_setenv_bootcmd(void)
+__weak int fsl_setenv_bootcmd(void)
 {
 	int ret;
 	enum boot_src src = get_boot_src();
diff --git a/arch/arm/cpu/armv8/smccc-call.S b/arch/arm/cpu/armv8/smccc-call.S
index dc92b28777..93f66d3366 100644
--- a/arch/arm/cpu/armv8/smccc-call.S
+++ b/arch/arm/cpu/armv8/smccc-call.S
@@ -1,7 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2015, Linaro Limited
- */
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+*/
 #include <linux/linkage.h>
 #include <linux/arm-smccc.h>
 #include <generated/asm-offsets.h>
@@ -45,3 +49,54 @@ ENDPROC(__arm_smccc_smc)
 ENTRY(__arm_smccc_hvc)
 	SMCCC	hvc
 ENDPROC(__arm_smccc_hvc)
+
+#ifdef CONFIG_ARM64
+
+	.macro SMCCC_1_2 instr
+	/* Save `res` and free a GPR that won't be clobbered */
+	stp     x1, x19, [sp, #-16]!
+
+	/* Ensure `args` won't be clobbered while loading regs in next step */
+	mov	x19, x0
+
+	/* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */
+	ldp	x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
+	ldp	x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
+	ldp	x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
+	ldp	x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
+	ldp	x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
+	ldp	x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
+	ldp	x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
+	ldp	x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
+	ldp	x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
+
+	\instr #0
+
+	/* Load the `res` from the stack */
+	ldr	x19, [sp]
+
+	/* Store the registers x0 - x17 into the result structure */
+	stp	x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
+	stp	x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
+	stp	x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
+	stp	x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
+	stp	x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
+	stp	x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
+	stp	x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
+	stp	x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
+	stp	x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
+
+	/* Restore original x19 */
+	ldp     xzr, x19, [sp], #16
+	ret
+	.endm
+
+/*
+ * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
+ *			  struct arm_smccc_1_2_regs *res);
+ */
+ENTRY(arm_smccc_1_2_smc)
+	SMCCC_1_2 smc
+ENDPROC(arm_smccc_1_2_smc)
+
+#endif
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3de10ec921..85fd5b1157 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -119,12 +119,15 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
 
 dtb-$(CONFIG_ROCKCHIP_RK3308) += \
 	rk3308-evb.dtb \
-	rk3308-roc-cc.dtb
+	rk3308-roc-cc.dtb \
+	rk3308-rock-pi-s.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
 	rk3328-evb.dtb \
 	rk3328-nanopi-r2c.dtb \
 	rk3328-nanopi-r2s.dtb \
+	rk3328-orangepi-r1-plus.dtb \
+	rk3328-orangepi-r1-plus-lts.dtb \
 	rk3328-roc-cc.dtb \
 	rk3328-rock64.dtb \
 	rk3328-rock-pi-e.dtb
@@ -159,6 +162,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
 	rk3399-roc-pc.dtb \
 	rk3399-roc-pc-mezzanine.dtb \
 	rk3399-rock-4c-plus.dtb \
+	rk3399-rock-4se.dtb \
 	rk3399-rock-pi-4a.dtb \
 	rk3399-rock-pi-4c.dtb \
 	rk3399-rock960.dtb \
@@ -167,13 +171,25 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
 
 dtb-$(CONFIG_ROCKCHIP_RK3568) += \
 	rk3566-anbernic-rgxx3.dtb \
+	rk3566-quartz64-a.dtb \
+	rk3566-quartz64-b.dtb \
 	rk3566-radxa-cm3-io.dtb \
+	rk3566-soquartz-blade.dtb \
+	rk3566-soquartz-cm4.dtb \
+	rk3566-soquartz-model-a.dtb \
 	rk3568-evb.dtb \
+	rk3568-lubancat-2.dtb \
+	rk3568-nanopi-r5c.dtb \
+	rk3568-nanopi-r5s.dtb \
+	rk3568-odroid-m1.dtb \
+	rk3568-radxa-e25.dtb \
 	rk3568-rock-3a.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
 	rk3588-edgeble-neu6a-io.dtb \
+	rk3588-edgeble-neu6b-io.dtb \
 	rk3588-evb1-v10.dtb \
+	rk3588s-rock-5a.dtb \
 	rk3588-rock-5b.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RV1108) += \
@@ -187,8 +203,10 @@ dtb-$(CONFIG_ARCH_S5P4418) += \
 	s5p4418-nanopi2.dtb
 
 dtb-$(CONFIG_ARCH_MESON) += \
+	meson-a1-ad401.dtb \
 	meson-axg-s400.dtb \
 	meson-axg-jethome-jethub-j100.dtb \
+	meson-gxbb-kii-pro.dtb \
 	meson-gxbb-nanopi-k2.dtb \
 	meson-gxbb-odroidc2.dtb \
 	meson-gxbb-nanopi-k2.dtb \
@@ -316,7 +334,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	cn9132-db-B.dtb				\
 	cn9130-crb-A.dtb			\
 	cn9130-crb-B.dtb			\
-	ac5-98dx35xx-rd.dtb
+	ac5-98dx35xx-rd.dtb			\
+	ac5-98dx35xx-atl-x240.dtb
 endif
 
 dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
@@ -426,6 +445,9 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
 	xilinx-versal-virt.dtb
 dtb-$(CONFIG_ARCH_VERSAL_NET) += \
 	versal-net-mini.dtb \
+	versal-net-mini-emmc.dtb \
+	versal-net-mini-ospi-single.dtb \
+	versal-net-mini-qspi-single.dtb \
 	xilinx-versal-net-virt.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
 	zynqmp-r5.dtb
@@ -464,7 +486,6 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
 	am4372-generic.dtb \
 	am437x-cm-t43.dtb
 dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
-dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
 dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
@@ -1029,6 +1050,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mp-phyboard-pollux-rdk.dtb \
 	imx8mp-venice.dtb \
 	imx8mp-venice-gw74xx.dtb \
+	imx8mp-venice-gw7905-2x.dtb \
 	imx8mp-verdin-wifi-dev.dtb \
 	imx8mq-pico-pi.dtb \
 	imx8mq-kontron-pitx-imx8m.dtb \
@@ -1066,7 +1088,9 @@ dtb-$(CONFIG_RCAR_GEN3) += \
 	r8a77965-ulcb-u-boot.dtb \
 	r8a77965-salvator-x-u-boot.dtb \
 	r8a77970-eagle-u-boot.dtb \
+	r8a77970-v3msk-u-boot.dtb \
 	r8a77980-condor-u-boot.dtb \
+	r8a77980-v3hsk-u-boot.dtb \
 	r8a77990-ebisu-u-boot.dtb \
 	r8a77995-draak-u-boot.dtb
 
@@ -1309,9 +1333,11 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
 			      k3-am642-r5-sk.dtb
 
 dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
-			      k3-am625-r5-sk.dtb
+			      k3-am625-r5-sk.dtb \
+			      k3-am625-verdin-wifi-dev.dtb \
+			      k3-am625-verdin-r5.dtb
 
-dtb-$(CONFIG_SOC_K3_AM625) += k3-am62a7-sk.dtb \
+dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \
 			      k3-am62a7-r5-sk.dtb
 
 dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -1331,6 +1357,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7986b-sd-rfb.dtb \
 	mt7986a-emmc-rfb.dtb \
 	mt7986b-emmc-rfb.dtb \
+	mt7988-rfb.dtb \
+	mt7988-sd-rfb.dtb \
 	mt8183-pumpkin.dtb \
 	mt8512-bm1-emmc.dtb \
 	mt8516-pumpkin.dtb \
diff --git a/arch/arm/dts/ac5-98dx25xx.dtsi b/arch/arm/dts/ac5-98dx25xx.dtsi
index 3c68355f32..f53b4781d7 100644
--- a/arch/arm/dts/ac5-98dx25xx.dtsi
+++ b/arch/arm/dts/ac5-98dx25xx.dtsi
@@ -251,6 +251,15 @@
 			status = "disabled";
 		};
 
+		nand: nand-controller@805b0000 {
+			compatible = "marvell,mvebu-ac5-pxa3xx-nand";
+			reg = <0x0 0x805b0000 0x0 0x54>;
+			#address-cells = <0x00000001>;
+			marvell,nand-enable-arbiter;
+			num-cs = <0x00000001>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@80600000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
diff --git a/arch/arm/dts/ac5-98dx35xx-atl-x240.dts b/arch/arm/dts/ac5-98dx35xx-atl-x240.dts
new file mode 100644
index 0000000000..c19b25925b
--- /dev/null
+++ b/arch/arm/dts/ac5-98dx35xx-atl-x240.dts
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "ac5-98dx35xx.dtsi"
+
+/ {
+	model = "Allied Telesis x240";
+	compatible = "alliedtelesis,x240", "marvell,ac5x", "marvell,ac5";
+
+	aliases {
+		serial0 = &uart0;
+		spiflash0 = &spiflash0;
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		spi0 = &spi0;
+		i2c0 = &i2cgpio;
+		usb0 = &usb0;
+		pinctrl0 = &pinctrl0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	boot-board {
+		compatible = "atl,boot-board";
+		present-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+		override-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		fault {
+			label = "fault:red";
+			gpios = <&system_gpio 11 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+	};
+
+	i2cgpio: i2c-gpio-0 {
+			compatible = "i2c-gpio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pinctrl-names = "default";
+			pinctrl-0 =  <&i2c0_gpio>;
+			scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+			sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+			i2c-gpio,delay-us = <2>;
+			status = "okay";
+		 };
+};
+
+&nand {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_pins>;
+
+	nand-ecc-strength = <4>;
+	nand-ecc-step-size = <512>;
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@user {
+			reg = <0x00000000 0x10000000>;
+			label = "user";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&i2cgpio {
+	mux@71 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nxp,pca9546";
+		reg = <0x71>;
+		i2c-mux-idle-disconnect;
+		reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;               /* MPP36 */
+		status = "okay";
+
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			hwmon@2e {
+				compatible = "adi,adt7476";
+				reg = <0x2e>;
+			};
+
+			rtc@68 {
+				compatible = "adi,max31331";
+				reg = <0x68>;
+			};
+
+			system_gpio: gpio@27 {
+				compatible = "nxp,pca9555";
+				gpio-controller;
+				#gpio-cells= <2>;
+				reg = <0x27>;
+				interrupt-parent = <&gpio0>;
+				interrupts = <25 IRQ_TYPE_LEVEL_LOW>;   /* MPP25 */
+			};
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+	spiflash0: flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
+		spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
+		reg = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+&gpio0 {
+	phy-reset {
+		gpio-hog;
+		gpios = <19 GPIO_ACTIVE_LOW>;
+		output-high;
+		line-name = "phy-reset";
+	};
+
+	usb-en {
+		gpio-hog;
+		gpios = <28 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "usb-en";
+	};
+
+	led-oe-n {
+		gpio-hog;
+		gpios = <23 GPIO_ACTIVE_LOW>;
+		output-low;
+		line-name = "led-oe-n";
+	};
+};
+
+&gpio1 {
+	nand-protect {
+		gpio-hog;
+		gpios = <8 GPIO_ACTIVE_LOW>;
+		output-low;
+		line-name = "nand-protect";
+	};
+};
+
+&pinctrl0 {
+	/*
+	 * MPP Bus:              MPP#
+	 * NF_IO                 [0-7]
+	 * NF_Wen                [8]
+	 * NF_ALE                [9]
+	 * NF_CLE                [10]
+	 * NF_Cen                [11]
+	 * QSPI_SCK/SPI0_SCK     [12]
+	 * QSPI_CSn/SPI0_CSn     [13]
+	 * QSPI_DIO[0]/SPI0_MOSI [14]
+	 * QSPI_DIO[1]/SPI0_MISO [15]
+	 * NF_Ren                [16]
+	 * NF_RBn                [17]
+	 * WD_INTn               [18]
+	 * B_B_OVRIDE_N          [19]
+	 * GREEN_SW_N            [20]
+	 * PHY_INT_N[0]          [21]
+	 * SPI_WPn               [22]
+	 * LED_OE_N              [23]
+	 * USB_PWR_FLT_N         [24]
+	 * SFP_INT_N             [25]
+	 * I2C0_SCL              [26] (GPIO)
+	 * I2C0_SDA              [27] (GPIO)
+	 * USB_EN                [28]
+	 * MONITOR_INT_N         [29]
+	 * XM1_MDC               [30]
+	 * XM1_MDIO              [31]
+	 * UA0_RXD               [32]
+	 * UA0_TXD               [33]
+	 * PHY_RST0n             [34]
+	 * TPM_INT_N             [35]
+	 * I2CMUX_RESET_N        [36]
+	 * SPI_SRAM_SEL_N        [37]
+	 * B_B_PRESENT           [38]
+	 * SPI_FLASH_SEL_N       [39]
+	 * NF_WP_N               [40]
+	 * POE_INT_N             [41]
+	 * PoE_RST_N             [42]
+	 * LED0_CLK              [43]
+	 * LED0_STB              [44]
+	 * LED0_DATA             [45]
+	 */
+	/*	     0    1    2    3    4    5    6    7    8    9 */
+	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 1    1    1    1    0xff 0xff 0    0
+		     0    0    0    0    0    0    0xff 0xff 0    0
+		     1    1    1    1    0    0    0    0    0    0
+		     0    0    0    1    1    1    >;
+
+	nand_pins: nand-pins {
+		marvell,pins = <0 1 2 3 4 5 6 7 8 9 10 11 16 17>;
+		marvell,function = <2>;
+	};
+
+	i2c0_gpio: i2c0-gpio-pins {
+		marvell,pins = <26 27>;
+		marvell,function = <0>;
+	};
+};
diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts
index d9f217cd4a..1dc85bb7ef 100644
--- a/arch/arm/dts/ac5-98dx35xx-rd.dts
+++ b/arch/arm/dts/ac5-98dx35xx-rd.dts
@@ -31,7 +31,6 @@
 		usb0 = &usb0;
 		usb1 = &usb1;
 		pinctrl0 = &pinctrl0;
-		sar-reg0 = "/config-space/sar-reg";
 	};
 
 	usb1phy: usb-phy {
diff --git a/arch/arm/dts/am335x-igep0033.dtsi b/arch/arm/dts/am335x-igep0033.dtsi
index ad57c74faf..4488dcce01 100644
--- a/arch/arm/dts/am335x-igep0033.dtsi
+++ b/arch/arm/dts/am335x-igep0033.dtsi
@@ -175,7 +175,7 @@
 		};
 
 		partition@1 {
-			label = "U-boot";
+			label = "U-Boot";
 			reg = <0x00080000 0x001e0000>;
 		};
 
diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 3e5789f372..1ee92406b7 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -180,7 +180,7 @@
 				reg = <0x0 0x200000>;
 			};
 			partition@200000 {
-				label = "U-boot Env";
+				label = "U-Boot Env";
 				reg = <0x200000 0x10000>;
 			};
 			partition@210000 {
diff --git a/arch/arm/dts/armada-385-thecus-n2350.dts b/arch/arm/dts/armada-385-thecus-n2350.dts
index fc29c4d25a..253cf01130 100644
--- a/arch/arm/dts/armada-385-thecus-n2350.dts
+++ b/arch/arm/dts/armada-385-thecus-n2350.dts
@@ -23,7 +23,7 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@0 {
 		device_type = "memory";
 		reg = <0x00000000 0x40000000>; /* 1GB */
 	};
@@ -37,43 +37,43 @@
 
 	};
 
-	usb3_0_phy: usb3_0_phy {
+	usb3_0_phy: usb-phy {
 		compatible = "usb-nop-xceiv";
 		vcc-supply = <&usb3_0_power>;
+		 #phy-cells = <0>;
 	};
 
-	usb3_1_phy: usb3_1_phy {
+	usb3_1_phy: usb-phy {
 		compatible = "usb-nop-xceiv";
 		vcc-supply = <&usb3_1_power>;
+		 #phy-cells = <0>;
 	};
 
-	gpio-keys {
+	keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		pinctrl-0 = <&pmx_power_button &pmx_copy_button &pmx_reset_button>;
 		pinctrl-names = "default";
 
-		button@1 {
+		button-1 {
 			label = "Power Button";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
 		};
 
-		button@2 {
+		button-2 {
 			label = "Copy Button";
 			linux,code = <KEY_COPY>;
 			gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
 		};
 
-		button@3 {
+		button-3 {
 			label = "Reset Button";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
-	gpio-leds {
+	leds {
 		compatible = "gpio-leds";
 		pinctrl-0 = <&pmx_sata1_white_led
 				&pmx_sata1_red_led
@@ -88,142 +88,142 @@
 
 		pinctrl-names = "default";
 
-		white_sata1 {
+		led-1 {
 			label = "n2350:white:sata1";
 			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "ide-disk1";
 		};
 
-		red_sata1 {
+		led-2 {
 			label = "n2350:red:sata1";
 			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 		};
 
-		white-sata2 {
+		led-3 {
 			label = "n2350:white:sata2";
 			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
 		};
 
-		red-sata2 {
+		led-4 {
 			label = "n2350:red:sata2";
 			gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
 		};
 
-		white-sys {
+		led-5 {
 			label = "n2350:white:sys";
 			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "default-on";
 		};
 
-		red-sys {
+		led-6 {
 			label = "n2350:red:sys";
 			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
 		};
 
-		blue-pwr {
+		led-7 {
 			label = "n2350:blue:pwr";
 			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
 		};
 
-		red-pwr {
+		led-8 {
 			label = "n2350:red:pwr";
 			gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
 		};
 
-		white-usb {
+		led-9 {
 			label = "n2350:white:usb";
 			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
 		};
 
-		red-usb {
+		led-10 {
 			label = "n2350:red:usb";
 			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		usb3_0_power: regulator@1 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "USB3_0_Power";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
-		};
+	fan {
+		compatible = "gpio-fan";
+		gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+		gpio-fan,speed-map = <	  0  0
+					600  1
+					3000 2 >;
+		pinctrl-0 = <&pmx_fan>;
+		pinctrl-names = "default";
+	};
 
-		usb3_1_power: regulator@2 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "USB3_1_Power";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
-		};
+	usb3_0_power: v5-vbus0 {
+		compatible = "regulator-fixed";
+		regulator-name = "USB3_0_Power";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+	};
 
-		reg_sata0: regulator@3 {
-			compatible = "regulator-fixed";
-			regulator-name = "pwr_en_sata0";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-		};
+	usb3_1_power: v5-vbus1 {
+		compatible = "regulator-fixed";
+		regulator-name = "USB3_1_Power";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+	};
 
-		reg_5v_sata0: v5-sata0 {
-			compatible = "regulator-fixed";
-			regulator-name = "v5.0-sata0";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			vin-supply = <&reg_sata0>;
-		};
+	reg_sata0: pwr-sata0 {
+		compatible = "regulator-fixed";
+		regulator-name = "pwr_en_sata0";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+	};
 
-		reg_12v_sata0: v12-sata0 {
-			compatible = "regulator-fixed";
-			regulator-name = "v12.0-sata0";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			vin-supply = <&reg_sata0>;
-		};
+	reg_5v_sata0: v5-sata0 {
+		compatible = "regulator-fixed";
+		regulator-name = "v5.0-sata0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&reg_sata0>;
+	};
 
-		reg_sata1: regulator@4 {
-			regulator-name = "pwr_en_sata1";
-			compatible = "regulator-fixed";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
-		};
+	reg_12v_sata0: v12-sata0 {
+		compatible = "regulator-fixed";
+		regulator-name = "v12.0-sata0";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		vin-supply = <&reg_sata0>;
+	};
 
-		reg_5v_sata1: v5-sata1 {
-			compatible = "regulator-fixed";
-			regulator-name = "v5.0-sata1";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			vin-supply = <&reg_sata1>;
-		};
+	reg_sata1: pwr-sata0 {
+		regulator-name = "pwr_en_sata1";
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+	};
 
-		reg_12v_sata1: v12-sata1 {
-			compatible = "regulator-fixed";
-			regulator-name = "v12.0-sata1";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			vin-supply = <&reg_sata1>;
-		};
+	reg_5v_sata1: v5-sata1 {
+		compatible = "regulator-fixed";
+		regulator-name = "v5.0-sata1";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&reg_sata1>;
+	};
 
+	reg_12v_sata1: v12-sata1 {
+		compatible = "regulator-fixed";
+		regulator-name = "v12.0-sata1";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		vin-supply = <&reg_sata1>;
 	};
 
 	gpio-poweroff {
@@ -267,7 +267,7 @@
 };
 
 &mdio {
-	phy0: ethernet-phy@0 {
+	phy0: ethernet-phy@1 {
 		reg = <1>;
 	};
 };
@@ -301,18 +301,14 @@
 
 &pciec {
 	status = "okay";
-	/*
-	 * The two PCIe units are accessible through
-	 * standard PCIe slots on the board.
-	 */
-	pcie@1,0 {
-		/* Port 0, Lane 0 */
-		status = "okay";
-	};
-	pcie@2,0 {
-		/* Port 1, Lane 0 */
-		status = "okay";
-	};
+};
+
+&pcie1 {
+	status = "okay";
+};
+
+&pcie2 {
+	status = "okay";
 };
 
 &pinctrl {
@@ -392,6 +388,11 @@
 		marvell,pins = "mpp17";
 		marvell,function = "gpio";
 	};
+
+	pmx_fan: pmx-fan {
+		marvell,pins = "mpp48";
+		marvell,function = "gpio";
+	};
 };
 
 &sdhci {
@@ -408,10 +409,10 @@
 	status = "okay";
 
 	/* spi: 4M Flash Macronix MX25L3205D */
-	spi-flash@0 {
+	flash@0 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		compatible = "macronix,mx25l3205d", "jedec,spi-nor";
+		compatible = "jedec,spi-nor";
 		reg = <0>;
 
 		spi-max-frequency = <108000000>;
diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts b/arch/arm/dts/avnet-ultra96-rev1.dts
index ddb8febaec..96a6403efa 100644
--- a/arch/arm/dts/avnet-ultra96-rev1.dts
+++ b/arch/arm/dts/avnet-ultra96-rev1.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2018 - 2020, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
index 533dfdf8e1..1e0ec075e4 100644
--- a/arch/arm/dts/corstone1000.dtsi
+++ b/arch/arm/dts/corstone1000.dtsi
@@ -38,7 +38,7 @@
 		reg = <0x88200000 0x77e00000>;
 	};
 
-	nvmxip-qspi@08000000 {
+	nvmxip: nvmxip-qspi@08000000 {
 		compatible = "nvmxip,qspi";
 		reg = <0x08000000 0x2000000>;
 		lba_shift = <9>;
@@ -106,6 +106,11 @@
 		method = "smc";
 	};
 
+	fwu-mdata {
+		compatible = "u-boot,fwu-mdata-gpt";
+		fwu-mdata-store = <&nvmxip>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/dts/dm8168-evm-u-boot.dtsi b/arch/arm/dts/dm8168-evm-u-boot.dtsi
deleted file mode 100644
index f939df27e4..0000000000
--- a/arch/arm/dts/dm8168-evm-u-boot.dtsi
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * dm8168-evm U-Boot Additions
- *
- * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
- */
-
-/ {
-	ocp {
-		bootph-all;
-	};
-};
diff --git a/arch/arm/dts/dm8168-evm.dts b/arch/arm/dts/dm8168-evm.dts
deleted file mode 100644
index 70255ab259..0000000000
--- a/arch/arm/dts/dm8168-evm.dts
+++ /dev/null
@@ -1,171 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/dts-v1/;
-
-#include "dm816x.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "DM8168 EVM";
-	compatible = "ti,dm8168-evm", "ti,dm8168";
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x40000000	/* 1 GB */
-		       0xc0000000 0x40000000>;	/* 1 GB */
-	};
-
-	/* FDC6331L controlled by SD_POW pin */
-	vmmcsd_fixed: fixedregulator0 {
-		compatible = "regulator-fixed";
-		regulator-name = "vmmcsd_fixed";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-};
-
-&dm816x_pinmux {
-	mcspi1_pins: pinmux_mcspi1_pins {
-		pinctrl-single,pins = <
-			DM816X_IOPAD(0x0a94, MUX_MODE0)			/* SPI_SCLK */
-			DM816X_IOPAD(0x0a98, MUX_MODE0)			/* SPI_SCS0 */
-			DM816X_IOPAD(0x0aa8, MUX_MODE0)			/* SPI_D0 */
-			DM816X_IOPAD(0x0aac, MUX_MODE0)			/* SPI_D1 */
-		>;
-	};
-
-	mmc_pins: pinmux_mmc_pins {
-		pinctrl-single,pins = <
-			DM816X_IOPAD(0x0a70, MUX_MODE0)			/* SD_POW */
-			DM816X_IOPAD(0x0a74, MUX_MODE0)			/* SD_CLK */
-			DM816X_IOPAD(0x0a78, MUX_MODE0)			/* SD_CMD */
-			DM816X_IOPAD(0x0a7C, MUX_MODE0)			/* SD_DAT0 */
-			DM816X_IOPAD(0x0a80, MUX_MODE0)			/* SD_DAT1 */
-			DM816X_IOPAD(0x0a84, MUX_MODE0)			/* SD_DAT2 */
-			DM816X_IOPAD(0x0a88, MUX_MODE0)			/* SD_DAT2 */
-			DM816X_IOPAD(0x0a8c, MUX_MODE2)			/* GP1[7] */
-			DM816X_IOPAD(0x0a90, MUX_MODE2)			/* GP1[8] */
-		>;
-	};
-
-	usb0_pins: pinmux_usb0_pins {
-		pinctrl-single,pins = <
-			DM816X_IOPAD(0x0d04, MUX_MODE0)			/* USB0_DRVVBUS */
-		>;
-	};
-
-	usb1_pins: pinmux_usb1_pins {
-		pinctrl-single,pins = <
-			DM816X_IOPAD(0x0d08, MUX_MODE0)			/* USB1_DRVVBUS */
-		>;
-	};
-};
-
-&i2c1 {
-	extgpio0: pcf8575@20 {
-		compatible = "nxp,pcf8575";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
-
-&i2c2 {
-	extgpio1: pcf8575@20 {
-		compatible = "nxp,pcf8575";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
-
-&gpmc {
-	ranges = <0 0 0x04000000 0x01000000>;	/* CS0: 16MB for NAND */
-
-	nand@0,0 {
-		compatible = "ti,omap2-nand";
-		linux,mtd-name= "micron,mt29f2g16aadwp";
-		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
-		interrupt-parent = <&gpmc>;
-		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
-			     <1 IRQ_TYPE_NONE>; /* termcount */
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ti,nand-ecc-opt = "bch8";
-		nand-bus-width = <16>;
-		gpmc,device-width = <2>;
-		gpmc,sync-clk-ps = <0>;
-		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <44>;
-		gpmc,cs-wr-off-ns = <44>;
-		gpmc,adv-on-ns = <6>;
-		gpmc,adv-rd-off-ns = <34>;
-		gpmc,adv-wr-off-ns = <44>;
-		gpmc,we-on-ns = <0>;
-		gpmc,we-off-ns = <40>;
-		gpmc,oe-on-ns = <0>;
-		gpmc,oe-off-ns = <54>;
-		gpmc,access-ns = <64>;
-		gpmc,rd-cycle-ns = <82>;
-		gpmc,wr-cycle-ns = <82>;
-		gpmc,bus-turnaround-ns = <0>;
-		gpmc,cycle2cycle-delay-ns = <0>;
-		gpmc,clk-activation-ns = <0>;
-		gpmc,wr-access-ns = <40>;
-		gpmc,wr-data-mux-bus-ns = <0>;
-		partition@0 {
-			label = "X-Loader";
-			reg = <0 0x80000>;
-		};
-		partition@80000 {
-			label = "U-Boot";
-			reg = <0x80000 0x1c0000>;
-		};
-		partition@1c0000 {
-			label = "Environment";
-			reg = <0x240000 0x40000>;
-		};
-		partition@280000 {
-			label = "Kernel";
-			reg = <0x280000 0x500000>;
-		};
-		partition@780000 {
-			label = "Filesystem";
-			reg = <0x780000 0xf880000>;
-		};
-	};
-};
-
-&mcspi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcspi1_pins>;
-
-	flash@0 {
-		compatible = "w25x32";
-		spi-max-frequency = <48000000>;
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-&mmc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc_pins>;
-	vmmc-supply = <&vmmcsd_fixed>;
-	bus-width = <4>;
-	cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
-};
-
-/* At least dm8168-evm rev c won't support multipoint, later may */
-&usb0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_pins>;
-	mentor,multipoint = <0>;
-};
-
-&usb1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb1_pins>;
-	mentor,multipoint = <0>;
-};
diff --git a/arch/arm/dts/dm816x-clocks.dtsi b/arch/arm/dts/dm816x-clocks.dtsi
deleted file mode 100644
index f7a839dabf..0000000000
--- a/arch/arm/dts/dm816x-clocks.dtsi
+++ /dev/null
@@ -1,246 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-&scrm {
-	main_fapll: main_fapll {
-		#clock-cells = <1>;
-		compatible = "ti,dm816-fapll-clock";
-		reg = <0x400 0x40>;
-		clocks = <&sys_clkin_ck &sys_clkin_ck>;
-		clock-indices = <1>, <2>, <3>, <4>, <5>,
-				<6>, <7>;
-		clock-output-names = "main_pll_clk1",
-				     "main_pll_clk2",
-				     "main_pll_clk3",
-				     "main_pll_clk4",
-				     "main_pll_clk5",
-				     "main_pll_clk6",
-				     "main_pll_clk7";
-	};
-
-	ddr_fapll: ddr_fapll {
-		#clock-cells = <1>;
-		compatible = "ti,dm816-fapll-clock";
-		reg = <0x440 0x30>;
-		clocks = <&sys_clkin_ck &sys_clkin_ck>;
-		clock-indices = <1>, <2>, <3>, <4>;
-		clock-output-names = "ddr_pll_clk1",
-				     "ddr_pll_clk2",
-				     "ddr_pll_clk3",
-				     "ddr_pll_clk4";
-	};
-
-	video_fapll: video_fapll {
-		#clock-cells = <1>;
-		compatible = "ti,dm816-fapll-clock";
-		reg = <0x470 0x30>;
-		clocks = <&sys_clkin_ck &sys_clkin_ck>;
-		clock-indices = <1>, <2>, <3>;
-		clock-output-names = "video_pll_clk1",
-				     "video_pll_clk2",
-				     "video_pll_clk3";
-	};
-
-	audio_fapll: audio_fapll {
-		#clock-cells = <1>;
-		compatible = "ti,dm816-fapll-clock";
-		reg = <0x4a0 0x30>;
-		clocks = <&main_fapll 7>, < &sys_clkin_ck>;
-		clock-indices = <1>, <2>, <3>, <4>, <5>;
-		clock-output-names = "audio_pll_clk1",
-				     "audio_pll_clk2",
-				     "audio_pll_clk3",
-				     "audio_pll_clk4",
-				     "audio_pll_clk5";
-	};
-};
-
-&scrm_clocks {
-	secure_32k_ck: secure_32k_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <32768>;
-	};
-
-	sys_32k_ck: sys_32k_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <32768>;
-	};
-
-	tclkin_ck: tclkin_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <32768>;
-	};
-
-	sys_clkin_ck: sys_clkin_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <27000000>;
-	};
-};
-
-/* 0x48180000 */
-&prcm_clocks {
-	clkout_pre_ck: clkout_pre_ck@100 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
-			  &audio_fapll 1>;
-		reg = <0x100>;
-	};
-
-	clkout_div_ck: clkout_div_ck@100 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&clkout_pre_ck>;
-		ti,bit-shift = <3>;
-		ti,max-div = <8>;
-		reg = <0x100>;
-	};
-
-	clkout_ck: clkout_ck@100 {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&clkout_div_ck>;
-		ti,bit-shift = <7>;
-		reg = <0x100>;
-	};
-
-	/* CM_DPLL clocks p1795 */
-	sysclk1_ck: sysclk1_ck@300 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&main_fapll 1>;
-		ti,max-div = <7>;
-		reg = <0x0300>;
-	};
-
-	sysclk2_ck: sysclk2_ck@304 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&main_fapll 2>;
-		ti,max-div = <7>;
-		reg = <0x0304>;
-	};
-
-	sysclk3_ck: sysclk3_ck@308 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&main_fapll 3>;
-		ti,max-div = <7>;
-		reg = <0x0308>;
-	};
-
-	sysclk4_ck: sysclk4_ck@30c {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&main_fapll 4>;
-		ti,max-div = <1>;
-		reg = <0x030c>;
-	};
-
-	sysclk5_ck: sysclk5_ck@310 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&sysclk4_ck>;
-		ti,max-div = <1>;
-		reg = <0x0310>;
-	};
-
-	sysclk6_ck: sysclk6_ck@314 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&main_fapll 4>;
-		ti,dividers = <2>, <4>;
-		reg = <0x0314>;
-	};
-
-	sysclk10_ck: sysclk10_ck@324 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&ddr_fapll 2>;
-		ti,max-div = <7>;
-		reg = <0x0324>;
-	};
-
-	sysclk24_ck: sysclk24_ck@3b4 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&main_fapll 5>;
-		ti,max-div = <7>;
-		reg = <0x03b4>;
-	};
-
-	mpu_ck: mpu_ck@15dc {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&sysclk2_ck>;
-		ti,bit-shift = <1>;
-                reg = <0x15dc>;
-	};
-
-	audio_pll_a_ck: audio_pll_a_ck@35c {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&audio_fapll 1>;
-		ti,max-div = <7>;
-		reg = <0x035c>;
-	};
-
-	sysclk18_ck: sysclk18_ck@378 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
-		reg = <0x0378>;
-	};
-
-	timer1_fck: timer1_fck@390 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x0390>;
-	};
-
-	timer2_fck: timer2_fck@394 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x0394>;
-	};
-
-	timer3_fck: timer3_fck@398 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x0398>;
-	};
-
-	timer4_fck: timer4_fck@39c {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x039c>;
-	};
-
-	timer5_fck: timer5_fck@3a0 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x03a0>;
-	};
-
-	timer6_fck: timer6_fck@3a4 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x03a4>;
-	};
-
-	timer7_fck: timer7_fck@3a8 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x03a8>;
-	};
-};
diff --git a/arch/arm/dts/dm816x.dtsi b/arch/arm/dts/dm816x.dtsi
deleted file mode 100644
index c4a8653b7f..0000000000
--- a/arch/arm/dts/dm816x.dtsi
+++ /dev/null
@@ -1,517 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/omap.h>
-
-/ {
-	compatible = "ti,dm816";
-	interrupt-parent = <&intc>;
-	#address-cells = <1>;
-	#size-cells = <1>;
-	chosen { };
-
-	aliases {
-		i2c0 = &i2c1;
-		i2c1 = &i2c2;
-		serial0 = &uart1;
-		serial1 = &uart2;
-		serial2 = &uart3;
-		ethernet0 = &eth0;
-		ethernet1 = &eth1;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		cpu@0 {
-			compatible = "arm,cortex-a8";
-			device_type = "cpu";
-			reg = <0>;
-		};
-	};
-
-	pmu {
-		compatible = "arm,cortex-a8-pmu";
-		interrupts = <3>;
-	};
-
-	/*
-	 * The soc node represents the soc top level view. It is used for IPs
-	 * that are not memory mapped in the MPU view or for the MPU itself.
-	 */
-	soc {
-		compatible = "ti,omap-infra";
-		mpu {
-			compatible = "ti,omap3-mpu";
-			ti,hwmods = "mpu";
-		};
-	};
-
-	/*
-	 * XXX: Use a flat representation of the dm816x interconnect.
-	 * The real dm816x interconnect network is quite complex. Since
-	 * it will not bring real advantage to represent that in DT
-	 * for the moment, just use a fake OCP bus entry to represent
-	 * the whole bus hierarchy.
-	 */
-	ocp {
-		compatible = "simple-bus";
-		reg = <0x44000000 0x10000>;
-		interrupts = <9 10>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		prcm: prcm@48180000 {
-			compatible = "ti,dm816-prcm", "simple-bus";
-			reg = <0x48180000 0x4000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x48180000 0x4000>;
-
-			prcm_clocks: clocks {
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-
-			prcm_clockdomains: clockdomains {
-			};
-		};
-
-		scrm: scrm@48140000 {
-			compatible = "ti,dm816-scrm", "simple-bus";
-			reg = <0x48140000 0x21000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			#pinctrl-cells = <1>;
-			ranges = <0 0x48140000 0x21000>;
-
-			dm816x_pinmux: pinmux@800 {
-				compatible = "pinctrl-single";
-				reg = <0x800 0x50a>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				#pinctrl-cells = <1>;
-				pinctrl-single,register-width = <16>;
-				pinctrl-single,function-mask = <0xf>;
-			};
-
-			/* Device Configuration Registers */
-			scm_conf: syscon@600 {
-				compatible = "syscon", "simple-bus";
-				reg = <0x600 0x110>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0 0x600 0x110>;
-
-				usb_phy0: usb-phy@20 {
-					compatible = "ti,dm8168-usb-phy";
-					reg = <0x20 0x8>;
-					reg-names = "phy";
-					clocks = <&main_fapll 6>;
-					clock-names = "refclk";
-					#phy-cells = <0>;
-					syscon = <&scm_conf>;
-				};
-
-				usb_phy1: usb-phy@28 {
-					compatible = "ti,dm8168-usb-phy";
-					reg = <0x28 0x8>;
-					reg-names = "phy";
-					clocks = <&main_fapll 6>;
-					clock-names = "refclk";
-					#phy-cells = <0>;
-					syscon = <&scm_conf>;
-				};
-			};
-
-			scrm_clocks: clocks {
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-
-			scrm_clockdomains: clockdomains {
-			};
-		};
-
-		edma: edma@49000000 {
-			compatible = "ti,edma3";
-			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
-			reg =   <0x49000000 0x10000>,
-			        <0x44e10f90 0x40>;
-			interrupts = <12 13 14>;
-			#dma-cells = <1>;
-		};
-
-		elm: elm@48080000 {
-			compatible = "ti,816-elm";
-			ti,hwmods = "elm";
-			reg = <0x48080000 0x2000>;
-			interrupts = <4>;
-		};
-
-		gpio1: gpio@48032000 {
-			compatible = "ti,omap4-gpio";
-			ti,hwmods = "gpio1";
-			ti,gpio-always-on;
-			reg = <0x48032000 0x1000>;
-			interrupts = <96>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio2: gpio@4804c000 {
-			compatible = "ti,omap4-gpio";
-			ti,hwmods = "gpio2";
-			ti,gpio-always-on;
-			reg = <0x4804c000 0x1000>;
-			interrupts = <98>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpmc: gpmc@50000000 {
-			compatible = "ti,am3352-gpmc";
-			ti,hwmods = "gpmc";
-			reg = <0x50000000 0x2000>;
-			#address-cells = <2>;
-			#size-cells = <1>;
-			interrupts = <100>;
-			dmas = <&edma 52>;
-			dma-names = "rxtx";
-			gpmc,num-cs = <6>;
-			gpmc,num-waitpins = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		i2c1: i2c@48028000 {
-			compatible = "ti,omap4-i2c";
-			ti,hwmods = "i2c1";
-			reg = <0x48028000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <70>;
-			dmas = <&edma 58 &edma 59>;
-			dma-names = "tx", "rx";
-		};
-
-		i2c2: i2c@4802a000 {
-			compatible = "ti,omap4-i2c";
-			ti,hwmods = "i2c2";
-			reg = <0x4802a000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <71>;
-			dmas = <&edma 60 &edma 61>;
-			dma-names = "tx", "rx";
-		};
-
-		intc: interrupt-controller@48200000 {
-			compatible = "ti,dm816-intc";
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			reg = <0x48200000 0x1000>;
-		};
-
-		rtc: rtc@480c0000 {
-			compatible = "ti,am3352-rtc", "ti,da830-rtc";
-			reg = <0x480c0000 0x1000>;
-			interrupts = <75 76>;
-			ti,hwmods = "rtc";
-		};
-
-		mailbox: mailbox@480c8000 {
-			compatible = "ti,omap4-mailbox";
-			reg = <0x480c8000 0x2000>;
-			interrupts = <77>;
-			ti,hwmods = "mailbox";
-			#mbox-cells = <1>;
-			ti,mbox-num-users = <4>;
-			ti,mbox-num-fifos = <12>;
-			mbox_dsp: mbox-dsp {
-				ti,mbox-tx = <3 0 0>;
-				ti,mbox-rx = <0 0 0>;
-			};
-		};
-
-		spinbox: spinbox@480ca000 {
-			compatible = "ti,omap4-hwspinlock";
-			reg = <0x480ca000 0x2000>;
-			ti,hwmods = "spinbox";
-			#hwlock-cells = <1>;
-		};
-
-		mdio: mdio@4a100800 {
-			compatible = "ti,davinci_mdio";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x4a100800 0x100>;
-			ti,hwmods = "davinci_mdio";
-			bus_freq = <1000000>;
-			phy0: ethernet-phy@0 {
-				reg = <1>;
-			};
-			phy1: ethernet-phy@1 {
-				reg = <2>;
-			};
-		};
-
-		eth0: ethernet@4a100000 {
-			compatible = "ti,dm816-emac";
-			ti,hwmods = "emac0";
-			reg = <0x4a100000 0x800
-			       0x4a100900 0x3700>;
-			clocks = <&sysclk24_ck>;
-			syscon = <&scm_conf>;
-			ti,davinci-ctrl-reg-offset = <0>;
-			ti,davinci-ctrl-mod-reg-offset = <0x900>;
-			ti,davinci-ctrl-ram-offset = <0x2000>;
-			ti,davinci-ctrl-ram-size = <0x2000>;
-			interrupts = <40 41 42 43>;
-			phy-handle = <&phy0>;
-		};
-
-		eth1: ethernet@4a120000 {
-			compatible = "ti,dm816-emac";
-			ti,hwmods = "emac1";
-			reg = <0x4a120000 0x4000>;
-			clocks = <&sysclk24_ck>;
-			syscon = <&scm_conf>;
-			ti,davinci-ctrl-reg-offset = <0>;
-			ti,davinci-ctrl-mod-reg-offset = <0x900>;
-			ti,davinci-ctrl-ram-offset = <0x2000>;
-			ti,davinci-ctrl-ram-size = <0x2000>;
-			interrupts = <44 45 46 47>;
-			phy-handle = <&phy1>;
-		};
-
-		mcspi1: spi@48030000 {
-			compatible = "ti,omap4-mcspi";
-			reg = <0x48030000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <65>;
-			ti,spi-num-cs = <4>;
-			ti,hwmods = "mcspi1";
-			dmas = <&edma 16 &edma 17
-				&edma 18 &edma 19
-				&edma 20 &edma 21
-				&edma 22 &edma 23>;
-			dma-names = "tx0", "rx0", "tx1", "rx1",
-				    "tx2", "rx2", "tx3", "rx3";
-		};
-
-		mmc1: mmc@48060000 {
-			compatible = "ti,omap4-hsmmc";
-			reg = <0x48060000 0x11000>;
-			ti,hwmods = "mmc1";
-			interrupts = <64>;
-			dmas = <&edma 24 &edma 25>;
-			dma-names = "tx", "rx";
-		};
-
-		timer1: timer@4802e000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x4802e000 0x2000>;
-			interrupts = <67>;
-			ti,hwmods = "timer1";
-			ti,timer-alwon;
-		};
-
-		timer2: timer@48040000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x48040000 0x2000>;
-			interrupts = <68>;
-			ti,hwmods = "timer2";
-		};
-
-		timer3: timer@48042000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x48042000 0x2000>;
-			interrupts = <69>;
-			ti,hwmods = "timer3";
-		};
-
-		timer4: timer@48044000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x48044000 0x2000>;
-			interrupts = <92>;
-			ti,hwmods = "timer4";
-			ti,timer-pwm;
-		};
-
-		timer5: timer@48046000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x48046000 0x2000>;
-			interrupts = <93>;
-			ti,hwmods = "timer5";
-			ti,timer-pwm;
-		};
-
-		timer6: timer@48048000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x48048000 0x2000>;
-			interrupts = <94>;
-			ti,hwmods = "timer6";
-			ti,timer-pwm;
-		};
-
-		timer7: timer@4804a000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x4804a000 0x2000>;
-			interrupts = <95>;
-			ti,hwmods = "timer7";
-			ti,timer-pwm;
-		};
-
-		uart1: serial@48020000 {
-			compatible = "ti,am3352-uart", "ti,omap3-uart";
-			ti,hwmods = "uart1";
-			reg = <0x48020000 0x2000>;
-			clock-frequency = <48000000>;
-			interrupts = <72>;
-			dmas = <&edma 26 &edma 27>;
-			dma-names = "tx", "rx";
-		};
-
-		uart2: serial@48022000 {
-			compatible = "ti,am3352-uart", "ti,omap3-uart";
-			ti,hwmods = "uart2";
-			reg = <0x48022000 0x2000>;
-			clock-frequency = <48000000>;
-			interrupts = <73>;
-			dmas = <&edma 28 &edma 29>;
-			dma-names = "tx", "rx";
-		};
-
-		uart3: serial@48024000 {
-			compatible = "ti,am3352-uart", "ti,omap3-uart";
-			ti,hwmods = "uart3";
-			reg = <0x48024000 0x2000>;
-			clock-frequency = <48000000>;
-			interrupts = <74>;
-			dmas = <&edma 30 &edma 31>;
-			dma-names = "tx", "rx";
-		};
-
-		/* NOTE: USB needs a transceiver driver for phys to work */
-		usb: usb_otg_hs@47401000 {
-			compatible = "ti,am33xx-usb";
-			reg = <0x47401000 0x400000>;
-			ranges;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ti,hwmods = "usb_otg_hs";
-
-			usb0: usb@47401000 {
-				compatible = "ti,musb-dm816";
-				reg = <0x47401400 0x400
-				       0x47401000 0x200>;
-				reg-names = "mc", "control";
-				interrupts = <18>;
-				interrupt-names = "mc";
-				dr_mode = "host";
-				interface-type = <0>;
-				phys = <&usb_phy0>;
-				phy-names = "usb2-phy";
-				mentor,multipoint = <1>;
-				mentor,num-eps = <16>;
-				mentor,ram-bits = <12>;
-				mentor,power = <500>;
-
-				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
-					&cppi41dma  2 0 &cppi41dma  3 0
-					&cppi41dma  4 0 &cppi41dma  5 0
-					&cppi41dma  6 0 &cppi41dma  7 0
-					&cppi41dma  8 0 &cppi41dma  9 0
-					&cppi41dma 10 0 &cppi41dma 11 0
-					&cppi41dma 12 0 &cppi41dma 13 0
-					&cppi41dma 14 0 &cppi41dma  0 1
-					&cppi41dma  1 1 &cppi41dma  2 1
-					&cppi41dma  3 1 &cppi41dma  4 1
-					&cppi41dma  5 1 &cppi41dma  6 1
-					&cppi41dma  7 1 &cppi41dma  8 1
-					&cppi41dma  9 1 &cppi41dma 10 1
-					&cppi41dma 11 1 &cppi41dma 12 1
-					&cppi41dma 13 1 &cppi41dma 14 1>;
-				dma-names =
-					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
-					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
-					"rx14", "rx15",
-					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
-					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
-					"tx14", "tx15";
-			};
-
-			usb1: usb@47401800 {
-				compatible = "ti,musb-dm816";
-				reg = <0x47401c00 0x400
-				       0x47401800 0x200>;
-				reg-names = "mc", "control";
-				interrupts = <19>;
-				interrupt-names = "mc";
-				dr_mode = "host";
-				interface-type = <0>;
-				phys = <&usb_phy1>;
-				phy-names = "usb2-phy";
-				mentor,multipoint = <1>;
-				mentor,num-eps = <16>;
-				mentor,ram-bits = <12>;
-				mentor,power = <500>;
-
-				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
-					&cppi41dma 17 0 &cppi41dma 18 0
-					&cppi41dma 19 0 &cppi41dma 20 0
-					&cppi41dma 21 0 &cppi41dma 22 0
-					&cppi41dma 23 0 &cppi41dma 24 0
-					&cppi41dma 25 0 &cppi41dma 26 0
-					&cppi41dma 27 0 &cppi41dma 28 0
-					&cppi41dma 29 0 &cppi41dma 15 1
-					&cppi41dma 16 1 &cppi41dma 17 1
-					&cppi41dma 18 1 &cppi41dma 19 1
-					&cppi41dma 20 1 &cppi41dma 21 1
-					&cppi41dma 22 1 &cppi41dma 23 1
-					&cppi41dma 24 1 &cppi41dma 25 1
-					&cppi41dma 26 1 &cppi41dma 27 1
-					&cppi41dma 28 1 &cppi41dma 29 1>;
-				dma-names =
-					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
-					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
-					"rx14", "rx15",
-					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
-					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
-					"tx14", "tx15";
-			};
-
-			cppi41dma: dma-controller@47402000 {
-				compatible = "ti,am3359-cppi41";
-				reg =  <0x47400000 0x1000
-					0x47402000 0x1000
-					0x47403000 0x1000
-					0x47404000 0x4000>;
-				reg-names = "glue", "controller", "scheduler", "queuemgr";
-				interrupts = <17>;
-				interrupt-names = "glue";
-				#dma-cells = <2>;
-				#dma-channels = <30>;
-				#dma-requests = <256>;
-			};
-		};
-
-		wd_timer2: wd_timer@480c2000 {
-			compatible = "ti,omap3-wdt";
-			ti,hwmods = "wd_timer";
-			reg = <0x480c2000 0x1000>;
-			interrupts = <0>;
-		};
-	};
-};
-
-#include "dm816x-clocks.dtsi"
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 06b36cc658..dde0c4091f 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -51,7 +51,7 @@
 
 	idle-states {
 		/*
-		 * PSCI node is not added default, U-boot will add missing
+		 * PSCI node is not added default, U-Boot will add missing
 		 * parts if it determines to use PSCI.
 		 */
 		entry-method = "psci";
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index 884bdad196..5e02cd91d7 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -7,7 +7,7 @@
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
 
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
 
 / {
 	model = "LS1043A QDS Board";
diff --git a/arch/arm/dts/fsl-ls1043a-rdb-u-boot.dtsi b/arch/arm/dts/fsl-ls1043a-rdb-u-boot.dtsi
new file mode 100644
index 0000000000..ef31c79fa0
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-rdb-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+#include "fsl-ls1043a-u-boot.dtsi"
+
diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts
index 9e7c79fd2b..f5b3bb68b3 100644
--- a/arch/arm/dts/fsl-ls1043a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1043a-rdb.dts
@@ -9,13 +9,17 @@
  */
 
 /dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
 
 / {
 	model = "LS1043A RDB Board";
 
         aliases {
 		spi1 = &dspi0;
+		serial0 = &duart0;
+		serial1 = &duart1;
+		serial2 = &duart2;
+		serial3 = &duart3;
         };
 
 };
diff --git a/arch/arm/dts/fsl-ls1043a-u-boot.dtsi b/arch/arm/dts/fsl-ls1043a-u-boot.dtsi
new file mode 100644
index 0000000000..65a870511c
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+&duart0 {
+	bootph-all;
+};
+
+&duart1 {
+	bootph-all;
+};
+
+&duart2 {
+	bootph-all;
+};
+
+&duart3 {
+	bootph-all;
+};
+
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 4960973a60..21643a1d95 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -8,7 +8,9 @@
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
 
-/include/ "skeleton64.dtsi"
+#include "skeleton64.dtsi"
+#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
 	compatible = "fsl,ls1043a";
@@ -223,28 +225,32 @@
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x00 0x21c0500 0x0 0x100>;
 			interrupts = <0 54 0x4>;
-			clocks = <&clockgen 4 0>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(1)>;
 		};
 
 		duart1: serial@21c0600 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x00 0x21c0600 0x0 0x100>;
 			interrupts = <0 54 0x4>;
-			clocks = <&clockgen 4 0>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(1)>;
 		};
 
 		duart2: serial@21d0500 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x0 0x21d0500 0x0 0x100>;
 			interrupts = <0 55 0x4>;
-			clocks = <&clockgen 4 0>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(1)>;
 		};
 
 		duart3: serial@21d0600 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x0 0x21d0600 0x0 0x100>;
 			interrupts = <0 55 0x4>;
-			clocks = <&clockgen 4 0>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(1)>;
 		};
 
 		lpuart0: serial@2950000 {
diff --git a/arch/arm/dts/fsl-ls1046a-frwy-u-boot.dtsi b/arch/arm/dts/fsl-ls1046a-frwy-u-boot.dtsi
new file mode 100644
index 0000000000..ce204e675b
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-frwy-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+#include "fsl-ls1046a-u-boot.dtsi"
+
diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts
index cda05411d8..ba10d212f1 100644
--- a/arch/arm/dts/fsl-ls1046a-frwy.dts
+++ b/arch/arm/dts/fsl-ls1046a-frwy.dts
@@ -2,22 +2,42 @@
 /*
  * Device Tree Include file for NXP Layerscape-1046A family SoC.
  *
- * Copyright 2019 NXP
+ * Copyright 2019-2023 NXP
  *
  */
 
 /dts-v1/;
-/include/ "fsl-ls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
 
 / {
 	model = "LS1046A FRWY Board";
 
 	aliases {
 		spi0 = &qspi;
+		serial0 = &duart0;
+		serial1 = &duart1;
+		serial2 = &duart2;
+		serial3 = &duart3;
 	};
 
 };
 
+&duart0 {
+	status = "okay";
+};
+
+&duart1 {
+	status = "okay";
+};
+
+&duart2 {
+	status = "okay";
+};
+
+&duart3 {
+	status = "okay";
+};
+
 &qspi {
 	status = "okay";
 
@@ -34,3 +54,49 @@
 &i2c0 {
 	status = "okay";
 };
+
+#include "fsl-ls1046-post.dtsi"
+
+&fman0 {
+	ethernet@e0000 {
+		phy-handle = <&qsgmii_phy4>;
+		phy-connection-type = "qsgmii";
+		status = "okay";
+	};
+
+	ethernet@e8000 {
+		phy-handle = <&qsgmii_phy2>;
+		phy-connection-type = "qsgmii";
+		status = "okay";
+	};
+
+	ethernet@ea000 {
+		phy-handle = <&qsgmii_phy1>;
+		phy-connection-type = "qsgmii";
+		status = "okay";
+	};
+
+	ethernet@f2000 {
+		phy-handle = <&qsgmii_phy3>;
+		phy-connection-type = "qsgmii";
+		status = "okay";
+	};
+
+	mdio@fd000 {
+		qsgmii_phy1: ethernet-phy@1c {
+			reg = <0x1c>;
+		};
+
+		qsgmii_phy2: ethernet-phy@1d {
+			reg = <0x1d>;
+		};
+
+		qsgmii_phy3: ethernet-phy@1e {
+			reg = <0x1e>;
+		};
+
+		qsgmii_phy4: ethernet-phy@1f {
+			reg = <0x1f>;
+		};
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi
index fec5c8ddb2..d66824975c 100644
--- a/arch/arm/dts/fsl-ls1046a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi
@@ -7,7 +7,7 @@
  * Mingkai Hu <Mingkai.hu@nxp.com>
  */
 
-/include/ "fsl-ls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
 
 / {
 	model = "LS1046A QDS Board";
diff --git a/arch/arm/dts/fsl-ls1046a-rdb-u-boot.dtsi b/arch/arm/dts/fsl-ls1046a-rdb-u-boot.dtsi
new file mode 100644
index 0000000000..ce204e675b
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-rdb-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+#include "fsl-ls1046a-u-boot.dtsi"
+
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
index 464129291c..66d718905c 100644
--- a/arch/arm/dts/fsl-ls1046a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -9,17 +9,29 @@
  */
 
 /dts-v1/;
-/include/ "fsl-ls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
 
 / {
 	model = "LS1046A RDB Board";
 
 	aliases {
 		spi0 = &qspi;
+		serial0 = &duart0;
+		serial1 = &duart1;
+		serial2 = &duart2;
+		serial3 = &duart3;
 	};
 
 };
 
+&duart0 {
+	status = "okay";
+};
+
+&duart1 {
+	status = "okay";
+};
+
 &qspi {
 	status = "okay";
 
diff --git a/arch/arm/dts/fsl-ls1046a-u-boot.dtsi b/arch/arm/dts/fsl-ls1046a-u-boot.dtsi
new file mode 100644
index 0000000000..65a870511c
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+&duart0 {
+	bootph-all;
+};
+
+&duart1 {
+	bootph-all;
+};
+
+&duart2 {
+	bootph-all;
+};
+
+&duart3 {
+	bootph-all;
+};
+
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 060dc399c2..44ee4c5808 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -8,7 +8,9 @@
  * Mingkai Hu <mingkai.hu@nxp.com>
  */
 
-/include/ "skeleton64.dtsi"
+#include "skeleton64.dtsi"
+#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
 	compatible = "fsl,ls1046a";
@@ -222,29 +224,37 @@
 		duart0: serial@21c0500 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x00 0x21c0500 0x0 0x100>;
-			interrupts = <0 54 0x4>;
-			clocks = <&clockgen 4 0>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(2)>;
+			status = "disabled";
 		};
 
 		duart1: serial@21c0600 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x00 0x21c0600 0x0 0x100>;
-			interrupts = <0 54 0x4>;
-			clocks = <&clockgen 4 0>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(2)>;
+			status = "disabled";
 		};
 
 		duart2: serial@21d0500 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x0 0x21d0500 0x0 0x100>;
-			interrupts = <0 55 0x4>;
-			clocks = <&clockgen 4 0>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(2)>;
+			status = "disabled";
 		};
 
 		duart3: serial@21d0600 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x0 0x21d0600 0x0 0x100>;
-			interrupts = <0 55 0x4>;
-			clocks = <&clockgen 4 0>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(2)>;
+			status = "disabled";
 		};
 
 		lpuart0: serial@2950000 {
diff --git a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi
index 89566bf849..4e6700d586 100644
--- a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi
@@ -6,6 +6,16 @@
 /{
 	aliases {
 		spi0 = &qspi;
+		ethernet0 = &dpmac7;
+		ethernet1 = &dpmac8;
+		ethernet2 = &dpmac9;
+		ethernet3 = &dpmac10;
+		ethernet4 = &dpmac3;
+		ethernet5 = &dpmac4;
+		ethernet6 = &dpmac5;
+		ethernet7 = &dpmac6;
+		ethernet8 = &dpmac2;
+		ethernet9 = &dpmac1;
 	};
 };
 
diff --git a/arch/arm/dts/imx28-xea-u-boot.dtsi b/arch/arm/dts/imx28-xea-u-boot.dtsi
index f6488154d8..bdbeca528c 100644
--- a/arch/arm/dts/imx28-xea-u-boot.dtsi
+++ b/arch/arm/dts/imx28-xea-u-boot.dtsi
@@ -12,6 +12,11 @@
  */
 #include "imx28-u-boot.dtsi"
 / {
+	aliases {
+		/delete-property/ spi1;
+		/delete-property/ usbphy0;
+		/delete-property/ usbphy1;
+	};
 	apb@80000000 {
 		bootph-pre-ram;
 
@@ -27,16 +32,47 @@
 
 &clks {
 	bootph-pre-ram;
+	status = "disable";
+};
+
+&duart {
+	/delete-property/ clocks;
+	bootph-pre-ram;
+	type = <1>; /* TYPE_PL011 */
 };
 
 &gpio0 {
 	bootph-pre-ram;
 };
 
+&mac0 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mac0_pins_a>;
+	phy-supply = <&reg_fec_3v3>;
+	phy-reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <1>;
+	phy-reset-post-delay = <1>;
+	status = "okay";
+
+	fixed-link {
+		speed = <100>;
+		full-duplex;
+	};
+};
+
 &pinctrl {
+	/delete-property/ pinctrl-names;
+	/delete-property/ pinctrl-0;
 	bootph-pre-ram;
 };
 
+&reg_fec_3v3 {
+	gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+	enable-active-high;
+	regulator-boot-on;
+};
+
 &ssp0 {
 	bootph-pre-ram;
 };
@@ -46,3 +82,12 @@
 	spi-max-frequency = <40000000>;
 	bootph-pre-ram;
 };
+
+/delete-node/ &ssp2;
+/delete-node/ &usb0;
+/delete-node/ &usbphy0;
+/delete-node/ &usb1;
+/delete-node/ &usbphy1;
+/delete-node/ &hog_pins_a;
+/delete-node/ &hog_pins_tiva;
+/delete-node/ &hog_pins_coding;
diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
index fd0061f00f..00abbeb22f 100644
--- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
@@ -6,6 +6,10 @@
 #include "imx8mm-u-boot.dtsi"
 
 / {
+	aliases {
+		spi0 = &flexspi;
+	};
+
 	wdt-reboot {
 		compatible = "wdt-reboot";
 		wdt = <&wdog1>;
diff --git a/arch/arm/dts/imx8mm-mx8menlo.dts b/arch/arm/dts/imx8mm-mx8menlo.dts
index 32f6f2f50c..0b123a8401 100644
--- a/arch/arm/dts/imx8mm-mx8menlo.dts
+++ b/arch/arm/dts/imx8mm-mx8menlo.dts
@@ -10,6 +10,7 @@
 / {
 	model = "MENLO MX8MM EMBEDDED DEVICE";
 	compatible = "menlo,mx8menlo",
+		     "toradex,verdin-imx8mm-nonwifi",
 		     "toradex,verdin-imx8mm",
 		     "fsl,imx8mm";
 
@@ -250,21 +251,21 @@
 		/* SODIMM 96 */
 		MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4			0x1c4
 		/* CPLD_D[7] */
-		MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5			0x1c4
+		MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5			0x184
 		/* CPLD_D[6] */
-		MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0			0x1c4
+		MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0			0x184
 		/* CPLD_D[5] */
-		MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11			0x1c4
+		MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11			0x184
 		/* CPLD_D[4] */
-		MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12			0x1c4
+		MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12			0x184
 		/* CPLD_D[3] */
-		MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13			0x1c4
+		MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13			0x184
 		/* CPLD_D[2] */
-		MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14			0x1c4
+		MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14			0x184
 		/* CPLD_D[1] */
-		MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15			0x1c4
+		MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15			0x184
 		/* CPLD_D[0] */
-		MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16			0x1c4
+		MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16			0x184
 		/* KBD_intK */
 		MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27			0x1c4
 		/* DISP_reset */
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 7fd5a05fad..035282bf0b 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -81,7 +81,9 @@
 
 		fit {
 			description = "Configuration to load ATF before U-Boot";
+#ifndef CONFIG_IMX_HAB
 			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+#endif
 			fit,fdt-list = "of-list";
 			#address-cells = <1>;
 
diff --git a/arch/arm/dts/imx8mm-verdin-dahlia.dtsi b/arch/arm/dts/imx8mm-verdin-dahlia.dtsi
deleted file mode 100644
index c2a5c2f7b2..0000000000
--- a/arch/arm/dts/imx8mm-verdin-dahlia.dtsi
+++ /dev/null
@@ -1,150 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright 2022 Toradex
- */
-
-/ {
-	sound_card: sound-card {
-		compatible = "simple-audio-card";
-		simple-audio-card,bitclock-master = <&dailink_master>;
-		simple-audio-card,format = "i2s";
-		simple-audio-card,frame-master = <&dailink_master>;
-		simple-audio-card,name = "imx8mm-wm8904";
-		simple-audio-card,routing =
-			"Headphone Jack", "HPOUTL",
-			"Headphone Jack", "HPOUTR",
-			"IN2L", "Line In Jack",
-			"IN2R", "Line In Jack",
-			"Headphone Jack", "MICBIAS",
-			"IN1L", "Headphone Jack";
-		simple-audio-card,widgets =
-			"Microphone", "Headphone Jack",
-			"Headphone", "Headphone Jack",
-			"Line", "Line In Jack";
-
-		dailink_master: simple-audio-card,codec {
-			clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
-			sound-dai = <&wm8904_1a>;
-		};
-
-		simple-audio-card,cpu {
-			sound-dai = <&sai2>;
-		};
-	};
-};
-
-/* Verdin SPI_1 */
-&ecspi2 {
-	status = "okay";
-};
-
-/* EEPROM on display adapter boards */
-&eeprom_display_adapter {
-	status = "okay";
-};
-
-/* EEPROM on Verdin Development board */
-&eeprom_carrier_board {
-	status = "okay";
-};
-
-&fec1 {
-	status = "okay";
-};
-
-/* Verdin QSPI_1 */
-&flexspi {
-	status = "okay";
-};
-
-/* Current measurement into module VCC */
-&hwmon {
-	status = "okay";
-};
-
-&hwmon_temp {
-	vs-supply = <&reg_1p8v>;
-	status = "okay";
-};
-
-&i2c3 {
-	status = "okay";
-};
-
-/* Verdin I2C_1 */
-&i2c4 {
-	status = "okay";
-
-	/* Audio Codec */
-	wm8904_1a: audio-codec@1a {
-		compatible = "wlf,wm8904";
-		AVDD-supply = <&reg_3p3v>;
-		clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
-		clock-names = "mclk";
-		CPVDD-supply = <&reg_3p3v>;
-		DBVDD-supply = <&reg_3p3v>;
-		DCVDD-supply = <&reg_3p3v>;
-		MICVDD-supply = <&reg_3p3v>;
-		reg = <0x1a>;
-		#sound-dai-cells = <0>;
-	};
-};
-
-/* Verdin PCIE_1 */
-&pcie0 {
-	status = "okay";
-};
-
-&pcie_phy {
-	status = "okay";
-};
-
-/* Verdin PWM_3_DSI */
-&pwm1 {
-	status = "okay";
-};
-
-/* Verdin PWM_1 */
-&pwm2 {
-	status = "okay";
-};
-
-/* Verdin PWM_2 */
-&pwm3 {
-	status = "okay";
-};
-
-/* Verdin I2S_1 */
-&sai2 {
-	status = "okay";
-};
-
-/* Verdin UART_3 */
-&uart1 {
-	status = "okay";
-};
-
-/* Verdin UART_1 */
-&uart2 {
-	status = "okay";
-};
-
-/* Verdin UART_2 */
-&uart3 {
-	status = "okay";
-};
-
-/* Verdin USB_1 */
-&usbotg1 {
-	status = "okay";
-};
-
-/* Verdin USB_2 */
-&usbotg2 {
-	status = "okay";
-};
-
-/* Verdin SD_1 */
-&usdhc2 {
-	status = "okay";
-};
diff --git a/arch/arm/dts/imx8mm-verdin-dev.dtsi b/arch/arm/dts/imx8mm-verdin-dev.dtsi
index 73cc3fafa0..3c4b8ca125 100644
--- a/arch/arm/dts/imx8mm-verdin-dev.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-dev.dtsi
@@ -3,14 +3,13 @@
  * Copyright 2022 Toradex
  */
 
-#include "imx8mm-verdin-dahlia.dtsi"
-
 / {
 	sound_card: sound-card {
 		compatible = "simple-audio-card";
 		simple-audio-card,bitclock-master = <&dailink_master>;
 		simple-audio-card,format = "i2s";
 		simple-audio-card,frame-master = <&dailink_master>;
+		simple-audio-card,mclk-fs = <256>;
 		simple-audio-card,name = "imx8mm-nau8822";
 		simple-audio-card,routing =
 			"Headphones", "LHP",
@@ -41,27 +40,121 @@
 	};
 };
 
+/* Verdin SPI_1 */
+&ecspi2 {
+	status = "okay";
+};
+
+/* EEPROM on display adapter boards */
+&eeprom_display_adapter {
+	status = "okay";
+};
+
+/* EEPROM on Verdin Development board */
+&eeprom_carrier_board {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+};
+
+/* Verdin QSPI_1 */
+&flexspi {
+	status = "okay";
+};
+
+/* Current measurement into module VCC */
+&hwmon {
+	status = "okay";
+};
+
+&hwmon_temp {
+	vs-supply = <&reg_1p8v>;
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
 &gpio_expander_21 {
 	status = "okay";
 };
 
 /* Verdin I2C_1 */
 &i2c4 {
+	status = "okay";
+
 	/* Audio Codec */
 	nau8822_1a: audio-codec@1a {
 		compatible = "nuvoton,nau8822";
 		reg = <0x1a>;
+		#sound-dai-cells = <0>;
 	};
 };
 
+/* Verdin PCIE_1 */
+&pcie0 {
+	status = "okay";
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+/* Verdin PWM_3_DSI */
+&pwm1 {
+	status = "okay";
+};
+
+/* Verdin PWM_1 */
+&pwm2 {
+	status = "okay";
+};
+
+/* Verdin PWM_2 */
+&pwm3 {
+	status = "okay";
+};
+
+/* Verdin I2S_1 */
+&sai2 {
+	status = "okay";
+};
+
+/* Verdin UART_3 */
+&uart1 {
+	status = "okay";
+};
+
 /* Verdin UART_1, connector X50 through RS485 transceiver */
 &uart2 {
 	linux,rs485-enabled-at-boot-time;
 	rs485-rts-active-low;
 	rs485-rx-during-tx;
+	status = "okay";
+};
+
+/* Verdin UART_2 */
+&uart3 {
+	status = "okay";
+};
+
+/* Verdin USB_1 */
+&usbotg1 {
+	disable-over-current;
+	status = "okay";
+};
+
+/* Verdin USB_2 */
+&usbotg2 {
+	disable-over-current;
+	status = "okay";
 };
 
 /* Limit frequency on dev board due to long traces and bad signal integrity */
 &usdhc2 {
 	max-frequency = <100000000>;
+	status = "okay";
 };
diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
index 494229e4e6..2b268f55cb 100644
--- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
@@ -56,6 +56,10 @@
 
 &gpio5 {
 	bootph-pre-ram;
+
+	ctrl-sleep-moci-hog {
+		bootph-pre-ram;
+	};
 };
 
 &i2c1 {
@@ -88,6 +92,10 @@
 	};
 };
 
+&pinctrl_ctrl_sleep_moci {
+	bootph-pre-ram;
+};
+
 &pinctrl_i2c1 {
 	bootph-pre-ram;
 };
diff --git a/arch/arm/dts/imx8mm-verdin.dtsi b/arch/arm/dts/imx8mm-verdin.dtsi
index bcab830c6e..6f08115871 100644
--- a/arch/arm/dts/imx8mm-verdin.dtsi
+++ b/arch/arm/dts/imx8mm-verdin.dtsi
@@ -3,8 +3,8 @@
  * Copyright 2022 Toradex
  */
 
-#include "dt-bindings/phy/phy-imx8-pcie.h"
-#include "dt-bindings/pwm/pwm.h"
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/pwm/pwm.h>
 #include "imx8mm.dtsi"
 
 / {
@@ -56,7 +56,11 @@
 	hdmi_connector: hdmi-connector {
 		compatible = "hdmi-connector";
 		ddc-i2c-bus = <&i2c2>;
+		/* Verdin PWM_3_DSI (SODIMM 19) */
+		hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 		label = "hdmi";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
 		type = "a";
 		status = "disabled";
 	};
@@ -95,9 +99,10 @@
 		compatible = "regulator-fixed";
 		enable-active-high;
 		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
-		off-on-delay = <500000>;
+		off-on-delay-us = <500000>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_reg_eth>;
+		regulator-always-on;
 		regulator-boot-on;
 		regulator-max-microvolt = <3300000>;
 		regulator-min-microvolt = <3300000>;
@@ -134,7 +139,7 @@
 		enable-active-high;
 		/* Verdin SD_1_PWR_EN (SODIMM 76) */
 		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
-		off-on-delay = <100000>;
+		off-on-delay-us = <100000>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
 		regulator-max-microvolt = <3300000>;
@@ -183,15 +188,15 @@
 	ddrc_opp_table: opp-table {
 		compatible = "operating-points-v2";
 
-		opp-25M {
+		opp-25000000 {
 			opp-hz = /bits/ 64 <25000000>;
 		};
 
-		opp-100M {
+		opp-100000000 {
 			opp-hz = /bits/ 64 <100000000>;
 		};
 
-		opp-750M {
+		opp-750000000 {
 			opp-hz = /bits/ 64 <750000000>;
 		};
 	};
@@ -358,7 +363,6 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pmic>;
 		reg = <0x25>;
-		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 
 		/*
 		 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
@@ -598,7 +602,7 @@
 	hdmi_lontium_lt8912: hdmi@48 {
 		compatible = "lontium,lt8912b";
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
+		pinctrl-0 = <&pinctrl_gpio_10_dsi>;
 		reg = <0x48>;
 		/* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
 		/* Verdin GPIO_10_DSI (SODIMM 21) */
@@ -610,7 +614,7 @@
 		compatible = "atmel,maxtouch";
 		/*
 		 * Verdin GPIO_9_DSI
-		 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
+		 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
 		 */
 		interrupt-parent = <&gpio3>;
 		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
@@ -653,9 +657,6 @@
 	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 				 <&clk IMX8MM_SYS_PLL2_250M>;
 	assigned-clock-rates = <10000000>, <250000000>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&clk IMX8MM_CLK_PCIE1_PHY>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	/* PCIE_1_RESET# (SODIMM 244) */
@@ -664,6 +665,7 @@
 
 &pcie_phy {
 	clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+	clock-names = "ref";
 	fsl,clkreq-unsupported;
 	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
 	fsl,tx-deemph-gen1 = <0x2d>;
@@ -739,7 +741,6 @@
 	adp-disable;
 	dr_mode = "otg";
 	hnp-disable;
-	over-current-active-low;
 	samsung,picophy-dc-vol-level-adjust = <7>;
 	samsung,picophy-pre-emp-curr-control = <3>;
 	srp-disable;
@@ -749,7 +750,6 @@
 /* Verdin USB_2 */
 &usbotg2 {
 	dr_mode = "host";
-	over-current-active-low;
 	samsung,picophy-dc-vol-level-adjust = <7>;
 	samsung,picophy-pre-emp-curr-control = <3>;
 	vbus-supply = <&reg_usb_otg2_vbus>;
diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi
index cef20dab46..5046b38e4e 100644
--- a/arch/arm/dts/imx8mn-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-u-boot.dtsi
@@ -145,7 +145,9 @@
 
 		fit {
 			description = "Configuration to load ATF before U-Boot";
+#ifndef CONFIG_IMX_HAB
 			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+#endif
 			fit,fdt-list = "of-list";
 			#address-cells = <1>;
 
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index af80aaea0b..e0caf3179e 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -13,6 +13,19 @@
 	bootph-pre-ram;
 };
 
+&eeprom_som {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	eth_mac_address: eth-mac-address@19 {
+		reg = <0x19 0x06>;
+	};
+};
+
+&fec1 {
+	nvmem-cells = <&eth_mac_address>;
+	nvmem-cell-names = "mac-address";
+};
+
 &gpio1 {
 	bootph-pre-ram;
 };
@@ -68,3 +81,7 @@
 &usdhc3 {
 	bootph-pre-ram;
 };
+
+&eeprom_som {
+	bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts b/arch/arm/dts/imx8mn-var-som-symphony.dts
index 3ed7021a48..5c8e4e8175 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony.dts
+++ b/arch/arm/dts/imx8mn-var-som-symphony.dts
@@ -56,10 +56,6 @@
 	};
 };
 
-&ethphy {
-	reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
-};
-
 &i2c2 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi
index 87b5e23c76..4eb578a03f 100644
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ b/arch/arm/dts/imx8mn-var-som.dtsi
@@ -11,6 +11,10 @@
 	model = "Variscite VAR-SOM-MX8MN module";
 	compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
 
+	aliases {
+		eeprom-som = &eeprom_som;
+	};
+
 	chosen {
 		stdout-path = &uart4;
 	};
@@ -98,11 +102,17 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ethphy: ethernet-phy@4 {
+		ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <4>;
 			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <10000>;
+			/*
+			 * Deassert delay:
+			 * ADIN1300 requires 5ms.
+			 * AR8033   requires 1ms.
+			 */
+			reset-deassert-us = <20000>;
 		};
 	};
 };
@@ -222,6 +232,12 @@
 			};
 		};
 	};
+
+	eeprom_som: eeprom@52 {
+		compatible = "atmel,24c04";
+		reg = <0x52>;
+		pagesize = <16>;
+	};
 };
 
 &i2c3 {
diff --git a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
index 5ca631e9d8..b56f3a2bd2 100644
--- a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
@@ -185,12 +185,10 @@
 
 &usb3_0 {
 	dma-ranges = <0x40000000 0x40000000 0xc0000000>;
-	/delete-property/ power-domains;
 };
 
 &usb3_1 {
 	dma-ranges = <0x40000000 0x40000000 0xc0000000>;
-	/delete-property/ power-domains;
 };
 
 &usb_dwc3_0 {
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
index 18d1728e1d..36e7444a62 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -44,6 +44,9 @@
 
 &aips3 {
 	bootph-pre-ram;
+	spba-bus@30800000 {
+		bootph-pre-ram;
+	};
 };
 
 &iomuxc {
@@ -103,7 +106,9 @@
 
 		fit {
 			description = "Configuration to load ATF before U-Boot";
+#ifndef CONFIG_IMX_HAB
 			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+#endif
 			fit,fdt-list = "of-list";
 			#address-cells = <1>;
 
diff --git a/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi
new file mode 100644
index 0000000000..b9e3db7de9
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+#include "imx8mp-venice-u-boot.dtsi"
+
+&eqos {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw702x.dtsi b/arch/arm/dts/imx8mp-venice-gw702x.dtsi
new file mode 100644
index 0000000000..560c68e4da
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw702x.dtsi
@@ -0,0 +1,587 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+	aliases {
+		ethernet0 = &eqos;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0 0x80000000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-user-pb {
+			label = "user_pb";
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_0>;
+		};
+
+		key-user-pb1x {
+			label = "user_pb1x";
+			linux,code = <BTN_1>;
+			interrupt-parent = <&gsc>;
+			interrupts = <0>;
+		};
+
+		key-erased {
+			label = "key_erased";
+			linux,code = <BTN_2>;
+			interrupt-parent = <&gsc>;
+			interrupts = <1>;
+		};
+
+		key-eeprom-wp {
+			label = "eeprom_wp";
+			linux,code = <BTN_3>;
+			interrupt-parent = <&gsc>;
+			interrupts = <2>;
+		};
+
+		key-tamper {
+			label = "tamper";
+			linux,code = <BTN_4>;
+			interrupt-parent = <&gsc>;
+			interrupts = <5>;
+		};
+
+		switch-hold {
+			label = "switch_hold";
+			linux,code = <BTN_5>;
+			interrupt-parent = <&gsc>;
+			interrupts = <7>;
+		};
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck3_reg>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck3_reg>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck3_reg>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck3_reg>;
+};
+
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			pinctrl-0 = <&pinctrl_ethphy0>;
+			pinctrl-names = "default";
+			reg = <0x0>;
+			interrupt-parent = <&gpio3>;
+			interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	gsc: gsc@20 {
+		compatible = "gw,gsc";
+		reg = <0x20>;
+		pinctrl-0 = <&pinctrl_gsc>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		adc {
+			compatible = "gw,gsc-adc";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			channel@6 {
+				gw,mode = <0>;
+				reg = <0x06>;
+				label = "temp";
+			};
+
+			channel@8 {
+				gw,mode = <3>;
+				reg = <0x08>;
+				label = "vdd_bat";
+			};
+
+			channel@16 {
+				gw,mode = <4>;
+				reg = <0x16>;
+				label = "fan_tach";
+			};
+
+			channel@82 {
+				gw,mode = <2>;
+				reg = <0x82>;
+				label = "vdd_vin";
+				gw,voltage-divider-ohms = <22100 1000>;
+			};
+
+			channel@84 {
+				gw,mode = <2>;
+				reg = <0x84>;
+				label = "vdd_adc1";
+				gw,voltage-divider-ohms = <10000 10000>;
+			};
+
+			channel@86 {
+				gw,mode = <2>;
+				reg = <0x86>;
+				label = "vdd_adc2";
+				gw,voltage-divider-ohms = <10000 10000>;
+			};
+
+			channel@88 {
+				gw,mode = <2>;
+				reg = <0x88>;
+				label = "vdd_1p0";
+			};
+
+			channel@8c {
+				gw,mode = <2>;
+				reg = <0x8c>;
+				label = "vdd_1p8";
+			};
+
+			channel@8e {
+				gw,mode = <2>;
+				reg = <0x8e>;
+				label = "vdd_2p5";
+			};
+
+			channel@90 {
+				gw,mode = <2>;
+				reg = <0x90>;
+				label = "vdd_3p3";
+				gw,voltage-divider-ohms = <10000 10000>;
+			};
+
+			channel@92 {
+				gw,mode = <2>;
+				reg = <0x92>;
+				label = "vdd_dram";
+			};
+
+			channel@98 {
+				gw,mode = <2>;
+				reg = <0x98>;
+				label = "vdd_soc";
+			};
+
+			channel@9a {
+				gw,mode = <2>;
+				reg = <0x9a>;
+				label = "vdd_arm";
+			};
+
+			channel@a2 {
+				gw,mode = <2>;
+				reg = <0xa2>;
+				label = "vdd_gsc";
+				gw,voltage-divider-ohms = <10000 10000>;
+			};
+		};
+
+		fan-controller@0 {
+			compatible = "gw,gsc-fan";
+			reg = <0x0a>;
+		};
+	};
+
+	gpio: gpio@23 {
+		compatible = "nxp,pca9555";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gsc>;
+		interrupts = <4>;
+	};
+
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+
+	eeprom@51 {
+		compatible = "atmel,24c02";
+		reg = <0x51>;
+		pagesize = <16>;
+	};
+
+	eeprom@52 {
+		compatible = "atmel,24c02";
+		reg = <0x52>;
+		pagesize = <16>;
+	};
+
+	eeprom@53 {
+		compatible = "atmel,24c02";
+		reg = <0x53>;
+		pagesize = <16>;
+	};
+
+	rtc@68 {
+		compatible = "dallas,ds1672";
+		reg = <0x68>;
+	};
+
+	pmic@69 {
+		compatible = "mps,mp5416";
+		reg = <0x69>;
+
+		regulators {
+			/* vdd_soc */
+			buck1 {
+				regulator-name = "buck1";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			/* vdd_dram */
+			buck2 {
+				regulator-name = "buck2";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			/* vdd_arm */
+			buck3_reg: buck3 {
+				regulator-name = "buck3";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			/* vdd_1p8 */
+			buck4 {
+				regulator-name = "buck4";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			/* OUT2: nvcc_snvs_1p8 */
+			ldo1 {
+				regulator-name = "ldo1";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			/* OUT3: vdd_1p0 */
+			ldo2 {
+				regulator-name = "ldo2";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			/* OUT4: vdd_2p5 */
+			ldo3 {
+				regulator-name = "ldo3";
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			/* OUT5: vdd_3p3 */
+			ldo4 {
+				regulator-name = "ldo4";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+		};
+	};
+};
+
+/* off-board header */
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	eeprom@52 {
+		compatible = "atmel,24c32";
+		reg = <0x52>;
+		pagesize = <32>;
+	};
+};
+
+/* off-board header */
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+/* off-board header */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+/* console */
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+/* off-board header */
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+/* off-board */
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x2
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x2
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
+		>;
+	};
+
+	pinctrl_ethphy0: ethphy0grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x140 /* RST# */
+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x150 /* IRQ# */
+		>;
+	};
+
+	pinctrl_gsc: gscgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x150 /* IRQ# */
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x400001c2
+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x400001c2
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x400001c2
+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x400001c2
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
+		>;
+	};
+
+	pinctrl_i2c3_gpio: i2c3gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x400001c2
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x400001c2
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140
+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi
new file mode 100644
index 0000000000..981841cee0
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+#include "imx8mp-venice-gw702x-u-boot.dtsi"
+
+&gpio1 {
+	app_gpioa {
+		gpio-hog;
+		input;
+		gpios = <13 GPIO_ACTIVE_HIGH>;
+		line-name = "gpioa";
+	};
+};
+
+&gpio4 {
+	app_gpiod {
+		gpio-hog;
+		input;
+		gpios = <1 GPIO_ACTIVE_HIGH>;
+		line-name = "gpiod";
+	};
+
+	app_gpiob {
+		gpio-hog;
+		input;
+		gpios = <4 GPIO_ACTIVE_HIGH>;
+		line-name = "gpiob";
+	};
+
+	app_gpioc {
+		gpio-hog;
+		input;
+		gpios = <5 GPIO_ACTIVE_HIGH>;
+		line-name = "gpioc";
+	};
+
+	pci_usb_sel {
+		gpio-hog;
+		output-low;
+		gpios = <26 GPIO_ACTIVE_HIGH>;
+		line-name = "pci_usb_sel";
+	};
+
+	pci_wdis {
+		gpio-hog;
+		output-high;
+		gpios = <28 GPIO_ACTIVE_HIGH>;
+		line-name = "pci_wdis#";
+	};
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw7905-2x.dts b/arch/arm/dts/imx8mp-venice-gw7905-2x.dts
new file mode 100644
index 0000000000..4a1bbbbe19
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw7905-2x.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mp.dtsi"
+#include "imx8mp-venice-gw702x.dtsi"
+#include "imx8mp-venice-gw7905.dtsi"
+
+/ {
+	model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit";
+	compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+/* Disable SOM interfaces not used on baseboard */
+&eqos {
+	status = "disabled";
+};
+
+&usdhc1 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw7905.dtsi b/arch/arm/dts/imx8mp-venice-gw7905.dtsi
new file mode 100644
index 0000000000..0d40cb0f05
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw7905.dtsi
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+/ {
+	led-controller {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		led-0 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+
+		led-1 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	pps {
+		compatible = "pps-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pps>;
+		gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	reg_usb2_vbus: regulator-usb2-vbus {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usb2_en>;
+		compatible = "regulator-fixed";
+		regulator-name = "usb2_vbus";
+		gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		compatible = "regulator-fixed";
+		regulator-name = "SD2_3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+/* off-board header */
+&ecspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi2>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&gpio4 {
+	gpio-line-names =
+		"", "", "", "",
+		"", "", "", "",
+		"", "", "", "",
+		"", "gpioa", "", "",
+		"", "", "", "",
+		"", "", "", "",
+		"", "", "", "",
+		"", "", "", "";
+};
+
+&gpio4 {
+	gpio-line-names =
+		"", "gpiod", "", "",
+		"gpiob", "gpioc", "", "",
+		"", "", "", "",
+		"", "", "", "",
+		"", "", "", "",
+		"", "", "", "",
+		"", "", "pci_usb_sel", "",
+		"pci_wdis#", "", "", "";
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	eeprom@52 {
+		compatible = "atmel,24c32";
+		reg = <0x52>;
+		pagesize = <32>;
+	};
+};
+
+/* off-board header */
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&pcie_phy {
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+	fsl,clkreq-unsupported;
+	clocks = <&pcie0_refclk>;
+	clock-names = "ref";
+	status = "okay";
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+/* GPS */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+/* USB1 - Type C front panel SINK port J14 */
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+/* USB2 4-port USB3.0 HUB:
+ *  P1 - USBC connector (host only)
+ *  P2 - USB2 test connector
+ *  P3 - miniPCIe full card
+ *  P4 - miniPCIe half card
+ */
+&usb3_phy1 {
+	vbus-supply = <&reg_usb2_vbus>;
+	status = "okay";
+};
+
+&usb3_1 {
+	fsl,permanently-attached;
+	fsl,disable-port-power-control;
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0x40000040 /* GPIOA */
+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x40000040 /* GPIOD */
+			MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04	0x40000040 /* GPIOB */
+			MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05	0x40000040 /* GPIOC */
+			MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26	0x40000106 /* PCI_USBSEL */
+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x40000106 /* PCI_WDIS# */
+		>;
+	};
+
+	pinctrl_gpio_leds: gpioledgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x6	/* LEDG */
+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27	0x6	/* LEDR */
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
+		>;
+	};
+
+	pinctrl_pcie0: pciegrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x106
+		>;
+	};
+
+	pinctrl_pps: ppsgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x106
+		>;
+	};
+
+	pinctrl_reg_usb2_en: regusb2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12	0x6 /* USBHUB_RST# (ext p/u) */
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
+		>;
+	};
+
+	pinctrl_spi2: spi2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x140
+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x140
+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x140
+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-verdin-dahlia.dtsi b/arch/arm/dts/imx8mp-verdin-dahlia.dtsi
deleted file mode 100644
index 4b8f86f630..0000000000
--- a/arch/arm/dts/imx8mp-verdin-dahlia.dtsi
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright 2022 Toradex
- */
-
-/* TODO: Audio Codec */
-
-&backlight {
-	power-supply = <&reg_3p3v>;
-};
-
-/* Verdin SPI_1 */
-&ecspi1 {
-	status = "okay";
-};
-
-/* EEPROM on display adapter boards */
-&eeprom_display_adapter {
-	status = "okay";
-};
-
-/* EEPROM on Verdin Development board */
-&eeprom_carrier_board {
-	status = "okay";
-};
-
-&eqos {
-	status = "okay";
-};
-
-&flexcan1 {
-	status = "okay";
-};
-
-&flexcan2 {
-	status = "okay";
-};
-
-/* Verdin QSPI_1 */
-&flexspi {
-	status = "okay";
-};
-
-/* Current measurement into module VCC */
-&hwmon {
-	status = "okay";
-};
-
-&hwmon_temp {
-	vs-supply = <&reg_1p8v>;
-	status = "okay";
-};
-
-/* Verdin I2C_2_DSI */
-&i2c2 {
-	status = "okay";
-};
-
-&i2c3 {
-	status = "okay";
-};
-
-/* Verdin I2C_1 */
-&i2c4 {
-	status = "okay";
-
-	/* TODO: Audio Codec */
-};
-
-/* TODO: Verdin PCIE_1 */
-
-/* Verdin PWM_1 */
-&pwm1 {
-	status = "okay";
-};
-
-/* Verdin PWM_2 */
-&pwm2 {
-	status = "okay";
-};
-
-/* Verdin PWM_3_DSI */
-&pwm3 {
-	status = "okay";
-};
-
-&reg_usdhc2_vmmc {
-	vin-supply = <&reg_3p3v>;
-};
-
-/* TODO: Verdin I2S_1 */
-
-/* Verdin UART_1 */
-&uart1 {
-	status = "okay";
-};
-
-/* Verdin UART_2 */
-&uart2 {
-	status = "okay";
-};
-
-/* Verdin UART_3, used as the Linux Console */
-&uart3 {
-	status = "okay";
-};
-
-/* Verdin USB_1 */
-&usb3_0 {
-	status = "okay";
-};
-
-&usb3_phy0 {
-	status = "okay";
-};
-
-/* Verdin USB_2 */
-&usb3_1 {
-	status = "okay";
-};
-
-&usb3_phy1 {
-	status = "okay";
-};
-
-/* Verdin SD_1 */
-&usdhc2 {
-	status = "okay";
-};
diff --git a/arch/arm/dts/imx8mp-verdin-dev.dtsi b/arch/arm/dts/imx8mp-verdin-dev.dtsi
index cefabe65b2..bdfdd4c782 100644
--- a/arch/arm/dts/imx8mp-verdin-dev.dtsi
+++ b/arch/arm/dts/imx8mp-verdin-dev.dtsi
@@ -3,8 +3,6 @@
  * Copyright 2022 Toradex
  */
 
-#include "imx8mp-verdin-dahlia.dtsi"
-
 / {
 	/* TODO: Audio Codec */
 
@@ -12,7 +10,7 @@
 		compatible = "regulator-fixed";
 		enable-active-high;
 		gpio = <&gpio_expander_21 4 GPIO_ACTIVE_HIGH>; /* ETH_PWR_EN */
-		off-on-delay = <500000>;
+		off-on-delay-us = <500000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-min-microvolt = <3300000>;
 		regulator-name = "+V3.3_ETH";
@@ -21,16 +19,106 @@
 	};
 };
 
+&backlight {
+	power-supply = <&reg_3p3v>;
+};
+
+/* Verdin SPI_1 */
+&ecspi1 {
+	status = "okay";
+};
+
+/* EEPROM on display adapter boards */
+&eeprom_display_adapter {
+	status = "okay";
+};
+
+/* EEPROM on Verdin Development board */
+&eeprom_carrier_board {
+	status = "okay";
+};
+
+&eqos {
+	status = "okay";
+};
+
 &fec {
 	phy-supply = <&reg_eth2phy>;
 	status = "okay";
 };
 
+&flexcan1 {
+	status = "okay";
+};
+
+&flexcan2 {
+	status = "okay";
+};
+
+/* Verdin QSPI_1 */
+&flexspi {
+	status = "okay";
+};
+
 &gpio_expander_21 {
 	status = "okay";
 	vcc-supply = <&reg_1p8v>;
 };
 
+/* Current measurement into module VCC */
+&hwmon {
+	status = "okay";
+};
+
+&hwmon_temp {
+	vs-supply = <&reg_1p8v>;
+	status = "okay";
+};
+
+/* Verdin I2C_2_DSI */
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+/* Verdin I2C_1 */
+&i2c4 {
+	status = "okay";
+
+	/* TODO: Audio Codec */
+};
+
+/* Verdin PCIE_1 */
+&pcie {
+	status = "okay";
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+/* Verdin PWM_1 */
+&pwm1 {
+	status = "okay";
+};
+
+/* Verdin PWM_2 */
+&pwm2 {
+	status = "okay";
+};
+
+/* Verdin PWM_3_DSI */
+&pwm3 {
+	status = "okay";
+};
+
+&reg_usdhc2_vmmc {
+	vin-supply = <&reg_3p3v>;
+};
+
 /* TODO: Verdin I2C_1 with Audio Codec */
 
 /* Verdin UART_1, connector X50 through RS485 transceiver */
@@ -38,9 +126,40 @@
 	linux,rs485-enabled-at-boot-time;
 	rs485-rts-active-low;
 	rs485-rx-during-tx;
+	status = "okay";
+};
+
+/* Verdin UART_2 */
+&uart2 {
+	status = "okay";
+};
+
+/* Verdin UART_3, used as the Linux Console */
+&uart3 {
+	status = "okay";
+};
+
+/* Verdin USB_1 */
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+/* Verdin USB_2 */
+&usb3_1 {
+	fsl,permanently-attached;
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
 };
 
 /* Limit frequency on dev board due to long traces and bad signal integrity */
 &usdhc2 {
 	max-frequency = <100000000>;
+	status = "okay";
 };
diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
index 9c6c417f7e..0162f9b2da 100644
--- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
@@ -62,6 +62,10 @@
 
 &gpio4 {
 	bootph-pre-ram;
+
+	ctrl-sleep-moci-hog {
+		bootph-pre-ram;
+	};
 };
 
 &gpio5 {
@@ -106,6 +110,10 @@
 	bootph-pre-ram;
 };
 
+&pinctrl_ctrl_sleep_moci {
+	bootph-pre-ram;
+};
+
 &pinctrl_i2c1 {
 	bootph-pre-ram;
 };
diff --git a/arch/arm/dts/imx8mp-verdin-wifi.dtsi b/arch/arm/dts/imx8mp-verdin-wifi.dtsi
index 36289c175e..ef94f9a57e 100644
--- a/arch/arm/dts/imx8mp-verdin-wifi.dtsi
+++ b/arch/arm/dts/imx8mp-verdin-wifi.dtsi
@@ -65,6 +65,11 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_bt_uart>;
 	status = "okay";
+
+	bluetooth {
+		compatible = "mrvl,88w8997";
+		max-speed = <921600>;
+	};
 };
 
 /* On-module Wi-Fi */
diff --git a/arch/arm/dts/imx8mp-verdin.dtsi b/arch/arm/dts/imx8mp-verdin.dtsi
index 7b712d1888..e9e4fcb562 100644
--- a/arch/arm/dts/imx8mp-verdin.dtsi
+++ b/arch/arm/dts/imx8mp-verdin.dtsi
@@ -3,7 +3,8 @@
  * Copyright 2022 Toradex
  */
 
-#include "dt-bindings/pwm/pwm.h"
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/pwm/pwm.h>
 #include "imx8mp.dtsi"
 
 / {
@@ -49,7 +50,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_gpio_keys>;
 
-		button-wakeup {
+		key-wakeup {
 			debounce-interval = <10>;
 			/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
 			gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
@@ -86,7 +87,7 @@
 		compatible = "regulator-fixed";
 		enable-active-high;
 		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
-		off-on-delay = <500000>;
+		off-on-delay-us = <500000>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_reg_eth>;
 		regulator-always-on;
@@ -127,7 +128,7 @@
 		enable-active-high;
 		/* Verdin SD_1_PWR_EN (SODIMM 76) */
 		gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
-		off-on-delay = <100000>;
+		off-on-delay-us = <100000>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
 		regulator-max-microvolt = <3300000>;
@@ -354,16 +355,6 @@
 			  "SODIMM_82",
 			  "SODIMM_70",
 			  "SODIMM_72";
-
-	ctrl-sleep-moci-hog {
-		gpio-hog;
-		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
-		gpios = <29 GPIO_ACTIVE_HIGH>;
-		line-name = "CTRL_SLEEP_MOCI#";
-		output-high;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
-	};
 };
 
 &gpio3 {
@@ -432,6 +423,16 @@
 			  "SODIMM_256",
 			  "SODIMM_48",
 			  "SODIMM_44";
+
+	ctrl-sleep-moci-hog {
+		gpio-hog;
+		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+		gpios = <29 GPIO_ACTIVE_HIGH>;
+		line-name = "CTRL_SLEEP_MOCI#";
+		output-high;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+	};
 };
 
 /* On-module I2C */
@@ -452,7 +453,6 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pmic>;
 		reg = <0x25>;
-		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 
 		/*
 		 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
@@ -678,8 +678,8 @@
 		status = "disabled";
 	};
 
-	lvds_ti_sn65dsi83: bridge@2c {
-		compatible = "ti,sn65dsi83";
+	lvds_ti_sn65dsi84: bridge@2c {
+		compatible = "ti,sn65dsi84";
 		/* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
 		/* Verdin GPIO_10_DSI (SODIMM 21) */
 		enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
@@ -712,7 +712,7 @@
 		compatible = "atmel,maxtouch";
 		/*
 		 * Verdin GPIO_9_DSI
-		 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
+		 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
 		 */
 		interrupt-parent = <&gpio4>;
 		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
@@ -748,7 +748,20 @@
 	};
 };
 
-/* TODO: Verdin PCIE_1 */
+/* Verdin PCIE_1 */
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	/* PCIE_1_RESET# (SODIMM 244) */
+	reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
+};
+
+&pcie_phy {
+	clocks = <&hsio_blk_ctrl>;
+	clock-names = "ref";
+	fsl,clkreq-unsupported;
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+};
 
 /* Verdin PWM_1 */
 &pwm1 {
@@ -806,28 +819,45 @@
 };
 
 /* Verdin USB_1 */
-&usb3_phy0 {
-	vbus-supply = <&reg_usb1_vbus>;
+&usb3_0 {
+	fsl,disable-port-power-control;
+	fsl,over-current-active-low;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_1_oc_n>;
 };
 
 &usb_dwc3_0 {
+	/* dual role only, not full featured OTG */
 	adp-disable;
 	dr_mode = "otg";
 	hnp-disable;
 	maximum-speed = "high-speed";
-	over-current-active-low;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usb_1_id>;
+	role-switch-default-mode = "peripheral";
 	srp-disable;
+	usb-role-switch;
+
+	connector {
+		compatible = "gpio-usb-b-connector", "usb-b-connector";
+		id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+		label = "Type-C";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb_1_id>;
+		self-powered;
+		type = "micro";
+		vbus-supply = <&reg_usb1_vbus>;
+	};
 };
 
 /* Verdin USB_2 */
+&usb3_1 {
+	fsl,disable-port-power-control;
+};
+
 &usb3_phy1 {
 	vbus-supply = <&reg_usb2_vbus>;
 };
 
 &usb_dwc3_1 {
-	disable-over-current;
 	dr_mode = "host";
 };
 
@@ -1045,7 +1075,6 @@
 
 	pinctrl_gpio_hog3: gpiohog3grp {
 		fsl,pins =
-			<MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x1c4>,	/* SODIMM 157 */
 			/* CSI_1_MCLK */
 			<MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x1c4>;	/* SODIMM 91 */
 	};
@@ -1220,7 +1249,7 @@
 
 	pinctrl_usb1_vbus: usb1vbusgrp {
 		fsl,pins =
-			<MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR		0x19>;	/* SODIMM 155 */
+			<MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x106>;	/* SODIMM 155 */
 	};
 
 	/* USB_1_ID */
@@ -1229,9 +1258,15 @@
 			<MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x1c4>;	/* SODIMM 161 */
 	};
 
+	/* USB_1_OC# */
+	pinctrl_usb_1_oc_n: usb1ocngrp {
+		fsl,pins =
+			<MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC		0x1c4>;	/* SODIMM 157 */
+	};
+
 	pinctrl_usb2_vbus: usb2vbusgrp {
 		fsl,pins =
-			<MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR		0x19>;	/* SODIMM 185 */
+			<MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x106>;	/* SODIMM 185 */
 	};
 
 	/* On-module Wi-Fi */
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index bb916a0948..428c60462e 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -123,6 +123,7 @@
 
 		A53_L2: l2-cache0 {
 			compatible = "cache";
+			cache-unified;
 			cache-level = <2>;
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
@@ -379,6 +380,8 @@
 				compatible = "fsl,imx8mp-tmu";
 				reg = <0x30260000 0x10000>;
 				clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
+				nvmem-cells = <&tmu_calib>;
+				nvmem-cell-names = "calib";
 				#thermal-sensor-cells = <1>;
 			};
 
@@ -406,12 +409,36 @@
 				status = "disabled";
 			};
 
+			gpt1: timer@302d0000 {
+				compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
+				reg = <0x302d0000 0x10000>;
+				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>;
+				clock-names = "ipg", "per";
+			};
+
+			gpt2: timer@302e0000 {
+				compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
+				reg = <0x302e0000 0x10000>;
+				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>;
+				clock-names = "ipg", "per";
+			};
+
+			gpt3: timer@302f0000 {
+				compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
+				reg = <0x302f0000 0x10000>;
+				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>;
+				clock-names = "ipg", "per";
+			};
+
 			iomuxc: pinctrl@30330000 {
 				compatible = "fsl,imx8mp-iomuxc";
 				reg = <0x30330000 0x10000>;
 			};
 
-			gpr: iomuxc-gpr@30340000 {
+			gpr: syscon@30340000 {
 				compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
 				reg = <0x30340000 0x10000>;
 			};
@@ -424,27 +451,44 @@
 				#address-cells = <1>;
 				#size-cells = <1>;
 
-				imx8mp_uid: unique-id@420 {
+				/*
+				 * The register address below maps to the MX8M
+				 * Fusemap Description Table entries this way.
+				 * Assuming
+				 *   reg = <ADDR SIZE>;
+				 * then
+				 *   Fuse Address = (ADDR * 4) + 0x400
+				 * Note that if SIZE is greater than 4, then
+				 * each subsequent fuse is located at offset
+				 * +0x10 in Fusemap Description Table (e.g.
+				 * reg = <0x8 0x8> describes fuses 0x420 and
+				 * 0x430).
+				 */
+				imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
 					reg = <0x8 0x8>;
 				};
 
-				cpu_speed_grade: speed-grade@10 {
+				cpu_speed_grade: speed-grade@10 { /* 0x440 */
 					reg = <0x10 4>;
 				};
 
-				eth_mac1: mac-address@90 {
+				eth_mac1: mac-address@90 { /* 0x640 */
 					reg = <0x90 6>;
 				};
 
-				eth_mac2: mac-address@96 {
+				eth_mac2: mac-address@96 { /* 0x658 */
 					reg = <0x96 6>;
 				};
+
+				tmu_calib: calib@264 { /* 0xd90-0xdc0 */
+					reg = <0x264 0x10>;
+				};
 			};
 
-			anatop: anatop@30360000 {
-				compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
-					     "syscon";
+			anatop: clock-controller@30360000 {
+				compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
 				reg = <0x30360000 0x10000>;
+				#clock-cells = <1>;
 			};
 
 			snvs: snvs@30370000 {
@@ -523,6 +567,7 @@
 				compatible = "fsl,imx8mp-gpc";
 				reg = <0x303a0000 0x1000>;
 				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-controller;
 				#interrupt-cells = <3>;
 
@@ -589,7 +634,7 @@
 						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
 					};
 
-					pgc_hsiomix: power-domains@17 {
+					pgc_hsiomix: power-domain@17 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
 						clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
@@ -631,6 +676,14 @@
 						reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
 						clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
 					};
+
+					pgc_mlmix: power-domain@24 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
+						clocks = <&clk IMX8MP_CLK_ML_AXI>,
+							 <&clk IMX8MP_CLK_ML_AHB>,
+							 <&clk IMX8MP_CLK_NPU_ROOT>;
+					};
 				};
 			};
 		};
@@ -693,6 +746,30 @@
 				clocks = <&osc_24m>;
 				clock-names = "per";
 			};
+
+			gpt6: timer@306e0000 {
+				compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
+				reg = <0x306e0000 0x10000>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>;
+				clock-names = "ipg", "per";
+			};
+
+			gpt5: timer@306f0000 {
+				compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
+				reg = <0x306f0000 0x10000>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>;
+				clock-names = "ipg", "per";
+			};
+
+			gpt4: timer@30700000 {
+				compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
+				reg = <0x30700000 0x10000>;
+				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>;
+				clock-names = "ipg", "per";
+			};
 		};
 
 		aips3: bus@30800000 {
@@ -702,112 +779,129 @@
 			#size-cells = <1>;
 			ranges;
 
-			ecspi1: spi@30820000 {
+			spba-bus@30800000 {
+				compatible = "fsl,spba-bus", "simple-bus";
+				reg = <0x30800000 0x100000>;
 				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
-				reg = <0x30820000 0x10000>;
-				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
-					 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
-				clock-names = "ipg", "per";
-				dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
-				dma-names = "rx", "tx";
-				status = "disabled";
-			};
+				#size-cells = <1>;
+				ranges;
 
-			ecspi2: spi@30830000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
-				reg = <0x30830000 0x10000>;
-				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
-					 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
-				clock-names = "ipg", "per";
-				dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
-				dma-names = "rx", "tx";
-				status = "disabled";
-			};
+				ecspi1: spi@30820000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
+					reg = <0x30820000 0x10000>;
+					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
+						 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
+					clock-names = "ipg", "per";
+					assigned-clock-rates = <80000000>;
+					assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
+					assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+					dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
 
-			ecspi3: spi@30840000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
-				reg = <0x30840000 0x10000>;
-				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
-					 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
-				clock-names = "ipg", "per";
-				dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
-				dma-names = "rx", "tx";
-				status = "disabled";
-			};
+				ecspi2: spi@30830000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
+					reg = <0x30830000 0x10000>;
+					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
+						 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
+					clock-names = "ipg", "per";
+					assigned-clock-rates = <80000000>;
+					assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
+					assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+					dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
 
-			uart1: serial@30860000 {
-				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
-				reg = <0x30860000 0x10000>;
-				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
-					 <&clk IMX8MP_CLK_UART1_ROOT>;
-				clock-names = "ipg", "per";
-				dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
-				dma-names = "rx", "tx";
-				status = "disabled";
-			};
+				ecspi3: spi@30840000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
+					reg = <0x30840000 0x10000>;
+					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
+						 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
+					clock-names = "ipg", "per";
+					assigned-clock-rates = <80000000>;
+					assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
+					assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+					dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
 
-			uart3: serial@30880000 {
-				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
-				reg = <0x30880000 0x10000>;
-				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
-					 <&clk IMX8MP_CLK_UART3_ROOT>;
-				clock-names = "ipg", "per";
-				dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
-				dma-names = "rx", "tx";
-				status = "disabled";
-			};
+				uart1: serial@30860000 {
+					compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
+					reg = <0x30860000 0x10000>;
+					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
+						 <&clk IMX8MP_CLK_UART1_ROOT>;
+					clock-names = "ipg", "per";
+					dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
 
-			uart2: serial@30890000 {
-				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
-				reg = <0x30890000 0x10000>;
-				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
-					 <&clk IMX8MP_CLK_UART2_ROOT>;
-				clock-names = "ipg", "per";
-				dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
-				dma-names = "rx", "tx";
-				status = "disabled";
-			};
+				uart3: serial@30880000 {
+					compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
+					reg = <0x30880000 0x10000>;
+					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
+						 <&clk IMX8MP_CLK_UART3_ROOT>;
+					clock-names = "ipg", "per";
+					dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
 
-			flexcan1: can@308c0000 {
-				compatible = "fsl,imx8mp-flexcan";
-				reg = <0x308c0000 0x10000>;
-				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
-					 <&clk IMX8MP_CLK_CAN1_ROOT>;
-				clock-names = "ipg", "per";
-				assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
-				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
-				assigned-clock-rates = <40000000>;
-				fsl,clk-source = /bits/ 8 <0>;
-				fsl,stop-mode = <&gpr 0x10 4>;
-				status = "disabled";
-			};
+				uart2: serial@30890000 {
+					compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
+					reg = <0x30890000 0x10000>;
+					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
+						 <&clk IMX8MP_CLK_UART2_ROOT>;
+					clock-names = "ipg", "per";
+					dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
 
-			flexcan2: can@308d0000 {
-				compatible = "fsl,imx8mp-flexcan";
-				reg = <0x308d0000 0x10000>;
-				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
-					 <&clk IMX8MP_CLK_CAN2_ROOT>;
-				clock-names = "ipg", "per";
-				assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
-				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
-				assigned-clock-rates = <40000000>;
-				fsl,clk-source = /bits/ 8 <0>;
-				fsl,stop-mode = <&gpr 0x10 5>;
-				status = "disabled";
+				flexcan1: can@308c0000 {
+					compatible = "fsl,imx8mp-flexcan";
+					reg = <0x308c0000 0x10000>;
+					interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
+						 <&clk IMX8MP_CLK_CAN1_ROOT>;
+					clock-names = "ipg", "per";
+					assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
+					assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
+					assigned-clock-rates = <40000000>;
+					fsl,clk-source = /bits/ 8 <0>;
+					fsl,stop-mode = <&gpr 0x10 4>;
+					status = "disabled";
+				};
+
+				flexcan2: can@308d0000 {
+					compatible = "fsl,imx8mp-flexcan";
+					reg = <0x308d0000 0x10000>;
+					interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
+						 <&clk IMX8MP_CLK_CAN2_ROOT>;
+					clock-names = "ipg", "per";
+					assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
+					assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
+					assigned-clock-rates = <40000000>;
+					fsl,clk-source = /bits/ 8 <0>;
+					fsl,stop-mode = <&gpr 0x10 5>;
+					status = "disabled";
+				};
 			};
 
 			crypto: crypto@30900000 {
@@ -1063,11 +1157,11 @@
 			noc_opp_table: opp-table {
 				compatible = "operating-points-v2";
 
-				opp-200M {
+				opp-200000000 {
 					opp-hz = /bits/ 64 <200000000>;
 				};
 
-				opp-1000M {
+				opp-1000000000 {
 					opp-hz = /bits/ 64 <1000000000>;
 				};
 			};
@@ -1080,10 +1174,78 @@
 			#size-cells = <1>;
 			ranges;
 
+			mipi_dsi: dsi@32e60000 {
+				compatible = "fsl,imx8mp-mipi-dsim";
+				reg = <0x32e60000 0x400>;
+				clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
+				clock-names = "bus_clk", "sclk_mipi";
+				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
+						  <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+							 <&clk IMX8MP_CLK_24M>;
+				assigned-clock-rates = <200000000>, <24000000>;
+				samsung,pll-clock-frequency = <24000000>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						dsim_from_lcdif1: endpoint {
+							remote-endpoint = <&lcdif1_to_dsim>;
+						};
+					};
+				};
+			};
+
+			lcdif1: display-controller@32e80000 {
+				compatible = "fsl,imx8mp-lcdif";
+				reg = <0x32e80000 0x10000>;
+				clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
+				clock-names = "pix", "axi", "disp_axi";
+				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
+				status = "disabled";
+
+				port {
+					lcdif1_to_dsim: endpoint {
+						remote-endpoint = <&dsim_from_lcdif1>;
+					};
+				};
+			};
+
+			lcdif2: display-controller@32e90000 {
+				compatible = "fsl,imx8mp-lcdif";
+				reg = <0x32e90000 0x10000>;
+				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
+				clock-names = "pix", "axi", "disp_axi";
+				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
+				status = "disabled";
+
+				port {
+					lcdif2_to_ldb: endpoint {
+						remote-endpoint = <&ldb_from_lcdif2>;
+					};
+				};
+			};
+
 			media_blk_ctrl: blk-ctrl@32ec0000 {
 				compatible = "fsl,imx8mp-media-blk-ctrl",
 					     "syscon";
 				reg = <0x32ec0000 0x10000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
 				power-domains = <&pgc_mediamix>,
 						<&pgc_mipi_phy1>,
 						<&pgc_mipi_phy1>,
@@ -1122,12 +1284,55 @@
 					      "disp1", "disp2", "isp", "phy";
 
 				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
-						  <&clk IMX8MP_CLK_MEDIA_APB>;
+						  <&clk IMX8MP_CLK_MEDIA_APB>,
+						  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
+						  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
+						  <&clk IMX8MP_VIDEO_PLL1>;
 				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
-							 <&clk IMX8MP_SYS_PLL1_800M>;
-				assigned-clock-rates = <500000000>, <200000000>;
-
+							 <&clk IMX8MP_SYS_PLL1_800M>,
+							 <&clk IMX8MP_VIDEO_PLL1_OUT>,
+							 <&clk IMX8MP_VIDEO_PLL1_OUT>;
+				assigned-clock-rates = <500000000>, <200000000>,
+						       <0>, <0>, <1039500000>;
 				#power-domain-cells = <1>;
+
+				lvds_bridge: bridge@5c {
+					compatible = "fsl,imx8mp-ldb";
+					reg = <0x5c 0x4>, <0x128 0x4>;
+					reg-names = "ldb", "lvds";
+					clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
+					clock-names = "ldb";
+					assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
+					assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
+					status = "disabled";
+
+					ports {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						port@0 {
+							reg = <0>;
+
+							ldb_from_lcdif2: endpoint {
+								remote-endpoint = <&lcdif2_to_ldb>;
+							};
+						};
+
+						port@1 {
+							reg = <1>;
+
+							ldb_lvds_ch0: endpoint {
+							};
+						};
+
+						port@2 {
+							reg = <2>;
+
+							ldb_lvds_ch1: endpoint {
+							};
+						};
+					};
+				};
 			};
 
 			pcie_phy: pcie-phy@32f00000 {
@@ -1158,6 +1363,7 @@
 						<&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
 				interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
 				#power-domain-cells = <1>;
+				#clock-cells = <0>;
 			};
 		};
 
@@ -1165,6 +1371,13 @@
 			compatible = "fsl,imx8mp-pcie";
 			reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
 			reg-names = "dbi", "config";
+			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+				 <&clk IMX8MP_CLK_HSIO_AXI>,
+				 <&clk IMX8MP_CLK_PCIE_ROOT>;
+			clock-names = "pcie", "pcie_bus", "pcie_aux";
+			assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+			assigned-clock-rates = <10000000>;
+			assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -1192,6 +1405,32 @@
 			status = "disabled";
 		};
 
+		pcie_ep: pcie-ep@33800000 {
+			compatible = "fsl,imx8mp-pcie-ep";
+			reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
+			reg-names = "dbi", "addr_space";
+			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+				 <&clk IMX8MP_CLK_HSIO_AXI>,
+				 <&clk IMX8MP_CLK_PCIE_ROOT>;
+			clock-names = "pcie", "pcie_bus", "pcie_aux";
+			assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+			assigned-clock-rates = <10000000>;
+			assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
+			num-lanes = <1>;
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+			interrupt-names = "dma";
+			fsl,max-link-speed = <3>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
+			resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
+				 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
+			reset-names = "apps", "turnoff";
+			phys = <&pcie_phy>;
+			phy-names = "pcie-phy";
+			num-ib-windows = <4>;
+			num-ob-windows = <4>;
+			status = "disabled";
+		};
+
 		gpu3d: gpu@38000000 {
 			compatible = "vivante,gc";
 			reg = <0x38000000 0x8000>;
@@ -1223,6 +1462,28 @@
 			power-domains = <&pgc_gpu2d>;
 		};
 
+		vpu_g1: video-codec@38300000 {
+			compatible = "nxp,imx8mm-vpu-g1";
+			reg = <0x38300000 0x10000>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
+			assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
+			assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
+			assigned-clock-rates = <600000000>;
+			power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
+		};
+
+		vpu_g2: video-codec@38310000 {
+			compatible = "nxp,imx8mq-vpu-g2";
+			reg = <0x38310000 0x10000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
+			assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
+			assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+			assigned-clock-rates = <500000000>;
+			power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
+		};
+
 		vpumix_blk_ctrl: blk-ctrl@38330000 {
 			compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
 			reg = <0x38330000 0x100>;
@@ -1234,6 +1495,9 @@
 				 <&clk IMX8MP_CLK_VPU_G2_ROOT>,
 				 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
 			clock-names = "g1", "g2", "vc8000e";
+			assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
+			assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
+			assigned-clock-rates = <600000000>, <600000000>;
 			interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
 					<&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
 					<&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
@@ -1279,7 +1543,7 @@
 			reg = <0x32f10100 0x8>,
 			      <0x381f0000 0x20>;
 			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
-				 <&clk IMX8MP_CLK_USB_ROOT>;
+				 <&clk IMX8MP_CLK_USB_SUSP>;
 			clock-names = "hsio", "suspend";
 			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
@@ -1292,9 +1556,9 @@
 			usb_dwc3_0: usb@38100000 {
 				compatible = "snps,dwc3";
 				reg = <0x38100000 0x10000>;
-				clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+				clocks = <&clk IMX8MP_CLK_USB_ROOT>,
 					 <&clk IMX8MP_CLK_USB_CORE_REF>,
-					 <&clk IMX8MP_CLK_USB_ROOT>;
+					 <&clk IMX8MP_CLK_USB_SUSP>;
 				clock-names = "bus_early", "ref", "suspend";
 				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 				phys = <&usb3_phy0>, <&usb3_phy0>;
@@ -1321,7 +1585,7 @@
 			reg = <0x32f10108 0x8>,
 			      <0x382f0000 0x20>;
 			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
-				 <&clk IMX8MP_CLK_USB_ROOT>;
+				 <&clk IMX8MP_CLK_USB_SUSP>;
 			clock-names = "hsio", "suspend";
 			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
@@ -1334,9 +1598,9 @@
 			usb_dwc3_1: usb@38200000 {
 				compatible = "snps,dwc3";
 				reg = <0x38200000 0x10000>;
-				clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+				clocks = <&clk IMX8MP_CLK_USB_ROOT>,
 					 <&clk IMX8MP_CLK_USB_CORE_REF>,
-					 <&clk IMX8MP_CLK_USB_ROOT>;
+					 <&clk IMX8MP_CLK_USB_SUSP>;
 				clock-names = "bus_early", "ref", "suspend";
 				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 				phys = <&usb3_phy1>, <&usb3_phy1>;
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index b3fef862b4..90b2274754 100644
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -97,7 +97,9 @@
 
 		fit {
 			description = "Configuration to load ATF before U-Boot";
+#ifndef CONFIG_IMX_HAB
 			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+#endif
 			#address-cells = <1>;
 
 			images {
diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi
index 4a42f1b2e3..2488e3a537 100644
--- a/arch/arm/dts/k3-am62-main.dtsi
+++ b/arch/arm/dts/k3-am62-main.dtsi
@@ -54,6 +54,12 @@
 			reg = <0x4044 0x8>;
 			#phy-cells = <1>;
 		};
+
+		epwm_tbclk: clock@4130 {
+			compatible = "ti,am62-epwm-tbclk", "syscon";
+			reg = <0x4130 0x4>;
+			#clock-cells = <1>;
+		};
 	};
 
 	dmss: bus@48000000 {
@@ -144,8 +150,8 @@
 		compatible = "ti,k2g-sci";
 		ti,host-id = <12>;
 		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 12>,
-			<&secure_proxy_main 13>;
+		mboxes = <&secure_proxy_main 12>,
+			 <&secure_proxy_main 13>;
 		reg-names = "debug_messages";
 		reg = <0x00 0x44043000 0x00 0xfe0>;
 
@@ -178,6 +184,21 @@
 		dma-names = "tx", "rx1", "rx2";
 	};
 
+	secure_proxy_sa3: mailbox@43600000 {
+		compatible = "ti,am654-secure-proxy";
+		#mbox-cells = <1>;
+		reg-names = "target_data", "rt", "scfg";
+		reg = <0x00 0x43600000 0x00 0x10000>,
+		      <0x00 0x44880000 0x00 0x20000>,
+		      <0x00 0x44860000 0x00 0x20000>;
+		/*
+		 * Marked Disabled:
+		 * Node is incomplete as it is meant for bootloaders and
+		 * firmware on non-MPU processors
+		 */
+		status = "disabled";
+	};
+
 	main_pmx0: pinctrl@f4000 {
 		compatible = "pinctrl-single";
 		reg = <0x00 0xf4000 0x00 0x2ac>;
@@ -186,6 +207,108 @@
 		pinctrl-single,function-mask = <0xffffffff>;
 	};
 
+	main_esm: esm@420000 {
+		compatible = "ti,j721e-esm";
+		reg = <0x00 0x420000 0x00 0x1000>;
+		ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
+	};
+
+	main_timer0: timer@2400000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2400000 0x00 0x400>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 36 2>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 36 2>;
+		assigned-clock-parents = <&k3_clks 36 3>;
+		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+	};
+
+	main_timer1: timer@2410000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2410000 0x00 0x400>;
+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 37 2>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 37 2>;
+		assigned-clock-parents = <&k3_clks 37 3>;
+		power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+	};
+
+	main_timer2: timer@2420000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2420000 0x00 0x400>;
+		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 38 2>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 38 2>;
+		assigned-clock-parents = <&k3_clks 38 3>;
+		power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+	};
+
+	main_timer3: timer@2430000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2430000 0x00 0x400>;
+		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 39 2>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 39 2>;
+		assigned-clock-parents = <&k3_clks 39 3>;
+		power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+	};
+
+	main_timer4: timer@2440000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2440000 0x00 0x400>;
+		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 40 2>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 40 2>;
+		assigned-clock-parents = <&k3_clks 40 3>;
+		power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+	};
+
+	main_timer5: timer@2450000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2450000 0x00 0x400>;
+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 41 2>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 41 2>;
+		assigned-clock-parents = <&k3_clks 41 3>;
+		power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+	};
+
+	main_timer6: timer@2460000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2460000 0x00 0x400>;
+		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 42 2>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 42 2>;
+		assigned-clock-parents = <&k3_clks 42 3>;
+		power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+	};
+
+	main_timer7: timer@2470000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2470000 0x00 0x400>;
+		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 43 2>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 43 2>;
+		assigned-clock-parents = <&k3_clks 43 3>;
+		power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+	};
+
 	main_uart0: serial@2800000 {
 		compatible = "ti,am64-uart", "ti,am654-uart";
 		reg = <0x00 0x02800000 0x00 0x100>;
@@ -193,6 +316,7 @@
 		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 146 0>;
 		clock-names = "fclk";
+		status = "disabled";
 	};
 
 	main_uart1: serial@2810000 {
@@ -202,6 +326,7 @@
 		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 152 0>;
 		clock-names = "fclk";
+		status = "disabled";
 	};
 
 	main_uart2: serial@2820000 {
@@ -211,6 +336,7 @@
 		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 153 0>;
 		clock-names = "fclk";
+		status = "disabled";
 	};
 
 	main_uart3: serial@2830000 {
@@ -220,6 +346,7 @@
 		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 154 0>;
 		clock-names = "fclk";
+		status = "disabled";
 	};
 
 	main_uart4: serial@2840000 {
@@ -229,6 +356,7 @@
 		power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 155 0>;
 		clock-names = "fclk";
+		status = "disabled";
 	};
 
 	main_uart5: serial@2850000 {
@@ -238,6 +366,7 @@
 		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 156 0>;
 		clock-names = "fclk";
+		status = "disabled";
 	};
 
 	main_uart6: serial@2860000 {
@@ -247,6 +376,7 @@
 		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 158 0>;
 		clock-names = "fclk";
+		status = "disabled";
 	};
 
 	main_i2c0: i2c@20000000 {
@@ -258,6 +388,7 @@
 		power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 102 2>;
 		clock-names = "fck";
+		status = "disabled";
 	};
 
 	main_i2c1: i2c@20010000 {
@@ -269,6 +400,7 @@
 		power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 103 2>;
 		clock-names = "fck";
+		status = "disabled";
 	};
 
 	main_i2c2: i2c@20020000 {
@@ -280,6 +412,7 @@
 		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 104 2>;
 		clock-names = "fck";
+		status = "disabled";
 	};
 
 	main_i2c3: i2c@20030000 {
@@ -291,6 +424,7 @@
 		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 105 2>;
 		clock-names = "fck";
+		status = "disabled";
 	};
 
 	main_spi0: spi@20100000 {
@@ -300,7 +434,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 172 0>;
+		clocks = <&k3_clks 141 0>;
+		status = "disabled";
 	};
 
 	main_spi1: spi@20110000 {
@@ -310,7 +445,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 173 0>;
+		clocks = <&k3_clks 142 0>;
+		status = "disabled";
 	};
 
 	main_spi2: spi@20120000 {
@@ -320,7 +456,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 174 0>;
+		clocks = <&k3_clks 143 0>;
+		status = "disabled";
 	};
 
 	main_gpio_intr: interrupt-controller@a00000 {
@@ -345,7 +482,7 @@
 			     <193>, <194>, <195>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
-		ti,ngpio = <87>;
+		ti,ngpio = <92>;
 		ti,davinci-gpio-unbanked = <0>;
 		power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 77 0>;
@@ -362,7 +499,7 @@
 			     <183>, <184>, <185>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
-		ti,ngpio = <88>;
+		ti,ngpio = <52>;
 		ti,davinci-gpio-unbanked = <0>;
 		power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 78 0>;
@@ -385,8 +522,11 @@
 		ti,clkbuf-sel = <0x7>;
 		ti,otap-del-sel-legacy = <0x0>;
 		ti,otap-del-sel-mmc-hs = <0x0>;
-		ti,otap-del-sel-ddr52 = <0x9>;
-		ti,otap-del-sel-hs200 = <0x6>;
+		ti,otap-del-sel-ddr52 = <0x5>;
+		ti,otap-del-sel-hs200 = <0x5>;
+		ti,itap-del-sel-legacy = <0xa>;
+		ti,itap-del-sel-mmc-hs = <0x1>;
+		status = "disabled";
 	};
 
 	sdhci1: mmc@fa00000 {
@@ -397,19 +537,20 @@
 		clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
 		clock-names = "clk_ahb", "clk_xin";
 		ti,trm-icp = <0x2>;
-		ti,otap-del-sel-legacy = <0x0>;
+		ti,otap-del-sel-legacy = <0x8>;
 		ti,otap-del-sel-sd-hs = <0x0>;
-		ti,otap-del-sel-sdr12 = <0xf>;
-		ti,otap-del-sel-sdr25 = <0xf>;
-		ti,otap-del-sel-sdr50 = <0xc>;
-		ti,otap-del-sel-sdr104 = <0x6>;
-		ti,otap-del-sel-ddr50 = <0x9>;
-		ti,itap-del-sel-legacy = <0x0>;
-		ti,itap-del-sel-sd-hs = <0x0>;
-		ti,itap-del-sel-sdr12 = <0x0>;
-		ti,itap-del-sel-sdr25 = <0x0>;
+		ti,otap-del-sel-sdr12 = <0x0>;
+		ti,otap-del-sel-sdr25 = <0x0>;
+		ti,otap-del-sel-sdr50 = <0x8>;
+		ti,otap-del-sel-sdr104 = <0x7>;
+		ti,otap-del-sel-ddr50 = <0x4>;
+		ti,itap-del-sel-legacy = <0xa>;
+		ti,itap-del-sel-sd-hs = <0x1>;
+		ti,itap-del-sel-sdr12 = <0xa>;
+		ti,itap-del-sel-sdr25 = <0x1>;
 		ti,clkbuf-sel = <0x7>;
 		bus-width = <4>;
+		status = "disabled";
 	};
 
 	sdhci2: mmc@fa20000 {
@@ -420,18 +561,65 @@
 		clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
 		clock-names = "clk_ahb", "clk_xin";
 		ti,trm-icp = <0x2>;
-		ti,otap-del-sel-legacy = <0x0>;
+		ti,otap-del-sel-legacy = <0x8>;
 		ti,otap-del-sel-sd-hs = <0x0>;
-		ti,otap-del-sel-sdr12 = <0xf>;
-		ti,otap-del-sel-sdr25 = <0xf>;
-		ti,otap-del-sel-sdr50 = <0xc>;
-		ti,otap-del-sel-sdr104 = <0x6>;
-		ti,otap-del-sel-ddr50 = <0x9>;
-		ti,itap-del-sel-legacy = <0x0>;
-		ti,itap-del-sel-sd-hs = <0x0>;
-		ti,itap-del-sel-sdr12 = <0x0>;
-		ti,itap-del-sel-sdr25 = <0x0>;
+		ti,otap-del-sel-sdr12 = <0x0>;
+		ti,otap-del-sel-sdr25 = <0x0>;
+		ti,otap-del-sel-sdr50 = <0x8>;
+		ti,otap-del-sel-sdr104 = <0x7>;
+		ti,otap-del-sel-ddr50 = <0x8>;
+		ti,itap-del-sel-legacy = <0xa>;
+		ti,itap-del-sel-sd-hs = <0xa>;
+		ti,itap-del-sel-sdr12 = <0xa>;
+		ti,itap-del-sel-sdr25 = <0x1>;
 		ti,clkbuf-sel = <0x7>;
+		status = "disabled";
+	};
+
+	usbss0: dwc3-usb@f900000 {
+		compatible = "ti,am62-usb";
+		reg = <0x00 0x0f900000 0x00 0x800>;
+		clocks = <&k3_clks 161 3>;
+		clock-names = "ref";
+		ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
+		ranges;
+		status = "disabled";
+
+		usb0: usb@31000000 {
+			compatible = "snps,dwc3";
+			reg =<0x00 0x31000000 0x00 0x50000>;
+			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+			interrupt-names = "host", "peripheral";
+			maximum-speed = "high-speed";
+			dr_mode = "otg";
+		};
+	};
+
+	usbss1: dwc3-usb@f910000 {
+		compatible = "ti,am62-usb";
+		reg = <0x00 0x0f910000 0x00 0x800>;
+		clocks = <&k3_clks 162 3>;
+		clock-names = "ref";
+		ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+		ranges;
+		status = "disabled";
+
+		usb1: usb@31100000 {
+			compatible = "snps,dwc3";
+			reg =<0x00 0x31100000 0x00 0x50000>;
+			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+			interrupt-names = "host", "peripheral";
+			maximum-speed = "high-speed";
+			dr_mode = "otg";
+		};
 	};
 
 	fss: bus@fc00000 {
@@ -456,6 +644,7 @@
 			power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			status = "disabled";
 		};
 	};
 
@@ -514,12 +703,13 @@
 			clocks = <&k3_clks 13 0>;
 			clock-names = "fck";
 			bus_freq = <1000000>;
+			status = "disabled";
 		};
 
 		cpts@3d000 {
 			compatible = "ti,j721e-cpts";
 			reg = <0x00 0x3d000 0x00 0x400>;
-			clocks = <&k3_clks 13 1>;
+			clocks = <&k3_clks 13 3>;
 			clock-names = "cpts";
 			interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "cpts";
@@ -551,6 +741,7 @@
 		power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 51 0>;
 		clock-names = "fck";
+		status = "disabled";
 	};
 
 	ecap1: pwm@23110000 {
@@ -560,6 +751,7 @@
 		power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 52 0>;
 		clock-names = "fck";
+		status = "disabled";
 	};
 
 	ecap2: pwm@23120000 {
@@ -569,6 +761,7 @@
 		power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 53 0>;
 		clock-names = "fck";
+		status = "disabled";
 	};
 
 	main_mcan0: can@20701000 {
@@ -583,5 +776,141 @@
 			     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "int0", "int1";
 		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+		status = "disabled";
+	};
+
+	main_rti0: watchdog@e000000 {
+		compatible = "ti,j7-rti-wdt";
+		reg = <0x00 0x0e000000 0x00 0x100>;
+		clocks = <&k3_clks 125 0>;
+		power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
+		assigned-clocks = <&k3_clks 125 0>;
+		assigned-clock-parents = <&k3_clks 125 2>;
+	};
+
+	main_rti1: watchdog@e010000 {
+		compatible = "ti,j7-rti-wdt";
+		reg = <0x00 0x0e010000 0x00 0x100>;
+		clocks = <&k3_clks 126 0>;
+		power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
+		assigned-clocks = <&k3_clks 126 0>;
+		assigned-clock-parents = <&k3_clks 126 2>;
+	};
+
+	main_rti2: watchdog@e020000 {
+		compatible = "ti,j7-rti-wdt";
+		reg = <0x00 0x0e020000 0x00 0x100>;
+		clocks = <&k3_clks 127 0>;
+		power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
+		assigned-clocks = <&k3_clks 127 0>;
+		assigned-clock-parents = <&k3_clks 127 2>;
+	};
+
+	main_rti3: watchdog@e030000 {
+		compatible = "ti,j7-rti-wdt";
+		reg = <0x00 0x0e030000 0x00 0x100>;
+		clocks = <&k3_clks 128 0>;
+		power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
+		assigned-clocks = <&k3_clks 128 0>;
+		assigned-clock-parents = <&k3_clks 128 2>;
+	};
+
+	main_rti15: watchdog@e0f0000 {
+		compatible = "ti,j7-rti-wdt";
+		reg = <0x00 0x0e0f0000 0x00 0x100>;
+		clocks = <&k3_clks 130 0>;
+		power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
+		assigned-clocks = <&k3_clks 130 0>;
+		assigned-clock-parents = <&k3_clks 130 2>;
+	};
+
+	epwm0: pwm@23000000 {
+		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+		#pwm-cells = <3>;
+		reg = <0x00 0x23000000 0x00 0x100>;
+		power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
+		clock-names = "tbclk", "fck";
+		status = "disabled";
+	};
+
+	epwm1: pwm@23010000 {
+		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+		#pwm-cells = <3>;
+		reg = <0x00 0x23010000 0x00 0x100>;
+		power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
+		clock-names = "tbclk", "fck";
+		status = "disabled";
+	};
+
+	epwm2: pwm@23020000 {
+		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+		#pwm-cells = <3>;
+		reg = <0x00 0x23020000 0x00 0x100>;
+		power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
+		clock-names = "tbclk", "fck";
+		status = "disabled";
+	};
+
+	mcasp0: audio-controller@2b00000 {
+		compatible = "ti,am33xx-mcasp-audio";
+		reg = <0x00 0x02b00000 0x00 0x2000>,
+		      <0x00 0x02b08000 0x00 0x400>;
+		reg-names = "mpu", "dat";
+		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "tx", "rx";
+
+		dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
+		dma-names = "tx", "rx";
+
+		clocks = <&k3_clks 190 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 190 0>;
+		assigned-clock-parents = <&k3_clks 190 2>;
+		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+		status = "disabled";
+	};
+
+	mcasp1: audio-controller@2b10000 {
+		compatible = "ti,am33xx-mcasp-audio";
+		reg = <0x00 0x02b10000 0x00 0x2000>,
+		      <0x00 0x02b18000 0x00 0x400>;
+		reg-names = "mpu", "dat";
+		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "tx", "rx";
+
+		dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
+		dma-names = "tx", "rx";
+
+		clocks = <&k3_clks 191 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 191 0>;
+		assigned-clock-parents = <&k3_clks 191 2>;
+		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+		status = "disabled";
+	};
+
+	mcasp2: audio-controller@2b20000 {
+		compatible = "ti,am33xx-mcasp-audio";
+		reg = <0x00 0x02b20000 0x00 0x2000>,
+		      <0x00 0x02b28000 0x00 0x400>;
+		reg-names = "mpu", "dat";
+		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "tx", "rx";
+
+		dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
+		dma-names = "tx", "rx";
+
+		clocks = <&k3_clks 192 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 192 0>;
+		assigned-clock-parents = <&k3_clks 192 2>;
+		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+		status = "disabled";
 	};
 };
diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi
index f56c803560..19fc38157d 100644
--- a/arch/arm/dts/k3-am62-mcu.dtsi
+++ b/arch/arm/dts/k3-am62-mcu.dtsi
@@ -14,6 +14,57 @@
 		pinctrl-single,function-mask = <0xffffffff>;
 	};
 
+	mcu_esm: esm@4100000 {
+		compatible = "ti,j721e-esm";
+		reg = <0x00 0x4100000 0x00 0x1000>;
+		ti,esm-pins = <0>, <1>, <2>, <85>;
+	};
+
+	/*
+	 * The MCU domain timer interrupts are routed only to the ESM module,
+	 * and not currently available for Linux. The MCU domain timers are
+	 * of limited use without interrupts, and likely reserved by the ESM.
+	 */
+	mcu_timer0: timer@4800000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x4800000 0x00 0x400>;
+		clocks = <&k3_clks 35 2>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+		status = "reserved";
+	};
+
+	mcu_timer1: timer@4810000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x4810000 0x00 0x400>;
+		clocks = <&k3_clks 48 2>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+		status = "reserved";
+	};
+
+	mcu_timer2: timer@4820000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x4820000 0x00 0x400>;
+		clocks = <&k3_clks 49 2>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+		status = "reserved";
+	};
+
+	mcu_timer3: timer@4830000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x4830000 0x00 0x400>;
+		clocks = <&k3_clks 50 2>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+		status = "reserved";
+	};
+
 	mcu_uart0: serial@4a00000 {
 		compatible = "ti,am64-uart", "ti,am654-uart";
 		reg = <0x00 0x04a00000 0x00 0x100>;
@@ -21,6 +72,7 @@
 		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 149 0>;
 		clock-names = "fclk";
+		status = "disabled";
 	};
 
 	mcu_i2c0: i2c@4900000 {
@@ -32,6 +84,7 @@
 		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 106 2>;
 		clock-names = "fck";
+		status = "disabled";
 	};
 
 	mcu_spi0: spi@4b00000 {
@@ -42,6 +95,7 @@
 		#size-cells = <0>;
 		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 147 0>;
+		status = "disabled";
 	};
 
 	mcu_spi1: spi@4b10000 {
@@ -52,6 +106,7 @@
 		#size-cells = <0>;
 		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 148 0>;
+		status = "disabled";
 	};
 
 	mcu_gpio_intr: interrupt-controller@4210000 {
@@ -81,4 +136,15 @@
 		clocks = <&k3_clks 79 0>;
 		clock-names = "gpio";
 	};
+
+	mcu_rti0: watchdog@4880000 {
+		compatible = "ti,j7-rti-wdt";
+		reg = <0x00 0x04880000 0x00 0x100>;
+		clocks = <&k3_clks 131 0>;
+		power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
+		assigned-clocks = <&k3_clks 131 0>;
+		assigned-clock-parents = <&k3_clks 131 2>;
+		/* Tightly coupled to M4F */
+		status = "reserved";
+	};
 };
diff --git a/arch/arm/dts/k3-am62-thermal.dtsi b/arch/arm/dts/k3-am62-thermal.dtsi
new file mode 100644
index 0000000000..a358757e26
--- /dev/null
+++ b/arch/arm/dts/k3-am62-thermal.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+	main0_thermal: main0-thermal {
+		polling-delay-passive = <250>;	/* milliSeconds */
+		polling-delay = <500>;		/* milliSeconds */
+		thermal-sensors = <&wkup_vtm0 0>;
+
+		trips {
+			main0_crit: main0-crit {
+				temperature = <105000>;	/* milliCelsius */
+				hysteresis = <2000>;	/* milliCelsius */
+				type = "critical";
+			};
+		};
+	};
+
+	main1_thermal: main1-thermal {
+		polling-delay-passive = <250>;	/* milliSeconds */
+		polling-delay = <500>;		/* milliSeconds */
+		thermal-sensors = <&wkup_vtm0 1>;
+
+		trips {
+			main1_crit: main1-crit {
+				temperature = <105000>;	/* milliCelsius */
+				hysteresis = <2000>;	/* milliCelsius */
+				type = "critical";
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/k3-am62-verdin-dev.dtsi b/arch/arm/dts/k3-am62-verdin-dev.dtsi
new file mode 100644
index 0000000000..846caee7df
--- /dev/null
+++ b/arch/arm/dts/k3-am62-verdin-dev.dtsi
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * Common dtsi for Verdin AM62 SoM on Development carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ * https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+ */
+
+/* Verdin ETHs */
+&cpsw3g {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>;
+	status = "okay";
+};
+
+/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
+&cpsw3g_mdio {
+	status = "okay";
+
+	cpsw3g_phy1: ethernet-phy@7 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <7>;
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
+		micrel,led-mode = <0>;
+	};
+};
+
+/* Verdin ETH_1 (On-module PHY) */
+&cpsw_port1 {
+	status = "okay";
+};
+
+/* Verdin ETH_2_RGMII */
+&cpsw_port2 {
+	phy-handle = <&cpsw3g_phy1>;
+	phy-mode = "rgmii-rxid";
+	status = "okay";
+};
+
+/* Verdin PWM_1, PWM_2 */
+&epwm0 {
+	status = "okay";
+};
+
+/* Verdin PWM_3_DSI */
+&epwm1 {
+	status = "okay";
+};
+
+&main_gpio0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ctrl_sleep_moci>,
+		    <&pinctrl_gpio_5>,
+		    <&pinctrl_gpio_6>,
+		    <&pinctrl_gpio_7>,
+		    <&pinctrl_gpio_8>;
+};
+
+/* Verdin I2C_1 */
+&main_i2c1 {
+	status = "okay";
+
+	/* IO Expander */
+	gpio_expander_21: gpio@21 {
+		compatible = "nxp,pcal6416";
+		reg = <0x21>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	/* Current measurement into module VCC */
+	hwmon@40 {
+		compatible = "ti,ina219";
+		reg = <0x40>;
+		shunt-resistor = <10000>;
+	};
+
+	/* Temperature sensor */
+	sensor@4f {
+		compatible = "ti,tmp75c";
+		reg = <0x4f>;
+	};
+
+	/* EEPROM */
+	eeprom@57 {
+		compatible = "st,24c02", "atmel,24c02";
+		reg = <0x57>;
+		pagesize = <16>;
+	};
+};
+
+/* Verdin I2C_2_DSI */
+&main_i2c2 {
+	status = "okay";
+};
+
+/* Verdin I2C_4_CSI */
+&main_i2c3 {
+	status = "okay";
+};
+
+/* Verdin CAN_1 */
+&main_mcan0 {
+	status = "okay";
+};
+
+/* Verdin SPI_1 */
+&main_spi1 {
+	status = "okay";
+};
+
+/* Verdin UART_3 */
+&main_uart0 {
+	status = "okay";
+};
+
+/* Verdin UART_1, connector X50 through RS485 transceiver. */
+&main_uart1 {
+	linux,rs485-enabled-at-boot-time;
+	rs485-rx-during-tx;
+	status = "okay";
+};
+
+/* Verdin I2S_1 */
+&mcasp0 {
+	status = "okay";
+};
+
+&mcu_gpio0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio_1>,
+		    <&pinctrl_gpio_2>,
+		    <&pinctrl_gpio_3>,
+		    <&pinctrl_gpio_4>;
+};
+
+/* Verdin I2C_3_HDMI */
+&mcu_i2c0 {
+	status = "okay";
+};
+
+/* Verdin UART_4 */
+&mcu_uart0 {
+	status = "okay";
+};
+
+/* Verdin QSPI_1 */
+&ospi0 {
+	status = "okay";
+};
+
+/* Verdin SD_1 */
+&sdhci1 {
+	ti,driver-strength-ohm = <33>;
+	status = "okay";
+};
+
+/* Verdin USB_1 */
+&usbss0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+/* Verdin USB_2 */
+&usbss1 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+/* Verdin CTRL_WAKE1_MICO# */
+&verdin_gpio_keys {
+	status = "okay";
+};
+
+/* Verdin UART_2 */
+&wkup_uart0 {
+	/* FIXME: WKUP UART0 is used by DM firmware */
+	status = "reserved";
+};
diff --git a/arch/arm/dts/k3-am62-verdin-wifi.dtsi b/arch/arm/dts/k3-am62-verdin-wifi.dtsi
new file mode 100644
index 0000000000..90ddc71bcd
--- /dev/null
+++ b/arch/arm/dts/k3-am62-verdin-wifi.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * Common dtsi for Verdin AM62 SoM WB variant
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ */
+
+/ {
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_wifi_en>;
+		reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>;
+	};
+};
+
+/* On-module Wi-Fi */
+&sdhci2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci2>;
+	bus-width = <4>;
+	cap-power-off-card;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	non-removable;
+	ti,fails-without-test-cd;
+	ti,driver-strength-ohm = <50>;
+	vmmc-supply = <&reg_3v3>;
+	status = "okay";
+};
+
+/* On-module Bluetooth */
+&main_uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/k3-am62-verdin.dtsi b/arch/arm/dts/k3-am62-verdin.dtsi
new file mode 100644
index 0000000000..57dd061911
--- /dev/null
+++ b/arch/arm/dts/k3-am62-verdin.dtsi
@@ -0,0 +1,1401 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * Common dtsi for Verdin AM62 SoM
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	aliases {
+		ethernet0 = &cpsw_port1;
+		ethernet1 = &cpsw_port2;
+		i2c0 = &main_i2c0;
+		i2c1 = &main_i2c1;
+		i2c2 = &main_i2c2;
+		i2c3 = &mcu_i2c0;
+		i2c4 = &main_i2c3;
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
+		mmc2 = &sdhci2;
+		rtc0 = &rtc_i2c;
+		rtc1 = &wkup_rtc0;
+		serial0 = &main_uart1;
+		serial1 = &wkup_uart0;
+		serial2 = &main_uart0;
+		serial3 = &mcu_uart0;
+		serial4 = &main_uart5;
+		usb0 = &usb0;
+		usb1 = &usb1;
+	};
+
+	verdin_gpio_keys: gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ctrl_wake1_mico>;
+		status = "disabled";
+
+		verdin_key_wakeup: key-wakeup {
+			debounce-interval = <10>;
+			/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
+			gpios = <&main_gpio0 32 GPIO_ACTIVE_LOW>;
+			label = "Wake-Up";
+			linux,code = <KEY_WAKEUP>;
+			wakeup-source;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0x00000000 0x40000000>; /* 1G RAM */
+	};
+
+	opp-table {
+		/* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */
+		opp-1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-supported-hw = <0x01 0x0004>;
+			clock-latency-ns = <6000000>;
+		};
+	};
+
+	/* Module Power Supply */
+	reg_vsodimm: regulator-vsodimm {
+		compatible = "regulator-fixed";
+		regulator-name = "+V_SODIMM";
+	};
+
+	/* Non PMIC On-module Supplies */
+	reg_3v3: regulator-3v3 {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "On-module +V3.3";
+		vin-supply = <&reg_vsodimm>;
+	};
+
+	reg_1v2_dsi: regulator-1v2-dsi {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <1200000>;
+		regulator-min-microvolt = <1200000>;
+		regulator-name = "On-module +V1.2_DSI";
+		vin-supply = <&reg_1v8>;
+	};
+
+	/* Enabled by +V1.2_DSI */
+	reg_1v8_dsi: regulator-1v8-dsi {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "On-module +V1.8_DSI";
+		vin-supply = <&reg_1v8>;
+	};
+
+	/* Enabled by +V2.5_ETH */
+	reg_1v0_eth: regulator-1v0-eth {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <1000000>;
+		regulator-min-microvolt = <1000000>;
+		regulator-name = "On-module +V1.0_ETH";
+		vin-supply = <&reg_1v8>;
+	};
+
+	/* Enabled by +V2.5_ETH */
+	reg_1v8_eth: regulator-1v8-eth {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "On-module +V1.8_ETH";
+		vin-supply = <&reg_1v8>;
+	};
+
+	/* Verdin SD_1 Power Supply */
+	reg_sdhc1_vmmc: regulator-sdhci1 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_sd1_pwr_en>;
+		enable-active-high;
+		/* Verdin SD_1_PWR_EN (SODIMM 76) */
+		gpio = <&main_gpio0 29 GPIO_ACTIVE_HIGH>;
+		off-on-delay-us = <100000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "+V3.3_SD";
+		startup-delay-us = <2000>;
+	};
+
+	reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc {
+		compatible = "regulator-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_vsel_sd>;
+		/* PMIC_VSEL_SD */
+		gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>;
+		regulator-name = "LDO1-VSEL-SD (PMIC)";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		states = <1800000 0x0>,
+			 <3300000 0x1>;
+		vin-supply = <&reg_sd_3v3_1v8>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_tfa_ddr: tfa@9e780000 {
+			reg = <0x00 0x9e780000 0x00 0x80000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9db00000 0x00 0xc00000>;
+			no-map;
+		};
+	};
+};
+
+&main_pmx0 {
+	/* Verdin PWM_1 */
+	pinctrl_epwm0_a: main-epwm0a-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (A13) SPI0_CS0.EHRPWM0_A */ /* SODIMM 15 */
+		>;
+	};
+
+	/* Verdin PWM_2 */
+	pinctrl_epwm0_b: main-epwm0b-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ /* SODIMM 16 */
+		>;
+	};
+
+	/* Verdin PWM_3_DSI */
+	pinctrl_epwm1_a: main-epwm1a-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (A14) SPI0_CLK.EHRPWM1_A */ /* SODIMM 19 */
+		>;
+	};
+
+	/* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */
+	pinctrl_qspi1_clk_gpio: main-gpio0-0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0000, PIN_INPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */
+		>;
+	};
+
+	/* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */
+	pinctrl_qspi1_io0_gpio: main-gpio0-3-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */
+		>;
+	};
+
+	/* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */
+	pinctrl_qspi1_io1_gpio: main-gpio0-4-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */
+		>;
+	};
+
+	/* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */
+	pinctrl_qspi1_io2_gpio: main-gpio0-5-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */
+		>;
+	};
+
+	/* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */
+	pinctrl_qspi1_io3_gpio: main-gpio0-6-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */
+		>;
+	};
+
+	/* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */
+	pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */
+		>;
+	};
+
+	/* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */
+	pinctrl_qspi1_cs2_gpio: main-gpio0-12-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */
+		>;
+	};
+
+	/* WiFi_W_WKUP_HOST# */
+	pinctrl_wifi_w_wkup_host: main-gpio0-15-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */ /* SODIMM 174 */
+		>;
+	};
+
+	/* WiFi_BT_WKUP_HOST# */
+	pinctrl_bt_wkup_host: main-gpio0-16-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */ /* SODIMM 172 */
+		>;
+	};
+
+	/* PMIC_ETH_RESET# */
+	pinctrl_eth_reset: main-gpio0-17-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0044, PIN_INPUT, 7) /* (N24) GPMC0_AD2.GPIO0_17 */
+		>;
+	};
+
+	/* PMIC_BRIDGE_RESET# */
+	pinctrl_bridge_reset: main-gpio0-20-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0050, PIN_INPUT, 7) /* (P22) GPMC0_AD5.GPIO0_20 */
+		>;
+	};
+
+	/* PMIC_VSEL_SD */
+	pinctrl_vsel_sd: main-gpio0-21-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0054, PIN_INPUT, 7) /* (P21) GPMC0_AD6.GPIO0_21 */
+		>;
+	};
+
+	/* PMIC_EN_WIFI */
+	pinctrl_wifi_en: main-gpio0-22-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0058, PIN_INPUT, 7) /* (R23) GPMC0_AD7.GPIO0_22 */
+		>;
+	};
+
+	/* PMIC_ETH_INT# */
+	pinctrl_eth_int: main-gpio0-25-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0064, PIN_INPUT_PULLUP, 7) /* (T25) GPMC0_AD10.GPIO0_25 */
+		>;
+	};
+
+	/* WiFi_WKUP_BT# */
+	pinctrl_wifi_wkup_bt: main-gpio0-26-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0068, PIN_INPUT, 7) /* (R21) GPMC0_AD11.GPIO0_26 */
+		>;
+	};
+
+	/* WiFi_WKUP_WLAN# */
+	pinctrl_wifi_wkup_wlan: main-gpio0-27-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x006c, PIN_INPUT, 7) /* (T22) GPMC0_AD12.GPIO0_27 */
+		>;
+	};
+
+	/* Verdin SD_1_PWR_EN */
+	pinctrl_sd1_pwr_en: main-gpio0-29-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0074, PIN_INPUT, 7) /* (U25) GPMC0_AD14.GPIO0_29 */ /* SODIMM 76 */
+		>;
+	};
+
+	/* Verdin DSI_1_BKL_EN */
+	pinctrl_dsi1_bkl_en: main-gpio0-30-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0078, PIN_INPUT, 7) /* (U24) GPMC0_AD15.GPIO0_30 */ /* SODIMM 21 */
+		>;
+	};
+
+	/* Verdin CTRL_SLEEP_MOCI# */
+	pinctrl_ctrl_sleep_moci: main-gpio0-31-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x007c, PIN_INPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 256 */
+		>;
+	};
+
+	/* Verdin CTRL_WAKE1_MICO# */
+	pinctrl_ctrl_wake1_mico: main-gpio0-32-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 252 */
+		>;
+	};
+
+	/* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */
+	pinctrl_i2s_2_d_out_gpio: main-gpio0-34-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x008c, PIN_INPUT, 7) /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */
+		>;
+	};
+
+	/* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */
+	pinctrl_i2s_2_bclk_gpio: main-gpio0-35-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0090, PIN_INPUT, 7) /* (M24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */
+		>;
+	};
+
+	/* Verdin GPIO_6 */
+	pinctrl_gpio_6: main-gpio0-36-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0094, PIN_INPUT, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ /* SODIMM 218 */
+		>;
+	};
+
+	/* Verdin ETH_2_RGMII_INT# */
+	pinctrl_eth2_rgmii_int: main-gpio0-38-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x009c, PIN_INPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 189 */
+		>;
+	};
+
+	/* Verdin GPIO_5 */
+	pinctrl_gpio_5: main-gpio0-40-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ /* SODIMM 216 */
+		>;
+	};
+
+	/* Verdin GPIO_7 */
+	pinctrl_gpio_7: main-gpio0-41-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 220 */
+		>;
+	};
+
+	/* Verdin GPIO_8 */
+	pinctrl_gpio_8: main-gpio0-42-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 222 */
+		>;
+	};
+
+	/* Verdin USB_1_OC# */
+	pinctrl_usb1_oc: main-gpio0-71-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0124, PIN_INPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ /* SODIMM 157 */
+		>;
+	};
+
+	/* Verdin USB_2_OC# */
+	pinctrl_usb2_oc: main-gpio0-72-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ /* SODIMM 187 */
+		>;
+	};
+
+	/* Verdin PWM_3_DSI as GPIO */
+	pinctrl_pwm3_dsi_gpio: main-gpio1-17-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01bc, PIN_INPUT, 7) /* (A14) SPI0_CLK.GPIO1_17 */ /* SODIMM 19 */
+		>;
+	};
+
+	/* Verdin QSPI_1_DQS as GPIO */
+	pinctrl_qspi1_dqs_gpio: main-gpio1-18-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01c0, PIN_INPUT, 7) /* (B13) SPI0_D0.GPIO1_18 */ /* SODIMM 66 */
+		>;
+	};
+
+	/* Verdin USB_1_ID */
+	pinctrl_usb0_id: main-gpio1-19-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1.GPIO1_19 */ /* SODIMM 161 */
+		>;
+	};
+
+	/* Verdin DSI_1_INT# (pulled-up as active-low) */
+	pinctrl_dsi1_int: main-gpio1-49-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0244, PIN_INPUT_PULLUP, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ /* SODIMM 17 */
+		>;
+	};
+
+	/* On-module I2C - PMIC_I2C */
+	pinctrl_i2c0: main-i2c0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01e0, PIN_INPUT, 0) /* (B16) I2C0_SCL */ /* PMIC_I2C_SCL */
+			AM62X_IOPAD(0x01e4, PIN_INPUT, 0) /* (A16) I2C0_SDA */ /* PMIC_I2C_SDA */
+		>;
+	};
+
+	/* Verdin I2C_1 */
+	pinctrl_i2c1: main-i2c1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ /* SODIMM 14 */
+			AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ /* SODIMM 12 */
+		>;
+	};
+
+	/* Verdin I2C_2_DSI */
+	pinctrl_i2c2: main-i2c2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x00b0, PIN_INPUT, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ /* SODIMM 55 */
+			AM62X_IOPAD(0x00b4, PIN_INPUT, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ /* SODIMM 53 */
+		>;
+	};
+
+	/* Verdin I2C_4_CSI */
+	pinctrl_i2c3: main-i2c3-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */
+			AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */
+		>;
+	};
+
+	/* I2S_1_MCLK */
+	pinctrl_i2s1_mclk: main-system-audio-ext-reflock1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ /* SODIMM 38 */
+		>;
+	};
+
+	/* Verdin I2S_1 */
+	pinctrl_mcasp0: main-mcasp0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01a4, PIN_INPUT,  0) /* (B20) MCASP0_ACLKX */ /* SODIMM 30 */
+			AM62X_IOPAD(0x01a8, PIN_INPUT,  0) /* (D20) MCASP0_AFSX  */ /* SODIMM 32 */
+			AM62X_IOPAD(0x01a0, PIN_OUTPUT, 0) /* (E18) MCASP0_AXR0  */ /* SODIMM 34 */
+			AM62X_IOPAD(0x019c, PIN_INPUT,  0) /* (B18) MCASP0_AXR1  */ /* SODIMM 36 */
+		>;
+	};
+
+	/* Verdin I2S_2 */
+	pinctrl_mcasp1: main-mcasp1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0090, PIN_INPUT,  2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */
+			AM62X_IOPAD(0x0098, PIN_INPUT,  2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX     */ /* SODIMM 44 */
+			AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0       */ /* SODIMM 46 */
+			AM62X_IOPAD(0x0088, PIN_INPUT,  2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1   */ /* SODIMM 48 */
+		>;
+	};
+
+	/* Verdin CAN_1 */
+	pinctrl_mcan0: main-mcan0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01dc, PIN_INPUT,  0) /* (E15) MCAN0_RX */ /* SODIMM 22 */
+			AM62X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ /* SODIMM 20 */
+		>;
+	};
+
+	/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
+	pinctrl_mdio: main-mdio1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC  */ /* ETH_1_MDC,  SODIMM 193 */
+			AM62X_IOPAD(0x15c, PIN_INPUT, 0)  /* (AB22) MDIO0_MDIO */ /* ETH_1_MDIO, SODIMM 191 */
+		>;
+	};
+
+	/* On-module eMMC */
+	pinctrl_sdhci0: main-mmc0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x220, PIN_INPUT, 0) /*  (Y3) MMC0_CMD  */
+			AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK  */
+			AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
+			AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
+			AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
+			AM62X_IOPAD(0x208, PIN_INPUT, 0) /*  (Y4) MMC0_DAT3 */
+			AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
+			AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
+			AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
+			AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
+		>;
+	};
+
+	/* Verdin SD_1 */
+	pinctrl_sdhci1: main-mmc1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x23c, PIN_INPUT,        0) /* (A21) MMC1_CMD  */ /* SODIMM 74 */
+			AM62X_IOPAD(0x234, PIN_INPUT,        0) /* (B22) MMC1_CLK  */ /* SODIMM 78 */
+			AM62X_IOPAD(0x230, PIN_INPUT,        0) /* (A22) MMC1_DAT0 */ /* SODIMM 80 */
+			AM62X_IOPAD(0x22c, PIN_INPUT,        0) /* (B21) MMC1_DAT1 */ /* SODIMM 82 */
+			AM62X_IOPAD(0x228, PIN_INPUT,        0) /* (C21) MMC1_DAT2 */ /* SODIMM 70 */
+			AM62X_IOPAD(0x224, PIN_INPUT,        0) /* (D22) MMC1_DAT3 */ /* SODIMM 72 */
+			AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ /* SODIMM 84 */
+		>;
+	};
+
+	/* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */
+	pinctrl_sdhci2: main-mmc2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD   */ /* WiFi_SDIO_CMD   */
+			AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK   */ /* WiFi_SDIO_CLK   */
+			AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0  */ /* WiFi_SDIO_DATA0 */
+			AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1  */ /* WiFi_SDIO_DATA1 */
+			AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2  */ /* WiFi_SDIO_DATA2 */
+			AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3  */ /* WiFi_SDIO_DATA3 */
+			AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */
+		>;
+	};
+
+	/* Verdin QSPI_1 */
+	pinctrl_ospi0: main-ospi0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK  */ /* SODIMM 52 */
+			AM62X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ /* SODIMM 54 */
+			AM62X_IOPAD(0x0030, PIN_OUTPUT, 0) /* (G21) OSPI0_CSn1 */ /* SODIMM 64 */
+			AM62X_IOPAD(0x000c, PIN_INPUT, 0)  /* (E25) OSPI0_D0   */ /* SODIMM 56 */
+			AM62X_IOPAD(0x0010, PIN_INPUT, 0)  /* (G24) OSPI0_D1   */ /* SODIMM 58 */
+			AM62X_IOPAD(0x0014, PIN_INPUT, 0)  /* (F25) OSPI0_D2   */ /* SODIMM 60 */
+			AM62X_IOPAD(0x0018, PIN_INPUT, 0)  /* (F24) OSPI0_D3   */ /* SODIMM 62 */
+		>;
+	};
+
+	/* Verdin ETH_1 RGMII (On-module PHY) */
+	pinctrl_rgmii1: main-rgmii1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x14c, PIN_INPUT,  0) /* (AB17) RGMII1_RD0    */
+			AM62X_IOPAD(0x150, PIN_INPUT,  0) /* (AC17) RGMII1_RD1    */
+			AM62X_IOPAD(0x154, PIN_INPUT,  0) /* (AB16) RGMII1_RD2    */
+			AM62X_IOPAD(0x158, PIN_INPUT,  0) /* (AA15) RGMII1_RD3    */
+			AM62X_IOPAD(0x148, PIN_INPUT,  0) /* (AD17) RGMII1_RXC    */
+			AM62X_IOPAD(0x144, PIN_INPUT,  0) /* (AE17) RGMII1_RX_CTL */
+			AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0    */
+			AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1    */
+			AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2    */
+			AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3    */
+			AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC    */
+			AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
+		>;
+	};
+
+	/* Verdin ETH_2 RGMII */
+	pinctrl_rgmii2: main-rgmii2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x184, PIN_INPUT,  0) /* (AE23) RGMII2_RD0    */ /* SODIMM 201 */
+			AM62X_IOPAD(0x188, PIN_INPUT,  0) /* (AB20) RGMII2_RD1    */ /* SODIMM 203 */
+			AM62X_IOPAD(0x18c, PIN_INPUT,  0) /* (AC21) RGMII2_RD2    */ /* SODIMM 205 */
+			AM62X_IOPAD(0x190, PIN_INPUT,  0) /* (AE22) RGMII2_RD3    */ /* SODIMM 207 */
+			AM62X_IOPAD(0x180, PIN_INPUT,  0) /* (AD23) RGMII2_RXC    */ /* SODIMM 197 */
+			AM62X_IOPAD(0x17c, PIN_INPUT,  0) /* (AD22) RGMII2_RX_CTL */ /* SODIMM 199 */
+			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /*  (Y18) RGMII2_TD0    */ /* SODIMM 221 */
+			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1    */ /* SODIMM 219 */
+			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2    */ /* SODIMM 217 */
+			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3    */ /* SODIMM 215 */
+			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC    */ /* SODIMM 213 */
+			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ /* SODIMM 211 */
+		>;
+	};
+
+	/* Verdin SPI_1 */
+	pinctrl_spi1: main-spi1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* (J25) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */
+			AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */
+			AM62X_IOPAD(0x0024, PIN_INPUT, 1) /* (H25) OSPI0_D6.SPI1_D0  */ /* SODIMM 200 */
+			AM62X_IOPAD(0x0028, PIN_INPUT, 1) /* (J22) OSPI0_D7.SPI1_D1  */ /* SODIMM 198 */
+		>;
+	};
+
+	/* ETH_25MHz_CLK */
+	pinctrl_eth_clock: main-system-clkout0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */
+		>;
+	};
+
+	/* PMIC_EXTINT# */
+	pinctrl_pmic_extint: main-system-extint-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */
+		>;
+	};
+
+	/* Verdin UART_3, used as the Linux console */
+	pinctrl_uart0: main-uart0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x1c8, PIN_INPUT_PULLUP, 0) /* (D14) UART0_RXD */ /* SODIMM 147 */
+			AM62X_IOPAD(0x1cc, PIN_OUTPUT,       0) /* (E14) UART0_TXD */ /* SODIMM 149 */
+		>;
+	};
+
+	/* Verdin UART_1 */
+	pinctrl_uart1: main-uart1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0194, PIN_INPUT_PULLUP, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */
+			AM62X_IOPAD(0x0198, PIN_OUTPUT,       2) /* (A19) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */
+			AM62X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 2) /* (E19) MCASP0_AFSR.UART1_RXD  */ /* SODIMM 129 */
+			AM62X_IOPAD(0x01b0, PIN_OUTPUT,       2) /* (A20) MCASP0_ACLKR.UART1_TXD */ /* SODIMM 131 */
+		>;
+	};
+
+	/* Bluetooth on WB SKUs, module-specific UART otherwise */
+	pinctrl_uart5: main-uart5-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0008, PIN_INPUT_PULLUP, 5) /* (J24) OSPI0_DQS.UART5_CTSn    */ /* WiFi_UART_CTS */
+			AM62X_IOPAD(0x0004, PIN_OUTPUT,       5) /* (G25) OSPI0_LBCLKO.UART5_RTSn */ /* WiFi_UART_RTS */
+			AM62X_IOPAD(0x0034, PIN_INPUT_PULLUP, 5) /* (H21) OSPI0_CSn2.UART5_RXD    */ /* WiFi_UART_RXD */
+			AM62X_IOPAD(0x0038, PIN_OUTPUT,       5) /* (E24) OSPI0_CSn3.UART5_TXD    */ /* WiFi_UART_TXD */
+		>;
+	};
+
+	/* Verdin USB_1 */
+	pinctrl_usb0: main-usb0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */
+		>;
+	};
+
+	/* Verdin USB_2 */
+	pinctrl_usb1: main-usb1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ /* SODIMM 185 */
+		>;
+	};
+
+	/* DSS VOUT0 RGB */
+	pinctrl_parallel_rgb: main-vout-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC            */
+			AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC            */
+			AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK             */
+			AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /*  (Y20) VOUT0_DE               */
+			AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /*  (U22) VOUT0_DATA0            */
+			AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /*  (V24) VOUT0_DATA1            */
+			AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /*  (W25) VOUT0_DATA2            */
+			AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /*  (W24) VOUT0_DATA3            */
+			AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /*  (Y25) VOUT0_DATA4            */
+			AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /*  (Y24) VOUT0_DATA5            */
+			AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /*  (Y23) VOUT0_DATA6            */
+			AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7            */
+			AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /*  (V21) VOUT0_DATA8            */
+			AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /*  (W21) VOUT0_DATA9            */
+			AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /*  (V20) VOUT0_DATA10           */
+			AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11           */
+			AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12           */
+			AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13           */
+			AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /*  (Y22) VOUT0_DATA14           */
+			AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15           */
+			AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /*  (R24) GPMC0_AD8.VOUT0_DATA16 */
+			AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /*  (R25) GPMC0_AD9.VOUT0_DATA17 */
+		>;
+	};
+};
+
+&mcu_pmx0 {
+	/* Verdin PCIE_1_RESET# */
+	pinctrl_pcie_1_reset: mcu-gpio0-0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x0000, PIN_INPUT, 7) /* (E8) MCU_SPI0_CS0.MCU_GPIO0_0 */ /* SODIMM 244 */
+		>;
+	};
+
+	/* Verdin GPIO_1 */
+	pinctrl_gpio_1: mcu-gpio0-1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (B8) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */
+		>;
+	};
+
+	/* Verdin GPIO_2 */
+	pinctrl_gpio_2: mcu-gpio0-2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (A7) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */
+		>;
+	};
+
+	/* Verdin GPIO_3 */
+	pinctrl_gpio_3: mcu-gpio0-3-default-pins {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (D9) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */
+		>;
+	};
+
+	/* Verdin GPIO_4 */
+	pinctrl_gpio_4: mcu-gpio0-4-default-pins {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (C9) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */
+		>;
+	};
+
+	/* Verdin I2C_3_HDMI */
+	pinctrl_mcu_i2c0: mcu-i2c0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /*  (A8) MCU_I2C0_SCL */ /* SODIMM 59 */
+			AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */
+		>;
+	};
+
+	/* Verdin UART_4 - Reserved to Cortex-M4 */
+	pinctrl_mcu_uart0: mcu-uart0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x0014, PIN_INPUT_PULLUP, 0) /* (B5) MCU_UART0_RXD */ /* SODIMM 151 */
+			AM62X_MCU_IOPAD(0x0018, PIN_OUTPUT,       0) /* (A5) MCU_UART0_TXD */ /* SODIMM 153 */
+		>;
+	};
+
+	/* Verdin CSI_1_MCLK */
+	pinctrl_csi1_mclk: wkup-clkout0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ /* SODIMM 91 */
+		>;
+	};
+
+	/* Verdin UART_2 */
+	pinctrl_wkup_uart0: wkup-uart0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x002c, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_UART0_CTSn */ /* SODIMM 143 */
+			AM62X_MCU_IOPAD(0x0030, PIN_OUTPUT,       0) /* (A4) WKUP_UART0_RTSn */ /* SODIMM 141 */
+			AM62X_MCU_IOPAD(0x0024, PIN_INPUT_PULLUP, 0) /* (B4) WKUP_UART0_RXD  */ /* SODIMM 137 */
+			AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT,       0) /* (C5) WKUP_UART0_TXD  */ /* SODIMM 139 */
+		>;
+	};
+};
+
+&cpsw3g {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii1>;
+	status = "disabled";
+};
+
+/* Verdin ETH_1 (On-module PHY) */
+&cpsw_port1 {
+	phy-handle = <&cpsw3g_phy0>;
+	phy-mode = "rgmii-rxid";
+	status = "disabled";
+};
+
+/* Verdin ETH_2_RGMII */
+&cpsw_port2 {
+	status = "disabled";
+};
+
+/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
+&cpsw3g_mdio {
+	assigned-clocks = <&k3_clks 157 20>;
+	assigned-clock-parents = <&k3_clks 157 22>;
+	assigned-clock-rates = <25000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eth_clock>, <&pinctrl_mdio>;
+	status = "disabled";
+
+	cpsw3g_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id2000.a231";
+		reg = <0>;
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_eth_int>, <&pinctrl_eth_reset>;
+		reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10>;
+		reset-deassert-us = <1000>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+	};
+};
+
+/* Verdin PWM_1, PWM_2 */
+&epwm0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_epwm0_a>, <&pinctrl_epwm0_b>;
+	status = "disabled";
+};
+
+/* Verdin PWM_3_DSI */
+&epwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_epwm1_a>;
+	status = "disabled";
+};
+
+&main_gpio0 {
+	gpio-line-names =
+		"SODIMM_52", /* 0 */
+		"",
+		"",
+		"SODIMM_56",
+		"SODIMM_58",
+		"SODIMM_60",
+		"SODIMM_62",
+		"",
+		"",
+		"",
+		"", /* 10 */
+		"SODIMM_54",
+		"SODIMM_64",
+		"",
+		"",
+		"SODIMM_174",
+		"SODIMM_172",
+		"",
+		"",
+		"",
+		"", /* 20 */
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"SODIMM_76",
+		"SODIMM_21", /* 30 */
+		"SODIMM_256",
+		"SODIMM_252",
+		"",
+		"SODIMM_46",
+		"SODIMM_42",
+		"SODIMM_218",
+		"",
+		"SODIMM_189",
+		"",
+		"SODIMM_216", /* 40 */
+		"SODIMM_220",
+		"SODIMM_222",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"", /* 50 */
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"", /* 60 */
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"", /* 70 */
+		"SODIMM_157",
+		"SODIMM_187",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"", /* 80 */
+		"",
+		"",
+		"",
+		"",
+		"",
+		"";
+
+	verdin_ctrl_sleep_moci: ctrl-sleep-moci-hog {
+		gpio-hog;
+		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+		gpios = <31 GPIO_ACTIVE_HIGH>;
+		line-name = "CTRL_SLEEP_MOCI#";
+		output-high;
+	};
+};
+
+&main_gpio1 {
+	gpio-line-names =
+		"", /* 0 */
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"", /* 10 */
+		"",
+		"",
+		"",
+		"",
+		"SODIMM_15",
+		"SODIMM_16",
+		"SODIMM_19",
+		"SODIMM_66",
+		"SODIMM_161",
+		"", /* 20 */
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"", /* 30 */
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"", /* 40 */
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"SODIMM_17",
+		"", /* 50 */
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"", /* 60 */
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"", /* 70 */
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"", /* 80 */
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"";
+};
+
+/* On-module I2C - PMIC_I2C */
+&main_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	dsi_bridge: dsi@e {
+		compatible = "toshiba,tc358778";
+		reg = <0xe>;
+		assigned-clocks = <&k3_clks 157 20>;
+		assigned-clock-parents = <&k3_clks 157 22>;
+		assigned-clock-rates = <25000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_bridge_reset>;
+		clocks = <&k3_clks 157 20>;
+		clock-names = "refclk";
+		reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>;
+		vddc-supply = <&reg_1v2_dsi>;
+		vddmipi-supply = <&reg_1v2_dsi>;
+		vddio-supply = <&reg_1v8_dsi>;
+
+		dsi_bridge_ports: ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				rgb_in: endpoint {
+					data-lines = <18>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+			};
+		};
+	};
+
+	pmic@30 {
+		compatible = "ti,tps65219";
+		reg = <0x30>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic_extint>;
+		interrupt-parent = <&gic500>;
+		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+
+		buck1-supply = <&reg_vsodimm>;
+		buck2-supply = <&reg_vsodimm>;
+		buck3-supply = <&reg_vsodimm>;
+		ldo1-supply = <&reg_3v3>;
+		ldo2-supply = <&reg_1v8>;
+		ldo3-supply = <&reg_3v3>;
+		ldo4-supply = <&reg_3v3>;
+		system-power-controller;
+		ti,power-button;
+
+		regulators {
+			reg_vdd_core: buck1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <850000>;
+				regulator-min-microvolt = <850000>;
+				regulator-name = "+VDD_CORE (PMIC BUCK1)";
+			};
+
+			reg_1v8: buck2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microvolt = <1800000>;
+				regulator-name = "+V1.8 (PMIC BUCK2)"; /* On-module and SODIMM 214 */
+			};
+
+			reg_vdd_ddr: buck3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1100000>;
+				regulator-min-microvolt = <1100000>;
+				regulator-name = "+VDD_DDR (PMIC BUCK3)";
+			};
+
+			reg_sd_3v3_1v8: ldo1 {
+				regulator-allow-bypass;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <3300000>;
+				regulator-name = "+V3.3_1.8_SD (PMIC LDO1)";
+			};
+
+			reg_vddr_core: ldo2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <850000>;
+				regulator-min-microvolt = <850000>;
+				regulator-name = "+VDDR_CORE (PMIC LDO2)";
+			};
+
+			reg_1v8a: ldo3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microvolt = <1800000>;
+				regulator-name = "+V1.8A (PMIC LDO3)";
+			};
+
+			reg_eth_2v5: ldo4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <2500000>;
+				regulator-min-microvolt = <2500000>;
+				regulator-name = "+V2.5_ETH (PMIC LDO4)";
+			};
+		};
+	};
+
+	rtc_i2c: rtc@32 {
+		compatible = "epson,rx8130";
+		reg = <0x32>;
+	};
+
+	sensor@48 {
+		compatible = "ti,tmp1075";
+		reg = <0x48>;
+	};
+
+	adc@49 {
+		compatible = "ti,ads1015";
+		reg = <0x49>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* Verdin PMIC_I2C (ADC_4 - ADC_3) */
+		channel@0 {
+			reg = <0>;
+			ti,datarate = <4>;
+			ti,gain = <2>;
+		};
+
+		/* Verdin PMIC_I2C (ADC_4 - ADC_1) */
+		channel@1 {
+			reg = <1>;
+			ti,datarate = <4>;
+			ti,gain = <2>;
+		};
+
+		/* Verdin PMIC_I2C (ADC_3 - ADC_1) */
+		channel@2 {
+			reg = <2>;
+			ti,datarate = <4>;
+			ti,gain = <2>;
+		};
+
+		/* Verdin PMIC_I2C (ADC_2 - ADC_1) */
+		channel@3 {
+			reg = <3>;
+			ti,datarate = <4>;
+			ti,gain = <2>;
+		};
+
+		/* Verdin PMIC_I2C ADC_4 */
+		channel@4 {
+			reg = <4>;
+			ti,datarate = <4>;
+			ti,gain = <2>;
+		};
+
+		/* Verdin PMIC_I2C ADC_3 */
+		channel@5 {
+			reg = <5>;
+			ti,datarate = <4>;
+			ti,gain = <2>;
+		};
+
+		/* Verdin PMIC_I2C ADC_2 */
+		channel@6 {
+			reg = <6>;
+			ti,datarate = <4>;
+			ti,gain = <2>;
+		};
+
+		/* Verdin PMIC_I2C ADC_1 */
+		channel@7 {
+			reg = <7>;
+			ti,datarate = <4>;
+			ti,gain = <2>;
+		};
+	};
+
+	eeprom@50 {
+		compatible = "st,24c02", "atmel,24c02";
+		pagesize = <16>;
+		reg = <0x50>;
+	};
+};
+
+/* Verdin I2C_1 */
+&main_i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "disabled";
+};
+
+/* Verdin I2C_2_DSI */
+&main_i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "disabled";
+};
+
+/* Verdin I2C_4_CSI */
+&main_i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "disabled";
+};
+
+&mailbox0_cluster0 {
+	mbox_m4_0: mbox-m4-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+/* Verdin CAN_1 */
+&main_mcan0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mcan0>;
+	status = "disabled";
+};
+
+/* Verdin CAN_2 - Reserved to Cortex-M4 */
+
+/* Verdin SPI_1 */
+&main_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi1>;
+	ti,pindir-d0-out-d1-in;
+	status = "disabled";
+};
+
+/* Verdin UART_3, used as the Linux console */
+&main_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart0>;
+	status = "disabled";
+};
+
+/* Verdin UART_1 */
+&main_uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "disabled";
+};
+
+/* Verdin I2S_1 */
+&mcasp0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mcasp0>;
+	op-mode = <0>; /* I2S mode */
+	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+	       1 2 0 0
+	       0 0 0 0
+	       0 0 0 0
+	       0 0 0 0
+	>;
+	tdm-slots = <2>;
+	rx-num-evt = <32>;
+	tx-num-evt = <32>;
+	#sound-dai-cells = <0>;
+	status = "disabled";
+};
+
+/* Verdin I2S_2 */
+&mcasp1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mcasp1>;
+	op-mode = <0>; /* I2S mode */
+	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+	       1 2 0 0
+	       0 0 0 0
+	       0 0 0 0
+	       0 0 0 0
+	>;
+	tdm-slots = <2>;
+	rx-num-evt = <32>;
+	tx-num-evt = <32>;
+	#sound-dai-cells = <0>;
+	status = "disabled";
+};
+
+/* Verdin I2C_3_HDMI */
+&mcu_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mcu_i2c0>;
+	status = "disabled";
+};
+
+&mcu_gpio0 {
+	gpio-line-names =
+		"SODIMM_244",
+		"SODIMM_206",
+		"SODIMM_208",
+		"SODIMM_210",
+		"SODIMM_212",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"";
+};
+
+/* Verdin UART_4 - Cortex-M4 UART */
+&mcu_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mcu_uart0>;
+	status = "disabled";
+};
+
+/* Verdin QSPI_1 */
+&ospi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ospi0>;
+	status = "disabled";
+};
+
+/* On-module eMMC */
+&sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci0>;
+	non-removable;
+	ti,driver-strength-ohm = <50>;
+	status = "okay";
+};
+
+/* Verdin SD_1 */
+&sdhci1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci1>;
+	disable-wp;
+	ti,driver-strength-ohm = <50>;
+	vmmc-supply = <&reg_sdhc1_vmmc>;
+	vqmmc-supply = <&reg_sdhc1_vqmmc>;
+	status = "disabled";
+};
+
+/* Verdin USB_1 */
+&usbss0 {
+	ti,vbus-divider;
+	status = "disabled";
+};
+
+/* TODO: role swich using ID pin */
+&usb0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb0_id>;
+	status = "disabled";
+};
+
+/* Verdin USB_2 */
+&usbss1 {
+	ti,vbus-divider;
+	status = "disabled";
+};
+
+&usb1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb1>;
+	dr_mode = "host";
+	status = "disabled";
+};
+
+/* Verdin UART_2 */
+&wkup_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wkup_uart0>;
+	status = "disabled";
+};
diff --git a/arch/arm/dts/k3-am62-wakeup.dtsi b/arch/arm/dts/k3-am62-wakeup.dtsi
index 4090134676..eae0528871 100644
--- a/arch/arm/dts/k3-am62-wakeup.dtsi
+++ b/arch/arm/dts/k3-am62-wakeup.dtsi
@@ -26,16 +26,47 @@
 		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 114 0>;
 		clock-names = "fclk";
+		status = "disabled";
 	};
 
 	wkup_i2c0: i2c@2b200000 {
 		compatible = "ti,am64-i2c", "ti,omap4-i2c";
-		reg = <0x00 0x02b200000 0x00 0x100>;
+		reg = <0x00 0x2b200000 0x00 0x100>;
 		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 107 4>;
 		clock-names = "fck";
+		status = "disabled";
+	};
+
+	wkup_rtc0: rtc@2b1f0000 {
+		compatible = "ti,am62-rtc";
+		reg = <0x00 0x2b1f0000 0x00 0x100>;
+		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
+		clock-names = "vbus", "osc32k";
+		power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
+		wakeup-source;
+	};
+
+	wkup_rti0: watchdog@2b000000 {
+		compatible = "ti,j7-rti-wdt";
+		reg = <0x00 0x2b000000 0x00 0x100>;
+		clocks = <&k3_clks 132 0>;
+		power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
+		assigned-clocks = <&k3_clks 132 0>;
+		assigned-clock-parents = <&k3_clks 132 2>;
+		/* Used by DM firmware */
+		status = "reserved";
+	};
+
+	wkup_vtm0: temperature-sensor@b00000 {
+		compatible = "ti,j7200-vtm";
+		reg = <0x00 0xb00000 0x00 0x400>,
+		      <0x00 0xb01000 0x00 0x400>;
+		power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+		#thermal-sensor-cells = <1>;
 	};
 };
diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi
index 37fcbe7a3c..5e72c445f3 100644
--- a/arch/arm/dts/k3-am62.dtsi
+++ b/arch/arm/dts/k3-am62.dtsi
@@ -8,9 +8,10 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
 #include <dt-bindings/soc/ti,sci_pm_domain.h>
 
+#include "k3-pinctrl.h"
+
 / {
 	model = "Texas Instruments K3 AM625 SoC";
 	compatible = "ti,am625";
@@ -80,6 +81,7 @@
 			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
 
 			 /* Wakeup Domain Range */
+			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
 			 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
 			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
 
@@ -90,14 +92,17 @@
 			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
 		};
 
-		cbass_wakeup: bus@2b000000 {
+		cbass_wakeup: bus@b00000 {
 			compatible = "simple-bus";
 			#address-cells = <2>;
 			#size-cells = <2>;
-			ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
+				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
 				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
 		};
 	};
+
+	#include "k3-am62-thermal.dtsi"
 };
 
 /* Now include the peripherals for each bus segments */
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
index 78df7cec3f..bf219226b9 100644
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -18,31 +18,6 @@
 		serial3 = &main_uart1;
 	};
 
-	chosen {
-		stdout-path = "serial2:115200n8";
-		tick-timer = &timer1;
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		/* 2G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
-		bootph-pre-ram;
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		secure_ddr: optee@9e800000 {
-			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
-			alignment = <0x1000>;
-			no-map;
-		};
-	};
-
 	a53_0: a53@0 {
 		compatible = "ti,am654-rproc";
 		reg = <0x00 0x00a90000 0x00 0x10>;
@@ -80,80 +55,44 @@
 	ti,secure-host;
 };
 
-&cbass_mcu {
-	mcu_esm: esm@4100000 {
-		compatible = "ti,j721e-esm";
-		reg = <0x0 0x4100000 0x0 0x1000>;
-		ti,esm-pins = <0>, <1>, <2>, <85>;
-		bootph-pre-ram;
-	};
+&mcu_esm {
+	bootph-pre-ram;
 };
 
-&cbass_main {
-	sa3_secproxy: secproxy@44880000 {
-		bootph-pre-ram;
-		compatible = "ti,am654-secure-proxy";
-		#mbox-cells = <1>;
-		reg-names = "rt", "scfg", "target_data";
-		reg = <0x00 0x44880000 0x00 0x20000>,
-		      <0x0 0x44860000 0x0 0x20000>,
-		      <0x0 0x43600000 0x0 0x10000>;
-	};
+&secure_proxy_sa3 {
+	bootph-pre-ram;
+	/* We require this for boot handshake */
+	status = "okay";
+};
+
+&main_esm {
+	bootph-pre-ram;
+};
 
+&cbass_main {
 	sysctrler: sysctrler {
 		compatible = "ti,am654-system-controller";
-		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>;
+		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
 		mbox-names = "tx", "rx", "boot_notify";
 		bootph-pre-ram;
 	};
-
-	main_esm: esm@420000 {
-		compatible = "ti,j721e-esm";
-		reg = <0x0 0x420000 0x0 0x1000>;
-		ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
-		bootph-pre-ram;
-	};
 };
 
-&mcu_pmx0 {
+&wkup_uart0_pins_default {
 	bootph-pre-ram;
-	wkup_uart0_pins_default: wkup-uart0-pins-default {
-		pinctrl-single,pins = <
-			AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
-			AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
-			AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
-			AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
-		>;
-		bootph-pre-ram;
-	};
 };
 
-&main_pmx0 {
+&main_uart1_pins_default {
 	bootph-pre-ram;
-	main_uart1_pins_default: main-uart1-pins-default {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
-			AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
-			AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
-			AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
-		>;
-		bootph-pre-ram;
-	};
 };
 
 /* WKUP UART0 is used for DM firmware logs */
 &wkup_uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_uart0_pins_default>;
-	status = "okay";
 	bootph-pre-ram;
 };
 
 /* Main UART1 is used for TIFS firmware logs */
 &main_uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart1_pins_default>;
-	status = "okay";
 	bootph-pre-ram;
 };
 
diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi
new file mode 100644
index 0000000000..a35d6418c2
--- /dev/null
+++ b/arch/arm/dts/k3-am625-sk-binman.dtsi
@@ -0,0 +1,463 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_AM625_R5_EVM
+
+&binman {
+	tiboot3-am62x-hs-evm.bin {
+		filename = "tiboot3-am62x-hs-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+				<&combined_dm_cfg>, <&sysfw_inner_cert>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl>;
+			content-sysfw = <&ti_fs_enc>;
+			content-sysfw-data = <&combined_tifs_cfg>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert>;
+			content-dm-data = <&combined_dm_cfg>;
+			load = <0x43c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x43c3a800>;
+		};
+		u_boot_spl: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_dm_cfg: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-am62x-hs-fs-evm.bin {
+		filename = "tiboot3-am62x-hs-fs-evm.bin";
+		symlink = "tiboot3.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+				<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl_fs>;
+			content-sysfw = <&ti_fs_enc_fs>;
+			content-sysfw-data = <&combined_tifs_cfg_fs>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+			content-dm-data = <&combined_dm_cfg_fs>;
+			load = <0x43c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x43c3a800>;
+		};
+		u_boot_spl_fs: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc_fs: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert_fs: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_dm_cfg_fs: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-am62x-gp-evm.bin {
+		filename = "tiboot3-am62x-gp-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
+				<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
+			combined;
+			dm-data;
+			content-sbl = <&u_boot_spl_unsigned>;
+			load = <0x43c00000>;
+			content-sysfw = <&ti_fs_gp>;
+			load-sysfw = <0x40000>;
+			content-sysfw-data = <&combined_tifs_cfg_gp>;
+			load-sysfw-data = <0x67000>;
+			content-dm-data = <&combined_dm_cfg_gp>;
+			load-dm-data = <0x43c3a800>;
+			sw-rev = <1>;
+			keyfile = "ti-degenerate-key.pem";
+		};
+		u_boot_spl_unsigned: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_gp: ti-fs-gp.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+
+	};
+};
+
+#endif
+
+#ifdef CONFIG_TARGET_AM625_A53_EVM
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_AM625_SK_DTB "spl/dts/k3-am625-sk.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define AM625_SK_DTB "u-boot.dtb"
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+		blob-ext {
+			filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+		};
+	};
+	ti-spl {
+		filename = "tispl.bin";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					ti-secure {
+						content = <&atf>;
+						keyfile = "custMpk.pem";
+					};
+					atf: atf-bl31 {
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					ti-secure {
+						content = <&tee>;
+						keyfile = "custMpk.pem";
+					};
+					tee: tee-os {
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					ti-secure {
+						content = <&dm>;
+						keyfile = "custMpk.pem";
+					};
+					dm: blob-ext {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_spl_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_spl_nodtb: blob-ext {
+						filename = SPL_NODTB;
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am625-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_am625_sk_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					spl_am625_sk_dtb: blob-ext {
+						filename = SPL_AM625_SK_DTB;
+					};
+
+				};
+
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am625-sk";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot {
+		filename = "u-boot.img";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for AM625 board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_nodtb: u-boot-nodtb {
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am625-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&am625_sk_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					am625_sk_dtb: blob-ext {
+						filename = AM625_SK_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am625-sk";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+
+			};
+		};
+	};
+};
+
+&binman {
+	ti-spl_unsigned {
+		filename = "tispl.bin_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					atf-bl31 {
+						filename = "bl31.bin";
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					tee-os {
+						filename = "tee-raw.bin";
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					blob-ext {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					blob {
+						filename = "spl/u-boot-spl-nodtb.bin";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am625-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = SPL_AM625_SK_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am625-sk";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot_unsigned {
+		filename = "u-boot.img_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for AM625 board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					blob {
+						filename = UBOOT_NODTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am625-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = AM625_SK_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am625-sk";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+#endif
diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
index 249155733a..c1685bc9ca 100644
--- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
@@ -4,10 +4,12 @@
  * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include "k3-am625-sk-binman.dtsi"
+
 / {
 	chosen {
 		stdout-path = "serial2:115200n8";
-		tick-timer = &timer1;
+		tick-timer = &main_timer0;
 	};
 
 	aliases {
@@ -19,16 +21,13 @@
 	};
 };
 
-&cbass_main{
+&cbass_main {
 	bootph-pre-ram;
+};
 
-	timer1: timer@2400000 {
-		compatible = "ti,omap5430-timer";
-		reg = <0x00 0x2400000 0x00 0x80>;
-		ti,timer-alwon;
-		clock-frequency = <25000000>;
-		bootph-pre-ram;
-	};
+&main_timer0 {
+	clock-frequency = <25000000>;
+	bootph-pre-ram;
 };
 
 &dmss {
@@ -75,10 +74,6 @@
 	bootph-pre-ram;
 };
 
-&main_uart1 {
-	bootph-pre-ram;
-};
-
 &cbass_mcu {
 	bootph-pre-ram;
 };
@@ -91,10 +86,6 @@
 	bootph-pre-ram;
 };
 
-&wkup_uart0 {
-	bootph-pre-ram;
-};
-
 &sdhci1 {
 	bootph-pre-ram;
 };
@@ -128,17 +119,7 @@
 };
 
 &cpsw3g {
-	reg = <0x0 0x8000000 0x0 0x200000>,
-	      <0x0 0x43000200 0x0 0x8>;
-	reg-names = "cpsw_nuss", "mac_efuse";
-	/delete-property/ ranges;
 	bootph-pre-ram;
-
-	cpsw-phy-sel@04044 {
-		compatible = "ti,am64-phy-gmii-sel";
-		reg = <0x0 0x00104044 0x0 0x8>;
-		bootph-pre-ram;
-	};
 };
 
 &cpsw_port1 {
diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts
index af5617ff44..3f9ef4053a 100644
--- a/arch/arm/dts/k3-am625-sk.dts
+++ b/arch/arm/dts/k3-am625-sk.dts
@@ -7,28 +7,19 @@
 
 /dts-v1/;
 
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am625.dtsi"
+#include "k3-am62x-sk-common.dtsi"
 
 / {
-	compatible =  "ti,am625-sk", "ti,am625";
+	compatible = "ti,am625-sk", "ti,am625";
 	model = "Texas Instruments AM625 SK";
 
-	aliases {
-		serial2 = &main_uart0;
-		mmc0 = &sdhci0;
-		mmc1 = &sdhci1;
-		mmc2 = &sdhci2;
-		spi0 = &ospi0;
-		ethernet0 = &cpsw_port1;
-		ethernet1 = &cpsw_port2;
-	};
-
-	chosen {
-		stdout-path = "serial2:115200n8";
-		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+	opp-table {
+		/* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
+		opp-1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-supported-hw = <0x01 0x0004>;
+			clock-latency-ns = <6000000>;
+		};
 	};
 
 	memory@80000000 {
@@ -38,39 +29,6 @@
 
 	};
 
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		ramoops@9ca00000 {
-			compatible = "ramoops";
-			reg = <0x00 0x9ca00000 0x00 0x00100000>;
-			record-size = <0x8000>;
-			console-size = <0x8000>;
-			ftrace-size = <0x00>;
-			pmsg-size = <0x8000>;
-		};
-
-		secure_tfa_ddr: tfa@9e780000 {
-			reg = <0x00 0x9e780000 0x00 0x80000>;
-			alignment = <0x1000>;
-			no-map;
-		};
-
-		secure_ddr: optee@9e800000 {
-			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
-			alignment = <0x1000>;
-			no-map;
-		};
-
-		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0x9db00000 0x00 0xc00000>;
-			no-map;
-		};
-	};
-
 	vmain_pd: regulator-0 {
 		/* TPS65988 PD CONTROLLER OUTPUT */
 		compatible = "regulator-fixed";
@@ -130,108 +88,20 @@
 			 <3300000 0x1>;
 	};
 
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&usr_led_pins_default>;
-
-		led-0 {
-			label = "am62-sk:green:heartbeat";
-			gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-			function = LED_FUNCTION_HEARTBEAT;
-			default-state = "off";
-		};
+	vcc_1v8: regulator-5 {
+		/* output of TPS6282518DMQ */
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_3v3_sys>;
+		regulator-always-on;
+		regulator-boot-on;
 	};
 };
 
 &main_pmx0 {
-	main_uart0_pins_default: main-uart0-pins-default {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
-			AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
-		>;
-	};
-
-	main_i2c0_pins_default: main-i2c0-pins-default {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
-			AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
-		>;
-	};
-
-	main_i2c1_pins_default: main-i2c1-pins-default {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
-			AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
-		>;
-	};
-
-	main_i2c2_pins_default: main-i2c2-pins-default {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
-			AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
-		>;
-	};
-
-	main_mmc0_pins_default: main-mmc0-pins-default {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
-			AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
-			AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
-			AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
-			AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
-			AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
-			AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
-			AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
-			AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
-			AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
-		>;
-	};
-
-	main_mmc1_pins_default: main-mmc1-pins-default {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
-			AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
-			AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
-			AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
-			AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
-			AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
-			AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
-		>;
-	};
-
-	usr_led_pins_default: usr-led-pins-default {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
-		>;
-	};
-
-	main_mdio1_pins_default: main-mdio1-pins-default {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
-			AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
-		>;
-	};
-
-	main_rgmii1_pins_default: main-rgmii1-pins-default {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
-			AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
-			AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
-			AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
-			AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
-			AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
-			AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
-			AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
-			AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
-			AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
-			AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
-			AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
-		>;
-	};
-
-	main_rgmii2_pins_default: main-rgmii2-pins-default {
+	main_rgmii2_pins_default: main-rgmii2-default-pins {
 		pinctrl-single,pins = <
 			AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
 			AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
@@ -248,7 +118,7 @@
 		>;
 	};
 
-	ospi0_pins_default: ospi0-pins-default {
+	ospi0_pins_default: ospi0-default-pins {
 		pinctrl-single,pins = <
 			AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
 			AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
@@ -264,77 +134,20 @@
 		>;
 	};
 
-	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
 		pinctrl-single,pins = <
 			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
 		>;
 	};
 
-	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
+	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
 		pinctrl-single,pins = <
 			AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
 		>;
 	};
 };
 
-&wkup_uart0 {
-	/* WKUP UART0 is used by DM firmware */
-	status = "reserved";
-};
-
-&mcu_uart0 {
-	status = "disabled";
-};
-
-&main_uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart0_pins_default>;
-};
-
-&main_uart1 {
-	/* Main UART1 is used by TIFS firmware */
-	status = "reserved";
-};
-
-&main_uart2 {
-	status = "disabled";
-};
-
-&main_uart3 {
-	status = "disabled";
-};
-
-&main_uart4 {
-	status = "disabled";
-};
-
-&main_uart5 {
-	status = "disabled";
-};
-
-&main_uart6 {
-	status = "disabled";
-};
-
-&mcu_i2c0 {
-	status = "disabled";
-};
-
-&wkup_i2c0 {
-	status = "disabled";
-};
-
-&main_i2c0 {
-	status = "disabled";
-	pinctrl-0 = <&main_i2c0_pins_default>;
-	clock-frequency = <400000>;
-};
-
 &main_i2c1 {
-	status = "disabled";
-	pinctrl-0 = <&main_i2c1_pins_default>;
-	clock-frequency = <400000>;
-
 	exp1: gpio@22 {
 		compatible = "ti,tca6424";
 		reg = <0x22>;
@@ -348,7 +161,7 @@
 				   "UART1_FET_BUF_EN", "WL_LT_EN",
 				   "GPIO_HDMI_RSTn", "CSI_GPIO1",
 				   "CSI_GPIO2", "PRU_3V3_EN",
-				   "HDMI_INTn", "TEST_GPIO2",
+				   "HDMI_INTn", "PD_I2C_IRQ",
 				   "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
 				   "MCASP1_FET_SEL", "UART1_FET_SEL",
 				   "TSINT#", "IO_EXP_TEST_LED";
@@ -363,41 +176,14 @@
 	};
 };
 
-&main_i2c2 {
-	status = "disabled";
-};
-
-&main_i2c3 {
-	status = "disabled";
-};
-
-&sdhci0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_mmc0_pins_default>;
-	ti,driver-strength-ohm = <50>;
-	disable-wp;
-};
-
 &sdhci1 {
-	/* SD/MMC */
 	vmmc-supply = <&vdd_mmc1>;
 	vqmmc-supply = <&vdd_sd_dv>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_mmc1_pins_default>;
-	ti,driver-strength-ohm = <50>;
-	disable-wp;
 };
 
 &cpsw3g {
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_mdio1_pins_default
-		     &main_rgmii1_pins_default
-		     &main_rgmii2_pins_default>;
-};
-
-&cpsw_port1 {
-	phy-mode = "rgmii-rxid";
-	phy-handle = <&cpsw3g_phy0>;
+	pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
 };
 
 &cpsw_port2 {
@@ -406,13 +192,6 @@
 };
 
 &cpsw3g_mdio {
-	cpsw3g_phy0: ethernet-phy@0 {
-		reg = <0>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-		ti,min-output-impedance;
-	};
-
 	cpsw3g_phy1: ethernet-phy@1 {
 		reg = <1>;
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
@@ -429,6 +208,7 @@
 };
 
 &ospi0 {
+	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&ospi0_pins_default>;
 
@@ -487,18 +267,6 @@
 	};
 };
 
-&ecap0 {
-	status = "disabled";
-};
-
-&ecap1 {
-	status = "disabled";
-};
-
-&ecap2 {
-	status = "disabled";
-};
-
-&main_mcan0 {
-	status = "disabled";
+&tlv320aic3106 {
+	DVDD-supply = <&vcc_1v8>;
 };
diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
new file mode 100644
index 0000000000..9bad4309b4
--- /dev/null
+++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
@@ -0,0 +1,2190 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This file was generated with the
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.08
+ * Fri Jun 09 2023 08:01:37 GMT+0200 (Central European Summer Time)
+ * DDR Type: LPDDR4
+ * F0 = 50MHz    F1 = NA     F2 = 800MHz
+ * Density (per channel): 16Gb
+ * Write DBI: Enable
+ * Number of Ranks: 1
+ */
+
+#define DDRSS_PLL_FHS_CNT 3
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
+
+#define DDRSS_CTL_0_DATA 0x00000B00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x00002710
+#define DDRSS_CTL_8_DATA 0x000186A0
+#define DDRSS_CTL_9_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_11_DATA 0x00027100
+#define DDRSS_CTL_12_DATA 0x00186A00
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000640
+#define DDRSS_CTL_15_DATA 0x00027100
+#define DDRSS_CTL_16_DATA 0x00186A00
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000640
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01010100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x0000000A
+#define DDRSS_CTL_24_DATA 0x000186A0
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00020200
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x08000010
+#define DDRSS_CTL_35_DATA 0x00002020
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x0000040C
+#define DDRSS_CTL_39_DATA 0x00000000
+#define DDRSS_CTL_40_DATA 0x0000081C
+#define DDRSS_CTL_41_DATA 0x00000000
+#define DDRSS_CTL_42_DATA 0x0000081C
+#define DDRSS_CTL_43_DATA 0x00000000
+#define DDRSS_CTL_44_DATA 0x05000804
+#define DDRSS_CTL_45_DATA 0x00000B00
+#define DDRSS_CTL_46_DATA 0x09090004
+#define DDRSS_CTL_47_DATA 0x00000204
+#define DDRSS_CTL_48_DATA 0x00370008
+#define DDRSS_CTL_49_DATA 0x09090024
+#define DDRSS_CTL_50_DATA 0x00001910
+#define DDRSS_CTL_51_DATA 0x00370008
+#define DDRSS_CTL_52_DATA 0x09090024
+#define DDRSS_CTL_53_DATA 0x09001910
+#define DDRSS_CTL_54_DATA 0x000A0A09
+#define DDRSS_CTL_55_DATA 0x0400036D
+#define DDRSS_CTL_56_DATA 0x09092004
+#define DDRSS_CTL_57_DATA 0x00000C0A
+#define DDRSS_CTL_58_DATA 0x060036D8
+#define DDRSS_CTL_59_DATA 0x09092006
+#define DDRSS_CTL_60_DATA 0x00000C0A
+#define DDRSS_CTL_61_DATA 0x060036D8
+#define DDRSS_CTL_62_DATA 0x03042006
+#define DDRSS_CTL_63_DATA 0x06050002
+#define DDRSS_CTL_64_DATA 0x10111011
+#define DDRSS_CTL_65_DATA 0x01010008
+#define DDRSS_CTL_66_DATA 0x0420200A
+#define DDRSS_CTL_67_DATA 0x04131304
+#define DDRSS_CTL_68_DATA 0x00001313
+#define DDRSS_CTL_69_DATA 0x00000101
+#define DDRSS_CTL_70_DATA 0x00000000
+#define DDRSS_CTL_71_DATA 0x01000000
+#define DDRSS_CTL_72_DATA 0x00130803
+#define DDRSS_CTL_73_DATA 0x00000059
+#define DDRSS_CTL_74_DATA 0x00000130
+#define DDRSS_CTL_75_DATA 0x00000610
+#define DDRSS_CTL_76_DATA 0x00000130
+#define DDRSS_CTL_77_DATA 0x00000610
+#define DDRSS_CTL_78_DATA 0x00000005
+#define DDRSS_CTL_79_DATA 0x0000000A
+#define DDRSS_CTL_80_DATA 0x00000004
+#define DDRSS_CTL_81_DATA 0x00000098
+#define DDRSS_CTL_82_DATA 0x000000BB
+#define DDRSS_CTL_83_DATA 0x00000098
+#define DDRSS_CTL_84_DATA 0x000000BB
+#define DDRSS_CTL_85_DATA 0x03004000
+#define DDRSS_CTL_86_DATA 0x00001201
+#define DDRSS_CTL_87_DATA 0x00060005
+#define DDRSS_CTL_88_DATA 0x00000006
+#define DDRSS_CTL_89_DATA 0x00000000
+#define DDRSS_CTL_90_DATA 0x05141408
+#define DDRSS_CTL_91_DATA 0x05030A05
+#define DDRSS_CTL_92_DATA 0x05030C06
+#define DDRSS_CTL_93_DATA 0x01030C06
+#define DDRSS_CTL_94_DATA 0x02010201
+#define DDRSS_CTL_95_DATA 0x00001401
+#define DDRSS_CTL_96_DATA 0x01360014
+#define DDRSS_CTL_97_DATA 0x01360136
+#define DDRSS_CTL_98_DATA 0x00000136
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x05010303
+#define DDRSS_CTL_101_DATA 0x0C040505
+#define DDRSS_CTL_102_DATA 0x06050203
+#define DDRSS_CTL_103_DATA 0x030C0605
+#define DDRSS_CTL_104_DATA 0x05060502
+#define DDRSS_CTL_105_DATA 0x03030306
+#define DDRSS_CTL_106_DATA 0x03010000
+#define DDRSS_CTL_107_DATA 0x00010000
+#define DDRSS_CTL_108_DATA 0x00000000
+#define DDRSS_CTL_109_DATA 0x01000000
+#define DDRSS_CTL_110_DATA 0x80104002
+#define DDRSS_CTL_111_DATA 0x00040003
+#define DDRSS_CTL_112_DATA 0x00040005
+#define DDRSS_CTL_113_DATA 0x00030000
+#define DDRSS_CTL_114_DATA 0x00050004
+#define DDRSS_CTL_115_DATA 0x00000004
+#define DDRSS_CTL_116_DATA 0x00040003
+#define DDRSS_CTL_117_DATA 0x00040005
+#define DDRSS_CTL_118_DATA 0x00000000
+#define DDRSS_CTL_119_DATA 0x00001640
+#define DDRSS_CTL_120_DATA 0x00001640
+#define DDRSS_CTL_121_DATA 0x00001640
+#define DDRSS_CTL_122_DATA 0x00001640
+#define DDRSS_CTL_123_DATA 0x00001640
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000026F
+#define DDRSS_CTL_126_DATA 0x00018400
+#define DDRSS_CTL_127_DATA 0x00018400
+#define DDRSS_CTL_128_DATA 0x00018400
+#define DDRSS_CTL_129_DATA 0x00018400
+#define DDRSS_CTL_130_DATA 0x00018400
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x00002A70
+#define DDRSS_CTL_133_DATA 0x00018400
+#define DDRSS_CTL_134_DATA 0x00018400
+#define DDRSS_CTL_135_DATA 0x00018400
+#define DDRSS_CTL_136_DATA 0x00018400
+#define DDRSS_CTL_137_DATA 0x00018400
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x00002A70
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x03050000
+#define DDRSS_CTL_157_DATA 0x03050305
+#define DDRSS_CTL_158_DATA 0x00000000
+#define DDRSS_CTL_159_DATA 0x08010000
+#define DDRSS_CTL_160_DATA 0x000E0808
+#define DDRSS_CTL_161_DATA 0x01000000
+#define DDRSS_CTL_162_DATA 0x0E080808
+#define DDRSS_CTL_163_DATA 0x00000000
+#define DDRSS_CTL_164_DATA 0x08080801
+#define DDRSS_CTL_165_DATA 0x0000080E
+#define DDRSS_CTL_166_DATA 0x00040003
+#define DDRSS_CTL_167_DATA 0x00000007
+#define DDRSS_CTL_168_DATA 0x00000000
+#define DDRSS_CTL_169_DATA 0x00000000
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x01000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x00001500
+#define DDRSS_CTL_177_DATA 0x0000100E
+#define DDRSS_CTL_178_DATA 0x00000002
+#define DDRSS_CTL_179_DATA 0x00000000
+#define DDRSS_CTL_180_DATA 0x00000001
+#define DDRSS_CTL_181_DATA 0x00000002
+#define DDRSS_CTL_182_DATA 0x00000C00
+#define DDRSS_CTL_183_DATA 0x00001000
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00001000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00001000
+#define DDRSS_CTL_188_DATA 0x00000000
+#define DDRSS_CTL_189_DATA 0x00000000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x0005000A
+#define DDRSS_CTL_193_DATA 0x0404000D
+#define DDRSS_CTL_194_DATA 0x0000000D
+#define DDRSS_CTL_195_DATA 0x005000A0
+#define DDRSS_CTL_196_DATA 0x060600C8
+#define DDRSS_CTL_197_DATA 0x000000C8
+#define DDRSS_CTL_198_DATA 0x005000A0
+#define DDRSS_CTL_199_DATA 0x060600C8
+#define DDRSS_CTL_200_DATA 0x000000C8
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000004
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000000
+#define DDRSS_CTL_208_DATA 0x00000024
+#define DDRSS_CTL_209_DATA 0x00000012
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x00000024
+#define DDRSS_CTL_212_DATA 0x00000012
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x00000004
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000024
+#define DDRSS_CTL_218_DATA 0x00000012
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x00000024
+#define DDRSS_CTL_221_DATA 0x00000012
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000000
+#define DDRSS_CTL_224_DATA 0x00000031
+#define DDRSS_CTL_225_DATA 0x000000B1
+#define DDRSS_CTL_226_DATA 0x000000B1
+#define DDRSS_CTL_227_DATA 0x00000031
+#define DDRSS_CTL_228_DATA 0x000000B1
+#define DDRSS_CTL_229_DATA 0x000000B1
+#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00000000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x46004646
+#define DDRSS_CTL_255_DATA 0x00002746
+#define DDRSS_CTL_256_DATA 0x00000027
+#define DDRSS_CTL_257_DATA 0x00000027
+#define DDRSS_CTL_258_DATA 0x00000027
+#define DDRSS_CTL_259_DATA 0x00000027
+#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_261_DATA 0x00000000
+#define DDRSS_CTL_262_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x0000000F
+#define DDRSS_CTL_264_DATA 0x0000000F
+#define DDRSS_CTL_265_DATA 0x0000000F
+#define DDRSS_CTL_266_DATA 0x0000000F
+#define DDRSS_CTL_267_DATA 0x0000000F
+#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_269_DATA 0x00000000
+#define DDRSS_CTL_270_DATA 0x00001000
+#define DDRSS_CTL_271_DATA 0x00000015
+#define DDRSS_CTL_272_DATA 0x00000015
+#define DDRSS_CTL_273_DATA 0x00000010
+#define DDRSS_CTL_274_DATA 0x00000015
+#define DDRSS_CTL_275_DATA 0x00000015
+#define DDRSS_CTL_276_DATA 0x00000020
+#define DDRSS_CTL_277_DATA 0x00010000
+#define DDRSS_CTL_278_DATA 0x00000100
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000101
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x0C181511
+#define DDRSS_CTL_291_DATA 0x00000304
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00020000
+#define DDRSS_CTL_306_DATA 0x00400100
+#define DDRSS_CTL_307_DATA 0x00080032
+#define DDRSS_CTL_308_DATA 0x01000200
+#define DDRSS_CTL_309_DATA 0x03200040
+#define DDRSS_CTL_310_DATA 0x00020018
+#define DDRSS_CTL_311_DATA 0x00400100
+#define DDRSS_CTL_312_DATA 0x00180320
+#define DDRSS_CTL_313_DATA 0x00030000
+#define DDRSS_CTL_314_DATA 0x00280028
+#define DDRSS_CTL_315_DATA 0x00000100
+#define DDRSS_CTL_316_DATA 0x01010000
+#define DDRSS_CTL_317_DATA 0x00000000
+#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_319_DATA 0x000FFF00
+#define DDRSS_CTL_320_DATA 0xFFFFFFFF
+#define DDRSS_CTL_321_DATA 0x00FFFF00
+#define DDRSS_CTL_322_DATA 0x0B000000
+#define DDRSS_CTL_323_DATA 0x0001FFFF
+#define DDRSS_CTL_324_DATA 0x01010101
+#define DDRSS_CTL_325_DATA 0x01010101
+#define DDRSS_CTL_326_DATA 0x00000118
+#define DDRSS_CTL_327_DATA 0x00000C01
+#define DDRSS_CTL_328_DATA 0x01000100
+#define DDRSS_CTL_329_DATA 0x00000000
+#define DDRSS_CTL_330_DATA 0x00000000
+#define DDRSS_CTL_331_DATA 0x01030303
+#define DDRSS_CTL_332_DATA 0x00000001
+#define DDRSS_CTL_333_DATA 0x00000000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x01000101
+#define DDRSS_CTL_372_DATA 0x01010001
+#define DDRSS_CTL_373_DATA 0x00010101
+#define DDRSS_CTL_374_DATA 0x01050503
+#define DDRSS_CTL_375_DATA 0x05020201
+#define DDRSS_CTL_376_DATA 0x08080C0C
+#define DDRSS_CTL_377_DATA 0x00080308
+#define DDRSS_CTL_378_DATA 0x000B030E
+#define DDRSS_CTL_379_DATA 0x000B0310
+#define DDRSS_CTL_380_DATA 0x0B0B0810
+#define DDRSS_CTL_381_DATA 0x01000000
+#define DDRSS_CTL_382_DATA 0x03020301
+#define DDRSS_CTL_383_DATA 0x04000102
+#define DDRSS_CTL_384_DATA 0x1B000004
+#define DDRSS_CTL_385_DATA 0x000000B2
+#define DDRSS_CTL_386_DATA 0x00000200
+#define DDRSS_CTL_387_DATA 0x00000200
+#define DDRSS_CTL_388_DATA 0x00000200
+#define DDRSS_CTL_389_DATA 0x00000200
+#define DDRSS_CTL_390_DATA 0x00000321
+#define DDRSS_CTL_391_DATA 0x000006F4
+#define DDRSS_CTL_392_DATA 0x03050202
+#define DDRSS_CTL_393_DATA 0x00260201
+#define DDRSS_CTL_394_DATA 0x00000C20
+#define DDRSS_CTL_395_DATA 0x00000200
+#define DDRSS_CTL_396_DATA 0x00000200
+#define DDRSS_CTL_397_DATA 0x00000200
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00003690
+#define DDRSS_CTL_400_DATA 0x00007940
+#define DDRSS_CTL_401_DATA 0x070D0402
+#define DDRSS_CTL_402_DATA 0x00260405
+#define DDRSS_CTL_403_DATA 0x00000C20
+#define DDRSS_CTL_404_DATA 0x00000200
+#define DDRSS_CTL_405_DATA 0x00000200
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00003690
+#define DDRSS_CTL_409_DATA 0x00007940
+#define DDRSS_CTL_410_DATA 0x070D0402
+#define DDRSS_CTL_411_DATA 0x00000405
+#define DDRSS_CTL_412_DATA 0x00000000
+#define DDRSS_CTL_413_DATA 0x0302000A
+#define DDRSS_CTL_414_DATA 0x01000500
+#define DDRSS_CTL_415_DATA 0x01010001
+#define DDRSS_CTL_416_DATA 0x00010001
+#define DDRSS_CTL_417_DATA 0x01010001
+#define DDRSS_CTL_418_DATA 0x02010000
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x02000201
+#define DDRSS_CTL_421_DATA 0x10100600
+#define DDRSS_CTL_422_DATA 0x00202020
+#define DDRSS_PI_0_DATA 0x00000B00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000002
+#define DDRSS_PI_12_DATA 0x00000005
+#define DDRSS_PI_13_DATA 0x00010001
+#define DDRSS_PI_14_DATA 0x08000000
+#define DDRSS_PI_15_DATA 0x00010300
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00010000
+#define DDRSS_PI_24_DATA 0x280A0001
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010000
+#define DDRSS_PI_27_DATA 0x00003200
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x00000000
+#define DDRSS_PI_30_DATA 0x01010102
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x00000000
+#define DDRSS_PI_34_DATA 0x00000001
+#define DDRSS_PI_35_DATA 0x000000AA
+#define DDRSS_PI_36_DATA 0x00000055
+#define DDRSS_PI_37_DATA 0x000000B5
+#define DDRSS_PI_38_DATA 0x0000004A
+#define DDRSS_PI_39_DATA 0x00000056
+#define DDRSS_PI_40_DATA 0x000000A9
+#define DDRSS_PI_41_DATA 0x000000A9
+#define DDRSS_PI_42_DATA 0x000000B5
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x00010100
+#define DDRSS_PI_46_DATA 0x00000015
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x01000000
+#define DDRSS_PI_54_DATA 0x03000000
+#define DDRSS_PI_55_DATA 0x00000000
+#define DDRSS_PI_56_DATA 0x00001701
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x0A0A140A
+#define DDRSS_PI_61_DATA 0x10020101
+#define DDRSS_PI_62_DATA 0x01000210
+#define DDRSS_PI_63_DATA 0x05000404
+#define DDRSS_PI_64_DATA 0x00010001
+#define DDRSS_PI_65_DATA 0x0001000E
+#define DDRSS_PI_66_DATA 0x01010100
+#define DDRSS_PI_67_DATA 0x00010000
+#define DDRSS_PI_68_DATA 0x00000034
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x0000FFFF
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x00000000
+#define DDRSS_PI_75_DATA 0x00000000
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x08000100
+#define DDRSS_PI_78_DATA 0x00020000
+#define DDRSS_PI_79_DATA 0x00010002
+#define DDRSS_PI_80_DATA 0x00000001
+#define DDRSS_PI_81_DATA 0x00020001
+#define DDRSS_PI_82_DATA 0x00020002
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000400
+#define DDRSS_PI_92_DATA 0x0A090B0C
+#define DDRSS_PI_93_DATA 0x04060708
+#define DDRSS_PI_94_DATA 0x01000005
+#define DDRSS_PI_95_DATA 0x00000800
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00010008
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x0000AA00
+#define DDRSS_PI_100_DATA 0x00000000
+#define DDRSS_PI_101_DATA 0x00010000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000008
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00010000
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x0000000A
+#define DDRSS_PI_137_DATA 0x000186A0
+#define DDRSS_PI_138_DATA 0x00000100
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010001
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00010000
+#define DDRSS_PI_160_DATA 0x00000004
+#define DDRSS_PI_161_DATA 0x00000000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00000800
+#define DDRSS_PI_165_DATA 0x00780078
+#define DDRSS_PI_166_DATA 0x00101001
+#define DDRSS_PI_167_DATA 0x00000034
+#define DDRSS_PI_168_DATA 0x00000043
+#define DDRSS_PI_169_DATA 0x00020043
+#define DDRSS_PI_170_DATA 0x02000200
+#define DDRSS_PI_171_DATA 0x00000004
+#define DDRSS_PI_172_DATA 0x0000080C
+#define DDRSS_PI_173_DATA 0x00081C00
+#define DDRSS_PI_174_DATA 0x001C0000
+#define DDRSS_PI_175_DATA 0x00000013
+#define DDRSS_PI_176_DATA 0x00000059
+#define DDRSS_PI_177_DATA 0x00000130
+#define DDRSS_PI_178_DATA 0x00000610
+#define DDRSS_PI_179_DATA 0x00000130
+#define DDRSS_PI_180_DATA 0x04000610
+#define DDRSS_PI_181_DATA 0x01010404
+#define DDRSS_PI_182_DATA 0x00001501
+#define DDRSS_PI_183_DATA 0x001D001D
+#define DDRSS_PI_184_DATA 0x01000100
+#define DDRSS_PI_185_DATA 0x00000100
+#define DDRSS_PI_186_DATA 0x00000000
+#define DDRSS_PI_187_DATA 0x05050503
+#define DDRSS_PI_188_DATA 0x01010C0C
+#define DDRSS_PI_189_DATA 0x01010101
+#define DDRSS_PI_190_DATA 0x000C0C0A
+#define DDRSS_PI_191_DATA 0x00000000
+#define DDRSS_PI_192_DATA 0x00000000
+#define DDRSS_PI_193_DATA 0x04000000
+#define DDRSS_PI_194_DATA 0x04020808
+#define DDRSS_PI_195_DATA 0x04040204
+#define DDRSS_PI_196_DATA 0x00090031
+#define DDRSS_PI_197_DATA 0x00110039
+#define DDRSS_PI_198_DATA 0x00110039
+#define DDRSS_PI_199_DATA 0x01010101
+#define DDRSS_PI_200_DATA 0x0002000D
+#define DDRSS_PI_201_DATA 0x000200C8
+#define DDRSS_PI_202_DATA 0x010000C8
+#define DDRSS_PI_203_DATA 0x000E000E
+#define DDRSS_PI_204_DATA 0x00C90100
+#define DDRSS_PI_205_DATA 0x010000C9
+#define DDRSS_PI_206_DATA 0x00C900C9
+#define DDRSS_PI_207_DATA 0x32103200
+#define DDRSS_PI_208_DATA 0x01013210
+#define DDRSS_PI_209_DATA 0x0A070601
+#define DDRSS_PI_210_DATA 0x0D09070D
+#define DDRSS_PI_211_DATA 0x0D09070D
+#define DDRSS_PI_212_DATA 0x000C000D
+#define DDRSS_PI_213_DATA 0x00001000
+#define DDRSS_PI_214_DATA 0x00000C00
+#define DDRSS_PI_215_DATA 0x00001000
+#define DDRSS_PI_216_DATA 0x00000C00
+#define DDRSS_PI_217_DATA 0x02001000
+#define DDRSS_PI_218_DATA 0x0016000D
+#define DDRSS_PI_219_DATA 0x001600C8
+#define DDRSS_PI_220_DATA 0x000000C8
+#define DDRSS_PI_221_DATA 0x00001900
+#define DDRSS_PI_222_DATA 0x32000056
+#define DDRSS_PI_223_DATA 0x06000101
+#define DDRSS_PI_224_DATA 0x001D0204
+#define DDRSS_PI_225_DATA 0x32120058
+#define DDRSS_PI_226_DATA 0x05000101
+#define DDRSS_PI_227_DATA 0x001D0408
+#define DDRSS_PI_228_DATA 0x32120058
+#define DDRSS_PI_229_DATA 0x05000101
+#define DDRSS_PI_230_DATA 0x00000408
+#define DDRSS_PI_231_DATA 0x05040900
+#define DDRSS_PI_232_DATA 0x00060900
+#define DDRSS_PI_233_DATA 0x00000315
+#define DDRSS_PI_234_DATA 0x20010004
+#define DDRSS_PI_235_DATA 0x0A0A0A03
+#define DDRSS_PI_236_DATA 0x13090000
+#define DDRSS_PI_237_DATA 0x10090011
+#define DDRSS_PI_238_DATA 0x0000315C
+#define DDRSS_PI_239_DATA 0x20030024
+#define DDRSS_PI_240_DATA 0x0C0A0C0C
+#define DDRSS_PI_241_DATA 0x13090000
+#define DDRSS_PI_242_DATA 0x10090011
+#define DDRSS_PI_243_DATA 0x0000315C
+#define DDRSS_PI_244_DATA 0x20030024
+#define DDRSS_PI_245_DATA 0x0C0A0C0C
+#define DDRSS_PI_246_DATA 0x00000000
+#define DDRSS_PI_247_DATA 0x000000B2
+#define DDRSS_PI_248_DATA 0x000006F4
+#define DDRSS_PI_249_DATA 0x00000C20
+#define DDRSS_PI_250_DATA 0x00007940
+#define DDRSS_PI_251_DATA 0x00000C20
+#define DDRSS_PI_252_DATA 0x00007940
+#define DDRSS_PI_253_DATA 0x01360014
+#define DDRSS_PI_254_DATA 0x03030136
+#define DDRSS_PI_255_DATA 0x00000003
+#define DDRSS_PI_256_DATA 0x00000000
+#define DDRSS_PI_257_DATA 0x05030503
+#define DDRSS_PI_258_DATA 0x00000503
+#define DDRSS_PI_259_DATA 0x00002710
+#define DDRSS_PI_260_DATA 0x000186A0
+#define DDRSS_PI_261_DATA 0x00000005
+#define DDRSS_PI_262_DATA 0x00000064
+#define DDRSS_PI_263_DATA 0x00000014
+#define DDRSS_PI_264_DATA 0x00027100
+#define DDRSS_PI_265_DATA 0x000186A0
+#define DDRSS_PI_266_DATA 0x00000005
+#define DDRSS_PI_267_DATA 0x00000640
+#define DDRSS_PI_268_DATA 0x00000136
+#define DDRSS_PI_269_DATA 0x00027100
+#define DDRSS_PI_270_DATA 0x000186A0
+#define DDRSS_PI_271_DATA 0x00000005
+#define DDRSS_PI_272_DATA 0x00000640
+#define DDRSS_PI_273_DATA 0x01000136
+#define DDRSS_PI_274_DATA 0x00320040
+#define DDRSS_PI_275_DATA 0x00010008
+#define DDRSS_PI_276_DATA 0x03200040
+#define DDRSS_PI_277_DATA 0x00010018
+#define DDRSS_PI_278_DATA 0x03200040
+#define DDRSS_PI_279_DATA 0x00000318
+#define DDRSS_PI_280_DATA 0x00280028
+#define DDRSS_PI_281_DATA 0x03040404
+#define DDRSS_PI_282_DATA 0x00000303
+#define DDRSS_PI_283_DATA 0x02020101
+#define DDRSS_PI_284_DATA 0x67676767
+#define DDRSS_PI_285_DATA 0x00000000
+#define DDRSS_PI_286_DATA 0x55000000
+#define DDRSS_PI_287_DATA 0x00000000
+#define DDRSS_PI_288_DATA 0x3C00005A
+#define DDRSS_PI_289_DATA 0x00005500
+#define DDRSS_PI_290_DATA 0x00005A00
+#define DDRSS_PI_291_DATA 0x0D100F3C
+#define DDRSS_PI_292_DATA 0x0003020E
+#define DDRSS_PI_293_DATA 0x00000001
+#define DDRSS_PI_294_DATA 0x01000000
+#define DDRSS_PI_295_DATA 0x00020201
+#define DDRSS_PI_296_DATA 0x00000000
+#define DDRSS_PI_297_DATA 0x00000000
+#define DDRSS_PI_298_DATA 0x00000004
+#define DDRSS_PI_299_DATA 0x00000000
+#define DDRSS_PI_300_DATA 0x00000031
+#define DDRSS_PI_301_DATA 0x00000000
+#define DDRSS_PI_302_DATA 0x00000000
+#define DDRSS_PI_303_DATA 0x00000000
+#define DDRSS_PI_304_DATA 0x00100F27
+#define DDRSS_PI_305_DATA 0x00000000
+#define DDRSS_PI_306_DATA 0x00000024
+#define DDRSS_PI_307_DATA 0x00000012
+#define DDRSS_PI_308_DATA 0x000000B1
+#define DDRSS_PI_309_DATA 0x00000000
+#define DDRSS_PI_310_DATA 0x00000000
+#define DDRSS_PI_311_DATA 0x46000000
+#define DDRSS_PI_312_DATA 0x00150F27
+#define DDRSS_PI_313_DATA 0x00000000
+#define DDRSS_PI_314_DATA 0x00000024
+#define DDRSS_PI_315_DATA 0x00000012
+#define DDRSS_PI_316_DATA 0x000000B1
+#define DDRSS_PI_317_DATA 0x00000000
+#define DDRSS_PI_318_DATA 0x00000000
+#define DDRSS_PI_319_DATA 0x46000000
+#define DDRSS_PI_320_DATA 0x00150F27
+#define DDRSS_PI_321_DATA 0x00000000
+#define DDRSS_PI_322_DATA 0x00000004
+#define DDRSS_PI_323_DATA 0x00000000
+#define DDRSS_PI_324_DATA 0x00000031
+#define DDRSS_PI_325_DATA 0x00000000
+#define DDRSS_PI_326_DATA 0x00000000
+#define DDRSS_PI_327_DATA 0x00000000
+#define DDRSS_PI_328_DATA 0x00100F27
+#define DDRSS_PI_329_DATA 0x00000000
+#define DDRSS_PI_330_DATA 0x00000024
+#define DDRSS_PI_331_DATA 0x00000012
+#define DDRSS_PI_332_DATA 0x000000B1
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x00000000
+#define DDRSS_PI_335_DATA 0x46000000
+#define DDRSS_PI_336_DATA 0x00150F27
+#define DDRSS_PI_337_DATA 0x00000000
+#define DDRSS_PI_338_DATA 0x00000024
+#define DDRSS_PI_339_DATA 0x00000012
+#define DDRSS_PI_340_DATA 0x000000B1
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x00000000
+#define DDRSS_PI_343_DATA 0x46000000
+#define DDRSS_PI_344_DATA 0x00150F27
+#define DDRSS_PHY_0_DATA 0x04F00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00030200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x01000000
+#define DDRSS_PHY_6_DATA 0x03000400
+#define DDRSS_PHY_7_DATA 0x00000001
+#define DDRSS_PHY_8_DATA 0x00000001
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x01010000
+#define DDRSS_PHY_12_DATA 0x00010000
+#define DDRSS_PHY_13_DATA 0x00C00001
+#define DDRSS_PHY_14_DATA 0x00CC0008
+#define DDRSS_PHY_15_DATA 0x00660601
+#define DDRSS_PHY_16_DATA 0x00000003
+#define DDRSS_PHY_17_DATA 0x00000000
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x0000AAAA
+#define DDRSS_PHY_20_DATA 0x00005555
+#define DDRSS_PHY_21_DATA 0x0000B5B5
+#define DDRSS_PHY_22_DATA 0x00004A4A
+#define DDRSS_PHY_23_DATA 0x00005656
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B7B7
+#define DDRSS_PHY_26_DATA 0x00004848
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x08000000
+#define DDRSS_PHY_30_DATA 0x0F000008
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x00E4E400
+#define DDRSS_PHY_33_DATA 0x00071020
+#define DDRSS_PHY_34_DATA 0x000C0020
+#define DDRSS_PHY_35_DATA 0x00062000
+#define DDRSS_PHY_36_DATA 0x00000000
+#define DDRSS_PHY_37_DATA 0x55555555
+#define DDRSS_PHY_38_DATA 0xAAAAAAAA
+#define DDRSS_PHY_39_DATA 0x55555555
+#define DDRSS_PHY_40_DATA 0xAAAAAAAA
+#define DDRSS_PHY_41_DATA 0x00005555
+#define DDRSS_PHY_42_DATA 0x01000100
+#define DDRSS_PHY_43_DATA 0x00800180
+#define DDRSS_PHY_44_DATA 0x00000001
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000000
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x041F07FF
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x01CC0B01
+#define DDRSS_PHY_75_DATA 0x1003CC0B
+#define DDRSS_PHY_76_DATA 0x20000140
+#define DDRSS_PHY_77_DATA 0x07FF0200
+#define DDRSS_PHY_78_DATA 0x0000DD01
+#define DDRSS_PHY_79_DATA 0x00100303
+#define DDRSS_PHY_80_DATA 0x00000000
+#define DDRSS_PHY_81_DATA 0x00000000
+#define DDRSS_PHY_82_DATA 0x00021000
+#define DDRSS_PHY_83_DATA 0x00100010
+#define DDRSS_PHY_84_DATA 0x00100010
+#define DDRSS_PHY_85_DATA 0x00100010
+#define DDRSS_PHY_86_DATA 0x00100010
+#define DDRSS_PHY_87_DATA 0x02020010
+#define DDRSS_PHY_88_DATA 0x51516041
+#define DDRSS_PHY_89_DATA 0x31C06000
+#define DDRSS_PHY_90_DATA 0x07AB0340
+#define DDRSS_PHY_91_DATA 0x0000C0C0
+#define DDRSS_PHY_92_DATA 0x04050000
+#define DDRSS_PHY_93_DATA 0x00000504
+#define DDRSS_PHY_94_DATA 0x42100010
+#define DDRSS_PHY_95_DATA 0x010C053E
+#define DDRSS_PHY_96_DATA 0x000F0C1D
+#define DDRSS_PHY_97_DATA 0x01000140
+#define DDRSS_PHY_98_DATA 0x007A0120
+#define DDRSS_PHY_99_DATA 0x00000C00
+#define DDRSS_PHY_100_DATA 0x000001CC
+#define DDRSS_PHY_101_DATA 0x20100200
+#define DDRSS_PHY_102_DATA 0x00000005
+#define DDRSS_PHY_103_DATA 0x56704132
+#define DDRSS_PHY_104_DATA 0x00000008
+#define DDRSS_PHY_105_DATA 0x034C034C
+#define DDRSS_PHY_106_DATA 0x034C034C
+#define DDRSS_PHY_107_DATA 0x034C034C
+#define DDRSS_PHY_108_DATA 0x034C034C
+#define DDRSS_PHY_109_DATA 0x0000034C
+#define DDRSS_PHY_110_DATA 0x00008000
+#define DDRSS_PHY_111_DATA 0x00800080
+#define DDRSS_PHY_112_DATA 0x00800080
+#define DDRSS_PHY_113_DATA 0x00800080
+#define DDRSS_PHY_114_DATA 0x00800080
+#define DDRSS_PHY_115_DATA 0x00800080
+#define DDRSS_PHY_116_DATA 0x00800080
+#define DDRSS_PHY_117_DATA 0x00800080
+#define DDRSS_PHY_118_DATA 0x00800080
+#define DDRSS_PHY_119_DATA 0x01800080
+#define DDRSS_PHY_120_DATA 0x01000000
+#define DDRSS_PHY_121_DATA 0x00000000
+#define DDRSS_PHY_122_DATA 0x00000000
+#define DDRSS_PHY_123_DATA 0x00080200
+#define DDRSS_PHY_124_DATA 0x00000000
+#define DDRSS_PHY_125_DATA 0x0000F0F0
+#define DDRSS_PHY_126_DATA 0x00000000
+#define DDRSS_PHY_127_DATA 0x00000000
+#define DDRSS_PHY_128_DATA 0x00000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00000000
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00000000
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04F00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01000000
+#define DDRSS_PHY_262_DATA 0x03000400
+#define DDRSS_PHY_263_DATA 0x00000001
+#define DDRSS_PHY_264_DATA 0x00000001
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x01010000
+#define DDRSS_PHY_268_DATA 0x00010000
+#define DDRSS_PHY_269_DATA 0x00C00001
+#define DDRSS_PHY_270_DATA 0x00CC0008
+#define DDRSS_PHY_271_DATA 0x00660601
+#define DDRSS_PHY_272_DATA 0x00000003
+#define DDRSS_PHY_273_DATA 0x00000000
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x0000AAAA
+#define DDRSS_PHY_276_DATA 0x00005555
+#define DDRSS_PHY_277_DATA 0x0000B5B5
+#define DDRSS_PHY_278_DATA 0x00004A4A
+#define DDRSS_PHY_279_DATA 0x00005656
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B7B7
+#define DDRSS_PHY_282_DATA 0x00004848
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x08000000
+#define DDRSS_PHY_286_DATA 0x0F000008
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x00E4E400
+#define DDRSS_PHY_289_DATA 0x00071020
+#define DDRSS_PHY_290_DATA 0x000C0020
+#define DDRSS_PHY_291_DATA 0x00062000
+#define DDRSS_PHY_292_DATA 0x00000000
+#define DDRSS_PHY_293_DATA 0x55555555
+#define DDRSS_PHY_294_DATA 0xAAAAAAAA
+#define DDRSS_PHY_295_DATA 0x55555555
+#define DDRSS_PHY_296_DATA 0xAAAAAAAA
+#define DDRSS_PHY_297_DATA 0x00005555
+#define DDRSS_PHY_298_DATA 0x01000100
+#define DDRSS_PHY_299_DATA 0x00800180
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000000
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x041F07FF
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x01CC0B01
+#define DDRSS_PHY_331_DATA 0x1003CC0B
+#define DDRSS_PHY_332_DATA 0x20000140
+#define DDRSS_PHY_333_DATA 0x07FF0200
+#define DDRSS_PHY_334_DATA 0x0000DD01
+#define DDRSS_PHY_335_DATA 0x00100303
+#define DDRSS_PHY_336_DATA 0x00000000
+#define DDRSS_PHY_337_DATA 0x00000000
+#define DDRSS_PHY_338_DATA 0x00021000
+#define DDRSS_PHY_339_DATA 0x00100010
+#define DDRSS_PHY_340_DATA 0x00100010
+#define DDRSS_PHY_341_DATA 0x00100010
+#define DDRSS_PHY_342_DATA 0x00100010
+#define DDRSS_PHY_343_DATA 0x02020010
+#define DDRSS_PHY_344_DATA 0x51516041
+#define DDRSS_PHY_345_DATA 0x31C06000
+#define DDRSS_PHY_346_DATA 0x07AB0340
+#define DDRSS_PHY_347_DATA 0x0000C0C0
+#define DDRSS_PHY_348_DATA 0x04050000
+#define DDRSS_PHY_349_DATA 0x00000504
+#define DDRSS_PHY_350_DATA 0x42100010
+#define DDRSS_PHY_351_DATA 0x010C053E
+#define DDRSS_PHY_352_DATA 0x000F0C1D
+#define DDRSS_PHY_353_DATA 0x01000140
+#define DDRSS_PHY_354_DATA 0x007A0120
+#define DDRSS_PHY_355_DATA 0x00000C00
+#define DDRSS_PHY_356_DATA 0x000001CC
+#define DDRSS_PHY_357_DATA 0x20100200
+#define DDRSS_PHY_358_DATA 0x00000005
+#define DDRSS_PHY_359_DATA 0x03415762
+#define DDRSS_PHY_360_DATA 0x00000008
+#define DDRSS_PHY_361_DATA 0x034C034C
+#define DDRSS_PHY_362_DATA 0x034C034C
+#define DDRSS_PHY_363_DATA 0x034C034C
+#define DDRSS_PHY_364_DATA 0x034C034C
+#define DDRSS_PHY_365_DATA 0x0000034C
+#define DDRSS_PHY_366_DATA 0x00008000
+#define DDRSS_PHY_367_DATA 0x00800080
+#define DDRSS_PHY_368_DATA 0x00800080
+#define DDRSS_PHY_369_DATA 0x00800080
+#define DDRSS_PHY_370_DATA 0x00800080
+#define DDRSS_PHY_371_DATA 0x00800080
+#define DDRSS_PHY_372_DATA 0x00800080
+#define DDRSS_PHY_373_DATA 0x00800080
+#define DDRSS_PHY_374_DATA 0x00800080
+#define DDRSS_PHY_375_DATA 0x01800080
+#define DDRSS_PHY_376_DATA 0x01000000
+#define DDRSS_PHY_377_DATA 0x00000000
+#define DDRSS_PHY_378_DATA 0x00000000
+#define DDRSS_PHY_379_DATA 0x00080200
+#define DDRSS_PHY_380_DATA 0x00000000
+#define DDRSS_PHY_381_DATA 0x0000F0F0
+#define DDRSS_PHY_382_DATA 0x00000000
+#define DDRSS_PHY_383_DATA 0x00000000
+#define DDRSS_PHY_384_DATA 0x00000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00000000
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00000000
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x00000000
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00000000
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x00000100
+#define DDRSS_PHY_518_DATA 0x00000200
+#define DDRSS_PHY_519_DATA 0x00000000
+#define DDRSS_PHY_520_DATA 0x00000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00400000
+#define DDRSS_PHY_524_DATA 0x00000080
+#define DDRSS_PHY_525_DATA 0x00DCBA98
+#define DDRSS_PHY_526_DATA 0x03000000
+#define DDRSS_PHY_527_DATA 0x00200000
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000000
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000000
+#define DDRSS_PHY_532_DATA 0x0000002A
+#define DDRSS_PHY_533_DATA 0x00000015
+#define DDRSS_PHY_534_DATA 0x00000015
+#define DDRSS_PHY_535_DATA 0x0000002A
+#define DDRSS_PHY_536_DATA 0x00000033
+#define DDRSS_PHY_537_DATA 0x0000000C
+#define DDRSS_PHY_538_DATA 0x0000000C
+#define DDRSS_PHY_539_DATA 0x00000033
+#define DDRSS_PHY_540_DATA 0x0A418820
+#define DDRSS_PHY_541_DATA 0x003F0000
+#define DDRSS_PHY_542_DATA 0x000F013F
+#define DDRSS_PHY_543_DATA 0x0000000F
+#define DDRSS_PHY_544_DATA 0x020002CC
+#define DDRSS_PHY_545_DATA 0x00030000
+#define DDRSS_PHY_546_DATA 0x00000300
+#define DDRSS_PHY_547_DATA 0x00000300
+#define DDRSS_PHY_548_DATA 0x00000300
+#define DDRSS_PHY_549_DATA 0x00000300
+#define DDRSS_PHY_550_DATA 0x00000300
+#define DDRSS_PHY_551_DATA 0x42080010
+#define DDRSS_PHY_552_DATA 0x0000803E
+#define DDRSS_PHY_553_DATA 0x00000003
+#define DDRSS_PHY_554_DATA 0x00000002
+#define DDRSS_PHY_555_DATA 0x00000000
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000000
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000000
+#define DDRSS_PHY_588_DATA 0x00000000
+#define DDRSS_PHY_589_DATA 0x00000000
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x00000000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000000
+#define DDRSS_PHY_596_DATA 0x00000000
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00000000
+#define DDRSS_PHY_600_DATA 0x00000000
+#define DDRSS_PHY_601_DATA 0x00000000
+#define DDRSS_PHY_602_DATA 0x00000000
+#define DDRSS_PHY_603_DATA 0x00000000
+#define DDRSS_PHY_604_DATA 0x00000000
+#define DDRSS_PHY_605_DATA 0x00000000
+#define DDRSS_PHY_606_DATA 0x00000000
+#define DDRSS_PHY_607_DATA 0x00000000
+#define DDRSS_PHY_608_DATA 0x00000000
+#define DDRSS_PHY_609_DATA 0x00000000
+#define DDRSS_PHY_610_DATA 0x00000000
+#define DDRSS_PHY_611_DATA 0x00000000
+#define DDRSS_PHY_612_DATA 0x00000000
+#define DDRSS_PHY_613_DATA 0x00000000
+#define DDRSS_PHY_614_DATA 0x00000000
+#define DDRSS_PHY_615_DATA 0x00000000
+#define DDRSS_PHY_616_DATA 0x00000000
+#define DDRSS_PHY_617_DATA 0x00000000
+#define DDRSS_PHY_618_DATA 0x00000000
+#define DDRSS_PHY_619_DATA 0x00000000
+#define DDRSS_PHY_620_DATA 0x00000000
+#define DDRSS_PHY_621_DATA 0x00000000
+#define DDRSS_PHY_622_DATA 0x00000000
+#define DDRSS_PHY_623_DATA 0x00000000
+#define DDRSS_PHY_624_DATA 0x00000000
+#define DDRSS_PHY_625_DATA 0x00000000
+#define DDRSS_PHY_626_DATA 0x00000000
+#define DDRSS_PHY_627_DATA 0x00000000
+#define DDRSS_PHY_628_DATA 0x00000000
+#define DDRSS_PHY_629_DATA 0x00000000
+#define DDRSS_PHY_630_DATA 0x00000000
+#define DDRSS_PHY_631_DATA 0x00000000
+#define DDRSS_PHY_632_DATA 0x00000000
+#define DDRSS_PHY_633_DATA 0x00000000
+#define DDRSS_PHY_634_DATA 0x00000000
+#define DDRSS_PHY_635_DATA 0x00000000
+#define DDRSS_PHY_636_DATA 0x00000000
+#define DDRSS_PHY_637_DATA 0x00000000
+#define DDRSS_PHY_638_DATA 0x00000000
+#define DDRSS_PHY_639_DATA 0x00000000
+#define DDRSS_PHY_640_DATA 0x00000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00000000
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00000000
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x00000000
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00000000
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x00000100
+#define DDRSS_PHY_774_DATA 0x00000200
+#define DDRSS_PHY_775_DATA 0x00000000
+#define DDRSS_PHY_776_DATA 0x00000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00400000
+#define DDRSS_PHY_780_DATA 0x00000080
+#define DDRSS_PHY_781_DATA 0x00DCBA98
+#define DDRSS_PHY_782_DATA 0x03000000
+#define DDRSS_PHY_783_DATA 0x00200000
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000000
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000000
+#define DDRSS_PHY_788_DATA 0x0000002A
+#define DDRSS_PHY_789_DATA 0x00000015
+#define DDRSS_PHY_790_DATA 0x00000015
+#define DDRSS_PHY_791_DATA 0x0000002A
+#define DDRSS_PHY_792_DATA 0x00000033
+#define DDRSS_PHY_793_DATA 0x0000000C
+#define DDRSS_PHY_794_DATA 0x0000000C
+#define DDRSS_PHY_795_DATA 0x00000033
+#define DDRSS_PHY_796_DATA 0x00000000
+#define DDRSS_PHY_797_DATA 0x00000000
+#define DDRSS_PHY_798_DATA 0x000F0000
+#define DDRSS_PHY_799_DATA 0x0000000F
+#define DDRSS_PHY_800_DATA 0x020002CC
+#define DDRSS_PHY_801_DATA 0x00030000
+#define DDRSS_PHY_802_DATA 0x00000300
+#define DDRSS_PHY_803_DATA 0x00000300
+#define DDRSS_PHY_804_DATA 0x00000300
+#define DDRSS_PHY_805_DATA 0x00000300
+#define DDRSS_PHY_806_DATA 0x00000300
+#define DDRSS_PHY_807_DATA 0x42080010
+#define DDRSS_PHY_808_DATA 0x0000803E
+#define DDRSS_PHY_809_DATA 0x00000003
+#define DDRSS_PHY_810_DATA 0x00000002
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000000
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000000
+#define DDRSS_PHY_844_DATA 0x00000000
+#define DDRSS_PHY_845_DATA 0x00000000
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x00000000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000000
+#define DDRSS_PHY_852_DATA 0x00000000
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00000000
+#define DDRSS_PHY_856_DATA 0x00000000
+#define DDRSS_PHY_857_DATA 0x00000000
+#define DDRSS_PHY_858_DATA 0x00000000
+#define DDRSS_PHY_859_DATA 0x00000000
+#define DDRSS_PHY_860_DATA 0x00000000
+#define DDRSS_PHY_861_DATA 0x00000000
+#define DDRSS_PHY_862_DATA 0x00000000
+#define DDRSS_PHY_863_DATA 0x00000000
+#define DDRSS_PHY_864_DATA 0x00000000
+#define DDRSS_PHY_865_DATA 0x00000000
+#define DDRSS_PHY_866_DATA 0x00000000
+#define DDRSS_PHY_867_DATA 0x00000000
+#define DDRSS_PHY_868_DATA 0x00000000
+#define DDRSS_PHY_869_DATA 0x00000000
+#define DDRSS_PHY_870_DATA 0x00000000
+#define DDRSS_PHY_871_DATA 0x00000000
+#define DDRSS_PHY_872_DATA 0x00000000
+#define DDRSS_PHY_873_DATA 0x00000000
+#define DDRSS_PHY_874_DATA 0x00000000
+#define DDRSS_PHY_875_DATA 0x00000000
+#define DDRSS_PHY_876_DATA 0x00000000
+#define DDRSS_PHY_877_DATA 0x00000000
+#define DDRSS_PHY_878_DATA 0x00000000
+#define DDRSS_PHY_879_DATA 0x00000000
+#define DDRSS_PHY_880_DATA 0x00000000
+#define DDRSS_PHY_881_DATA 0x00000000
+#define DDRSS_PHY_882_DATA 0x00000000
+#define DDRSS_PHY_883_DATA 0x00000000
+#define DDRSS_PHY_884_DATA 0x00000000
+#define DDRSS_PHY_885_DATA 0x00000000
+#define DDRSS_PHY_886_DATA 0x00000000
+#define DDRSS_PHY_887_DATA 0x00000000
+#define DDRSS_PHY_888_DATA 0x00000000
+#define DDRSS_PHY_889_DATA 0x00000000
+#define DDRSS_PHY_890_DATA 0x00000000
+#define DDRSS_PHY_891_DATA 0x00000000
+#define DDRSS_PHY_892_DATA 0x00000000
+#define DDRSS_PHY_893_DATA 0x00000000
+#define DDRSS_PHY_894_DATA 0x00000000
+#define DDRSS_PHY_895_DATA 0x00000000
+#define DDRSS_PHY_896_DATA 0x00000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00000000
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00000000
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x0000002A
+#define DDRSS_PHY_1045_DATA 0x00000015
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x0000002A
+#define DDRSS_PHY_1048_DATA 0x00000033
+#define DDRSS_PHY_1049_DATA 0x0000000C
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x00000033
+#define DDRSS_PHY_1052_DATA 0x2307B9AC
+#define DDRSS_PHY_1053_DATA 0x10000000
+#define DDRSS_PHY_1054_DATA 0x000F0000
+#define DDRSS_PHY_1055_DATA 0x0000000F
+#define DDRSS_PHY_1056_DATA 0x020002CC
+#define DDRSS_PHY_1057_DATA 0x00030000
+#define DDRSS_PHY_1058_DATA 0x00000300
+#define DDRSS_PHY_1059_DATA 0x00000300
+#define DDRSS_PHY_1060_DATA 0x00000300
+#define DDRSS_PHY_1061_DATA 0x00000300
+#define DDRSS_PHY_1062_DATA 0x00000300
+#define DDRSS_PHY_1063_DATA 0x42080010
+#define DDRSS_PHY_1064_DATA 0x0000803E
+#define DDRSS_PHY_1065_DATA 0x00000003
+#define DDRSS_PHY_1066_DATA 0x00000002
+#define DDRSS_PHY_1067_DATA 0x00000000
+#define DDRSS_PHY_1068_DATA 0x00000000
+#define DDRSS_PHY_1069_DATA 0x00000000
+#define DDRSS_PHY_1070_DATA 0x00000000
+#define DDRSS_PHY_1071_DATA 0x00000000
+#define DDRSS_PHY_1072_DATA 0x00000000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00010100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000000
+#define DDRSS_PHY_1286_DATA 0x00050000
+#define DDRSS_PHY_1287_DATA 0x04000000
+#define DDRSS_PHY_1288_DATA 0x00000055
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00000000
+#define DDRSS_PHY_1292_DATA 0x00000000
+#define DDRSS_PHY_1293_DATA 0x00002001
+#define DDRSS_PHY_1294_DATA 0x00004001
+#define DDRSS_PHY_1295_DATA 0x00020028
+#define DDRSS_PHY_1296_DATA 0x01010100
+#define DDRSS_PHY_1297_DATA 0x00000000
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x0F0F0E06
+#define DDRSS_PHY_1300_DATA 0x00010101
+#define DDRSS_PHY_1301_DATA 0x010F0004
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x00000000
+#define DDRSS_PHY_1304_DATA 0x00000064
+#define DDRSS_PHY_1305_DATA 0x00000000
+#define DDRSS_PHY_1306_DATA 0x00000000
+#define DDRSS_PHY_1307_DATA 0x01020103
+#define DDRSS_PHY_1308_DATA 0x0F020102
+#define DDRSS_PHY_1309_DATA 0x03030303
+#define DDRSS_PHY_1310_DATA 0x03030303
+#define DDRSS_PHY_1311_DATA 0x00041B42
+#define DDRSS_PHY_1312_DATA 0x00005201
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x00000000
+#define DDRSS_PHY_1318_DATA 0x00000000
+#define DDRSS_PHY_1319_DATA 0x07030101
+#define DDRSS_PHY_1320_DATA 0x00005400
+#define DDRSS_PHY_1321_DATA 0x000040A2
+#define DDRSS_PHY_1322_DATA 0x00024410
+#define DDRSS_PHY_1323_DATA 0x00004410
+#define DDRSS_PHY_1324_DATA 0x00004410
+#define DDRSS_PHY_1325_DATA 0x00004410
+#define DDRSS_PHY_1326_DATA 0x00004410
+#define DDRSS_PHY_1327_DATA 0x00004410
+#define DDRSS_PHY_1328_DATA 0x00004410
+#define DDRSS_PHY_1329_DATA 0x00004410
+#define DDRSS_PHY_1330_DATA 0x00004410
+#define DDRSS_PHY_1331_DATA 0x00004410
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000076
+#define DDRSS_PHY_1334_DATA 0x00000400
+#define DDRSS_PHY_1335_DATA 0x00000008
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x03000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x04102006
+#define DDRSS_PHY_1346_DATA 0x00041020
+#define DDRSS_PHY_1347_DATA 0x01C98C98
+#define DDRSS_PHY_1348_DATA 0x3F400000
+#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1350_DATA 0x0000001F
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000001
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x76543210
+#define DDRSS_PHY_1360_DATA 0x00040198
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00040700
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000002
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x0001F7C2
+#define DDRSS_PHY_1372_DATA 0x00020002
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00001142
+#define DDRSS_PHY_1375_DATA 0x03020000
+#define DDRSS_PHY_1376_DATA 0x00000080
+#define DDRSS_PHY_1377_DATA 0x03900390
+#define DDRSS_PHY_1378_DATA 0x03900390
+#define DDRSS_PHY_1379_DATA 0x03900390
+#define DDRSS_PHY_1380_DATA 0x03900390
+#define DDRSS_PHY_1381_DATA 0x03000300
+#define DDRSS_PHY_1382_DATA 0x03000300
+#define DDRSS_PHY_1383_DATA 0x00000300
+#define DDRSS_PHY_1384_DATA 0x00000300
+#define DDRSS_PHY_1385_DATA 0x00000300
+#define DDRSS_PHY_1386_DATA 0x00000300
+#define DDRSS_PHY_1387_DATA 0x3183BF77
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x0C000DFF
+#define DDRSS_PHY_1390_DATA 0x30000DFF
+#define DDRSS_PHY_1391_DATA 0x3F0DFF11
+#define DDRSS_PHY_1392_DATA 0x01990000
+#define DDRSS_PHY_1393_DATA 0x780DFFCC
+#define DDRSS_PHY_1394_DATA 0x00000C11
+#define DDRSS_PHY_1395_DATA 0x00018011
+#define DDRSS_PHY_1396_DATA 0x0089FF00
+#define DDRSS_PHY_1397_DATA 0x000C3F11
+#define DDRSS_PHY_1398_DATA 0x01990000
+#define DDRSS_PHY_1399_DATA 0x000C3F11
+#define DDRSS_PHY_1400_DATA 0x01990000
+#define DDRSS_PHY_1401_DATA 0x3F0DFF11
+#define DDRSS_PHY_1402_DATA 0x01990000
+#define DDRSS_PHY_1403_DATA 0x00018011
+#define DDRSS_PHY_1404_DATA 0x0089FF00
+#define DDRSS_PHY_1405_DATA 0x20040004
diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts
new file mode 100644
index 0000000000..0cae9c5777
--- /dev/null
+++ b/arch/arm/dts/k3-am625-verdin-r5.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Toradex Verdin AM62 dts file for R5 SPL
+ * Copyright 2023 Toradex - https://www.toradex.com/
+ */
+
+#include "k3-am625-verdin-wifi-dev.dts"
+#include "k3-am625-verdin-lpddr4-1600MTs.dtsi"
+#include "k3-am62-ddr.dtsi"
+
+#include "k3-am625-verdin-wifi-dev-u-boot.dtsi"
+
+/ {
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		/*
+		 * FIXME: Currently only the SPL running on the R5 has a clock
+		 * driver. As a workaround therefore move the assigned-clock
+		 * stuff required for our ETH_25MHz_CLK from the cpsw3g_mdio
+		 * node of the regular device tree to here (last one each in
+		 * below three lines, adding a <0> as spacing for parents).
+		 */
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>;
+		assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>;
+		assigned-clock-rates = <200000000>, <1200000000>, <25000000>;
+		clocks = <&k3_clks 61 0>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		ti,sci = <&dmsc>;
+		ti,sci-host-id = <10>;
+		ti,sci-proc-id = <32>;
+		bootph-pre-ram;
+	};
+
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 22>,
+			<&secure_proxy_main 23>;
+		ti,host-id = <36>;
+		ti,secure-host;
+		bootph-pre-ram;
+	};
+};
+
+&cbass_main {
+	sysctrler: sysctrler {
+		compatible = "ti,am654-system-controller";
+		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		bootph-pre-ram;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&main_esm {
+	bootph-pre-ram;
+};
+
+&mcu_esm {
+	bootph-pre-ram;
+};
+
+&secure_proxy_sa3 {
+	bootph-pre-ram;
+	/* We require this for boot handshake */
+	status = "okay";
+};
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
new file mode 100644
index 0000000000..089b2a5f5c
--- /dev/null
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
@@ -0,0 +1,532 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ */
+
+#include "k3-binman.dtsi"
+
+&custmpk_pem {
+	filename = "../../ti/keys/custMpk.pem";
+};
+
+&dkey_pem {
+	filename = "../../ti/keys/ti-degenerate-key.pem";
+};
+
+#ifndef CONFIG_ARM64
+
+&bcfg_yaml {
+	schema = "../../ti/common/schema.yaml";
+};
+
+&pcfg_yaml {
+	schema = "../../ti/common/schema.yaml";
+};
+
+&rcfg_yaml {
+	schema = "../../ti/common/schema.yaml";
+};
+
+&scfg_yaml {
+	schema = "../../ti/common/schema.yaml";
+};
+
+/* combined-tifs-cfg */
+
+&bcfg_yaml_tifs {
+	schema = "../../ti/common/schema.yaml";
+};
+
+&pcfg_yaml_tifs {
+	schema = "../../ti/common/schema.yaml";
+};
+
+&rcfg_yaml_tifs {
+	schema = "../../ti/common/schema.yaml";
+};
+
+&scfg_yaml_tifs {
+	schema = "../../ti/common/schema.yaml";
+};
+
+/* combined-dm-cfg */
+
+&pcfg_yaml_dm {
+	schema = "../../ti/common/schema.yaml";
+};
+
+&rcfg_yaml_dm {
+	schema = "../../ti/common/schema.yaml";
+};
+
+/* combined-sysfw-cfg */
+
+&bcfg_yaml_sysfw {
+	schema = "../../ti/common/schema.yaml";
+};
+
+&pcfg_yaml_sysfw {
+	schema = "../../ti/common/schema.yaml";
+};
+
+&rcfg_yaml_sysfw {
+	schema = "../../ti/common/schema.yaml";
+};
+
+&scfg_yaml_sysfw {
+	schema = "../../ti/common/schema.yaml";
+};
+
+#endif /* CONFIG_ARM64 */
+
+#ifdef CONFIG_TARGET_VERDIN_AM62_R5
+
+&binman {
+	tiboot3-am62x-hs-verdin.bin {
+		filename = "tiboot3-am62x-hs-verdin.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+				<&combined_dm_cfg>, <&sysfw_inner_cert>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl>;
+			content-sysfw = <&ti_fs_enc>;
+			content-sysfw-data = <&combined_tifs_cfg>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert>;
+			content-dm-data = <&combined_dm_cfg>;
+			load = <0x43c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x43c3a800>;
+		};
+		u_boot_spl: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_dm_cfg: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-am62x-hs-fs-verdin.bin {
+		filename = "tiboot3-am62x-hs-fs-verdin.bin";
+		symlink = "tiboot3.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+				<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl_fs>;
+			content-sysfw = <&ti_fs_enc_fs>;
+			content-sysfw-data = <&combined_tifs_cfg_fs>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+			content-dm-data = <&combined_dm_cfg_fs>;
+			load = <0x43c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x43c3a800>;
+		};
+		u_boot_spl_fs: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc_fs: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert_fs: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_dm_cfg_fs: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-am62x-gp-verdin.bin {
+		filename = "tiboot3-am62x-gp-verdin.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
+				<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
+			combined;
+			dm-data;
+			content-sbl = <&u_boot_spl_unsigned>;
+			load = <0x43c00000>;
+			content-sysfw = <&ti_fs_gp>;
+			load-sysfw = <0x40000>;
+			content-sysfw-data = <&combined_tifs_cfg_gp>;
+			load-sysfw-data = <0x67000>;
+			content-dm-data = <&combined_dm_cfg_gp>;
+			load-dm-data = <0x43c3a800>;
+			sw-rev = <1>;
+			keyfile = "ti-degenerate-key.pem";
+		};
+		u_boot_spl_unsigned: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_gp: ti-fs-gp.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+#endif /* CONFIG_TARGET_VERDIN_AM62_R5 */
+
+#ifdef CONFIG_TARGET_VERDIN_AM62_A53
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_VERDIN_AM62_DTB "spl/dts/k3-am625-verdin-wifi-dev.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define VERDIN_AM62_DTB "u-boot.dtb"
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+		blob-ext {
+			filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+		};
+	};
+	ti-spl {
+		filename = "tispl.bin";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					ti-secure {
+						content = <&atf>;
+						keyfile = "custMpk.pem";
+					};
+					atf: atf-bl31 {
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					ti-secure {
+						content = <&tee>;
+						keyfile = "custMpk.pem";
+					};
+					tee: tee-os {
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					ti-secure {
+						content = <&dm>;
+						keyfile = "custMpk.pem";
+					};
+					dm: blob-ext {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_spl_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_spl_nodtb: blob-ext {
+						filename = SPL_NODTB;
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am625-verdin-wifi-dev";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_verdin_am62_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					spl_verdin_am62_dtb: blob-ext {
+						filename = SPL_VERDIN_AM62_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am625-verdin-wifi-dev";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot {
+		filename = "u-boot.img";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for AM625 board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_nodtb: u-boot-nodtb {
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am625-verdin-wifi-dev";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&verdin_am62_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					verdin_am62_dtb: blob-ext {
+						filename = VERDIN_AM62_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am625-verdin-wifi-dev";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	ti-spl_unsigned {
+		filename = "tispl.bin_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					atf-bl31 {
+						filename = "bl31.bin";
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					tee-os {
+						filename = "tee-raw.bin";
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					blob-ext {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					blob {
+						filename = "spl/u-boot-spl-nodtb.bin";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am625-verdin-wifi-dev";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = SPL_VERDIN_AM62_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am625-verdin-wifi-dev";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot_unsigned {
+		filename = "u-boot.img_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for AM625 board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					blob {
+						filename = UBOOT_NODTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am625-verdin-wifi-dev";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = VERDIN_AM62_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am625-verdin-wifi-dev";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+#endif /* CONFIG_TARGET_VERDIN_AM62_A53 */
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
new file mode 100644
index 0000000000..5d564603eb
--- /dev/null
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ */
+
+#include "k3-am625-verdin-wifi-dev-binman.dtsi"
+
+/ {
+	aliases {
+		eeprom0 = &eeprom_module;
+		eeprom1 = &eeprom_carrier_board;
+		eeprom2 = &eeprom_display_adapter;
+	};
+
+	chosen {
+		tick-timer = &main_timer0;
+	};
+
+	memory@80000000 {
+		bootph-pre-ram;
+	};
+};
+
+&cbass_main {
+	bootph-pre-ram;
+
+	timer@2400000 {
+		clock-frequency = <25000000>;
+		bootph-pre-ram;
+	};
+};
+
+&cbass_mcu {
+	bootph-pre-ram;
+};
+
+&cbass_wakeup {
+	bootph-pre-ram;
+};
+
+&chipid {
+	bootph-pre-ram;
+};
+
+&cpsw3g {
+	bootph-pre-ram;
+};
+
+&cpsw3g_phy0 {
+	bootph-pre-ram;
+};
+
+&cpsw3g_phy1 {
+	bootph-pre-ram;
+};
+
+&cpsw_port1 {
+	bootph-pre-ram;
+};
+
+&cpsw_port2 {
+	bootph-pre-ram;
+};
+
+/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
+&cpsw3g_mdio {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+	bootph-pre-ram;
+};
+
+&dmsc {
+	bootph-pre-ram;
+
+	k3_sysreset: sysreset-controller {
+		compatible = "ti,sci-sysreset";
+		bootph-pre-ram;
+	};
+};
+
+&dmss {
+	bootph-pre-ram;
+};
+
+&fss {
+	bootph-pre-ram;
+};
+
+&k3_clks {
+	bootph-pre-ram;
+};
+
+&k3_pds {
+	bootph-pre-ram;
+};
+
+&k3_reset {
+	bootph-pre-ram;
+};
+
+&main_gpio0 {
+	bootph-pre-ram;
+};
+
+/* On-module I2C - PMIC_I2C */
+&main_i2c0 {
+	eeprom_module: eeprom@50 {
+		compatible = "i2c-eeprom";
+		pagesize = <16>;
+		reg = <0x50>;
+	};
+};
+
+/* Verdin I2C_1 */
+&main_i2c1 {
+	/* EEPROM on display adapter (MIPI DSI Display Adapter) */
+	eeprom_display_adapter: eeprom@50 {
+		compatible = "i2c-eeprom";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+
+	/* EEPROM on carrier board */
+	eeprom_carrier_board: eeprom@57 {
+		compatible = "i2c-eeprom";
+		reg = <0x57>;
+		pagesize = <16>;
+	};
+};
+
+&main_pmx0 {
+	bootph-pre-ram;
+};
+
+/* Verdin UART_3, used as the Linux console */
+&main_uart0 {
+	bootph-pre-ram;
+};
+
+/* Verdin UART_1 */
+&main_uart1 {
+	bootph-pre-ram;
+};
+
+&mcu_pmx0 {
+	bootph-pre-ram;
+};
+
+&pinctrl_ctrl_sleep_moci {
+	bootph-pre-ram;
+};
+
+&pinctrl_i2c0 {
+	bootph-pre-ram;
+};
+
+&pinctrl_i2c1 {
+	bootph-pre-ram;
+};
+
+&pinctrl_sdhci0 {
+	bootph-pre-ram;
+};
+
+&pinctrl_uart0 {
+	bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+	bootph-pre-ram;
+};
+
+&pinctrl_wkup_uart0 {
+	bootph-pre-ram;
+};
+
+&sdhci0 {
+	bootph-pre-ram;
+};
+
+&sdhci2 {
+	status = "disabled";
+};
+
+&secure_proxy_main {
+	bootph-pre-ram;
+};
+
+&verdin_ctrl_sleep_moci {
+	bootph-pre-ram;
+};
+
+&wkup_conf {
+	bootph-pre-ram;
+};
+
+/* Verdin UART_2 */
+&wkup_uart0 {
+	bootph-pre-ram;
+};
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev.dts b/arch/arm/dts/k3-am625-verdin-wifi-dev.dts
new file mode 100644
index 0000000000..4b657d6d3e
--- /dev/null
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ * https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+ */
+
+/dts-v1/;
+
+#include "k3-am625.dtsi"
+#include "k3-am62-verdin.dtsi"
+#include "k3-am62-verdin-wifi.dtsi"
+#include "k3-am62-verdin-dev.dtsi"
+
+/ {
+	model = "Toradex Verdin AM62 WB on Verdin Development Board";
+	compatible = "toradex,verdin-am62-wifi-dev",
+		     "toradex,verdin-am62-wifi",
+		     "toradex,verdin-am62",
+		     "ti,am625";
+};
diff --git a/arch/arm/dts/k3-am625.dtsi b/arch/arm/dts/k3-am625.dtsi
index 887f31c23f..4193c2b3ee 100644
--- a/arch/arm/dts/k3-am625.dtsi
+++ b/arch/arm/dts/k3-am625.dtsi
@@ -48,6 +48,8 @@
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&L2_0>;
+			operating-points-v2 = <&a53_opp_table>;
+			clocks = <&k3_clks 135 0>;
 		};
 
 		cpu1: cpu@1 {
@@ -62,6 +64,8 @@
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&L2_0>;
+			operating-points-v2 = <&a53_opp_table>;
+			clocks = <&k3_clks 136 0>;
 		};
 
 		cpu2: cpu@2 {
@@ -76,6 +80,8 @@
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&L2_0>;
+			operating-points-v2 = <&a53_opp_table>;
+			clocks = <&k3_clks 137 0>;
 		};
 
 		cpu3: cpu@3 {
@@ -90,13 +96,59 @@
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&L2_0>;
+			operating-points-v2 = <&a53_opp_table>;
+			clocks = <&k3_clks 138 0>;
+		};
+	};
+
+	a53_opp_table: opp-table {
+		compatible = "operating-points-v2-ti-cpu";
+		opp-shared;
+		syscon = <&wkup_conf>;
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-supported-hw = <0x01 0x0007>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-supported-hw = <0x01 0x0007>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-supported-hw = <0x01 0x0007>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-supported-hw = <0x01 0x0007>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-supported-hw = <0x01 0x0006>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-1250000000 {
+			opp-hz = /bits/ 64 <1250000000>;
+			opp-supported-hw = <0x01 0x0004>;
+			clock-latency-ns = <6000000>;
+			opp-suspend;
 		};
 	};
 
 	L2_0: l2-cache0 {
 		compatible = "cache";
+		cache-unified;
 		cache-level = <2>;
-		cache-size = <0x40000>;
+		cache-size = <0x80000>;
 		cache-line-size = <64>;
 		cache-sets = <512>;
 	};
diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi
new file mode 100644
index 0000000000..de09430d93
--- /dev/null
+++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi
@@ -0,0 +1,466 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_AM62A7_R5_EVM
+
+&rcfg_yaml_tifs {
+	config = "tifs-rm-cfg.yaml";
+};
+
+&binman {
+	tiboot3-am62ax-hs-evm.bin {
+		filename = "tiboot3-am62ax-hs-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+				<&combined_dm_cfg>, <&sysfw_inner_cert>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl>;
+			content-sysfw = <&ti_fs_enc>;
+			content-sysfw-data = <&combined_tifs_cfg>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert>;
+			content-dm-data = <&combined_dm_cfg>;
+			load = <0x43c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x43c3a800>;
+		};
+		u_boot_spl: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_dm_cfg: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-am62ax-hs-fs-evm.bin {
+		filename = "tiboot3-am62ax-hs-fs-evm.bin";
+		symlink = "tiboot3.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+				<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl_fs>;
+			content-sysfw = <&ti_fs_enc_fs>;
+			content-sysfw-data = <&combined_tifs_cfg_fs>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+			content-dm-data = <&combined_dm_cfg_fs>;
+			load = <0x43c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x43c3a800>;
+		};
+		u_boot_spl_fs: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc_fs: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert_fs: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_dm_cfg_fs: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-am62ax-gp-evm.bin {
+		filename = "tiboot3-am62ax-gp-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
+				<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
+			combined;
+			dm-data;
+			content-sbl = <&u_boot_spl_unsigned>;
+			load = <0x43c00000>;
+			content-sysfw = <&ti_fs_gp>;
+			load-sysfw = <0x40000>;
+			content-sysfw-data = <&combined_tifs_cfg_gp>;
+			load-sysfw-data = <0x67000>;
+			content-dm-data = <&combined_dm_cfg_gp>;
+			load-dm-data = <0x43c3a800>;
+			sw-rev = <1>;
+			keyfile = "ti-degenerate-key.pem";
+		};
+		u_boot_spl_unsigned: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_gp: ti-fs-gp.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+#endif
+
+#ifdef CONFIG_TARGET_AM62A7_A53_EVM
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_AM62A7_SK_DTB "spl/dts/k3-am62a7-sk.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define AM62A7_SK_DTB "u-boot.dtb"
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+		blob-ext {
+			filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+		};
+	};
+	ti-spl {
+		filename = "tispl.bin";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					ti-secure {
+						content = <&atf>;
+						keyfile = "custMpk.pem";
+					};
+					atf: atf-bl31 {
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					ti-secure {
+						content = <&tee>;
+						keyfile = "custMpk.pem";
+					};
+					tee: tee-os {
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					ti-secure {
+						content = <&dm>;
+						keyfile = "custMpk.pem";
+					};
+					dm: blob-ext {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_spl_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_spl_nodtb: blob-ext {
+						filename = SPL_NODTB;
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am62a7-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_am62a7_sk_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					spl_am62a7_sk_dtb: blob-ext {
+						filename = SPL_AM62A7_SK_DTB;
+					};
+
+				};
+
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am62a7-sk";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot {
+		filename = "u-boot.img";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for AM62Ax board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_nodtb: u-boot-nodtb {
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am62a7-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&am62a7_sk_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					am62a7_sk_dtb: blob-ext {
+						filename = AM62A7_SK_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am62a7-sk";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+
+			};
+		};
+	};
+};
+
+&binman {
+	ti-spl_unsigned {
+		filename = "tispl.bin_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					atf-bl31 {
+						filename = "bl31.bin";
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					tee-os {
+						filename = "tee-raw.bin";
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					blob-ext {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					blob {
+						filename = "spl/u-boot-spl-nodtb.bin";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am62a7-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = SPL_AM62A7_SK_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am62a7-sk";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot_unsigned {
+		filename = "u-boot.img_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for AM62Ax board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					blob {
+						filename = UBOOT_NODTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am62a7-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = AM62A7_SK_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am62a7-sk";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+#endif
diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts
index cc4b179e27..bbbd9e51d6 100644
--- a/arch/arm/dts/k3-am62a7-r5-sk.dts
+++ b/arch/arm/dts/k3-am62a7-r5-sk.dts
@@ -7,6 +7,7 @@
 #include "k3-am62a7-sk.dts"
 #include "k3-am62a-ddr-1866mhz-32bit.dtsi"
 #include "k3-am62a-ddr.dtsi"
+#include "k3-am62a-sk-binman.dtsi"
 
 #include "k3-am62a7-sk-u-boot.dtsi"
 
diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts
index b08a083d72..270e669f65 100644
--- a/arch/arm/dts/k3-am62a7-sk.dts
+++ b/arch/arm/dts/k3-am62a7-sk.dts
@@ -10,6 +10,7 @@
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 #include "k3-am62a7.dtsi"
+#include "k3-am62a-sk-binman.dtsi"
 
 / {
 	compatible =  "ti,am62a7-sk", "ti,am62a7";
diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi
new file mode 100644
index 0000000000..34c8ffc553
--- /dev/null
+++ b/arch/arm/dts/k3-am62x-sk-common.dtsi
@@ -0,0 +1,412 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common dtsi for AM62x SK and derivatives
+ *
+ * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-am625.dtsi"
+
+/ {
+	aliases {
+		serial2 = &main_uart0;
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
+		mmc2 = &sdhci2;
+		spi0 = &ospi0;
+		ethernet0 = &cpsw_port1;
+		ethernet1 = &cpsw_port2;
+		usb0 = &usb0;
+		usb1 = &usb1;
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 2G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ramoops@9ca00000 {
+			compatible = "ramoops";
+			reg = <0x00 0x9ca00000 0x00 0x00100000>;
+			record-size = <0x8000>;
+			console-size = <0x8000>;
+			ftrace-size = <0x00>;
+			pmsg-size = <0x8000>;
+		};
+
+		secure_tfa_ddr: tfa@9e780000 {
+			reg = <0x00 0x9e780000 0x00 0x80000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9db00000 0x00 0xc00000>;
+			no-map;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usr_led_pins_default>;
+
+		led-0 {
+			label = "am62-sk:green:heartbeat";
+			gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			function = LED_FUNCTION_HEARTBEAT;
+			default-state = "off";
+		};
+	};
+
+	tlv320_mclk: clk-0 {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12288000>;
+	};
+
+	codec_audio: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "AM62x-SKEVM";
+		simple-audio-card,widgets =
+			"Headphone",	"Headphone Jack",
+			"Line",		"Line In",
+			"Microphone",	"Microphone Jack";
+		simple-audio-card,routing =
+			"Headphone Jack",	"HPLOUT",
+			"Headphone Jack",	"HPROUT",
+			"LINE1L",		"Line In",
+			"LINE1R",		"Line In",
+			"MIC3R",		"Microphone Jack",
+			"Microphone Jack",	"Mic Bias";
+		simple-audio-card,format = "dsp_b";
+		simple-audio-card,bitclock-master = <&sound_master>;
+		simple-audio-card,frame-master = <&sound_master>;
+		simple-audio-card,bitclock-inversion;
+
+		simple-audio-card,cpu {
+			sound-dai = <&mcasp1>;
+		};
+
+		sound_master: simple-audio-card,codec {
+			sound-dai = <&tlv320aic3106>;
+			clocks = <&tlv320_mclk>;
+		};
+	};
+};
+
+&main_pmx0 {
+	/* First pad number is ALW package and second is AMC package */
+	main_uart0_pins_default: main-uart0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */
+			AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */
+		>;
+	};
+
+	main_uart1_pins_default: main-uart1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */
+			AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */
+			AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19/D15) MCASP0_AFSR.UART1_RXD */
+			AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_ACLKR.UART1_TXD */
+		>;
+	};
+
+	main_i2c0_pins_default: main-i2c0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */
+			AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */
+		>;
+	};
+
+	main_i2c1_pins_default: main-i2c1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */
+			AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */
+		>;
+	};
+
+	main_i2c2_pins_default: main-i2c2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */
+			AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */
+		>;
+	};
+
+	main_mmc0_pins_default: main-mmc0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */
+			AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */
+			AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2/V2) MMC0_DAT0 */
+			AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1/V1) MMC0_DAT1 */
+			AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3/W2) MMC0_DAT2 */
+			AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4/W1) MMC0_DAT3 */
+			AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2/Y2) MMC0_DAT4 */
+			AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1/W3) MMC0_DAT5 */
+			AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2/W4) MMC0_DAT6 */
+			AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */
+		>;
+	};
+
+	main_mmc1_pins_default: main-mmc1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */
+			AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */
+			AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22/A19) MMC1_DAT0 */
+			AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21/B19) MMC1_DAT1 */
+			AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21/B20) MMC1_DAT2 */
+			AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22/C19) MMC1_DAT3 */
+			AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17/C15) MMC1_SDCD */
+		>;
+	};
+
+	usr_led_pins_default: usr-led-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */
+		>;
+	};
+
+	main_mdio1_pins_default: main-mdio1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */
+			AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */
+		>;
+	};
+
+	main_rgmii1_pins_default: main-rgmii1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */
+			AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */
+			AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16/AA17) RGMII1_RD2 */
+			AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15/Y15) RGMII1_RD3 */
+			AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17/AA16) RGMII1_RXC */
+			AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17/W14) RGMII1_RX_CTL */
+			AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20/U14) RGMII1_TD0 */
+			AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20/AA19) RGMII1_TD1 */
+			AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18/Y17) RGMII1_TD2 */
+			AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18/AA18) RGMII1_TD3 */
+			AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19/W16) RGMII1_TXC */
+			AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */
+		>;
+	};
+
+	main_usb1_pins_default: main-usb1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */
+		>;
+	};
+
+	main_mcasp1_pins_default: main-mcasp1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24/K17) GPMC0_BE0N_CLE.MCASP1_ACLKX */
+			AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23/P21) GPMC0_WAIT0.MCASP1_AFSX */
+			AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25/J17) GPMC0_WEN.MCASP1_AXR0 */
+			AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */
+		>;
+	};
+};
+
+&mcu_pmx0 {
+	wkup_uart0_pins_default: wkup-uart0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */
+			AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */
+			AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4/B5) WKUP_UART0_RXD */
+			AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */
+		>;
+	};
+};
+
+&wkup_uart0 {
+	/* WKUP UART0 is used by DM firmware */
+	status = "reserved";
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&main_uart0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+&main_uart1 {
+	/* Main UART1 is used by TIFS firmware */
+	status = "reserved";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart1_pins_default>;
+};
+
+&main_i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
+
+	eeprom@51 {
+		/* AT24C512C-MAHM-T or M24512-DFMC6TG */
+		compatible = "atmel,24c512";
+		reg = <0x51>;
+	};
+
+	typec_pd0: tps6598x@3f {
+		compatible = "ti,tps6598x";
+		reg = <0x3f>;
+
+		connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			self-powered;
+			data-role = "dual";
+			power-role = "sink";
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					usb_con_hs: endpoint {
+						remote-endpoint = <&usb0_hs_ep>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&main_i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c1_pins_default>;
+	clock-frequency = <400000>;
+
+	tlv320aic3106: audio-codec@1b {
+		#sound-dai-cells = <0>;
+		compatible = "ti,tlv320aic3106";
+		reg = <0x1b>;
+		ai3x-micbias-vg = <1>;	/* 2.0V */
+
+		/* Regulators */
+		AVDD-supply = <&vcc_3v3_sys>;
+		IOVDD-supply = <&vcc_3v3_sys>;
+		DRVDD-supply = <&vcc_3v3_sys>;
+	};
+};
+
+&sdhci0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mmc0_pins_default>;
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+};
+
+&sdhci1 {
+	/* SD/MMC */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mmc1_pins_default>;
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+};
+
+&cpsw3g {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_rgmii1_pins_default>;
+};
+
+&cpsw_port1 {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw3g_mdio {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mdio1_pins_default>;
+
+	cpsw3g_phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+};
+
+&mailbox0_cluster0 {
+	mbox_m4_0: mbox-m4-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&usbss0 {
+	status = "okay";
+	ti,vbus-divider;
+};
+
+&usbss1 {
+	status = "okay";
+	ti,vbus-divider;
+};
+
+&usb0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	usb-role-switch;
+
+	port@0 {
+		reg = <0>;
+		usb0_hs_ep: endpoint {
+		    remote-endpoint = <&usb_con_hs>;
+	       };
+	};
+};
+
+&usb1 {
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_usb1_pins_default>;
+};
+
+&mcasp1 {
+	status = "okay";
+	#sound-dai-cells = <0>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcasp1_pins_default>;
+
+	op-mode = <0>;          /* MCASP_IIS_MODE */
+	tdm-slots = <2>;
+
+	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+	       1 0 2 0
+	       0 0 0 0
+	       0 0 0 0
+	       0 0 0 0
+	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
+};
diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
index 64857b0909..73577e8cfd 100644
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include "k3-am64x-binman.dtsi"
+
 / {
 	chosen {
 		stdout-path = "serial2:115200n8";
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index e870492a69..b49064181a 100644
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -8,6 +8,7 @@
 #include "k3-am642.dtsi"
 #include "k3-am64-evm-ddr4-1600MTs.dtsi"
 #include "k3-am64-ddr.dtsi"
+#include "k3-am64x-binman.dtsi"
 
 / {
 	chosen {
diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
index 69dbe943bd..3d6be025bd 100644
--- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include "k3-am64x-binman.dtsi"
+
 / {
 	chosen {
 		stdout-path = "serial2:115200n8";
diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi
new file mode 100644
index 0000000000..a5e54006b4
--- /dev/null
+++ b/arch/arm/dts/k3-am64x-binman.dtsi
@@ -0,0 +1,515 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_AM642_R5_EVM
+
+&binman {
+	tiboot3-am64x_sr2-hs-evm.bin {
+		filename = "tiboot3-am64x_sr2-hs-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl>, <&ti_sci_enc>,
+				<&combined_sysfw_cfg>, <&sysfw_inner_cert>;
+			combined;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl>;
+			content-sysfw = <&ti_sci_enc>;
+			content-sysfw-data = <&combined_sysfw_cfg>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert>;
+			load = <0x70000000>;
+			load-sysfw = <0x44000>;
+			load-sysfw-data = <0x7b000>;
+		};
+		u_boot_spl: u-boot-spl {
+			no-expanded;
+		};
+		ti_sci_enc: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_sysfw_cfg: combined-sysfw-cfg.bin {
+			filename = "combined-sysfw-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+
+	};
+};
+
+&binman {
+	tiboot3-am64x_sr2-hs-fs-evm.bin {
+		filename = "tiboot3-am64x_sr2-hs-fs-evm.bin";
+		symlink = "tiboot3.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_fs>, <&ti_sci_enc_fs>,
+				<&combined_sysfw_cfg_fs>, <&sysfw_inner_cert_fs>;
+			combined;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl_fs>;
+			content-sysfw = <&ti_sci_enc_fs>;
+			content-sysfw-data = <&combined_sysfw_cfg_fs>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+			load = <0x70000000>;
+			load-sysfw = <0x44000>;
+			load-sysfw-data = <0x7b000>;
+		};
+		u_boot_spl_fs: u-boot-spl {
+			no-expanded;
+		};
+		ti_sci_enc_fs: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_sysfw_cfg_fs: combined-sysfw-cfg.bin {
+			filename = "combined-sysfw-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert_fs: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+
+	};
+};
+
+&binman {
+	tiboot3-am64x-gp-evm.bin {
+		filename = "tiboot3-am64x-gp-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_unsigned>, <&ti_sci_gp>, <&combined_sysfw_cfg_gp>;
+			combined;
+			content-sbl = <&u_boot_spl_unsigned>;
+			load = <0x70000000>;
+			content-sysfw = <&ti_sci_gp>;
+			load-sysfw = <0x44000>;
+			content-sysfw-data = <&combined_sysfw_cfg_gp>;
+			load-sysfw-data = <0x7b000>;
+			sw-rev = <1>;
+			keyfile = "ti-degenerate-key.pem";
+		};
+		u_boot_spl_unsigned: u-boot-spl {
+			no-expanded;
+		};
+		ti_sci_gp: ti-sci-gp.bin {
+			filename = "ti-sysfw/ti-sci-firmware-am64x-gp.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_sysfw_cfg_gp: combined-sysfw-cfg-gp.bin {
+			filename = "combined-sysfw-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+#endif
+
+#ifdef CONFIG_TARGET_AM642_A53_EVM
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb"
+#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define AM642_EVM_DTB "u-boot.dtb"
+#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb"
+
+&binman {
+	ti-spl {
+		filename = "tispl.bin";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					ti-secure {
+						content = <&atf>;
+						keyfile = "custMpk.pem";
+					};
+					atf: atf-bl31 {
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					ti-secure {
+						content = <&tee>;
+						keyfile = "custMpk.pem";
+					};
+					tee: tee-os {
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					blob-ext {
+						filename = "/dev/null";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_spl_nodtb>;
+						keyfile = "custMpk.pem";
+
+					};
+					u_boot_spl_nodtb: blob-ext {
+						filename = SPL_NODTB;
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am642-evm";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_am64x_evm_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					spl_am64x_evm_dtb: blob-ext {
+						filename = SPL_AM642_EVM_DTB;
+					};
+
+				};
+
+				fdt-1 {
+					description = "k3-am642-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_am64x_sk_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					spl_am64x_sk_dtb: blob-ext {
+						filename = SPL_AM642_SK_DTB;
+					};
+
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am642-evm";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+
+				conf-1 {
+					description = "k3-am642-sk";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot {
+		filename = "u-boot.img";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for AM64 board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_nodtb: u-boot-nodtb {
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am642-evm";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&am64x_evm_dtb>;
+						keyfile = "custMpk.pem";
+
+					};
+					am64x_evm_dtb: blob-ext {
+						filename = AM642_EVM_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-1 {
+					description = "k3-am642-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&am64x_sk_dtb>;
+						keyfile = "custMpk.pem";
+
+					};
+					am64x_sk_dtb: blob-ext {
+						filename = AM642_SK_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am642-evm";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+
+				conf-1 {
+					description = "k3-am642-sk";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	ti-spl_unsigned {
+		filename = "tispl.bin_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					atf-bl31 {
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					tee-os {
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					blob-ext {
+						filename = "/dev/null";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					blob {
+						filename = "spl/u-boot-spl-nodtb.bin";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am642-evm";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = SPL_AM642_EVM_DTB;
+					};
+				};
+
+				fdt-1 {
+					description = "k3-am642-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = SPL_AM642_SK_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am642-evm";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+
+				conf-1 {
+					description = "k3-am642-sk";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot_unsigned {
+		filename = "u-boot.img_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for AM64 board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					blob {
+						filename = UBOOT_NODTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am642-evm";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = AM642_EVM_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-1 {
+					description = "k3-am642-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = AM642_SK_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am642-evm";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+
+				conf-1 {
+					description = "k3-am642-sk";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+#endif
diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
index 03ccc54329..3ecb461b01 100644
--- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) Siemens AG, 2020-2022
+ * Copyright (c) Siemens AG, 2020-2023
  *
  * Authors:
  *   Jan Kiszka <jan.kiszka@siemens.com>
@@ -10,30 +10,102 @@
 #include <config.h>
 
 / {
-	binman {
-		filename = "flash.bin";
+	binman: binman {
+		multiple-images;
+	};
+};
+
+&binman {
+	common_part: template {
 		pad-byte = <0xff>;
 		size = <0x8c0000>;
 		allow-repack;
 
-		blob-ext@0x000000 {
+		blob-ext@0 {
 			offset = <0x000000>;
-#ifdef CONFIG_TARGET_IOT2050_A53_PG1
-			filename = "seboot_pg1.bin";
-#else
-			filename = "seboot_pg2.bin";
-#endif
 			missing-msg = "iot2050-seboot";
 		};
 
-		blob@0x180000 {
+		fit@180000 {
 			offset = <0x180000>;
 			filename = "tispl.bin";
+			pad-byte = <0xff>;
+			description = "Configuration to load ATF and SPL";
+
+			images {
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					atf: atf-bl31 {
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					tee: tee-os {
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					blob-ext {
+						filename = "/dev/null";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					u_boot_spl_nodtb: blob-ext {
+						filename = "spl/u-boot-spl-nodtb.bin";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am65-iot2050-spl.dtb";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					spl_am65x_evm_dtb: blob-ext {
+						filename = "spl/dts/k3-am65-iot2050-spl.dtb";
+					};
+				};
+			};
+
+			configurations {
+				default = "spl";
+				spl {
+					fdt = "fdt-0";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+				};
+			};
 		};
 
-		fit@0x380000 {
+		fit@380000 {
 			description = "U-Boot for IOT2050";
-			fit,fdt-list = "of-list";
 			offset = <0x380000>;
 			images {
 				u-boot {
@@ -61,36 +133,6 @@
 					};
 				};
 
-#ifdef CONFIG_TARGET_IOT2050_A53_PG2
-				bkey-usb3-overlay {
-					description = "M.2-bkey-usb3-overlay";
-					type = "blob";
-					load = <0x82100000>;
-					arch = "arm64";
-					compression = "none";
-					blob-ext {
-						filename = "k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo";
-					};
-					hash {
-						algo = "sha256";
-					};
-				};
-
-				bkey-ekey-pcie-overlay {
-					description = "M.2-bkey-ekey-pcie-overlay";
-					type = "blob";
-					load = <0x82110000>;
-					arch = "arm64";
-					compression = "none";
-					blob-ext {
-						filename = "k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo";
-					};
-					hash {
-						algo = "sha256";
-					};
-				};
-#endif
-
 #ifdef CONFIG_WDT_K3_RTI_FW_FILE
 				k3-rti-wdt-firmware {
 					type = "firmware";
@@ -109,20 +151,10 @@
 			};
 
 			configurations {
-				default = "@config-DEFAULT-SEQ";
 				@config-SEQ {
 					description = "NAME";
 					firmware = "u-boot";
 					fdt = "fdt-SEQ";
-					loadables =
-#ifdef CONFIG_TARGET_IOT2050_A53_PG2
-						"bkey-usb3-overlay",
-						"bkey-ekey-pcie-overlay",
-#endif
-#ifdef CONFIG_WDT_K3_RTI_FW_FILE
-						"k3-rti-wdt-firmware",
-#endif
-						<>;
 					signature {
 						sign-images = "firmware", "fdt", "loadables";
 					};
@@ -134,32 +166,112 @@
 		};
 
 		/* primary env */
-		fill@0x680000 {
+		fill@680000 {
 			offset = <0x680000>;
 			size   = <0x020000>;
 			fill-byte = [00];
 		};
 		/* secondary env */
-		fill@0x6a0000 {
+		fill@6a0000 {
 			offset = <0x6a0000>;
 			size   = <0x020000>;
 			fill-byte = [00];
 		};
 
-		/* OTP update command block */
-#if CONFIG_IOT2050_EMBED_OTPCMD
-		blob-ext@0x6c0000 {
+/* OTP update command block */
+#ifdef CONFIG_IOT2050_EMBED_OTPCMD
+		blob-ext@6c0000 {
 			offset = <0x6c0000>;
+
 			size   = <0x010000>;
 			filename = "otpcmd.bin";
 			missing-msg = "iot2050-otpcmd";
 		};
 #else
-		fill@0x6c0000 {
+		fill@6c0000 {
 			offset = <0x6c0000>;
 			size   = <0x010000>;
 			fill-byte = [ff];
 		};
 #endif
 	};
+
+	flash-pg1 {
+		filename = "flash-pg1.bin";
+		insert-template = <&common_part>;
+
+		blob-ext@0 {
+			filename = "seboot_pg1.bin";
+		};
+
+		fit@380000 {
+			fit,fdt-list-val = "k3-am6528-iot2050-basic", "k3-am6548-iot2050-advanced";
+
+			configurations {
+				default = "k3-am6528-iot2050-basic";
+				@config-SEQ {
+					loadables =
+#ifdef CONFIG_WDT_K3_RTI_FW_FILE
+						"k3-rti-wdt-firmware",
+#endif
+						<>;
+				};
+			};
+		};
+	};
+
+	flash-pg2 {
+		filename = "flash-pg2.bin";
+		insert-template = <&common_part>;
+
+		blob-ext@0 {
+			filename = "seboot_pg2.bin";
+		};
+
+		fit@380000 {
+			fit,fdt-list-val = "k3-am6528-iot2050-basic-pg2", "k3-am6548-iot2050-advanced-pg2", "k3-am6548-iot2050-advanced-m2";
+
+			images {
+				bkey-usb3-overlay {
+					description = "M.2-bkey-usb3-overlay";
+					type = "blob";
+					load = <0x82100000>;
+					arch = "arm64";
+					compression = "none";
+					blob-ext {
+						filename = "k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo";
+					};
+					hash {
+						algo = "sha256";
+					};
+				};
+
+				bkey-ekey-pcie-overlay {
+					description = "M.2-bkey-ekey-pcie-overlay";
+					type = "blob";
+					load = <0x82110000>;
+					arch = "arm64";
+					compression = "none";
+					blob-ext {
+						filename = "k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo";
+					};
+					hash {
+						algo = "sha256";
+					};
+				};
+			};
+
+			configurations {
+				default = "k3-am6528-iot2050-basic-pg2";
+				@config-SEQ {
+					loadables =
+#ifdef CONFIG_WDT_K3_RTI_FW_FILE
+						"k3-rti-wdt-firmware",
+#endif
+						"bkey-usb3-overlay",
+						"bkey-ekey-pcie-overlay";
+				};
+			};
+		};
+	};
 };
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 0c1305df7e..e4cbc47c2a 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include "k3-am654-r5-base-board-u-boot.dtsi"
+#include "k3-am65x-binman.dtsi"
 
 &pru0_0 {
 	remoteproc-name = "pru0_0";
diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
index 4516ab1437..949320c91d 100644
--- a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/pinctrl/k3.h>
 #include <dt-bindings/net/ti-dp83867.h>
+#include "k3-am65x-binman.dtsi"
 
 / {
 	chosen {
diff --git a/arch/arm/dts/k3-am65x-binman.dtsi b/arch/arm/dts/k3-am65x-binman.dtsi
new file mode 100644
index 0000000000..59605ca597
--- /dev/null
+++ b/arch/arm/dts/k3-am65x-binman.dtsi
@@ -0,0 +1,518 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_AM654_R5_EVM
+
+&binman {
+	tiboot3-am65x_sr2-hs-evm.bin {
+		filename = "tiboot3-am65x_sr2-hs-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl>;
+			core = "public";
+			load = <CONFIG_SPL_TEXT_BASE>;
+			keyfile = "custMpk.pem";
+		};
+		u_boot_spl: u-boot-spl {
+			no-expanded;
+		};
+	};
+	sysfw {
+		filename = "sysfw.bin";
+		ti-secure-rom {
+			content = <&ti_sci_cert>;
+			core = "secure";
+			load = <0x40000>;
+			keyfile = "custMpk.pem";
+			countersign;
+		};
+		ti_sci_cert: ti-sci-cert.bin {
+			filename = "ti-sysfw/ti-sci-firmware-am65x_sr2-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		ti-sci-firmware-am65x-hs-enc.bin {
+			filename = "ti-sysfw/ti-sci-firmware-am65x_sr2-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+	};
+	itb {
+		filename = "sysfw-am65x_sr2-hs-evm.itb";
+		fit {
+			description = "SYSFW and Config fragments";
+			#address-cells = <1>;
+			images {
+				sysfw.bin {
+					description = "sysfw";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+					    filename = "sysfw.bin";
+					};
+				};
+				board-cfg.bin {
+					description = "board-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&board_cfg>;
+						keyfile = "custMpk.pem";
+					};
+					board_cfg: board-cfg {
+						filename = "board-cfg.bin";
+						type = "blob-ext";
+					};
+				};
+				pm-cfg.bin {
+					description = "pm-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&pm_cfg>;
+						keyfile = "custMpk.pem";
+					};
+					pm_cfg: pm-cfg {
+						filename = "pm-cfg.bin";
+						type = "blob-ext";
+					};
+				};
+				rm-cfg.bin {
+					description = "rm-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&rm_cfg>;
+						keyfile = "custMpk.pem";\
+					};
+					rm_cfg: rm-cfg {
+						filename = "rm-cfg.bin";
+						type = "blob-ext";
+					};
+				};
+				sec-cfg.bin {
+					description = "sec-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&sec_cfg>;
+						keyfile = "custMpk.pem";
+					};
+					sec_cfg: sec-cfg {
+						filename = "sec-cfg.bin";
+						type = "blob-ext";
+					};
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	tiboot3-am65x_sr2-gp-evm.bin {
+		filename = "tiboot3-am65x_sr2-gp-evm.bin";
+		symlink = "tiboot3.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_unsigned>;
+			core = "public";
+			load = <CONFIG_SPL_TEXT_BASE>;
+			sw-rev = <CONFIG_K3_X509_SWRV>;
+			keyfile = "ti-degenerate-key.pem";
+		};
+		u_boot_spl_unsigned: u-boot-spl {
+			no-expanded;
+		};
+	};
+	sysfw_gp {
+		filename = "sysfw.bin_gp";
+		ti-secure-rom {
+			content = <&ti_sci>;
+			core = "secure";
+			load = <0x40000>;
+			sw-rev = <CONFIG_K3_X509_SWRV>;
+			keyfile = "ti-degenerate-key.pem";
+		};
+		ti_sci: ti-sci.bin {
+			filename = "ti-sysfw/ti-sci-firmware-am65x_sr2-gp.bin";
+			type = "blob-ext";
+			optional;
+		};
+	};
+	itb_gp {
+		filename = "sysfw-am65x_sr2-gp-evm.itb";
+		symlink = "sysfw.itb";
+		fit {
+			description = "SYSFW and Config fragments";
+			#address-cells = <1>;
+			images {
+				sysfw.bin {
+					description = "sysfw";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+					    filename = "sysfw.bin_gp";
+					};
+				};
+				board-cfg.bin {
+					description = "board-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+						filename = "board-cfg.bin";
+					};
+				};
+				pm-cfg.bin {
+					description = "pm-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+						filename = "pm-cfg.bin";
+					};
+				};
+				rm-cfg.bin {
+					description = "rm-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+						filename = "rm-cfg.bin";
+					};
+				};
+				sec-cfg.bin {
+					description = "sec-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+						filename = "sec-cfg.bin";
+					};
+				};
+			};
+		};
+	};
+};
+#endif
+
+#ifdef CONFIG_TARGET_AM654_A53_EVM
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define AM654_EVM_DTB "u-boot.dtb"
+
+&binman {
+	ti-spl {
+		filename = "tispl.bin";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					ti-secure {
+						content = <&atf>;
+						keyfile = "custMpk.pem";
+					};
+					atf: atf-bl31 {
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					ti-secure {
+						content = <&tee>;
+						keyfile = "custMpk.pem";
+					};
+					tee: tee-os {
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					blob-ext {
+						filename = "/dev/null";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_spl_nodtb>;
+						keyfile = "custMpk.pem";
+
+					};
+					u_boot_spl_nodtb: blob-ext {
+						filename = SPL_NODTB;
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am654-base-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_am65x_evm_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					spl_am65x_evm_dtb: blob-ext {
+						filename = SPL_AM654_EVM_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am654-base-board";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot {
+		filename = "u-boot.img";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for AM65 board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_nodtb: u-boot-nodtb {
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am654-base-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&am65x_evm_dtb>;
+						keyfile = "custMpk.pem";
+
+					};
+					am65x_evm_dtb: blob-ext {
+						filename = AM654_EVM_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am654-base-board";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	ti-spl_unsigned {
+		filename = "tispl.bin_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					atf-bl31 {
+						filename = "bl31.bin";
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					tee-os {
+						filename = "tee-raw.bin";
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					blob-ext {
+						filename = "/dev/null";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					blob-ext {
+						filename = SPL_NODTB;
+					};
+				};
+
+				fdt-0 {
+					description = "k3-j721e-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = SPL_AM654_EVM_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am654-base-board";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot_unsigned {
+		filename = "u-boot.img_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for AM65 board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					blob {
+						filename = UBOOT_NODTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am654-base-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = AM654_EVM_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am654-base-board";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+#endif
diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
index ee31b1ebe7..79faa1b573 100644
--- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include "k3-j721s2-binman.dtsi"
+
 / {
 	chosen {
 		stdout-path = "serial2:115200n8";
diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi
new file mode 100644
index 0000000000..2ea2dd18a1
--- /dev/null
+++ b/arch/arm/dts/k3-binman.dtsi
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	binman: binman {
+		multiple-images;
+	};
+};
+
+&binman {
+	custMpk {
+		filename = "custMpk.pem";
+		custmpk_pem: blob-ext {
+			filename = "../keys/custMpk.pem";
+		};
+	};
+
+	ti-degenerate-key {
+		filename = "ti-degenerate-key.pem";
+		dkey_pem: blob-ext {
+			filename = "../keys/ti-degenerate-key.pem";
+		};
+	};
+};
+
+#ifndef CONFIG_ARM64
+
+&binman {
+	board-cfg {
+		filename = "board-cfg.bin";
+		bcfg_yaml: ti-board-config {
+			config = "board-cfg.yaml";
+			schema = "../common/schema.yaml";
+		};
+	};
+	pm-cfg {
+		filename = "pm-cfg.bin";
+		pcfg_yaml: ti-board-config {
+			config = "pm-cfg.yaml";
+			schema = "../common/schema.yaml";
+		};
+	};
+	rm-cfg {
+		filename = "rm-cfg.bin";
+		rcfg_yaml: ti-board-config {
+			config = "rm-cfg.yaml";
+			schema = "../common/schema.yaml";
+		};
+	};
+	sec-cfg {
+		filename = "sec-cfg.bin";
+		scfg_yaml: ti-board-config {
+			config = "sec-cfg.yaml";
+			schema = "../common/schema.yaml";
+		};
+	};
+	combined-tifs-cfg {
+		filename = "combined-tifs-cfg.bin";
+		ti-board-config {
+			bcfg_yaml_tifs: board-cfg {
+				config = "board-cfg.yaml";
+				schema = "../common/schema.yaml";
+			};
+			scfg_yaml_tifs: sec-cfg {
+				config = "sec-cfg.yaml";
+				schema = "../common/schema.yaml";
+			};
+			pcfg_yaml_tifs: pm-cfg {
+				config = "pm-cfg.yaml";
+				schema = "../common/schema.yaml";
+			};
+			rcfg_yaml_tifs: rm-cfg {
+				config = "rm-cfg.yaml";
+				schema = "../common/schema.yaml";
+			};
+		};
+	};
+	combined-dm-cfg {
+		filename = "combined-dm-cfg.bin";
+		ti-board-config {
+			pcfg_yaml_dm: pm-cfg {
+				config = "pm-cfg.yaml";
+				schema = "../common/schema.yaml";
+			};
+			rcfg_yaml_dm: rm-cfg {
+				config = "rm-cfg.yaml";
+				schema = "../common/schema.yaml";
+			};
+		};
+	};
+	combined-sysfw-cfg {
+		filename = "combined-sysfw-cfg.bin";
+		ti-board-config {
+			bcfg_yaml_sysfw: board-cfg {
+				config = "board-cfg.yaml";
+				schema = "../common/schema.yaml";
+			};
+			scfg_yaml_sysfw: sec-cfg {
+				config = "sec-cfg.yaml";
+				schema = "../common/schema.yaml";
+			};
+			pcfg_yaml_sysfw: pm-cfg {
+				config = "pm-cfg.yaml";
+				schema = "../common/schema.yaml";
+			};
+			rcfg_yaml_sysfw: rm-cfg {
+				config = "rm-cfg.yaml";
+				schema = "../common/schema.yaml";
+			};
+		};
+	};
+};
+
+#endif
diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi
new file mode 100644
index 0000000000..14f7dea65e
--- /dev/null
+++ b/arch/arm/dts/k3-j7200-binman.dtsi
@@ -0,0 +1,502 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_J7200_R5_EVM
+
+&bcfg_yaml {
+	config = "board-cfg_j7200.yaml";
+};
+
+&rcfg_yaml {
+	config = "rm-cfg_j7200.yaml";
+};
+
+&pcfg_yaml {
+	config = "pm-cfg_j7200.yaml";
+};
+
+&scfg_yaml {
+	config = "sec-cfg_j7200.yaml";
+};
+
+&bcfg_yaml_tifs {
+	config = "board-cfg_j7200.yaml";
+};
+
+&rcfg_yaml_tifs {
+	config = "rm-cfg_j7200.yaml";
+};
+
+&pcfg_yaml_tifs {
+	config = "pm-cfg_j7200.yaml";
+};
+
+&scfg_yaml_tifs {
+	config = "sec-cfg_j7200.yaml";
+};
+
+&rcfg_yaml_dm {
+	config = "rm-cfg_j7200.yaml";
+};
+
+&pcfg_yaml_dm {
+	config = "pm-cfg_j7200.yaml";
+};
+
+&binman {
+	tiboot3-j7200_sr2-hs-evm.bin {
+		filename = "tiboot3-j7200_sr2-hs-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+				<&combined_dm_cfg>, <&sysfw_inner_cert>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl>;
+			content-sysfw = <&ti_fs_enc>;
+			content-sysfw-data = <&combined_tifs_cfg>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert>;
+			content-dm-data = <&combined_dm_cfg>;
+			load = <0x41c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x7f000>;
+			load-dm-data = <0x41c80000>;
+		};
+		u_boot_spl: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_dm_cfg: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-j7200_sr2-hs-fs-evm.bin {
+		filename = "tiboot3-j7200_sr2-hs-fs-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+				<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl_fs>;
+			content-sysfw = <&ti_fs_enc_fs>;
+			content-sysfw-data = <&combined_tifs_cfg_fs>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+			content-dm-data = <&combined_dm_cfg_fs>;
+			load = <0x41c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x7f000>;
+			load-dm-data = <0x41c80000>;
+		};
+		u_boot_spl_fs: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc_fs: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-fs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert_fs: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-fs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_dm_cfg_fs: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-j7200-gp-evm.bin {
+		filename = "tiboot3-j7200-gp-evm.bin";
+		symlink = "tiboot3.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
+				<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
+			combined;
+			dm-data;
+			content-sbl = <&u_boot_spl_unsigned>;
+			load = <0x41c00000>;
+			content-sysfw = <&ti_fs_gp>;
+			load-sysfw = <0x40000>;
+			content-sysfw-data = <&combined_tifs_cfg_gp>;
+			load-sysfw-data = <0x7f000>;
+			content-dm-data = <&combined_dm_cfg_gp>;
+			load-dm-data = <0x41c80000>;
+			sw-rev = <1>;
+			keyfile = "ti-degenerate-key.pem";
+		};
+		u_boot_spl_unsigned: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_gp: ti-fs-gp.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j7200-gp.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+#endif
+
+#ifdef CONFIG_TARGET_J7200_A72_EVM
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_J7200_EVM_DTB "spl/dts/k3-j7200-common-proc-board.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define J7200_EVM_DTB "u-boot.dtb"
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+		blob-ext {
+			filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+		};
+	};
+	ti-spl {
+		filename = "tispl.bin";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					ti-secure {
+						content = <&atf>;
+						keyfile = "custMpk.pem";
+					};
+					atf: atf-bl31 {
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					ti-secure {
+						content = <&tee>;
+						keyfile = "custMpk.pem";
+					};
+					tee: tee-os {
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					ti-secure {
+						content = <&dm>;
+						keyfile = "custMpk.pem";
+					};
+
+					dm: blob-ext {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_spl_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_spl_nodtb: blob-ext {
+						filename = SPL_NODTB;
+					};
+				};
+
+				fdt-0 {
+					description = "k3-j7200-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_j7200_evm_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					spl_j7200_evm_dtb: blob-ext {
+						filename = SPL_J7200_EVM_DTB;
+					};
+				};
+
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-j7200-common-proc-board";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot {
+		filename = "u-boot.img";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for J7200 board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_nodtb: u-boot-nodtb {
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-j7200-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&j7200_evm_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					j7200_evm_dtb: blob-ext {
+						filename = J7200_EVM_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-j7200-common-proc-board";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+
+			};
+		};
+	};
+};
+
+&binman {
+	ti-spl_unsigned {
+		filename = "tispl.bin_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					atf-bl31 {
+						filename = "bl31.bin";
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					tee-os {
+						filename = "tee-raw.bin";
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					blob-ext {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					blob {
+						filename = SPL_NODTB;
+					};
+				};
+
+				fdt-1 {
+					description = "k3-j7200-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = SPL_J7200_EVM_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-1";
+
+				conf-1 {
+					description = "k3-j7200-common-proc-board";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot_unsigned {
+		filename = "u-boot.img_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for J7200 board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					blob {
+						filename = UBOOT_NODTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-1 {
+					description = "k3-j7200-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = J7200_EVM_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-1";
+
+				conf-1 {
+					description = "k3-j7200-common-proc-board";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+#endif
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index f57c2306ba..f25c7136c9 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include "k3-j7200-binman.dtsi"
+
 / {
 	chosen {
 		stdout-path = "serial2:115200n8";
diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi
new file mode 100644
index 0000000000..4f566c21a9
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-binman.dtsi
@@ -0,0 +1,701 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_J721E_R5_EVM
+
+&binman {
+	tiboot3-j721e_sr1_1-hs-evm.bin {
+		filename = "tiboot3-j721e_sr1_1-hs-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl>;
+			core = "public";
+			load = <CONFIG_SPL_TEXT_BASE>;
+			keyfile = "custMpk.pem";
+		};
+		u_boot_spl: u-boot-spl {
+			no-expanded;
+		};
+	};
+	sysfw {
+		filename = "sysfw.bin";
+		ti-secure-rom {
+			content = <&ti_fs_cert>;
+			core = "secure";
+			load = <0x40000>;
+			keyfile = "custMpk.pem";
+			countersign;
+		};
+		ti_fs_cert: ti-fs-cert.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		ti-fs-firmware-j721e_sr1_1-hs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+	};
+	itb {
+		filename = "sysfw-j721e_sr1_1-hs-evm.itb";
+		fit {
+			description = "SYSFW and Config fragments";
+			#address-cells = <1>;
+			images {
+				sysfw.bin {
+					description = "sysfw";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+					    filename = "sysfw.bin";
+					};
+				};
+				board-cfg.bin {
+					description = "board-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&board_cfg>;
+						keyfile = "custMpk.pem";
+					};
+					board_cfg: board-cfg {
+						filename = "board-cfg.bin";
+						type = "blob-ext";
+					};
+
+				};
+				pm-cfg.bin {
+					description = "pm-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&pm_cfg>;
+						keyfile = "custMpk.pem";
+					};
+					pm_cfg: pm-cfg {
+						filename = "pm-cfg.bin";
+						type = "blob-ext";
+					};
+				};
+				rm-cfg.bin {
+					description = "rm-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&rm_cfg>;
+						keyfile = "custMpk.pem";
+					};
+					rm_cfg: rm-cfg {
+						filename = "rm-cfg.bin";
+						type = "blob-ext";
+					};
+				};
+				sec-cfg.bin {
+					description = "sec-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&sec_cfg>;
+						keyfile = "custMpk.pem";
+					};
+					sec_cfg: sec-cfg {
+						filename = "sec-cfg.bin";
+						type = "blob-ext";
+					};
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	tiboot3-j721e_sr2-hs-fs-evm.bin {
+		filename = "tiboot3-j721e_sr2-hs-fs-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_fs>;
+			core = "public";
+			load = <CONFIG_SPL_TEXT_BASE>;
+			keyfile = "custMpk.pem";
+		};
+		u_boot_spl_fs: u-boot-spl {
+			no-expanded;
+		};
+	};
+	sysfw_fs {
+		filename = "sysfw.bin_fs";
+		ti-fs-cert-fs.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-fs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		ti-fs-firmware-j721e-hs-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-fs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+	};
+	itb_fs {
+		filename = "sysfw-j721e_sr2-hs-fs-evm.itb";
+		fit {
+			description = "SYSFW and Config fragments";
+			#address-cells = <1>;
+			images {
+				sysfw.bin {
+					description = "sysfw";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+					    filename = "sysfw.bin_fs";
+					};
+				};
+				board-cfg.bin {
+					description = "board-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					board-cfg {
+						filename = "board-cfg.bin";
+						type = "blob-ext";
+					};
+
+				};
+				pm-cfg.bin {
+					description = "pm-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					pm-cfg {
+						filename = "pm-cfg.bin";
+						type = "blob-ext";
+					};
+				};
+				rm-cfg.bin {
+					description = "rm-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					rm-cfg {
+						filename = "rm-cfg.bin";
+						type = "blob-ext";
+					};
+				};
+				sec-cfg.bin {
+					description = "sec-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					sec-cfg {
+						filename = "sec-cfg.bin";
+						type = "blob-ext";
+					};
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	tiboot3-j721e-gp-evm.bin {
+		filename = "tiboot3-j721e-gp-evm.bin";
+		symlink = "tiboot3.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_unsigned>;
+			core = "public";
+			load = <CONFIG_SPL_TEXT_BASE>;
+			sw-rev = <CONFIG_K3_X509_SWRV>;
+			keyfile = "ti-degenerate-key.pem";
+		};
+		u_boot_spl_unsigned: u-boot-spl {
+			no-expanded;
+		};
+	};
+	sysfw_gp {
+		filename = "sysfw.bin_gp";
+		ti-secure-rom {
+			content = <&ti_fs>;
+			core = "secure";
+			load = <0x40000>;
+			sw-rev = <CONFIG_K3_X509_SWRV>;
+			keyfile = "ti-degenerate-key.pem";
+		};
+		ti_fs: ti-fs.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j721e-gp.bin";
+			type = "blob-ext";
+			optional;
+		};
+	};
+	itb_gp {
+		filename = "sysfw-j721e-gp-evm.itb";
+		symlink = "sysfw.itb";
+		fit {
+			description = "SYSFW and Config fragments";
+			#address-cells = <1>;
+			images {
+				sysfw.bin {
+					description = "sysfw";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+					    filename = "sysfw.bin_gp";
+					};
+				};
+				board-cfg.bin {
+					description = "board-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+						filename = "board-cfg.bin";
+					};
+				};
+				pm-cfg.bin {
+					description = "pm-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+						filename = "pm-cfg.bin";
+					};
+				};
+				rm-cfg.bin {
+					description = "rm-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+						filename = "rm-cfg.bin";
+					};
+				};
+				sec-cfg.bin {
+					description = "sec-cfg";
+					type = "firmware";
+					arch = "arm";
+					compression = "none";
+					blob-ext {
+						filename = "sec-cfg.bin";
+					};
+				};
+			};
+		};
+	};
+};
+#endif
+
+#ifdef CONFIG_TARGET_J721E_A72_EVM
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_J721E_EVM_DTB "spl/dts/k3-j721e-common-proc-board.dtb"
+#define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define J721E_EVM_DTB "u-boot.dtb"
+#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb"
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+		blob-ext {
+			filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+		};
+	};
+	ti-spl {
+		filename = "tispl.bin";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					ti-secure {
+						content = <&atf>;
+						keyfile = "custMpk.pem";
+					};
+					atf: atf-bl31 {
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					ti-secure {
+						content = <&tee>;
+						keyfile = "custMpk.pem";
+					};
+					tee: tee-os {
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					ti-secure {
+						content = <&dm>;
+						keyfile = "custMpk.pem";
+					};
+					dm: blob-ext {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_spl_nodtb>;
+						keyfile = "custMpk.pem";
+
+					};
+					u_boot_spl_nodtb: blob-ext {
+						filename = SPL_NODTB;
+					};
+				};
+
+				fdt-0 {
+					description = "k3-j721e-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_j721e_evm_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					spl_j721e_evm_dtb: blob-ext {
+						filename = SPL_J721E_EVM_DTB;
+					};
+				};
+
+				fdt-1 {
+					description = "k3-j721e-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_j721e_sk_dtb>;
+						keyfile = "custMpk.pem";
+
+					};
+					spl_j721e_sk_dtb: blob-ext {
+						filename = SPL_J721E_SK_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-j721e-common-proc-board";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+
+				conf-1 {
+					description = "k3-j721e-sk";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot {
+		filename = "u-boot.img";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for j721e board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_nodtb: u-boot-nodtb {
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-j721e-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&j721e_evm_dtb>;
+						keyfile = "custMpk.pem";
+
+					};
+					j721e_evm_dtb: blob-ext {
+						filename = J721E_EVM_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-1 {
+					description = "k3-j721e-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&j721e_sk_dtb>;
+						keyfile = "custMpk.pem";
+
+					};
+					j721e_sk_dtb: blob-ext {
+						filename = J721E_SK_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-j721e-common-proc-board";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+
+				conf-1 {
+					description = "k3-j721e-sk";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	ti-spl_unsigned {
+		filename = "tispl.bin_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					atf-bl31 {
+						filename = "bl31.bin";
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					tee-os {
+						filename = "tee-raw.bin";
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					blob-ext {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					blob-ext {
+						filename = SPL_NODTB;
+					};
+				};
+
+				fdt-0 {
+					description = "k3-j721e-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = SPL_J721E_EVM_DTB;
+					};
+				};
+
+				fdt-1 {
+					description = "k3-j721e-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = SPL_J721E_SK_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-j721e-common-proc-board";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+
+				conf-1 {
+					description = "k3-j721e-sk";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot_unsigned {
+		filename = "u-boot.img_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for j721e board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					blob {
+						filename = UBOOT_NODTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-j721e-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = J721E_EVM_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-1 {
+					description = "k3-j721e-sk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = J721E_SK_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-j721e-common-proc-board";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+
+				conf-1 {
+					description = "k3-j721e-sk";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+#endif
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 867ec2bb1a..540c847eb3 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/net/ti-dp83867.h>
+#include "k3-j721e-binman.dtsi"
 
 / {
 	chosen {
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 1b40cf2580..32f71e9b6a 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -8,6 +8,7 @@
 #include "k3-j721e-som-p0.dtsi"
 #include "k3-j721e-ddr-evm-lp4-4266.dtsi"
 #include "k3-j721e-ddr.dtsi"
+#include "k3-j721e-binman.dtsi"
 #include <dt-bindings/phy/phy-cadence.h>
 
 / {
diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
index 31f979f3bb..205dacff4d 100644
--- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/net/ti-dp83867.h>
+#include "k3-j721e-binman.dtsi"
 
 / {
 	chosen {
diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi
new file mode 100644
index 0000000000..5bca4e94ec
--- /dev/null
+++ b/arch/arm/dts/k3-j721s2-binman.dtsi
@@ -0,0 +1,546 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_J721S2_R5_EVM
+
+&binman {
+	tiboot3-j721s2-hs-evm.bin {
+		filename = "tiboot3-j721s2-hs-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+				<&combined_dm_cfg>, <&sysfw_inner_cert>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl>;
+			content-sysfw = <&ti_fs_enc>;
+			content-sysfw-data = <&combined_tifs_cfg>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert>;
+			content-dm-data = <&combined_dm_cfg>;
+			load = <0x41c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x41c80000>;
+		};
+		u_boot_spl: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_dm_cfg: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-j721s2-hs-fs-evm.bin {
+		filename = "tiboot3-j721s2-hs-fs-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+				<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl_fs>;
+			content-sysfw = <&ti_fs_enc_fs>;
+			content-sysfw-data = <&combined_tifs_cfg_fs>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+			content-dm-data = <&combined_dm_cfg_fs>;
+			load = <0x41c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x41c80000>;
+		};
+		u_boot_spl_fs: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc_fs: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-fs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert_fs: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-fs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_dm_cfg_fs: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-j721s2-gp-evm.bin {
+		filename = "tiboot3-j721s2-gp-evm.bin";
+		symlink = "tiboot3.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
+				<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
+			combined;
+			dm-data;
+			content-sbl = <&u_boot_spl_unsigned>;
+			load = <0x41c00000>;
+			content-sysfw = <&ti_fs_gp>;
+			load-sysfw = <0x40000>;
+			content-sysfw-data = <&combined_tifs_cfg_gp>;
+			load-sysfw-data = <0x67000>;
+			content-dm-data = <&combined_dm_cfg_gp>;
+			load-dm-data = <0x41c80000>;
+			sw-rev = <1>;
+			keyfile = "ti-degenerate-key.pem";
+		};
+		u_boot_spl_unsigned: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_gp: ti-fs-gp.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j721s2-gp.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+
+	};
+};
+
+#endif
+
+#ifdef CONFIG_TARGET_J721S2_A72_EVM
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_J721S2_EVM_DTB "spl/dts/k3-j721s2-common-proc-board.dtb"
+#define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define J721S2_EVM_DTB "u-boot.dtb"
+#define AM68_SK_DTB "arch/arm/dts/k3-am68-sk-base-board.dtb"
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+		blob-ext {
+			filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+		};
+	};
+	ti-spl {
+		filename = "tispl.bin";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					ti-secure {
+						content = <&atf>;
+						keyfile = "custMpk.pem";
+					};
+					atf: atf-bl31 {
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					ti-secure {
+						content = <&tee>;
+						keyfile = "custMpk.pem";
+					};
+					tee: tee-os {
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					ti-secure {
+						content = <&dm>;
+						keyfile = "custMpk.pem";
+					};
+					dm: blob-ext {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_spl_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_spl_nodtb: blob-ext {
+						filename = SPL_NODTB;
+					};
+				};
+
+				fdt-0 {
+					description = "k3-j721s2-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_j721s2_evm_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					spl_j721s2_evm_dtb: blob-ext {
+						filename = SPL_J721S2_EVM_DTB;
+					};
+
+				};
+
+				fdt-1 {
+					description = "k3-am68-sk-base-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_am68_sk_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					spl_am68_sk_dtb: blob-ext {
+						filename = SPL_AM68_SK_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-j721s2-common-proc-board";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+
+				conf-1 {
+					description = "k3-am68-sk-base-board";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot {
+		filename = "u-boot.img";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for J721S2 board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_nodtb>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_nodtb: u-boot-nodtb {
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-j721s2-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&j721s2_evm_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					j721s2_evm_dtb: blob-ext {
+						filename = J721S2_EVM_DTB;
+					};
+
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-1 {
+					description = "k3-am68-sk-base-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&am68_sk_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					am68_sk_dtb: blob-ext {
+						filename = AM68_SK_DTB;
+					};
+
+					hash {
+						algo = "crc32";
+					};
+				};
+
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-j721s2-common-proc-board";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+				conf-1 {
+					description = "k3-am68-sk-base-board";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-1";
+				};
+
+			};
+		};
+	};
+};
+
+&binman {
+	ti-spl_unsigned {
+		filename = "tispl.bin_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration to load ATF and SPL";
+			#address-cells = <1>;
+
+			images {
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					atf-bl31 {
+						filename = "bl31.bin";
+					};
+				};
+
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <0x9e800000>;
+					entry = <0x9e800000>;
+					tee-os {
+						filename = "tee-raw.bin";
+					};
+				};
+
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+					blob-ext {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				spl {
+					description = "SPL (64-bit)";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SPL_TEXT_BASE>;
+					entry = <CONFIG_SPL_TEXT_BASE>;
+					blob {
+						filename = "spl/u-boot-spl-nodtb.bin";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-j721s2-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = SPL_J721S2_EVM_DTB;
+					};
+				};
+				fdt-1 {
+					description = "k3-am68-sk-base-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = SPL_AM68_SK_DTB;
+					};
+				};
+
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-j721s2-common-proc-board";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+				conf-1 {
+					description = "k3-am68-sk-base-board";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot_unsigned {
+		filename = "u-boot.img_unsigned";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot for J721S2 board";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					blob {
+						filename = UBOOT_NODTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-j721s2-common-proc-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = J721S2_EVM_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+				fdt-1 {
+					description = "k3-am68-sk-base-board";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = AM68_SK_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-j721s2-common-proc-board";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+				conf-1 {
+					description = "k3-am68-sk-base-board";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
+#endif
diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
index 4fd6d36417..f940ffee87 100644
--- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include "k3-j721s2-binman.dtsi"
+
 / {
 	chosen {
 		stdout-path = "serial2:115200n8";
diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
index e02b334d10..c74e8e58ae 100644
--- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -8,6 +8,7 @@
 #include "k3-j721s2-som-p0.dtsi"
 #include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
 #include "k3-j721s2-ddr.dtsi"
+#include "k3-j721s2-binman.dtsi"
 
 / {
 	chosen {
diff --git a/arch/arm/dts/k3-pinctrl.h b/arch/arm/dts/k3-pinctrl.h
new file mode 100644
index 0000000000..c97548a3f4
--- /dev/null
+++ b/arch/arm/dts/k3-pinctrl.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for pinctrl bindings for TI's K3 SoC
+ * family.
+ *
+ * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#ifndef DTS_ARM64_TI_K3_PINCTRL_H
+#define DTS_ARM64_TI_K3_PINCTRL_H
+
+#define PULLUDEN_SHIFT		(16)
+#define PULLTYPESEL_SHIFT	(17)
+#define RXACTIVE_SHIFT		(18)
+
+#define PULL_DISABLE		(1 << PULLUDEN_SHIFT)
+#define PULL_ENABLE		(0 << PULLUDEN_SHIFT)
+
+#define PULL_UP			(1 << PULLTYPESEL_SHIFT | PULL_ENABLE)
+#define PULL_DOWN		(0 << PULLTYPESEL_SHIFT | PULL_ENABLE)
+
+#define INPUT_EN		(1 << RXACTIVE_SHIFT)
+#define INPUT_DISABLE		(0 << RXACTIVE_SHIFT)
+
+/* Only these macros are expected be used directly in device tree files */
+#define PIN_OUTPUT		(INPUT_DISABLE | PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP	(INPUT_DISABLE | PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	(INPUT_DISABLE | PULL_DOWN)
+#define PIN_INPUT		(INPUT_EN | PULL_DISABLE)
+#define PIN_INPUT_PULLUP	(INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(INPUT_EN | PULL_DOWN)
+
+#define AM62AX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM62AX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
+#define AM62X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM62X_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
+#define AM64X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM64X_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
+#define AM65X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM65X_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
+#define J721E_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define J721E_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
+#define J721S2_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define J721S2_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
+#define J784S4_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define J784S4_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
+#endif
diff --git a/arch/arm/dts/meson-a1-ad401.dts b/arch/arm/dts/meson-a1-ad401.dts
new file mode 100644
index 0000000000..69c25c68c3
--- /dev/null
+++ b/arch/arm/dts/meson-a1-ad401.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-a1.dtsi"
+
+/ {
+	compatible = "amlogic,ad401", "amlogic,a1";
+	model = "Amlogic Meson A1 AD401 Development Board";
+
+	aliases {
+		serial0 = &uart_AO_B;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x8000000>;
+	};
+};
+
+&uart_AO_B {
+	status = "okay";
+};
diff --git a/arch/arm/dts/meson-a1.dtsi b/arch/arm/dts/meson-a1.dtsi
new file mode 100644
index 0000000000..6509329b85
--- /dev/null
+++ b/arch/arm/dts/meson-a1.dtsi
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/meson-a1-gpio.h>
+
+/ {
+	compatible = "amlogic,a1";
+
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x800000>;
+			alignment = <0x0 0x400000>;
+			linux,cma-default;
+		};
+	};
+
+	sm: secure-monitor {
+		compatible = "amlogic,meson-gxbb-sm";
+
+		pwrc: power-controller {
+			compatible = "amlogic,meson-a1-pwrc";
+			#power-domain-cells = <1>;
+			status = "okay";
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		apb: bus@fe000000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xfe000000 0x0 0x1000000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
+
+			reset: reset-controller@0 {
+				compatible = "amlogic,meson-a1-reset";
+				reg = <0x0 0x0 0x0 0x8c>;
+				#reset-cells = <1>;
+			};
+
+			periphs_pinctrl: pinctrl@400 {
+				compatible = "amlogic,meson-a1-periphs-pinctrl";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				ranges;
+
+				gpio: bank@400 {
+					reg = <0x0 0x0400 0x0 0x003c>,
+					      <0x0 0x0480 0x0 0x0118>;
+					reg-names = "mux", "gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					gpio-ranges = <&periphs_pinctrl 0 0 62>;
+				};
+
+			};
+
+			uart_AO: serial@1c00 {
+				compatible = "amlogic,meson-gx-uart",
+					     "amlogic,meson-ao-uart";
+				reg = <0x0 0x1c00 0x0 0x18>;
+				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>, <&xtal>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
+				status = "disabled";
+			};
+
+			uart_AO_B: serial@2000 {
+				compatible = "amlogic,meson-gx-uart",
+					     "amlogic,meson-ao-uart";
+				reg = <0x0 0x2000 0x0 0x18>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>, <&xtal>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
+				status = "disabled";
+			};
+		};
+
+		gic: interrupt-controller@ff901000 {
+			compatible = "arm,gic-400";
+			reg = <0x0 0xff901000 0x0 0x1000>,
+			      <0x0 0xff902000 0x0 0x2000>,
+			      <0x0 0xff904000 0x0 0x2000>,
+			      <0x0 0xff906000 0x0 0x2000>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	xtal: xtal-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "xtal";
+		#clock-cells = <0>;
+	};
+};
diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi
index efa6a0570b..8070b62af5 100644
--- a/arch/arm/dts/meson-g12-common-u-boot.dtsi
+++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi
@@ -5,7 +5,7 @@
  */
 
 / {
-	/* Keep HW order from U-boot */
+	/* Keep HW order from U-Boot */
 	aliases {
 		/delete-property/ mmc0;
 		/delete-property/ mmc1;
diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi
index 9f123ab042..9e0620f395 100644
--- a/arch/arm/dts/meson-gx-u-boot.dtsi
+++ b/arch/arm/dts/meson-gx-u-boot.dtsi
@@ -5,7 +5,7 @@
  */
 
 / {
-	/* Keep HW order from U-boot */
+	/* Keep HW order from U-Boot */
 	aliases {
 		/delete-property/ mmc0;
 		/delete-property/ mmc1;
diff --git a/arch/arm/dts/meson-gxbb-kii-pro-u-boot.dtsi b/arch/arm/dts/meson-gxbb-kii-pro-u-boot.dtsi
new file mode 100644
index 0000000000..191c5192c6
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-kii-pro-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-gx-u-boot.dtsi"
+
+&ethmac {
+	snps,reset-gpio = <&gpio GPIOZ_14 0>;
+	snps,reset-delays-us = <0>, <10000>, <1000000>;
+	snps,reset-active-low;
+};
diff --git a/arch/arm/dts/meson-gxbb-kii-pro.dts b/arch/arm/dts/meson-gxbb-kii-pro.dts
new file mode 100644
index 0000000000..e238f1f101
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-kii-pro.dts
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Mohammad Rasim <mohammad.rasim96@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-p20x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+	compatible = "videostrong,kii-pro", "amlogic,meson-gxbb";
+	model = "Videostrong KII Pro";
+
+	spdif_dit: audio-codec-0 {
+		#sound-dai-cells = <0>;
+		compatible = "linux,spdif-dit";
+		status = "okay";
+		sound-name-prefix = "DIT";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led {
+			gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		poll-interval = <20>;
+
+		button-reset {
+			label = "reset";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	sound {
+		compatible = "amlogic,gx-sound-card";
+		model = "KII-PRO";
+		assigned-clocks = <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>,
+				  <&clkc CLKID_MPLL2>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+
+		dai-link-0 {
+			sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
+		};
+
+		dai-link-2 {
+			sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+			dai-format = "i2s";
+			mclk-fs = <256>;
+
+			codec-0 {
+				sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+			};
+		};
+
+		dai-link-3 {
+			sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+			codec-0 {
+				sound-dai = <&spdif_dit>;
+			};
+		};
+
+		dai-link-4 {
+			sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+			codec-0 {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+};
+
+&aiu {
+	status = "okay";
+	pinctrl-0 = <&spdif_out_y_pins>;
+	pinctrl-names = "default";
+};
+
+&ethmac {
+	status = "okay";
+	pinctrl-0 = <&eth_rmii_pins>;
+	pinctrl-names = "default";
+
+	phy-handle = <&eth_phy0>;
+	phy-mode = "rmii";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		eth_phy0: ethernet-phy@0 {
+			/* IC Plus IP101GR (0x02430c54) */
+			reg = <0>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <10000>;
+			reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ir {
+	linux,rc-map-name = "rc-videostrong-kii-pro";
+};
+
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm4335a0";
+		shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
index 7c55744ac7..717baf26d3 100644
--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -224,12 +224,12 @@
 &eth {
 	status = "okay";
 	mediatek,gmac-id = <0>;
-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 	mediatek,switch = "mt7531";
 	reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
 
 	fixed-link {
-		speed = <1000>;
+		speed = <2500>;
 		full-duplex;
 	};
 };
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index 886a133e05..321de75ae3 100644
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -233,12 +233,12 @@
 &eth {
 	status = "okay";
 	mediatek,gmac-id = <0>;
-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 	mediatek,switch = "mt7531";
 	reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
 
 	fixed-link {
-		speed = <1000>;
+		speed = <2500>;
 		full-duplex;
 	};
 };
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
index 82f6a34162..f347725f2f 100644
--- a/arch/arm/dts/mt7629-rfb.dts
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -25,12 +25,12 @@
 &eth {
 	status = "okay";
 	mediatek,gmac-id = <0>;
-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 	mediatek,switch = "mt7531";
 	reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
 
 	fixed-link {
-		speed = <1000>;
+		speed = <2500>;
 		full-duplex;
 	};
 };
diff --git a/arch/arm/dts/mt7981-emmc-rfb.dts b/arch/arm/dts/mt7981-emmc-rfb.dts
index 2b7eae99ce..9aa7cd8f6e 100644
--- a/arch/arm/dts/mt7981-emmc-rfb.dts
+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
@@ -18,6 +18,11 @@
 		tick-timer = &timer0;
 	};
 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
 	reg_3p3v: regulator-3p3v {
 		  compatible = "regulator-fixed";
 		  regulator-name = "fixed-3.3V";
@@ -41,12 +46,12 @@
 &eth {
 	status = "okay";
 	mediatek,gmac-id = <0>;
-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 	mediatek,switch = "mt7531";
 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
 
 	fixed-link {
-		speed = <1000>;
+		speed = <2500>;
 		full-duplex;
 	};
 };
diff --git a/arch/arm/dts/mt7981-rfb.dts b/arch/arm/dts/mt7981-rfb.dts
index 5559ace953..22a022acb6 100644
--- a/arch/arm/dts/mt7981-rfb.dts
+++ b/arch/arm/dts/mt7981-rfb.dts
@@ -17,6 +17,11 @@
 		stdout-path = &uart0;
 		tick-timer = &timer0;
 	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
 };
 
 &uart0 {
@@ -32,12 +37,12 @@
 &eth {
 	status = "okay";
 	mediatek,gmac-id = <0>;
-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 	mediatek,switch = "mt7531";
 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
 
 	fixed-link {
-		speed = <1000>;
+		speed = <2500>;
 		full-duplex;
 	};
 };
diff --git a/arch/arm/dts/mt7981-sd-rfb.dts b/arch/arm/dts/mt7981-sd-rfb.dts
index 34ac227ecf..7d70808404 100644
--- a/arch/arm/dts/mt7981-sd-rfb.dts
+++ b/arch/arm/dts/mt7981-sd-rfb.dts
@@ -18,6 +18,11 @@
 		tick-timer = &timer0;
 	};
 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
 	reg_3p3v: regulator-3p3v {
 		  compatible = "regulator-fixed";
 		  regulator-name = "fixed-3.3V";
@@ -41,12 +46,12 @@
 &eth {
 	status = "okay";
 	mediatek,gmac-id = <0>;
-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 	mediatek,switch = "mt7531";
 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
 
 	fixed-link {
-		speed = <1000>;
+		speed = <2500>;
 		full-duplex;
 	};
 };
diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi
index 2c8ef14f98..7aaa7770f8 100644
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -152,6 +152,20 @@
 		status = "disabled";
 	};
 
+	i2c0: i2c@11007000 {
+		compatible = "mediatek,mt7981-i2c";
+		reg = <0x11007000 0x1000>,
+		      <0x10217080 0x80>;
+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+		clock-div = <1>;
+		clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
+			 <&infracfg_ao CK_INFRA_AP_DMA_CK>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	uart0: serial@11002000 {
 		compatible = "mediatek,hsuart";
 		reg = <0x11002000 0x400>;
@@ -223,6 +237,7 @@
 		reset-names = "fe";
 		mediatek,ethsys = <&ethsys>;
 		mediatek,sgmiisys = <&sgmiisys0>;
+		mediatek,infracfg = <&topmisc>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
@@ -241,6 +256,12 @@
 		#clock-cells = <1>;
 	};
 
+	topmisc: topmisc@11d10000 {
+		compatible = "mediatek,mt7981-topmisc", "syscon";
+		reg = <0x11d10000 0x10000>;
+		#clock-cells = <1>;
+	};
+
 	spi0: spi@1100a000 {
 		compatible = "mediatek,ipm-spi";
 		reg = <0x1100a000 0x100>;
diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
index 4d12440fa3..15256302b8 100644
--- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
@@ -19,6 +19,11 @@
 		tick-timer = &timer0;
 	};
 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x80000000>;
+	};
+
 	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
diff --git a/arch/arm/dts/mt7986a-rfb.dts b/arch/arm/dts/mt7986a-rfb.dts
index 80def57e1a..e5c9be7da8 100644
--- a/arch/arm/dts/mt7986a-rfb.dts
+++ b/arch/arm/dts/mt7986a-rfb.dts
@@ -18,6 +18,11 @@
 		tick-timer = &timer0;
 	};
 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
 	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
@@ -50,12 +55,12 @@
 &eth {
 	status = "okay";
 	mediatek,gmac-id = <0>;
-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 	mediatek,switch = "mt7531";
 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 
 	fixed-link {
-		speed = <1000>;
+		speed = <2500>;
 		full-duplex;
 	};
 };
diff --git a/arch/arm/dts/mt7986a-sd-rfb.dts b/arch/arm/dts/mt7986a-sd-rfb.dts
index 5807c5d5cc..4f8fa70ec9 100644
--- a/arch/arm/dts/mt7986a-sd-rfb.dts
+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
@@ -19,6 +19,11 @@
 		tick-timer = &timer0;
 	};
 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
 	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
@@ -42,12 +47,12 @@
 &eth {
 	status = "okay";
 	mediatek,gmac-id = <0>;
-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 	mediatek,switch = "mt7531";
 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 
 	fixed-link {
-		speed = <1000>;
+		speed = <2500>;
 		full-duplex;
 	};
 };
diff --git a/arch/arm/dts/mt7986b-rfb.dts b/arch/arm/dts/mt7986b-rfb.dts
index 0c4e3e878f..8196845a12 100644
--- a/arch/arm/dts/mt7986b-rfb.dts
+++ b/arch/arm/dts/mt7986b-rfb.dts
@@ -18,6 +18,11 @@
 		tick-timer = &timer0;
 	};
 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
 	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
@@ -41,12 +46,12 @@
 &eth {
 	status = "okay";
 	mediatek,gmac-id = <0>;
-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 	mediatek,switch = "mt7531";
 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 
 	fixed-link {
-		speed = <1000>;
+		speed = <2500>;
 		full-duplex;
 	};
 };
diff --git a/arch/arm/dts/mt7986b-sd-rfb.dts b/arch/arm/dts/mt7986b-sd-rfb.dts
index 48f9320e7a..ec80a2fb71 100644
--- a/arch/arm/dts/mt7986b-sd-rfb.dts
+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
@@ -19,6 +19,11 @@
 		tick-timer = &timer0;
 	};
 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
 	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
@@ -42,12 +47,12 @@
 &eth {
 	status = "okay";
 	mediatek,gmac-id = <0>;
-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 	mediatek,switch = "mt7531";
 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 
 	fixed-link {
-		speed = <1000>;
+		speed = <2500>;
 		full-duplex;
 	};
 };
diff --git a/arch/arm/dts/mt7988-rfb.dts b/arch/arm/dts/mt7988-rfb.dts
new file mode 100644
index 0000000000..2c11428430
--- /dev/null
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "mt7988-rfb";
+	compatible = "mediatek,mt7988-rfb";
+
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x10000000>;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+	mediatek,gmac-id = <0>;
+	phy-mode = "usxgmii";
+	mediatek,switch = "mt7988";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+		pause;
+	};
+};
+
+&pinctrl {
+	i2c1_pins: i2c1-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c1_0";
+		};
+	};
+
+	pwm_pins: pwm-pins {
+		mux {
+			function = "pwm";
+			groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
+				 "pwm5", "pwm6", "pwm7";
+		};
+	};
+
+	spi0_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+	};
+
+	spi2_pins: spi2-pins {
+		mux {
+			function = "spi";
+			groups = "spi2", "spi2_wp_hold";
+		};
+	};
+
+	mmc0_pins_default: mmc0default {
+		mux {
+			function = "flash";
+			groups =  "emmc_51";
+		};
+
+		conf-cmd-dat {
+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+			input-enable;
+		};
+
+		conf-clk {
+			pins = "EMMC_CK";
+		};
+
+		conf-dsl {
+			pins = "EMMC_DSL";
+		};
+
+		conf-rst {
+			pins = "EMMC_RSTB";
+		};
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	must_tx;
+	enhance_timing;
+	dma_ext;
+	ipm_design;
+	support_quad;
+	tick_dly = <2>;
+	sample_sel = <0>;
+
+	spi_nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+	};
+};
+
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	must_tx;
+	enhance_timing;
+	dma_ext;
+	ipm_design;
+	support_quad;
+	tick_dly = <2>;
+	sample_sel = <0>;
+
+	spi_nor@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_default>;
+	max-frequency = <52000000>;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	non-removable;
+	status = "okay";
+};
diff --git a/arch/arm/dts/mt7988-sd-rfb.dts b/arch/arm/dts/mt7988-sd-rfb.dts
new file mode 100644
index 0000000000..a3df37d252
--- /dev/null
+++ b/arch/arm/dts/mt7988-sd-rfb.dts
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "mt7988-rfb";
+	compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb";
+
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x10000000>;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+	mediatek,gmac-id = <0>;
+	phy-mode = "usxgmii";
+	mediatek,switch = "mt7988";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+		pause;
+	};
+};
+
+&pinctrl {
+	i2c1_pins: i2c1-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c1_0";
+		};
+	};
+
+	pwm_pins: pwm-pins {
+		mux {
+			function = "pwm";
+			groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
+				 "pwm5", "pwm6", "pwm7";
+		};
+	};
+
+	spi0_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+	};
+
+	mmc1_pins_default: mmc1default {
+		mux {
+			function = "flash";
+			groups =  "emmc_45";
+		};
+
+		conf-cmd-dat {
+			pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
+			       "SPI2_CLK", "SPI2_HOLD";
+			input-enable;
+		};
+
+		conf-clk {
+			pins = "SPI2_WP";
+		};
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	must_tx;
+	enhance_timing;
+	dma_ext;
+	ipm_design;
+	support_quad;
+	tick_dly = <2>;
+	sample_sel = <0>;
+
+	spi_nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins_default>;
+	max-frequency = <52000000>;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/mt7988-u-boot.dtsi b/arch/arm/dts/mt7988-u-boot.dtsi
new file mode 100644
index 0000000000..43e00a36ef
--- /dev/null
+++ b/arch/arm/dts/mt7988-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+&system_clk {
+	bootph-all;
+};
+
+&spi_clk {
+	bootph-all;
+};
+
+&uart0 {
+	bootph-all;
+};
+
+&uart1 {
+	bootph-all;
+};
+
+&uart2 {
+	bootph-all;
+};
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
new file mode 100644
index 0000000000..ddd629e8c9
--- /dev/null
+++ b/arch/arm/dts/mt7988.dtsi
@@ -0,0 +1,391 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt7988-clk.h>
+#include <dt-bindings/reset/mt7988-reset.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "mediatek,mt7988-rfb";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x0>;
+			mediatek,hwver = <&hwver>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x1>;
+			mediatek,hwver = <&hwver>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x2>;
+			mediatek,hwver = <&hwver>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x3>;
+			mediatek,hwver = <&hwver>;
+		};
+	};
+
+	system_clk: dummy40m {
+		compatible = "fixed-clock";
+		clock-frequency = <40000000>;
+		#clock-cells = <0>;
+	};
+
+	spi_clk: dummy208m {
+		compatible = "fixed-clock";
+		clock-frequency = <208000000>;
+		#clock-cells = <0>;
+	};
+
+	hwver: hwver {
+		compatible = "mediatek,hwver", "syscon";
+		reg = <0 0x8000000 0 0x1000>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		clock-frequency = <13000000>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	watchdog: watchdog@1001c000 {
+		compatible = "mediatek,mt7622-wdt",
+			     "mediatek,mt6589-wdt",
+			     "syscon";
+		reg = <0 0x1001c000 0 0x1000>;
+		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+		#reset-cells = <1>;
+	};
+
+	gic: interrupt-controller@c000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		interrupt-controller;
+		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
+		      <0 0x0c080000 0 0x200000>; /* GICR */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
+		compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
+		reg = <0 0x10001000 0 0x1000>;
+		clock-parent = <&infracfg_ao>;
+		#clock-cells = <1>;
+	};
+
+	apmixedsys: apmixedsys@1001e000 {
+		compatible = "mediatek,mt7988-fixed-plls", "syscon";
+		reg = <0 0x1001e000 0 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	topckgen: topckgen@1001b000 {
+		compatible = "mediatek,mt7988-topckgen", "syscon";
+		reg = <0 0x1001b000 0 0x1000>;
+		clock-parent = <&apmixedsys>;
+		#clock-cells = <1>;
+	};
+
+	pinctrl: pinctrl@1001f000 {
+		compatible = "mediatek,mt7988-pinctrl";
+		reg = <0 0x1001f000 0 0x1000>,
+		      <0 0x11c10000 0 0x1000>,
+		      <0 0x11d00000 0 0x1000>,
+		      <0 0x11d20000 0 0x1000>,
+		      <0 0x11e00000 0 0x1000>,
+		      <0 0x11f00000 0 0x1000>,
+		      <0 0x1000b000 0 0x1000>;
+		reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
+			    "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
+			    "eint";
+		gpio: gpio-controller {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+
+	sgmiisys0: syscon@10060000 {
+		compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
+		reg = <0 0x10060000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	sgmiisys1: syscon@10070000 {
+		compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
+		reg = <0 0x10070000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	usxgmiisys0: syscon@10080000 {
+		compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
+		reg = <0 0x10080000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	usxgmiisys1: syscon@10081000 {
+		compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
+		reg = <0 0x10081000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	xfi_pextp0: syscon@11f20000 {
+		compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
+		reg = <0 0x11f20000 0 0x10000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	xfi_pextp1: syscon@11f30000 {
+		compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
+		reg = <0 0x11f30000 0 0x10000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	xfi_pll: syscon@11f40000 {
+		compatible = "mediatek,mt7988-xfi_pll", "syscon";
+		reg = <0 0x11f40000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	topmisc: topmisc@11d10000 {
+		compatible = "mediatek,mt7988-topmisc", "syscon",
+			     "mediatek,mt7988-power-controller";
+		reg = <0 0x11d10000 0 0x10000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	infracfg_ao: infracfg@10001000 {
+		compatible = "mediatek,mt7988-infracfg", "syscon";
+		reg = <0 0x10001000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	uart0: serial@11000000 {
+		compatible = "mediatek,hsuart";
+		reg = <0 0x11000000 0 0x100>;
+		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+				  <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+					 <&infracfg_ao CK_INFRA_UART_O0>;
+		status = "disabled";
+	};
+
+	uart1: serial@11000100 {
+		compatible = "mediatek,hsuart";
+		reg = <0 0x11000100 0 0x100>;
+		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+				  <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+					 <&infracfg_ao CK_INFRA_UART_O1>;
+		status = "disabled";
+	};
+
+	uart2: serial@11000200 {
+		compatible = "mediatek,hsuart";
+		reg = <0 0x11000200 0 0x100>;
+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+				  <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+					 <&infracfg_ao CK_INFRA_UART_O2>;
+		status = "disabled";
+	};
+
+	i2c0: i2c@11003000 {
+		compatible = "mediatek,mt7988-i2c",
+			     "mediatek,mt7981-i2c";
+		reg = <0 0x11003000 0 0x1000>,
+		      <0 0x10217080 0 0x80>;
+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+		clock-div = <1>;
+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@11004000 {
+		compatible = "mediatek,mt7988-i2c",
+			     "mediatek,mt7981-i2c";
+		reg = <0 0x11004000 0 0x1000>,
+		      <0 0x10217100 0 0x80>;
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+		clock-div = <1>;
+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@11005000 {
+		compatible = "mediatek,mt7988-i2c",
+			     "mediatek,mt7981-i2c";
+		reg = <0 0x11005000 0 0x1000>,
+		      <0 0x10217180 0 0x80>;
+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+		clock-div = <1>;
+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	pwm: pwm@10048000 {
+		compatible = "mediatek,mt7988-pwm";
+		reg = <0 0x10048000 0 0x1000>;
+		#pwm-cells = <2>;
+		clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
+		clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+			      "pwm4","pwm5","pwm6","pwm7","pwm8";
+		status = "disabled";
+	};
+
+	snand: snand@11001000 {
+		compatible = "mediatek,mt7988-snand",
+			     "mediatek,mt7986-snand";
+		reg = <0 0x11001000 0 0x1000>,
+		      <0 0x11002000 0 0x1000>;
+		reg-names = "nfi", "ecc";
+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao CK_INFRA_SPINFI>,
+			 <&infracfg_ao CK_INFRA_NFI>,
+			 <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
+		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
+		assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
+				  <&topckgen CK_TOP_NFI1X_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
+					 <&topckgen CK_TOP_CB_M_D8>;
+		status = "disabled";
+	};
+
+	spi0: spi@1100a000 {
+		compatible = "mediatek,ipm-spi";
+		reg = <0 0x11007000 0 0x100>;
+		clocks = <&spi_clk>,
+			 <&spi_clk>;
+		clock-names = "sel-clk", "spi-clk";
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	spi1: spi@1100b000 {
+		compatible = "mediatek,ipm-spi";
+		reg = <0 0x11008000 0 0x100>;
+		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	spi2: spi@11009000 {
+		compatible = "mediatek,ipm-spi";
+		reg = <0 0x11009000 0 0x100>;
+		clocks = <&spi_clk>,
+			 <&spi_clk>;
+		clock-names = "sel-clk", "spi-clk";
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	mmc0: mmc@11230000 {
+		compatible = "mediatek,mt7988-mmc",
+			     "mediatek,mt7986-mmc";
+		reg = <0 0x11230000 0 0x1000>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
+			 <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
+			 <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
+			 <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
+		clock-names = "source", "hclk", "source_cg", "axi_cg";
+		status = "disabled";
+	};
+
+	ethdma: syscon@15000000 {
+		compatible = "mediatek,mt7988-ethdma", "syscon";
+		reg = <0 0x15000000 0 0x20000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	ethwarp: syscon@15031000 {
+		compatible = "mediatek,mt7988-ethwarp", "syscon";
+		reg = <0 0x15031000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	eth: ethernet@15100000 {
+		compatible = "mediatek,mt7988-eth", "syscon";
+		reg = <0 0x15100000 0 0x20000>;
+		mediatek,ethsys = <&ethdma>;
+		mediatek,sgmiisys = <&sgmiisys0>;
+		mediatek,usxgmiisys = <&usxgmiisys0>;
+		mediatek,xfi_pextp = <&xfi_pextp0>;
+		mediatek,xfi_pll = <&xfi_pll>;
+		mediatek,infracfg = <&topmisc>;
+		mediatek,toprgu = <&watchdog>;
+		resets = <&ethdma ETHDMA_FE_RST>, <&ethwarp ETHWARP_GSW_RST>;
+		reset-names = "fe", "mcm";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mediatek,mcm;
+		status = "disabled";
+	};
+};
diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
index be2ad0cf6c..e49e564b79 100644
--- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
+++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
@@ -289,6 +289,23 @@
 			status = "disable";
 		};
 
+		aes: aes@f0858000 {
+			compatible = "nuvoton,npcm845-aes";
+			reg = <0x0 0xf0858000 0x0 0x1000>,
+			      <0x0 0xf0851000 0x0 0x1000>;
+			status = "disabled";
+			clocks = <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "clk_ahb";
+		};
+
+		sha:sha@f085a000 {
+			compatible = "nuvoton,npcm845-sha";
+			reg = <0x0 0xf085a000 0x0 0x1000>;
+			status = "disabled";
+			clocks = <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "clk_ahb";
+		};
+
 		apb {
 			serial0: serial@0 {
 				compatible = "nuvoton,npcm845-uart";
@@ -417,22 +434,6 @@
 				status = "disabled";
 			};
 
-			aes: aes@f0858000 {
-				compatible = "nuvoton,npcm845-aes";
-				reg = <0x0 0xf0858000 0x0 0x1000>,
-				<0x0 0xf0851000 0x0 0x1000>;
-				status = "disabled";
-				clocks = <&clk NPCM8XX_CLK_AHB>;
-				clock-names = "clk_ahb";
-			};
-
-			sha:sha@f085a000 {
-				compatible = "nuvoton,npcm845-sha";
-				reg = <0x0 0xf085a000 0x0 0x1000>;
-				status = "disabled";
-				clocks = <&clk NPCM8XX_CLK_AHB>;
-				clock-names = "clk_ahb";
-			};
 		};
 	};
 	pinctrl: pinctrl@f0800000 {
diff --git a/arch/arm/dts/r7s72100-gr-peach.dts b/arch/arm/dts/r7s72100-gr-peach.dts
index fe1a4aa4d7..70d034c26d 100644
--- a/arch/arm/dts/r7s72100-gr-peach.dts
+++ b/arch/arm/dts/r7s72100-gr-peach.dts
@@ -126,6 +126,8 @@
 	phy-handle = <&phy0>;
 
 	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0007.c0f0",
+			     "ethernet-phy-ieee802.3-c22";
 		reg = <0>;
 
 		reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/dts/r8a77970-v3msk-u-boot.dts b/arch/arm/dts/r8a77970-v3msk-u-boot.dts
new file mode 100644
index 0000000000..6ee06d7c00
--- /dev/null
+++ b/arch/arm/dts/r8a77970-v3msk-u-boot.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the V3MSK board
+ *
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ */
+
+#include "r8a77970-v3msk.dts"
+#include "r8a77970-u-boot.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	aliases {
+		spi0 = &rpc;
+	};
+
+	cpld {
+		compatible = "renesas,v3msk-cpld";
+		status = "okay";
+		gpio-mdc = <&gpio1 21 0>;
+		gpio-mosi = <&gpio1 22 0>;
+		gpio-miso = <&gpio1 23 0>;
+		gpio-enablez = <&gpio1 19 0>;
+		/* Disable V3MSK Videobox Mini CANFD PHY */
+		gpios = <&gpio0 12 0>, <&gpio0 14 0>;
+	};
+};
+
+&avb {
+	pinctrl-0 = <&avb0_pins>;
+	pinctrl-names = "default";
+
+};
+
+&phy0 {
+	reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+};
+
+&pfc {
+	avb0_pins: avb {
+		mux {
+			groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
+			function = "avb0";
+		};
+	};
+};
+
+&rpc {
+	num-cs = <1>;
+	status = "okay";
+	spi-max-frequency = <50000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	flash0: spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		status = "okay";
+	};
+};
diff --git a/arch/arm/dts/r8a77970-v3msk.dts b/arch/arm/dts/r8a77970-v3msk.dts
new file mode 100644
index 0000000000..c2b65f8de5
--- /dev/null
+++ b/arch/arm/dts/r8a77970-v3msk.dts
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the V3M Starter Kit board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77970.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Renesas V3M Starter Kit board";
+	compatible = "renesas,v3msk", "renesas,r8a77970";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		serial0 = &scif0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&adv7511_out>;
+			};
+		};
+	};
+
+	lvds-decoder {
+		compatible = "thine,thc63lvd1024";
+		vcc-supply = <&vcc_d3_3v>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				thc63lvd1024_in: endpoint {
+					remote-endpoint = <&lvds0_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				thc63lvd1024_out: endpoint {
+					remote-endpoint = <&adv7511_in>;
+				};
+			};
+		};
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x78000000>;
+	};
+
+	osc5_clk: osc5-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <148500000>;
+	};
+
+	vcc_d1_8v: regulator-0 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_D1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vcc_d3_3v: regulator-1 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_D3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vcc_vddq_vin0: regulator-2 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_VDDQ_VIN0";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&avb {
+	pinctrl-0 = <&avb_pins>;
+	pinctrl-names = "default";
+
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+	rx-internal-delay-ps = <1800>;
+	tx-internal-delay-ps = <2000>;
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0022.1622",
+			     "ethernet-phy-ieee802.3-c22";
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&du {
+	clocks = <&cpg CPG_MOD 724>,
+		 <&osc5_clk>;
+	clock-names = "du.0", "dclkin.0";
+	status = "okay";
+};
+
+&extal_clk {
+	clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	hdmi@39{
+		compatible = "adi,adv7511w";
+		#sound-dai-cells = <0>;
+		reg = <0x39>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+		avdd-supply = <&vcc_d1_8v>;
+		dvdd-supply = <&vcc_d1_8v>;
+		pvdd-supply = <&vcc_d1_8v>;
+		bgvdd-supply = <&vcc_d1_8v>;
+		dvdd-3v-supply = <&vcc_d3_3v>;
+
+		adi,input-depth = <8>;
+		adi,input-colorspace = "rgb";
+		adi,input-clock = "1x";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7511_in: endpoint {
+					remote-endpoint = <&thc63lvd1024_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				adv7511_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
+};
+
+&lvds0 {
+	status = "okay";
+
+	ports {
+		port@1 {
+			lvds0_out: endpoint {
+				remote-endpoint = <&thc63lvd1024_in>;
+			};
+		};
+	};
+};
+
+&mmc0 {
+	pinctrl-0 = <&mmc_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&vcc_d3_3v>;
+	vqmmc-supply = <&vcc_vddq_vin0>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&pfc {
+	avb_pins: avb0 {
+		groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
+		function = "avb0";
+	};
+
+	i2c0_pins: i2c0 {
+		groups = "i2c0";
+		function = "i2c0";
+	};
+
+	mmc_pins: mmc_3_3v {
+		groups = "mmc_data8", "mmc_ctrl";
+		function = "mmc";
+		power-source = <3300>;
+	};
+
+	qspi0_pins: qspi0 {
+		groups = "qspi0_ctrl", "qspi0_data4";
+		function = "qspi0";
+	};
+
+	scif0_pins: scif0 {
+		groups = "scif0_data";
+		function = "scif0";
+	};
+};
+
+&rpc {
+	pinctrl-0 = <&qspi0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash@0 {
+		compatible = "spansion,s25fs512s", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			bootparam@0 {
+				reg = <0x00000000 0x040000>;
+				read-only;
+			};
+			cr7@40000 {
+				reg = <0x00040000 0x080000>;
+				read-only;
+			};
+			cert_header_sa3@c0000 {
+				reg = <0x000c0000 0x080000>;
+				read-only;
+			};
+			bl2@140000 {
+				reg = <0x00140000 0x040000>;
+				read-only;
+			};
+			cert_header_sa6@180000 {
+				reg = <0x00180000 0x040000>;
+				read-only;
+			};
+			bl31@1c0000 {
+				reg = <0x001c0000 0x460000>;
+				read-only;
+			};
+			uboot@640000 {
+				reg = <0x00640000 0x0c0000>;
+				read-only;
+			};
+			uboot-env@700000 {
+				reg = <0x00700000 0x040000>;
+				read-only;
+			};
+			dtb@740000 {
+				reg = <0x00740000 0x080000>;
+			};
+			kernel@7c0000 {
+				reg = <0x007c0000 0x1400000>;
+			};
+			user@1bc0000 {
+				reg = <0x01bc0000 0x2440000>;
+			};
+		};
+	};
+};
+
+&scif0 {
+	pinctrl-0 = <&scif0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
diff --git a/arch/arm/dts/r8a77980-v3hsk-u-boot.dts b/arch/arm/dts/r8a77980-v3hsk-u-boot.dts
new file mode 100644
index 0000000000..d083df65f9
--- /dev/null
+++ b/arch/arm/dts/r8a77980-v3hsk-u-boot.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Eagle board
+ *
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ */
+
+#include "r8a77980-v3hsk.dts"
+#include "r8a77980-u-boot.dtsi"
+
+/ {
+	aliases {
+		spi0 = &rpc;
+	};
+};
+
+&rpc {
+	num-cs = <1>;
+	status = "okay";
+	spi-max-frequency = <50000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	flash0: spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		status = "okay";
+	};
+};
+
+&i2c0 {
+	cpld {
+		compatible = "renesas,v3hsk-cpld";
+		reg = <0x70>;
+		u-boot,i2c-offset-len = <2>;
+	};
+};
diff --git a/arch/arm/dts/r8a77980-v3hsk.dts b/arch/arm/dts/r8a77980-v3hsk.dts
new file mode 100644
index 0000000000..d168b0e774
--- /dev/null
+++ b/arch/arm/dts/r8a77980-v3hsk.dts
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the V3H Starter Kit board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77980.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Renesas V3H Starter Kit board";
+	compatible = "renesas,v3hsk", "renesas,r8a77980";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		serial0 = &scif0;
+		ethernet0 = &gether;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&adv7511_out>;
+			};
+		};
+	};
+
+	lvds-decoder {
+		compatible = "thine,thc63lvd1024";
+		vcc-supply = <&vcc3v3_d5>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				thc63lvd1024_in: endpoint {
+					remote-endpoint = <&lvds0_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				thc63lvd1024_out: endpoint {
+					remote-endpoint = <&adv7511_in>;
+				};
+			};
+		};
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0 0x48000000 0 0x78000000>;
+	};
+
+	osc1_clk: osc1-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <148500000>;
+	};
+
+	vcc1v8_d4: regulator-0 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC1V8_D4";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vcc3v3_d5: regulator-1 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC3V3_D5";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&du {
+	clocks = <&cpg CPG_MOD 724>,
+		 <&osc1_clk>;
+	clock-names = "du.0", "dclkin.0";
+	status = "okay";
+};
+
+&extal_clk {
+	clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
+&gether {
+	pinctrl-0 = <&gether_pins>;
+	pinctrl-names = "default";
+
+	phy-mode = "rgmii";
+	phy-handle = <&phy0>;
+	renesas,no-ether-link;
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0022.1622",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	hdmi@39 {
+		compatible = "adi,adv7511w";
+		#sound-dai-cells = <0>;
+		reg = <0x39>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+		avdd-supply = <&vcc1v8_d4>;
+		dvdd-supply = <&vcc1v8_d4>;
+		pvdd-supply = <&vcc1v8_d4>;
+		bgvdd-supply = <&vcc1v8_d4>;
+		dvdd-3v-supply = <&vcc3v3_d5>;
+
+		adi,input-depth = <8>;
+		adi,input-colorspace = "rgb";
+		adi,input-clock = "1x";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7511_in: endpoint {
+					remote-endpoint = <&thc63lvd1024_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				adv7511_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
+};
+
+&lvds0 {
+	status = "okay";
+
+	ports {
+		port@1 {
+			lvds0_out: endpoint {
+				remote-endpoint = <&thc63lvd1024_in>;
+			};
+		};
+	};
+};
+
+&pfc {
+	gether_pins: gether {
+		groups = "gether_mdio_a", "gether_rgmii",
+			 "gether_txcrefclk", "gether_txcrefclk_mega";
+		function = "gether";
+	};
+
+	i2c0_pins: i2c0 {
+		groups = "i2c0";
+		function = "i2c0";
+	};
+
+	qspi0_pins: qspi0 {
+		groups = "qspi0_ctrl", "qspi0_data4";
+		function = "qspi0";
+	};
+
+	scif0_pins: scif0 {
+		groups = "scif0_data";
+		function = "scif0";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk_b";
+		function = "scif_clk";
+	};
+};
+
+&rpc {
+	pinctrl-0 = <&qspi0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash@0 {
+		compatible = "spansion,s25fs512s", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			bootparam@0 {
+				reg = <0x00000000 0x040000>;
+				read-only;
+			};
+			cr7@40000 {
+				reg = <0x00040000 0x080000>;
+				read-only;
+			};
+			cert_header_sa3@c0000 {
+				reg = <0x000c0000 0x080000>;
+				read-only;
+			};
+			bl2@140000 {
+				reg = <0x00140000 0x040000>;
+				read-only;
+			};
+			cert_header_sa6@180000 {
+				reg = <0x00180000 0x040000>;
+				read-only;
+			};
+			bl31@1c0000 {
+				reg = <0x001c0000 0x460000>;
+				read-only;
+			};
+			uboot@640000 {
+				reg = <0x00640000 0x0c0000>;
+				read-only;
+			};
+			uboot-env@700000 {
+				reg = <0x00700000 0x040000>;
+				read-only;
+			};
+			dtb@740000 {
+				reg = <0x00740000 0x080000>;
+			};
+			kernel@7c0000 {
+				reg = <0x007c0000 0x1400000>;
+			};
+			user@1bc0000 {
+				reg = <0x01bc0000 0x2440000>;
+			};
+		};
+	};
+};
+
+&rwdt {
+	timeout-sec = <60>;
+	status = "okay";
+};
+
+&scif0 {
+	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&scif_clk {
+	clock-frequency = <14745600>;
+};
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
index 1920698884..c4c5a2d225 100644
--- a/arch/arm/dts/rk3288-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-u-boot.dtsi
@@ -4,7 +4,6 @@
  */
 
 #include "rockchip-u-boot.dtsi"
-#include "rockchip-optee.dtsi"
 
 / {
 	aliases {
diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
index 90ce9e1395..6bfa84906e 100644
--- a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
@@ -5,6 +5,20 @@
 
 #include "rk3288-veyron-u-boot.dtsi"
 
+/ {
+	sound {
+		compatible = "rockchip,audio-max98090-jerry";
+
+		cpu {
+			sound-dai = <&i2s 0>;
+		};
+
+		codec {
+			sound-dai = <&max98090 0>;
+		};
+	};
+};
+
 &dmc {
 	rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
 		0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
@@ -15,19 +29,3 @@
 		0x0 0xc3 0x6 0x1>;
 	rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>;
 };
-
-&sdmmc {
-	bootph-all;
-};
-
-&emmc {
-	bootph-all;
-};
-
-&uart2 {
-	bootph-all;
-};
-
-&pinctrl {
-	bootph-all;
-};
diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
index ab564e73ed..4f9c59c675 100644
--- a/arch/arm/dts/rk3288-veyron-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
@@ -31,6 +31,10 @@
 	>;
 };
 
+&emmc {
+	bootph-all;
+};
+
 &gpio3 {
 	bootph-all;
 };
diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
index a27a3adc08..d88dee8057 100644
--- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
@@ -6,12 +6,37 @@
 
 / {
 	chosen {
-		u-boot,spl-boot-order = "same-as-spl", &emmc;
+		u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc;
 	};
 };
 
 &uart0 {
 	bootph-all;
-	clock-frequency = <24000000>;
-	status = "okay";
+};
+
+&pinctrl {
+	bootph-some-ram;
+
+	uart0 {
+		bootph-some-ram;
+	};
+	rtc {
+		bootph-some-ram;
+	};
+};
+
+&uart0_xfer {
+	bootph-some-ram;
+};
+
+&uart0_cts {
+	bootph-some-ram;
+};
+
+&uart0_rts {
+	bootph-some-ram;
+};
+
+&rtc_32k {
+	bootph-some-ram;
 };
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi
index c8451b2475..db2c20a705 100644
--- a/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-u-boot.dtsi
@@ -26,6 +26,11 @@
 	bootph-all;
 };
 
+&sdmmc {
+	bootph-all;
+	u-boot,spl-fifo-mode;
+};
+
 &grf {
 	bootph-all;
 };
diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi
index a5c0b72ae0..9a152a8a90 100644
--- a/arch/arm/dts/rk3308.dtsi
+++ b/arch/arm/dts/rk3308.dtsi
@@ -584,7 +584,7 @@
 		status = "disabled";
 	};
 
-	sdmmc: dwmmc@ff480000 {
+	sdmmc: mmc@ff480000 {
 		compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xff480000 0x0 0x4000>;
 		max-frequency = <150000000>;
@@ -599,7 +599,7 @@
 		status = "disabled";
 	};
 
-	emmc: dwmmc@ff490000 {
+	emmc: mmc@ff490000 {
 		compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xff490000 0x0 0x4000>;
 		max-frequency = <150000000>;
@@ -612,7 +612,7 @@
 		status = "disabled";
 	};
 
-	sdio: dwmmc@ff4a0000 {
+	sdio: mmc@ff4a0000 {
 		compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xff4a0000 0x0 0x4000>;
 		max-frequency = <150000000>;
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 4bfa0c2330..12b68df1ac 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -41,11 +41,6 @@
 };
 
 &gmac2phy {
-	/* Integrated PHY unsupported by U-boot */
+	/* Integrated PHY unsupported by U-Boot */
 	status = "broken";
 };
-
-&usb_host0_xhci {
-	vbus-supply = <&vcc5v0_host_xhci>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
new file mode 100644
index 0000000000..ebe33e48cb
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2020 David Bauer
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-lpddr3-666.dtsi"
+/ {
+	chosen {
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+	};
+};
+
+&gpio0 {
+	bootph-pre-ram;
+};
+
+&pinctrl {
+	bootph-pre-ram;
+};
+
+&sdmmc0m1_pin {
+	bootph-pre-ram;
+};
+
+&pcfg_pull_up_4ma {
+	bootph-pre-ram;
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+&vcc_sd {
+	bootph-pre-ram;
+};
+
+&gmac2io {
+	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+};
+
+&spi0 {
+	spi_flash: spiflash@0 {
+		bootph-all;
+	};
+};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
new file mode 100644
index 0000000000..5d7d567283
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
+ * (http://www.orangepi.org)
+ *
+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
+ */
+
+/dts-v1/;
+#include "rk3328-orangepi-r1-plus.dts"
+
+/ {
+	model = "Xunlong Orange Pi R1 Plus LTS";
+	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
+};
+
+&gmac2io {
+	phy-handle = <&yt8531c>;
+	tx_delay = <0x19>;
+	rx_delay = <0x05>;
+
+	mdio {
+		/delete-node/ ethernet-phy@1;
+
+		yt8531c: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+
+			motorcomm,clk-out-frequency-hz = <125000000>;
+			motorcomm,keep-pll-enabled;
+			motorcomm,auto-sleep-disabled;
+
+			pinctrl-0 = <&eth_phy_reset_pin>;
+			pinctrl-names = "default";
+			reset-assert-us = <15000>;
+			reset-deassert-us = <50000>;
+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
new file mode 100644
index 0000000000..637c70adf1
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2020 David Bauer
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr4-666.dtsi"
+/ {
+	chosen {
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+	};
+};
+
+&gpio0 {
+	bootph-pre-ram;
+};
+
+&pinctrl {
+	bootph-pre-ram;
+};
+
+&sdmmc0m1_pin {
+	bootph-pre-ram;
+};
+
+&pcfg_pull_up_4ma {
+	bootph-pre-ram;
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+&vcc_sd {
+	bootph-pre-ram;
+};
+
+&gmac2io {
+	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+};
+
+&spi0 {
+	spi_flash: spiflash@0 {
+		bootph-all;
+	};
+};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
new file mode 100644
index 0000000000..dc83d74045
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Based on rk3328-nanopi-r2s.dts, which is:
+ *   Copyright (c) 2020 David Bauer <mail@david-bauer.net>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3328.dtsi"
+
+/ {
+	model = "Xunlong Orange Pi R1 Plus";
+	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
+
+	aliases {
+		ethernet1 = &rtl8153;
+		mmc0 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac_clk: gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac_clkin";
+		#clock-cells = <0>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
+		pinctrl-names = "default";
+
+		led-0 {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-1 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		led-2 {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&sdmmc0m1_pin>;
+		pinctrl-names = "default";
+		regulator-name = "vcc_sd";
+		regulator-boot-on;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_sys: vcc-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vdd_5v_lan: vdd-5v-lan-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&lan_vdd_pin>;
+		pinctrl-names = "default";
+		regulator-name = "vdd_5v_lan";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&display_subsystem {
+	status = "disabled";
+};
+
+&gmac2io {
+	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
+	clock_in_out = "input";
+	phy-handle = <&rtl8211e>;
+	phy-mode = "rgmii";
+	phy-supply = <&vcc_io>;
+	pinctrl-0 = <&rgmiim1_pins>;
+	pinctrl-names = "default";
+	snps,aal;
+	rx_delay = <0x18>;
+	tx_delay = <0x24>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtl8211e: ethernet-phy@1 {
+			reg = <1>;
+			pinctrl-0 = <&eth_phy_reset_pin>;
+			pinctrl-names = "default";
+			reset-assert-us = <10000>;
+			reset-deassert-us = <50000>;
+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	rk805: pmic@18 {
+		compatible = "rockchip,rk805";
+		reg = <0x18>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk805-clkout2";
+		gpio-controller;
+		#gpio-cells = <2>;
+		pinctrl-0 = <&pmic_int_l>;
+		pinctrl-names = "default";
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc5-supply = <&vcc_io>;
+		vcc6-supply = <&vcc_sys>;
+
+		regulators {
+			vdd_log: DCDC_REG1 {
+				regulator-name = "vdd_log";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vdd_arm: DCDC_REG2 {
+				regulator-name = "vdd_arm";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <950000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_io: DCDC_REG4 {
+				regulator-name = "vcc_io";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_18: LDO_REG1 {
+				regulator-name = "vcc_18";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc18_emmc: LDO_REG2 {
+				regulator-name = "vcc18_emmc";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_10: LDO_REG3 {
+				regulator-name = "vdd_10";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+		};
+	};
+};
+
+&io_domains {
+	pmuio-supply = <&vcc_io>;
+	vccio1-supply = <&vcc_io>;
+	vccio2-supply = <&vcc18_emmc>;
+	vccio3-supply = <&vcc_io>;
+	vccio4-supply = <&vcc_io>;
+	vccio5-supply = <&vcc_io>;
+	vccio6-supply = <&vcc_io>;
+	status = "okay";
+};
+
+&pinctrl {
+	gmac2io {
+		eth_phy_reset_pin: eth-phy-reset-pin {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	leds {
+		lan_led_pin: lan-led-pin {
+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		sys_led_pin: sys-led-pin {
+			rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wan_led_pin: wan-led-pin {
+			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	lan {
+		lan_vdd_pin: lan-vdd-pin {
+			rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+	pinctrl-names = "default";
+	vmmc-supply = <&vcc_sd>;
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <0>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&u2phy {
+	status = "okay";
+};
+
+&u2phy_host {
+	status = "okay";
+};
+
+&u2phy_otg {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb20_otg {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbdrd3 {
+	dr_mode = "host";
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* Second port is for USB 3.0 */
+	rtl8153: device@2 {
+		compatible = "usbbda,8153";
+		reg = <2>;
+	};
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
index 27a454f017..2062f34bf8 100644
--- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -48,20 +48,6 @@
 	bootph-pre-ram;
 };
 
-&usb_host0_xhci {
-	vbus-supply = <&vcc_host1_5v>;
-	status = "okay";
-};
-
-/*
- * This makes XHCI responsible for toggling VBUS. This is needed to work
- * around an issue where either XHCI only works with USB 2.0 or OTG doesn't
- * work, depending on how VBUS is configured. Having USB 3.0 seems better.
- */
-&vcc_host1_5v {
-	/delete-property/ regulator-always-on;
-};
-
 /* Need this and all the pinctrl/gpio stuff above to set pinmux */
 &vcc_sd {
 	bootph-pre-ram;
diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
index 088e21c76a..1f220c6dcd 100644
--- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
@@ -45,11 +45,6 @@
 	bootph-pre-ram;
 };
 
-&usb_host0_xhci {
-	vbus-supply = <&vcc_host_5v>;
-	status = "okay";
-};
-
 /* Need this and all the pinctrl/gpio stuff above to set pinmux */
 &vcc_sd {
 	bootph-pre-ram;
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
index c20a99a620..6904515b96 100644
--- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
@@ -48,28 +48,13 @@
 	bootph-pre-ram;
 };
 
-&usb_host0_xhci {
-	vbus-supply = <&vcc_host_5v>;
-	status = "okay";
-};
-
-/*
- * This makes XHCI responsible for toggling VBUS. This is needed to work
- * around an issue where either XHCI only works with USB 2.0 or OTG doesn't
- * work, depending on how VBUS is configured. Having USB 3.0 seems better.
- */
-&vcc_host_5v {
-	/delete-property/ regulator-always-on;
-	/delete-property/ regulator-boot-on;
-};
-
 /* Need this and all the pinctrl/gpio stuff above to set pinmux */
 &vcc_sd {
 	bootph-pre-ram;
 };
 
 &spi0 {
-	spi_flash: spiflash@0 {
+	spi_flash: flash@0 {
 		bootph-all;
 	};
 };
diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts
index 1b0f7e4551..f69a38f42d 100644
--- a/arch/arm/dts/rk3328-rock64.dts
+++ b/arch/arm/dts/rk3328-rock64.dts
@@ -345,7 +345,7 @@
 &spi0 {
 	status = "okay";
 
-	spiflash@0 {
+	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index 668f8ca29d..a9f2536de2 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -27,15 +27,10 @@
 		       0x0 0xff798000 0x0 0x1000>;
 	};
 
-	usb_host0_xhci: usb@ff600000 {
-		compatible = "rockchip,rk3328-xhci";
-		reg = <0x0 0xff600000 0x0 0x100000>;
-		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-		snps,dis-enblslpm-quirk;
-		snps,phyif-utmi-bits = <16>;
-		snps,dis-u2-freeclk-exists-quirk;
-		snps,dis-u2-susphy-quirk;
-		status = "disabled";
+	rng: rng@ff060000 {
+		compatible = "rockchip,cryptov1-rng";
+		reg = <0x0 0xff060000 0x0 0x4000>;
+		status = "okay";
 	};
 };
 
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 27e45d5886..e8d8f00be8 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -984,7 +984,7 @@
 	};
 
 	/*
-	 * U-boot Specific Change
+	 * U-Boot Specific Change
 	 *
 	 * The OTG controller must come after the USB host pair for it
 	 * to work. This is likely due to lack of support for the USB
diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
index ea7a5a17ae..88a77cad8d 100644
--- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
@@ -10,10 +10,6 @@
 	chosen {
 		u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc;
 	};
-
-	config {
-		u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
-	};
 };
 
 &edp {
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
index 347243fe47..cabf0a9dae 100644
--- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
@@ -10,10 +10,6 @@
 	chosen {
 		u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
 	};
-
-	config {
-		u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
-	};
 };
 
 &rng {
diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
index f85e7b62d9..c8f4418a73 100644
--- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
@@ -11,10 +11,6 @@
 		u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdhci, &sdmmc;
 	};
 
-	config {
-		u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
-	};
-
 	vcc_hub_en: vcc_hub_en-regulator {
 		compatible = "regulator-fixed";
 		enable-active-high;
diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts b/arch/arm/dts/rk3399-rock-4c-plus.dts
index 028eb508ae..8bfd5f88d1 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus.dts
+++ b/arch/arm/dts/rk3399-rock-4c-plus.dts
@@ -548,9 +548,8 @@
 &sdhci {
 	max-frequency = <150000000>;
 	bus-width = <8>;
-	mmc-hs400-1_8v;
+	mmc-hs200-1_8v;
 	non-removable;
-	mmc-hs400-enhanced-strobe;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
new file mode 100644
index 0000000000..85ee5770ad
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-rock-pi-4-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-rock-4se.dts b/arch/arm/dts/rk3399-rock-4se.dts
new file mode 100644
index 0000000000..7cfc198bba
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock-4se.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
+ * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
+ */
+
+/dts-v1/;
+#include "rk3399-rock-pi-4.dtsi"
+#include "rk3399-t-opp.dtsi"
+
+/ {
+	model = "Radxa ROCK 4SE";
+	compatible = "radxa,rock-4se", "rockchip,rk3399";
+
+	aliases {
+		mmc2 = &sdio0;
+	};
+};
+
+&pinctrl {
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdio0 {
+	status = "okay";
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm4329-fmac";
+		reg = <1>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+		clocks = <&rk808 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		max-speed = <1500000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+	};
+};
+
+&vcc5v0_host {
+	enable-active-high;
+	gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&vcc5v0_host_en>;
+};
diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi b/arch/arm/dts/rk3399-rock-pi-4.dtsi
index 907071d4fe..b1b7f4ffb1 100644
--- a/arch/arm/dts/rk3399-rock-pi-4.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi
@@ -9,7 +9,6 @@
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/pwm/pwm.h>
 #include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
 
 / {
 	aliases {
@@ -645,9 +644,9 @@
 };
 
 &sdhci {
+	max-frequency = <150000000>;
 	bus-width = <8>;
-	mmc-hs400-1_8v;
-	mmc-hs400-enhanced-strobe;
+	mmc-hs200-1_8v;
 	non-removable;
 	status = "okay";
 };
diff --git a/arch/arm/dts/rk3399-rock-pi-4a.dts b/arch/arm/dts/rk3399-rock-pi-4a.dts
index 89f2af5e11..931334aa3d 100644
--- a/arch/arm/dts/rk3399-rock-pi-4a.dts
+++ b/arch/arm/dts/rk3399-rock-pi-4a.dts
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include "rk3399-rock-pi-4.dtsi"
+#include "rk3399-opp.dtsi"
 
 / {
 	model = "Radxa ROCK Pi 4A";
diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts b/arch/arm/dts/rk3399-rock-pi-4c.dts
index 4053ba7261..d32efab74e 100644
--- a/arch/arm/dts/rk3399-rock-pi-4c.dts
+++ b/arch/arm/dts/rk3399-rock-pi-4c.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 #include "rk3399-rock-pi-4.dtsi"
+#include "rk3399-opp.dtsi"
 
 / {
 	model = "Radxa ROCK Pi 4C";
diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
index bd864d0670..732727d9b0 100644
--- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
@@ -9,10 +9,6 @@
 	chosen {
 		u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci;
 	};
-
-	config {
-		u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
-	};
 };
 
 &sdhci {
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
index a18e5d1cf7..f986e1941e 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
@@ -46,7 +46,17 @@
 			<&pmucru CLK_RTC32K_FRAC>;
 };
 
+&dsi_dphy0 {
+	status = "okay";
+};
+
+&dsi0 {
+	status = "okay";
+};
+
 &i2c2 {
+	pinctrl-0 = <&i2c2m1_xfer>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
new file mode 100644
index 0000000000..06cc15ed21
--- /dev/null
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&gpio0 {
+	bootph-all;
+};
+
+&sdhci {
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&sfc {
+	bootph-pre-ram;
+	u-boot,spl-sfc-no-dma;
+
+	flash@0 {
+		bootph-pre-ram;
+	};
+};
+
+&uart2 {
+	bootph-all;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
+
+/*
+ * U-Boot does not support multiple regulators using the same gpio,
+ * use vcc5v0_usb20_host to fix use of USB 2.0 port
+ */
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb20_host>;
+};
+
+&vcc3v3_sd {
+	bootph-pre-ram;
+};
+
+&vcc_sd_h {
+	bootph-all;
+};
diff --git a/arch/arm/dts/rk3566-quartz64-a.dts b/arch/arm/dts/rk3566-quartz64-a.dts
new file mode 100644
index 0000000000..25a8c781f4
--- /dev/null
+++ b/arch/arm/dts/rk3566-quartz64-a.dts
@@ -0,0 +1,839 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "Pine64 RK3566 Quartz64-A Board";
+	compatible = "pine64,quartz64-a", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	fan: gpio_fan {
+		compatible = "gpio-fan";
+		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		gpio-fan,speed-map = <0    0
+				      4500 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fan_en_h>;
+		#cooling-cells = <2>;
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-work {
+			label = "work-led";
+			default-state = "off";
+			gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&work_led_enable_h>;
+			retain-state-suspended;
+		};
+
+		led-diy {
+			label = "diy-led";
+			default-state = "on";
+			gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&diy_led_enable_h>;
+			retain-state-suspended;
+		};
+	};
+
+	rk817-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK817";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk817>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk817 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <5000000>;
+		reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+	};
+
+	spdif_dit: spdif-dit {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	spdif_sound: spdif-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "SPDIF";
+
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&spdif_dit>;
+		};
+	};
+
+	vcc12v_dcin: vcc12v_dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	/* vbus feeds the rk817 usb input.
+	 * With no battery attached, also feeds vcc_bat+
+	 * via ON/OFF_BAT jumper
+	 */
+	vbus: vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_enable_h>;
+		regulator-name = "vcc3v3_pcie_p";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3>;
+	};
+
+	vcc5v0_usb: vcc5v0_usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	/* all four ports are controlled by one gpio
+	 * the host ports are sourced from vcc5v0_usb
+	 * the otg port is sourced from vcc5v0_midu
+	 */
+	vcc5v0_usb20_host: vcc5v0_usb20_host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb20_host_en>;
+		regulator-name = "vcc5v0_usb20_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_usb20_otg: vcc5v0_usb20_otg {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc5v0_usb20_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dcdc_boost>;
+	};
+
+	vcc3v3_sd: vcc3v3_sd {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_sd_h>;
+		regulator-boot-on;
+		regulator-name = "vcc3v3_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3>;
+	};
+
+	/* sourced from vbus and vcc_bat+ via rk817 sw5 */
+	vcc_sys: vcc_sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <4400000>;
+		regulator-max-microvolt = <4400000>;
+		vin-supply = <&vbus>;
+	};
+
+	/* sourced from vcc_sys, sdio module operates internally at 3.3v */
+	vcc_wl: vcc_wl {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_wl";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sys>;
+	};
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_thermal {
+	trips {
+		cpu_hot: cpu_hot {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map1 {
+			trip = <&cpu_hot>;
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_3v3>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m0_miim
+		     &gmac1m0_tx_bus2
+		     &gmac1m0_rx_bus2
+		     &gmac1m0_rgmii_clk
+		     &gmac1m0_clkinout
+		     &gmac1m0_rgmii_bus>;
+	snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda_0v9>;
+	avdd-1v8-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk817: pmic@20 {
+		compatible = "rockchip,rk817";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		#clock-cells = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+		rockchip,system-power-controller;
+		#sound-dai-cells = <0>;
+		wakeup-source;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc5-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc_sys>;
+		vcc9-supply = <&dcdc_boost>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_logic";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_gpu";
+					regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_3v3: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_3v3";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_acodec";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc1v8_dvp";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc2v8_dvp: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-name = "vcc2v8_dvp";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			dcdc_boost: BOOST {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5000000>;
+				regulator-name = "boost";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			otg_switch: OTG_SWITCH {
+				regulator-name = "otg_switch";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+/* i2c3 is exposed on con40
+ * pin 3 - i2c3_sda_m0, pullup to vcc_3v3
+ * pin 5 - i2c3_scl_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+	status = "okay";
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx
+		     &i2s1m0_lrcktx
+		     &i2s1m0_sdi0
+		     &i2s1m0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie_p>;
+	status = "okay";
+};
+
+&pinctrl {
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	fan {
+		fan_en_h: fan-en-h {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		work_led_enable_h: work-led-enable-h {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		diy_led_enable_h: diy-led-enable-h {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_enable_h: pcie-enable-h {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb2 {
+		vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
+			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	vcc_sd {
+		vcc_sd_h: vcc-sd-h {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc1v8_dvp>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	non-removable;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_wl>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sfc {
+	pinctrl-0 = <&fspi_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+/* spdif is exposed on con40 pin 18 */
+&spdif {
+	status = "okay";
+};
+
+/* spi1 is exposed on con40
+ * pin 11 - spi1_mosi_m1
+ * pin 13 - spi1_miso_m1
+ * pin 15 - spi1_clk_m1
+ * pin 17 - spi1_cs0_m1
+ */
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+/* uart0 is exposed on con40
+ * pin 12 - uart0_tx
+ * pin 14 - uart0_rx
+ */
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	status = "okay";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk817 1>;
+		clock-names = "lpo";
+		host-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		device-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc_sys>;
+		vddio-supply = <&vcca1v8_pmu>;
+		max-speed = <3000000>;
+	};
+};
+
+/* uart2 is exposed on con40
+ * pin 8 - uart2_tx_m0_debug
+ * pin 10 - uart2_rx_m0_debug
+ */
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+/* usb3 controller is muxed with sata1 */
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb20_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb20_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb20_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb20_host>;
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
new file mode 100644
index 0000000000..3c2c54e941
--- /dev/null
+++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&sdhci {
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&sfc {
+	bootph-pre-ram;
+	u-boot,spl-sfc-no-dma;
+
+	flash@0 {
+		bootph-pre-ram;
+	};
+};
+
+&uart2 {
+	bootph-all;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+};
+
+&vcc5v0_usb30_host {
+	/delete-property/ regulator-always-on;
+};
+
+&vcc5v0_usb_otg {
+	/delete-property/ regulator-always-on;
+};
diff --git a/arch/arm/dts/rk3566-quartz64-b.dts b/arch/arm/dts/rk3566-quartz64-b.dts
new file mode 100644
index 0000000000..b276eb0810
--- /dev/null
+++ b/arch/arm/dts/rk3566-quartz64-b.dts
@@ -0,0 +1,739 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "Pine64 RK3566 Quartz64-B Board";
+	compatible = "pine64,quartz64-b", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+		mmc2 = &sdmmc1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-user {
+			label = "user-led";
+			default-state = "on";
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&user_led_enable_h>;
+			retain-state-suspended;
+		};
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		status = "okay";
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <5000000>;
+	};
+
+	vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_enable_h>;
+		regulator-name = "vcc3v3_pcie_p";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3>;
+	};
+
+	vcc5v0_in: vcc5v0-in-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_in";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_in>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb30_host";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb30_host_en_h>;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_otg";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en_h>;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+	clock_in_out = "input";
+	phy-mode = "rgmii";
+	phy-supply = <&vcc_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_clkinout
+		     &gmac1m1_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f, also works well here */
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x4f>;
+	rx_delay = <0x24>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+		rockchip,system-power-controller;
+		#sound-dai-cells = <0>;
+		wakeup-source;
+		#clock-cells = <1>;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_log: DCDC_REG1 {
+				regulator-name = "vdd_log";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-boot-on;
+				regulator-name = "vcc_3v3";
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+			};
+		};
+	};
+};
+
+/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2m1_xfer>;
+	status = "okay";
+};
+
+/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3m1_xfer>;
+	status = "okay";
+};
+
+/*
+ * i2c4_m0 is exposed on PI40, pulled up to vcc_3v3
+ * pin 27 - i2c4_sda_m0
+ * pin 28 - i2c4_scl_m0
+ */
+&i2c4 {
+	status = "okay";
+};
+
+/*
+ * i2c5_m0 is exposed on PI40
+ * pin 29 - i2c5_scl_m0
+ * pin 31 - i2c5_sda_m0
+ */
+&i2c5 {
+	status = "disabled";
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx
+		     &i2s1m0_lrcktx
+		     &i2s1m0_sdi0
+		     &i2s1m0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+	};
+};
+
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie_p>;
+	status = "okay";
+};
+
+&pinctrl {
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		user_led_enable_h: user-led-enable-h {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_enable_h: pcie-enable-h {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcca1v8_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcca1v8_pmu>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	non-removable;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr50;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	vmmc-supply = <&vcc3v3_sys>;
+	vqmmc-supply = <&vcca1v8_pmu>;
+	status = "okay";
+};
+
+&sfc {
+	pinctrl-0 = <&fspi_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	status = "okay";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+		clocks = <&rk809 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcca1v8_pmu>;
+	};
+};
+
+/*
+ * uart2_m0 is exposed on PI40
+ * pin 8  - uart2_tx_m0
+ * pin 10 - uart2_rx_m0
+ */
+&uart2 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb30_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb30_host>;
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index f91740c1c0..c925439f71 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -11,73 +11,13 @@
 	};
 };
 
-&emmc_bus8 {
-	bootph-all;
-};
-
-&emmc_clk {
-	bootph-all;
-};
-
-&emmc_cmd {
-	bootph-all;
-};
-
-&emmc_datastrobe {
-	bootph-all;
-};
-
-&pinctrl {
-	bootph-all;
-};
-
-&pcfg_pull_none {
-	bootph-all;
-};
-
-&pcfg_pull_up_drv_level_2 {
-	bootph-all;
-};
-
-&pcfg_pull_up {
-	bootph-all;
-};
-
-&sdmmc0_bus4 {
-	bootph-all;
-};
-
-&sdmmc0_clk {
-	bootph-all;
-};
-
-&sdmmc0_cmd {
-	bootph-all;
-};
-
-&sdmmc0_det {
-	bootph-all;
-};
-
-&sdmmc0_pwren {
-	bootph-all;
-};
-
 &sdhci {
 	cap-mmc-highspeed;
 	mmc-ddr-1_8v;
 };
 
-&uart2m0_xfer {
-	bootph-all;
-};
-
 &uart2 {
 	clock-frequency = <24000000>;
 	bootph-all;
 	status = "okay";
 };
-
-&vcc5v0_usb30 {
-	regulator-boot-on;
-};
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts b/arch/arm/dts/rk3566-radxa-cm3-io.dts
index d89d5263cb..5e4236af4f 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io.dts
+++ b/arch/arm/dts/rk3566-radxa-cm3-io.dts
@@ -254,6 +254,14 @@
 	status = "okay";
 };
 
+&usb2phy0_otg {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	status = "okay";
+};
+
 &vop {
 	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
 	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
diff --git a/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi
new file mode 100644
index 0000000000..0e662eafa4
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3566-soquartz-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3566-soquartz-blade.dts b/arch/arm/dts/rk3566-soquartz-blade.dts
new file mode 100644
index 0000000000..4e49bebf54
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-blade.dts
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+#include "rk3566-soquartz.dtsi"
+
+/ {
+	model = "PINE64 RK3566 SOQuartz on Blade carrier board";
+	compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566";
+
+	/* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */
+	vcc3v0_sd: vcc3v0-sd-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v0_sd";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	/* labeled VCC_SSD in schematic */
+	vcc3v3_pcie_p: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie_p";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc5v_dcin: vcc5v-dcin-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};
+
+&combphy2 {
+	phy-supply = <&vcc3v3_sys>;
+	status = "okay";
+};
+
+&gmac1 {
+	status = "okay";
+};
+
+/*
+ * i2c1 is exposed on CM1 / Module1A
+ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+	status = "okay";
+
+};
+
+/*
+ * i2c2 is exposed on CM1 / Module1A - to PI40
+ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+	status = "disabled";
+};
+
+/*
+ * i2c3 is exposed on CM1 / Module1A - to PI40
+ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+	status = "disabled";
+};
+
+/*
+ * i2c4 is exposed on CM2 / Module1B - to PI40
+ * pin 45 - GPIO24 - i2c4_scl_m1
+ * pin 47 - GPIO23 - i2c4_sda_m1
+ */
+&i2c4 {
+	status = "disabled";
+};
+
+/*
+ * i2s1_8ch is exposed on CM1 / Module1A - to PI40
+ * pin 24 - GPIO26 - i2s1_sdi1_m1
+ * pin 25 - GPIO21 - i2s1_sdo0_m1
+ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
+ * pin 27 - GPIO20 - i2s1_sdi0_m1
+ * pin 29 - GPIO16 - i2s1_sdi3_m1
+ * pin 30 - GPIO6  - i2s1_sdi2_m1
+ * pin 40 - GPIO9  - i2s1_sdo1_m1, shared with spi3
+ * pin 41 - GPIO25 - i2s1_sdo2_m1
+ * pin 49 - GPIO18 - i2s1_sclk_tx_m1
+ * pin 50 - GPIO17 - i2s1_mclk_m1
+ * pin 56 - GPIO3  - i2s1_sdo3_m1, shared with i2c2
+ */
+&i2s1_8ch {
+	status = "disabled";
+};
+
+&led_diy {
+	color = <LED_COLOR_ID_RED>;
+	function = LED_FUNCTION_DISK_ACTIVITY;
+	linux,default-trigger = "disk-activity";
+	status = "okay";
+};
+
+&led_work {
+	color = <LED_COLOR_ID_GREEN>;
+	function = LED_FUNCTION_STATUS;
+	linux,default-trigger = "heartbeat";
+	status = "okay";
+};
+
+&pcie2x1 {
+	vpcie3v3-supply = <&vcc3v3_pcie_p>;
+	status = "okay";
+};
+
+&rgmii_phy1 {
+	status = "okay";
+};
+
+/*
+ * saradc is exposed on CM1 / Module1A - to J2
+ * pin 94 - AIN1 - saradc_vin3
+ * pin 96 - AIN0 - saradc_vin2
+ */
+&saradc {
+	status = "disabled";
+};
+
+&sdmmc0 {
+	vmmc-supply = <&vcc3v0_sd>;
+	status = "okay";
+};
+
+/*
+ * spi3 is exposed on CM1 / Module1A - to PI40
+ * pin 37 - GPIO7  - spi3_cs1_m0
+ * pin 38 - GPIO11 - spi3_clk_m0
+ * pin 39 - GPIO8  - spi3_cs0_m0
+ * pin 40 - GPIO9  - spi3_miso_m0, shared with i2s1_8ch
+ * pin 44 - GPIO10 - spi3_mosi_m0
+ */
+&spi3 {
+	status = "disabled";
+};
+
+/*
+ * uart2 is exposed on CM1 / Module1A - to PI40
+ * pin 51 - GPIO15 - uart2_rx_m0
+ * pin 55 - GPIO14 - uart2_tx_m0
+ */
+&uart2 {
+	status = "okay";
+};
+
+/*
+ * uart7 is exposed on CM1 / Module1A - to PI40
+ * pin 46 - GPIO22 - uart7_tx_m2
+ * pin 47 - GPIO23 - uart7_rx_m2
+ */
+&uart7 {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vbus>;
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	status = "okay";
+};
+
+&vbus {
+	vin-supply = <&vcc5v_dcin>;
+};
diff --git a/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi
new file mode 100644
index 0000000000..0e662eafa4
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3566-soquartz-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3566-soquartz-cm4.dts b/arch/arm/dts/rk3566-soquartz-cm4.dts
new file mode 100644
index 0000000000..cddf6cd2fe
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-cm4.dts
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-soquartz.dtsi"
+
+/ {
+	model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
+	compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566";
+
+	/* labeled +12v in schematic */
+	vcc12v_dcin: vcc12v-dcin-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	/* labeled +5v in schematic */
+	vcc_5v: vcc-5v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc_sd_pwr: vcc-sd-pwr-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sd_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+};
+
+/* phy for pcie */
+&combphy2 {
+	phy-supply = <&vcc3v3_sys>;
+	status = "okay";
+};
+
+&gmac1 {
+	status = "okay";
+};
+
+/*
+ * i2c1 is exposed on CM1 / Module1A
+ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+	status = "okay";
+
+	/*
+	 * the rtc interrupt is tied to PMIC_PWRON,
+	 * it will force reset the board if triggered.
+	 */
+	pcf85063: rtc@51 {
+		compatible = "nxp,pcf85063";
+		reg = <0x51>;
+	};
+};
+
+/*
+ * i2c2 is exposed on CM1 / Module1A - to PI40
+ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+	status = "disabled";
+};
+
+/*
+ * i2c3 is exposed on CM1 / Module1A - to PI40
+ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+	status = "disabled";
+};
+
+/*
+ * i2c4 is exposed on CM2 / Module1B - to PI40
+ * pin 45 - GPIO24 - i2c4_scl_m1
+ * pin 47 - GPIO23 - i2c4_sda_m1
+ */
+&i2c4 {
+	status = "disabled";
+};
+
+/*
+ * i2s1_8ch is exposed on CM1 / Module1A - to PI40
+ * pin 24 - GPIO26 - i2s1_sdi1_m1
+ * pin 25 - GPIO21 - i2s1_sdo0_m1
+ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
+ * pin 27 - GPIO20 - i2s1_sdi0_m1
+ * pin 29 - GPIO16 - i2s1_sdi3_m1
+ * pin 30 - GPIO6  - i2s1_sdi2_m1
+ * pin 40 - GPIO9  - i2s1_sdo1_m1, shared with spi3
+ * pin 41 - GPIO25 - i2s1_sdo2_m1
+ * pin 49 - GPIO18 - i2s1_sclk_tx_m1
+ * pin 50 - GPIO17 - i2s1_mclk_m1
+ * pin 56 - GPIO3  - i2s1_sdo3_m1, shared with i2c2
+ */
+&i2s1_8ch {
+	status = "disabled";
+};
+
+&led_diy {
+	status = "okay";
+};
+
+&led_work {
+	status = "okay";
+};
+
+&pcie2x1 {
+	vpcie3v3-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&rgmii_phy1 {
+	status = "okay";
+};
+
+/*
+ * saradc is exposed on CM1 / Module1A - to J2
+ * pin 94 - AIN1 - saradc_vin3
+ * pin 96 - AIN0 - saradc_vin2
+ */
+&saradc {
+	status = "disabled";
+};
+
+&sdmmc0 {
+	vmmc-supply = <&vcc_sd_pwr>;
+	status = "okay";
+};
+
+/*
+ *  spi3 is exposed on CM1 / Module1A - to PI40
+ * pin 37 - GPIO7  - spi3_cs1_m0
+ * pin 38 - GPIO11 - spi3_clk_m0
+ * pin 39 - GPIO8  - spi3_cs0_m0
+ * pin 40 - GPIO9  - spi3_miso_m0, shared with i2s1_8ch
+ * pin 44 - GPIO10 - spi3_mosi_m0
+ */
+&spi3 {
+	status = "disabled";
+};
+
+/*
+ * uart2 is exposed on CM1 / Module1A - to PI40
+ * pin 51 - GPIO15 - uart2_rx_m0
+ * pin 55 - GPIO14 - uart2_tx_m0
+ */
+&uart2 {
+	status = "okay";
+};
+
+/*
+ * uart7 is exposed on CM1 / Module1A - to PI40
+ * pin 46 - GPIO22 - uart7_tx_m2
+ * pin 47 - GPIO23 - uart7_rx_m2
+ */
+&uart7 {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc_5v>;
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	status = "okay";
+};
+
+&vbus {
+	vin-supply = <&vcc_5v>;
+};
diff --git a/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi
new file mode 100644
index 0000000000..0e662eafa4
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3566-soquartz-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3566-soquartz-model-a.dts b/arch/arm/dts/rk3566-soquartz-model-a.dts
new file mode 100644
index 0000000000..2208dbfb7f
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-model-a.dts
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-soquartz.dtsi"
+
+/ {
+	model = "PINE64 RK3566 SOQuartz on Model A carrier board";
+	compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566";
+
+	/* labeled DCIN_12V in schematic */
+	vcc12v_dcin: vcc12v-dcin-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_usb: vcc5v0-usb-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	/*
+	 * Labelled VCC3V0_SD in schematic to not conflict with PMIC
+	 * regulator, it's 3.3v in actuality
+	 */
+	vcc3v0_sd: vcc3v0-sd-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v0_sd";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc12v_pcie: vcc12v-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_pcie";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+};
+
+/* phy for pcie */
+&combphy2 {
+	phy-supply = <&vcc3v3_sys>;
+	status = "okay";
+};
+
+&gmac1 {
+	status = "okay";
+};
+
+/*
+ * i2c1 is exposed on CM1 / Module1A
+ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+	status = "okay";
+
+	/*
+	 * the rtc interrupt is tied to PMIC_PWRON,
+	 * it will force reset the board if triggered.
+	 */
+	pcf85063: rtc@51 {
+		compatible = "nxp,pcf85063";
+		reg = <0x51>;
+	};
+};
+
+/*
+ * i2c2 is exposed on CM1 / Module1A - to PI40
+ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+	status = "disabled";
+};
+
+/*
+ * i2c3 is exposed on CM1 / Module1A - to PI40
+ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+	status = "disabled";
+};
+
+/*
+ * i2c4 is exposed on CM2 / Module1B - to PI40
+ * pin 45 - GPIO24 - i2c4_scl_m1
+ * pin 47 - GPIO23 - i2c4_sda_m1
+ */
+&i2c4 {
+	status = "disabled";
+};
+
+/*
+ * i2s1_8ch is exposed on CM1 / Module1A - to PI40
+ * pin 24 - GPIO26 - i2s1_sdi1_m1
+ * pin 25 - GPIO21 - i2s1_sdo0_m1
+ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
+ * pin 27 - GPIO20 - i2s1_sdi0_m1
+ * pin 29 - GPIO16 - i2s1_sdi3_m1
+ * pin 30 - GPIO6  - i2s1_sdi2_m1
+ * pin 40 - GPIO9  - i2s1_sdo1_m1, shared with spi3
+ * pin 41 - GPIO25 - i2s1_sdo2_m1
+ * pin 49 - GPIO18 - i2s1_sclk_tx_m1
+ * pin 50 - GPIO17 - i2s1_mclk_m1
+ * pin 56 - GPIO3  - i2s1_sdo3_m1, shared with i2c2
+ */
+&i2s1_8ch {
+	status = "disabled";
+};
+
+&led_diy {
+	status = "okay";
+};
+
+&led_work {
+	status = "okay";
+};
+
+&pcie2x1 {
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&rgmii_phy1 {
+	status = "okay";
+};
+
+&rgmii_phy1 {
+	status = "okay";
+};
+
+/*
+ * saradc is exposed on CM1 / Module1A - to J2
+ * pin 94 - AIN1 - saradc_vin3
+ * pin 96 - AIN0 - saradc_vin2
+ */
+&saradc {
+	status = "disabled";
+};
+
+/*
+ * vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+
+ * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys,
+ * so we use vcc3v3_sd here to ensure the regulator is enabled on older boards.
+ */
+&sdmmc0 {
+	vmmc-supply = <&vcc3v3_sd>;
+	status = "okay";
+};
+
+/*
+ * spi3 is exposed on CM1 / Module1A - to PI40
+ * pin 37 - GPIO7  - spi3_cs1_m0
+ * pin 38 - GPIO11 - spi3_clk_m0
+ * pin 39 - GPIO8  - spi3_cs0_m0
+ * pin 40 - GPIO9  - spi3_miso_m0, shared with i2s1_8ch
+ * pin 44 - GPIO10 - spi3_mosi_m0
+ */
+&spi3 {
+	status = "disabled";
+};
+
+/*
+ * uart2 is exposed on CM1 / Module1A - to PI40
+ * pin 51 - GPIO15 - uart2_rx_m0
+ * pin 55 - GPIO14 - uart2_tx_m0
+ */
+&uart2 {
+	status = "okay";
+};
+
+/*
+ * uart7 is exposed on CM1 / Module1A - to PI40
+ * pin 46 - GPIO22 - uart7_tx_m2
+ * pin 47 - GPIO23 - uart7_rx_m2
+ */
+&uart7 {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb>;
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	status = "okay";
+};
+
+&vbus {
+	vin-supply = <&vcc5v0_usb>;
+};
+
+&vcc3v3_sd {
+	regulator-always-on;
+	regulator-boot-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi
new file mode 100644
index 0000000000..793cca2cea
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&sdhci {
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&uart2 {
+	bootph-all;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+};
diff --git a/arch/arm/dts/rk3566-soquartz.dtsi b/arch/arm/dts/rk3566-soquartz.dtsi
new file mode 100644
index 0000000000..31aa2b8efe
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz.dtsi
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "Pine64 RK3566 SoQuartz SOM";
+	compatible = "pine64,soquartz", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+		mmc2 = &sdmmc1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_diy: led-diy {
+			label = "diy-led";
+			default-state = "on";
+			gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&diy_led_enable_h>;
+			retain-state-suspended;
+			status = "disabled";
+		};
+
+		led_work: led-work {
+			label = "work-led";
+			default-state = "off";
+			gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&work_led_enable_h>;
+			retain-state-suspended;
+			status = "disabled";
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		status = "okay";
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+	};
+
+	vbus: vbus-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	/* sourced from vbus, vbus is provided by the carrier board */
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_3v3>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m0_miim
+		     &gmac1m0_tx_bus2
+		     &gmac1m0_rx_bus2
+		     &gmac1m0_rgmii_clk
+		     &gmac1m0_clkinout
+		     &gmac1m0_rgmii_bus>;
+	snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f, also works well here */
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	phy-handle = <&rgmii_phy1>;
+	status = "disabled";
+};
+
+&gpio0 {
+	nextrst-hog {
+		gpio-hog;
+		/*
+		 * GPIO_ACTIVE_LOW + output-low here means that the pin is set
+		 * to high, because output-low decides the value pre-inversion.
+		 */
+		gpios = <RK_PA5 GPIO_ACTIVE_LOW>;
+		line-name = "nEXTRST";
+		output-low;
+	};
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+					regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_npu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_acodec";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				status = "disabled";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+		};
+	};
+};
+
+/*
+ * i2c1 is exposed on CM1 / Module1A
+ * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+	status = "disabled";
+};
+
+/*
+ * i2c2 is exposed on CM1 / Module1A
+ * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2m1_xfer>;
+	status = "disabled";
+};
+
+/*
+ * i2c3 is exposed on CM1 / Module1A
+ * pin 35 - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+	status = "disabled";
+};
+
+/*
+ * i2c4 is exposed on CM2 / Module1B
+ * pin 45 - i2c4_scl_m1
+ * pin 47 - i2c4_sda_m1
+ */
+&i2c4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c4m1_xfer>;
+	status = "disabled";
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+/*
+ * i2s1_8ch is exposed on CM1 / Module1A
+ * pin 24 - i2s1_sdi1_m1
+ * pin 25 - i2s1_sdo0_m1
+ * pin 26 - i2s1_lrck_tx_m1
+ * pin 27 - i2s1_sdi0_m1
+ * pin 29 - i2s1_sdi3_m1
+ * pin 30 - i2s1_sdi2_m1
+ * pin 40 - i2s1_sdo1_m1, shared with spi3
+ * pin 41 - i2s1_sdo2_m1
+ * pin 49 - i2s1_sclk_tx_m1
+ * pin 50 - i2s1_mclk_m1
+ * pin 56 - i2s1_sdo3_m1, shared with i2c2
+ */
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx
+		     &i2s1m1_lrcktx &i2s1m1_lrckrx
+		     &i2s1m1_sdi0   &i2s1m1_sdi1
+		     &i2s1m1_sdi2   &i2s1m1_sdi3
+		     &i2s1m1_sdo0   &i2s1m1_sdo1
+		     &i2s1m1_sdo2   &i2s1m1_sdo3>;
+	status = "disabled";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		status = "disabled";
+	};
+};
+
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+};
+
+&pinctrl {
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		work_led_enable_h: work-led-enable-h {
+			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		diy_led_enable_h: diy-led-enable-h {
+			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_clkreq_h: pcie-clkreq-h {
+			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vcc_3v3>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+/*
+ * saradc is exposed on CM1 / Module1A
+ * pin 94 - saradc_vin3
+ * pin 96 - saradc_vin2
+ */
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "disabled";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	non-removable;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	broken-cd;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "disabled";
+};
+
+&sdmmc1 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	sd-uhs-sdr50;
+	vmmc-supply = <&vcc3v3_sys>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+/*
+ * spi3 is exposed on CM1 / Module1A
+ * pin 37 - spi3_cs1_m0
+ * pin 38 - spi3_clk_m0
+ * pin 39 - spi3_cs0_m0
+ * pin 40 - spi3_miso_m0, shared with i2s1_8ch
+ * pin 44 - spi3_mosi_m0
+ */
+&spi3 {
+	status = "disabled";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk809 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcca1v8_pmu>;
+	};
+};
+
+/*
+ * uart2 is exposed on CM1 / Module1A
+ * pin 51 - uart2_rx_m0
+ * pin 55 - uart2_tx_m0
+ */
+&uart2 {
+	status = "disabled";
+};
+
+/*
+ * uart7 is exposed on CM1 / Module1A
+ * pin 46 - uart7_tx_m2
+ * pin 47 - uart7_rx_m2
+ */
+&uart7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart7m2_xfer>;
+	status = "disabled";
+};
+
+/* dwc3_otg is the only usb port available */
+&usb2phy0 {
+	status = "disabled";
+};
+
+&usb2phy0_otg {
+	status = "disabled";
+};
+
+&usb_host0_xhci {
+	status = "disabled";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
new file mode 100644
index 0000000000..27c6277523
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2023 Andy Yan <andyshrk@163.com>
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&sdhci {
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&uart2 {
+	bootph-all;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-lubancat-2.dts b/arch/arm/dts/rk3568-lubancat-2.dts
new file mode 100644
index 0000000000..e653b067aa
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2.dts
@@ -0,0 +1,733 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "EmbedFire LubanCat 2";
+	compatible = "embedfire,lubancat-2", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		user_led: user-led {
+			label = "user_led";
+			linux,default-trigger = "heartbeat";
+			default-state = "on";
+			gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&user_led_pin>;
+		};
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	dc_5v: dc-5v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_5v>;
+	};
+
+	vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "m2_pcie_3v3";
+		enable-active-high;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc3v3_m2_pcie_en>;
+		pinctrl-names = "default";
+		startup-delay-us = <200000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "minipcie_3v3";
+		enable-active-high;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc3v3_mini_pcie_en>;
+		pinctrl-names = "default";
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb20_host";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc5v0_usb20_host_en>;
+		pinctrl-names = "default";
+	};
+
+	vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb30_host";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc5v0_usb30_host_en>;
+		pinctrl-names = "default";
+	};
+
+	vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_otg_vbus";
+		enable-active-high;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc5v0_otg_vbus_en>;
+		pinctrl-names = "default";
+	};
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&gmac0 {
+	phy-mode = "rgmii";
+	clock_in_out = "output";
+
+	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+
+	tx_delay = <0x22>;
+	rx_delay = <0x0e>;
+
+	phy-handle = <&rgmii_phy0>;
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&gmac1 {
+	phy-mode = "rgmii";
+	clock_in_out = "output";
+
+	snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+
+	tx_delay = <0x21>;
+	rx_delay = <0x0e>;
+
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&gic {
+	mbi-ranges = <94 31>, <229 31>, <289 31>;
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x2 {
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_m2_pcie>;
+	status = "okay";
+};
+
+&pcie2x1 {
+	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+	disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_mini_pcie>;
+	status = "okay";
+};
+
+&pmu_io_domains {
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm8 {
+	status = "okay";
+};
+
+&pwm9 {
+	status = "disabled";
+};
+
+&pwm10 {
+	status = "disabled";
+};
+
+&pwm14 {
+	status = "disabled";
+};
+
+&spi3 {
+	pinctrl-0 = <&spi3m1_pins>;
+	status = "disabled";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3m1_xfer>;
+	status = "disabled";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&sdhci {
+	assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
+	assigned-clock-rates = <200000000>, <24000000>, <200000000>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	mmc-hs200-1_8v;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+	supports-emmc;
+	status = "okay";
+};
+
+&sdmmc0 {
+	max-frequency = <150000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	status = "okay";
+};
+
+/* USB OTG/USB Host_1 USB 2.0 Comb */
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb30_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_otg_vbus>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+/* USB Host_2/USB Host_3 USB 2.0 Comb */
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb20_host>;
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */
+&usb_host0_xhci {
+	phys = <&usb2phy0_otg>;
+	phy-names = "usb2-phy";
+	extcon = <&usb2phy0>;
+	maximum-speed = "high-speed";
+	dr_mode = "host";
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+/* USB3.0 Host */
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
+
+&pinctrl {
+	leds {
+		user_led_pin: user-status-led-pin {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
+			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en {
+			rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic-int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
diff --git a/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
new file mode 100644
index 0000000000..fe5bc6af47
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rk3568-nanopi-r5s-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3568-nanopi-r5c.dts b/arch/arm/dts/rk3568-nanopi-r5c.dts
new file mode 100644
index 0000000000..f70ca9f047
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5c.dts
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
+ */
+
+/dts-v1/;
+#include "rk3568-nanopi-r5s.dtsi"
+
+/ {
+	model = "FriendlyElec NanoPi R5C";
+	compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&reset_button_pin>;
+
+		button-reset {
+			debounce-interval = <50>;
+			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
+
+		led-lan {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
+		};
+
+		power_led: led-power {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_POWER;
+			linux,default-trigger = "heartbeat";
+			gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-wan {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WAN;
+			gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-wlan {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+			gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie20_reset_pin>;
+	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pcie3x1 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pcie3x2 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pinctrl {
+	gpio-leds {
+		lan_led_pin: lan-led-pin {
+			rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		power_led_pin: power-led-pin {
+			rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wan_led_pin: wan-led-pin {
+			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wlan_led_pin: wlan-led-pin {
+			rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie20_reset_pin: pcie20-reset-pin {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	rockchip-key {
+		reset_button_pin: reset-button-pin {
+			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
new file mode 100644
index 0000000000..0ecca85b20
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdhci {
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&uart2 {
+	clock-frequency = <24000000>;
+	bootph-all;
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dts b/arch/arm/dts/rk3568-nanopi-r5s.dts
new file mode 100644
index 0000000000..b6ad8328c7
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s.dts
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
+ */
+
+/dts-v1/;
+#include "rk3568-nanopi-r5s.dtsi"
+
+/ {
+	model = "FriendlyElec NanoPi R5S";
+	compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
+
+		led-lan1 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			function-enumerator = <1>;
+			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-lan2 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			function-enumerator = <2>;
+			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
+		};
+
+		power_led: led-power {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_POWER;
+			linux,default-trigger = "heartbeat";
+			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-wan {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WAN;
+			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 15ms, 50ms for rtl8211f */
+	snps,reset-delays-us = <0 15000 50000>;
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+		pinctrl-0 = <&eth_phy0_reset_pin>;
+		pinctrl-names = "default";
+	};
+};
+
+&pcie2x1 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pcie30phy {
+	data-lanes = <1 2>;
+	status = "okay";
+};
+
+&pcie3x1 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pcie3x2 {
+	num-lanes = <1>;
+	num-ib-windows = <8>;
+	num-ob-windows = <8>;
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pinctrl {
+	gmac0 {
+		eth_phy0_reset_pin: eth-phy0-reset-pin {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gpio-leds {
+		lan1_led_pin: lan1-led-pin {
+			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		lan2_led_pin: lan2-led-pin {
+			rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		power_led_pin: power-led-pin {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wan_led_pin: wan-led-pin {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dtsi b/arch/arm/dts/rk3568-nanopi-r5s.dtsi
new file mode 100644
index 0000000000..58ba328ea7
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s.dtsi
@@ -0,0 +1,590 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	aliases {
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	vdd_usbc: vdd-usbc-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_usbc";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vdd_usbc>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vdd_usbc>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <200000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb: vcc5v0-usb-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vdd_usbc>;
+	};
+
+	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+		regulator-name = "vcc5v0_usb_host";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	pcie30_avdd0v9: pcie30-avdd0v9-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <950000>;
+				regulator-max-microvolt = <950000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+	};
+};
+
+&i2c5 {
+	status = "okay";
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <0>;
+		clock-output-names = "rtcic_32kout";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		wakeup-source;
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&pcie30phy {
+	data-lanes = <1 2>;
+	status = "okay";
+};
+
+&pinctrl {
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic-int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	max-frequency = <150000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	extcon = <&usb2phy0>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
new file mode 100644
index 0000000000..0fc360b06d
--- /dev/null
+++ b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&fspi_dual_io_pins {
+	bootph-all;
+};
+
+&sdhci {
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&sfc {
+	bootph-pre-ram;
+	u-boot,spl-sfc-no-dma;
+
+	flash@0 {
+		bootph-pre-ram;
+	};
+};
+
+&uart2 {
+	bootph-all;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-odroid-m1.dts b/arch/arm/dts/rk3568-odroid-m1.dts
new file mode 100644
index 0000000000..59ecf868db
--- /dev/null
+++ b/arch/arm/dts/rk3568-odroid-m1.dts
@@ -0,0 +1,744 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Hardkernel Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "Hardkernel ODROID-M1";
+	compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		i2c0 = &i2c3;
+		i2c3 = &i2c0;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+		serial0 = &uart1;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	dc_12v: dc-12v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_receiver_pin>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_power: led-0 {
+			gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			default-state = "keep";
+			linux,default-trigger = "default-on";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_power_pin>;
+		};
+		led_work: led-1 {
+			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_work_pin>;
+		};
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det_pin>;
+		simple-audio-card,name = "Analog RK817";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,widgets =
+			"Headphone", "Headphones",
+			"Speaker", "Speaker";
+		simple-audio-card,routing =
+			"Headphones", "HPOL",
+			"Headphones", "HPOR",
+			"Speaker", "SPKO";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		enable-active-high;
+		gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_pcie_en_pin>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_host";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en_pin>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_otg";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en_pin>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&combphy0 {
+	/* Used for USB3 */
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&combphy1 {
+	/* Used for USB3 */
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&combphy2 {
+	/* used for SATA */
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii";
+	phy-supply = <&vcc3v3_sys>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	status = "okay";
+
+	tx_delay = <0x4f>;
+	rx_delay = <0x2d>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+		rockchip,system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-always-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_pin>;
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pinctrl {
+	fspi {
+		fspi_dual_io_pins: fspi-dual-io-pins {
+			rockchip,pins =
+				/* fspi_clk */
+				<1 RK_PD0 1 &pcfg_pull_none>,
+				/* fspi_cs0n */
+				<1 RK_PD3 1 &pcfg_pull_none>,
+				/* fspi_d0 */
+				<1 RK_PD1 1 &pcfg_pull_none>,
+				/* fspi_d1 */
+				<1 RK_PD2 1 &pcfg_pull_none>;
+		};
+	};
+
+	ir-receiver {
+		ir_receiver_pin: ir-receiver-pin {
+			/* external pullup to VCC3V3_SYS */
+			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_power_pin: led-power-pin {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		led_work_pin: led-work-pin {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_reset_pin: pcie-reset-pin {
+			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
+			rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	rk809 {
+		hp_det_pin: hp-det-pin {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sata2 {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr50;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sfc {
+	/* Dual I/O mode as the D2 pin conflicts with the eMMC */
+	pinctrl-0 = <&fspi_dual_io_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <100000000>;
+		spi-rx-bus-width = <2>;
+		spi-tx-bus-width = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "SPL";
+				reg = <0x0 0xe0000>;
+			};
+			partition@e0000 {
+				label = "U-Boot Env";
+				reg = <0xe0000 0x20000>;
+			};
+			partition@100000 {
+				label = "U-Boot";
+				reg = <0x100000 0x200000>;
+			};
+			partition@300000 {
+				label = "splash";
+				reg = <0x300000 0x100000>;
+			};
+			partition@400000 {
+				label = "Filesystem";
+				reg = <0x400000 0xc00000>;
+			};
+		};
+	};
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm/dts/rk3568-pinctrl.dtsi b/arch/arm/dts/rk3568-pinctrl.dtsi
index 8f90c66dd9..0a979bfb63 100644
--- a/arch/arm/dts/rk3568-pinctrl.dtsi
+++ b/arch/arm/dts/rk3568-pinctrl.dtsi
@@ -3117,4 +3117,98 @@
 				<0 RK_PA1 0 &pcfg_pull_none>;
 		};
 	};
+
+	lcdc {
+		/omit-if-no-ref/
+		lcdc_clock: lcdc-clock {
+			rockchip,pins =
+				/* lcdc_clk */
+				<3 RK_PA0 1 &pcfg_pull_none>,
+				/* lcdc_den */
+				<3 RK_PC3 1 &pcfg_pull_none>,
+				/* lcdc_hsync */
+				<3 RK_PC1 1 &pcfg_pull_none>,
+				/* lcdc_vsync */
+				<3 RK_PC2 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		lcdc_data16: lcdc-data16 {
+			rockchip,pins =
+				/* lcdc_d3 */
+				<2 RK_PD3 1 &pcfg_pull_none>,
+				/* lcdc_d4 */
+				<2 RK_PD4 1 &pcfg_pull_none>,
+				/* lcdc_d5 */
+				<2 RK_PD5 1 &pcfg_pull_none>,
+				/* lcdc_d6 */
+				<2 RK_PD6 1 &pcfg_pull_none>,
+				/* lcdc_d7 */
+				<2 RK_PD7 1 &pcfg_pull_none>,
+				/* lcdc_d10 */
+				<3 RK_PA3 1 &pcfg_pull_none>,
+				/* lcdc_d11 */
+				<3 RK_PA4 1 &pcfg_pull_none>,
+				/* lcdc_d12 */
+				<3 RK_PA5 1 &pcfg_pull_none>,
+				/* lcdc_d13 */
+				<3 RK_PA6 1 &pcfg_pull_none>,
+				/* lcdc_d14 */
+				<3 RK_PA7 1 &pcfg_pull_none>,
+				/* lcdc_d15 */
+				<3 RK_PB0 1 &pcfg_pull_none>,
+				/* lcdc_d19 */
+				<3 RK_PB4 1 &pcfg_pull_none>,
+				/* lcdc_d20 */
+				<3 RK_PB5 1 &pcfg_pull_none>,
+				/* lcdc_d21 */
+				<3 RK_PB6 1 &pcfg_pull_none>,
+				/* lcdc_d22 */
+				<3 RK_PB7 1 &pcfg_pull_none>,
+				/* lcdc_d23 */
+				<3 RK_PC0 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		lcdc_data18: lcdc-data18 {
+			rockchip,pins =
+				/* lcdc_d2 */
+				<2 RK_PD2 1 &pcfg_pull_none>,
+				/* lcdc_d3 */
+				<2 RK_PD3 1 &pcfg_pull_none>,
+				/* lcdc_d4 */
+				<2 RK_PD4 1 &pcfg_pull_none>,
+				/* lcdc_d5 */
+				<2 RK_PD5 1 &pcfg_pull_none>,
+				/* lcdc_d6 */
+				<2 RK_PD6 1 &pcfg_pull_none>,
+				/* lcdc_d7 */
+				<2 RK_PD7 1 &pcfg_pull_none>,
+				/* lcdc_d10 */
+				<3 RK_PA3 1 &pcfg_pull_none>,
+				/* lcdc_d11 */
+				<3 RK_PA4 1 &pcfg_pull_none>,
+				/* lcdc_d12 */
+				<3 RK_PA5 1 &pcfg_pull_none>,
+				/* lcdc_d13 */
+				<3 RK_PA6 1 &pcfg_pull_none>,
+				/* lcdc_d14 */
+				<3 RK_PA7 1 &pcfg_pull_none>,
+				/* lcdc_d15 */
+				<3 RK_PB0 1 &pcfg_pull_none>,
+				/* lcdc_d18 */
+				<3 RK_PB3 1 &pcfg_pull_none>,
+				/* lcdc_d19 */
+				<3 RK_PB4 1 &pcfg_pull_none>,
+				/* lcdc_d20 */
+				<3 RK_PB5 1 &pcfg_pull_none>,
+				/* lcdc_d21 */
+				<3 RK_PB6 1 &pcfg_pull_none>,
+				/* lcdc_d22 */
+				<3 RK_PB7 1 &pcfg_pull_none>,
+				/* lcdc_d23 */
+				<3 RK_PC0 1 &pcfg_pull_none>;
+		};
+	};
+
 };
diff --git a/arch/arm/dts/rk3568-radxa-cm3i.dtsi b/arch/arm/dts/rk3568-radxa-cm3i.dtsi
new file mode 100644
index 0000000000..c50fbdd486
--- /dev/null
+++ b/arch/arm/dts/rk3568-radxa-cm3i.dtsi
@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+	compatible = "radxa,cm3i", "rockchip,rk3568";
+
+	aliases {
+		mmc0 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		led_user: led-0 {
+			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_GREEN>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_user_en>;
+		};
+	};
+
+	pcie30_avdd0v9: pcie30-avdd0v9-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v_input>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v_input>;
+	};
+
+	/* labeled +5v_input in schematic */
+	vcc5v_input: vcc5v-input-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v_input";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&display_subsystem {
+	status = "disabled";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v_input>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&pinctrl {
+	leds {
+		led_user_en: led_user_en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	extcon = <&usb2phy0>;
+};
diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
new file mode 100644
index 0000000000..572bdc5665
--- /dev/null
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+/* PCIe PHY driver in U-Boot does not support bifurcation */
+&pcie3x1 {
+	status = "disabled";
+};
+
+&sdhci {
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+};
+
+&uart2 {
+	bootph-all;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+};
diff --git a/arch/arm/dts/rk3568-radxa-e25.dts b/arch/arm/dts/rk3568-radxa-e25.dts
new file mode 100644
index 0000000000..72ad74c38a
--- /dev/null
+++ b/arch/arm/dts/rk3568-radxa-e25.dts
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3568-radxa-cm3i.dtsi"
+
+/ {
+	model = "Radxa E25 Carrier Board";
+	compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
+
+	aliases {
+		mmc1 = &sdmmc0;
+	};
+
+	pwm-leds {
+		compatible = "pwm-leds-multicolor";
+
+		multi-led {
+			color = <LED_COLOR_ID_RGB>;
+			max-brightness = <255>;
+
+			led-red {
+				color = <LED_COLOR_ID_RED>;
+				pwms = <&pwm1 0 1000000 0>;
+			};
+
+			led-green {
+				color = <LED_COLOR_ID_GREEN>;
+				pwms = <&pwm2 0 1000000 0>;
+			};
+
+			led-blue {
+				color = <LED_COLOR_ID_BLUE>;
+				pwms = <&pwm12 0 1000000 0>;
+			};
+		};
+	};
+
+	vbus_typec: vbus-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vbus_typec_en>;
+		regulator-name = "vbus_typec";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	/* actually fed by vcc5v0_sys, dependent
+	 * on pi6c clock generator
+	 */
+	vcc3v3_minipcie: vcc3v3-minipcie-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&minipcie_enable_h>;
+		regulator-name = "vcc3v3_minipcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_pi6c_05>;
+	};
+
+	vcc3v3_ngff: vcc3v3-ngff-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ngffpcie_enable_h>;
+		regulator-name = "vcc3v3_ngff";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie30x1_enable_h>;
+		regulator-name = "vcc3v3_pcie30x1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_enable_h>;
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&combphy1 {
+	phy-supply = <&vcc3v3_pcie30x1>;
+};
+
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie20_reset_h>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
+	status = "okay";
+};
+
+&pcie30phy {
+	data-lanes = <1 2>;
+	status = "okay";
+};
+
+&pcie3x1 {
+	num-lanes = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie30x1m0_pins>;
+	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_minipcie>;
+	status = "okay";
+};
+
+&pcie3x2 {
+	num-lanes = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie30x2_reset_h>;
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
+	status = "okay";
+};
+
+&pinctrl {
+	pcie {
+		pcie20_reset_h: pcie20-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie30x1_enable_h: pcie30x1-enable-h {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie30x2_reset_h: pcie30x2-reset-h {
+			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_enable_h: pcie-enable-h {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		minipcie_enable_h: minipcie-enable-h {
+			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		ngffpcie_enable_h: ngffpcie-enable-h {
+			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vbus_typec_en: vbus_typec_en {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&pwm12 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm12m1_pins>;
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	/* Also used in pcie30x1_clkreqnm0 */
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vbus_typec>;
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc3v3_minipcie>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc3v3_ngff>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index bbf54f888f..b05b7151e6 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -7,65 +7,21 @@
 #include "rk356x-u-boot.dtsi"
 
 / {
-	aliases {
-		spi0 = &sfc;
-	};
-
 	chosen {
 		stdout-path = &uart2;
 	};
 };
 
-&emmc_bus8 {
-	bootph-all;
-};
-
-&emmc_clk {
-	bootph-all;
-};
-
-&emmc_cmd {
-	bootph-all;
-};
-
-&emmc_datastrobe {
-	bootph-all;
-};
-
-&fspi_pins {
-	bootph-all;
+&pcie3x2 {
+	pinctrl-0 = <&pcie3x2_reset_h>;
 };
 
 &pinctrl {
-	bootph-all;
-};
-
-&pcfg_pull_none {
-	bootph-all;
-};
-
-&pcfg_pull_up_drv_level_2 {
-	bootph-all;
-};
-
-&pcfg_pull_up {
-	bootph-all;
-};
-
-&sdmmc0_bus4 {
-	bootph-all;
-};
-
-&sdmmc0_clk {
-	bootph-all;
-};
-
-&sdmmc0_cmd {
-	bootph-all;
-};
-
-&sdmmc0_det {
-	bootph-all;
+	pcie {
+		pcie3x2_reset_h: pcie3x2-reset-h {
+			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
 };
 
 &sdhci {
@@ -93,28 +49,8 @@
 	};
 };
 
-&sdmmc2 {
-	status = "disabled";
-};
-
-&uart1 {
-	status = "disabled";
-};
-
-&uart2m0_xfer {
-	bootph-all;
-};
-
 &uart2 {
 	clock-frequency = <24000000>;
 	bootph-all;
 	status = "okay";
 };
-
-&vcc5v0_usb_host {
-	regulator-boot-on;
-};
-
-&vcc5v0_usb_hub {
-	regulator-boot-on;
-};
diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
index ba67b58f05..f1be76a54c 100644
--- a/arch/arm/dts/rk3568.dtsi
+++ b/arch/arm/dts/rk3568.dtsi
@@ -94,9 +94,10 @@
 		power-domains = <&power RK3568_PD_PIPE>;
 		reg = <0x3 0xc0400000 0x0 0x00400000>,
 		      <0x0 0xfe270000 0x0 0x00010000>,
-		      <0x3 0x7f000000 0x0 0x01000000>;
-		ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
-			 <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
+		      <0x0 0xf2000000 0x0 0x00100000>;
+		ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
+			 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
+			 <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
 		reg-names = "dbi", "apb", "config";
 		resets = <&cru SRST_PCIE30X1_POWERUP>;
 		reset-names = "pipe";
@@ -146,9 +147,10 @@
 		power-domains = <&power RK3568_PD_PIPE>;
 		reg = <0x3 0xc0800000 0x0 0x00400000>,
 		      <0x0 0xfe280000 0x0 0x00010000>,
-		      <0x3 0xbf000000 0x0 0x01000000>;
-		ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
-			 <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
+		      <0x0 0xf0000000 0x0 0x00100000>;
+		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
+			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
+			 <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
 		reg-names = "dbi", "apb", "config";
 		resets = <&cru SRST_PCIE30X2_POWERUP>;
 		reset-names = "pipe";
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index c340c2bba6..32f687f292 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -9,10 +9,11 @@
 	aliases {
 		mmc0 = &sdhci;
 		mmc1 = &sdmmc0;
+		spi4 = &sfc;
 	};
 
 	chosen {
-		u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
 	};
 
 	dmc: dmc {
@@ -59,14 +60,77 @@
 	status = "okay";
 };
 
+&pinctrl {
+	bootph-all;
+};
+
+&pcfg_pull_none {
+	bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+	bootph-all;
+};
+
+&pcfg_pull_up {
+	bootph-all;
+};
+
+&emmc_bus8 {
+	bootph-all;
+};
+
+&emmc_clk {
+	bootph-all;
+};
+
+&emmc_cmd {
+	bootph-all;
+};
+
+&emmc_datastrobe {
+	bootph-all;
+};
+
+&emmc_rstnout {
+	bootph-all;
+};
+
+&fspi_pins {
+	bootph-all;
+};
+
+&sdmmc0_bus4 {
+	bootph-all;
+};
+
+&sdmmc0_clk {
+	bootph-all;
+};
+
+&sdmmc0_cmd {
+	bootph-all;
+};
+
+&sdmmc0_det {
+	bootph-all;
+};
+
+&sdmmc0_pwren {
+	bootph-all;
+};
+
+&uart2m0_xfer {
+	bootph-all;
+};
+
 &sdhci {
 	bootph-pre-ram;
-	status = "okay";
+	max-frequency = <200000000>;
 };
 
 &sdmmc0 {
 	bootph-pre-ram;
-	status = "okay";
 };
 
 #ifdef CONFIG_ROCKCHIP_SPI_IMAGE
diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
index 6492ace0de..61680c7ac4 100644
--- a/arch/arm/dts/rk356x.dtsi
+++ b/arch/arm/dts/rk356x.dtsi
@@ -422,8 +422,9 @@
 		clock-names = "xin24m";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
-		assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
-		assigned-clock-rates = <1200000000>, <200000000>;
+		assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
+		assigned-clock-rates = <32768>, <1200000000>, <200000000>;
+		assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
 		rockchip,grf = <&grf>;
 	};
 
@@ -743,8 +744,8 @@
 		compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
 		reg = <0x00 0xfe060000 0x00 0x10000>;
 		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-		clock-names = "pclk", "hclk";
-		clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
+		clock-names = "pclk";
+		clocks = <&cru PCLK_DSITX_0>;
 		phy-names = "dphy";
 		phys = <&dsi_dphy0>;
 		power-domains = <&power RK3568_PD_VO>;
@@ -771,8 +772,8 @@
 		compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
 		reg = <0x0 0xfe070000 0x0 0x10000>;
 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-		clock-names = "pclk", "hclk";
-		clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
+		clock-names = "pclk";
+		clocks = <&cru PCLK_DSITX_1>;
 		phy-names = "dphy";
 		phys = <&dsi_dphy1>;
 		power-domains = <&power RK3568_PD_VO>;
@@ -951,7 +952,7 @@
 		compatible = "rockchip,rk3568-pcie";
 		reg = <0x3 0xc0000000 0x0 0x00400000>,
 		      <0x0 0xfe260000 0x0 0x00010000>,
-		      <0x3 0x3f000000 0x0 0x01000000>;
+		      <0x0 0xf4000000 0x0 0x00100000>;
 		reg-names = "dbi", "apb", "config";
 		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
@@ -966,6 +967,7 @@
 		clock-names = "aclk_mst", "aclk_slv",
 			      "aclk_dbi", "pclk", "aux";
 		device_type = "pci";
+		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 7>;
 		interrupt-map = <0 0 0 1 &pcie_intc 0>,
 				<0 0 0 2 &pcie_intc 1>,
@@ -980,8 +982,9 @@
 		phys = <&combphy2 PHY_TYPE_PCIE>;
 		phy-names = "pcie-phy";
 		power-domains = <&power RK3568_PD_PIPE>;
-		ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
-			  0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
+		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
+			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
+			 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
 		resets = <&cru SRST_PCIE20_POWERUP>;
 		reset-names = "pipe";
 		#address-cells = <3>;
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
new file mode 100644
index 0000000000..cd7626b24b
--- /dev/null
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include "rk3588j-u-boot.dtsi"
+
+/ {
+	aliases {
+		mmc0 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = &sdmmc;
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
new file mode 100644
index 0000000000..e9d5a8bab5
--- /dev/null
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/dts-v1/;
+#include "rk3588j.dtsi"
+#include "rk3588-edgeble-neu6b.dtsi"
+
+/ {
+	model = "Edgeble Neu6B IO Board";
+	compatible = "edgeble,neural-compute-module-6b-io",
+		     "edgeble,neural-compute-module-6b", "rockchip,rk3588";
+
+	aliases {
+		serial2 = &uart2;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
new file mode 100644
index 0000000000..1c5bcf1280
--- /dev/null
+++ b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/ {
+	compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588";
+
+	aliases {
+		mmc0 = &sdhci;
+	};
+
+	vcc12v_dcin: vcc12v-dcin-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	max-frequency = <200000000>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 1cd8a57a6f..1b2fcbb0bb 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -7,17 +7,36 @@
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/usb/pd.h>
 
 / {
 	aliases {
 		mmc1 = &sdmmc;
-		spi0 = &sfc;
 	};
 
 	chosen {
 		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
 	};
 
+	vcc12v_dcin: vcc12v-dcin-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_usbdcin: vcc5v0-usbdcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usbdcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
 	vcc5v0_host: vcc5v0-host-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc5v0_host";
@@ -29,30 +48,32 @@
 		pinctrl-0 = <&vcc5v0_host_en>;
 		vin-supply = <&vcc5v0_sys>;
 	};
-};
-
-&combphy0_ps {
-	status = "okay";
-};
-
-&emmc_bus8 {
-	bootph-all;
-};
 
-&emmc_clk {
-	bootph-all;
-};
-
-&emmc_cmd {
-	bootph-all;
-};
+	vcc5v0_usb: vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usbdcin>;
+	};
 
-&emmc_data_strobe {
-	bootph-all;
+	vbus5v0_typec: vbus5v0-typec {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus5v0_typec";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&typec5v_pwren>;
+	};
 };
 
-&emmc_rstnout {
-	bootph-all;
+&combphy0_ps {
+	status = "okay";
 };
 
 &fspim2_pins {
@@ -67,8 +88,6 @@
 };
 
 &pinctrl {
-	bootph-all;
-
 	pcie {
 		pcie_reset_h: pcie-reset-h {
 			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -85,18 +104,16 @@
 			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
-};
 
-&pcfg_pull_none {
-	bootph-all;
-};
-
-&pcfg_pull_up_drv_level_2 {
-	bootph-all;
-};
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
 
-&pcfg_pull_up {
-	bootph-all;
+		typec5v_pwren: typec5v-pwren {
+			rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
 };
 
 &sdmmc {
@@ -104,22 +121,6 @@
 	status = "okay";
 };
 
-&sdmmc_bus4 {
-	bootph-all;
-};
-
-&sdmmc_clk {
-	bootph-all;
-};
-
-&sdmmc_cmd {
-	bootph-all;
-};
-
-&sdmmc_det {
-	bootph-all;
-};
-
 &sdhci {
 	cap-mmc-highspeed;
 	mmc-ddr-1_8v;
@@ -147,10 +148,6 @@
 	};
 };
 
-&uart2m0_xfer {
-	bootph-all;
-};
-
 &usb_host0_ehci {
 	companion = <&usb_host0_ohci>;
 	phys = <&u2phy2_host>;
@@ -168,6 +165,15 @@
 	status = "okay";
 };
 
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	rockchip,typec-vbus-det;
+	status = "okay";
+};
+
 &u2phy2 {
 	resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
 	reset-names = "phy", "apb";
@@ -209,3 +215,139 @@
 	status = "okay";
 };
 
+&usbdp_phy0 {
+	orientation-switch;
+	svid = <0xff01>;
+	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		usbdp_phy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+
+		usbdp_phy0_dp_altmode_mux: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&dp_altmode_mux>;
+		};
+	};
+};
+
+&usbdp_phy0_u3 {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	dr_mode = "otg";
+	usb-role-switch;
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		dwc3_0_role_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
+};
+
+&usbdp_phy1 {
+	rockchip,dp-lane-mux = <2 3>;
+	status = "okay";
+};
+
+&usbdp_phy1_u3 {
+	status = "okay";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&i2c4 {
+	pinctrl-0 = <&i2c4m1_xfer>;
+	status = "okay";
+
+	usbc0: fusb302@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus5v0_typec>;
+		status = "okay";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				usbc0_role_sw: endpoint@0 {
+					remote-endpoint = <&dwc3_0_role_switch>;
+				};
+			};
+		};
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			power-role = "dual";
+			try-power-role = "sink";
+			op-sink-microwatt = <1000000>;
+			sink-pdos =
+				<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+			altmodes {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				altmode@0 {
+					reg = <0>;
+					svid = <0xff01>;
+					vdo = <0xffffffff>;
+				};
+			};
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&usbdp_phy0_orientation_switch>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dp_altmode_mux: endpoint {
+						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+					};
+				};
+			};
+		};
+	};
+};
+
diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts
index 95805cb0ad..3e4aee8f70 100644
--- a/arch/arm/dts/rk3588-rock-5b.dts
+++ b/arch/arm/dts/rk3588-rock-5b.dts
@@ -2,6 +2,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include "rk3588.dtsi"
 
 / {
@@ -17,6 +18,31 @@
 		stdout-path = "serial2:1500000n8";
 	};
 
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <0 95 145 195 255>;
+		fan-supply = <&vcc5v0_sys>;
+		pwms = <&pwm1 0 50000 0>;
+		#cooling-cells = <2>;
+	};
+
+	sound {
+		compatible = "audio-graph-card";
+		label = "Analog";
+
+		widgets = "Microphone", "Mic Jack",
+			  "Headphone", "Headphones";
+
+		routing = "MIC2", "Mic Jack",
+			  "Headphones", "HPOL",
+			  "Headphones", "HPOR";
+
+		dais = <&i2s0_8ch_p0>;
+		hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_detect>;
+	};
+
 	vcc5v0_sys: vcc5v0-sys-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc5v0_sys";
@@ -27,6 +53,132 @@
 	};
 };
 
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c6 {
+	status = "okay";
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+};
+
+&i2c7 {
+	status = "okay";
+
+	es8316: audio-codec@11 {
+		compatible = "everest,es8316";
+		reg = <0x11>;
+		clocks = <&cru I2S0_8CH_MCLKOUT>;
+		clock-names = "mclk";
+		#sound-dai-cells = <0>;
+
+		port {
+			es8316_p0_0: endpoint {
+				remote-endpoint = <&i2s0_8ch_p0_0>;
+			};
+		};
+	};
+};
+
+&i2s0_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_lrck
+		     &i2s0_mclk
+		     &i2s0_sclk
+		     &i2s0_sdi0
+		     &i2s0_sdo0>;
+	status = "okay";
+
+	i2s0_8ch_p0: port {
+		i2s0_8ch_p0_0: endpoint {
+			dai-format = "i2s";
+			mclk-fs = <256>;
+			remote-endpoint = <&es8316_p0_0>;
+		};
+	};
+};
+
+&pinctrl {
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sound {
+		hp_detect: hp-detect {
+			rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+};
+
 &sdhci {
 	bus-width = <8>;
 	no-sdio;
diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
index 4c8ac804d6..68b419f3ab 100644
--- a/arch/arm/dts/rk3588-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-u-boot.dtsi
@@ -5,3 +5,96 @@
 
 #include "rockchip-u-boot.dtsi"
 #include "rk3588s-u-boot.dtsi"
+
+/ {
+	usbdrd3_1: usbdrd3_1 {
+		compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+		clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
+			 <&cru ACLK_USB3OTG1>;
+		clock-names = "ref", "suspend", "bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		usbdrd_dwc3_1: usb@fc400000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xfc400000 0x0 0x400000>;
+			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&power RK3588_PD_USB>;
+			resets = <&cru SRST_A_USB3OTG1>;
+			reset-names = "usb3-otg";
+			dr_mode = "host";
+			phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
+			phy-names = "usb2-phy", "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+		};
+	};
+
+	usbdpphy1_grf: syscon@fd5cc000 {
+		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+		reg = <0x0 0xfd5cc000 0x0 0x4000>;
+	};
+
+	usb2phy1_grf: syscon@fd5d4000 {
+		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+			     "simple-mfd";
+		reg = <0x0 0xfd5d4000 0x0 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		u2phy1: usb2-phy@4000 {
+			compatible = "rockchip,rk3588-usb2phy";
+			reg = <0x4000 0x10>;
+			interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
+			resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
+			reset-names = "phy", "apb";
+			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+			clock-names = "phyclk";
+			clock-output-names = "usb480m_phy1";
+			#clock-cells = <0>;
+			rockchip,usbctrl-grf = <&usb_grf>;
+			status = "disabled";
+
+			u2phy1_otg: otg-port {
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
+	};
+
+	usbdp_phy1: phy@fed90000 {
+		compatible = "rockchip,rk3588-usbdp-phy";
+		reg = <0x0 0xfed90000 0x0 0x10000>;
+		rockchip,u2phy-grf = <&usb2phy1_grf>;
+		rockchip,usb-grf = <&usb_grf>;
+		rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+		rockchip,vo-grf = <&vo0_grf>;
+		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+			 <&cru CLK_USBDP_PHY1_IMMORTAL>,
+			 <&cru PCLK_USBDPPHY1>,
+			 <&u2phy1>;
+		clock-names = "refclk", "immortal", "pclk", "utmi";
+		resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
+			 <&cru SRST_USBDP_COMBO_PHY1_CMN>,
+			 <&cru SRST_USBDP_COMBO_PHY1_LANE>,
+			 <&cru SRST_USBDP_COMBO_PHY1_PCS>,
+			 <&cru SRST_P_USBDPPHY1>;
+		reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+		status = "disabled";
+
+		usbdp_phy1_dp: dp-port {
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usbdp_phy1_u3: usb3-port {
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
index d085e57fbc..8be75556af 100644
--- a/arch/arm/dts/rk3588.dtsi
+++ b/arch/arm/dts/rk3588.dtsi
@@ -7,6 +7,74 @@
 #include "rk3588-pinctrl.dtsi"
 
 / {
+	i2s8_8ch: i2s@fddc8000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x0 0xfddc8000 0x0 0x1000>;
+		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
+		assigned-clock-parents = <&cru PLL_AUPLL>;
+		dmas = <&dmac2 22>;
+		dma-names = "tx";
+		power-domains = <&power RK3588_PD_VO0>;
+		resets = <&cru SRST_M_I2S8_8CH_TX>;
+		reset-names = "tx-m";
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
+	i2s6_8ch: i2s@fddf4000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x0 0xfddf4000 0x0 0x1000>;
+		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
+		assigned-clock-parents = <&cru PLL_AUPLL>;
+		dmas = <&dmac2 4>;
+		dma-names = "tx";
+		power-domains = <&power RK3588_PD_VO1>;
+		resets = <&cru SRST_M_I2S6_8CH_TX>;
+		reset-names = "tx-m";
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
+	i2s7_8ch: i2s@fddf8000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x0 0xfddf8000 0x0 0x1000>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
+		assigned-clock-parents = <&cru PLL_AUPLL>;
+		dmas = <&dmac2 21>;
+		dma-names = "rx";
+		power-domains = <&power RK3588_PD_VO1>;
+		resets = <&cru SRST_M_I2S7_8CH_RX>;
+		reset-names = "rx-m";
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
+	i2s10_8ch: i2s@fde00000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x0 0xfde00000 0x0 0x1000>;
+		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
+		assigned-clock-parents = <&cru PLL_AUPLL>;
+		dmas = <&dmac2 24>;
+		dma-names = "rx";
+		power-domains = <&power RK3588_PD_VO1>;
+		resets = <&cru SRST_M_I2S10_8CH_RX>;
+		reset-names = "rx-m";
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
 	gmac0: ethernet@fe1b0000 {
 		compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
 		reg = <0x0 0xfe1b0000 0x0 0x10000>;
diff --git a/arch/arm/dts/rk3588j-u-boot.dtsi b/arch/arm/dts/rk3588j-u-boot.dtsi
new file mode 100644
index 0000000000..f5c9e329a5
--- /dev/null
+++ b/arch/arm/dts/rk3588j-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include "rk3588-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3588j.dtsi b/arch/arm/dts/rk3588j.dtsi
new file mode 100644
index 0000000000..38b9dbf38a
--- /dev/null
+++ b/arch/arm/dts/rk3588j.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include "rk3588.dtsi"
diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
new file mode 100644
index 0000000000..9bb0e4f89e
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ */
+
+#include "rk3588s-u-boot.dtsi"
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/usb/pd.h>
+
+/ {
+	aliases {
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	status = "okay";
+};
+
+&sdhci {
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
+};
+
diff --git a/arch/arm/dts/rk3588s-rock-5a.dts b/arch/arm/dts/rk3588s-rock-5a.dts
new file mode 100644
index 0000000000..901825514f
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a.dts
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3588s.dtsi"
+
+/ {
+	model = "Radxa ROCK 5 Model A";
+	compatible = "radxa,rock-5a", "rockchip,rk3588s";
+
+	aliases {
+		mmc0 = &sdhci;
+		serial2 = &uart2;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+};
+
+&gmac1 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii";
+	pinctrl-0 = <&gmac1_miim
+		     &gmac1_tx_bus2
+		     &gmac1_rx_bus2
+		     &gmac1_rgmii_clk
+		     &gmac1_rgmii_bus>;
+	pinctrl-names = "default";
+	tx_delay = <0x3a>;
+	rx_delay = <0x3e>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		/* RTL8211F */
+		compatible = "ethernet-phy-id001c.c916";
+		reg = <0x1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtl8211f_rst>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pinctrl {
+	rtl8211f {
+		rtl8211f_rst: rtl8211f-rst {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	max-frequency = <200000000>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index c703e41802..245bc8b27c 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -7,12 +7,52 @@
 #include <dt-bindings/phy/phy.h>
 
 / {
+	aliases {
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &spi2;
+		spi3 = &spi3;
+		spi4 = &spi4;
+		spi5 = &sfc;
+	};
+
 	dmc {
 		compatible = "rockchip,rk3588-dmc";
 		bootph-all;
 		status = "okay";
 	};
 
+	usbdrd3_0: usbdrd3_0 {
+		compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+		clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
+			 <&cru ACLK_USB3OTG0>;
+		clock-names = "ref", "suspend", "bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		usbdrd_dwc3_0: usb@fc000000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xfc000000 0x0 0x400000>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&power RK3588_PD_USB>;
+			resets = <&cru SRST_A_USB3OTG0>;
+			reset-names = "usb3-otg";
+			dr_mode = "otg";
+			phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
+			phy-names = "usb2-phy", "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			quirk-skip-phy-init;
+		};
+	};
+
 	usb_host0_ehci: usb@fc800000 {
 		compatible = "generic-ehci";
 		reg = <0x0 0xfc800000 0x0 0x40000>;
@@ -64,6 +104,33 @@
 		reg = <0x0 0xfd5bc000 0x0 0x100>;
 	};
 
+	usb2phy0_grf: syscon@fd5d0000 {
+		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+			     "simple-mfd";
+		reg = <0x0 0xfd5d0000 0x0 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		u2phy0: usb2-phy@0 {
+			compatible = "rockchip,rk3588-usb2phy";
+			reg = <0x0 0x10>;
+			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
+			resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
+			reset-names = "phy", "apb";
+			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+			clock-names = "phyclk";
+			clock-output-names = "usb480m_phy0";
+			#clock-cells = <0>;
+			rockchip,usbctrl-grf = <&usb_grf>;
+			status = "disabled";
+
+			u2phy0_otg: otg-port {
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
+	};
+
 	usb2phy2_grf: syscon@fd5d8000 {
 		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
 			     "simple-mfd";
@@ -87,6 +154,17 @@
 		};
 	};
 
+	vo0_grf: syscon@fd5a6000 {
+		compatible = "rockchip,rk3588-vo-grf", "syscon";
+		reg = <0x0 0xfd5a6000 0x0 0x2000>;
+		clocks = <&cru PCLK_VO0GRF>;
+	};
+
+	usb_grf: syscon@fd5ac000 {
+		compatible = "rockchip,rk3588-usb-grf", "syscon";
+		reg = <0x0 0xfd5ac000 0x0 0x4000>;
+	};
+
 	usb2phy3_grf: syscon@fd5dc000 {
 		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
 			     "simple-mfd";
@@ -110,6 +188,11 @@
 		};
 	};
 
+	usbdpphy0_grf: syscon@fd5c8000 {
+		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+		reg = <0x0 0xfd5c8000 0x0 0x4000>;
+	};
+
 	pcie2x1l2: pcie@fe190000 {
 		compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
 		#address-cells = <3>;
@@ -174,24 +257,43 @@
 		status = "disabled";
 	};
 
-	otp: nvmem@fecc0000 {
-		compatible = "rockchip,rk3588-otp";
-		reg = <0x0 0xfecc0000 0x0 0x400>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		status = "okay";
-
-		cpu_id: id@7 {
-			reg = <0x07 0x10>;
-		};
-	};
-
 	rng: rng@fe378000 {
 		compatible = "rockchip,trngv1";
 		reg = <0x0 0xfe378000 0x0 0x200>;
 		status = "disabled";
 	};
 
+	usbdp_phy0: phy@fed80000 {
+		compatible = "rockchip,rk3588-usbdp-phy";
+		reg = <0x0 0xfed80000 0x0 0x10000>;
+		rockchip,u2phy-grf = <&usb2phy0_grf>;
+		rockchip,usb-grf = <&usb_grf>;
+		rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
+		rockchip,vo-grf = <&vo0_grf>;
+		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+			 <&cru CLK_USBDP_PHY0_IMMORTAL>,
+			 <&cru PCLK_USBDPPHY0>,
+			 <&u2phy0>;
+		clock-names = "refclk", "immortal", "pclk", "utmi";
+		resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
+			 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
+			 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
+			 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
+			 <&cru SRST_P_USBDPPHY0>;
+		reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+		status = "disabled";
+
+		usbdp_phy0_dp: dp-port {
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usbdp_phy0_u3: usb3-port {
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+	};
+
 	combphy0_ps: phy@fee00000 {
 		compatible = "rockchip,rk3588-naneng-combphy";
 		reg = <0x0 0xfee00000 0x0 0x100>;
@@ -209,6 +311,42 @@
 	};
 };
 
+&emmc_bus8 {
+	bootph-all;
+};
+
+&emmc_clk {
+	bootph-all;
+};
+
+&emmc_cmd {
+	bootph-all;
+};
+
+&emmc_data_strobe {
+	bootph-all;
+};
+
+&emmc_rstnout {
+	bootph-all;
+};
+
+&pinctrl {
+	bootph-all;
+};
+
+&pcfg_pull_none {
+	bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+	bootph-all;
+};
+
+&pcfg_pull_up {
+	bootph-all;
+};
+
 &xin24m {
 	bootph-all;
 	status = "okay";
@@ -242,12 +380,32 @@
 	u-boot,spl-fifo-mode;
 };
 
+&sdmmc_bus4 {
+	bootph-all;
+};
+
+&sdmmc_clk {
+	bootph-all;
+};
+
+&sdmmc_cmd {
+	bootph-all;
+};
+
+&sdmmc_det {
+	bootph-all;
+};
+
 &uart2 {
 	clock-frequency = <24000000>;
 	bootph-pre-ram;
 	status = "okay";
 };
 
+&uart2m0_xfer {
+	bootph-all;
+};
+
 &ioc {
 	bootph-pre-ram;
 };
diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi
index fca8503aed..7dbac9ae2e 100644
--- a/arch/arm/dts/rk3588s.dtsi
+++ b/arch/arm/dts/rk3588s.dtsi
@@ -60,6 +60,8 @@
 			enable-method = "psci";
 			capacity-dmips-mhz = <530>;
 			clocks = <&scmi_clk SCMI_CLK_CPUL>;
+			assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
+			assigned-clock-rates = <816000000>;
 			cpu-idle-states = <&CPU_SLEEP>;
 			i-cache-size = <32768>;
 			i-cache-line-size = <64>;
@@ -136,6 +138,8 @@
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
 			clocks = <&scmi_clk SCMI_CLK_CPUB01>;
+			assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
+			assigned-clock-rates = <816000000>;
 			cpu-idle-states = <&CPU_SLEEP>;
 			i-cache-size = <65536>;
 			i-cache-line-size = <64>;
@@ -174,6 +178,8 @@
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
 			clocks = <&scmi_clk SCMI_CLK_CPUB23>;
+			assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
+			assigned-clock-rates = <816000000>;
 			cpu-idle-states = <&CPU_SLEEP>;
 			i-cache-size = <65536>;
 			i-cache-line-size = <64>;
@@ -222,6 +228,8 @@
 			cache-size = <131072>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
+			cache-unified;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -230,6 +238,8 @@
 			cache-size = <131072>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
+			cache-unified;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -238,6 +248,8 @@
 			cache-size = <131072>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
+			cache-unified;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -246,6 +258,8 @@
 			cache-size = <131072>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
+			cache-unified;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -254,6 +268,8 @@
 			cache-size = <524288>;
 			cache-line-size = <64>;
 			cache-sets = <1024>;
+			cache-level = <2>;
+			cache-unified;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -262,6 +278,8 @@
 			cache-size = <524288>;
 			cache-line-size = <64>;
 			cache-sets = <1024>;
+			cache-level = <2>;
+			cache-unified;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -270,6 +288,8 @@
 			cache-size = <524288>;
 			cache-line-size = <64>;
 			cache-sets = <1024>;
+			cache-level = <2>;
+			cache-unified;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -278,6 +298,8 @@
 			cache-size = <524288>;
 			cache-line-size = <64>;
 			cache-sets = <1024>;
+			cache-level = <2>;
+			cache-unified;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -286,6 +308,8 @@
 			cache-size = <3145728>;
 			cache-line-size = <64>;
 			cache-sets = <4096>;
+			cache-level = <3>;
+			cache-unified;
 		};
 	};
 
@@ -304,10 +328,6 @@
 
 			scmi_clk: protocol@14 {
 				reg = <0x14>;
-				assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>,
-						  <&scmi_clk SCMI_CLK_CPUB23>;
-				assigned-clock-rates = <1200000000>,
-						       <1200000000>;
 				#clock-cells = <1>;
 			};
 
@@ -414,7 +434,7 @@
 			<&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
 			<&cru CLK_GPU>;
 		assigned-clock-rates =
-			<100000000>, <786432000>,
+			<1100000000>, <786432000>,
 			<850000000>, <1188000000>,
 			<702000000>,
 			<400000000>, <500000000>,
@@ -1132,6 +1152,103 @@
 		status = "disabled";
 	};
 
+	i2s0_8ch: i2s@fe470000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x0 0xfe470000 0x0 0x1000>;
+		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
+		assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
+		dmas = <&dmac0 0>, <&dmac0 1>;
+		dma-names = "tx", "rx";
+		power-domains = <&power RK3588_PD_AUDIO>;
+		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
+		reset-names = "tx-m", "rx-m";
+		rockchip,trcm-sync-tx-only;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s0_lrck
+			     &i2s0_sclk
+			     &i2s0_sdi0
+			     &i2s0_sdi1
+			     &i2s0_sdi2
+			     &i2s0_sdi3
+			     &i2s0_sdo0
+			     &i2s0_sdo1
+			     &i2s0_sdo2
+			     &i2s0_sdo3>;
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
+	i2s1_8ch: i2s@fe480000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x0 0xfe480000 0x0 0x1000>;
+		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		dmas = <&dmac0 2>, <&dmac0 3>;
+		dma-names = "tx", "rx";
+		resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
+		reset-names = "tx-m", "rx-m";
+		rockchip,trcm-sync-tx-only;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s1m0_lrck
+			     &i2s1m0_sclk
+			     &i2s1m0_sdi0
+			     &i2s1m0_sdi1
+			     &i2s1m0_sdi2
+			     &i2s1m0_sdi3
+			     &i2s1m0_sdo0
+			     &i2s1m0_sdo1
+			     &i2s1m0_sdo2
+			     &i2s1m0_sdo3>;
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
+	i2s2_2ch: i2s@fe490000 {
+		compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
+		reg = <0x0 0xfe490000 0x0 0x1000>;
+		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
+		clock-names = "i2s_clk", "i2s_hclk";
+		assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
+		assigned-clock-parents = <&cru PLL_AUPLL>;
+		dmas = <&dmac1 0>, <&dmac1 1>;
+		dma-names = "tx", "rx";
+		power-domains = <&power RK3588_PD_AUDIO>;
+		rockchip,trcm-sync-tx-only;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s2m1_lrck
+			     &i2s2m1_sclk
+			     &i2s2m1_sdi
+			     &i2s2m1_sdo>;
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
+	i2s3_2ch: i2s@fe4a0000 {
+		compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
+		reg = <0x0 0xfe4a0000 0x0 0x1000>;
+		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
+		clock-names = "i2s_clk", "i2s_hclk";
+		assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
+		assigned-clock-parents = <&cru PLL_AUPLL>;
+		dmas = <&dmac1 2>, <&dmac1 3>;
+		dma-names = "tx", "rx";
+		power-domains = <&power RK3588_PD_AUDIO>;
+		rockchip,trcm-sync-tx-only;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s3_lrck
+			     &i2s3_sclk
+			     &i2s3_sdi
+			     &i2s3_sdo>;
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@fe600000 {
 		compatible = "arm,gic-v3";
 		reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
@@ -1141,7 +1258,24 @@
 		mbi-alias = <0x0 0xfe610000>;
 		mbi-ranges = <424 56>;
 		msi-controller;
+		ranges;
+		#address-cells = <2>;
 		#interrupt-cells = <4>;
+		#size-cells = <2>;
+
+		its0: msi-controller@fe640000 {
+			compatible = "arm,gic-v3-its";
+			reg = <0x0 0xfe640000 0x0 0x20000>;
+			msi-controller;
+			#msi-cells = <1>;
+		};
+
+		its1: msi-controller@fe660000 {
+			compatible = "arm,gic-v3-its";
+			reg = <0x0 0xfe660000 0x0 0x20000>;
+			msi-controller;
+			#msi-cells = <1>;
+		};
 
 		ppi-partitions {
 			ppi_partition0: interrupt-partition-0 {
@@ -1241,6 +1375,22 @@
 		status = "disabled";
 	};
 
+	timer0: timer@feae0000 {
+		compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
+		reg = <0x0 0xfeae0000 0x0 0x20>;
+		interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
+		clock-names = "pclk", "timer";
+	};
+
+	wdt: watchdog@feaf0000 {
+		compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
+		reg = <0x0 0xfeaf0000 0x0 0x100>;
+		clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
+		clock-names = "tclk", "pclk";
+		interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
+	};
+
 	spi0: spi@feb00000 {
 		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
 		reg = <0x0 0xfeb00000 0x0 0x1000>;
@@ -1572,6 +1722,26 @@
 		status = "disabled";
 	};
 
+	tsadc: tsadc@fec00000 {
+		compatible = "rockchip,rk3588-tsadc";
+		reg = <0x0 0xfec00000 0x0 0x400>;
+		interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
+		clock-names = "tsadc", "apb_pclk";
+		assigned-clocks = <&cru CLK_TSADC>;
+		assigned-clock-rates = <2000000>;
+		resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
+		reset-names = "tsadc-apb", "tsadc";
+		rockchip,hw-tshut-temp = <120000>;
+		rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+		rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+		pinctrl-0 = <&tsadc_gpio_func>;
+		pinctrl-1 = <&tsadc_shut>;
+		pinctrl-names = "gpio", "otpout";
+		#thermal-sensor-cells = <1>;
+		status = "disabled";
+	};
+
 	i2c6: i2c@fec80000 {
 		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
 		reg = <0x0 0xfec80000 0x0 0x1000>;
@@ -1627,6 +1797,60 @@
 		status = "disabled";
 	};
 
+	otp: efuse@fecc0000 {
+		compatible = "rockchip,rk3588-otp";
+		reg = <0x0 0xfecc0000 0x0 0x400>;
+		clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
+			 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
+		clock-names = "otp", "apb_pclk", "phy", "arb";
+		resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
+			 <&cru SRST_OTPC_ARB>;
+		reset-names = "otp", "apb", "arb";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpu_code: cpu-code@2 {
+			reg = <0x02 0x2>;
+		};
+
+		otp_id: id@7 {
+			reg = <0x07 0x10>;
+		};
+
+		cpub0_leakage: cpu-leakage@17 {
+			reg = <0x17 0x1>;
+		};
+
+		cpub1_leakage: cpu-leakage@18 {
+			reg = <0x18 0x1>;
+		};
+
+		cpul_leakage: cpu-leakage@19 {
+			reg = <0x19 0x1>;
+		};
+
+		log_leakage: log-leakage@1a {
+			reg = <0x1a 0x1>;
+		};
+
+		gpu_leakage: gpu-leakage@1b {
+			reg = <0x1b 0x1>;
+		};
+
+		otp_cpu_version: cpu-version@1c {
+			reg = <0x1c 0x1>;
+			bits = <3 3>;
+		};
+
+		npu_leakage: npu-leakage@28 {
+			reg = <0x28 0x1>;
+		};
+
+		codec_leakage: codec-leakage@29 {
+			reg = <0x29 0x1>;
+		};
+	};
+
 	dmac2: dma-controller@fed10000 {
 		compatible = "arm,pl330", "arm,primecell";
 		reg = <0x0 0xfed10000 0x0 0x4000>;
diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi
deleted file mode 100644
index d84c10cf43..0000000000
--- a/arch/arm/dts/rockchip-optee.dtsi
+++ /dev/null
@@ -1,64 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2020 Google LLC
- */
-
-#include <config.h>
-
-#if defined(CONFIG_HAS_ROM) && defined(CONFIG_FIT)
-&binman {
-	itb {
-		filename = "u-boot.itb";
-		fit {
-			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-			description = "FIT image with OP-TEE support";
-			#address-cells = <1>;
-
-			images {
-				uboot {
-					description = "U-Boot";
-					type = "standalone";
-					os = "U-Boot";
-					arch = "arm";
-					compression = "none";
-					load = <CONFIG_TEXT_BASE>;
-
-					u-boot-nodtb {
-					};
-				};
-				optee {
-					description = "OP-TEE";
-					type = "firmware";
-					arch = "arm";
-					os = "tee";
-					compression = "none";
-					load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
-					entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
-
-					blob-ext {
-						filename = "tee.bin";
-					};
-				};
-				fdt {
-					description = CONFIG_SYS_BOARD;
-					type = "flat_dt";
-					compression = "none";
-
-					u-boot-dtb {
-					};
-				};
-			};
-
-			configurations {
-				default = "conf";
-				conf {
-					description = CONFIG_SYS_BOARD;
-					firmware = "optee";
-					loadables = "uboot";
-					fdt = "fdt";
-				};
-			};
-		};
-	};
-};
-#endif
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index 2878b80926..be2658e8ef 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -33,9 +33,13 @@
 			};
 		};
 
-#if defined(CONFIG_SPL_FIT) && defined(CONFIG_ARM64)
+#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE))
 		fit: fit {
+#ifdef CONFIG_ARM64
 			description = "FIT image for U-Boot with bl31 (TF-A)";
+#else
+			description = "FIT image with OP-TEE";
+#endif
 			#address-cells = <1>;
 			fit,fdt-list = "of-list";
 			filename = "u-boot.itb";
@@ -44,10 +48,14 @@
 			offset = <CONFIG_SPL_PAD_TO>;
 			images {
 				u-boot {
-					description = "U-Boot (64-bit)";
+					description = "U-Boot";
 					type = "standalone";
 					os = "U-Boot";
+#ifdef CONFIG_ARM64
 					arch = "arm64";
+#else
+					arch = "arm";
+#endif
 					compression = "none";
 					load = <CONFIG_TEXT_BASE>;
 					entry = <CONFIG_TEXT_BASE>;
@@ -60,6 +68,7 @@
 #endif
 				};
 
+#ifdef CONFIG_ARM64
 				@atf-SEQ {
 					fit,operation = "split-elf";
 					description = "ARM Trusted Firmware";
@@ -99,6 +108,25 @@
 					};
 #endif
 				};
+#else
+				op-tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm";
+					os = "tee";
+					compression = "none";
+					load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+					entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+
+					tee-os {
+					};
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+					hash {
+						algo = "sha256";
+					};
+#endif
+				};
+#endif
 
 				@fdt-SEQ {
 					description = "fdt-NAME";
@@ -117,7 +145,11 @@
 				@config-SEQ {
 					description = "NAME.dtb";
 					fdt = "fdt-SEQ";
+#ifdef CONFIG_ARM64
 					fit,firmware = "atf-1", "u-boot";
+#else
+					fit,firmware = "op-tee", "u-boot";
+#endif
 					fit,loadables;
 				};
 			};
@@ -150,7 +182,7 @@
 			};
 		};
 
-#ifdef CONFIG_ARM64
+#if defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)
 		fit {
 			type = "blob";
 			filename = "u-boot.itb";
diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
index 19b5451db4..522cffb1ac 100644
--- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
@@ -169,7 +169,7 @@
 	ltdc_pins: ltdc@0 {
 		pins {
 			pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
-				 <STM32_PINMUX('G',12, AF14)>, /* B4 */
+				 <STM32_PINMUX('G',12, AF9)>,  /* B4 */
 				 <STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
 				 <STM32_PINMUX('I',10, AF14)>, /* HSYNC */
 				 <STM32_PINMUX('I',14, AF14)>, /* CLK */
diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
index b5198fddff..2c823cce98 100644
--- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
@@ -28,11 +28,6 @@
 		button-gpio = <&gpioa 0 0>;
 	};
 
-	dsi_host: dsi_host {
-		compatible = "synopsys,dw-mipi-dsi";
-		status = "okay";
-	};
-
 	led1 {
 		compatible = "st,led1";
 		led-gpio = <&gpioj 5 0>;
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index d2472cd8f1..27e0c38267 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -6,6 +6,114 @@
 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
 
 &pinctrl {
+	adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
+		pins {
+			pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
+				 <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
+		};
+	};
+
+	i2c1_pins_a: i2c1-0 {
+		pins {
+			pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
+				 <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
+			bias-disable;
+			drive-open-drain;
+			slew-rate = <0>;
+		};
+	};
+
+	i2c1_sleep_pins_a: i2c1-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
+				 <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
+		};
+	};
+
+	i2c5_pins_a: i2c5-0 {
+		pins {
+			pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
+				 <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
+			bias-disable;
+			drive-open-drain;
+			slew-rate = <0>;
+		};
+	};
+
+	i2c5_sleep_pins_a: i2c5-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
+				 <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
+		};
+	};
+
+	mcp23017_pins_a: mcp23017-0 {
+		pins {
+			pinmux = <STM32_PINMUX('G', 12, GPIO)>;
+			bias-pull-up;
+		};
+	};
+
+	pwm3_pins_a: pwm3-0 {
+		pins {
+			pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
+			bias-pull-down;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+	};
+
+	pwm3_sleep_pins_a: pwm3-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
+		};
+	};
+
+	pwm4_pins_a: pwm4-0 {
+		pins {
+			pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
+			bias-pull-down;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+	};
+
+	pwm4_sleep_pins_a: pwm4-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
+		};
+	};
+
+	pwm8_pins_a: pwm8-0 {
+		pins {
+			pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
+			bias-pull-down;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+	};
+
+	pwm8_sleep_pins_a: pwm8-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
+		};
+	};
+
+	pwm14_pins_a: pwm14-0 {
+		pins {
+			pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
+			bias-pull-down;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+	};
+
+	pwm14_sleep_pins_a: pwm14-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
+		};
+	};
+
 	sdmmc1_b4_pins_a: sdmmc1-b4-0 {
 		pins {
 			pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -108,6 +216,36 @@
 		};
 	};
 
+	spi5_pins_a: spi5-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
+				 <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <1>;
+		};
+
+		pins2 {
+			pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
+			bias-disable;
+		};
+	};
+
+	spi5_sleep_pins_a: spi5-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
+				 <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
+				 <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
+		};
+	};
+
+	stm32g0_intn_pins_a: stm32g0-intn-0 {
+		pins {
+			pinmux = <STM32_PINMUX('I', 2, GPIO)>;
+			bias-pull-up;
+		};
+	};
+
 	uart4_pins_a: uart4-0 {
 		pins1 {
 			pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
@@ -120,4 +258,133 @@
 			bias-disable;
 		};
 	};
+
+	uart4_idle_pins_a: uart4-idle-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+			bias-disable;
+		};
+	};
+
+	uart4_sleep_pins_a: uart4-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
+				 <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
+		};
+	};
+
+	uart8_pins_a: uart8-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
+			bias-pull-up;
+		};
+	};
+
+	uart8_idle_pins_a: uart8-idle-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
+			bias-pull-up;
+		};
+	};
+
+	uart8_sleep_pins_a: uart8-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
+				 <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
+		};
+	};
+
+	usart1_pins_a: usart1-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
+				 <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
+				 <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
+			bias-pull-up;
+		};
+	};
+
+	usart1_idle_pins_a: usart1-idle-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+				 <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins3 {
+			pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
+			bias-pull-up;
+		};
+	};
+
+	usart1_sleep_pins_a: usart1-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+				 <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
+				 <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
+				 <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
+		};
+	};
+
+	usart2_pins_a: usart2-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
+				 <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
+				 <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
+			bias-disable;
+		};
+	};
+
+	usart2_idle_pins_a: usart2-idle-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
+				 <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins3 {
+			pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
+			bias-disable;
+		};
+	};
+
+	usart2_sleep_pins_a: usart2-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
+				 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
+				 <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
+				 <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
+		};
+	};
 };
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
index 6d82bf646d..d163c267e3 100644
--- a/arch/arm/dts/stm32mp131.dtsi
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -77,6 +77,28 @@
 		always-on;
 	};
 
+	/* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */
+	reg11: reg11 {
+		compatible = "regulator-fixed";
+		regulator-name = "reg11";
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+	};
+
+	reg18: reg18 {
+		compatible = "regulator-fixed";
+		regulator-name = "reg18";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	usb33: usb33 {
+		compatible = "regulator-fixed";
+		regulator-name = "usb33";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -97,13 +119,595 @@
 			};
 		};
 
+		timers2: timer@40000000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global";
+			clocks = <&rcc TIM2_K>;
+			clock-names = "int";
+			dmas = <&dmamux1 18 0x400 0x1>,
+			       <&dmamux1 19 0x400 0x1>,
+			       <&dmamux1 20 0x400 0x1>,
+			       <&dmamux1 21 0x400 0x1>,
+			       <&dmamux1 22 0x400 0x1>;
+			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer@1 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <1>;
+				status = "disabled";
+			};
+
+			counter {
+				compatible = "st,stm32-timer-counter";
+				status = "disabled";
+			};
+		};
+
+		timers3: timer@40001000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global";
+			clocks = <&rcc TIM3_K>;
+			clock-names = "int";
+			dmas = <&dmamux1 23 0x400 0x1>,
+			       <&dmamux1 24 0x400 0x1>,
+			       <&dmamux1 25 0x400 0x1>,
+			       <&dmamux1 26 0x400 0x1>,
+			       <&dmamux1 27 0x400 0x1>,
+			       <&dmamux1 28 0x400 0x1>;
+			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer@2 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <2>;
+				status = "disabled";
+			};
+
+			counter {
+				compatible = "st,stm32-timer-counter";
+				status = "disabled";
+			};
+		};
+
+		timers4: timer@40002000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 0x400>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global";
+			clocks = <&rcc TIM4_K>;
+			clock-names = "int";
+			dmas = <&dmamux1 29 0x400 0x1>,
+			       <&dmamux1 30 0x400 0x1>,
+			       <&dmamux1 31 0x400 0x1>,
+			       <&dmamux1 32 0x400 0x1>;
+			dma-names = "ch1", "ch2", "ch3", "up";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer@3 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <3>;
+				status = "disabled";
+			};
+
+			counter {
+				compatible = "st,stm32-timer-counter";
+				status = "disabled";
+			};
+		};
+
+		timers5: timer@40003000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40003000 0x400>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global";
+			clocks = <&rcc TIM5_K>;
+			clock-names = "int";
+			dmas = <&dmamux1 55 0x400 0x1>,
+			       <&dmamux1 56 0x400 0x1>,
+			       <&dmamux1 57 0x400 0x1>,
+			       <&dmamux1 58 0x400 0x1>,
+			       <&dmamux1 59 0x400 0x1>,
+			       <&dmamux1 60 0x400 0x1>;
+			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer@4 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <4>;
+				status = "disabled";
+			};
+
+			counter {
+				compatible = "st,stm32-timer-counter";
+				status = "disabled";
+			};
+		};
+
+		timers6: timer@40004000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40004000 0x400>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global";
+			clocks = <&rcc TIM6_K>;
+			clock-names = "int";
+			dmas = <&dmamux1 69 0x400 0x1>;
+			dma-names = "up";
+			status = "disabled";
+
+			timer@5 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <5>;
+				status = "disabled";
+			};
+		};
+
+		timers7: timer@40005000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40005000 0x400>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global";
+			clocks = <&rcc TIM7_K>;
+			clock-names = "int";
+			dmas = <&dmamux1 70 0x400 0x1>;
+			dma-names = "up";
+			status = "disabled";
+
+			timer@6 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <6>;
+				status = "disabled";
+			};
+		};
+
+		lptimer1: timer@40009000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-lptimer";
+			reg = <0x40009000 0x400>;
+			interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc LPTIM1_K>;
+			clock-names = "mux";
+			wakeup-source;
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm-lp";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			trigger@0 {
+				compatible = "st,stm32-lptimer-trigger";
+				reg = <0>;
+				status = "disabled";
+			};
+
+			counter {
+				compatible = "st,stm32-lptimer-counter";
+				status = "disabled";
+			};
+
+			timer {
+				compatible = "st,stm32-lptimer-timer";
+				status = "disabled";
+			};
+		};
+
+		i2s2: audio-controller@4000b000 {
+			compatible = "st,stm32h7-i2s";
+			reg = <0x4000b000 0x400>;
+			#sound-dai-cells = <0>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			dmas = <&dmamux1 39 0x400 0x01>,
+			       <&dmamux1 40 0x400 0x01>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		spi2: spi@4000b000 {
+			compatible = "st,stm32h7-spi";
+			reg = <0x4000b000 0x400>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SPI2_K>;
+			resets = <&rcc SPI2_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			dmas = <&dmamux1 39 0x400 0x01>,
+			       <&dmamux1 40 0x400 0x01>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		i2s3: audio-controller@4000c000 {
+			compatible = "st,stm32h7-i2s";
+			reg = <0x4000c000 0x400>;
+			#sound-dai-cells = <0>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			dmas = <&dmamux1 61 0x400 0x01>,
+			       <&dmamux1 62 0x400 0x01>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		spi3: spi@4000c000 {
+			compatible = "st,stm32h7-spi";
+			reg = <0x4000c000 0x400>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SPI3_K>;
+			resets = <&rcc SPI3_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			dmas = <&dmamux1 61 0x400 0x01>,
+			       <&dmamux1 62 0x400 0x01>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		spdifrx: audio-controller@4000d000 {
+			compatible = "st,stm32h7-spdifrx";
+			reg = <0x4000d000 0x400>;
+			#sound-dai-cells = <0>;
+			clocks = <&rcc SPDIF_K>;
+			clock-names = "kclk";
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			dmas = <&dmamux1 93 0x400 0x01>,
+			       <&dmamux1 94 0x400 0x01>;
+			dma-names = "rx", "rx-ctrl";
+			status = "disabled";
+		};
+
+		usart3: serial@4000f000 {
+			compatible = "st,stm32h7-uart";
+			reg = <0x4000f000 0x400>;
+			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc USART3_K>;
+			resets = <&rcc USART3_R>;
+			wakeup-source;
+			dmas = <&dmamux1 45 0x400 0x5>,
+			       <&dmamux1 46 0x400 0x1>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
 		uart4: serial@40010000 {
 			compatible = "st,stm32h7-uart";
 			reg = <0x40010000 0x400>;
-			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&rcc UART4_K>;
 			resets = <&rcc UART4_R>;
+			wakeup-source;
+			dmas = <&dmamux1 63 0x400 0x5>,
+			       <&dmamux1 64 0x400 0x1>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		uart5: serial@40011000 {
+			compatible = "st,stm32h7-uart";
+			reg = <0x40011000 0x400>;
+			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc UART5_K>;
+			resets = <&rcc UART5_R>;
+			wakeup-source;
+			dmas = <&dmamux1 65 0x400 0x5>,
+			       <&dmamux1 66 0x400 0x1>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		i2c1: i2c@40012000 {
+			compatible = "st,stm32mp13-i2c";
+			reg = <0x40012000 0x400>;
+			interrupt-names = "event", "error";
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc I2C1_K>;
+			resets = <&rcc I2C1_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			dmas = <&dmamux1 33 0x400 0x1>,
+			       <&dmamux1 34 0x400 0x1>;
+			dma-names = "rx", "tx";
+			st,syscfg-fmp = <&syscfg 0x4 0x1>;
+			i2c-analog-filter;
+			status = "disabled";
+		};
+
+		i2c2: i2c@40013000 {
+			compatible = "st,stm32mp13-i2c";
+			reg = <0x40013000 0x400>;
+			interrupt-names = "event", "error";
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc I2C2_K>;
+			resets = <&rcc I2C2_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			dmas = <&dmamux1 35 0x400 0x1>,
+			       <&dmamux1 36 0x400 0x1>;
+			dma-names = "rx", "tx";
+			st,syscfg-fmp = <&syscfg 0x4 0x2>;
+			i2c-analog-filter;
+			status = "disabled";
+		};
+
+		uart7: serial@40018000 {
+			compatible = "st,stm32h7-uart";
+			reg = <0x40018000 0x400>;
+			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc UART7_K>;
+			resets = <&rcc UART7_R>;
+			wakeup-source;
+			dmas = <&dmamux1 79 0x400 0x5>,
+			       <&dmamux1 80 0x400 0x1>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		uart8: serial@40019000 {
+			compatible = "st,stm32h7-uart";
+			reg = <0x40019000 0x400>;
+			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc UART8_K>;
+			resets = <&rcc UART8_R>;
+			wakeup-source;
+			dmas = <&dmamux1 81 0x400 0x5>,
+			       <&dmamux1 82 0x400 0x1>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		timers1: timer@44000000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x44000000 0x400>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "brk", "up", "trg-com", "cc";
+			clocks = <&rcc TIM1_K>;
+			clock-names = "int";
+			dmas = <&dmamux1 11 0x400 0x1>,
+			       <&dmamux1 12 0x400 0x1>,
+			       <&dmamux1 13 0x400 0x1>,
+			       <&dmamux1 14 0x400 0x1>,
+			       <&dmamux1 15 0x400 0x1>,
+			       <&dmamux1 16 0x400 0x1>,
+			       <&dmamux1 17 0x400 0x1>;
+			dma-names = "ch1", "ch2", "ch3", "ch4",
+				    "up", "trig", "com";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer@0 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <0>;
+				status = "disabled";
+			};
+
+			counter {
+				compatible = "st,stm32-timer-counter";
+				status = "disabled";
+			};
+		};
+
+		timers8: timer@44001000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x44001000 0x400>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "brk", "up", "trg-com", "cc";
+			clocks = <&rcc TIM8_K>;
+			clock-names = "int";
+			dmas = <&dmamux1 47 0x400 0x1>,
+			       <&dmamux1 48 0x400 0x1>,
+			       <&dmamux1 49 0x400 0x1>,
+			       <&dmamux1 50 0x400 0x1>,
+			       <&dmamux1 51 0x400 0x1>,
+			       <&dmamux1 52 0x400 0x1>,
+			       <&dmamux1 53 0x400 0x1>;
+			dma-names = "ch1", "ch2", "ch3", "ch4",
+				    "up", "trig", "com";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer@7 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <7>;
+				status = "disabled";
+			};
+
+			counter {
+				compatible = "st,stm32-timer-counter";
+				status = "disabled";
+			};
+		};
+
+		usart6: serial@44003000 {
+			compatible = "st,stm32h7-uart";
+			reg = <0x44003000 0x400>;
+			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc USART6_K>;
+			resets = <&rcc USART6_R>;
+			wakeup-source;
+			dmas = <&dmamux1 71 0x400 0x5>,
+			       <&dmamux1 72 0x400 0x1>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		i2s1: audio-controller@44004000 {
+			compatible = "st,stm32h7-i2s";
+			reg = <0x44004000 0x400>;
+			#sound-dai-cells = <0>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			dmas = <&dmamux1 37 0x400 0x01>,
+			       <&dmamux1 38 0x400 0x01>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		spi1: spi@44004000 {
+			compatible = "st,stm32h7-spi";
+			reg = <0x44004000 0x400>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SPI1_K>;
+			resets = <&rcc SPI1_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			dmas = <&dmamux1 37 0x400 0x01>,
+			       <&dmamux1 38 0x400 0x01>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		sai1: sai@4400a000 {
+			compatible = "st,stm32h7-sai";
+			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
+			ranges = <0 0x4400a000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rcc SAI1_R>;
+			status = "disabled";
+
+			sai1a: audio-controller@4400a004 {
+				compatible = "st,stm32-sai-sub-a";
+				reg = <0x4 0x20>;
+				#sound-dai-cells = <0>;
+				clocks = <&rcc SAI1_K>;
+				clock-names = "sai_ck";
+				dmas = <&dmamux1 87 0x400 0x01>;
+				status = "disabled";
+			};
+
+			sai1b: audio-controller@4400a024 {
+				compatible = "st,stm32-sai-sub-b";
+				reg = <0x24 0x20>;
+				#sound-dai-cells = <0>;
+				clocks = <&rcc SAI1_K>;
+				clock-names = "sai_ck";
+				dmas = <&dmamux1 88 0x400 0x01>;
+				status = "disabled";
+			};
+		};
+
+		sai2: sai@4400b000 {
+			compatible = "st,stm32h7-sai";
+			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+			ranges = <0 0x4400b000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rcc SAI2_R>;
+			status = "disabled";
+
+			sai2a: audio-controller@4400b004 {
+				compatible = "st,stm32-sai-sub-a";
+				reg = <0x4 0x20>;
+				#sound-dai-cells = <0>;
+				clocks = <&rcc SAI2_K>;
+				clock-names = "sai_ck";
+				dmas = <&dmamux1 89 0x400 0x01>;
+				status = "disabled";
+			};
+
+			sai2b: audio-controller@4400b024 {
+				compatible = "st,stm32-sai-sub-b";
+				reg = <0x24 0x20>;
+				#sound-dai-cells = <0>;
+				clocks = <&rcc SAI2_K>;
+				clock-names = "sai_ck";
+				dmas = <&dmamux1 90 0x400 0x01>;
+				status = "disabled";
+			};
+		};
+
+		dfsdm: dfsdm@4400d000 {
+			compatible = "st,stm32mp1-dfsdm";
+			reg = <0x4400d000 0x800>;
+			clocks = <&rcc DFSDM_K>;
+			clock-names = "dfsdm";
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
+
+			dfsdm0: filter@0 {
+				compatible = "st,stm32-dfsdm-adc";
+				reg = <0>;
+				#io-channel-cells = <1>;
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 101 0x400 0x01>;
+				dma-names = "rx";
+				status = "disabled";
+			};
+
+			dfsdm1: filter@1 {
+				compatible = "st,stm32-dfsdm-adc";
+				reg = <1>;
+				#io-channel-cells = <1>;
+				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 102 0x400 0x01>;
+				dma-names = "rx";
+				status = "disabled";
+			};
 		};
 
 		dma1: dma-controller@48000000 {
@@ -153,13 +757,345 @@
 			dma-channels = <16>;
 		};
 
+		adc_2: adc@48004000 {
+			compatible = "st,stm32mp13-adc-core";
+			reg = <0x48004000 0x400>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
+			clock-names = "bus", "adc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			adc2: adc@0 {
+				compatible = "st,stm32mp13-adc";
+				#io-channel-cells = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0>;
+				interrupt-parent = <&adc_2>;
+				interrupts = <0>;
+				dmas = <&dmamux1 10 0x400 0x80000001>;
+				dma-names = "rx";
+				status = "disabled";
+
+				channel@13 {
+					reg = <13>;
+					label = "vrefint";
+				};
+				channel@14 {
+					reg = <14>;
+					label = "vddcore";
+				};
+				channel@16 {
+					reg = <16>;
+					label = "vddcpu";
+				};
+				channel@17 {
+					reg = <17>;
+					label = "vddq_ddr";
+				};
+			};
+		};
+
+		usbotg_hs: usb@49000000 {
+			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+			reg = <0x49000000 0x40000>;
+			clocks = <&rcc USBO_K>;
+			clock-names = "otg";
+			resets = <&rcc USBO_R>;
+			reset-names = "dwc2";
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			g-rx-fifo-size = <512>;
+			g-np-tx-fifo-size = <32>;
+			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+			dr_mode = "otg";
+			otg-rev = <0x200>;
+			usb33d-supply = <&usb33>;
+			status = "disabled";
+		};
+
+		usart1: serial@4c000000 {
+			compatible = "st,stm32h7-uart";
+			reg = <0x4c000000 0x400>;
+			interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc USART1_K>;
+			resets = <&rcc USART1_R>;
+			wakeup-source;
+			dmas = <&dmamux1 41 0x400 0x5>,
+			       <&dmamux1 42 0x400 0x1>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		usart2: serial@4c001000 {
+			compatible = "st,stm32h7-uart";
+			reg = <0x4c001000 0x400>;
+			interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc USART2_K>;
+			resets = <&rcc USART2_R>;
+			wakeup-source;
+			dmas = <&dmamux1 43 0x400 0x5>,
+			       <&dmamux1 44 0x400 0x1>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		i2s4: audio-controller@4c002000 {
+			compatible = "st,stm32h7-i2s";
+			reg = <0x4c002000 0x400>;
+			#sound-dai-cells = <0>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			dmas = <&dmamux1 83 0x400 0x01>,
+			       <&dmamux1 84 0x400 0x01>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		spi4: spi@4c002000 {
+			compatible = "st,stm32h7-spi";
+			reg = <0x4c002000 0x400>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SPI4_K>;
+			resets = <&rcc SPI4_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			dmas = <&dmamux1 83 0x400 0x01>,
+			       <&dmamux1 84 0x400 0x01>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		spi5: spi@4c003000 {
+			compatible = "st,stm32h7-spi";
+			reg = <0x4c003000 0x400>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SPI5_K>;
+			resets = <&rcc SPI5_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			dmas = <&dmamux1 85 0x400 0x01>,
+			       <&dmamux1 86 0x400 0x01>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		i2c3: i2c@4c004000 {
+			compatible = "st,stm32mp13-i2c";
+			reg = <0x4c004000 0x400>;
+			interrupt-names = "event", "error";
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc I2C3_K>;
+			resets = <&rcc I2C3_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			dmas = <&dmamux1 73 0x400 0x1>,
+			       <&dmamux1 74 0x400 0x1>;
+			dma-names = "rx", "tx";
+			st,syscfg-fmp = <&syscfg 0x4 0x4>;
+			i2c-analog-filter;
+			status = "disabled";
+		};
+
+		i2c4: i2c@4c005000 {
+			compatible = "st,stm32mp13-i2c";
+			reg = <0x4c005000 0x400>;
+			interrupt-names = "event", "error";
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc I2C4_K>;
+			resets = <&rcc I2C4_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			dmas = <&dmamux1 75 0x400 0x1>,
+			       <&dmamux1 76 0x400 0x1>;
+			dma-names = "rx", "tx";
+			st,syscfg-fmp = <&syscfg 0x4 0x8>;
+			i2c-analog-filter;
+			status = "disabled";
+		};
+
+		i2c5: i2c@4c006000 {
+			compatible = "st,stm32mp13-i2c";
+			reg = <0x4c006000 0x400>;
+			interrupt-names = "event", "error";
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc I2C5_K>;
+			resets = <&rcc I2C5_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			dmas = <&dmamux1 115 0x400 0x1>,
+			       <&dmamux1 116 0x400 0x1>;
+			dma-names = "rx", "tx";
+			st,syscfg-fmp = <&syscfg 0x4 0x10>;
+			i2c-analog-filter;
+			status = "disabled";
+		};
+
+		timers12: timer@4c007000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x4c007000 0x400>;
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global";
+			clocks = <&rcc TIM12_K>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer@11 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <11>;
+				status = "disabled";
+			};
+		};
+
+		timers13: timer@4c008000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x4c008000 0x400>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global";
+			clocks = <&rcc TIM13_K>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer@12 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <12>;
+				status = "disabled";
+			};
+		};
+
+		timers14: timer@4c009000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x4c009000 0x400>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global";
+			clocks = <&rcc TIM14_K>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer@13 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <13>;
+				status = "disabled";
+			};
+		};
+
+		timers15: timer@4c00a000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x4c00a000 0x400>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global";
+			clocks = <&rcc TIM15_K>;
+			clock-names = "int";
+			dmas = <&dmamux1 105 0x400 0x1>,
+			       <&dmamux1 106 0x400 0x1>,
+			       <&dmamux1 107 0x400 0x1>,
+			       <&dmamux1 108 0x400 0x1>;
+			dma-names = "ch1", "up", "trig", "com";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer@14 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <14>;
+				status = "disabled";
+			};
+		};
+
+		timers16: timer@4c00b000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x4c00b000 0x400>;
+			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global";
+			clocks = <&rcc TIM16_K>;
+			clock-names = "int";
+			dmas = <&dmamux1 109 0x400 0x1>,
+			       <&dmamux1 110 0x400 0x1>;
+			dma-names = "ch1", "up";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer@15 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <15>;
+				status = "disabled";
+			};
+		};
+
+		timers17: timer@4c00c000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x4c00c000 0x400>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global";
+			clocks = <&rcc TIM17_K>;
+			clock-names = "int";
+			dmas = <&dmamux1 111 0x400 0x1>,
+			       <&dmamux1 112 0x400 0x1>;
+			dma-names = "ch1", "up";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer@16 {
+				compatible = "st,stm32h7-timer-trigger";
+				reg = <16>;
+				status = "disabled";
+			};
+		};
+
 		rcc: rcc@50000000 {
 			compatible = "st,stm32mp13-rcc", "syscon";
 			reg = <0x50000000 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
-			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-
 			clock-names = "hse", "hsi", "csi", "lse", "lsi";
 			clocks = <&scmi_clk CK_SCMI_HSE>,
 				 <&scmi_clk CK_SCMI_HSI>,
@@ -181,6 +1117,111 @@
 			clocks = <&rcc SYSCFG>;
 		};
 
+		lptimer2: timer@50021000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-lptimer";
+			reg = <0x50021000 0x400>;
+			interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc LPTIM2_K>;
+			clock-names = "mux";
+			wakeup-source;
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm-lp";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			trigger@1 {
+				compatible = "st,stm32-lptimer-trigger";
+				reg = <1>;
+				status = "disabled";
+			};
+
+			counter {
+				compatible = "st,stm32-lptimer-counter";
+				status = "disabled";
+			};
+
+			timer {
+				compatible = "st,stm32-lptimer-timer";
+				status = "disabled";
+			};
+		};
+
+		lptimer3: timer@50022000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-lptimer";
+			reg = <0x50022000 0x400>;
+			interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc LPTIM3_K>;
+			clock-names = "mux";
+			wakeup-source;
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm-lp";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			trigger@2 {
+				compatible = "st,stm32-lptimer-trigger";
+				reg = <2>;
+				status = "disabled";
+			};
+
+			timer {
+				compatible = "st,stm32-lptimer-timer";
+				status = "disabled";
+			};
+		};
+
+		lptimer4: timer@50023000 {
+			compatible = "st,stm32-lptimer";
+			reg = <0x50023000 0x400>;
+			interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc LPTIM4_K>;
+			clock-names = "mux";
+			wakeup-source;
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm-lp";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer {
+				compatible = "st,stm32-lptimer-timer";
+				status = "disabled";
+			};
+		};
+
+		lptimer5: timer@50024000 {
+			compatible = "st,stm32-lptimer";
+			reg = <0x50024000 0x400>;
+			interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc LPTIM5_K>;
+			clock-names = "mux";
+			wakeup-source;
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm-lp";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			timer {
+				compatible = "st,stm32-lptimer-timer";
+				status = "disabled";
+			};
+		};
+
 		mdma: dma-controller@58000000 {
 			compatible = "st,stm32h7-mdma";
 			reg = <0x58000000 0x1000>;
@@ -261,13 +1302,31 @@
 			clocks = <&rcc SDMMC2_K>;
 			clock-names = "apb_pclk";
 			resets = <&rcc SDMMC2_R>;
-
 			cap-sd-highspeed;
 			cap-mmc-highspeed;
 			max-frequency = <130000000>;
 			status = "disabled";
 		};
 
+		usbh_ohci: usb@5800c000 {
+			compatible = "generic-ohci";
+			reg = <0x5800c000 0x1000>;
+			clocks = <&usbphyc>, <&rcc USBH>;
+			resets = <&rcc USBH_R>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		usbh_ehci: usb@5800d000 {
+			compatible = "generic-ehci";
+			reg = <0x5800d000 0x1000>;
+			clocks = <&usbphyc>, <&rcc USBH>;
+			resets = <&rcc USBH_R>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+			companion = <&usbh_ohci>;
+			status = "disabled";
+		};
+
 		iwdg2: watchdog@5a002000 {
 			compatible = "st,stm32mp1-iwdg";
 			reg = <0x5a002000 0x400>;
@@ -276,6 +1335,29 @@
 			status = "disabled";
 		};
 
+		usbphyc: usbphyc@5a006000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#clock-cells = <0>;
+			compatible = "st,stm32mp1-usbphyc";
+			reg = <0x5a006000 0x1000>;
+			clocks = <&rcc USBPHY_K>;
+			resets = <&rcc USBPHY_R>;
+			vdda1v1-supply = <&reg11>;
+			vdda1v8-supply = <&reg18>;
+			status = "disabled";
+
+			usbphyc_port0: usb-phy@0 {
+				#phy-cells = <0>;
+				reg = <0>;
+			};
+
+			usbphyc_port1: usb-phy@1 {
+				#phy-cells = <1>;
+				reg = <1>;
+			};
+		};
+
 		rtc: rtc@5c004000 {
 			compatible = "st,stm32mp1-rtc";
 			reg = <0x5c004000 0x400>;
@@ -294,6 +1376,7 @@
 
 			part_number_otp: part_number_otp@4 {
 				reg = <0x4 0x2>;
+				bits = <0 12>;
 			};
 			ts_cal1: calib@5c {
 				reg = <0x5c 0x2>;
@@ -314,7 +1397,6 @@
 			ranges = <0 0x50002000 0x8400>;
 			interrupt-parent = <&exti>;
 			st,syscfg = <&exti 0x60 0xff>;
-			pins-are-numbered;
 
 			gpioa: gpio@50002000 {
 				gpio-controller;
diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi
index 531c263c9f..df451c3c2a 100644
--- a/arch/arm/dts/stm32mp133.dtsi
+++ b/arch/arm/dts/stm32mp133.dtsi
@@ -33,5 +33,36 @@
 			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
 			status = "disabled";
 		};
+
+		adc_1: adc@48003000 {
+			compatible = "st,stm32mp13-adc-core";
+			reg = <0x48003000 0x400>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
+			clock-names = "bus", "adc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			adc1: adc@0 {
+				compatible = "st,stm32mp13-adc";
+				#io-channel-cells = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0>;
+				interrupt-parent = <&adc_1>;
+				interrupts = <0>;
+				dmas = <&dmamux1 9 0x400 0x80000001>;
+				dma-names = "rx";
+				status = "disabled";
+
+				channel@18 {
+					reg = <18>;
+					label = "vrefint";
+				};
+			};
+		};
 	};
 };
diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
index 52f86596ce..f0900ca672 100644
--- a/arch/arm/dts/stm32mp135f-dk.dts
+++ b/arch/arm/dts/stm32mp135f-dk.dts
@@ -19,6 +19,13 @@
 
 	aliases {
 		serial0 = &uart4;
+		serial1 = &usart1;
+		serial2 = &uart8;
+		serial3 = &usart2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
 	};
 
 	memory@c0000000 {
@@ -40,7 +47,7 @@
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		user-pa13 {
+		button-user {
 			label = "User-PA13";
 			linux,code = <BTN_1>;
 			gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
@@ -59,6 +66,22 @@
 		};
 	};
 
+	v3v3_sw: v3v3-sw {
+		compatible = "regulator-fixed";
+		regulator-name = "v3v3_sw";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	vdd_adc: vdd-adc {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_adc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
 	vdd_sd: vdd-sd {
 		compatible = "regulator-fixed";
 		regulator-name = "vdd_sd";
@@ -66,6 +89,101 @@
 		regulator-max-microvolt = <2900000>;
 		regulator-always-on;
 	};
+
+	vdd_usb: vdd-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_usb";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+};
+
+&adc_1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&adc1_usb_cc_pins_a>;
+	vdda-supply = <&vdd_adc>;
+	vref-supply = <&vdd_adc>;
+	status = "okay";
+	adc1: adc@0 {
+		status = "okay";
+		/*
+		 * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12.
+		 * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+		 * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
+		 * Use arbitrary margin here (e.g. 5us).
+		 */
+		channel@6 {
+			reg = <6>;
+			st,min-sample-time-ns = <5000>;
+		};
+		channel@12 {
+			reg = <12>;
+			st,min-sample-time-ns = <5000>;
+		};
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&i2c1_pins_a>;
+	pinctrl-1 = <&i2c1_sleep_pins_a>;
+	i2c-scl-rising-time-ns = <96>;
+	i2c-scl-falling-time-ns = <3>;
+	clock-frequency = <1000000>;
+	status = "okay";
+	/* spare dmas for other usage */
+	/delete-property/dmas;
+	/delete-property/dma-names;
+
+	mcp23017: pinctrl@21 {
+		compatible = "microchip,mcp23017";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-parent = <&gpiog>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mcp23017_pins_a>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		microchip,irq-mirror;
+	};
+
+	typec@53 {
+		compatible = "st,stm32g0-typec";
+		reg = <0x53>;
+		/* Alert pin on PI2 */
+		interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-parent = <&gpioi>;
+		/* Internal pull-up on PI2 */
+		pinctrl-names = "default";
+		pinctrl-0 = <&stm32g0_intn_pins_a>;
+		firmware-name = "stm32g0-ucsi.mp135f-dk.fw";
+		connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+
+			port {
+				con_usb_c_g0_ep: endpoint {
+					remote-endpoint = <&usbotg_hs_ep>;
+				};
+			};
+		};
+	};
+};
+
+&i2c5 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&i2c5_pins_a>;
+	pinctrl-1 = <&i2c5_sleep_pins_a>;
+	i2c-scl-rising-time-ns = <170>;
+	i2c-scl-falling-time-ns = <5>;
+	clock-frequency = <400000>;
+	status = "okay";
+	/* spare dmas for other usage */
+	/delete-property/dmas;
+	/delete-property/dma-names;
 };
 
 &iwdg2 {
@@ -90,8 +208,163 @@
 	status = "okay";
 };
 
+&spi5 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&spi5_pins_a>;
+	pinctrl-1 = <&spi5_sleep_pins_a>;
+	status = "disabled";
+};
+
+&timers3 {
+	/delete-property/dmas;
+	/delete-property/dma-names;
+	status = "disabled";
+	pwm {
+		pinctrl-0 = <&pwm3_pins_a>;
+		pinctrl-1 = <&pwm3_sleep_pins_a>;
+		pinctrl-names = "default", "sleep";
+		status = "okay";
+	};
+	timer@2 {
+		status = "okay";
+	};
+};
+
+&timers4 {
+	/delete-property/dmas;
+	/delete-property/dma-names;
+	status = "disabled";
+	pwm {
+		pinctrl-0 = <&pwm4_pins_a>;
+		pinctrl-1 = <&pwm4_sleep_pins_a>;
+		pinctrl-names = "default", "sleep";
+		status = "okay";
+	};
+	timer@3 {
+		status = "okay";
+	};
+};
+
+&timers8 {
+	/delete-property/dmas;
+	/delete-property/dma-names;
+	status = "disabled";
+	pwm {
+		pinctrl-0 = <&pwm8_pins_a>;
+		pinctrl-1 = <&pwm8_sleep_pins_a>;
+		pinctrl-names = "default", "sleep";
+		status = "okay";
+	};
+	timer@7 {
+		status = "okay";
+	};
+};
+
+&timers14 {
+	status = "disabled";
+	pwm {
+		pinctrl-0 = <&pwm14_pins_a>;
+		pinctrl-1 = <&pwm14_sleep_pins_a>;
+		pinctrl-names = "default", "sleep";
+		status = "okay";
+	};
+	timer@13 {
+		status = "okay";
+	};
+};
+
 &uart4 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "sleep", "idle";
 	pinctrl-0 = <&uart4_pins_a>;
+	pinctrl-1 = <&uart4_sleep_pins_a>;
+	pinctrl-2 = <&uart4_idle_pins_a>;
+	/delete-property/dmas;
+	/delete-property/dma-names;
 	status = "okay";
 };
+
+&uart8 {
+	pinctrl-names = "default", "sleep", "idle";
+	pinctrl-0 = <&uart8_pins_a>;
+	pinctrl-1 = <&uart8_sleep_pins_a>;
+	pinctrl-2 = <&uart8_idle_pins_a>;
+	/delete-property/dmas;
+	/delete-property/dma-names;
+	status = "disabled";
+};
+
+&usart1 {
+	pinctrl-names = "default", "sleep", "idle";
+	pinctrl-0 = <&usart1_pins_a>;
+	pinctrl-1 = <&usart1_sleep_pins_a>;
+	pinctrl-2 = <&usart1_idle_pins_a>;
+	uart-has-rtscts;
+	status = "disabled";
+};
+
+/* Bluetooth */
+&usart2 {
+	pinctrl-names = "default", "sleep", "idle";
+	pinctrl-0 = <&usart2_pins_a>;
+	pinctrl-1 = <&usart2_sleep_pins_a>;
+	pinctrl-2 = <&usart2_idle_pins_a>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&usbh_ehci {
+	phys = <&usbphyc_port0>;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	/* onboard HUB */
+	hub@1 {
+		compatible = "usb424,2514";
+		reg = <1>;
+		vdd-supply = <&v3v3_sw>;
+	};
+};
+
+&usbotg_hs {
+	phys = <&usbphyc_port1 0>;
+	phy-names = "usb2-phy";
+	usb-role-switch;
+	status = "okay";
+	port {
+		usbotg_hs_ep: endpoint {
+			remote-endpoint = <&con_usb_c_g0_ep>;
+		};
+	};
+};
+
+&usbphyc {
+	status = "okay";
+};
+
+&usbphyc_port0 {
+	phy-supply = <&vdd_usb>;
+	st,current-boost-microamp = <1000>;
+	st,decrease-hs-slew-rate;
+	st,tune-hs-dc-level = <2>;
+	st,enable-hs-rftime-reduction;
+	st,trim-hs-current = <11>;
+	st,trim-hs-impedance = <2>;
+	st,tune-squelch-level = <1>;
+	st,enable-hs-rx-gain-eq;
+	st,no-hs-ftime-ctrl;
+	st,no-lsfs-sc;
+};
+
+&usbphyc_port1 {
+	phy-supply = <&vdd_usb>;
+	st,current-boost-microamp = <1000>;
+	st,decrease-hs-slew-rate;
+	st,tune-hs-dc-level = <2>;
+	st,enable-hs-rftime-reduction;
+	st,trim-hs-current = <11>;
+	st,trim-hs-impedance = <2>;
+	st,tune-squelch-level = <1>;
+	st,enable-hs-rx-gain-eq;
+	st,no-hs-ftime-ctrl;
+	st,no-lsfs-sc;
+};
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index 2cc9341d43..e86d989dd3 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -1261,7 +1261,7 @@
 	};
 
 	qspi_bk1_pins_a: qspi-bk1-0 {
-		pins1 {
+		pins {
 			pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
 				 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
 				 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
@@ -1270,12 +1270,6 @@
 			drive-push-pull;
 			slew-rate = <1>;
 		};
-		pins2 {
-			pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
-			bias-pull-up;
-			drive-push-pull;
-			slew-rate = <1>;
-		};
 	};
 
 	qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
@@ -1283,13 +1277,12 @@
 			pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
 				 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
 				 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
-				 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
-				 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+				 <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */
 		};
 	};
 
 	qspi_bk2_pins_a: qspi-bk2-0 {
-		pins1 {
+		pins {
 			pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
 				 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
 				 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
@@ -1298,7 +1291,34 @@
 			drive-push-pull;
 			slew-rate = <1>;
 		};
-		pins2 {
+	};
+
+	qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
+				 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
+				 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
+				 <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */
+		};
+	};
+
+	qspi_cs1_pins_a: qspi-cs1-0 {
+		pins {
+			pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
+			bias-pull-up;
+			drive-push-pull;
+			slew-rate = <1>;
+		};
+	};
+
+	qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+		};
+	};
+
+	qspi_cs2_pins_a: qspi-cs2-0 {
+		pins {
 			pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
 			bias-pull-up;
 			drive-push-pull;
@@ -1306,13 +1326,9 @@
 		};
 	};
 
-	qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+	qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 {
 		pins {
-			pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
-				 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
-				 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
-				 <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
-				 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
+			pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
 		};
 	};
 
@@ -1864,6 +1880,21 @@
 		};
 	};
 
+	spi1_pins_b: spi1-1 {
+		pins1 {
+			pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
+				 <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <1>;
+		};
+
+		pins2 {
+			pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
+			bias-disable;
+		};
+	};
+
 	spi2_pins_a: spi2-0 {
 		pins1 {
 			pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
@@ -2147,7 +2178,7 @@
 				 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
 			bias-disable;
 			drive-push-pull;
-			slew-rate = <3>;
+			slew-rate = <0>;
 		};
 		pins2 {
 			pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
@@ -2165,7 +2196,7 @@
 			pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
 			bias-disable;
 			drive-push-pull;
-			slew-rate = <3>;
+			slew-rate = <0>;
 		};
 		pins3 {
 			pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
@@ -2432,19 +2463,4 @@
 			bias-disable;
 		};
 	};
-
-	spi1_pins_b: spi1-1 {
-		pins1 {
-			pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
-				 <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
-			bias-disable;
-			drive-push-pull;
-			slew-rate = <1>;
-		};
-
-		pins2 {
-			pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
-			bias-disable;
-		};
-	};
 };
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
index d872c6fc56..573dd4d3ed 100644
--- a/arch/arm/dts/stm32mp15-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
@@ -226,6 +226,7 @@
 		mkimage {
 			args = "-T stm32image -a 0x2ffc2500 -e 0x2ffc2500";
 			u-boot-spl {
+				no-write-symbols;
 			};
 		};
 	};
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index 5d178b5d3c..21d11be328 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -1148,8 +1148,8 @@
 		usbotg_hs: usb-otg@49000000 {
 			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
 			reg = <0x49000000 0x10000>;
-			clocks = <&rcc USBO_K>;
-			clock-names = "otg";
+			clocks = <&rcc USBO_K>, <&usbphyc>;
+			clock-names = "otg", "utmi";
 			resets = <&rcc USBO_R>;
 			reset-names = "dwc2";
 			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
@@ -1693,7 +1693,6 @@
 			ranges = <0 0x50002000 0xa400>;
 			interrupt-parent = <&exti>;
 			st,syscfg = <&exti 0x60 0xff>;
-			pins-are-numbered;
 
 			gpioa: gpio@50002000 {
 				gpio-controller;
@@ -1822,7 +1821,6 @@
 			#size-cells = <1>;
 			compatible = "st,stm32mp157-z-pinctrl";
 			ranges = <0 0x54004000 0x400>;
-			pins-are-numbered;
 			interrupt-parent = <&exti>;
 			st,syscfg = <&exti 0x60 0xff>;
 
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index cff3f49948..2623cebf21 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -12,6 +12,7 @@
 		i2c3 = &i2c4;
 		usb0 = &usbotg_hs;
 	};
+
 	config {
 		u-boot,boot-led = "heartbeat";
 		u-boot,error-led = "error";
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index 4c8be9c8eb..0da3667ab1 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -17,9 +17,6 @@
 
 	aliases {
 		ethernet0 = &ethernet0;
-		serial0 = &uart4;
-		serial1 = &usart3;
-		serial2 = &uart7;
 	};
 
 	chosen {
diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi
index 5a8fc15ab2..ae93497cd5 100644
--- a/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi
@@ -4,3 +4,10 @@
  */
 
 #include "stm32mp157a-dk1-scmi-u-boot.dtsi"
+
+/ {
+	fwu-mdata {
+		compatible = "u-boot,fwu-mdata-gpt";
+		fwu-mdata-store = <&sdmmc1>;
+	};
+};
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index 2bc92ef3ae..ab13e340f4 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -18,9 +18,6 @@
 
 	aliases {
 		ethernet0 = &ethernet0;
-		serial0 = &uart4;
-		serial1 = &usart3;
-		serial2 = &uart7;
 		serial3 = &usart2;
 	};
 
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index fe5c8f25ce..3541a17dce 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -16,6 +16,10 @@
 	model = "STMicroelectronics STM32MP157C eval daughter";
 	compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
 
+	aliases {
+		serial0 = &uart4;
+	};
+
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
@@ -65,15 +69,6 @@
 			reg = <0x38000000 0x10000>;
 			no-map;
 		};
-
-		gpu_reserved: gpu@e8000000 {
-			reg = <0xe8000000 0x8000000>;
-			no-map;
-		};
-	};
-
-	aliases {
-		serial0 = &uart4;
 	};
 
 	sd_switch: regulator-sd_switch {
@@ -148,10 +143,6 @@
 	status = "okay";
 };
 
-&gpu {
-	contiguous-area = <&gpu_reserved>;
-};
-
 &hash1 {
 	status = "okay";
 };
diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi
index 71a94f9130..9768db8de9 100644
--- a/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi
@@ -14,4 +14,129 @@
 		spi0 = &qspi;
 		usb0 = &usbotg_hs;
 	};
+
+	fwu-mdata {
+		compatible = "u-boot,fwu-mdata-gpt";
+		fwu-mdata-store = <&sdmmc1>;
+	};
+};
+
+&flash0 {
+	bootph-pre-ram;
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 {
+			label = "fsbl1";
+			reg = <0x00000000 0x00040000>;
+		};
+		partition@40000 {
+			label = "fsbl2";
+			reg = <0x00040000 0x00040000>;
+		};
+		partition@80000 {
+			label = "metadata1";
+			reg = <0x00080000 0x00040000>;
+		};
+		partition@c0000 {
+			label = "metadata2";
+			reg = <0x000c0000 0x00040000>;
+		};
+		partition@100000 {
+			label = "fip-a";
+			reg = <0x00100000 0x00400000>;
+		};
+		partition@500000 {
+			label = "fip-b";
+			reg = <0x00500000 0x00400000>;
+		};
+		partition@900000 {
+			label = "u-boot-env";
+			reg = <0x00900000 0x00080000>;
+		};
+		partition@980000 {
+			label = "nor-user";
+			reg = <0x00980000 0x03680000>;
+		};
+	};
+};
+
+&fmc {
+	nand-controller@4,0 {
+		nand@0 {
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				partition@0 {
+					label = "fsbl1";
+					reg = <0x00000000 0x00080000>;
+				};
+				partition@80000 {
+					label = "fsbl2";
+					reg = <0x00080000 0x00080000>;
+				};
+				partition@100000 {
+					label = "metadata1";
+					reg = <0x00100000 0x00080000>;
+				};
+				partition@180000 {
+					label = "metadata2";
+					reg = <0x00180000 0x00080000>;
+				};
+				partition@200000 {
+					label = "fip-a1";
+					reg = <0x00200000 0x00400000>;
+				};
+				partition@600000 {
+					label = "fip-a2";
+					reg = <0x00600000 0x00400000>;
+				};
+				partition@a00000 {
+					label = "fip-b1";
+					reg = <0x00a00000 0x00400000>;
+				};
+				partition@e00000 {
+					label = "fip-b2";
+					reg = <0x00e00000 0x00400000>;
+				};
+				partition@1200000 {
+					label = "UBI";
+					reg = <0x01200000 0x3ee00000>;
+				};
+			};
+		};
+	};
+};
+
+&qspi {
+	bootph-pre-ram;
+};
+
+&qspi_clk_pins_a {
+	bootph-pre-ram;
+	pins {
+		bootph-pre-ram;
+	};
+};
+
+&qspi_bk1_pins_a {
+	bootph-pre-ram;
+	pins1 {
+		bootph-pre-ram;
+	};
+	pins2 {
+		bootph-pre-ram;
+	};
+};
+
+&qspi_bk2_pins_a {
+	bootph-pre-ram;
+	pins1 {
+		bootph-pre-ram;
+	};
+	pins2 {
+		bootph-pre-ram;
+	};
 };
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
index cb32c30431..1f7fdbce53 100644
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
@@ -23,6 +23,103 @@
 
 &flash0 {
 	bootph-pre-ram;
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
+		partition@0 {
+			label = "fsbl1";
+			reg = <0x00000000 0x00040000>;
+		};
+		partition@80000 {
+			label = "fsbl2";
+			reg = <0x00040000 0x00040000>;
+		};
+		partition@100000 {
+			label = "ssbl";
+			reg = <0x00080000 0x00200000>;
+		};
+		partition@280000  {
+			label = "u-boot-env";
+			reg = <0x00280000 0x00080000>;
+		};
+		partition@300000 {
+			label = "nor-user";
+			reg = <0x00300000 0x03d00000>;
+		};
+#else
+		partition@0 {
+			label = "fsbl1";
+			reg = <0x00000000 0x00040000>;
+		};
+		partition@40000 {
+			label = "fsbl2";
+			reg = <0x00040000 0x00040000>;
+		};
+		partition@100000 {
+			label = "fip";
+			reg = <0x00080000 0x00400000>;
+		};
+		partition@480000 {
+			label = "u-boot-env";
+			reg = <0x00480000 0x00080000>;
+		};
+		partition@500000 {
+			label = "nor-user";
+			reg = <0x00500000 0x03b00000>;
+		};
+#endif
+	};
+};
+
+&fmc {
+	nand-controller@4,0 {
+		nand@0 {
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
+				partition@0 {
+					label = "fsbl";
+					reg = <0x00000000 0x00200000>;
+				};
+				partition@200000 {
+					label = "ssbl1";
+					reg = <0x00200000 0x00200000>;
+				};
+				partition@400000 {
+					label = "ssbl2";
+					reg = <0x00400000 0x00200000>;
+				};
+				partition@600000 {
+					label = "UBI";
+					reg = <0x00600000 0x3fa00000>;
+				};
+#else
+				partition@0 {
+					label = "fsbl";
+					reg = <0x00000000 0x00200000>;
+				};
+				partition@200000 {
+					label = "fip1";
+					reg = <0x00200000 0x00400000>;
+				};
+				partition@600000 {
+					label = "fip2";
+					reg = <0x00600000 0x00400000>;
+				};
+				partition@1200000 {
+					label = "UBI";
+					reg = <0x00a00000 0x3f600000>;
+				};
+#endif
+			};
+		};
+	};
 };
 
 &qspi {
@@ -55,4 +152,3 @@
 		bootph-pre-ram;
 	};
 };
-
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index 2d5db41ed6..ba8e9d9a42 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -8,21 +8,21 @@
 #include "stm32mp157c-ed1.dts"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/media/video-interfaces.h>
 
 / {
 	model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
 	compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
 
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	aliases {
-		serial0 = &uart4;
 		serial1 = &usart3;
 		ethernet0 = &ethernet0;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	clocks {
 		clk_ext_camera: clk-ext-camera {
 			#clock-cells = <0>;
@@ -90,7 +90,7 @@
 	port {
 		dcmi_0: endpoint {
 			remote-endpoint = <&ov5640_0>;
-			bus-type = <5>;
+			bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
 			bus-width = <8>;
 			hsync-active = <0>;
 			vsync-active = <0>;
@@ -144,7 +144,7 @@
 	max-speed = <1000>;
 	phy-handle = <&phy0>;
 
-	mdio0 {
+	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "snps,dwmac-mdio";
@@ -255,8 +255,16 @@
 
 &qspi {
 	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
-	pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
+	pinctrl-0 = <&qspi_clk_pins_a
+		     &qspi_bk1_pins_a
+		     &qspi_cs1_pins_a
+		     &qspi_bk2_pins_a
+		     &qspi_cs2_pins_a>;
+	pinctrl-1 = <&qspi_clk_sleep_pins_a
+		     &qspi_bk1_sleep_pins_a
+		     &qspi_cs1_sleep_pins_a
+		     &qspi_bk2_sleep_pins_a
+		     &qspi_cs2_sleep_pins_a>;
 	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -393,6 +401,7 @@
 	st,tune-squelch-level = <3>;
 	st,tune-hs-rx-offset = <2>;
 	st,no-lsfs-sc;
+
 	connector {
 		compatible = "usb-a-connector";
 		vbus-supply = <&vbus_sw>;
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
index 83e2c87713..d3b85a8764 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
@@ -118,13 +118,12 @@
 
 &ethernet0 {
 	status = "okay";
-	pinctrl-0 = <&ethernet0_rmii_pins_a>;
-	pinctrl-1 = <&ethernet0_rmii_sleep_pins_a>;
+	pinctrl-0 = <&ethernet0_rmii_pins_c &mco2_pins_a>;
+	pinctrl-1 = <&ethernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>;
 	pinctrl-names = "default", "sleep";
 	phy-mode = "rmii";
 	max-speed = <100>;
 	phy-handle = <&phy0>;
-	st,eth-ref-clk-sel;
 
 	mdio0 {
 		#address-cells = <1>;
@@ -136,7 +135,7 @@
 			/* LAN8710Ai */
 			compatible = "ethernet-phy-id0007.c0f0",
 				     "ethernet-phy-ieee802.3-c22";
-			clocks = <&rcc ETHCK_K>;
+			clocks = <&rcc CK_MCO2>;
 			reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <500>;
 			reset-deassert-us = <500>;
@@ -429,8 +428,12 @@
 
 &qspi {
 	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
-	pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
+	pinctrl-0 = <&qspi_clk_pins_a
+		     &qspi_bk1_pins_a
+		     &qspi_cs1_pins_a>;
+	pinctrl-1 = <&qspi_clk_sleep_pins_a
+		     &qspi_bk1_sleep_pins_a
+		     &qspi_cs1_sleep_pins_a>;
 	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -446,6 +449,21 @@
 	};
 };
 
+&rcc {
+	/* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */
+	clocks = <&rcc CK_MCO2>;
+	clock-names = "ETH_RX_CLK/ETH_REF_CLK";
+
+	/*
+	 * Set PLL4P output to 100 MHz to supply SDMMC with faster clock,
+	 * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2,
+	 * so that MCO2 behaves as a divider for the ETHRX clock here.
+	 */
+	assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>;
+	assigned-clock-parents = <&rcc PLL4_P>;
+	assigned-clock-rates = <50000000>, <100000000>;
+};
+
 &rng1 {
 	status = "okay";
 };
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index bc0730cf2b..f12941b05f 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -92,6 +92,33 @@
 
 &flash0 {
 	bootph-pre-ram;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "fsbl1";
+			reg = <0x00000000 0x00040000>;
+		};
+		partition@40000 {
+			label = "fsbl2";
+			reg = <0x00040000 0x00040000>;
+		};
+		partition@500000 {
+			label = "uboot";
+			reg = <0x00080000 0x00160000>;
+		};
+		partition@900000 {
+			label = "env1";
+			reg = <0x001E0000 0x00010000>;
+		};
+		partition@980000 {
+			label = "env2";
+			reg = <0x001F0000 0x00010000>;
+		};
+	};
 };
 
 &qspi {
@@ -126,6 +153,20 @@
 };
 
 &rcc {
+	/*
+	 * Reinstate clock names from stm32mp151.dtsi, the MCO2 trick
+	 * used in stm32mp15xx-dhcom-som.dtsi is not supported by the
+	 * U-Boot clock framework.
+	 */
+	clock-names = "hse", "hsi", "csi", "lse", "lsi";
+	clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
+		 <&clk_lse>, <&clk_lsi>;
+
+	/* The MCO2 is already configured correctly, remove those. */
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+
 	st,clksrc = <
 		CLK_MPU_PLL1P
 		CLK_AXI_PLL2P
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi
index 98033b5147..f36eec1b4a 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi
@@ -191,8 +191,12 @@
 
 &qspi {
 	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
-	pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
+	pinctrl-0 = <&qspi_clk_pins_a
+		     &qspi_bk1_pins_a
+		     &qspi_cs1_pins_a>;
+	pinctrl-1 = <&qspi_clk_sleep_pins_a
+		     &qspi_bk1_sleep_pins_a
+		     &qspi_cs1_sleep_pins_a>;
 	reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index 804c66283e..eb905ad282 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -28,6 +28,33 @@
 
 &flash0 {
 	bootph-pre-ram;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "fsbl1";
+			reg = <0x00000000 0x00040000>;
+		};
+		partition@40000 {
+			label = "fsbl2";
+			reg = <0x00040000 0x00040000>;
+		};
+		partition@500000 {
+			label = "uboot";
+			reg = <0x00080000 0x00160000>;
+		};
+		partition@900000 {
+			label = "env1";
+			reg = <0x001E0000 0x00010000>;
+		};
+		partition@980000 {
+			label = "env2";
+			reg = <0x001F0000 0x00010000>;
+		};
+	};
 };
 
 &i2c4 {
diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
index 34af90195d..f4de6c0b75 100644
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
@@ -8,6 +8,12 @@
 #include <dt-bindings/mfd/st,stpmic1.h>
 
 / {
+	aliases {
+		serial0 = &uart4;
+		serial1 = &usart3;
+		serial2 = &uart7;
+	};
+
 	memory@c0000000 {
 		device_type = "memory";
 		reg = <0xc0000000 0x20000000>;
@@ -53,11 +59,6 @@
 			reg = <0x38000000 0x10000>;
 			no-map;
 		};
-
-		gpu_reserved: gpu@d4000000 {
-			reg = <0xd4000000 0x4000000>;
-			no-map;
-		};
 	};
 
 	led {
@@ -72,7 +73,7 @@
 
 	sound {
 		compatible = "audio-graph-card";
-		label = "STM32MP1-DK";
+		label = "STM32MP15-DK";
 		routing =
 			"Playback" , "MCLK",
 			"Capture" , "MCLK",
@@ -149,7 +150,7 @@
 	max-speed = <1000>;
 	phy-handle = <&phy0>;
 
-	mdio0 {
+	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "snps,dwmac-mdio";
@@ -159,10 +160,6 @@
 	};
 };
 
-&gpu {
-	contiguous-area = <&gpu_reserved>;
-};
-
 &hash1 {
 	status = "okay";
 };
@@ -509,14 +506,12 @@
 	sai2a: audio-controller@4400b004 {
 		#clock-cells = <0>;
 		dma-names = "tx";
-		clocks = <&rcc SAI2_K>;
-		clock-names = "sai_ck";
 		status = "okay";
 
 		sai2a_port: port {
 			sai2a_endpoint: endpoint {
 				remote-endpoint = <&cs42l51_tx_endpoint>;
-				format = "i2s";
+				dai-format = "i2s";
 				mclk-fs = <256>;
 				dai-tdm-slot-num = <2>;
 				dai-tdm-slot-width = <32>;
@@ -534,7 +529,7 @@
 		sai2b_port: port {
 			sai2b_endpoint: endpoint {
 				remote-endpoint = <&cs42l51_rx_endpoint>;
-				format = "i2s";
+				dai-format = "i2s";
 				mclk-fs = <256>;
 				dai-tdm-slot-num = <2>;
 				dai-tdm-slot-width = <32>;
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
index 9f9837b33b..9957646a46 100644
--- a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -21,7 +21,7 @@
 		#size-cells = <0>;
 		status = "okay";
 
-		flash@0 {
+		flash0: flash@0 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "jedec,spi-nor";
@@ -74,8 +74,24 @@
 				};
 
 				partition@500000 {
-					label = "Ex-OPTEE";
-					reg = <0x500000 0x200000>;
+					label = "MDATA-Pri";
+					reg = <0x500000 0x1000>;
+				};
+
+				partition@530000 {
+					label = "MDATA-Sec";
+					reg = <0x530000 0x1000>;
+				};
+
+				/* FWU Multi bank update partitions */
+				partition@600000 {
+					label = "FIP-Bank0";
+					reg = <0x600000 0x400000>;
+				};
+
+				partition@a00000 {
+					label = "FIP-Bank1";
+					reg = <0xa00000 0x400000>;
 				};
 			};
 		};
@@ -102,6 +118,33 @@
 		optee {
 			status = "okay";
 		};
+
+		fwu-mdata {
+			compatible = "u-boot,fwu-mdata-mtd";
+			fwu-mdata-store = <&flash0>;
+			mdata-parts = "MDATA-Pri", "MDATA-Sec";
+
+			fwu-bank0 {
+				id = <0>;
+				label = "FIP-Bank0";
+				fwu-image0 {
+					id = <0>;
+					offset = <0x0>;
+					size = <0x400000>;
+					uuid = "5a66a702-99fd-4fef-a392-c26e261a2828";
+				};
+			};
+			fwu-bank1 {
+				id = <1>;
+				label = "FIP-Bank1";
+				fwu-image0 {
+					id = <0>;
+					offset = <0x0>;
+					size = <0x400000>;
+					uuid = "a8f868a1-6e5c-4757-878d-ce63375ef2c0";
+				};
+			};
+		};
 	};
 };
 
diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts
index 1863d29d3d..bd685ddfdb 100644
--- a/arch/arm/dts/versal-mini-emmc0.dts
+++ b/arch/arm/dts/versal-mini-emmc0.dts
@@ -4,8 +4,8 @@
  *
  * (C) Copyright 2018-2019, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts
index 8701c3bb27..fbdcf5d77f 100644
--- a/arch/arm/dts/versal-mini-emmc1.dts
+++ b/arch/arm/dts/versal-mini-emmc1.dts
@@ -4,8 +4,8 @@
  *
  * (C) Copyright 2018-2019, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi
index 2d04521dd6..19caea7368 100644
--- a/arch/arm/dts/versal-mini-ospi.dtsi
+++ b/arch/arm/dts/versal-mini-ospi.dtsi
@@ -4,8 +4,8 @@
  *
  * (C) Copyright 2018-2019, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi
index bb8819dd25..2fec92ce3e 100644
--- a/arch/arm/dts/versal-mini-qspi.dtsi
+++ b/arch/arm/dts/versal-mini-qspi.dtsi
@@ -4,8 +4,8 @@
  *
  * (C) Copyright 2018-2019, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/versal-mini.dts b/arch/arm/dts/versal-mini.dts
index 769eb9e7b2..a213b745bc 100644
--- a/arch/arm/dts/versal-mini.dts
+++ b/arch/arm/dts/versal-mini.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2019, Xilinx, Inc.
  *
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/versal-net-mini-emmc.dts b/arch/arm/dts/versal-net-mini-emmc.dts
new file mode 100644
index 0000000000..8a864ba3ed
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-emmc.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal NET Mini eMMC Configuration
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ * Ashok Reddy Soma <ashok.reddy.soma@amd.com>
+ */
+
+/dts-v1/;
+
+/ {
+	compatible = "xlnx,versal-net-mini";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "Xilinx Versal NET MINI eMMC";
+
+	aliases {
+		serial0 = &dcc;
+		mmc0 = &sdhci1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0 0 0 0x20000000>;
+	};
+
+	clk200: clk200 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+	};
+
+	dcc: dcc {
+		compatible = "arm,dcc";
+		status = "okay";
+		bootph-all;
+	};
+
+	amba: amba {
+		bootph-all;
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		sdhci1: sdhci@f1050000 {
+			compatible = "xlnx,versal-net-emmc";
+			status = "okay";
+			non-removable;
+			disable-wp;
+			bus-width = <8>;
+			reg = <0 0xf1050000 0 0x10000>;
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <&clk200>, <&clk200>;
+			xlnx,mio-bank = <0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/versal-net-mini-ospi-single.dts b/arch/arm/dts/versal-net-mini-ospi-single.dts
new file mode 100644
index 0000000000..11a8e8b136
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-ospi-single.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET OSPI single DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ * Ashok Reddy Soma <ashok.reddy.soma@amd.com>
+ */
+
+#include "versal-net-mini-ospi.dtsi"
+
+/ {
+	model = "Xilinx Versal NET MINI OSPI SINGLE";
+};
+
+&flash0 {
+	spi-rx-bus-width = <8>;
+};
diff --git a/arch/arm/dts/versal-net-mini-ospi.dtsi b/arch/arm/dts/versal-net-mini-ospi.dtsi
new file mode 100644
index 0000000000..ce8e2158f6
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-ospi.dtsi
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal NET Mini OSPI Configuration
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ * Ashok Reddy Soma <ashok.reddy.soma@amd.com>
+ */
+
+/dts-v1/;
+
+/ {
+	compatible = "xlnx,versal-net-mini";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "Xilinx Versal NET MINI OSPI";
+
+	aliases {
+		serial0 = &dcc;
+		spi0 = &ospi;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200";
+	};
+
+	memory@bbf00000 {
+		device_type = "memory";
+		reg = <0 0xBBF00000 0 0x100000>;
+	};
+
+	clk125: clk125 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
+	dcc: dcc {
+		compatible = "arm,dcc";
+		status = "okay";
+		bootph-all;
+	};
+
+	amba: amba {
+		bootph-all;
+		compatible = "simple-bus";
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+
+		ospi: spi@f1010000 {
+			compatible = "cadence,qspi", "cdns,qspi-nor";
+			status = "okay";
+			reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;
+			clock-names = "ref_clk", "pclk";
+			clocks = <&clk125>, <&clk125>;
+			bus-num = <2>;
+			num-cs = <1>;
+			cdns,fifo-depth = <256>;
+			cdns,fifo-width = <4>;
+			cdns,is-dma = <1>;
+			cdns,is-stig-pgm = <1>;
+			cdns,trigger-address = <0xc0000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			flash0: flash@0 {
+				compatible = "mt35xu02g", "micron,m25p80",
+					     "jedec,spi-nor";
+				reg = <0>;
+				spi-tx-bus-width = <8>;
+				spi-rx-bus-width = <8>;
+				spi-max-frequency = <20000000>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi-single.dts b/arch/arm/dts/versal-net-mini-qspi-single.dts
new file mode 100644
index 0000000000..fec1b514ed
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI single DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+	model = "Xilinx Versal NET MINI QSPI SINGLE";
+};
+
+&flash0 {
+	spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi.dtsi b/arch/arm/dts/versal-net-mini-qspi.dtsi
new file mode 100644
index 0000000000..097b58c633
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal NET Mini QSPI Configuration
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ * Ashok Reddy Soma <ashok.reddy.soma@amd.com>
+ */
+
+/dts-v1/;
+
+/ {
+	compatible = "xlnx,versal-net-mini";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "Xilinx Versal NET MINI QSPI";
+
+	aliases {
+		serial0 = &dcc;
+		spi0 = &qspi;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200";
+	};
+
+	memory@bbf00000 {
+		device_type = "memory";
+		reg = <0 0xbbf00000 0 0x100000>;
+	};
+
+	clk150: clk150 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <150000000>;
+	};
+
+	dcc: dcc {
+		compatible = "arm,dcc";
+		status = "okay";
+		bootph-all;
+	};
+
+	amba: amba {
+		bootph-all;
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		qspi: spi@f1030000 {
+			compatible = "xlnx,versal-qspi-1.0";
+			status = "okay";
+			clock-names = "ref_clk", "pclk";
+			num-cs = <1>;
+			reg = <0 0xf1030000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clk150>, <&clk150>;
+
+			flash0: flash@0 {
+				compatible = "n25q512a", "micron,m25p80",
+					     "jedec,spi-nor";
+				reg = <0>;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				spi-max-frequency = <20000000>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 97a9e49a19..8c6eafec1d 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -153,6 +153,7 @@
 			clocks = <&clkc 38>;
 			interrupt-parent = <&intc>;
 			interrupts = <0 25 4>;
+			clock-frequency = <400000>;
 			reg = <0xe0004000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -164,6 +165,7 @@
 			clocks = <&clkc 39>;
 			interrupt-parent = <&intc>;
 			interrupts = <0 48 4>;
+			clock-frequency = <400000>;
 			reg = <0xe0005000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts
index cfe0710229..d06838c5ee 100644
--- a/arch/arm/dts/zynq-dlc20-rev1.0.dts
+++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts
@@ -2,7 +2,7 @@
 /*
  * Copyright (C) 2018 Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts
index 38365d1c0e..3214ee49e2 100644
--- a/arch/arm/dts/zynq-minized.dts
+++ b/arch/arm/dts/zynq-minized.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2017 - 2018, Xilinx, Inc.
  *
- * Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
+ * Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 27fb194fc9..8d47f24b75 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -5,6 +5,7 @@
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Xilinx ZC702 board";
@@ -102,8 +103,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c0_default>;
 	pinctrl-1 = <&pinctrl_i2c0_gpio>;
-	scl-gpios = <&gpio0 50 0>;
-	sda-gpios = <&gpio0 51 0>;
+	scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	i2c-mux@74 {
 		compatible = "nxp,pca9548";
diff --git a/arch/arm/dts/zynqmp-a2197-revA.dts b/arch/arm/dts/zynqmp-a2197-revA.dts
index 04f9f025e5..84167050d1 100644
--- a/arch/arm/dts/zynqmp-a2197-revA.dts
+++ b/arch/arm/dts/zynqmp-a2197-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2019, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 /dts-v1/;
 
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 38dc9cd8fc..1ae8ea2e43 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
@@ -126,7 +126,7 @@
 };
 
 &gpu {
-	clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;
+	clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
 };
 
 &lpd_dma_chan1 {
@@ -169,24 +169,28 @@
 	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
 		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
 		 <&zynqmp_clk GEM_TSU>;
+	assigned-clocks = <&zynqmp_clk GEM_TSU>;
 };
 
 &gem1 {
 	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
 		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
 		 <&zynqmp_clk GEM_TSU>;
+	assigned-clocks = <&zynqmp_clk GEM_TSU>;
 };
 
 &gem2 {
 	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
 		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
 		 <&zynqmp_clk GEM_TSU>;
+	assigned-clocks = <&zynqmp_clk GEM_TSU>;
 };
 
 &gem3 {
 	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
 		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
 		 <&zynqmp_clk GEM_TSU>;
+	assigned-clocks = <&zynqmp_clk GEM_TSU>;
 };
 
 &gpio {
@@ -285,10 +289,6 @@
 	clocks = <&zynqmp_clk AMS_REF>;
 };
 
-&zynqmp_pcap {
-	clocks = <&zynqmp_clk PCAP>;
-};
-
 &zynqmp_dpdma {
 	clocks = <&zynqmp_clk DPDMA_REF>;
 	assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index 7460e4a4fd..1b247bfa89 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2019 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 /dts-v1/;
 
@@ -131,7 +131,7 @@
 		  "", "", "", "", "", /* 155 - 159 */
 		  "", "", "", "", "", /* 160 - 164 */
 		  "", "", "", "", "", /* 165 - 169 */
-		  "", "", "", ""; /* 170 - 174 */
+		  "", "", "", ""; /* 170 - 173 */
 };
 
 &i2c0 { /* MIO34/35 */
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index 3fa18f560c..bf6ffb778b 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2019 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 /dts-v1/;
 
@@ -201,7 +201,7 @@
 		  "", "", "", "", "", /* 155 - 159 */
 		  "", "", "", "", "", /* 160 - 164 */
 		  "", "", "", "", "", /* 165 - 169 */
-		  "", "", "", ""; /* 170 - 174 */
+		  "", "", "", ""; /* 170 - 173 */
 };
 
 &i2c0 { /* MIO 34-35 - can't stay here */
diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
index 02d2427809..d5cfc61faf 100644
--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2019, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 /dts-v1/;
 
@@ -125,14 +125,14 @@
 		  "", "", "", "", "", /* 155 - 159 */
 		  "", "", "", "", "", /* 160 - 164 */
 		  "", "", "", "", "", /* 165 - 169 */
-		  "", "", "", ""; /* 170 - 174 */
+		  "", "", "", ""; /* 170 - 173 */
 };
 
 &i2c0 { /* MIO 34-35 - can't stay here */
 	status = "okay";
 	clock-frequency = <400000>;
-	scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	i2c-mux@74 { /* u94 */
 		compatible = "nxp,pca9548";
 		#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index 2d7fe592c8..97500b1328 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2019, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 /dts-v1/;
 
@@ -154,7 +154,7 @@
 		  "", "", "", "", "", /* 155 - 159 */
 		  "", "", "", "", "", /* 160 - 164 */
 		  "", "", "", "", "", /* 165 - 169 */
-		  "", "", "", ""; /* 170 - 174 */
+		  "", "", "", ""; /* 170 - 173 */
 };
 
 &i2c0 { /* MIO 34-35 - can't stay here */
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index e46748d32c..3bdcf052a5 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2019, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 /dts-v1/;
 
@@ -149,7 +149,7 @@
 		  "", "", "", "", "", /* 155 - 159 */
 		  "", "", "", "", "", /* 160 - 164 */
 		  "", "", "", "", "", /* 165 - 169 */
-		  "", "", "", ""; /* 170 - 174 */
+		  "", "", "", ""; /* 170 - 173 */
 };
 
 &i2c0 { /* MIO 34-35 - can't stay here */
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index f564817e2c..9a693a57a9 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2019, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 /dts-v1/;
 
@@ -149,7 +149,7 @@
 		  "", "", "", "", "", /* 155 - 159 */
 		  "", "", "", "", "", /* 160 - 164 */
 		  "", "", "", "", "", /* 165 - 169 */
-		  "", "", "", ""; /* 170 - 174 */
+		  "", "", "", ""; /* 170 - 173 */
 };
 
 &i2c0 { /* MIO 34-35 - can't stay here */
diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts
index d1e58eb6d1..08ec2f7b4a 100644
--- a/arch/arm/dts/zynqmp-mini-emmc0.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2018, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts
index 0c139f82aa..905de08fdb 100644
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2018, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts
index 8fae01b250..e5688fd703 100644
--- a/arch/arm/dts/zynqmp-mini-nand.dts
+++ b/arch/arm/dts/zynqmp-mini-nand.dts
@@ -4,8 +4,8 @@
  *
  * (C) Copyright 2018, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
index a7cf4eff6c..fc0a2e801e 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -4,8 +4,8 @@
  *
  * (C) Copyright 2015 - 2020, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-mini.dts b/arch/arm/dts/zynqmp-mini.dts
index 15bee169a9..b9a24f0436 100644
--- a/arch/arm/dts/zynqmp-mini.dts
+++ b/arch/arm/dts/zynqmp-mini.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2017, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
index d63deb83e3..16691a85e1 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2019, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 /dts-v1/;
 
@@ -134,7 +134,7 @@
 		  "", "", "", "", "", /* 155 - 159 */
 		  "", "", "", "", "", /* 160 - 164 */
 		  "", "", "", "", "", /* 165 - 169 */
-		  "", "", "", ""; /* 170 - 174 */
+		  "", "", "", ""; /* 170 - 173 */
 };
 
 &i2c0 { /* MIO 34-35 - can't stay here */
diff --git a/arch/arm/dts/zynqmp-r5.dts b/arch/arm/dts/zynqmp-r5.dts
index 9789d7144e..77b15fe158 100644
--- a/arch/arm/dts/zynqmp-r5.dts
+++ b/arch/arm/dts/zynqmp-r5.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2018, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
index c82e1dfac9..d318773bd9 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -68,8 +68,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	u14: ina260@40 { /* u14 */
 		compatible = "ti,ina260";
@@ -188,6 +188,7 @@
 	phy-handle = <&phy0>;
 	phy-mode = "sgmii";
 	is-internal-pcspma;
+	assigned-clock-rates = <250000000>;
 };
 
 &gem1 { /* mdio mio50/51, gem mio38 - mio49 */
@@ -196,6 +197,7 @@
 	pinctrl-0 = <&pinctrl_gem1_default>;
 	phy-handle = <&phy1>;
 	phy-mode = "rgmii-id";
+	assigned-clock-rates = <250000000>;
 
 	mdio: mdio {
 		#address-cells = <1>;
@@ -208,7 +210,7 @@
 			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
 			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 			ti,dp83867-rxctrl-strap-quirk;
-			reset-assert-us = <100>;
+			reset-assert-us = <300>;
 			reset-deassert-us = <280>;
 			reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
 		};
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
index 9dd160c7a7..69dba0761b 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2021 - 2022, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -68,8 +68,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	u14: ina260@40 { /* u14 */
 		compatible = "ti,ina260";
@@ -188,6 +188,7 @@
 	phy-handle = <&phy0>;
 	phy-mode = "sgmii";
 	is-internal-pcspma;
+	assigned-clock-rates = <250000000>;
 };
 
 &gem1 { /* mdio mio50/51, gem mio38 - mio49 */
@@ -196,6 +197,7 @@
 	pinctrl-0 = <&pinctrl_gem1_default>;
 	phy-handle = <&phy1>;
 	phy-mode = "rgmii-id";
+	assigned-clock-rates = <250000000>;
 
 	mdio: mdio {
 		#address-cells = <1>;
@@ -208,7 +210,7 @@
 			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
 			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 			ti,dp83867-rxctrl-strap-quirk;
-			reset-assert-us = <100>;
+			reset-assert-us = <300>;
 			reset-deassert-us = <280>;
 			reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
 		};
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index 6f5a426065..a81b3f6f51 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -9,7 +9,7 @@
  * "Y" – A01 board modified with legacy interposer (Nexperia)
  * "Z" – A01 board modified with Diode interposer
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -34,8 +34,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	u14: ina260@40 { /* u14 */
 		compatible = "ti,ina260";
@@ -165,6 +165,7 @@
 	pinctrl-0 = <&pinctrl_gem3_default>;
 	phy-handle = <&phy0>;
 	phy-mode = "rgmii-id";
+	assigned-clock-rates = <250000000>;
 
 	mdio: mdio {
 		#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 7764adf129..f935f25c88 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2020 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -16,7 +16,8 @@
 /plugin/;
 
 &{/} {
-	compatible = "xlnx,zynqmp-sk-kv260-rev1",
+	compatible = "xlnx,zynqmp-sk-kv260-rev2",
+		     "xlnx,zynqmp-sk-kv260-rev1",
 		     "xlnx,zynqmp-sk-kv260-revB",
 		     "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
 	model = "ZynqMP KV260 revB";
@@ -28,8 +29,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	u14: ina260@40 { /* u14 */
 		compatible = "ti,ina260";
@@ -152,6 +153,7 @@
 	pinctrl-0 = <&pinctrl_gem3_default>;
 	phy-handle = <&phy0>;
 	phy-mode = "rgmii-id";
+	assigned-clock-rates = <250000000>;
 
 	mdio: mdio {
 		#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts
index 24514409cb..653bd93622 100644
--- a/arch/arm/dts/zynqmp-sm-k24-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts
@@ -11,8 +11,9 @@
 #include "zynqmp-sm-k26-revA.dts"
 
 / {
-	model = "ZynqMP SM-K24 RevA";
-	compatible = "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24",
+	model = "ZynqMP SM-K24 RevA/B/1";
+	compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB",
+		     "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24",
 		     "xlnx,zynqmp";
 
 	memory@0 {
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index f6ed047f3d..d718fec760 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2020 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
@@ -50,6 +50,17 @@
 		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		pmu_region: pmu@7ff00000 {
+			reg = <0x0 0x7ff00000 0x0 0x100000>;
+			no-map;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -256,8 +267,8 @@
 	status = "okay";
 	bootph-all;
 	clock-frequency = <400000>;
-	scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	eeprom: eeprom@50 { /* u46 - also at address 0x58 */
 		bootph-all;
@@ -352,7 +363,7 @@
 			  "", "", "", "", "", /* 155 - 159 */
 			  "", "", "", "", "", /* 160 - 164 */
 			  "", "", "", "", "", /* 165 - 169 */
-			  "", "", "", ""; /* 170 - 174 */
+			  "", "", "", ""; /* 170 - 173 */
 };
 
 &xilinx_ams {
diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts
index c70966c1f3..85b0d16772 100644
--- a/arch/arm/dts/zynqmp-smk-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2020 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include "zynqmp-sm-k26-revA.dts"
diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts
index 63c553f772..a288029797 100644
--- a/arch/arm/dts/zynqmp-zc1232-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1232-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts
index 343033cc7e..5c4acd17cc 100644
--- a/arch/arm/dts/zynqmp-zc1254-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1254-revA.dts
@@ -4,8 +4,8 @@
  *
  * (C) Copyright 2015 - 2020, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 7ea2a1c96f..cffad44740 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2015 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
@@ -118,8 +118,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	eeprom: eeprom@55 {
 		compatible = "atmel,24c64"; /* 24AA64 */
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index b6bc2f5be0..bb0477825a 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2015 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
@@ -109,8 +109,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c0_default>;
 	pinctrl-1 = <&pinctrl_i2c0_gpio>;
-	scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	tca6416_u26: gpio@20 {
 		compatible = "ti,tca6416";
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index 6021f8b4e1..69ad58039e 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2016 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index e153a64f4f..3017c9b29a 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2015 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index ae2d03d983..74a5b020e8 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -4,8 +4,8 @@
  *
  * (C) Copyright 2015 - 2021, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
@@ -91,8 +91,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c0_default>;
 	pinctrl-1 = <&pinctrl_i2c0_gpio>;
-	scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 74 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 75 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 };
 
 &i2c1 {
@@ -100,8 +100,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 76 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 77 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 };
 
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 742a539864..a84cd86694 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2016 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  * Nathalie Chan King Choy
  */
 
@@ -188,8 +188,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	clock-frequency = <100000>;
 	i2c-mux@75 { /* u11 */
 		compatible = "nxp,pca9548";
@@ -569,6 +569,7 @@
 	pinctrl-0 = <&pinctrl_usb0_default>;
 	phy-names = "usb3-phy";
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
+	/delete-property/ reset-gpios;
 };
 
 &dwc3_0 {
@@ -584,6 +585,7 @@
 	pinctrl-0 = <&pinctrl_usb1_default>;
 	phy-names = "usb3-phy";
 	phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
+	reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
 };
 
 &dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
index d508f33599..c0a4d913af 100644
--- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
+++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2016 - 2020, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include "zynqmp-zcu102-revB.dts"
diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.1.dts b/arch/arm/dts/zynqmp-zcu102-rev1.1.dts
index b6798394fc..705369766a 100644
--- a/arch/arm/dts/zynqmp-zcu102-rev1.1.dts
+++ b/arch/arm/dts/zynqmp-zcu102-rev1.1.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2016 - 2020, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include "zynqmp-zcu102-rev1.0.dts"
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index d78bfb8987..79d67c495d 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2015 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
@@ -232,8 +232,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c0_default>;
 	pinctrl-1 = <&pinctrl_i2c0_gpio>;
-	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	tca6416_u97: gpio@20 {
 		compatible = "ti,tca6416";
@@ -496,8 +496,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	/* PL i2c via PCA9306 - u45 */
 	i2c-mux@74 { /* u34 */
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
index de3b5ab9d9..ce0a6e5f60 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2016 - 2020, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include "zynqmp-zcu102-revA.dts"
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index b9d82afc51..90fbfca87f 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
@@ -139,8 +139,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	/* Another connection to this bus via PL i2c via PCA9306 - u45 */
 	i2c-mux@74 { /* u34 */
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 6f24e335a1..69470f8ded 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
@@ -144,8 +144,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	tca6416_u97: gpio@20 {
 		compatible = "ti,tca6416";
diff --git a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts
index f43c477a17..a9b5826a77 100644
--- a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts
+++ b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2016 - 2022, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include "zynqmp-zcu106-revA.dts"
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 266c24e412..7a8094a16b 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2016 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
@@ -232,8 +232,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c0_default>;
 	pinctrl-1 = <&pinctrl_i2c0_gpio>;
-	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	tca6416_u97: gpio@20 {
 		compatible = "ti,tca6416";
@@ -495,8 +495,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	/* PL i2c via PCA9306 - u45 */
 	i2c-mux@74 { /* u34 */
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 8535cc0891..c9ff99f8a8 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
@@ -204,8 +204,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c0_default>;
 	pinctrl-1 = <&pinctrl_i2c0_gpio>;
-	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	tca6416_u22: gpio@20 {
 		compatible = "ti,tca6416";
@@ -384,8 +384,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	i2c-mux@74 { /* u26 */
 		compatible = "nxp,pca9548";
diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
index e88fc23b1f..9404c139a2 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -4,8 +4,8 @@
  *
  * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
index 97ae1b2d2d..c06d262506 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -4,8 +4,8 @@
  *
  * (C) Copyright 2018 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts
index eaf99a9fa8..99ea143c02 100644
--- a/arch/arm/dts/zynqmp-zcu1285-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
@@ -4,8 +4,8 @@
  *
  * (C) Copyright 2018 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 7e7e1577eb..9b3ae67bff 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
@@ -222,7 +222,7 @@
 		  "", "", "", "", "", /* 155 - 159 */
 		  "", "", "", "", "", /* 160 - 164 */
 		  "", "", "", "", "", /* 165 - 169 */
-		  "", "", "", ""; /* 170 - 174 */
+		  "", "", "", ""; /* 170 - 173 */
 };
 
 &i2c0 {
@@ -231,8 +231,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c0_default>;
 	pinctrl-1 = <&pinctrl_i2c0_gpio>;
-	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	tca6416_u15: gpio@20 { /* u15 */
 		compatible = "ti,tca6416";
@@ -397,8 +397,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	i2c-mux@74 {
 		compatible = "nxp,pca9548"; /* u20 */
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 35a30971cb..43eeaec5b1 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 /dts-v1/;
@@ -228,7 +228,7 @@
 		  "", "", "", "", "", /* 155 - 159 */
 		  "", "", "", "", "", /* 160 - 164 */
 		  "", "", "", "", "", /* 165 - 169 */
-		  "", "", "", ""; /* 170 - 174 */
+		  "", "", "", ""; /* 170 - 173 */
 };
 
 &gpu {
@@ -241,8 +241,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c0_default>;
 	pinctrl-1 = <&pinctrl_i2c0_gpio>;
-	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	tca6416_u15: gpio@20 { /* u15 */
 		compatible = "ti,tca6416";
@@ -407,8 +407,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1_default>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+	scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
 	i2c-mux@74 {
 		compatible = "nxp,pca9548"; /* u20 */
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 6a166381fa..1632be843b 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2014 - 2021, Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -33,6 +33,7 @@
 			operating-points-v2 = <&cpu_opp_table>;
 			reg = <0x0>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu1: cpu@1 {
@@ -42,6 +43,7 @@
 			reg = <0x1>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu2: cpu@2 {
@@ -51,6 +53,7 @@
 			reg = <0x2>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu3: cpu@3 {
@@ -60,6 +63,13 @@
 			reg = <0x3>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
 		};
 
 		idle-states {
@@ -111,7 +121,7 @@
 		#size-cells = <2>;
 		ranges;
 
-		ipi_mailbox_pmu1: mailbox@ff990400 {
+		ipi_mailbox_pmu1: mailbox@ff9905c0 {
 			bootph-all;
 			reg = <0x0 0xff9905c0 0x0 0x20>,
 			      <0x0 0xff9905e0 0x0 0x20>,
@@ -139,6 +149,10 @@
 			     <0 144 4>,
 			     <0 145 4>,
 			     <0 146 4>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>,
+				     <&cpu2>,
+				     <&cpu3>;
 	};
 
 	psci {
@@ -179,7 +193,6 @@
 
 			zynqmp_pcap: pcap {
 				compatible = "xlnx,zynqmp-pcap-fpga";
-				clock-names = "ref_clk";
 			};
 
 			xlnx_aes: zynqmp-aes {
@@ -396,12 +409,12 @@
 
 		gpu: gpu@fd4b0000 {
 			status = "disabled";
-			compatible = "arm,mali-400", "arm,mali-utgard";
+			compatible = "xlnx,zynqmp-mali", "arm,mali-400";
 			reg = <0x0 0xfd4b0000 0x0 0x10000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
-			interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
-			clock-names = "gpu", "gpu_pp0", "gpu_pp1";
+			interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
+			clock-names = "bus", "core";
 			power-domains = <&zynqmp_firmware PD_GPU>;
 		};
 
@@ -611,6 +624,7 @@
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 17 4>;
+			clock-frequency = <400000>;
 			reg = <0x0 0xff020000 0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -622,6 +636,7 @@
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 18 4>;
+			clock-frequency = <400000>;
 			reg = <0x0 0xff030000 0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -876,7 +891,6 @@
 				iommus = <&smmu 0x860>;
 				snps,quirk-frame-length-adjustment = <0x20>;
 				clock-names = "ref";
-				snps,enable_guctl1_resume_quirk;
 				snps,enable_guctl1_ipd_quirk;
 				snps,xhci-stream-quirk;
 				snps,resume-hs-terminations;
@@ -908,7 +922,6 @@
 				iommus = <&smmu 0x861>;
 				snps,quirk-frame-length-adjustment = <0x20>;
 				clock-names = "ref";
-				snps,enable_guctl1_resume_quirk;
 				snps,enable_guctl1_ipd_quirk;
 				snps,xhci-stream-quirk;
 				snps,resume-hs-terminations;
@@ -940,21 +953,19 @@
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 56 4>;
-			interrupt-names = "ams-irq";
 			reg = <0x0 0xffa50000 0x0 0x800>;
-			reg-names = "ams-base";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			#io-channel-cells = <1>;
 			ranges = <0 0 0xffa50800 0x800>;
 
-			ams_ps: ams_ps@0 {
+			ams_ps: ams-ps@0 {
 				compatible = "xlnx,zynqmp-ams-ps";
 				status = "disabled";
 				reg = <0x0 0x400>;
 			};
 
-			ams_pl: ams_pl@400 {
+			ams_pl: ams-pl@400 {
 				compatible = "xlnx,zynqmp-ams-pl";
 				status = "disabled";
 				reg = <0x400 0x400>;
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index ad25b3e8aa..67400c2c63 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -13,10 +13,6 @@
 #include <asm/arch/clocks_am33xx.h>
 #include <asm/arch/hardware.h>
 
-#if defined(CONFIG_TI816X)
-#include <asm/arch/clock_ti81xx.h>
-#endif
-
 #define LDELAY 1000000
 
 /*CM_<clock_domain>__CLKCTRL */
diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
deleted file mode 100644
index d22d958706..0000000000
--- a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * ti81xx.h
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * This file is released under the terms of GPL v2 and any later version.
- * See the file COPYING in the root directory of the source tree for details.
- */
-
-#ifndef _CLOCK_TI81XX_H_
-#define _CLOCK_TI81XX_H_
-
-#define PRCM_MOD_EN     0x2
-
-#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
-#define CM_ALWON_BASE   (PRCM_BASE + 0x1400)
-
-struct cm_def {
-	unsigned int resv0[2];
-	unsigned int l3fastclkstctrl;
-	unsigned int resv1[1];
-	unsigned int pciclkstctrl;
-	unsigned int resv2[1];
-	unsigned int ducaticlkstctrl;
-	unsigned int resv3[1];
-	unsigned int emif0clkctrl;
-	unsigned int emif1clkctrl;
-	unsigned int dmmclkctrl;
-	unsigned int fwclkctrl;
-	unsigned int resv4[10];
-	unsigned int usbclkctrl;
-	unsigned int resv5[1];
-	unsigned int sataclkctrl;
-	unsigned int resv6[4];
-	unsigned int ducaticlkctrl;
-	unsigned int pciclkctrl;
-};
-
-struct cm_alwon {
-	unsigned int l3slowclkstctrl;
-	unsigned int ethclkstctrl;
-	unsigned int l3medclkstctrl;
-	unsigned int mmu_clkstctrl;
-	unsigned int mmucfg_clkstctrl;
-	unsigned int ocmc0clkstctrl;
-#if defined(CONFIG_TI816X)
-	unsigned int ocmc1clkstctrl;
-#endif
-	unsigned int mpuclkstctrl;
-	unsigned int sysclk4clkstctrl;
-	unsigned int sysclk5clkstctrl;
-	unsigned int sysclk6clkstctrl;
-	unsigned int rtcclkstctrl;
-	unsigned int l3fastclkstctrl;
-	unsigned int resv0[67];
-	unsigned int mcasp0clkctrl;
-	unsigned int mcasp1clkctrl;
-	unsigned int mcasp2clkctrl;
-	unsigned int mcbspclkctrl;
-	unsigned int uart0clkctrl;
-	unsigned int uart1clkctrl;
-	unsigned int uart2clkctrl;
-	unsigned int gpio0clkctrl;
-	unsigned int gpio1clkctrl;
-	unsigned int i2c0clkctrl;
-	unsigned int i2c1clkctrl;
-#if defined(CONFIG_TI816X)
-	unsigned int resv1[1];
-	unsigned int timer1clkctrl;
-	unsigned int timer2clkctrl;
-	unsigned int timer3clkctrl;
-	unsigned int timer4clkctrl;
-	unsigned int timer5clkctrl;
-	unsigned int timer6clkctrl;
-	unsigned int timer7clkctrl;
-#endif
-	unsigned int wdtimerclkctrl;
-	unsigned int spiclkctrl;
-	unsigned int mailboxclkctrl;
-	unsigned int spinboxclkctrl;
-	unsigned int mmudataclkctrl;
-	unsigned int resv2[2];
-	unsigned int mmucfgclkctrl;
-#if defined(CONFIG_TI816X)
-	unsigned int resv3[1];
-	unsigned int sdioclkctrl;
-#endif
-	unsigned int ocmc0clkctrl;
-#if defined(CONFIG_TI816X)
-	unsigned int ocmc1clkctrl;
-#endif
-	unsigned int resv4[2];
-	unsigned int controlclkctrl;
-	unsigned int resv5[2];
-	unsigned int gpmcclkctrl;
-	unsigned int ethernet0clkctrl;
-	unsigned int ethernet1clkctrl;
-	unsigned int mpuclkctrl;
-#if defined(CONFIG_TI816X)
-	unsigned int resv6[1];
-#endif
-	unsigned int l3clkctrl;
-	unsigned int l4hsclkctrl;
-	unsigned int l4lsclkctrl;
-	unsigned int rtcclkctrl;
-	unsigned int tpccclkctrl;
-	unsigned int tptc0clkctrl;
-	unsigned int tptc1clkctrl;
-	unsigned int tptc2clkctrl;
-	unsigned int tptc3clkctrl;
-#if defined(CONFIG_TI816X)
-	unsigned int sr0clkctrl;
-	unsigned int sr1clkctrl;
-#endif
-};
-
-#endif /* _CLOCK_TI81XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 15a5b641ff..1a03107107 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -369,15 +369,9 @@ struct ddr_ctrl {
 	unsigned int ddrckectrl;
 };
 
-#ifdef CONFIG_TI816X
-void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
-		const struct emif_regs *regs,
-		const struct dmm_lisa_map_regs *lisa_regs, int nrs);
-#else
 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
 		const struct emif_regs *regs, int nr);
-#endif
 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
 
 #endif  /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/arch-am33xx/emac_defs.h b/arch/arm/include/asm/arch-am33xx/emac_defs.h
deleted file mode 100644
index eb6516da93..0000000000
--- a/arch/arm/include/asm/arch-am33xx/emac_defs.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010 Texas Instruments
- *
- * Based on:
- *
- * ----------------------------------------------------------------------------
- *
- * dm644x_emac.h
- *
- * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
- *
- * Copyright (C) 2005 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- *
- */
-
-#ifndef _EMAC_DEFS_H_
-#define _EMAC_DEFS_H_
-
-#ifdef CONFIG_TI816X
-#define EMAC_BASE_ADDR			(0x4A100000)
-#define EMAC_WRAPPER_BASE_ADDR		(0x4A100900)
-#define EMAC_WRAPPER_RAM_ADDR		(0x4A102000)
-#define EMAC_MDIO_BASE_ADDR		(0x4A100800)
-#define EMAC_MDIO_BUS_FREQ		(250000000UL)
-#define EMAC_MDIO_CLOCK_FREQ		(2000000UL)
-
-typedef volatile unsigned int	dv_reg;
-typedef volatile unsigned int	*dv_reg_p;
-
-#define DAVINCI_EMAC_VERSION2
-#define DAVINCI_EMAC_GIG_ENABLE
-#endif
-
-#endif  /* _EMAC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 2d7f9da365..387f053ce6 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -14,8 +14,6 @@
 #include <asm/arch/omap.h>
 #ifdef CONFIG_AM33XX
 #include <asm/arch/hardware_am33xx.h>
-#elif defined(CONFIG_TI816X)
-#include <asm/arch/hardware_ti816x.h>
 #elif defined(CONFIG_AM43XX)
 #include <asm/arch/hardware_am43xx.h>
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
deleted file mode 100644
index 78b79486ed..0000000000
--- a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * hardware_ti816x.h
- *
- * TI816x hardware specific header
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- * Based on TI-PSP-04.00.02.14
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __AM33XX_HARDWARE_TI816X_H
-#define __AM33XX_HARDWARE_TI816X_H
-
-/* UART */
-#define UART0_BASE		0x48020000
-#define UART1_BASE		0x48022000
-#define UART2_BASE		0x48024000
-
-/* Watchdog Timer */
-#define WDT_BASE		0x480C2000
-
-/* Control Module Base Address */
-#define CTRL_BASE		0x48140000
-#define CTRL_DEVICE_BASE	0x48140600
-
-/* PRCM Base Address */
-#define PRCM_BASE		0x48180000
-
-#define PRM_RSTCTRL		(PRCM_BASE + 0x00A0)
-#define PRM_RSTST		(PRM_RSTCTRL + 8)
-
-/* VTP Base address */
-#define VTP0_CTRL_ADDR		0x48198358
-#define VTP1_CTRL_ADDR		0x4819A358
-
-/* DDR Base address */
-#define DDR_PHY_CMD_ADDR	0x48198000
-#define DDR_PHY_DATA_ADDR	0x481980C8
-#define DDR_PHY_CMD_ADDR2	0x4819A000
-#define DDR_PHY_DATA_ADDR2	0x4819A0C8
-#define DDR_DATA_REGS_NR	4
-
-
-#define DDRPHY_0_CONFIG_BASE	0x48198000
-#define DDRPHY_1_CONFIG_BASE	0x4819A000
-#define DDRPHY_CONFIG_BASE	((emif == 0) ? \
-	DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE)
-
-/* RTC base address */
-#define RTC_BASE		0x480C0000
-
-#endif /* __AM33XX_HARDWARE_TI816X_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index ed15d15c5b..b1b189631a 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -24,9 +24,4 @@
 #define OMAP_HSMMC1_BASE		0x48060000
 #define OMAP_HSMMC2_BASE		0x481D8000
 
-#if defined(CONFIG_TI816X)
-#undef MMC_CLOCK_REFERENCE
-#define MMC_CLOCK_REFERENCE	48 /* MHz */
-#endif
-
 #endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
index 7cf973710d..ebb2d303df 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -20,8 +20,6 @@
 
 #ifdef CONFIG_AM33XX
 #include <asm/arch/mux_am33xx.h>
-#elif defined(CONFIG_TI816X)
-#include <asm/arch/mux_ti816x.h>
 #elif defined(CONFIG_AM43XX)
 #include <asm/arch/mux_am43xx.h>
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
deleted file mode 100644
index a6a8a988a0..0000000000
--- a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * mux_ti816x.h
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _MUX_TI816X_H_
-#define _MUX_TI816X_H_
-
-#include <asm/io.h>
-
-#define MUX_CFG(value, offset)  \
-	__raw_writel(value, (CTRL_BASE + offset));
-
-#define PULLDOWN_EN	(0x0 << 4)	/* Pull Down Selection */
-#define PULLUP_EN	(0x1 << 4)	/* Pull Up Selection */
-#define PULLUDEN	(0x0 << 3)	/* Pull up enabled */
-#define PULLUDDIS	(0x1 << 3)	/* Pull up disabled */
-#define MODE(val)	(val)		/* used for Readability */
-
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
-	int pincntl1;
-	int pincntl2;
-	int pincntl3;
-	int pincntl4;
-	int pincntl5;
-	int pincntl6;
-	int pincntl7;
-	int pincntl8;
-	int pincntl9;
-	int pincntl10;
-	int pincntl11;
-	int pincntl12;
-	int pincntl13;
-	int pincntl14;
-	int pincntl15;
-	int pincntl16;
-	int pincntl17;
-	int pincntl18;
-	int pincntl19;
-	int pincntl20;
-	int pincntl21;
-	int pincntl22;
-	int pincntl23;
-	int pincntl24;
-	int pincntl25;
-	int pincntl26;
-	int pincntl27;
-	int pincntl28;
-	int pincntl29;
-	int pincntl30;
-	int pincntl31;
-	int pincntl32;
-	int pincntl33;
-	int pincntl34;
-	int pincntl35;
-	int pincntl36;
-	int pincntl37;
-	int pincntl38;
-	int pincntl39;
-	int pincntl40;
-	int pincntl41;
-	int pincntl42;
-	int pincntl43;
-	int pincntl44;
-	int pincntl45;
-	int pincntl46;
-	int pincntl47;
-	int pincntl48;
-	int pincntl49;
-	int pincntl50;
-	int pincntl51;
-	int pincntl52;
-	int pincntl53;
-	int pincntl54;
-	int pincntl55;
-	int pincntl56;
-	int pincntl57;
-	int pincntl58;
-	int pincntl59;
-	int pincntl60;
-	int pincntl61;
-	int pincntl62;
-	int pincntl63;
-	int pincntl64;
-	int pincntl65;
-	int pincntl66;
-	int pincntl67;
-	int pincntl68;
-	int pincntl69;
-	int pincntl70;
-	int pincntl71;
-	int pincntl72;
-	int pincntl73;
-	int pincntl74;
-	int pincntl75;
-	int pincntl76;
-	int pincntl77;
-	int pincntl78;
-	int pincntl79;
-	int pincntl80;
-	int pincntl81;
-	int pincntl82;
-	int pincntl83;
-	int pincntl84;
-	int pincntl85;
-	int pincntl86;
-	int pincntl87;
-	int pincntl88;
-	int pincntl89;
-	int pincntl90;
-	int pincntl91;
-	int pincntl92;
-	int pincntl93;
-	int pincntl94;
-	int pincntl95;
-	int pincntl96;
-	int pincntl97;
-	int pincntl98;
-	int pincntl99;
-	int pincntl100;
-	int pincntl101;
-	int pincntl102;
-	int pincntl103;
-	int pincntl104;
-	int pincntl105;
-	int pincntl106;
-	int pincntl107;
-	int pincntl108;
-	int pincntl109;
-	int pincntl110;
-	int pincntl111;
-	int pincntl112;
-	int pincntl113;
-	int pincntl114;
-	int pincntl115;
-	int pincntl116;
-	int pincntl117;
-	int pincntl118;
-	int pincntl119;
-	int pincntl120;
-	int pincntl121;
-	int pincntl122;
-	int pincntl123;
-	int pincntl124;
-	int pincntl125;
-	int pincntl126;
-	int pincntl127;
-	int pincntl128;
-	int pincntl129;
-	int pincntl130;
-	int pincntl131;
-	int pincntl132;
-	int pincntl133;
-	int pincntl134;
-	int pincntl135;
-	int pincntl136;
-	int pincntl137;
-	int pincntl138;
-	int pincntl139;
-	int pincntl140;
-	int pincntl141;
-	int pincntl142;
-	int pincntl143;
-	int pincntl144;
-	int pincntl145;
-	int pincntl146;
-	int pincntl147;
-	int pincntl148;
-	int pincntl149;
-	int pincntl150;
-	int pincntl151;
-	int pincntl152;
-	int pincntl153;
-	int pincntl154;
-	int pincntl155;
-	int pincntl156;
-	int pincntl157;
-	int pincntl158;
-	int pincntl159;
-	int pincntl160;
-	int pincntl161;
-	int pincntl162;
-	int pincntl163;
-	int pincntl164;
-	int pincntl165;
-	int pincntl166;
-	int pincntl167;
-	int pincntl168;
-	int pincntl169;
-	int pincntl170;
-	int pincntl171;
-	int pincntl172;
-	int pincntl173;
-	int pincntl174;
-	int pincntl175;
-	int pincntl176;
-	int pincntl177;
-	int pincntl178;
-	int pincntl179;
-	int pincntl180;
-	int pincntl181;
-	int pincntl182;
-	int pincntl183;
-	int pincntl184;
-	int pincntl185;
-	int pincntl186;
-	int pincntl187;
-	int pincntl188;
-	int pincntl189;
-	int pincntl190;
-	int pincntl191;
-	int pincntl192;
-	int pincntl193;
-	int pincntl194;
-	int pincntl195;
-	int pincntl196;
-	int pincntl197;
-	int pincntl198;
-	int pincntl199;
-	int pincntl200;
-	int pincntl201;
-	int pincntl202;
-	int pincntl203;
-	int pincntl204;
-	int pincntl205;
-	int pincntl206;
-	int pincntl207;
-	int pincntl208;
-	int pincntl209;
-	int pincntl210;
-	int pincntl211;
-	int pincntl212;
-	int pincntl213;
-	int pincntl214;
-	int pincntl215;
-	int pincntl216;
-	int pincntl217;
-	int pincntl218;
-	int pincntl219;
-	int pincntl220;
-	int pincntl221;
-	int pincntl222;
-	int pincntl223;
-	int pincntl224;
-	int pincntl225;
-	int pincntl226;
-	int pincntl227;
-	int pincntl228;
-	int pincntl229;
-	int pincntl230;
-	int pincntl231;
-	int pincntl232;
-	int pincntl233;
-	int pincntl234;
-	int pincntl235;
-	int pincntl236;
-	int pincntl237;
-	int pincntl238;
-	int pincntl239;
-	int pincntl240;
-	int pincntl241;
-	int pincntl242;
-	int pincntl243;
-	int pincntl244;
-	int pincntl245;
-	int pincntl246;
-	int pincntl247;
-	int pincntl248;
-	int pincntl249;
-	int pincntl250;
-	int pincntl251;
-	int pincntl252;
-	int pincntl253;
-	int pincntl254;
-	int pincntl255;
-	int pincntl256;
-	int pincntl257;
-	int pincntl258;
-	int pincntl259;
-	int pincntl260;
-	int pincntl261;
-	int pincntl262;
-	int pincntl263;
-	int pincntl264;
-	int pincntl265;
-	int pincntl266;
-	int pincntl267;
-	int pincntl268;
-	int pincntl269;
-	int pincntl270;
-	int pincntl271;
-	int pincntl272;
-	int pincntl273;
-	int pincntl274;
-	int pincntl275;
-	int pincntl276;
-	int pincntl277;
-	int pincntl278;
-	int pincntl279;
-	int pincntl280;
-	int pincntl281;
-	int pincntl282;
-	int pincntl283;
-	int pincntl284;
-	int pincntl285;
-	int pincntl286;
-	int pincntl287;
-	int pincntl288;
-	int pincntl289;
-	int pincntl290;
-	int pincntl291;
-	int pincntl292;
-	int pincntl293;
-	int pincntl294;
-	int pincntl295;
-	int pincntl296;
-	int pincntl297;
-	int pincntl298;
-	int pincntl299;
-	int pincntl300;
-	int pincntl301;
-	int pincntl302;
-	int pincntl303;
-	int pincntl304;
-	int pincntl305;
-	int pincntl306;
-	int pincntl307;
-	int pincntl308;
-	int pincntl309;
-	int pincntl310;
-	int pincntl311;
-	int pincntl312;
-	int pincntl313;
-	int pincntl314;
-	int pincntl315;
-	int pincntl316;
-	int pincntl317;
-	int pincntl318;
-	int pincntl319;
-	int pincntl320;
-	int pincntl321;
-	int pincntl322;
-	int pincntl323;
-};
-
-#endif /* endif _MUX_TI816X_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index 4c71dbf3ab..53046deed5 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -20,10 +20,6 @@
 #define NON_SECURE_SRAM_START	0x402F0400
 #define NON_SECURE_SRAM_END	0x40310000
 #define NON_SECURE_SRAM_IMG_END	0x4030B800
-#elif defined(CONFIG_TI816X)
-#define NON_SECURE_SRAM_START	0x40300000
-#define NON_SECURE_SRAM_END	0x40320000
-#define NON_SECURE_SRAM_IMG_END	0x4031B800
 #elif defined(CONFIG_AM43XX)
 #define NON_SECURE_SRAM_START	0x402F0400
 #define NON_SECURE_SRAM_END	0x40340000
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 6bd3ca0d07..9ddb346dc9 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -9,19 +9,7 @@
 #define BOOT_DEVICE_NONE	0x00
 #define BOOT_DEVICE_MMC2_2	0xFF
 
-#if defined(CONFIG_TI816X)
-#define BOOT_DEVICE_XIP		0x01
-#define BOOT_DEVICE_XIPWAIT	0x02
-#define BOOT_DEVICE_NAND	0x03
-#define BOOT_DEVICE_ONENAND	0x04
-#define BOOT_DEVICE_MMC2	0x05 /* ROM only supports 2nd instance. */
-#define BOOT_DEVICE_MMC1	0x06
-#define BOOT_DEVICE_UART	0x43
-#define BOOT_DEVICE_USB		0x45
-
-#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC2
-#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC1
-#elif defined(CONFIG_AM33XX)
+#if defined(CONFIG_AM33XX)
 #define BOOT_DEVICE_XIP		0x01
 #define BOOT_DEVICE_XIPWAIT	0x02
 #define BOOT_DEVICE_NAND	0x05
diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h
deleted file mode 100644
index fd8dad394a..0000000000
--- a/arch/arm/include/asm/arch-bcmcygnus/configs.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014-2017 Broadcom.
- */
-
-#ifndef __ARCH_CONFIGS_H
-#define __ARCH_CONFIGS_H
-
-#include <asm/iproc-common/configs.h>
-
-/* uArchitecture specifics */
-
-/* Serial Info */
-#define CFG_SYS_NS16550_CLK		100000000
-#define CFG_SYS_NS16550_CLK_DIV	54
-#define CFG_SYS_NS16550_COM3		0x18023000
-
-#endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h
deleted file mode 100644
index 0d4baf3c00..0000000000
--- a/arch/arm/include/asm/arch-bcmnsp/configs.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Broadcom Corporation.
- */
-
-#ifndef __ARCH_CONFIGS_H
-#define __ARCH_CONFIGS_H
-
-#include <asm/iproc-common/configs.h>
-
-/* uArchitecture specifics */
-
-/* Serial Info */
-#define CFG_SYS_NS16550_CLK		0x03b9aca0
-#define CFG_SYS_NS16550_COM1		0x18000300
-
-#endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
index 1b02d484d9..c18c51ed2c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
@@ -22,7 +22,7 @@
  *
  *  -PCIe
  *     -there is a range of stream IDs set aside for PCI in this
- *      file.  U-boot will scan the PCI bus and for each device discovered:
+ *      file.  U-Boot will scan the PCI bus and for each device discovered:
  *         -allocate a streamID
  *         -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
  *         -set a msi-map entry in the PEXn controller node in the
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index b36b6d3889..140849d4e1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -23,7 +23,7 @@
  *
  *  -PCIe
  *     -there is a range of stream IDs set aside for PCI in this
- *      file.  U-boot will scan the PCI bus and for each device discovered:
+ *      file.  U-Boot will scan the PCI bus and for each device discovered:
  *         -allocate a streamID
  *         -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
  *         -set a msi-map entry in the PEXn controller node in the
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 6e2fc82a0e..f1b7526ac7 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -13,7 +13,7 @@
 #define ROM_VERSION_A0		IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
 #define ROM_VERSION_B0		IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
 
-#define M4_BOOTROM_BASE_ADDR   0x007E0000
+#define MCU_BOOTROM_BASE_ADDR   0x007E0000
 
 #define GPIO1_BASE_ADDR		0X30200000
 #define GPIO2_BASE_ADDR		0x30210000
@@ -40,6 +40,7 @@
 #define UART1_BASE_ADDR		0x30860000
 #define UART3_BASE_ADDR		0x30880000
 #define UART2_BASE_ADDR		0x30890000
+#define CAAM_BASE_ADDR		0x30900000
 #define I2C1_BASE_ADDR		0x30A20000
 #define I2C2_BASE_ADDR		0x30A30000
 #define I2C3_BASE_ADDR		0x30A40000
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h
index 55b46afaf7..4ed8e954e3 100644
--- a/arch/arm/include/asm/arch-imx8m/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -4,7 +4,7 @@
  */
 
 #ifndef __ARCH_IMX8M_SYS_PROTO_H
-#define __ARCH_NMX8M_SYS_PROTO_H
+#define __ARCH_IMX8M_SYS_PROTO_H
 
 #include <asm/mach-imx/sys_proto.h>
 #include <asm/arch/imx-regs.h>
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 5bbae21e37..95bf753a76 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -4,7 +4,7 @@
  */
 
 #ifndef __ARCH_IMX8ULP_SYS_PROTO_H
-#define __ARCH_NMX8ULP_SYS_PROTO_H
+#define __ARCH_IMX8ULP_SYS_PROTO_H
 
 #include <asm/mach-imx/sys_proto.h>
 
diff --git a/arch/arm/include/asm/arch-imx9/ccm_regs.h b/arch/arm/include/asm/arch-imx9/ccm_regs.h
index d326a6ea51..f6ec8fda3e 100644
--- a/arch/arm/include/asm/arch-imx9/ccm_regs.h
+++ b/arch/arm/include/asm/arch-imx9/ccm_regs.h
@@ -12,7 +12,7 @@
 #define ARM_A55_MTR_BUS_CLK_ROOT	1
 #define ARM_A55_CLK_ROOT		2
 #define M33_CLK_ROOT			3
-#define SENTINEL_CLK_ROOT		4
+#define ELE_CLK_ROOT			4
 #define BUS_WAKEUP_CLK_ROOT		5
 #define BUS_AON_CLK_ROOT		6
 #define WAKEUP_AXI_CLK_ROOT		7
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h
index ba97f92f5a..2f7a129275 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -4,7 +4,7 @@
  */
 
 #ifndef __ARCH_IMX9_SYS_PROTO_H
-#define __ARCH_NMX9_SYS_PROTO_H
+#define __ARCH_IMX9_SYS_PROTO_H
 
 #include <asm/mach-imx/sys_proto.h>
 
diff --git a/arch/arm/include/asm/arch-imxrt/imxrt.h b/arch/arm/include/asm/arch-imxrt/imxrt.h
deleted file mode 100644
index 14f7c769b0..0000000000
--- a/arch/arm/include/asm/arch-imxrt/imxrt.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#ifndef _ASM_ARCH_IMXRT_H
-#define _ASM_ARCH_IMXRT_H
-
-#endif /* _ASM_ARCH_IMXRT_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
deleted file mode 100644
index 762bbeee0a..0000000000
--- a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * LPC32xx GPIO interface macro for pin mapping.
- *
- * (C) Copyright 2015  DENX Software Engineering GmbH
- * Written-by: Sylvain Lemieux <slemieux@@tycoint.com>
- */
-
-#ifndef _LPC32XX_GPIO_GRP_H
-#define _LPC32XX_GPIO_GRP_H
-
-/*
- * Macro to map the pin for the lpc32xx_gpio driver.
- * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
- *         mapping is done per register, as group of 32.
- *         (see drivers/gpio/lpc32xx_gpio.c for details).
- *       - macros can be use with the following pins:
- *         P0.0 - P0.7
- *         P1.0 - P1.23
- *         P2.0 - P2.12
- *         P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28
- *         P3 GPO_0 - GPO_23
- *         P3 GPIO_0 - GPIO_5 (output register only)
- */
-#define LPC32XX_GPIO_P0_GRP 0
-#define LPC32XX_GPIO_P1_GRP 32
-#define LPC32XX_GPIO_P2_GRP 64
-#define LPC32XX_GPO_P3_GRP  96
-#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
-#define LPC32XX_GPI_P3_GRP  128
-
-/*
- * A specific GPIO can be selected with this macro
- * ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1)
- * See the LPC32x0 User's guide for GPIO group numbers
- */
-#define LPC32XX_GPIO(x, y) ((x) + (y))
-
-#endif /* _LPC32XX_GPIO_GRP_H */
diff --git a/arch/arm/include/asm/arch-meson/a1.h b/arch/arm/include/asm/arch-meson/a1.h
new file mode 100644
index 0000000000..86d1a68de8
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/a1.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2023 SberDevices, Inc.
+ * Author: Igor Prusov <ivprusov@sberdevices.ru>
+ */
+
+#ifndef __MESON_A1_H__
+#define __MESON_A1_H__
+
+#define A1_SYSCTRL_BASE			0xfe005800
+
+/* SYSCTRL registers */
+#define A1_SYSCTRL_ADDR(off)		(A1_SYSCTRL_BASE + ((off) << 2))
+
+#define A1_SYSCTRL_SEC_STATUS_REG4	A1_SYSCTRL_ADDR(0xc4)
+
+#define A1_SYSCTRL_MEM_SIZE_MASK	0xFFFF0000
+#define A1_SYSCTRL_MEM_SIZE_SHIFT	16
+
+#endif /* __MESON_A1_H__ */
diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
index 53b7517649..4b1d564bc4 100644
--- a/arch/arm/include/asm/arch-meson/sm.h
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -58,4 +58,34 @@ enum {
  */
 int meson_sm_get_reboot_reason(void);
 
+#define PWRDM_OFF 0
+#define PWRDM_ON 1
+
+/**
+ * meson_sm_pwrdm_set - do command at specified power domain.
+ *
+ * @index: power domain index.
+ * @cmd: command index.
+ * @return: zero on success or error code on failure.
+ */
+int meson_sm_pwrdm_set(size_t index, int cmd);
+
+/**
+ * meson_sm_pwrdm_off - disable specified power domain.
+ *
+ * @index: power domain index.
+ * @return: zero on success or error code on failure.
+ */
+#define meson_sm_pwrdm_off(index) \
+	meson_sm_pwrdm_set(index, PWRDM_OFF)
+
+/**
+ * meson_sm_pwrdm_on - enable specified power domain.
+ *
+ * @index: power domain index.
+ * @return: zero on success or error code on failure.
+ */
+#define meson_sm_pwrdm_on(index) \
+	meson_sm_pwrdm_set(index, PWRDM_ON)
+
 #endif /* __MESON_SM_H__ */
diff --git a/arch/arm/include/asm/arch-mx27/mxcmmc.h b/arch/arm/include/asm/arch-mx27/mxcmmc.h
deleted file mode 100644
index 52fb0ab578..0000000000
--- a/arch/arm/include/asm/arch-mx27/mxcmmc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- */
-
-#ifndef ASM_ARCH_MXCMMC_H
-#define ASM_ARCH_MXCMMC_H
-
-int mxc_mmc_init(struct bd_info *bis);
-
-#endif
diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index 63a51042e1..d585b5cf4b 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -42,7 +42,7 @@ enum mxc_clock {
 u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
-int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
+int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk);
 void set_usb_phy_clk(void);
 void enable_usb_phy1_clk(bool enable);
 void enable_usb_phy2_clk(bool enable);
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 72944af18a..8fd3dd2df3 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -23,7 +23,7 @@
 #define GPU_ARB_END_ADDR                0x01803FFF
 #define APBH_DMA_ARB_BASE_ADDR          0x01804000
 #define APBH_DMA_ARB_END_ADDR           0x0180BFFF
-#define M4_BOOTROM_BASE_ADDR			0x007F8000
+#define MCU_BOOTROM_BASE_ADDR			0x007F8000
 
 #elif !defined(CONFIG_MX6SLL)
 #define CAAM_ARB_BASE_ADDR              0x00100000
diff --git a/arch/arm/include/asm/arch-mx6/opos6ul.h b/arch/arm/include/asm/arch-mx6/opos6ul.h
deleted file mode 100644
index b55a54cf1c..0000000000
--- a/arch/arm/include/asm/arch-mx6/opos6ul.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Armadeus Systems
- */
-
-#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__
-#define __ARCH_ARM_MX6UL_OPOS6UL_H__
-
-int opos6ul_board_late_init(void);
-
-#endif
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index c863cd9da3..6f5ae5173c 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -18,7 +18,7 @@
 #define GIC400_ARB_END_ADDR             0x31007FFF
 #define APBH_DMA_ARB_BASE_ADDR          0x33000000
 #define APBH_DMA_ARB_END_ADDR           0x33007FFF
-#define M4_BOOTROM_BASE_ADDR            0x00180000
+#define MCU_BOOTROM_BASE_ADDR            0x00180000
 
 #define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
 #define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h
deleted file mode 100644
index d89cf27b6a..0000000000
--- a/arch/arm/include/asm/arch-mxs/regs-uartapp.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Freescale MXS UARTAPP Register Definitions
- *
- * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
- *
- * Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-#ifndef __ARCH_ARM___MXS_UARTAPP_H
-#define __ARCH_ARM___MXS_UARTAPP_H
-
-#include <asm/mach-imx/regs-common.h>
-
-#ifndef __ASSEMBLY__
-struct mxs_uartapp_regs {
-	mxs_reg_32(hw_uartapp_ctrl0)
-	mxs_reg_32(hw_uartapp_ctrl1)
-	mxs_reg_32(hw_uartapp_ctrl2)
-	mxs_reg_32(hw_uartapp_linectrl)
-	mxs_reg_32(hw_uartapp_linectrl2)
-	mxs_reg_32(hw_uartapp_intr)
-	mxs_reg_32(hw_uartapp_data)
-	mxs_reg_32(hw_uartapp_stat)
-	mxs_reg_32(hw_uartapp_debug)
-	mxs_reg_32(hw_uartapp_version)
-	mxs_reg_32(hw_uartapp_autobaud)
-};
-#endif
-
-#define UARTAPP_CTRL0_SFTRST_MASK				(1 << 31)
-#define UARTAPP_CTRL0_CLKGATE_MASK			(1 << 30)
-#define UARTAPP_CTRL0_RUN_MASK				(1 << 29)
-#define UARTAPP_CTRL0_RX_SOURCE_MASK			(1 << 28)
-#define UARTAPP_CTRL0_RXTO_ENABLE_MASK			(1 << 27)
-#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET			16
-#define UARTAPP_CTRL0_RXTIMEOUT_MASK			(0x7FF << 16)
-#define UARTAPP_CTRL0_XFER_COUNT_OFFSET			0
-#define UARTAPP_CTRL0_XFER_COUNT_MASK			0xFFFF
-
-#define UARTAPP_CTRL1_RUN_MASK				(1 << 28)
-
-#define UARTAPP_CTRL1_XFER_COUNT_OFFSET			0
-#define UARTAPP_CTRL1_XFER_COUNT_MASK			0xFFFF
-
-#define UARTAPP_CTRL2_INVERT_RTS_MASK			(1 << 31)
-#define UARTAPP_CTRL2_INVERT_CTS_MASK			(1 << 30)
-#define UARTAPP_CTRL2_INVERT_TX_MASK			(1 << 29)
-#define UARTAPP_CTRL2_INVERT_RX_MASK			(1 << 28)
-#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK			(1 << 27)
-#define UARTAPP_CTRL2_DMAONERR_MASK			(1 << 26)
-#define UARTAPP_CTRL2_TXDMAE_MASK				(1 << 25)
-#define UARTAPP_CTRL2_RXDMAE_MASK				(1 << 24)
-#define UARTAPP_CTRL2_RXIFLSEL_OFFSET			20
-#define UARTAPP_CTRL2_RXIFLSEL_MASK			(0x7 << 20)
-
-#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY		(0x0 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER		(0x1 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF		(0x2 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS		(0x3 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS		(0x4 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_INVALID5		(0x5 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_INVALID6		(0x6 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_INVALID7		(0x7 << 20)
-#define UARTAPP_CTRL2_TXIFLSEL_OFFSET			16
-#define UARTAPP_CTRL2_TXIFLSEL_MASK			(0x7 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_EMPTY			(0x0 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER		(0x1 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF		(0x2 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS		(0x3 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS		(0x4 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_INVALID5		(0x5 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_INVALID6		(0x6 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_INVALID7		(0x7 << 16)
-#define UARTAPP_CTRL2_CTSEN_MASK				(1 << 15)
-#define UARTAPP_CTRL2_RTSEN_MASK				(1 << 14)
-#define UARTAPP_CTRL2_OUT2_MASK				(1 << 13)
-#define UARTAPP_CTRL2_OUT1_MASK				(1 << 12)
-#define UARTAPP_CTRL2_RTS_MASK				(1 << 11)
-#define UARTAPP_CTRL2_DTR_MASK				(1 << 10)
-#define UARTAPP_CTRL2_RXE_MASK				(1 << 9)
-#define UARTAPP_CTRL2_TXE_MASK				(1 << 8)
-#define UARTAPP_CTRL2_LBE_MASK				(1 << 7)
-#define UARTAPP_CTRL2_USE_LCR2_MASK			(1 << 6)
-
-#define UARTAPP_CTRL2_SIRLP_MASK				(1 << 2)
-#define UARTAPP_CTRL2_SIREN_MASK				(1 << 1)
-#define UARTAPP_CTRL2_UARTEN_MASK				0x01
-
-#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET			16
-#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK			(0xFFFF << 16)
-#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET		6
-
-#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET		8
-#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK		(0x3F << 8)
-#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK	0x3F
-
-#define UARTAPP_LINECTRL_SPS_MASK				(1 << 7)
-#define UARTAPP_LINECTRL_WLEN_OFFSET			5
-#define UARTAPP_LINECTRL_WLEN_MASK			(0x03 << 5)
-#define UARTAPP_LINECTRL_WLEN_5BITS			(0x00 << 5)
-#define UARTAPP_LINECTRL_WLEN_6BITS			(0x01 << 5)
-#define UARTAPP_LINECTRL_WLEN_7BITS			(0x02 << 5)
-#define UARTAPP_LINECTRL_WLEN_8BITS			(0x03 << 5)
-
-#define UARTAPP_LINECTRL_FEN_MASK				(1 << 4)
-#define UARTAPP_LINECTRL_STP2_MASK			(1 << 3)
-#define UARTAPP_LINECTRL_EPS_MASK				(1 << 2)
-#define UARTAPP_LINECTRL_PEN_MASK				(1 << 1)
-#define UARTAPP_LINECTRL_BRK_MASK				1
-
-#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET		16
-#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK		(0xFFFF << 16)
-#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET	6
-
-#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET		8
-#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK		(0x3F << 8)
-#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK	0x3F
-
-#define UARTAPP_LINECTRL2_SPS_MASK			(1 << 7)
-#define UARTAPP_LINECTRL2_WLEN_OFFSET			5
-#define UARTAPP_LINECTRL2_WLEN_MASK			(0x03 << 5)
-#define UARTAPP_LINECTRL2_WLEN_5BITS			(0x00 << 5)
-#define UARTAPP_LINECTRL2_WLEN_6BITS			(0x01 << 5)
-#define UARTAPP_LINECTRL2_WLEN_7BITS			(0x02 << 5)
-#define UARTAPP_LINECTRL2_WLEN_8BITS			(0x03 << 5)
-
-#define UARTAPP_LINECTRL2_FEN_MASK			(1 << 4)
-#define UARTAPP_LINECTRL2_STP2_MASK			(1 << 3)
-#define UARTAPP_LINECTRL2_EPS_MASK			(1 << 2)
-#define UARTAPP_LINECTRL2_PEN_MASK			(1 << 1)
-
-#define UARTAPP_INTR_ABDIEN_MASK				(1 << 27)
-#define UARTAPP_INTR_OEIEN_MASK				(1 << 26)
-#define UARTAPP_INTR_BEIEN_MASK				(1 << 25)
-#define UARTAPP_INTR_PEIEN_MASK				(1 << 24)
-#define UARTAPP_INTR_FEIEN_MASK				(1 << 23)
-#define UARTAPP_INTR_RTIEN_MASK				(1 << 22)
-#define UARTAPP_INTR_TXIEN_MASK				(1 << 21)
-#define UARTAPP_INTR_RXIEN_MASK				(1 << 20)
-#define UARTAPP_INTR_DSRMIEN_MASK				(1 << 19)
-#define UARTAPP_INTR_DCDMIEN_MASK				(1 << 18)
-#define UARTAPP_INTR_CTSMIEN_MASK				(1 << 17)
-#define UARTAPP_INTR_RIMIEN_MASK				(1 << 16)
-
-#define UARTAPP_INTR_ABDIS_MASK				(1 << 11)
-#define UARTAPP_INTR_OEIS_MASK				(1 << 10)
-#define UARTAPP_INTR_BEIS_MASK				(1 << 9)
-#define UARTAPP_INTR_PEIS_MASK				(1 << 8)
-#define UARTAPP_INTR_FEIS_MASK				(1 << 7)
-#define UARTAPP_INTR_RTIS_MASK				(1 << 6)
-#define UARTAPP_INTR_TXIS_MASK				(1 << 5)
-#define UARTAPP_INTR_RXIS_MASK				(1 << 4)
-#define UARTAPP_INTR_DSRMIS_MASK				(1 << 3)
-#define UARTAPP_INTR_DCDMIS_MASK				(1 << 2)
-#define UARTAPP_INTR_CTSMIS_MASK				(1 << 1)
-#define UARTAPP_INTR_RIMIS_MASK				0x1
-
-#define UARTAPP_DATA_DATA_OFFSET				0
-#define UARTAPP_DATA_DATA_MASK				0xFFFFFFFF
-#define UARTAPP_STAT_PRESENT_MASK				(1 << 31)
-#define UARTAPP_STAT_PRESENT_UNAVAILABLE		(0x0 << 31)
-#define UARTAPP_STAT_PRESENT_AVAILABLE			(0x1 << 31)
-
-#define UARTAPP_STAT_HISPEED_MASK				(1 << 30)
-#define UARTAPP_STAT_HISPEED_UNAVAILABLE		(0x0 << 30)
-#define UARTAPP_STAT_HISPEED_AVAILABLE			(0x1 << 30)
-
-#define UARTAPP_STAT_BUSY_MASK				(1 << 29)
-#define UARTAPP_STAT_CTS_MASK				(1 << 28)
-#define UARTAPP_STAT_TXFE_MASK				(1 << 27)
-#define UARTAPP_STAT_RXFF_MASK				(1 << 26)
-#define UARTAPP_STAT_TXFF_MASK				(1 << 25)
-#define UARTAPP_STAT_RXFE_MASK				(1 << 24)
-#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET			20
-#define UARTAPP_STAT_RXBYTE_INVALID_MASK		(0xF << 20)
-
-#define UARTAPP_STAT_OERR_MASK				(1 << 19)
-#define UARTAPP_STAT_BERR_MASK				(1 << 18)
-#define UARTAPP_STAT_PERR_MASK				(1 << 17)
-#define UARTAPP_STAT_FERR_MASK				(1 << 16)
-#define UARTAPP_STAT_RXCOUNT_OFFSET				0
-#define UARTAPP_STAT_RXCOUNT_MASK				0xFFFF
-
-#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET			16
-#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK				(0xFFFF << 16)
-
-#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET			10
-#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK				(0x3F << 10)
-
-#define UARTAPP_DEBUG_TXDMARUN_MASK			(1 << 5)
-#define UARTAPP_DEBUG_RXDMARUN_MASK			(1 << 4)
-#define UARTAPP_DEBUG_TXCMDEND_MASK			(1 << 3)
-#define UARTAPP_DEBUG_RXCMDEND_MASK			(1 << 2)
-#define UARTAPP_DEBUG_TXDMARQ_MASK			(1 << 1)
-#define UARTAPP_DEBUG_RXDMARQ_MASK			0x01
-
-#define UARTAPP_VERSION_MAJOR_OFFSET			24
-#define UARTAPP_VERSION_MAJOR_MASK			(0xFF << 24)
-
-#define UARTAPP_VERSION_MINOR_OFFSET			16
-#define UARTAPP_VERSION_MINOR_MASK			(0xFF << 16)
-
-#define UARTAPP_VERSION_STEP_OFFSET				0
-#define UARTAPP_VERSION_STEP_MASK				0xFFFF
-
-#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET			24
-#define UARTAPP_AUTOBAUD_REFCHAR1_MASK				(0xFF << 24)
-
-#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET			16
-#define UARTAPP_AUTOBAUD_REFCHAR0_MASK				(0xFF << 16)
-
-#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK			(1 << 4)
-#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK		(1 << 3)
-#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK		(1 << 2)
-#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK		(1 << 1)
-#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK		0x01
-#endif /* __ARCH_ARM___UARTAPP_H */
diff --git a/arch/arm/include/asm/arch-npcm8xx/gcr.h b/arch/arm/include/asm/arch-npcm8xx/gcr.h
index ee6677a0e5..20230d64e6 100644
--- a/arch/arm/include/asm/arch-npcm8xx/gcr.h
+++ b/arch/arm/include/asm/arch-npcm8xx/gcr.h
@@ -12,6 +12,7 @@
 /* On-Chip ARBEL NPCM8XX VERSIONS */
 #define ARBEL_Z1			0x00A35850
 #define ARBEL_A1			0x04a35850
+#define ARBEL_A2			0x08a35850
 #define ARBEL_NPCM845			0x00000000
 #define ARBEL_NPCM830			0x00300395
 #define ARBEL_NPCM810			0x00000220
diff --git a/arch/arm/include/asm/arch-omap3/omap3-regs.h b/arch/arm/include/asm/arch-omap3/omap3-regs.h
deleted file mode 100644
index 7b3c6c7ab5..0000000000
--- a/arch/arm/include/asm/arch-omap3/omap3-regs.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it>
- */
-
-#ifndef _OMAP3_REGS_H
-#define _OMAP3_REGS_H
-
-/*
- * Register definitions for OMAP3 processors.
- */
-
-/*
- * GPMC_CONFIG1 - GPMC_CONFIG7
- */
-
-/* Values for GPMC_CONFIG1 - signal control parameters */
-#define WRAPBURST                     (1 << 31)
-#define READMULTIPLE                  (1 << 30)
-#define READTYPE                      (1 << 29)
-#define WRITEMULTIPLE                 (1 << 28)
-#define WRITETYPE                     (1 << 27)
-#define CLKACTIVATIONTIME(x)          (((x) & 3) << 25)
-#define ATTACHEDDEVICEPAGELENGTH(x)   (((x) & 3) << 23)
-#define WAITREADMONITORING            (1 << 22)
-#define WAITWRITEMONITORING           (1 << 21)
-#define WAITMONITORINGTIME(x)         (((x) & 3) << 18)
-#define WAITPINSELECT(x)              (((x) & 3) << 16)
-#define DEVICESIZE(x)                 (((x) & 3) << 12)
-#define DEVICESIZE_8BIT               DEVICESIZE(0)
-#define DEVICESIZE_16BIT              DEVICESIZE(1)
-#define DEVICETYPE(x)                 (((x) & 3) << 10)
-#define DEVICETYPE_NOR                DEVICETYPE(0)
-#define DEVICETYPE_NAND               DEVICETYPE(2)
-#define MUXADDDATA                    (1 << 9)
-#define TIMEPARAGRANULARITY           (1 << 4)
-#define GPMCFCLKDIVIDER(x)            (((x) & 3) << 0)
-
-/* Values for GPMC_CONFIG2 - CS timing */
-#define CSWROFFTIME(x)   (((x) & 0x1f) << 16)
-#define CSRDOFFTIME(x)   (((x) & 0x1f) <<  8)
-#define CSEXTRADELAY     (1 << 7)
-#define CSONTIME(x)      (((x) &  0xf) <<  0)
-
-/* Values for GPMC_CONFIG3 - nADV timing */
-#define ADVWROFFTIME(x)  (((x) & 0x1f) << 16)
-#define ADVRDOFFTIME(x)  (((x) & 0x1f) <<  8)
-#define ADVEXTRADELAY    (1 << 7)
-#define ADVONTIME(x)     (((x) &  0xf) <<  0)
-
-/* Values for GPMC_CONFIG4 - nWE and nOE timing */
-#define WEOFFTIME(x)     (((x) & 0x1f) << 24)
-#define WEEXTRADELAY     (1 << 23)
-#define WEONTIME(x)      (((x) &  0xf) << 16)
-#define OEOFFTIME(x)     (((x) & 0x1f) <<  8)
-#define OEEXTRADELAY     (1 << 7)
-#define OEONTIME(x)      (((x) &  0xf) <<  0)
-
-/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */
-#define PAGEBURSTACCESSTIME(x)  (((x) &  0xf) << 24)
-#define RDACCESSTIME(x)         (((x) & 0x1f) << 16)
-#define WRCYCLETIME(x)          (((x) & 0x1f) <<  8)
-#define RDCYCLETIME(x)          (((x) & 0x1f) <<  0)
-
-/* Values for GPMC_CONFIG6 - misc timings */
-#define WRACCESSTIME(x)        (((x) & 0x1f) << 24)
-#define WRDATAONADMUXBUS(x)    (((x) &  0xf) << 16)
-#define CYCLE2CYCLEDELAY(x)    (((x) &  0xf) <<  8)
-#define CYCLE2CYCLESAMECSEN    (1 << 7)
-#define CYCLE2CYCLEDIFFCSEN    (1 << 6)
-#define BUSTURNAROUND(x)       (((x) &  0xf) <<  0)
-
-/* Values for GPMC_CONFIG7 - CS address mapping configuration */
-#define MASKADDRESS(x)         (((x) &  0xf) <<  8)
-#define CSVALID                (1 << 6)
-#define BASEADDRESS(x)         (((x) & 0x3f) <<  0)
-
-#endif /* _OMAP3_REGS_H */
diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h
deleted file mode 100644
index 2460646e36..0000000000
--- a/arch/arm/include/asm/arch-omap5/mux_omap5.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated
- * Richard Woodruff		<r-woodruff2@ti.com>
- * Aneesh V			<aneesh@ti.com>
- * Balaji Krishnamoorthy	<balajitk@ti.com>
- */
-#ifndef _MUX_OMAP5_H_
-#define _MUX_OMAP5_H_
-
-#include <asm/types.h>
-
-#ifdef CONFIG_OFF_PADCONF
-#define OFF_PD          (1 << 12)
-#define OFF_PU          (3 << 12)
-#define OFF_OUT_PTD     (0 << 10)
-#define OFF_OUT_PTU     (2 << 10)
-#define OFF_IN          (1 << 10)
-#define OFF_OUT         (0 << 10)
-#define OFF_EN          (1 << 9)
-#else
-#define OFF_PD          (0 << 12)
-#define OFF_PU          (0 << 12)
-#define OFF_OUT_PTD     (0 << 10)
-#define OFF_OUT_PTU     (0 << 10)
-#define OFF_IN          (0 << 10)
-#define OFF_OUT         (0 << 10)
-#define OFF_EN          (0 << 9)
-#endif
-
-#define IEN             (1 << 8)
-#define IDIS            (0 << 8)
-#define PTU             (3 << 3)
-#define PTD             (1 << 3)
-#define EN              (1 << 3)
-#define DIS             (0 << 3)
-
-#define M0              0
-#define M1              1
-#define M2              2
-#define M3              3
-#define M4              4
-#define M5              5
-#define M6              6
-#define M7              7
-
-#define SAFE_MODE	M7
-
-#ifdef CONFIG_OFF_PADCONF
-#define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
-#define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
-#define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
-#define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
-#else
-#define OFF_IN_PD       0
-#define OFF_IN_PU       0
-#define OFF_OUT_PD      0
-#define OFF_OUT_PU      0
-#endif
-
-#define CORE_REVISION		0x0000
-#define CORE_HWINFO		0x0004
-#define CORE_SYSCONFIG		0x0010
-#define EMMC_CLK		0x0040
-#define EMMC_CMD		0x0042
-#define EMMC_DATA0		0x0044
-#define EMMC_DATA1		0x0046
-#define EMMC_DATA2		0x0048
-#define EMMC_DATA3		0x004a
-#define EMMC_DATA4		0x004c
-#define EMMC_DATA5		0x004e
-#define EMMC_DATA6		0x0050
-#define EMMC_DATA7		0x0052
-#define C2C_CLKOUT0		0x0054
-#define C2C_CLKOUT1		0x0056
-#define C2C_CLKIN0		0x0058
-#define C2C_CLKIN1		0x005a
-#define C2C_DATAIN0		0x005c
-#define C2C_DATAIN1		0x005e
-#define C2C_DATAIN2		0x0060
-#define C2C_DATAIN3		0x0062
-#define C2C_DATAIN4		0x0064
-#define C2C_DATAIN5		0x0066
-#define C2C_DATAIN6		0x0068
-#define C2C_DATAIN7		0x006a
-#define C2C_DATAOUT0		0x006c
-#define C2C_DATAOUT1		0x006e
-#define C2C_DATAOUT2		0x0070
-#define C2C_DATAOUT3		0x0072
-#define C2C_DATAOUT4		0x0074
-#define C2C_DATAOUT5		0x0076
-#define C2C_DATAOUT6		0x0078
-#define C2C_DATAOUT7		0x007a
-#define C2C_DATA8		0x007c
-#define C2C_DATA9		0x007e
-#define C2C_DATA10		0x0080
-#define C2C_DATA11		0x0082
-#define C2C_DATA12		0x0084
-#define C2C_DATA13		0x0086
-#define C2C_DATA14		0x0088
-#define C2C_DATA15		0x008a
-#define LLIA_WAKEREQOUT		0x008c
-#define LLIB_WAKEREQOUT		0x008e
-#define HSI1_ACREADY		0x0090
-#define HSI1_CAREADY		0x0092
-#define HSI1_ACWAKE		0x0094
-#define HSI1_CAWAKE		0x0096
-#define HSI1_ACFLAG		0x0098
-#define HSI1_ACDATA		0x009a
-#define HSI1_CAFLAG		0x009c
-#define HSI1_CADATA		0x009e
-#define UART1_TX		0x00a0
-#define UART1_CTS		0x00a2
-#define UART1_RX		0x00a4
-#define UART1_RTS		0x00a6
-#define HSI2_CAREADY		0x00a8
-#define HSI2_ACREADY		0x00aa
-#define HSI2_CAWAKE		0x00ac
-#define HSI2_ACWAKE		0x00ae
-#define HSI2_CAFLAG		0x00b0
-#define HSI2_CADATA		0x00b2
-#define HSI2_ACFLAG		0x00b4
-#define HSI2_ACDATA		0x00b6
-#define UART2_RTS		0x00b8
-#define UART2_CTS		0x00ba
-#define UART2_RX		0x00bc
-#define UART2_TX		0x00be
-#define USBB1_HSIC_STROBE	0x00c0
-#define USBB1_HSIC_DATA		0x00c2
-#define USBB2_HSIC_STROBE	0x00c4
-#define USBB2_HSIC_DATA		0x00c6
-#define TIMER10_PWM_EVT		0x00c8
-#define DSIPORTA_TE0		0x00ca
-#define DSIPORTA_LANE0X		0x00cc
-#define DSIPORTA_LANE0Y		0x00ce
-#define DSIPORTA_LANE1X		0x00d0
-#define DSIPORTA_LANE1Y		0x00d2
-#define DSIPORTA_LANE2X		0x00d4
-#define DSIPORTA_LANE2Y		0x00d6
-#define DSIPORTA_LANE3X		0x00d8
-#define DSIPORTA_LANE3Y		0x00da
-#define DSIPORTA_LANE4X		0x00dc
-#define DSIPORTA_LANE4Y		0x00de
-#define DSIPORTC_LANE0X		0x00e0
-#define DSIPORTC_LANE0Y		0x00e2
-#define DSIPORTC_LANE1X		0x00e4
-#define DSIPORTC_LANE1Y		0x00e6
-#define DSIPORTC_LANE2X		0x00e8
-#define DSIPORTC_LANE2Y		0x00ea
-#define DSIPORTC_LANE3X		0x00ec
-#define DSIPORTC_LANE3Y		0x00ee
-#define DSIPORTC_LANE4X		0x00f0
-#define DSIPORTC_LANE4Y		0x00f2
-#define DSIPORTC_TE0		0x00f4
-#define TIMER9_PWM_EVT		0x00f6
-#define I2C4_SCL		0x00f8
-#define I2C4_SDA		0x00fa
-#define MCSPI2_CLK		0x00fc
-#define MCSPI2_SIMO		0x00fe
-#define MCSPI2_SOMI		0x0100
-#define MCSPI2_CS0		0x0102
-#define RFBI_DATA15		0x0104
-#define RFBI_DATA14		0x0106
-#define RFBI_DATA13		0x0108
-#define RFBI_DATA12		0x010a
-#define RFBI_DATA11		0x010c
-#define RFBI_DATA10		0x010e
-#define RFBI_DATA9		0x0110
-#define RFBI_DATA8		0x0112
-#define RFBI_DATA7		0x0114
-#define RFBI_DATA6		0x0116
-#define RFBI_DATA5		0x0118
-#define RFBI_DATA4		0x011a
-#define RFBI_DATA3		0x011c
-#define RFBI_DATA2		0x011e
-#define RFBI_DATA1		0x0120
-#define RFBI_DATA0		0x0122
-#define RFBI_WE			0x0124
-#define RFBI_CS0		0x0126
-#define RFBI_A0			0x0128
-#define RFBI_RE			0x012a
-#define RFBI_HSYNC0		0x012c
-#define RFBI_TE_VSYNC0		0x012e
-#define GPIO6_182		0x0130
-#define GPIO6_183		0x0132
-#define GPIO6_184		0x0134
-#define GPIO6_185		0x0136
-#define GPIO6_186		0x0138
-#define GPIO6_187		0x013a
-#define HDMI_CEC		0x013c
-#define HDMI_HPD		0x013e
-#define HDMI_DDC_SCL		0x0140
-#define HDMI_DDC_SDA		0x0142
-#define CSIPORTC_LANE0X		0x0144
-#define CSIPORTC_LANE0Y		0x0146
-#define CSIPORTC_LANE1X		0x0148
-#define CSIPORTC_LANE1Y		0x014a
-#define CSIPORTB_LANE0X		0x014c
-#define CSIPORTB_LANE0Y		0x014e
-#define CSIPORTB_LANE1X		0x0150
-#define CSIPORTB_LANE1Y		0x0152
-#define CSIPORTB_LANE2X		0x0154
-#define CSIPORTB_LANE2Y		0x0156
-#define CSIPORTA_LANE0X		0x0158
-#define CSIPORTA_LANE0Y		0x015a
-#define CSIPORTA_LANE1X		0x015c
-#define CSIPORTA_LANE1Y		0x015e
-#define CSIPORTA_LANE2X		0x0160
-#define CSIPORTA_LANE2Y		0x0162
-#define CSIPORTA_LANE3X		0x0164
-#define CSIPORTA_LANE3Y		0x0166
-#define CSIPORTA_LANE4X		0x0168
-#define CSIPORTA_LANE4Y		0x016a
-#define CAM_SHUTTER		0x016c
-#define CAM_STROBE		0x016e
-#define CAM_GLOBALRESET		0x0170
-#define TIMER11_PWM_EVT		0x0172
-#define TIMER5_PWM_EVT		0x0174
-#define TIMER6_PWM_EVT		0x0176
-#define TIMER8_PWM_EVT		0x0178
-#define I2C3_SCL		0x017a
-#define I2C3_SDA		0x017c
-#define GPIO8_233		0x017e
-#define GPIO8_234		0x0180
-#define ABE_CLKS		0x0182
-#define ABEDMIC_DIN1		0x0184
-#define ABEDMIC_DIN2		0x0186
-#define ABEDMIC_DIN3		0x0188
-#define ABEDMIC_CLK1		0x018a
-#define ABEDMIC_CLK2		0x018c
-#define ABEDMIC_CLK3		0x018e
-#define ABESLIMBUS1_CLOCK	0x0190
-#define ABESLIMBUS1_DATA	0x0192
-#define ABEMCBSP2_DR		0x0194
-#define ABEMCBSP2_DX		0x0196
-#define ABEMCBSP2_FSX		0x0198
-#define ABEMCBSP2_CLKX		0x019a
-#define ABEMCPDM_UL_DATA	0x019c
-#define ABEMCPDM_DL_DATA	0x019e
-#define ABEMCPDM_FRAME		0x01a0
-#define ABEMCPDM_LB_CLK		0x01a2
-#define WLSDIO_CLK		0x01a4
-#define WLSDIO_CMD		0x01a6
-#define WLSDIO_DATA0		0x01a8
-#define WLSDIO_DATA1		0x01aa
-#define WLSDIO_DATA2		0x01ac
-#define WLSDIO_DATA3		0x01ae
-#define UART5_RX		0x01b0
-#define UART5_TX		0x01b2
-#define UART5_CTS		0x01b4
-#define UART5_RTS		0x01b6
-#define I2C2_SCL		0x01b8
-#define I2C2_SDA		0x01ba
-#define MCSPI1_CLK		0x01bc
-#define MCSPI1_SOMI		0x01be
-#define MCSPI1_SIMO		0x01c0
-#define MCSPI1_CS0		0x01c2
-#define MCSPI1_CS1		0x01c4
-#define I2C5_SCL		0x01c6
-#define I2C5_SDA		0x01c8
-#define PERSLIMBUS2_CLOCK	0x01ca
-#define PERSLIMBUS2_DATA	0x01cc
-#define UART6_TX		0x01ce
-#define UART6_RX		0x01d0
-#define UART6_CTS		0x01d2
-#define UART6_RTS		0x01d4
-#define UART3_CTS_RCTX		0x01d6
-#define UART3_RTS_IRSD		0x01d8
-#define UART3_TX_IRTX		0x01da
-#define UART3_RX_IRRX		0x01dc
-#define USBB3_HSIC_STROBE	0x01de
-#define USBB3_HSIC_DATA		0x01e0
-#define SDCARD_CLK		0x01e2
-#define SDCARD_CMD		0x01e4
-#define SDCARD_DATA2		0x01e6
-#define SDCARD_DATA3		0x01e8
-#define SDCARD_DATA0		0x01ea
-#define SDCARD_DATA1		0x01ec
-#define USBD0_HS_DP		0x01ee
-#define USBD0_HS_DM		0x01f0
-#define I2C1_PMIC_SCL		0x01f2
-#define I2C1_PMIC_SDA		0x01f4
-#define USBD0_SS_RX		0x01f6
-
-#define LLIA_WAKEREQIN		0x0040
-#define LLIB_WAKEREQIN		0x0042
-#define DRM_EMU0		0x0044
-#define DRM_EMU1		0x0046
-#define JTAG_NTRST		0x0048
-#define JTAG_TCK		0x004a
-#define JTAG_RTCK		0x004c
-#define JTAG_TMSC		0x004e
-#define JTAG_TDI		0x0050
-#define JTAG_TDO		0x0052
-#define SYS_32K			0x0054
-#define FREF_CLK_IOREQ		0x0056
-#define FREF_CLK0_OUT		0x0058
-#define FREF_CLK1_OUT		0x005a
-#define FREF_CLK2_OUT		0x005c
-#define FREF_CLK2_REQ		0x005e
-#define FREF_CLK1_REQ		0x0060
-#define SYS_NRESPWRON		0x0062
-#define SYS_NRESWARM		0x0064
-#define SYS_PWR_REQ		0x0066
-#define SYS_NIRQ1		0x0068
-#define SYS_NIRQ2		0x006a
-#define SR_PMIC_SCL		0x006c
-#define SR_PMIC_SDA		0x006e
-#define SYS_BOOT0		0x0070
-#define SYS_BOOT1		0x0072
-#define SYS_BOOT2		0x0074
-#define SYS_BOOT3		0x0076
-#define SYS_BOOT4		0x0078
-#define SYS_BOOT5		0x007a
-
-#endif /* _MUX_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
index 86c906bb0e..84b63e4d56 100644
--- a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
+++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
@@ -189,6 +189,21 @@ enum {
 	DCLK_VOP_DIV_SHIFT	= 0,
 	DCLK_VOP_DIV_MASK	= 0xff,
 
+	/* CRU_CLKSEL_CON10 */
+	/* CRU_CLKSEL_CON13 */
+	/* CRU_CLKSEL_CON16 */
+	/* CRU_CLKSEL_CON19 */
+	/* CRU_CLKSEL_CON22 */
+	CLK_UART_PLL_SEL_SHIFT		= 13,
+	CLK_UART_PLL_SEL_MASK		= 0x7 << CLK_UART_PLL_SEL_SHIFT,
+	CLK_UART_PLL_SEL_DPLL		= 0,
+	CLK_UART_PLL_SEL_VPLL0,
+	CLK_UART_PLL_SEL_VPLL1,
+	CLK_UART_PLL_SEL_480M,
+	CLK_UART_PLL_SEL_24M,
+	CLK_UART_DIV_CON_SHIFT		= 0,
+	CLK_UART_DIV_CON_MASK		= 0x1f << CLK_UART_DIV_CON_SHIFT,
+
 	/* CRU_CLK_SEL25_CON */
 	/* CRU_CLK_SEL26_CON */
 	/* CRU_CLK_SEL27_CON */
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
index 13ea4aba8e..9778790f34 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -15,6 +15,8 @@
 # include <asm/arch-rockchip/cru_rk3288.h>
 #elif defined(CONFIG_ROCKCHIP_RK3399)
 # include <asm/arch-rockchip/cru_rk3399.h>
+#elif defined(CONFIG_ROCKCHIP_RK3568)
+#include <asm/arch-rockchip/cru_rk3568.h>
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
index 399f19ad21..9c7ddd751f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -106,6 +106,8 @@ struct rk3568_cru {
 	unsigned int emmc_con[2];/* Address Offset: 0x0598 */
 };
 
+#define rockchip_cru rk3568_cru
+
 check_member(rk3568_cru, mode_con00, 0xc0);
 check_member(rk3568_cru, softrst_con[0], 0x400);
 
@@ -493,7 +495,7 @@ enum {
 
 	/* CRU_CLK_SEL81_CON */
 	CPLL_25M_DIV_SHIFT		= 8,
-	CPLL_25M_DIV_MASK		= 0x1f << CPLL_25M_DIV_SHIFT,
+	CPLL_25M_DIV_MASK		= 0x3f << CPLL_25M_DIV_SHIFT,
 	CPLL_50M_DIV_SHIFT		= 0,
 	CPLL_50M_DIV_MASK		= 0x1f << CPLL_50M_DIV_SHIFT,
 
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 6db869c098..11774deded 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -148,10 +148,6 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
 struct dram_para {
 	u32 clk;
 	enum sunxi_dram_type type;
-	u8 cols;
-	u8 rows;
-	u8 ranks;
-	u8 bus_full_width;
 	u32 dx_odt;
 	u32 dx_dri;
 	u32 ca_dri;
@@ -163,6 +159,12 @@ struct dram_para {
 	u32 tpr12;
 };
 
+struct dram_config {
+	u8 cols;
+	u8 rows;
+	u8 ranks;
+	u8 bus_full_width;
+};
 
 static inline int ns_to_t(int nanoseconds)
 {
@@ -171,6 +173,6 @@ static inline int ns_to_t(int nanoseconds)
 	return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
 }
 
-void mctl_set_timing_params(struct dram_para *para);
+void mctl_set_timing_params(const struct dram_para *para);
 
 #endif /* _SUNXI_DRAM_SUN50I_H616_H */
diff --git a/arch/arm/include/asm/arm11.h b/arch/arm/include/asm/arm11.h
new file mode 100644
index 0000000000..5276f735ef
--- /dev/null
+++ b/arch/arm/include/asm/arm11.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Marek Vasut <marex@denx.de>
+ */
+#ifndef ARM11_H
+#define ARM11_H
+
+#ifndef __ASSEMBLY__
+void arm11_arch_cp15_allow_unaligned(void);
+#endif /* ! __ASSEMBLY__ */
+
+#endif	/* ARM11_H */
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 2fb824b69e..c002998ac0 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -156,6 +156,7 @@ void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 				 u32 cpu_rev);
 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
 			  u32 cpu_variant, u32 cpu_rev);
+void v7_arch_cp15_allow_unaligned(void);
 #endif /* ! __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/include/asm/boot0-linux-kernel-header.h b/arch/arm/include/asm/boot0-linux-kernel-header.h
index c6cd76f32a..c930fea5fd 100644
--- a/arch/arm/include/asm/boot0-linux-kernel-header.h
+++ b/arch/arm/include/asm/boot0-linux-kernel-header.h
@@ -31,8 +31,6 @@
 	.long	\sym\()_hi32
 	.endm
 
-.globl _start
-_start:
 	/*
 	 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
 	 */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 0c13075711..2a222c5388 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -92,8 +92,8 @@ struct arch_global_data {
 	struct udevice *scu_dev;
 #endif
 
-#ifdef CONFIG_IMX_SENTINEL
-	struct udevice *s400_dev;
+#ifdef CONFIG_IMX_ELE
+	struct udevice *ele_dev;
 	u32 soc_rev;
 	u32 lifecycle;
 	u32 uid[4];
diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h
deleted file mode 100644
index ce831bc13a..0000000000
--- a/arch/arm/include/asm/iproc-common/configs.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Broadcom Corporation.
- */
-
-#ifndef __IPROC_COMMON_CONFIGS_H
-#define __IPROC_COMMON_CONFIGS_H
-
-#include <linux/stringify.h>
-
-/* Memory Info */
-#define CFG_SYS_SDRAM_BASE		0x61000000
-
-#endif /* __IPROC_COMMON_CONFIGS_H */
diff --git a/arch/arm/include/asm/iproc-common/iproc_sdhci.h b/arch/arm/include/asm/iproc-common/iproc_sdhci.h
deleted file mode 100644
index 4e299217fc..0000000000
--- a/arch/arm/include/asm/iproc-common/iproc_sdhci.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: <SPDX License Expression> */
-/*
- * Copyright 2019 Broadcom
- *
- */
-
-#ifndef __IPROC_SDHCI_H
-#define __IPROC_SDHCI_H
-
-int iproc_sdhci_init(int dev_index, u32 quirks);
-
-#endif
diff --git a/arch/arm/include/asm/kona-common/kona_sdhci.h b/arch/arm/include/asm/kona-common/kona_sdhci.h
deleted file mode 100644
index 22db651a4e..0000000000
--- a/arch/arm/include/asm/kona-common/kona_sdhci.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Broadcom Corporation.
- */
-
-#ifndef __KONA_SDHCI_H
-#define __KONA_SDHCI_H
-
-int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks);
-
-#endif
diff --git a/arch/arm/include/asm/linkage.h b/arch/arm/include/asm/linkage.h
index dbe4b4e31a..73bf25ba4e 100644
--- a/arch/arm/include/asm/linkage.h
+++ b/arch/arm/include/asm/linkage.h
@@ -1,7 +1,7 @@
 #ifndef __ASM_LINKAGE_H
 #define __ASM_LINKAGE_H
 
-#define __ALIGN .align 0
-#define __ALIGN_STR ".align 0"
+#define __ALIGN .p2align 2
+#define __ALIGN_STR ".p2align 2"
 
 #endif
diff --git a/arch/arm/include/asm/mach-imx/ahab.h b/arch/arm/include/asm/mach-imx/ahab.h
new file mode 100644
index 0000000000..4222e3db27
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/ahab.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __IMX_AHAB_H__
+#define __IMX_AHAB_H__
+
+#include <asm/mach-imx/image.h>
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length);
+int ahab_auth_release(void);
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index);
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/ele_api.h
index 5582ff1a25..cfd4ecebb6 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/ele_api.h
@@ -3,12 +3,12 @@
  * Copyright 2021 NXP
  */
 
-#ifndef __S400_API_H__
-#define __S400_API_H__
+#ifndef __ELE_API_H__
+#define __ELE_API_H__
 
-#define AHAB_VERSION    0x6
-#define AHAB_CMD_TAG    0x17
-#define AHAB_RESP_TAG   0xe1
+#define ELE_VERSION    0x6
+#define ELE_CMD_TAG    0x17
+#define ELE_RESP_TAG   0xe1
 
 /* ELE commands */
 #define ELE_PING_REQ (0x01)
@@ -24,6 +24,8 @@
 #define ELE_GET_FW_VERSION_REQ (0x9D)
 #define ELE_RET_LIFECYCLE_UP_REQ (0xA0)
 #define ELE_GET_EVENTS_REQ (0xA2)
+#define ELE_START_RNG (0xA3)
+#define ELE_GENERATE_DEK_BLOB (0xAF)
 #define ELE_ENABLE_PATCH_REQ (0xC3)
 #define ELE_RELEASE_RDC_REQ (0xC4)
 #define ELE_GET_FW_STATUS_REQ (0xC5)
@@ -109,17 +111,17 @@
 #define ELE_SUCCESS_IND (0xD6)
 #define ELE_FAILURE_IND (0x29)
 
-#define S400_MAX_MSG          255U
+#define ELE_MAX_MSG          255U
 
-struct sentinel_msg {
+struct ele_msg {
 	u8 version;
 	u8 size;
 	u8 command;
 	u8 tag;
-	u32 data[(S400_MAX_MSG - 1U)];
+	u32 data[(ELE_MAX_MSG - 1U)];
 };
 
-struct sentinel_get_info_data {
+struct ele_get_info_data {
 	u32 hdr;
 	u32 soc;
 	u32 lc;
@@ -130,19 +132,22 @@ struct sentinel_get_info_data {
 	u32 state;
 };
 
-int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
-int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
-int ahab_release_container(u32 *response);
-int ahab_verify_image(u32 img_id, u32 *response);
-int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
-int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
-int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
-int ahab_release_caam(u32 core_did, u32 *response);
-int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
-int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
-int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
-int ahab_get_fw_status(u32 *status, u32 *response);
-int ahab_release_m33_trout(void);
-int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response);
-
+int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response);
+int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
+int ele_release_container(u32 *response);
+int ele_verify_image(u32 img_id, u32 *response);
+int ele_forward_lifecycle(u16 life_cycle, u32 *response);
+int ele_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
+int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
+int ele_release_caam(u32 core_did, u32 *response);
+int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
+int ele_get_events(u32 *events, u32 *events_cnt, u32 *response);
+int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_output_size);
+int ele_dump_buffer(u32 *buffer, u32 buffer_length);
+int ele_get_info(struct ele_get_info_data *info, u32 *response);
+int ele_get_fw_status(u32 *status, u32 *response);
+int ele_release_m33_trout(void);
+int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response);
+int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response);
+int ele_start_rng(void);
 #endif
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 85d9ca60b1..31ae179b21 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -236,6 +236,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start,
 			  u64 *phys_sdram_2_start,
 			  u64 *phys_sdram_2_size);
 
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data);
 int arch_auxiliary_core_check_up(u32 core_id);
 
 int board_mmc_get_env_dev(int devno);
diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h
index 0a228fb8ee..7fb482abc3 100644
--- a/arch/arm/include/asm/unaligned.h
+++ b/arch/arm/include/asm/unaligned.h
@@ -1,19 +1,2 @@
-#ifndef _ASM_ARM_UNALIGNED_H
-#define _ASM_ARM_UNALIGNED_H
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-/*
- * Select endianness
- */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-#define get_unaligned	__get_unaligned_le
-#define put_unaligned	__put_unaligned_le
-#else
-#define get_unaligned	__get_unaligned_be
-#define put_unaligned	__put_unaligned_be
-#endif
-
-#endif /* _ASM_ARM_UNALIGNED_H */
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <asm-generic/unaligned.h>
diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
index 6de0ce9152..181a8ac4c2 100644
--- a/arch/arm/lib/asm-offsets.c
+++ b/arch/arm/lib/asm-offsets.c
@@ -9,6 +9,11 @@
  * generate asm statements containing #defines,
  * compile this file to assembler, and then extract the
  * #defines from the assembly-language output.
+ *
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
  */
 
 #include <common.h>
@@ -90,6 +95,17 @@ int main(void)
 	DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
 	DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
 	DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
+#ifdef CONFIG_ARM64
+	DEFINE(ARM_SMCCC_1_2_REGS_X0_OFFS,	offsetof(struct arm_smccc_1_2_regs, a0));
+	DEFINE(ARM_SMCCC_1_2_REGS_X2_OFFS,	offsetof(struct arm_smccc_1_2_regs, a2));
+	DEFINE(ARM_SMCCC_1_2_REGS_X4_OFFS,	offsetof(struct arm_smccc_1_2_regs, a4));
+	DEFINE(ARM_SMCCC_1_2_REGS_X6_OFFS,	offsetof(struct arm_smccc_1_2_regs, a6));
+	DEFINE(ARM_SMCCC_1_2_REGS_X8_OFFS,	offsetof(struct arm_smccc_1_2_regs, a8));
+	DEFINE(ARM_SMCCC_1_2_REGS_X10_OFFS,	offsetof(struct arm_smccc_1_2_regs, a10));
+	DEFINE(ARM_SMCCC_1_2_REGS_X12_OFFS,	offsetof(struct arm_smccc_1_2_regs, a12));
+	DEFINE(ARM_SMCCC_1_2_REGS_X14_OFFS,	offsetof(struct arm_smccc_1_2_regs, a14));
+	DEFINE(ARM_SMCCC_1_2_REGS_X16_OFFS,	offsetof(struct arm_smccc_1_2_regs, a16));
+#endif
 #endif
 
 	return 0;
diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h
deleted file mode 100644
index ba88c441e3..0000000000
--- a/arch/arm/mach-at91/include/mach/at91_rtt.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Real-time Timer
- * Based on AT91SAM9XE datasheet
- */
-
-#ifndef AT91_RTT_H
-#define AT91_RTT_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_rtt {
-	u32	mr;	/* Mode Register   RW 0x00008000 */
-	u32	ar;	/* Alarm Register  RW 0xFFFFFFFF */
-	u32	vr;	/* Value Register  RO 0x00000000 */
-	u32	sr;	/* Status Register RO 0x00000000 */
-} at91_rtt_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_RTT_MR_RTPRES	0x0000ffff
-#define AT91_RTT_MR_ALMIEN	0x00010000
-#define AT91_RTT_RTTINCIEN	0x00020000
-#define AT91_RTT_RTTRST	0x00040000
-
-#define AT91_RTT_SR_ALMS	0x00000001
-#define AT91_RTT_SR_RTTINC	0x00000002
-
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/aintc_defs.h b/arch/arm/mach-davinci/include/mach/aintc_defs.h
deleted file mode 100644
index 7419a58bd1..0000000000
--- a/arch/arm/mach-davinci/include/mach/aintc_defs.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-#ifndef _DV_AINTC_DEFS_H_
-#define _DV_AINTC_DEFS_H_
-
-struct dv_aintc_regs {
-	unsigned int	fiq0;		/* 0x00 */
-	unsigned int	fiq1;		/* 0x04 */
-	unsigned int	irq0;		/* 0x08 */
-	unsigned int	irq1;		/* 0x0c */
-	unsigned int	fiqentry;	/* 0x10 */
-	unsigned int	irqentry;	/* 0x14 */
-	unsigned int	eint0;		/* 0x18 */
-	unsigned int	eint1;		/* 0x1c */
-	unsigned int	intctl;		/* 0x20 */
-	unsigned int	eabase;		/* 0x24 */
-	unsigned char	rsvd0[8];	/* 0x28 */
-	unsigned int	intpri0;	/* 0x30 */
-	unsigned int	intpri1;	/* 0x34 */
-	unsigned int	intpri2;	/* 0x38 */
-	unsigned int	intpri3;	/* 0x3c */
-	unsigned int	intpri4;	/* 0x40 */
-	unsigned int	intpri5;	/* 0x44 */
-	unsigned int	intpri6;	/* 0x48 */
-	unsigned int	intpri7;	/* 0x4c */
-};
-
-#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
-
-#define DV_AINTC_INTCTL_IDMODE	(1 << 2)
-
-#endif /* _DV_AINTC_DEFS_H_ */
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3266545c26..d94b5828d0 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -31,7 +31,7 @@ config IMX_RDC
 
 config IMX_BOOTAUX
 	bool "Support boot auxiliary core"
-	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8M
+	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8 || ARCH_IMX8M
 	help
 	  bootaux [addr] to boot auxiliary core.
 
@@ -86,6 +86,7 @@ config CMD_DEKBLOB
 	select IMX_CAAM_DEK_ENCAP if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP
 	select IMX_OPTEE_DEK_ENCAP if ARCH_IMX8M
 	select IMX_SECO_DEK_ENCAP if ARCH_IMX8
+	select IMX_ELE_DEK_ENCAP if ARCH_IMX8ULP || ARCH_IMX9
 	help
 	  This enables the 'dek_blob' command which is used with the
 	  Freescale secure boot mechanism. This command encapsulates and
@@ -113,6 +114,12 @@ config IMX_SECO_DEK_ENCAP
 	  This enabled the DEK blob encapsulation with the SECO API. This option
 	  is only available on imx8.
 
+config IMX_ELE_DEK_ENCAP
+	bool "Support the DEK blob encapsulation with ELE"
+	help
+	  This enabled the DEK blob encapsulation with the ELE API. This option
+	  is only available on imx8ulp and imx9.
+
 config CMD_PRIBLOB
 	bool "Support the set_priblob_bitfield command"
 	depends on HAS_CAAM && IMX_HAB
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 906f538259..aebfa6517b 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -54,7 +54,7 @@ obj-$(CONFIG_IMX_RDC) += rdc-sema.o
 ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 endif
-obj-$(CONFIG_SATA) += sata.o
+obj-$(CONFIG_$(SPL_)SATA) += sata.o
 obj-$(CONFIG_IMX_HAB)    += hab.o
 obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
@@ -66,6 +66,11 @@ ifeq ($(SOC),$(filter $(SOC),vf610))
 obj-y += ddrmc-vf610.o
 obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o
 endif
+ifeq ($(SOC),$(filter $(SOC),imx8))
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+endif
+endif
 ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
 obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 69ed57537b..6fa5b41fcd 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2008-2015 Freescale Semiconductor, Inc.
+ * Copyright 2022 NXP
  *
  * Command for encapsulating DEK blob
  */
@@ -20,6 +21,11 @@
 #include <firmware/imx/sci/sci.h>
 #include <asm/mach-imx/image.h>
 #endif
+#ifdef CONFIG_IMX_ELE_DEK_ENCAP
+#include <asm/mach-imx/ele_api.h>
+#include <asm/mach-imx/image.h>
+#endif
+
 #include <cpu_func.h>
 
 /**
@@ -101,6 +107,7 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
 			       0x0, &shm_output);
 	if (ret < 0) {
 		printf("Cannot register output shared memory 0x%X\n", ret);
+		tee_shm_free(shm_input);
 		goto error;
 	}
 
@@ -122,11 +129,11 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
 	if (ret < 0)
 		printf("Cannot generate Blob with PTA DEK Blob 0x%X\n", ret);
 
-error:
 	/* Free shared memory */
 	tee_shm_free(shm_input);
 	tee_shm_free(shm_output);
 
+error:
 	/* Close session */
 	ret = tee_close_session(dev, arg.session);
 	if (ret < 0)
@@ -154,7 +161,7 @@ error:
 
 static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
 {
-	sc_err_t err;
+	int err;
 	sc_rm_mr_t mr_input, mr_output;
 	struct generate_key_blob_hdr hdr;
 	u8 in_size, out_size;
@@ -283,6 +290,84 @@ error:
 }
 #endif /* CONFIG_IMX_SECO_DEK_ENCAP */
 
+#ifdef CONFIG_IMX_ELE_DEK_ENCAP
+
+#define DEK_BLOB_HDR_SIZE 8
+#define AHAB_PRIVATE_KEY 0x81
+#define AHAB_DEK_BLOB	 0x01
+#define AHAB_ALG_AES	 0x03
+#define AHAB_128_AES_KEY 0x10
+#define AHAB_192_AES_KEY 0x18
+#define AHAB_256_AES_KEY 0x20
+
+static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
+{
+	u8 in_size, out_size;
+	u8 *src_ptr, *dst_ptr;
+	struct generate_key_blob_hdr hdr;
+
+	/* Set sizes */
+	in_size = sizeof(struct generate_key_blob_hdr) + len / 8;
+	out_size = BLOB_SIZE(len / 8) + DEK_BLOB_HDR_SIZE;
+
+	/* Get src and dst virtual addresses */
+	src_ptr = map_sysmem(src_addr, in_size);
+	dst_ptr = map_sysmem(dst_addr, out_size);
+
+	/* Check addr input */
+	if (!(src_ptr && dst_ptr)) {
+		debug("src_addr or dst_addr invalid\n");
+		return -1;
+	}
+
+	/* Build key header */
+	hdr.version = 0x0;
+	hdr.length_lsb = in_size;
+	hdr.length_msb = 0x00;
+	hdr.tag = AHAB_PRIVATE_KEY;
+	hdr.flags = AHAB_DEK_BLOB;
+	hdr.algorithm = AHAB_ALG_AES;
+	hdr.mode = 0x0; /* Not used by the ELE */
+
+	switch (len) {
+	case 128:
+		hdr.size = AHAB_128_AES_KEY;
+		break;
+	case 192:
+		hdr.size = AHAB_192_AES_KEY;
+		break;
+	case 256:
+		hdr.size = AHAB_256_AES_KEY;
+		break;
+	default:
+		/* Not supported */
+		debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
+		return -1;
+	}
+
+	/* Move input key and append blob header */
+	memmove((void *)(src_ptr + sizeof(struct generate_key_blob_hdr)),
+		(void *)src_ptr, len / 8);
+	memcpy((void *)src_ptr, (void *)&hdr,
+	       sizeof(struct generate_key_blob_hdr));
+
+	/* Flush the cache */
+	flush_dcache_range(src_addr, src_addr + in_size);
+	flush_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr +
+			roundup(out_size, ARCH_DMA_MINALIGN)));
+
+	/* Call ELE */
+	if (ele_generate_dek_blob(0x00, src_addr, dst_addr, out_size))
+		return -1;
+
+	/* Invalidate output buffer */
+	invalidate_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr +
+			roundup(out_size, ARCH_DMA_MINALIGN)));
+
+	return 0;
+}
+#endif /* CONFIG_IMX_ELE_DEK_ENCAP */
+
 /**
  * do_dek_blob() - Handle the "dek_blob" command-line command
  * @cmdtp:  Command data struct pointer
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 702cfc3327..488638c905 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -510,3 +510,7 @@ char nxp_board_rev_string(void)
 	return (*rev + nxp_board_rev() - 1);
 }
 #endif
+
+__weak void reset_cpu(void)
+{
+}
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index 99fc540271..785b0d6ec3 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -7,14 +7,13 @@
 #include <command.h>
 #include <errno.h>
 #include <asm/io.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
 #include <asm/mach-imx/sys_proto.h>
 #include <asm/arch-imx/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/image.h>
 #include <console.h>
 #include <cpu_func.h>
-#include <asm/mach-imx/ahab.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -267,7 +266,7 @@ int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
 	flush_dcache_range(IMG_CONTAINER_BASE,
 			   IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1);
 
-	err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp);
+	err = ele_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp);
 	if (err) {
 		printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
 		       err, resp);
@@ -282,7 +281,7 @@ int ahab_auth_release(void)
 	int err;
 	u32 resp;
 
-	err = ahab_release_container(&resp);
+	err = ele_release_container(&resp);
 	if (err) {
 		printf("Error: release container failed, resp 0x%x!\n", resp);
 		display_ahab_auth_ind(resp);
@@ -296,7 +295,7 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
 	int err;
 	u32 resp;
 
-	err = ahab_verify_image(image_index, &resp);
+	err = ele_verify_image(image_index, &resp);
 	if (err) {
 		printf("Authenticate img %d failed, return %d, resp 0x%x\n",
 		       image_index, err, resp);
@@ -403,7 +402,7 @@ static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
-	addr = simple_strtoul(argv[1], NULL, 16);
+	addr = hextoul(argv[1], NULL);
 
 	printf("Authenticate OS container at 0x%lx\n", addr);
 
@@ -485,7 +484,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
 		return -EPERM;
 	}
 
-	err = ahab_forward_lifecycle(8, &resp);
+	err = ele_forward_lifecycle(8, &resp);
 	if (err != 0) {
 		printf("Error in forward lifecycle to OEM closed\n");
 		return -EIO;
@@ -502,7 +501,7 @@ int ahab_dump(void)
 	int ret, i = 0;
 
 	do {
-		ret = ahab_dump_buffer(buffer, 32);
+		ret = ele_dump_buffer(buffer, 32);
 		if (ret < 0) {
 			printf("Error in dump AHAB log\n");
 			return -EIO;
@@ -547,7 +546,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const
 
 	display_life_cycle(lc);
 
-	ret = ahab_get_events(events, &cnt, NULL);
+	ret = ele_get_events(events, &cnt, NULL);
 	if (ret) {
 		printf("Get ELE EVENTS error %d\n", ret);
 		return CMD_RET_FAILURE;
@@ -564,6 +563,68 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const
 	return 0;
 }
 
+static int do_sec_fuse_prog(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	ulong addr;
+	u32 header, response;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	addr = hextoul(argv[1], NULL);
+	header = *(u32 *)addr;
+
+	if ((header & 0xff0000ff) != 0x89000000) {
+		printf("Wrong Signed message block format, header 0x%x\n", header);
+		return CMD_RET_FAILURE;
+	}
+
+	header = (header & 0xffff00) >> 8;
+
+	printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header);
+	flush_dcache_range(addr, addr + header - 1);
+
+	if (ele_write_secure_fuse(addr, &response)) {
+		printf("Program secure fuse failed, response 0x%x\n", response);
+		return CMD_RET_FAILURE;
+	}
+
+	printf("Program secure fuse completed, response 0x%x\n", response);
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_ahab_return_lifecycle(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	ulong addr;
+	u32 header, response;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	addr = hextoul(argv[1], NULL);
+	header = *(u32 *)addr;
+
+	if ((header & 0xff0000ff) != 0x89000000) {
+		printf("Wrong Signed message block format, header 0x%x\n", header);
+		return CMD_RET_FAILURE;
+	}
+
+	header = (header & 0xffff00) >> 8;
+
+	printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header);
+	flush_dcache_range(addr, addr + header - 1);
+
+	if (ele_return_lifecycle_update(addr, &response)) {
+		printf("Return lifecycle failed, response 0x%x\n", response);
+		return CMD_RET_FAILURE;
+	}
+
+	printf("Return lifecycle completed, response 0x%x\n", response);
+
+	return CMD_RET_SUCCESS;
+}
+
 U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
 	   "autenticate OS container via AHAB",
 	   "addr\n"
@@ -584,3 +645,15 @@ U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status,
 	   "display AHAB lifecycle only",
 	   ""
 );
+
+U_BOOT_CMD(ahab_sec_fuse_prog, CONFIG_SYS_MAXARGS, 1, do_sec_fuse_prog,
+	   "Program secure fuse via signed message block",
+	   "addr\n"
+	   "addr - Signed message block for secure fuse\n"
+);
+
+U_BOOT_CMD(ahab_return_lifecycle, CONFIG_SYS_MAXARGS, 1, do_ahab_return_lifecycle,
+	   "Return lifecycle to OEM field return via signed message block",
+	   "addr\n"
+	   "addr - Return lifecycle message block signed by OEM SRK\n"
+);
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index c6747b257c..b3ef36c797 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -289,9 +289,10 @@ static char *rsn_str[] = {
 };
 
 static char *sts_str[] = {
-			  "STS = HAB_SUCCESS (0xF0)\n",
+			  "STS = HAB_STS_ANY (0x00)\n",
 			  "STS = HAB_FAILURE (0x33)\n",
 			  "STS = HAB_WARNING (0x69)\n",
+			  "STS = HAB_SUCCESS (0xF0)\n",
 			  "STS = INVALID\n",
 			  NULL
 };
@@ -336,8 +337,7 @@ static uint8_t hab_statuses[5] = {
 	HAB_STS_ANY,
 	HAB_FAILURE,
 	HAB_WARNING,
-	HAB_SUCCESS,
-	-1
+	HAB_SUCCESS
 };
 
 static uint8_t hab_reasons[26] = {
@@ -365,8 +365,7 @@ static uint8_t hab_reasons[26] = {
 	HAB_UNS_ITEM,
 	HAB_UNS_KEY,
 	HAB_UNS_PROTOCOL,
-	HAB_UNS_STATE,
-	-1
+	HAB_UNS_STATE
 };
 
 static uint8_t hab_contexts[12] = {
@@ -380,8 +379,7 @@ static uint8_t hab_contexts[12] = {
 	HAB_CTX_COMMAND,
 	HAB_CTX_AUT_DAT,
 	HAB_CTX_ASSERT,
-	HAB_CTX_EXIT,
-	-1
+	HAB_CTX_EXIT
 };
 
 static uint8_t hab_engines[16] = {
@@ -399,30 +397,35 @@ static uint8_t hab_engines[16] = {
 	HAB_ENG_ROM,
 	HAB_ENG_HDCP,
 	HAB_ENG_RTL,
-	HAB_ENG_SW,
-	-1
+	HAB_ENG_SW
 };
 
-static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
+static inline u32 get_idx(u8 *list, u8 tgt, u32 size)
 {
-	uint8_t idx = 0;
-	uint8_t element = list[idx];
-	while (element != -1) {
+	u32 idx = 0;
+	u8 element;
+
+	while (idx < size) {
+		element = list[idx];
 		if (element == tgt)
 			return idx;
-		element = list[++idx];
+		++idx;
 	}
-	return -1;
+	return idx;
 }
 
 static void process_event_record(uint8_t *event_data, size_t bytes)
 {
 	struct record *rec = (struct record *)event_data;
 
-	printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
-	printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
-	printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
-	printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
+	printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0],
+	       ARRAY_SIZE(hab_statuses))]);
+	printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1],
+	       ARRAY_SIZE(hab_reasons))]);
+	printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2],
+	       ARRAY_SIZE(hab_contexts))]);
+	printf("%s", eng_str[get_idx(hab_engines, rec->contents[3],
+	       ARRAY_SIZE(hab_engines))]);
 }
 
 static void display_event(uint8_t *event_data, size_t bytes)
@@ -932,10 +935,10 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
 	printf("ivt entry = 0x%08x, dcd = 0x%08x, csf = 0x%08x\n", ivt->entry,
 	       ivt->dcd, ivt->csf);
 	puts("Dumping IVT\n");
-	print_buffer(ivt_addr, (void *)(ivt_addr), 4, 0x8, 0);
+	print_buffer(ivt_addr, (void *)(uintptr_t)(ivt_addr), 4, 0x8, 0);
 
 	puts("Dumping CSF Header\n");
-	print_buffer(ivt->csf, (void *)(ivt->csf), 4, 0x10, 0);
+	print_buffer(ivt->csf, (void *)(uintptr_t)(ivt->csf), 4, 0x10, 0);
 
 #if  !defined(CONFIG_SPL_BUILD)
 	get_hab_status();
@@ -944,7 +947,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
 	puts("\nCalling authenticate_image in ROM\n");
 	printf("\tivt_offset = 0x%x\n", ivt_offset);
 	printf("\tstart = 0x%08lx\n", start);
-	printf("\tbytes = 0x%x\n", bytes);
+	printf("\tbytes = 0x%lx\n", (ulong)bytes);
 #endif
 
 #ifndef CONFIG_ARM64
diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index 5b059a6429..5f188ab32d 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -22,6 +22,25 @@
 #define QSPI_NOR_DEV	3
 #define ROM_API_DEV	4
 
+/* The unit of second image offset number which provision by the fuse bits */
+#define SND_IMG_OFF_UNIT    (0x100000UL)
+
+/*
+ * If num = 0, off = (2 ^ 2) * 1MB
+ * else If num = 2, off = (2 ^ 0) * 1MB
+ * else off = (2 ^ num) * 1MB
+ */
+#define SND_IMG_NUM_TO_OFF(num) \
+	((1UL << ((0 == (num)) ? 2 : (2 == (num)) ? 0 : (num))) * SND_IMG_OFF_UNIT)
+
+#define GET_SND_IMG_NUM(fuse) (((fuse) >> 24) & 0x1F)
+
+#if defined(CONFIG_IMX8QM)
+#define FUSE_IMG_SET_OFF_WORD 464
+#elif defined(CONFIG_IMX8QXP)
+#define FUSE_IMG_SET_OFF_WORD 720
+#endif
+
 int get_container_size(ulong addr, u16 *header_length)
 {
 	struct container_hdr *phdr;
@@ -31,7 +50,7 @@ int get_container_size(ulong addr, u16 *header_length)
 	u32 max_offset = 0, img_end;
 
 	phdr = (struct container_hdr *)addr;
-	if (phdr->tag != 0x87 && phdr->version != 0x0) {
+	if (phdr->tag != 0x87 || phdr->version != 0x0) {
 		debug("Wrong container header\n");
 		return -EFAULT;
 	}
@@ -136,15 +155,53 @@ static int get_dev_container_size(void *dev, int dev_type, unsigned long offset,
 	return ret;
 }
 
+static bool check_secondary_cnt_set(unsigned long *set_off)
+{
+#if IS_ENABLED(CONFIG_ARCH_IMX8)
+	int ret;
+	u8 set_id = 1;
+	u32 fuse_val = 0;
+
+	if (!(is_imx8qxp() && is_soc_rev(CHIP_REV_B))) {
+		ret = sc_misc_get_boot_container(-1, &set_id);
+		if (ret)
+			return false;
+		/* Secondary boot */
+		if (set_id == 2) {
+			ret = sc_misc_otp_fuse_read(-1, FUSE_IMG_SET_OFF_WORD, &fuse_val);
+			if (!ret) {
+				if (set_off)
+					*set_off = SND_IMG_NUM_TO_OFF(GET_SND_IMG_NUM(fuse_val));
+				return true;
+			}
+		}
+	}
+#endif
+
+	return false;
+}
+
 static unsigned long get_boot_device_offset(void *dev, int dev_type)
 {
-	unsigned long offset = 0;
+	unsigned long offset = 0, sec_set_off = 0;
+	bool sec_boot = false;
+
+	if (dev_type == ROM_API_DEV) {
+		offset = (unsigned long)dev;
+		return offset;
+	}
+
+	sec_boot = check_secondary_cnt_set(&sec_set_off);
+	if (sec_boot)
+		printf("Secondary set selected\n");
+	else
+		printf("Primary set selected\n");
 
 	if (dev_type == MMC_DEV) {
 		struct mmc *mmc = (struct mmc *)dev;
 
 		if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) {
-			offset = CONTAINER_HDR_MMCSD_OFFSET;
+			offset = sec_boot ? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET;
 		} else {
 			u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
 
@@ -154,19 +211,23 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type)
 				else
 					offset = CONTAINER_HDR_EMMC_OFFSET;
 			} else {
-				offset = CONTAINER_HDR_MMCSD_OFFSET;
+				offset = sec_boot ? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET;
 			}
 		}
 	} else if (dev_type == QSPI_DEV) {
-		offset = CONTAINER_HDR_QSPI_OFFSET;
+		offset = sec_boot ? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) :
+			CONTAINER_HDR_QSPI_OFFSET;
 	} else if (dev_type == NAND_DEV) {
-		offset = CONTAINER_HDR_NAND_OFFSET;
+		offset = sec_boot ? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) :
+			CONTAINER_HDR_NAND_OFFSET;
 	} else if (dev_type == QSPI_NOR_DEV) {
 		offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000;
-	} else if (dev_type == ROM_API_DEV) {
-		offset = (unsigned long)dev;
+	} else {
+		printf("Not supported dev_type: %d\n", dev_type);
 	}
 
+	debug("container set offset 0x%lx\n", offset);
+
 	return offset;
 }
 
@@ -227,6 +288,25 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
 
 	return end / mmc->read_bl_len;
 }
+
+int spl_mmc_emmc_boot_partition(struct mmc *mmc)
+{
+	int part;
+
+	part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
+	if (part == 1 || part == 2) {
+		unsigned long sec_set_off = 0;
+		bool sec_boot = false;
+
+		sec_boot = check_secondary_cnt_set(&sec_set_off);
+		if (sec_boot)
+			part = (part == 1) ? 2 : 1;
+	} else if (part == 7) {
+		part = 0;
+	}
+
+	return part;
+}
 #endif
 
 #ifdef CONFIG_SPL_NAND_SUPPORT
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index 9addb824b6..b58b14ca9b 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2022 NXP
  */
 
 #include <common.h>
@@ -16,6 +16,8 @@
 #include <asm/mach-imx/image.h>
 #include <console.h>
 #include <cpu_func.h>
+#include "u-boot/sha256.h"
+#include <asm/mach-imx/ahab.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -24,6 +26,86 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE  (0x60000000UL)
 
 #define SECO_PT                 2U
+#define AHAB_HASH_TYPE_MASK	0x00000700
+#define AHAB_HASH_TYPE_SHA256	0
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
+{
+	int err;
+
+	memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container,
+	       ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
+
+	err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
+				   SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
+	if (err)
+		printf("Authenticate container hdr failed, return %d\n", err);
+
+	return err;
+}
+
+int ahab_auth_release(void)
+{
+	int err;
+
+	err = sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0);
+	if (err)
+		printf("Error: release container failed!\n");
+
+	return err;
+}
+
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
+{
+	sc_faddr_t start, end;
+	sc_rm_mr_t mr;
+	int err;
+	int ret = 0;
+
+	debug("img %d, dst 0x%llx, src 0x%x, size 0x%x\n",
+	      image_index, img->dst, img->offset, img->size);
+
+	/* Find the memreg and set permission for seco pt */
+	err = sc_rm_find_memreg(-1, &mr,
+				img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
+				ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1);
+
+	if (err) {
+		printf("Error: can't find memreg for image load address 0x%llx, error %d\n",
+		       img->dst, err);
+		return -ENOMEM;
+	}
+
+	err = sc_rm_get_memreg_info(-1, mr, &start, &end);
+	if (!err)
+		debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
+
+	err = sc_rm_set_memreg_permissions(-1, mr,
+					   SECO_PT, SC_RM_PERM_FULL);
+	if (err) {
+		printf("Set permission failed for img %d, error %d\n",
+		       image_index, err);
+		return -EPERM;
+	}
+
+	err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
+				   1 << image_index);
+	if (err) {
+		printf("Authenticate img %d failed, return %d\n",
+		       image_index, err);
+		ret = -EIO;
+	}
+
+	err = sc_rm_set_memreg_permissions(-1, mr,
+					   SECO_PT, SC_RM_PERM_NONE);
+	if (err) {
+		printf("Remove permission failed for img %d, error %d\n",
+		       image_index, err);
+		ret = -EPERM;
+	}
+
+	return ret;
+}
 
 static inline bool check_in_dram(ulong addr)
 {
@@ -46,11 +128,12 @@ int authenticate_os_container(ulong addr)
 	struct container_hdr *phdr;
 	int i, ret = 0;
 	int err;
-	sc_rm_mr_t mr;
-	sc_faddr_t start, end;
 	u16 length;
 	struct boot_img_t *img;
 	unsigned long s, e;
+#ifdef CONFIG_ARMV8_CE_SHA256
+	u8 hash_value[SHA256_SUM_LEN];
+#endif
 
 	if (addr % 4) {
 		puts("Error: Image's address is not 4 byte aligned\n");
@@ -76,14 +159,9 @@ int authenticate_os_container(ulong addr)
 	length = phdr->length_lsb + (phdr->length_msb << 8);
 
 	debug("container length %u\n", length);
-	memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)addr,
-	       ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
 
-	err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
-				   SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
+	err = ahab_auth_cntr_hdr(phdr, length);
 	if (err) {
-		printf("Authenticate container hdr failed, return %d\n",
-		       err);
 		ret = -EIO;
 		goto exit;
 	}
@@ -105,50 +183,27 @@ int authenticate_os_container(ulong addr)
 
 		flush_dcache_range(s, e);
 
-		/* Find the memreg and set permission for seco pt */
-		err = sc_rm_find_memreg(-1, &mr, s, e);
-		if (err) {
-			printf("Error: can't find memreg for image load address 0x%llx, error %d\n", img->dst, err);
-			ret = -ENOMEM;
-			goto exit;
-		}
-
-		err = sc_rm_get_memreg_info(-1, mr, &start, &end);
-		if (!err)
-			debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
-
-		err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT,
-						   SC_RM_PERM_FULL);
-		if (err) {
-			printf("Set permission failed for img %d, error %d\n",
-			       i, err);
-			ret = -EPERM;
-			goto exit;
-		}
-
-		err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
-					   (1 << i));
-		if (err) {
-			printf("Authenticate img %d failed, return %d\n",
-			       i, err);
-			ret = -EIO;
+#ifdef CONFIG_ARMV8_CE_SHA256
+		if (((img->hab_flags & AHAB_HASH_TYPE_MASK) >> 8) == AHAB_HASH_TYPE_SHA256) {
+			sha256_csum_wd((void *)img->dst, img->size, hash_value, CHUNKSZ_SHA256);
+			err = memcmp(&img->hash, &hash_value, SHA256_SUM_LEN);
+			if (err) {
+				printf("img %d hash comparison failed, error %d\n", i, err);
+				ret = -EIO;
+				goto exit;
+			}
+		} else {
+#endif
+			ret = ahab_verify_cntr_image(img, i);
+			if (ret)
+				goto exit;
+#ifdef CONFIG_ARMV8_CE_SHA256
 		}
-
-		err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT,
-						   SC_RM_PERM_NONE);
-		if (err) {
-			printf("Remove permission failed for img %d, err %d\n",
-			       i, err);
-			ret = -EPERM;
-		}
-
-		if (ret)
-			goto exit;
+#endif
 	}
 
 exit:
-	if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0) != SC_ERR_NONE)
-		printf("Error: release container failed!\n");
+	ahab_auth_release();
 
 	return ret;
 }
@@ -263,7 +318,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	u16 lc;
 
 	err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		printf("Error in get lifecycle\n");
 		return -EIO;
 	}
@@ -271,7 +326,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	display_life_cycle(lc);
 
 	err = sc_seco_get_event(-1, idx, &event);
-	while (err == SC_ERR_NONE) {
+	while (!err) {
 		printf("SECO Event[%u] = 0x%08X\n", idx, event);
 		display_ahab_auth_event(event);
 
@@ -312,7 +367,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
 		return -EACCES;
 
 	err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		printf("Error in get lifecycle\n");
 		return -EIO;
 	}
@@ -324,7 +379,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
 	}
 
 	err = sc_seco_forward_lifecycle(-1, 16);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		printf("Error in forward lifecycle to OEM closed\n");
 		return -EIO;
 	}
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 7b292c07ef..c62357044e 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -26,6 +26,8 @@
 #include <asm/armv8/mmu.h>
 #include <asm/setup.h>
 #include <asm/mach-imx/boot_mode.h>
+#include <power-domain.h>
+#include <elf.h>
 #include <spl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -107,6 +109,178 @@ int arch_misc_init(void)
 }
 #endif
 
+#ifdef CONFIG_IMX_BOOTAUX
+
+#ifdef CONFIG_IMX8QM
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
+{
+	sc_rsrc_t core_rsrc, mu_rsrc;
+	sc_faddr_t tcml_addr;
+	u32 tcml_size = SZ_128K;
+	ulong addr;
+
+	switch (core_id) {
+	case 0:
+		core_rsrc = SC_R_M4_0_PID0;
+		tcml_addr = 0x34FE0000;
+		mu_rsrc = SC_R_M4_0_MU_1A;
+		break;
+	case 1:
+		core_rsrc = SC_R_M4_1_PID0;
+		tcml_addr = 0x38FE0000;
+		mu_rsrc = SC_R_M4_1_MU_1A;
+		break;
+	default:
+		printf("Not support this core boot up, ID:%u\n", core_id);
+		return -EINVAL;
+	}
+
+	addr = (sc_faddr_t)boot_private_data;
+
+	if (addr >= tcml_addr && addr <= tcml_addr + tcml_size) {
+		printf("Wrong image address 0x%lx, should not in TCML\n",
+		       addr);
+		return -EINVAL;
+	}
+
+	printf("Power on M4 and MU\n");
+
+	if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+		return -EIO;
+
+	if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+		return -EIO;
+
+	printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr);
+
+	if (addr != tcml_addr)
+		memcpy((void *)tcml_addr, (void *)addr, tcml_size);
+
+	printf("Start M4 %u\n", core_id);
+	if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE)
+		return -EIO;
+
+	printf("bootaux complete\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_IMX8QXP
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
+{
+	sc_rsrc_t core_rsrc, mu_rsrc = SC_R_NONE;
+	sc_faddr_t aux_core_ram;
+	u32 size;
+	ulong addr;
+
+	switch (core_id) {
+	case 0:
+		core_rsrc = SC_R_M4_0_PID0;
+		aux_core_ram = 0x34FE0000;
+		mu_rsrc = SC_R_M4_0_MU_1A;
+		size = SZ_128K;
+		break;
+	case 1:
+		core_rsrc = SC_R_DSP;
+		aux_core_ram = 0x596f8000;
+		size = SZ_2K;
+		break;
+	default:
+		printf("Not support this core boot up, ID:%u\n", core_id);
+		return -EINVAL;
+	}
+
+	addr = (sc_faddr_t)boot_private_data;
+
+	if (addr >= aux_core_ram && addr <= aux_core_ram + size) {
+		printf("Wrong image address 0x%lx, should not in aux core ram\n",
+		       addr);
+		return -EINVAL;
+	}
+
+	printf("Power on aux core %d\n", core_id);
+
+	if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+		return -EIO;
+
+	if (mu_rsrc != SC_R_NONE) {
+		if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+			return -EIO;
+	}
+
+	if (core_id == 1) {
+		struct power_domain pd;
+
+		if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) {
+			printf("Error enable clock\n");
+			return -EIO;
+		}
+
+		if (!power_domain_lookup_name("audio_sai0", &pd)) {
+			if (power_domain_on(&pd)) {
+				printf("Error power on SAI0\n");
+				return -EIO;
+			}
+		}
+
+		if (!power_domain_lookup_name("audio_ocram", &pd)) {
+			if (power_domain_on(&pd)) {
+				printf("Error power on HIFI RAM\n");
+				return -EIO;
+			}
+		}
+	}
+
+	printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram);
+	if (core_id == 0) {
+		/* M4 use bin file */
+		memcpy((void *)aux_core_ram, (void *)addr, size);
+	} else {
+		/* HIFI use elf file */
+		if (!valid_elf_image(addr))
+			return -1;
+		addr = load_elf_image_shdr(addr);
+	}
+
+	printf("Start %s\n", core_id == 0 ? "M4" : "HIFI");
+
+	if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE)
+		return -EIO;
+
+	printf("bootaux complete\n");
+	return 0;
+}
+#endif
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+	sc_rsrc_t core_rsrc;
+	sc_pm_power_mode_t power_mode;
+
+	switch (core_id) {
+	case 0:
+		core_rsrc = SC_R_M4_0_PID0;
+		break;
+#ifdef CONFIG_IMX8QM
+	case 1:
+		core_rsrc = SC_R_M4_1_PID0;
+		break;
+#endif
+	default:
+		printf("Not support this core, ID:%u\n", core_id);
+		return 0;
+	}
+
+	if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE)
+		return 0;
+
+	if (power_mode != SC_PM_PW_MODE_OFF)
+		return 1;
+
+	return 0;
+}
+#endif
+
 int print_bootinfo(void)
 {
 	enum boot_device bt_dev = get_boot_device();
@@ -195,7 +369,7 @@ enum boot_device get_boot_device(void)
 #define FUSE_UNIQUE_ID_WORD1 17
 void get_board_serial(struct tag_serialnr *serialnr)
 {
-	sc_err_t err;
+	int err;
 	u32 val1 = 0, val2 = 0;
 	u32 word1, word2;
 
@@ -206,13 +380,13 @@ void get_board_serial(struct tag_serialnr *serialnr)
 	word2 = FUSE_UNIQUE_ID_WORD1;
 
 	err = sc_misc_otp_fuse_read(-1, word1, &val1);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		printf("%s fuse %d read error: %d\n", __func__, word1, err);
 		return;
 	}
 
 	err = sc_misc_otp_fuse_read(-1, word2, &val2);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		printf("%s fuse %d read error: %d\n", __func__, word2, err);
 		return;
 	}
diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c
index 02b3ee5c11..491c8bb8c7 100644
--- a/arch/arm/mach-imx/imx8/fdt.c
+++ b/arch/arm/mach-imx/imx8/fdt.c
@@ -110,7 +110,7 @@ static int config_smmu_resource_sid(int rsrc, int sid)
 
 	err = sc_rm_set_master_sid(-1, rsrc, sid);
 	debug("set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		if (!check_owned_resource(rsrc)) {
 			printf("%s rsrc[%d] not owned\n", __func__, rsrc);
 			return -1;
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c
index d7b20a1fcb..1eaa68f8d5 100644
--- a/arch/arm/mach-imx/imx8/snvs_security_sc.c
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c
@@ -286,16 +286,15 @@ static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2,
 				     u32 *_p3, u32 *_p4, u32 *_p5,
 				     u32 _cnt)
 {
-	int scierr = 0;
+	int err;
 	u32 d1 = ptr_value(_p1);
 	u32 d2 = ptr_value(_p2);
 	u32 d3 = ptr_value(_p3);
 	u32 d4 = ptr_value(_p4);
 	u32 d5 = ptr_value(_p5);
 
-	scierr = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3,
-				       &d4, &d4, _cnt);
-	if (scierr != SC_ERR_NONE) {
+	err = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3, &d4, &d4, _cnt);
+	if (err) {
 		printf("Failed to set secvio configuration\n");
 		debug("Failed to set conf id 0x%x with values ", id);
 		debug("0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x (cnt: %d)\n",
@@ -315,7 +314,7 @@ static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2,
 		*(u32 *)_p5 = d5;
 
 exit:
-	return scierr;
+	return err;
 }
 
 #define SC_CHECK_WRITE1(id, _p1) \
@@ -323,7 +322,7 @@ exit:
 
 static int apply_snvs_config(struct snvs_security_sc_conf *cnf)
 {
-	int scierr = 0;
+	int err = 0;
 
 	debug("%s\n", __func__);
 
@@ -365,92 +364,88 @@ static int apply_snvs_config(struct snvs_security_sc_conf *cnf)
 			cnf->lp.act_tamper_routing_ctl1,
 			cnf->lp.act_tamper_routing_ctl2);
 
-	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg),
-					   &cnf->lp.tamper_filt_cfg,
-					   &cnf->lp.tamper_filt1_cfg,
-					   &cnf->lp.tamper_filt2_cfg, NULL,
-					   NULL, 3);
-	if (scierr != SC_ERR_NONE)
+	err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg),
+					&cnf->lp.tamper_filt_cfg,
+					&cnf->lp.tamper_filt1_cfg,
+					&cnf->lp.tamper_filt2_cfg,
+					NULL, NULL, 3);
+	if (err)
 		goto exit;
 
 	/* Configure AT */
-	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg),
-					   &cnf->lp.act_tamper1_cfg,
-					   &cnf->lp.act_tamper2_cfg,
-					   &cnf->lp.act_tamper2_cfg,
-					   &cnf->lp.act_tamper2_cfg,
-					   &cnf->lp.act_tamper2_cfg, 5);
-	if (scierr != SC_ERR_NONE)
+	err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg),
+					&cnf->lp.act_tamper1_cfg,
+					&cnf->lp.act_tamper2_cfg,
+					&cnf->lp.act_tamper2_cfg,
+					&cnf->lp.act_tamper2_cfg,
+					&cnf->lp.act_tamper2_cfg, 5);
+	if (err)
 		goto exit;
 
 	/* Configure AT routing */
-	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1),
-					   &cnf->lp.act_tamper_routing_ctl1,
-					   &cnf->lp.act_tamper_routing_ctl2,
-					   NULL, NULL, NULL, 2);
-	if (scierr != SC_ERR_NONE)
+	err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1),
+					&cnf->lp.act_tamper_routing_ctl1,
+					&cnf->lp.act_tamper_routing_ctl2,
+					NULL, NULL, NULL, 2);
+	if (err)
 		goto exit;
 
 	/* Configure AT frequency */
-	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl),
-				 &cnf->lp.act_tamper_clk_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl),
+			      &cnf->lp.act_tamper_clk_ctl);
+	if (err)
 		goto exit;
 
 	/* Activate the ATs */
-	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl),
-				 &cnf->lp.act_tamper_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl), &cnf->lp.act_tamper_ctl);
+	if (err)
 		goto exit;
 
 	/* Activate the detectors */
-	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg),
-					   &cnf->lp.tamper_det_cfg,
-					   &cnf->lp.tamper_det_cfg2, NULL, NULL,
-					   NULL, 2);
-	if (scierr != SC_ERR_NONE)
+	err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg),
+					&cnf->lp.tamper_det_cfg,
+					&cnf->lp.tamper_det_cfg2, NULL, NULL, NULL, 2);
+	if (err)
 		goto exit;
 
 	/* Configure LP secvio */
-	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl),
-				 &cnf->lp.secvio_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl), &cnf->lp.secvio_ctl);
+	if (err)
 		goto exit;
 
 	/* Configure HP secvio */
-	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl),
-				 &cnf->hp.secvio_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl), &cnf->hp.secvio_ctl);
+	if (err)
 		goto exit;
 
 	/* Lock access */
-	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock);
-	if (scierr != SC_ERR_NONE)
+	err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock);
+	if (err)
 		goto exit;
 
-	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock);
-	if (scierr != SC_ERR_NONE)
+	err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock);
+	if (err)
 		goto exit;
 
 exit:
-	return (scierr == SC_ERR_NONE) ? 0 : -EIO;
+	return err;
 }
 
 static int dgo_write(u32 _id, u8 _access, u32 *_pdata)
 {
-	int scierr = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata);
+	int err = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata);
 
-	if (scierr != SC_ERR_NONE) {
+	if (err) {
 		printf("Failed to set dgo configuration\n");
 		debug("Failed to set conf id 0x%x : 0x%.8x", _id, *_pdata);
 	}
 
-	return scierr;
+	return err;
 }
 
 static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf)
 {
-	int scierr = 0;
+	int err;
 
 	debug("%s\n", __func__);
 
@@ -468,50 +463,50 @@ static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf)
 			cnf->tamper_misc_ctl,
 			cnf->tamper_core_volt_mon_ctl);
 
-	dgo_write(0x04, 1, &cnf->tamper_offset_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = dgo_write(0x04, 1, &cnf->tamper_offset_ctl);
+	if (err)
 		goto exit;
 
-	dgo_write(0x14, 1, &cnf->tamper_pull_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = dgo_write(0x14, 1, &cnf->tamper_pull_ctl);
+	if (err)
 		goto exit;
 
-	dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl);
+	if (err)
 		goto exit;
 
-	dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl);
+	if (err)
 		goto exit;
 
-	dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl);
+	if (err)
 		goto exit;
 
 	/* Last as it could lock the writes */
-	dgo_write(0x44, 1, &cnf->tamper_misc_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = dgo_write(0x44, 1, &cnf->tamper_misc_ctl);
+	if (err)
 		goto exit;
 
 exit:
-	return (scierr == SC_ERR_NONE) ? 0 : -EIO;
+	return err;
 }
 
 static int pad_write(u32 _pad, u32 _value)
 {
-	int scierr = sc_pad_set(-1, _pad, _value);
+	int err = sc_pad_set(-1, _pad, _value);
 
-	if (scierr != SC_ERR_NONE) {
+	if (err) {
 		printf("Failed to set pad configuration\n");
 		debug("Failed to set conf pad 0x%x : 0x%.8x", _pad, _value);
 	}
 
-	return scierr;
+	return err;
 }
 
 static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size)
 {
-	int scierr = 0;
+	int err = 0;
 	u32 idx;
 
 	debug("%s\n", __func__);
@@ -519,13 +514,13 @@ static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size)
 	for (idx = 0; idx < size; idx++) {
 		debug("\t idx %d: pad %d: 0x%.8x\n", idx, confs[idx].pad,
 		      confs[idx].mux_conf);
-		pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf);
-		if (scierr != SC_ERR_NONE)
+		err = pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf);
+		if (err)
 			goto exit;
 	}
 
 exit:
-	return (scierr == SC_ERR_NONE) ? 0 : -EIO;
+	return err;
 }
 
 int examples(void)
@@ -753,7 +748,7 @@ static char snvs_clear_status_help_text[] =
 static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc,
 				char *const argv[])
 {
-	int scierr = 0;
+	int err;
 	u32 idx = 0;
 
 	struct snvs_security_sc_conf conf = {0};
@@ -764,20 +759,18 @@ static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	conf.lp.status = hextoul(argv[++idx], NULL);
 	conf.lp.tamper_det_status = hextoul(argv[++idx], NULL);
 
-	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status),
-					   &conf.lp.status, NULL, NULL, NULL,
-					   NULL, 1);
-	if (scierr != SC_ERR_NONE)
+	err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status),
+					&conf.lp.status, NULL, NULL, NULL, NULL, 1);
+	if (err)
 		goto exit;
 
-	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status),
-					   &conf.lp.tamper_det_status, NULL,
-					   NULL, NULL, NULL, 1);
-	if (scierr != SC_ERR_NONE)
+	err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status),
+					&conf.lp.tamper_det_status, NULL, NULL, NULL, NULL, 1);
+	if (err)
 		goto exit;
 
 exit:
-	return (scierr == SC_ERR_NONE) ? 0 : 1;
+	return err;
 }
 
 U_BOOT_CMD(snvs_clear_status,
@@ -793,7 +786,7 @@ static char snvs_sec_status_help_text[] =
 static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
 			      char *const argv[])
 {
-	int scierr;
+	int err;
 	u32 idx;
 
 	u32 data[5];
@@ -864,8 +857,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	for (idx = 0; idx < ARRAY_SIZE(pads); idx++) {
 		u8 pad_id = pads[idx];
 
-		scierr = sc_pad_get(-1, pad_id, &data[0]);
-		if (scierr == 0)
+		err = sc_pad_get(-1, pad_id, &data[0]);
+		if (!err)
 			printf("\t- Pin %d: %.8x\n", pad_id, data[0]);
 		else
 			printf("Failed to read Pin %d\n", pad_id);
@@ -876,8 +869,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	for (idx = 0; idx < ARRAY_SIZE(fuses); idx++) {
 		u32 fuse_id = fuses[idx];
 
-		scierr = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]);
-		if (scierr == 0)
+		err = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]);
+		if (!err)
 			printf("\t- Fuse %d: %.8x\n", fuse_id, data[0]);
 		else
 			printf("Failed to read Fuse %d\n", fuse_id);
@@ -888,10 +881,10 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	for (idx = 0; idx < ARRAY_SIZE(snvs); idx++) {
 		struct snvs_reg *reg = &snvs[idx];
 
-		scierr = sc_seco_secvio_config(-1, reg->id, 0, &data[0],
-					       &data[1], &data[2], &data[3],
-					       &data[4], reg->nb);
-		if (scierr == 0) {
+		err = sc_seco_secvio_config(-1, reg->id, 0, &data[0],
+					    &data[1], &data[2], &data[3],
+					    &data[4], reg->nb);
+		if (!err) {
 			int subidx;
 
 			printf("\t- SNVS %.2x(%d):", reg->id, reg->nb);
@@ -908,8 +901,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	for (idx = 0; idx < ARRAY_SIZE(dgo); idx++) {
 		u8 dgo_id = dgo[idx];
 
-		scierr = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]);
-		if (scierr == 0)
+		err = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]);
+		if (!err)
 			printf("\t- DGO %.2x: %.8x\n", dgo_id, data[0]);
 		else
 			printf("Failed to read DGO %d\n", dgo_id);
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 7639439bdc..3d62d7052e 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -124,6 +124,9 @@ config TARGET_IMX8MM_VENICE
 	select IMX8M_LPDDR4
 	select GATEWORKS_SC
 	select MISC
+	select FSL_CAAM
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
 
 config TARGET_KONTRON_MX8MM
 	bool "Kontron Electronics N80xx"
@@ -175,6 +178,9 @@ config TARGET_IMX8MN_VENICE
 	select IMX8M_LPDDR4
 	select GATEWORKS_SC
 	select MISC
+	select FSL_CAAM
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
 
 config TARGET_IMX8MP_DATA_MODUL_EDM_SBC
 	bool "Data Modul eDM SBC i.MX8M Plus"
@@ -232,6 +238,9 @@ config TARGET_IMX8MP_VENICE
 	select IMX8M_LPDDR4
 	select GATEWORKS_SC
 	select MISC
+	select FSL_CAAM
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
 
 config TARGET_PICO_IMX8MQ
 	bool "Support Technexion Pico iMX8MQ"
@@ -245,6 +254,10 @@ config TARGET_IMX8MN_VAR_SOM
 	select IMX8MN
 	select SUPPORT_SPL
 	select IMX8M_DDR4
+	select MISC
+	select I2C_EEPROM
+	select DM_ETH_PHY
+	select NVMEM
 
 config TARGET_KONTRON_PITX_IMX8M
 	bool "Support Kontron pITX-imx8m"
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 31c34b6031..986870799d 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -90,7 +90,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq)
 	case ANATOP_DRAM_PLL:
 		setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
 		setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
-		writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
 
 		pll_base = &ana_pll->dram_pll_gnrl_ctl;
 		break;
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 5ffdcabbb5..78b775f449 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -333,7 +333,7 @@ phys_size_t get_effective_memsize(void)
 	}
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	ulong top_addr;
 
@@ -737,7 +737,7 @@ static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int siz
 		if (nodeoff < 0)
 			continue; /* Not found, skip it */
 
-		printf("Found %s node\n", nodes_path[i]);
+		debug("Found %s node\n", nodes_path[i]);
 
 add_status:
 		rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
@@ -1266,7 +1266,7 @@ int ft_system_setup(void *blob, struct bd_info *bd)
 		if (nodeoff >= 0) {
 			const char *speed = "high-speed";
 
-			printf("Found %s node\n", usb_dwc3_path[v]);
+			debug("Found %s node\n", usb_dwc3_path[v]);
 
 usb_modify_speed:
 
diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile
index f7692cf3a7..2c9938fcdf 100644
--- a/arch/arm/mach-imx/imx8ulp/Makefile
+++ b/arch/arm/mach-imx/imx8ulp/Makefile
@@ -5,7 +5,6 @@
 
 obj-y += lowlevel_init.o
 obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o
-obj-$(CONFIG_AHAB_BOOT) += ahab.o
 
 ifeq ($(CONFIG_SPL_BUILD),y)
 obj-y += upower/
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 50b097b035..cfc09e79cb 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -9,7 +9,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/mu_hal.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
 #include <asm/arch/rdc.h>
 #include <div64.h>
 
@@ -203,12 +203,12 @@ int xrdc_config_msc(u32 msc, u32 index, u32 dom, u32 perm)
 int release_rdc(enum rdc_type type)
 {
 	ulong s_mu_base = 0x27020000UL;
-	struct sentinel_msg msg;
+	struct ele_msg msg;
 	int ret;
 	u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 2;
 	msg.command = ELE_RELEASE_RDC_REQ;
 	msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */
@@ -266,7 +266,7 @@ void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access)
 				mrgd[4] |= ((access & 0xFFF) << 16);
 			}
 
-			/* not handle other cases, since S400 only set ACCESS1 and 2 */
+			/* not handle other cases, since ELE only set ACCESS1 and 2 */
 			writel(mrgd[4], xrdc_base + off + 0x10);
 			return;
 		}
@@ -295,7 +295,7 @@ void xrdc_init_mda(void)
 
 void xrdc_init_mrc(void)
 {
-	/* Re-config MRC3 for SRAM0 in case protected by S400 */
+	/* Re-config MRC3 for SRAM0 in case protected by ELE */
 	xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000);
 	xrdc_config_mrc_dx_perm(3, 0, 0, 1);
 	xrdc_config_mrc_dx_perm(3, 0, 1, 1);
@@ -320,7 +320,7 @@ void xrdc_init_mrc(void)
 	xrdc_config_mrc_dx_perm(5, 0, 1, 1);
 	xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);
 
-	/* Set MRC6 for DDR access from Sentinel */
+	/* Set MRC6 for DDR access from ELE */
 	xrdc_config_mrc_w0_w1(6, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
 	xrdc_config_mrc_dx_perm(6, 0, 4, 1);
 	xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
@@ -404,7 +404,7 @@ int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_acc
 	val &= ~(0xFU << offset);
 
 	/* MBC0-3
-	 *  Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+	 *  Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
 	 *  So select MBC0_MEMN_GLBAC0
 	 */
 	if (sec_access) {
@@ -445,7 +445,7 @@ int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_en
 			continue;
 
 		/* MRC0,1
-		 *  Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+		 *  Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
 		 *  So select MRCx_MEMN_GLBAC0
 		 */
 		if (sec_access) {
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 81eae02b6a..e23cf60d12 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -14,7 +14,7 @@
 #include <event.h>
 #include <spl.h>
 #include <asm/arch/rdc.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
 #include <asm/mach-imx/mu_hal.h>
 #include <cpu_func.h>
 #include <asm/setup.h>
@@ -70,7 +70,7 @@ int mmc_get_env_dev(void)
 }
 #endif
 
-static void set_cpu_info(struct sentinel_get_info_data *info)
+static void set_cpu_info(struct ele_get_info_data *info)
 {
 	gd->arch.soc_rev = info->soc;
 	gd->arch.lifecycle = info->lc;
@@ -582,9 +582,9 @@ void get_board_serial(struct tag_serialnr *serialnr)
 	u32 res;
 	int ret;
 
-	ret = ahab_read_common_fuse(1, uid, 4, &res);
+	ret = ele_read_common_fuse(1, uid, 4, &res);
 	if (ret)
-		printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+		printf("ele read fuse failed %d, 0x%x\n", ret, res);
 	else
 		printf("UID 0x%x,0x%x,0x%x,0x%x\n", uid[0], uid[1], uid[2], uid[3]);
 
@@ -783,7 +783,7 @@ int imx8ulp_dm_post_init(void)
 	struct udevice *devp;
 	int ret;
 	u32 res;
-	struct sentinel_get_info_data *info = (struct sentinel_get_info_data *)SRAM0_BASE;
+	struct ele_get_info_data *info = (struct ele_get_info_data *)SRAM0_BASE;
 
 	ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8ulp_mu), &devp);
 	if (ret) {
@@ -791,11 +791,11 @@ int imx8ulp_dm_post_init(void)
 		return ret;
 	}
 
-	ret = ahab_get_info(info, &res);
+	ret = ele_get_info(info, &res);
 	if (ret) {
-		printf("ahab_get_info failed %d\n", ret);
+		printf("ele_get_info failed %d\n", ret);
 		/* fallback to A0.1 revision */
-		memset((void *)info, 0, sizeof(struct sentinel_get_info_data));
+		memset((void *)info, 0, sizeof(struct ele_get_info_data));
 		info->soc = 0xa000084d;
 	}
 
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
index fcb02ed3af..b471a75caa 100644
--- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
@@ -217,8 +217,8 @@ int upower_init(void)
 	 * CM33 Cache
 	 * PowerQuad RAM
 	 * ETF RAM
-	 * Sentinel PKC, Data RAM1, Inst RAM0/1
-	 * Sentinel ROM
+	 * ELE PKC, Data RAM1, Inst RAM0/1
+	 * ELE ROM
 	 * uPower IRAM/DRAM
 	 * uPower ROM
 	 * CM33 ROM
@@ -230,7 +230,7 @@ int upower_init(void)
 	 * SSRAM Partition 7_a(128KB)
 	 * SSRAM Partition 7_b(64KB)
 	 * SSRAM Partition 7_c(64KB)
-	 * Sentinel Data RAM0, Inst RAM2
+	 * ELE Data RAM0, Inst RAM2
 	 */
 	/* MIPI-CSI FIFO BIT28 not set */
 	memon = 0x3FFFFFEFFFFFFCUL;
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index a7ecccaf87..766a8811c1 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -709,8 +709,8 @@ struct imx_clk_setting imx_clk_settings[] = {
 	/* Set A55 mtr bus to 133M */
 	{ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
 
-	/* Sentinel to 133M */
-	{SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+	/* ELE to 133M */
+	{ELE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
 	/* Bus_wakeup to 133M */
 	{BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
 	/* Bus_AON to 133M */
@@ -740,8 +740,8 @@ struct imx_clk_setting imx_clk_settings[] = {
 	{ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3},
 	/* Set A55 mtr bus to 133M */
 	{ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
-	/* Sentinel to 200M */
-	{SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
+	/* ELE to 200M */
+	{ELE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
 	/* Bus_wakeup to 133M */
 	{BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
 	/* Bus_AON to 133M */
diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c
index 06b93f6099..7d7ae86594 100644
--- a/arch/arm/mach-imx/imx9/clock_root.c
+++ b/arch/arm/mach-imx/imx9/clock_root.c
@@ -34,7 +34,7 @@ static struct clk_root_map clk_root_array[] = {
 	{ ARM_A55_MTR_BUS_CLK_ROOT,	2 },
 	{ ARM_A55_CLK_ROOT,		0 },
 	{ M33_CLK_ROOT,			2 },
-	{ SENTINEL_CLK_ROOT,		2 },
+	{ ELE_CLK_ROOT,			2 },
 	{ BUS_WAKEUP_CLK_ROOT,		2 },
 	{ BUS_AON_CLK_ROOT,		2 },
 	{ WAKEUP_AXI_CLK_ROOT,		0 },
diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c
index 256e6fa1c5..6afb59e051 100644
--- a/arch/arm/mach-imx/imx9/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx9/imx_bootaux.c
@@ -13,7 +13,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
 {
 	struct arm_smccc_res res;
 
-	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
+	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0,
 		      0, 0, 0, 0, &res);
 
 	return res.a0;
@@ -25,7 +25,7 @@ int arch_auxiliary_core_down(u32 core_id)
 
 	printf("## Stopping auxiliary core\n");
 
-	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STOP, 0, 0,
+	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, 0,
 		      0, 0, 0, 0, &res);
 
 	return 0;
@@ -40,7 +40,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
 
 	printf("## Starting auxiliary core addr = 0x%08lX...\n", addr);
 
-	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, addr, 0,
+	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, addr, 0,
 		      0, 0, 0, 0, &res);
 
 	return 0;
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 64e8ac610e..f43b73a6c2 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -34,7 +34,7 @@
 #include <asm/setup.h>
 #include <asm/bootm.h>
 #include <asm/arch-imx/cpu.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
 #include <fuse.h>
 #include <asm/arch/ddr.h>
 
@@ -151,7 +151,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
 	return val;
 }
 
-static void set_cpu_info(struct sentinel_get_info_data *info)
+static void set_cpu_info(struct ele_get_info_data *info)
 {
 	gd->arch.soc_rev = info->soc;
 	gd->arch.lifecycle = info->lc;
@@ -557,7 +557,7 @@ int imx9_probe_mu(void *ctx, struct event *event)
 	struct udevice *devp;
 	int node, ret;
 	u32 res;
-	struct sentinel_get_info_data info;
+	struct ele_get_info_data info;
 
 	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4");
 
@@ -568,7 +568,7 @@ int imx9_probe_mu(void *ctx, struct event *event)
 	if (gd->flags & GD_FLG_RELOC)
 		return 0;
 
-	ret = ahab_get_info(&info, &res);
+	ret = ele_get_info(&info, &res);
 	if (ret)
 		return ret;
 
@@ -600,35 +600,31 @@ int timer_init(void)
 enum env_location env_get_location(enum env_operation op, int prio)
 {
 	enum boot_device dev = get_boot_device();
-	enum env_location env_loc = ENVL_UNKNOWN;
 
 	if (prio)
-		return env_loc;
+		return ENVL_UNKNOWN;
 
 	switch (dev) {
-#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 	case QSPI_BOOT:
-		env_loc = ENVL_SPI_FLASH;
-		break;
-#endif
-#if defined(CONFIG_ENV_IS_IN_MMC)
+		if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		return ENVL_NOWHERE;
 	case SD1_BOOT:
 	case SD2_BOOT:
 	case SD3_BOOT:
 	case MMC1_BOOT:
 	case MMC2_BOOT:
 	case MMC3_BOOT:
-		env_loc =  ENVL_MMC;
-		break;
-#endif
+		if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
+			return ENVL_MMC;
+		else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4))
+			return ENVL_EXT4;
+		else if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT))
+			return ENVL_FAT;
+		return ENVL_NOWHERE;
 	default:
-#if defined(CONFIG_ENV_IS_NOWHERE)
-		env_loc = ENVL_NOWHERE;
-#endif
-		break;
+		return ENVL_NOWHERE;
 	}
-
-	return env_loc;
 }
 
 static int mix_power_init(enum mix_power_domain pd)
@@ -646,7 +642,7 @@ static int mix_power_init(enum mix_power_domain pd)
 		mem_id = SRC_MEM_MEDIA;
 		scr = BIT(5);
 
-		/* Enable S400 handshake */
+		/* Enable ELE handshake */
 		struct blk_ctrl_s_aonmix_regs *s_regs =
 			(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
 
@@ -763,8 +759,8 @@ int m33_prepare(void)
 	while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT))
 		val = readl(&mix_regs->func_stat);
 
-	/* Release Sentinel TROUT */
-	ahab_release_m33_trout();
+	/* Release ELE TROUT */
+	ele_release_m33_trout();
 
 	/* Mask WDOG1 IRQ from A55, we use it for M33 reset */
 	setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6));
@@ -772,7 +768,7 @@ int m33_prepare(void)
 	/* Turn on WDOG1 clock */
 	ccm_lpcg_on(CCGR_WDG1, 1);
 
-	/* Set sentinel LP handshake for M33 reset */
+	/* Set ELE LP handshake for M33 reset */
 	setbits_le32(&s_regs->lp_handshake[0], BIT(6));
 
 	/* Clear M33 TCM for ECC */
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index e05c704810..d0f855bb1b 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -10,7 +10,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
 #include <div64.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
 #include <asm/mach-imx/mu_hal.h>
 
 #define DID_NUM 16
@@ -196,7 +196,7 @@ int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x,
 	val &= ~(0xFU << offset);
 
 	/* MBC0-3
-	 *  Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+	 *  Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
 	 *  So select MBC0_MEMN_GLBAC0
 	 */
 	if (sec_access) {
@@ -266,7 +266,7 @@ int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32 addr_start,
 			continue;
 
 		/* MRC0,1
-		 *  Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+		 *  Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
 		 *  So select MRCx_MEMN_GLBAC0
 		 */
 		if (sec_access) {
@@ -315,7 +315,7 @@ bool trdc_mbc_enabled(ulong trdc_base)
 int release_rdc(u8 xrdc)
 {
 	ulong s_mu_base = 0x47520000UL;
-	struct sentinel_msg msg;
+	struct ele_msg msg;
 	int ret;
 	u32 rdc_id;
 
@@ -336,8 +336,8 @@ int release_rdc(u8 xrdc)
 		return -EINVAL;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 2;
 	msg.command = ELE_RELEASE_RDC_REQ;
 	msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */
@@ -394,7 +394,7 @@ void trdc_init(void)
 		/* DDR */
 		trdc_mrc_set_control(0x49010000, 0, 0, 0x7777);
 
-		/* S400*/
+		/* ELE */
 		trdc_mrc_region_config(0x49010000, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0);
 
 		/* MTR */
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 888c53d690..f7b14ca38d 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -14,6 +14,7 @@
 #include <linux/compiler.h>
 #include <cpu_func.h>
 
+#ifndef CONFIG_IMX8
 /* Just to avoid build error */
 #if IS_ENABLED(CONFIG_IMX8M)
 #define SRC_M4C_NON_SCLR_RST_MASK	BIT(0)
@@ -45,7 +46,7 @@ static const struct rproc_att *get_host_mapping(unsigned long auxcore)
  * is valid, returns the entry point address.
  * Translates load addresses in the elf file to the U-Boot address space.
  */
-static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack)
+static u32 load_elf_image_m_core_phdr(unsigned long addr, u32 *stack)
 {
 	Elf32_Ehdr *ehdr; /* ELF header structure pointer */
 	Elf32_Phdr *phdr; /* Program header structure pointer */
@@ -95,7 +96,7 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack
 
 int arch_auxiliary_core_up(u32 core_id, ulong addr)
 {
-	ulong stack, pc;
+	u32 stack, pc;
 
 	if (!addr)
 		return -EINVAL;
@@ -121,18 +122,18 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
 		pc = *(u32 *)(addr + 4);
 	}
 
-	printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
+	printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n",
 	       stack, pc);
 
-	/* Set the stack and pc to M4 bootROM */
-	writel(stack, M4_BOOTROM_BASE_ADDR);
-	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+	/* Set the stack and pc to MCU bootROM */
+	writel(stack, MCU_BOOTROM_BASE_ADDR);
+	writel(pc, MCU_BOOTROM_BASE_ADDR + 4);
 
 	flush_dcache_all();
 
-	/* Enable M4 */
+	/* Enable MCU */
 	if (IS_ENABLED(CONFIG_IMX8M)) {
-		arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL);
+		arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0, 0, 0, 0, 0, NULL);
 	} else {
 		clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
 				SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
@@ -147,7 +148,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
 	unsigned int val;
 
 	if (IS_ENABLED(CONFIG_IMX8M)) {
-		arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res);
+		arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, 0, 0, 0, 0, &res);
 		return res.a0;
 	}
 
@@ -158,30 +159,34 @@ int arch_auxiliary_core_check_up(u32 core_id)
 
 	return 1;
 }
-
+#endif
 /*
  * To i.MX6SX and i.MX7D, the image supported by bootaux needs
  * the reset vector at the head for the image, with SP and PC
  * as the first two words.
  *
- * Per the cortex-M reference manual, the reset vector of M4 needs
- * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
- * of that vector.  So to boot M4, the A core must build the M4's reset
+ * Per the cortex-M reference manual, the reset vector of M4/M7 needs
+ * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
+ * of that vector.  So to boot M4/M7, the A core must build the M4/M7's reset
  * vector with getting the PC and SP from image and filling them to
- * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
- * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
- * accessing the M4 TCMUL.
+ * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
+ * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
+ * accessing the M4/M7 TCMUL/IDTCM.
  */
 static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
 		      char *const argv[])
 {
 	ulong addr;
 	int ret, up;
+	u32 core = 0;
 
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
-	up = arch_auxiliary_core_check_up(0);
+	if (argc > 2)
+		core = simple_strtoul(argv[2], NULL, 10);
+
+	up = arch_auxiliary_core_check_up(core);
 	if (up) {
 		printf("## Auxiliary core is already up\n");
 		return CMD_RET_SUCCESS;
@@ -192,7 +197,7 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
 	if (!addr)
 		return CMD_RET_FAILURE;
 
-	ret = arch_auxiliary_core_up(0, addr);
+	ret = arch_auxiliary_core_up(core, addr);
 	if (ret)
 		return CMD_RET_FAILURE;
 
@@ -202,5 +207,7 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
 U_BOOT_CMD(
 	bootaux, CONFIG_SYS_MAXARGS, 1,	do_bootaux,
 	"Start auxiliary core",
-	""
+	"<address> [<core>]\n"
+	"   - start auxiliary core [<core>] (default 0),\n"
+	"     at address <address>\n"
 );
diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c
index 0f4565e311..b58f11c1e5 100644
--- a/arch/arm/mach-imx/mx6/module_fuse.c
+++ b/arch/arm/mach-imx/mx6/module_fuse.c
@@ -206,7 +206,7 @@ int ft_system_setup(void *blob, struct bd_info *bd)
 			if (off < 0)
 				continue; /* Not found, skip it */
 add_status:
-			rc = fdt_setprop(blob, nodeoff, "status", status,
+			rc = fdt_setprop(blob, off, "status", status,
 					 strlen(status) + 1);
 			if (rc) {
 				if (rc == -FDT_ERR_NOSPACE) {
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig
index b2026a3758..d3233d8d14 100644
--- a/arch/arm/mach-imx/mxs/Kconfig
+++ b/arch/arm/mach-imx/mxs/Kconfig
@@ -10,10 +10,12 @@ choice
 
 config TARGET_MX23_OLINUXINO
 	bool "Support mx23_olinuxino"
+	select PL01X_SERIAL
 	select BOARD_EARLY_INIT_F
 
 config TARGET_MX23EVK
 	bool "Support mx23evk"
+	select PL01X_SERIAL
 	select BOARD_EARLY_INIT_F
 
 config TARGET_XFI3
@@ -41,16 +43,37 @@ choice
 
 config TARGET_MX28EVK
 	bool "Support mx28evk"
+	select PL01X_SERIAL
 	select BOARD_EARLY_INIT_F
 
 config TARGET_XEA
 	bool "Support XEA"
+	select PL01X_SERIAL
 
 endchoice
 
 config SYS_SOC
 	default "mxs"
 
+config SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT
+	bool "Force minimal current draw from VDD5V by MX28 PMU"
+	default n
+	help
+	  After setting this option, the current drawn from VDD5V
+	  by the PMU is reduced to zero - the DCDC_BATT is used as
+	  the main power source for PMU.
+
+config SPL_MXS_PMU_DISABLE_BATT_CHARGE
+	bool "Disable Battery Charging in MX28 PMU"
+	default n
+
+config SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR
+	bool "Enable the 4P2 linear regulator in MX28 PMU"
+	default y
+	help
+	  This option enables the 4P2 linear regulator (derived
+	  from VDD5V) - so the VDD4P2 power source is operational.
+
 source "board/freescale/mx28evk/Kconfig"
 source "board/liebherr/xea/Kconfig"
 
diff --git a/arch/arm/mach-imx/parse-container.c b/arch/arm/mach-imx/parse-container.c
index f7582825d6..e2a9e2b273 100644
--- a/arch/arm/mach-imx/parse-container.c
+++ b/arch/arm/mach-imx/parse-container.c
@@ -1,75 +1,16 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2021 NXP
  */
 
 #include <common.h>
+#include <stdlib.h>
 #include <errno.h>
 #include <log.h>
 #include <spl.h>
 #include <asm/mach-imx/image.h>
 #ifdef CONFIG_AHAB_BOOT
-#include <firmware/imx/sci/sci.h>
-#endif
-
-#define SEC_SECURE_RAM_BASE		0x31800000UL
-#define SEC_SECURE_RAM_END_BASE		(SEC_SECURE_RAM_BASE + 0xFFFFUL)
-#define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE	0x60000000UL
-
-#define SECO_PT         2U
-
-#ifdef CONFIG_AHAB_BOOT
-static int authenticate_image(struct boot_img_t *img, int image_index)
-{
-	sc_faddr_t start, end;
-	sc_rm_mr_t mr;
-	int err;
-	int ret = 0;
-
-	debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n",
-	      image_index, (uint32_t)img->dst, img->offset, img->size);
-
-	/* Find the memreg and set permission for seco pt */
-	err = sc_rm_find_memreg(-1, &mr,
-				img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
-				ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1);
-
-	if (err) {
-		printf("can't find memreg for image %d load address 0x%x, error %d\n",
-		       image_index, img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), err);
-		return -ENOMEM;
-	}
-
-	err = sc_rm_get_memreg_info(-1, mr, &start, &end);
-	if (!err)
-		debug("memreg %u 0x%x -- 0x%x\n", mr, start, end);
-
-	err = sc_rm_set_memreg_permissions(-1, mr,
-					   SECO_PT, SC_RM_PERM_FULL);
-	if (err) {
-		printf("set permission failed for img %d, error %d\n",
-		       image_index, err);
-		return -EPERM;
-	}
-
-	err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
-				   1 << image_index);
-	if (err) {
-		printf("authenticate img %d failed, return %d\n",
-		       image_index, err);
-		ret = -EIO;
-	}
-
-	err = sc_rm_set_memreg_permissions(-1, mr,
-					   SECO_PT, SC_RM_PERM_NONE);
-	if (err) {
-		printf("remove permission failed for img %d, error %d\n",
-		       image_index, err);
-		ret = -EPERM;
-	}
-
-	return ret;
-}
+#include <asm/mach-imx/ahab.h>
 #endif
 
 static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
@@ -110,10 +51,8 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
 	}
 
 #ifdef CONFIG_AHAB_BOOT
-	if (authenticate_image(&images[image_index], image_index)) {
-		printf("Failed to authenticate image %d\n", image_index);
+	if (ahab_verify_cntr_image(&images[image_index], image_index))
 		return NULL;
-	}
 #endif
 
 	return &images[image_index];
@@ -134,21 +73,27 @@ static int read_auth_container(struct spl_image_info *spl_image,
 	 * It will not override the ATF code, so safe to use it here,
 	 * no need malloc
 	 */
-	container = (struct container_hdr *)spl_get_load_buffer(-size, size);
+	container = malloc(size);
+	if (!container)
+		return -ENOMEM;
 
 	debug("%s: container: %p sector: %lu sectors: %u\n", __func__,
 	      container, sector, sectors);
-	if (info->read(info, sector, sectors, container) != sectors)
-		return -EIO;
+	if (info->read(info, sector, sectors, container) != sectors) {
+		ret = -EIO;
+		goto end;
+	}
 
 	if (container->tag != 0x87 && container->version != 0x0) {
-		printf("Wrong container header\n");
-		return -ENOENT;
+		printf("Wrong container header");
+		ret = -ENOENT;
+		goto end;
 	}
 
 	if (!container->num_images) {
-		printf("Wrong container, no image found\n");
-		return -ENOENT;
+		printf("Wrong container, no image found");
+		ret = -ENOENT;
+		goto end;
 	}
 
 	length = container->length_lsb + (container->length_msb << 8);
@@ -158,25 +103,24 @@ static int read_auth_container(struct spl_image_info *spl_image,
 		size = roundup(length, info->bl_len);
 		sectors = size / info->bl_len;
 
-		container = (struct container_hdr *)spl_get_load_buffer(-size, size);
+		free(container);
+		container = malloc(size);
+		if (!container)
+			return -ENOMEM;
 
 		debug("%s: container: %p sector: %lu sectors: %u\n",
 		      __func__, container, sector, sectors);
 		if (info->read(info, sector, sectors, container) !=
-		    sectors)
-			return -EIO;
+		    sectors) {
+			ret = -EIO;
+			goto end;
+		}
 	}
 
 #ifdef CONFIG_AHAB_BOOT
-	memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container,
-	       ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
-
-	ret = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
-				   SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
-	if (ret) {
-		printf("authenticate container hdr failed, return %d\n", ret);
-		return ret;
-	}
+	ret = ahab_auth_cntr_hdr(container, length);
+	if (ret)
+		goto end_auth;
 #endif
 
 	for (i = 0; i < container->num_images; i++) {
@@ -197,9 +141,12 @@ static int read_auth_container(struct spl_image_info *spl_image,
 
 end_auth:
 #ifdef CONFIG_AHAB_BOOT
-	if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0))
-		printf("Error: release container failed!\n");
+	ahab_auth_release();
 #endif
+
+end:
+	free(container);
+
 	return ret;
 }
 
diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c
index 9b92eae781..5b022d5c82 100644
--- a/arch/arm/mach-imx/priblob.c
+++ b/arch/arm/mach-imx/priblob.c
@@ -13,12 +13,16 @@
 #include <asm/io.h>
 #include <common.h>
 #include <command.h>
-#include "../drivers/crypto/fsl_caam_internal.h"
+#include <fsl_sec.h>
 
 int do_priblob_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
 {
-	writel((readl(CAAM_SCFGR) & 0xFFFFFFFC) | 3, CAAM_SCFGR);
-	printf("New priblob setting = 0x%x\n", readl(CAAM_SCFGR) & 0x3);
+	ccsr_sec_t *sec_regs = (ccsr_sec_t *)CAAM_BASE_ADDR;
+	u32 scfgr = sec_in32(&sec_regs->scfgr);
+
+	scfgr |= 0x3;
+	sec_out32(&sec_regs->scfgr, scfgr);
+	printf("New priblob setting = 0x%x\n", sec_in32(&sec_regs->scfgr) & 0x3);
 
 	return 0;
 }
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index cb9801b7a1..6c13b00ef1 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -20,6 +20,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <g_dnl.h>
 #include <linux/libfdt.h>
+#include <memalign.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -315,47 +316,21 @@ ulong board_spl_fit_size_align(ulong size)
 	size = ALIGN(size, 0x1000);
 	size += CONFIG_CSF_SIZE;
 
-	return size;
-}
+	if (size > CONFIG_SYS_BOOTM_LEN)
+		panic("spl: ERROR: image too big\n");
 
-void board_spl_fit_post_load(const void *fit)
-{
-	u32 offset = ALIGN(fdt_totalsize(fit), 0x1000);
-
-	if (imx_hab_authenticate_image((uintptr_t)fit,
-				       offset + IVT_SIZE + CSF_PAD_SIZE,
-				       offset)) {
-		panic("spl: ERROR:  image authentication unsuccessful\n");
-	}
+	return size;
 }
 #endif
 
 void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
 {
-	int align_len = ARCH_DMA_MINALIGN - 1;
-
-	/* Some devices like SDP, NOR, NAND, SPI are using bl_len =1, so their fit address
-	 * is different with SD/MMC, this cause mismatch with signed address. Thus, adjust
-	 * the bl_len to align with SD/MMC.
-	 */
-	if (bl_len < 512)
-		bl_len = 512;
-
-	return  (void *)((CONFIG_TEXT_BASE - fit_size - bl_len -
-			align_len) & ~align_len);
-}
+#if defined(CONFIG_SPL_LOAD_FIT_ADDRESS)
+	return (void *)CONFIG_SPL_LOAD_FIT_ADDRESS;
+#else
+	return (void *)(CONFIG_TEXT_BASE + CONFIG_SYS_BOOTM_LEN);
 #endif
-
-#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = imx_ddr_size();
-
-	return 0;
 }
-#endif
-
 /*
  * read the address where the IVT header must sit
  * from IVT image header, loaded from SPL into
@@ -365,7 +340,6 @@ int dram_init_banksize(void)
 void *spl_load_simple_fit_fix_load(const void *fit)
 {
 	struct ivt *ivt;
-	unsigned long new;
 	unsigned long offset;
 	unsigned long size;
 	u8 *tmp = (u8 *)fit;
@@ -375,16 +349,23 @@ void *spl_load_simple_fit_fix_load(const void *fit)
 	size = board_spl_fit_size_align(size);
 	tmp += offset;
 	ivt = (struct ivt *)tmp;
-	if (ivt->hdr.magic != IVT_HEADER_MAGIC) {
-		debug("no IVT header found\n");
-		return (void *)fit;
-	}
+
 	debug("%s: ivt: %p offset: %lx size: %lx\n", __func__, ivt, offset, size);
 	debug("%s: ivt self: %x\n", __func__, ivt->self);
-	new = ivt->self;
-	new -= offset;
-	debug("%s: new %lx\n", __func__, new);
-	memcpy((void *)new, fit, size);
 
-	return (void *)new;
+	if (imx_hab_authenticate_image((uintptr_t)fit, (uintptr_t)ivt, offset))
+		panic("spl: ERROR: image authentication unsuccessful\n");
+
+	return (void *)fit;
 }
+#endif /* CONFIG_IMX_HAB */
+
+#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = imx_ddr_size();
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c
index 9164045115..4af4169967 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -76,13 +76,16 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image,
 	u32 image_offset;
 
 	ret = rom_api_query_boot_infor(QUERY_IVT_OFF, &offset);
-	ret |= rom_api_query_boot_infor(QUERY_PAGE_SZ, &pagesize);
-	ret |= rom_api_query_boot_infor(QUERY_IMG_OFF, &image_offset);
+	if (ret != ROM_API_OKAY)
+		goto err;
 
-	if (ret != ROM_API_OKAY) {
-		puts("ROMAPI: Failure query boot infor pagesize/offset\n");
-		return -1;
-	}
+	ret = rom_api_query_boot_infor(QUERY_PAGE_SZ, &pagesize);
+	if (ret != ROM_API_OKAY)
+		goto err;
+
+	ret = rom_api_query_boot_infor(QUERY_IMG_OFF, &image_offset);
+	if (ret != ROM_API_OKAY)
+		goto err;
 
 	header = (struct legacy_img_hdr *)(CONFIG_SPL_IMX_ROMAPI_LOADADDR);
 
@@ -124,6 +127,10 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image,
 	}
 
 	return 0;
+
+err:
+	puts("ROMAPI: Failure query boot infor pagesize/offset\n");
+	return -1;
 }
 
 static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
@@ -344,12 +351,12 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
 	u32 boot, bstage;
 
 	ret = rom_api_query_boot_infor(QUERY_BT_DEV, &boot);
-	ret |= rom_api_query_boot_infor(QUERY_BT_STAGE, &bstage);
+	if (ret != ROM_API_OKAY)
+		goto err;
 
-	if (ret != ROM_API_OKAY) {
-		puts("ROMAPI: failure at query_boot_info\n");
-		return -1;
-	}
+	ret = rom_api_query_boot_infor(QUERY_BT_STAGE, &bstage);
+	if (ret != ROM_API_OKAY)
+		goto err;
 
 	printf("Boot Stage: ");
 
@@ -374,4 +381,7 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
 		return spl_romapi_load_image_stream(spl_image, bootdev);
 
 	return spl_romapi_load_image_seekable(spl_image, bootdev, boot);
+err:
+	puts("ROMAPI: failure at query_boot_info\n");
+	return -1;
 }
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index bae0a827c2..9168bf842d 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -52,7 +52,7 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
 config SYS_K3_MCU_SCRATCHPAD_BASE
 	hex
 	default 0x40280000 if SOC_K3_AM654
-	default 0x40280000 if SOC_K3_J721S2
+	default 0x41cff9fc if SOC_K3_J721S2
 	default 0x41cff9fc if SOC_K3_J721E
 	help
 	  Describes the base address of MCU Scratchpad RAM.
@@ -194,4 +194,5 @@ source "board/ti/am62ax/Kconfig"
 source "board/ti/j721e/Kconfig"
 source "board/siemens/iot2050/Kconfig"
 source "board/ti/j721s2/Kconfig"
+source "board/toradex/verdin-am62/Kconfig"
 endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index b5bc236781..fd77b8bbba 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -10,6 +10,13 @@ obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
 obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
 obj-$(CONFIG_ARM64) += cache.o
+obj-$(CONFIG_OF_LIBFDT) += common_fdt.o
+ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy)
+obj-$(CONFIG_SOC_K3_AM654) += am654_fdt.o
+obj-$(CONFIG_SOC_K3_J721E) += j721e_fdt.o
+obj-$(CONFIG_SOC_K3_J721S2) += j721s2_fdt.o
+obj-$(CONFIG_SOC_K3_AM625) += am625_fdt.o
+endif
 ifeq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_SOC_K3_AM654) += am654_init.o
 obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
diff --git a/arch/arm/mach-k3/am625_fdt.c b/arch/arm/mach-k3/am625_fdt.c
new file mode 100644
index 0000000000..37806907af
--- /dev/null
+++ b/arch/arm/mach-k3/am625_fdt.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2023 Toradex - https://www.toradex.com/
+ */
+
+#include <asm/hardware.h>
+#include "common_fdt.h"
+#include <fdt_support.h>
+
+static void fdt_fixup_cores_nodes_am625(void *blob, int core_nr)
+{
+	char node_path[32];
+
+	if (core_nr < 1)
+		return;
+
+	for (; core_nr < 4; core_nr++) {
+		snprintf(node_path, sizeof(node_path), "/cpus/cpu@%d", core_nr);
+		fdt_del_node_path(blob, node_path);
+		snprintf(node_path, sizeof(node_path), "/cpus/cpu-map/cluster0/core%d", core_nr);
+		fdt_del_node_path(blob, node_path);
+		snprintf(node_path, sizeof(node_path), "/bus@f0000/watchdog@e0%d0000", core_nr);
+		fdt_del_node_path(blob, node_path);
+	}
+}
+
+static void fdt_fixup_gpu_nodes_am625(void *blob, int has_gpu)
+{
+	if (!has_gpu) {
+		fdt_del_node_path(blob, "/bus@f0000/gpu@fd00000");
+		fdt_del_node_path(blob, "/bus@f0000/watchdog@e0f0000");
+	}
+}
+
+static void fdt_fixup_pru_node_am625(void *blob, int has_pru)
+{
+	if (!has_pru)
+		fdt_del_node_path(blob, "/bus@f0000/pruss@30040000");
+}
+
+static int k3_get_core_nr(void)
+{
+	u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
+
+	return (full_devid & JTAG_DEV_CORE_NR_MASK) >> JTAG_DEV_CORE_NR_SHIFT;
+}
+
+static int k3_has_pru(void)
+{
+	u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
+	u32 feature_mask = (full_devid & JTAG_DEV_FEATURES_MASK) >>
+			   JTAG_DEV_FEATURES_SHIFT;
+
+	return !(feature_mask & JTAG_DEV_FEATURE_NO_PRU);
+}
+
+static int k3_has_gpu(void)
+{
+	u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
+
+	return (full_devid & JTAG_DEV_GPU_MASK) >> JTAG_DEV_GPU_SHIFT;
+}
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+	fdt_fixup_cores_nodes_am625(blob, k3_get_core_nr());
+	fdt_fixup_gpu_nodes_am625(blob, k3_has_gpu());
+	fdt_fixup_pru_node_am625(blob, k3_has_pru());
+
+	return 0;
+}
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 026c4f9c02..0e5d44269e 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -15,6 +15,15 @@
 #include <dm/uclass-internal.h>
 #include <dm/pinctrl.h>
 
+#define RTC_BASE_ADDRESS		0x2b1f0000
+#define REG_K3RTC_S_CNT_LSW		(RTC_BASE_ADDRESS + 0x18)
+#define REG_K3RTC_KICK0			(RTC_BASE_ADDRESS + 0x70)
+#define REG_K3RTC_KICK1			(RTC_BASE_ADDRESS + 0x74)
+
+/* Magic values for lock/unlock */
+#define K3RTC_KICK0_UNLOCK_VALUE	0x83e70b13
+#define K3RTC_KICK1_UNLOCK_VALUE	0x95a4f1e0
+
 /*
  * This uninitialized global variable would normal end up in the .bss section,
  * but the .bss is cleared between writing and reading this variable, so move
@@ -71,6 +80,42 @@ static __maybe_unused void enable_mcu_esm_reset(void)
 	writel(stat, CTRLMMR_MCU_RST_CTRL);
 }
 
+#if defined(CONFIG_CPU_V7R)
+
+/*
+ * RTC Erratum i2327 Workaround for Silicon Revision 1
+ *
+ * Due to a bug in initial synchronization out of cold power on,
+ * IRQ status can get locked infinitely if we do not unlock RTC
+ *
+ * This workaround *must* be applied within 1 second of power on,
+ * So, this is closest point to be able to guarantee the max
+ * timing.
+ *
+ * https://www.ti.com/lit/er/sprz487c/sprz487c.pdf
+ */
+void rtc_erratumi2327_init(void)
+{
+	u32 counter;
+
+	/*
+	 * If counter has gone past 1, nothing we can do, leave
+	 * system locked! This is the only way we know if RTC
+	 * can be used for all practical purposes.
+	 */
+	counter = readl(REG_K3RTC_S_CNT_LSW);
+	if (counter > 1)
+		return;
+	/*
+	 * Need to set this up at the very start
+	 * MUST BE DONE under 1 second of boot.
+	 */
+	writel(K3RTC_KICK0_UNLOCK_VALUE, REG_K3RTC_KICK0);
+	writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1);
+	return;
+}
+#endif
+
 void board_init_f(ulong dummy)
 {
 	struct udevice *dev;
@@ -78,6 +123,7 @@ void board_init_f(ulong dummy)
 
 #if defined(CONFIG_CPU_V7R)
 	setup_k3_mpu_regions();
+	rtc_erratumi2327_init();
 #endif
 
 	/*
@@ -168,6 +214,7 @@ void board_init_f(ulong dummy)
 	if (ret)
 		panic("DRAM init failed: %d\n", ret);
 #endif
+	spl_enable_dcache();
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c
index 1f51b04089..d72e19936b 100644
--- a/arch/arm/mach-k3/am62a7_init.c
+++ b/arch/arm/mach-k3/am62a7_init.c
@@ -14,6 +14,10 @@
 #include <dm/uclass-internal.h>
 #include <dm/pinctrl.h>
 
+struct fwl_data cbass_main_fwls[] = {
+       { "FSS_DAT_REG3", 7, 8 },
+};
+
 /*
  * This uninitialized global variable would normal end up in the .bss section,
  * but the .bss is cleared between writing and reading this variable, so move
@@ -166,6 +170,9 @@ void board_init_f(ulong dummy)
 	/* Output System Firmware version info */
 	k3_sysfw_print_ver();
 
+       /* Disable ROM configured firewalls right after loading sysfw */
+       remove_fwl_configs(cbass_main_fwls, ARRAY_SIZE(cbass_main_fwls));
+
 #if defined(CONFIG_K3_AM62A_DDRSS)
 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 	if (ret)
@@ -174,7 +181,7 @@ void board_init_f(ulong dummy)
 
 	setup_qos();
 
-	printf("am62a_init: %s done\n", __func__);
+	debug("am62a_init: %s done\n", __func__);
 }
 
 static u32 __get_backup_bootmedia(u32 devstat)
@@ -272,7 +279,7 @@ u32 spl_boot_device(void)
 	else
 		bootmedia = __get_backup_bootmedia(devstat);
 
-	printf("am62a_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
+	debug("am62a_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
 	       __func__, devstat, bootmedia, bootindex);
 	return bootmedia;
 }
diff --git a/arch/arm/mach-k3/am62ax/dev-data.c b/arch/arm/mach-k3/am62ax/dev-data.c
index 74739c6385..abf5d8e91a 100644
--- a/arch/arm/mach-k3/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/am62ax/dev-data.c
@@ -66,8 +66,8 @@ const struct ti_k3_pd_platdata am62ax_pd_platdata = {
 	.pd = soc_pd_list,
 	.lpsc = soc_lpsc_list,
 	.devs = soc_dev_list,
-	.num_psc = 2,
-	.num_pd = 4,
-	.num_lpsc = 14,
-	.num_devs = 19,
+	.num_psc = ARRAY_SIZE(soc_psc_list),
+	.num_pd = ARRAY_SIZE(soc_pd_list),
+	.num_lpsc = ARRAY_SIZE(soc_lpsc_list),
+	.num_devs = ARRAY_SIZE(soc_dev_list),
 };
diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/am62x/clk-data.c
index c0881778fe..d7bfed0e03 100644
--- a/arch/arm/mach-k3/am62x/clk-data.c
+++ b/arch/arm/mach-k3/am62x/clk-data.c
@@ -57,7 +57,7 @@ static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
 
 static const char * const clkout0_ctrl_out0_parents[] = {
 	"hsdiv4_16fft_main_2_hsdivout1_clk",
-	"hsdiv4_16fft_main_2_hsdivout1_clk",
+	"hsdiv4_16fft_main_2_hsdivout1_clk10",
 };
 
 static const char * const clk_32k_rc_sel_out0_parents[] = {
@@ -195,6 +195,7 @@ static const struct clk_data clk_list[] = {
 	CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
 	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
 	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
+	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
 	CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
 	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
 	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
@@ -313,7 +314,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(157, 20, "clkout0_ctrl_out0"),
 	DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-	DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"),
 	DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
 	DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
diff --git a/arch/arm/mach-k3/am62x/dev-data.c b/arch/arm/mach-k3/am62x/dev-data.c
index 616d0650b9..59c95df2a8 100644
--- a/arch/arm/mach-k3/am62x/dev-data.c
+++ b/arch/arm/mach-k3/am62x/dev-data.c
@@ -58,6 +58,7 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(161, &soc_lpsc_list[8]),
 	PSC_DEV(162, &soc_lpsc_list[9]),
 	PSC_DEV(75, &soc_lpsc_list[10]),
+	PSC_DEV(36, &soc_lpsc_list[11]),
 	PSC_DEV(102, &soc_lpsc_list[11]),
 	PSC_DEV(146, &soc_lpsc_list[11]),
 	PSC_DEV(13, &soc_lpsc_list[12]),
@@ -71,8 +72,8 @@ const struct ti_k3_pd_platdata am62x_pd_platdata = {
 	.pd = soc_pd_list,
 	.lpsc = soc_lpsc_list,
 	.devs = soc_dev_list,
-	.num_psc = 2,
-	.num_pd = 5,
-	.num_lpsc = 16,
-	.num_devs = 21,
+	.num_psc = ARRAY_SIZE(soc_psc_list),
+	.num_pd = ARRAY_SIZE(soc_pd_list),
+	.num_lpsc = ARRAY_SIZE(soc_lpsc_list),
+	.num_devs = ARRAY_SIZE(soc_dev_list),
 };
diff --git a/arch/arm/mach-k3/am654_fdt.c b/arch/arm/mach-k3/am654_fdt.c
new file mode 100644
index 0000000000..652fe8d32b
--- /dev/null
+++ b/arch/arm/mach-k3/am654_fdt.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2023 Toradex - https://www.toradex.com/
+ */
+
+#include "common_fdt.h"
+#include <fdt_support.h>
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+	return fdt_fixup_msmc_ram_k3(blob);
+}
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 88687c2d09..f8087d2421 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -222,14 +222,13 @@ struct mm_region *mem_map = j721s2_mem_map;
 
 #endif /* CONFIG_SOC_K3_J721S2 */
 
-#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) || \
-	defined(CONFIG_SOC_K3_AM62A7)
+#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7)
 
 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
-#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 3)
+#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 4)
 
 /* ToDo: Add 64bit IO */
-struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
+struct mm_region am62_mem_map[NR_MMU_REGIONS] = {
 	{
 		.virt = 0x0UL,
 		.phys = 0x0UL,
@@ -240,10 +239,65 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
 	}, {
 		.virt = 0x80000000UL,
 		.phys = 0x80000000UL,
+		.size = 0x1E780000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xA0000000UL,
+		.phys = 0xA0000000UL,
+		.size = 0x60000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+
+	}, {
+		.virt = 0x880000000UL,
+		.phys = 0x880000000UL,
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {
+		.virt = 0x500000000UL,
+		.phys = 0x500000000UL,
+		.size = 0x400000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = am62_mem_map;
+#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
+
+#ifdef CONFIG_SOC_K3_AM642
+
+/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
+#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 4)
+
+/* ToDo: Add 64bit IO */
+struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x1E800000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xA0000000UL,
+		.phys = 0xA0000000UL,
+		.size = 0x60000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
 		.virt = 0x880000000UL,
 		.phys = 0x880000000UL,
 		.size = 0x80000000UL,
@@ -263,4 +317,4 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
 };
 
 struct mm_region *mem_map = am64_mem_map;
-#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
+#endif /* CONFIG_SOC_K3_AM642 */
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 34737a43aa..a35110429b 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -357,97 +357,6 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image,
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT)
-int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
-{
-	u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
-	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
-	int ret, node, subnode, len, prev_node;
-	u32 range[4], addr, size;
-	const fdt32_t *sub_reg;
-
-	ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
-	msmc_size = msmc_end - msmc_start + 1;
-	debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
-	      msmc_start, msmc_size);
-
-	/* find or create "msmc_sram node */
-	ret = fdt_path_offset(blob, parent_path);
-	if (ret < 0)
-		return ret;
-
-	node = fdt_find_or_add_subnode(blob, ret, node_name);
-	if (node < 0)
-		return node;
-
-	ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
-	if (ret < 0)
-		return ret;
-
-	reg[0] = cpu_to_fdt64(msmc_start);
-	reg[1] = cpu_to_fdt64(msmc_size);
-	ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
-	if (ret < 0)
-		return ret;
-
-	fdt_setprop_cell(blob, node, "#address-cells", 1);
-	fdt_setprop_cell(blob, node, "#size-cells", 1);
-
-	range[0] = 0;
-	range[1] = cpu_to_fdt32(msmc_start >> 32);
-	range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
-	range[3] = cpu_to_fdt32(msmc_size);
-	ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
-	if (ret < 0)
-		return ret;
-
-	subnode = fdt_first_subnode(blob, node);
-	prev_node = 0;
-
-	/* Look for invalid subnodes and delete them */
-	while (subnode >= 0) {
-		sub_reg = fdt_getprop(blob, subnode, "reg", &len);
-		addr = fdt_read_number(sub_reg, 1);
-		sub_reg++;
-		size = fdt_read_number(sub_reg, 1);
-		debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
-		      subnode, addr, size);
-		if (addr + size > msmc_size ||
-		    !strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
-		    !strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
-			fdt_del_node(blob, subnode);
-			debug("%s: deleting subnode %d\n", __func__, subnode);
-			if (!prev_node)
-				subnode = fdt_first_subnode(blob, node);
-			else
-				subnode = fdt_next_subnode(blob, prev_node);
-		} else {
-			prev_node = subnode;
-			subnode = fdt_next_subnode(blob, prev_node);
-		}
-	}
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_SYSTEM_SETUP)
-int ft_system_setup(void *blob, struct bd_info *bd)
-{
-	int ret;
-
-	ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
-	if (ret < 0)
-		ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
-					 "sram@70000000");
-	if (ret)
-		printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
-
-	return ret;
-}
-#endif
-
-#endif
-
 #ifndef CONFIG_SYSRESET
 void reset_cpu(void)
 {
@@ -568,39 +477,50 @@ void disable_linefill_optimization(void)
 }
 #endif
 
-void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
+static void remove_fwl_regions(struct fwl_data fwl_data, size_t num_regions,
+			       enum k3_firewall_region_type fwl_type)
 {
-	struct ti_sci_msg_fwl_region region;
 	struct ti_sci_fwl_ops *fwl_ops;
 	struct ti_sci_handle *ti_sci;
-	size_t i, j;
+	struct ti_sci_msg_fwl_region region;
+	size_t j;
 
 	ti_sci = get_ti_sci_handle();
 	fwl_ops = &ti_sci->ops.fwl_ops;
-	for (i = 0; i < fwl_data_size; i++) {
-		for (j = 0; j <  fwl_data[i].regions; j++) {
-			region.fwl_id = fwl_data[i].fwl_id;
-			region.region = j;
-			region.n_permission_regs = 3;
-
-			fwl_ops->get_fwl_region(ti_sci, &region);
-
-			/* Don't disable the background regions */
-			if (region.control != 0 &&
-			    ((region.control & K3_BACKGROUND_FIREWALL_BIT) ==
-			     0)) {
-				pr_debug("Attempting to disable firewall %5d (%25s)\n",
-					 region.fwl_id, fwl_data[i].name);
-				region.control = 0;
-
-				if (fwl_ops->set_fwl_region(ti_sci, &region))
-					pr_err("Could not disable firewall %5d (%25s)\n",
-					       region.fwl_id, fwl_data[i].name);
-			}
+
+	for (j = 0; j < fwl_data.regions; j++) {
+		region.fwl_id = fwl_data.fwl_id;
+		region.region = j;
+		region.n_permission_regs = 3;
+
+		fwl_ops->get_fwl_region(ti_sci, &region);
+
+		/* Don't disable the background regions */
+		if (region.control != 0 &&
+		    ((region.control >> K3_FIREWALL_BACKGROUND_BIT) & 1) == fwl_type) {
+			pr_debug("Attempting to disable firewall %5d (%25s)\n",
+				 region.fwl_id, fwl_data.name);
+			region.control = 0;
+
+			if (fwl_ops->set_fwl_region(ti_sci, &region))
+				pr_err("Could not disable firewall %5d (%25s)\n",
+				       region.fwl_id, fwl_data.name);
 		}
 	}
 }
 
+void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
+{
+	size_t i;
+
+	for (i = 0; i < fwl_data_size; i++) {
+		remove_fwl_regions(fwl_data[i], fwl_data[i].regions,
+				   K3_FIREWALL_REGION_FOREGROUND);
+		remove_fwl_regions(fwl_data[i], fwl_data[i].regions,
+				   K3_FIREWALL_REGION_BACKGROUND);
+	}
+}
+
 void spl_enable_dcache(void)
 {
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
@@ -617,8 +537,10 @@ void spl_enable_dcache(void)
 		ram_top = (phys_addr_t) 0x100000000;
 
 	gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
+	gd->arch.tlb_addr &= ~(0x10000 - 1);
 	debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
 	      gd->arch.tlb_addr + gd->arch.tlb_size);
+	gd->relocaddr = gd->arch.tlb_addr;
 
 	dcache_enable();
 #endif
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 899be64a50..9bd9ad6d1a 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -9,9 +9,7 @@
 #include <asm/armv7_mpu.h>
 #include <asm/hardware.h>
 
-#define J721E  0xbb64
-#define J7200  0xbb6d
-#define K3_BACKGROUND_FIREWALL_BIT BIT(8)
+#define K3_FIREWALL_BACKGROUND_BIT (8)
 
 struct fwl_data {
 	const char *name;
@@ -19,6 +17,11 @@ struct fwl_data {
 	u16 regions;
 };
 
+enum k3_firewall_region_type {
+	K3_FIREWALL_REGION_FOREGROUND,
+	K3_FIREWALL_REGION_BACKGROUND
+};
+
 enum k3_device_type {
 	K3_DEVICE_TYPE_BAD,
 	K3_DEVICE_TYPE_GP,
diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c
new file mode 100644
index 0000000000..645c4de42f
--- /dev/null
+++ b/arch/arm/mach-k3/common_fdt.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2023 Toradex - https://www.toradex.com/
+ */
+
+#include "common.h"
+#include <dm.h>
+#include <fdt_support.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include "common_fdt.h"
+
+static int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
+{
+	u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
+	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+	int ret, node, subnode, len, prev_node;
+	u32 range[4], addr, size;
+	const fdt32_t *sub_reg;
+
+	ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
+	msmc_size = msmc_end - msmc_start + 1;
+	debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
+	      msmc_start, msmc_size);
+
+	/* find or create "msmc_sram node */
+	ret = fdt_path_offset(blob, parent_path);
+	if (ret < 0)
+		return ret;
+
+	node = fdt_find_or_add_subnode(blob, ret, node_name);
+	if (node < 0)
+		return node;
+
+	ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
+	if (ret < 0)
+		return ret;
+
+	reg[0] = cpu_to_fdt64(msmc_start);
+	reg[1] = cpu_to_fdt64(msmc_size);
+	ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
+	if (ret < 0)
+		return ret;
+
+	fdt_setprop_cell(blob, node, "#address-cells", 1);
+	fdt_setprop_cell(blob, node, "#size-cells", 1);
+
+	range[0] = 0;
+	range[1] = cpu_to_fdt32(msmc_start >> 32);
+	range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
+	range[3] = cpu_to_fdt32(msmc_size);
+	ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
+	if (ret < 0)
+		return ret;
+
+	subnode = fdt_first_subnode(blob, node);
+	prev_node = 0;
+
+	/* Look for invalid subnodes and delete them */
+	while (subnode >= 0) {
+		sub_reg = fdt_getprop(blob, subnode, "reg", &len);
+		addr = fdt_read_number(sub_reg, 1);
+		sub_reg++;
+		size = fdt_read_number(sub_reg, 1);
+		debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
+		      subnode, addr, size);
+		if (addr + size > msmc_size ||
+		    !strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
+		    !strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
+			fdt_del_node(blob, subnode);
+			debug("%s: deleting subnode %d\n", __func__, subnode);
+			if (!prev_node)
+				subnode = fdt_first_subnode(blob, node);
+			else
+				subnode = fdt_next_subnode(blob, prev_node);
+		} else {
+			prev_node = subnode;
+			subnode = fdt_next_subnode(blob, prev_node);
+		}
+	}
+
+	return 0;
+}
+
+int fdt_fixup_msmc_ram_k3(void *blob)
+{
+	int ret;
+
+	ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
+	if (ret < 0)
+		ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
+					 "sram@70000000");
+	if (ret)
+		printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
+
+	return ret;
+}
+
+int fdt_del_node_path(void *blob, const char *path)
+{
+	int ret;
+	int nodeoff;
+
+	nodeoff = fdt_path_offset(blob, path);
+	if (nodeoff < 0)
+		return 0; /* Not found, skip it */
+
+	ret = fdt_del_node(blob, nodeoff);
+	if (ret < 0)
+		printf("Unable to delete node %s, err=%s\n", path, fdt_strerror(ret));
+	else
+		debug("Deleted node %s\n", path);
+
+	return ret;
+}
diff --git a/arch/arm/mach-k3/common_fdt.h b/arch/arm/mach-k3/common_fdt.h
new file mode 100644
index 0000000000..4d23ae638c
--- /dev/null
+++ b/arch/arm/mach-k3/common_fdt.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2023 Toradex - https://www.toradex.com/
+ */
+
+#ifndef _COMMON_FDT_H
+#define _COMMON_FDT_H
+
+int fdt_fixup_msmc_ram_k3(void *blob);
+int fdt_del_node_path(void *blob, const char *path);
+
+#endif /* _COMMON_FDT_H */
diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
deleted file mode 100644
index cbf9c10210..0000000000
--- a/arch/arm/mach-k3/config.mk
+++ /dev/null
@@ -1,103 +0,0 @@
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
-#	Lokesh Vutla <lokeshvutla@ti.com>
-
-ifdef CONFIG_SPL_BUILD
-
-# Openssl is required to generate x509 certificate.
-# Error out if openssl is not available.
-ifeq ($(shell which openssl),)
-$(error "No openssl in $(PATH), consider installing openssl")
-endif
-
-IMAGE_SIZE= $(shell cat $(obj)/u-boot-spl.bin | wc -c)
-MAX_SIZE= $(shell printf "%d" $(CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE))
-
-ifeq ($(CONFIG_SYS_K3_KEY), "")
-KEY=""
-# On HS use real key or warn if not available
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/keys/custMpk.pem),)
-KEY=$(TI_SECURE_DEV_PKG)/keys/custMpk.pem
-else
-$(warning "WARNING: signing key not found. Random key will NOT work on HS hardware!")
-endif
-endif
-else
-KEY=$(patsubst "%",$(srctree)/%,$(CONFIG_SYS_K3_KEY))
-endif
-
-# X509 SWRV default
-SWRV = $(CONFIG_K3_X509_SWRV)
-# On HS use SECDEV provided software revision or warn if not available
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/keys/swrv.txt),)
-SWRV= $(shell cat $(TI_SECURE_DEV_PKG)/keys/swrv.txt)
-else
-$(warning "WARNING: Software revision file not found. Default may not work on HS hardware.")
-endif
-endif
-
-# tiboot3.bin is mandated by ROM and ROM only supports R5 boot.
-# So restrict tiboot3.bin creation for CPU_V7R.
-ifdef CONFIG_CPU_V7R
-image_check: $(obj)/u-boot-spl.bin FORCE
-	@if [ $(IMAGE_SIZE) -gt $(MAX_SIZE) ]; then			    \
-		echo "===============================================" >&2; \
-		echo "ERROR: Final Image too big. " >&2;		    \
-		echo "$< size = $(IMAGE_SIZE), max size = $(MAX_SIZE)" >&2; \
-		echo "===============================================" >&2; \
-		exit 1;							    \
-	fi
-
-tiboot3.bin: image_check FORCE
-	$(srctree)/tools/k3_gen_x509_cert.sh -c 16 -b $(obj)/u-boot-spl.bin \
-				-o $@ -l $(CONFIG_SPL_TEXT_BASE) -r $(SWRV) -k $(KEY)
-
-INPUTS-y	+= tiboot3.bin
-endif
-
-ifdef CONFIG_ARM64
-
-ifeq ($(CONFIG_SOC_K3_J721E),)
-export DM := /dev/null
-endif
-
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-SPL_ITS := u-boot-spl-k3_HS.its
-$(SPL_ITS): export IS_HS=1
-INPUTS-y	+= tispl.bin_HS
-INPUTS-y	+= tispl.bin
-tispl.bin: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$(subst ",,$(CONFIG_SPL_OF_LIST)))
-else
-SPL_ITS := u-boot-spl-k3.its
-INPUTS-y	+= tispl.bin
-endif
-
-ifeq ($(CONFIG_SPL_OF_LIST),)
-LIST_OF_DTB := $(CONFIG_DEFAULT_DEVICE_TREE)
-else
-LIST_OF_DTB := $(CONFIG_SPL_OF_LIST)
-endif
-
-quiet_cmd_k3_mkits = MKITS   $@
-cmd_k3_mkits = \
-	$(srctree)/tools/k3_fit_atf.sh \
-	$(CONFIG_K3_ATF_LOAD_ADDR) \
-	$(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(LIST_OF_DTB))) > $@
-
-$(SPL_ITS): FORCE
-	$(call cmd,k3_mkits)
-endif
-
-else
-
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-INPUTS-y	+= u-boot.img_HS
-else
-INPUTS-y	+= u-boot.img
-endif
-endif
-
-include $(srctree)/arch/arm/mach-k3/config_secure.mk
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h
index 88d5894726..acd2d109c2 100644
--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -20,6 +20,28 @@
 #define MCU_CTRL_MMR0_BASE			0x04500000
 #define WKUP_CTRL_MMR0_BASE			0x43000000
 
+#define CTRLMMR_WKUP_JTAG_DEVICE_ID		(WKUP_CTRL_MMR0_BASE + 0x18)
+#define JTAG_DEV_ID_MASK			GENMASK(31, 18)
+#define JTAG_DEV_ID_SHIFT			18
+#define JTAG_DEV_CORE_NR_MASK			GENMASK(21, 19)
+#define JTAG_DEV_CORE_NR_SHIFT			19
+#define JTAG_DEV_GPU_MASK			BIT(18)
+#define JTAG_DEV_GPU_SHIFT			18
+#define JTAG_DEV_FEATURES_MASK			GENMASK(17, 13)
+#define JTAG_DEV_FEATURES_SHIFT			13
+#define JTAG_DEV_SECURITY_MASK			BIT(12)
+#define JTAG_DEV_SECURITY_SHIFT			12
+#define JTAG_DEV_SAFETY_MASK			BIT(11)
+#define JTAG_DEV_SAFETY_SHIFT			11
+#define JTAG_DEV_SPEED_MASK			GENMASK(10, 6)
+#define JTAG_DEV_SPEED_SHIFT			6
+#define JTAG_DEV_TEMP_MASK			GENMASK(5, 3)
+#define JTAG_DEV_TEMP_SHIFT			3
+#define JTAG_DEV_PKG_MASK			GENMASK(2, 0)
+#define JTAG_DEV_PKG_SHIFT			0
+
+#define JTAG_DEV_FEATURE_NO_PRU			0x4
+
 #define CTRLMMR_MAIN_DEVSTAT			(WKUP_CTRL_MMR0_BASE + 0x30)
 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK	GENMASK(6, 3)
 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT	3
diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c
index 0437e30abb..9b45786a2d 100644
--- a/arch/arm/mach-k3/j7200/clk-data.c
+++ b/arch/arm/mach-k3/j7200/clk-data.c
@@ -379,6 +379,7 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
 	CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
 	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
+	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out1", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c4, 0, 2, 0, 0, 48000000),
 	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
 	CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
 	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
@@ -534,6 +535,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 	DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
 	DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"),
+	DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"),
 	DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -546,7 +549,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 
 const struct ti_k3_clk_platdata j7200_clk_platdata = {
 	.clk_list = clk_list,
-	.clk_list_cnt = 108,
+	.clk_list_cnt = 109,
 	.soc_dev_clk_data = soc_dev_clk_data,
-	.soc_dev_clk_data_cnt = 127,
+	.soc_dev_clk_data_cnt = 129,
 };
diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c
index d3194ae51a..4ddc34210e 100644
--- a/arch/arm/mach-k3/j7200/dev-data.c
+++ b/arch/arm/mach-k3/j7200/dev-data.c
@@ -53,6 +53,7 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(92, &soc_lpsc_list[5]),
 	PSC_DEV(91, &soc_lpsc_list[6]),
 	PSC_DEV(146, &soc_lpsc_list[7]),
+	PSC_DEV(278, &soc_lpsc_list[7]),
 	PSC_DEV(4, &soc_lpsc_list[8]),
 	PSC_DEV(4, &soc_lpsc_list[9]),
 	PSC_DEV(202, &soc_lpsc_list[10]),
@@ -74,8 +75,8 @@ const struct ti_k3_pd_platdata j7200_pd_platdata = {
 	.pd = soc_pd_list,
 	.lpsc = soc_lpsc_list,
 	.devs = soc_dev_list,
-	.num_psc = 2,
-	.num_pd = 6,
-	.num_lpsc = 17,
-	.num_devs = 22,
+	.num_psc = ARRAY_SIZE(soc_psc_list),
+	.num_pd = ARRAY_SIZE(soc_pd_list),
+	.num_lpsc = ARRAY_SIZE(soc_lpsc_list),
+	.num_devs = ARRAY_SIZE(soc_dev_list),
 };
diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c
index 5ab795139e..e4511092c8 100644
--- a/arch/arm/mach-k3/j721e/clk-data.c
+++ b/arch/arm/mach-k3/j721e/clk-data.c
@@ -553,6 +553,7 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
 	CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
 	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
+	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0, 48000000),
 	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
 	CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0, 0),
 	CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
@@ -760,6 +761,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 	DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
 	DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(279, 0, "usart_programmable_clock_divider_out2"),
+	DEV_CLK(279, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
 	DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -780,7 +783,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 
 const struct ti_k3_clk_platdata j721e_clk_platdata = {
 	.clk_list = clk_list,
-	.clk_list_cnt = 156,
+	.clk_list_cnt = 157,
 	.soc_dev_clk_data = soc_dev_clk_data,
-	.soc_dev_clk_data_cnt = 171,
+	.soc_dev_clk_data_cnt = 173,
 };
diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c
index 300d998c62..97f017f8af 100644
--- a/arch/arm/mach-k3/j721e/dev-data.c
+++ b/arch/arm/mach-k3/j721e/dev-data.c
@@ -46,6 +46,7 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(30, &soc_lpsc_list[0]),
 	PSC_DEV(61, &soc_lpsc_list[0]),
 	PSC_DEV(146, &soc_lpsc_list[1]),
+	PSC_DEV(279, &soc_lpsc_list[1]),
 	PSC_DEV(90, &soc_lpsc_list[2]),
 	PSC_DEV(47, &soc_lpsc_list[3]),
 	PSC_DEV(288, &soc_lpsc_list[4]),
@@ -72,8 +73,8 @@ const struct ti_k3_pd_platdata j721e_pd_platdata = {
 	.pd = soc_pd_list,
 	.lpsc = soc_lpsc_list,
 	.devs = soc_dev_list,
-	.num_psc = 2,
-	.num_pd = 5,
-	.num_lpsc = 16,
-	.num_devs = 22,
+	.num_psc = ARRAY_SIZE(soc_psc_list),
+	.num_pd = ARRAY_SIZE(soc_pd_list),
+	.num_lpsc = ARRAY_SIZE(soc_lpsc_list),
+	.num_devs = ARRAY_SIZE(soc_dev_list),
 };
diff --git a/arch/arm/mach-k3/j721e_fdt.c b/arch/arm/mach-k3/j721e_fdt.c
new file mode 100644
index 0000000000..652fe8d32b
--- /dev/null
+++ b/arch/arm/mach-k3/j721e_fdt.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2023 Toradex - https://www.toradex.com/
+ */
+
+#include "common_fdt.h"
+#include <fdt_support.h>
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+	return fdt_fixup_msmc_ram_k3(blob);
+}
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 0c5d41a77e..b6164575b7 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -294,7 +294,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
 {
 	switch (boot_device) {
 	case BOOT_DEVICE_MMC1:
-		return MMCSD_MODE_EMMCBOOT;
+		return (spl_mmc_emmc_boot_partition(mmc) ? MMCSD_MODE_EMMCBOOT : MMCSD_MODE_FS);
 	case BOOT_DEVICE_MMC2:
 		return MMCSD_MODE_FS;
 	default:
diff --git a/arch/arm/mach-k3/j721s2/clk-data.c b/arch/arm/mach-k3/j721s2/clk-data.c
index ad6bd991b7..0c5c321c1e 100644
--- a/arch/arm/mach-k3/j721s2/clk-data.c
+++ b/arch/arm/mach-k3/j721s2/clk-data.c
@@ -247,6 +247,7 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0),
 	CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
 	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
+	CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0),
 	CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
 	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
 	CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0),
@@ -383,6 +384,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"),
 	DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 	DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"),
+	DEV_CLK(354, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(354, 3, "usart_programmable_clock_divider_out5"),
 	DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(357, 3, "usart_programmable_clock_divider_out8"),
 	DEV_CLK(360, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -397,7 +400,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 
 const struct ti_k3_clk_platdata j721s2_clk_platdata = {
 	.clk_list = clk_list,
-	.clk_list_cnt = 104,
+	.clk_list_cnt = 105,
 	.soc_dev_clk_data = soc_dev_clk_data,
-	.soc_dev_clk_data_cnt = 122,
+	.soc_dev_clk_data_cnt = 124,
 };
diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/j721s2/dev-data.c
index e36f1edb78..8c999a3c5a 100644
--- a/arch/arm/mach-k3/j721s2/dev-data.c
+++ b/arch/arm/mach-k3/j721s2/dev-data.c
@@ -67,6 +67,7 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(99, &soc_lpsc_list[12]),
 	PSC_DEV(98, &soc_lpsc_list[13]),
 	PSC_DEV(146, &soc_lpsc_list[14]),
+	PSC_DEV(354, &soc_lpsc_list[15]),
 	PSC_DEV(357, &soc_lpsc_list[15]),
 	PSC_DEV(4, &soc_lpsc_list[16]),
 	PSC_DEV(202, &soc_lpsc_list[17]),
@@ -78,8 +79,8 @@ const struct ti_k3_pd_platdata j721s2_pd_platdata = {
 	.pd = soc_pd_list,
 	.lpsc = soc_lpsc_list,
 	.devs = soc_dev_list,
-	.num_psc = 2,
-	.num_pd = 6,
-	.num_lpsc = 19,
-	.num_devs = 24,
+	.num_psc = ARRAY_SIZE(soc_psc_list),
+	.num_pd = ARRAY_SIZE(soc_pd_list),
+	.num_lpsc = ARRAY_SIZE(soc_lpsc_list),
+	.num_devs = ARRAY_SIZE(soc_dev_list),
 };
diff --git a/arch/arm/mach-k3/j721s2_fdt.c b/arch/arm/mach-k3/j721s2_fdt.c
new file mode 100644
index 0000000000..652fe8d32b
--- /dev/null
+++ b/arch/arm/mach-k3/j721s2_fdt.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2023 Toradex - https://www.toradex.com/
+ */
+
+#include "common_fdt.h"
+#include <fdt_support.h>
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+	return fdt_fixup_msmc_ram_k3(blob);
+}
diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 02a2c12dbd..89659f479e 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -67,14 +67,6 @@ void ti_secure_image_check_binary(void **p_image, size_t *p_size)
 
 		return;
 	}
-
-	if (get_device_type() != K3_DEVICE_TYPE_HS_SE &&
-	    !ti_secure_cert_detected(*p_image)) {
-		printf("Warning: Did not detect image signing certificate. "
-		       "Skipping authentication to prevent boot failure. "
-		       "This will fail on Security Enforcing(HS-SE) devices\n");
-		return;
-	}
 }
 
 void ti_secure_image_post_process(void **p_image, size_t *p_size)
@@ -91,9 +83,16 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size)
 		return;
 	}
 
+	if (get_device_type() == K3_DEVICE_TYPE_GP)
+		return;
+
 	if (get_device_type() != K3_DEVICE_TYPE_HS_SE &&
-	    get_device_type() != K3_DEVICE_TYPE_HS_FS)
+	    !ti_secure_cert_detected(*p_image)) {
+		printf("Warning: Did not detect image signing certificate. "
+		       "Skipping authentication to prevent boot failure. "
+		       "This will fail on Security Enforcing(HS-SE) devices\n");
 		return;
+	}
 
 	/* Clean out image so it can be seen by system firmware */
 	image_addr = dma_map_single(*p_image, *p_size, DMA_BIDIRECTIONAL);
diff --git a/arch/arm/mach-keystone/include/mach/xhci-keystone.h b/arch/arm/mach-keystone/include/mach/xhci-keystone.h
deleted file mode 100644
index 989b0c3158..0000000000
--- a/arch/arm/mach-keystone/include/mach/xhci-keystone.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * USB 3.0 DRD Controller
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- */
-
-#ifndef __ASSEMBLY__
-#include <linux/bitops.h>
-#endif
-
-#define USB3_PHY_REF_SSP_EN		BIT(29)
-#define USB3_PHY_OTG_VBUSVLDECTSEL	BIT(16)
-
-/* KEYSTONE2 XHCI PHY register structure */
-struct keystone_xhci_phy {
-	unsigned int phy_utmi;		/* ctl0 */
-	unsigned int phy_pipe;		/* ctl1 */
-	unsigned int phy_param_ctrl_1;	/* ctl2 */
-	unsigned int phy_param_ctrl_2;	/* ctl3 */
-	unsigned int phy_clock;		/* ctl4 */
-	unsigned int phy_pll;		/* ctl5 */
-};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 04aa2fd97f..8971e2d2b0 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -58,6 +58,15 @@ config TARGET_MT7986
 	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
 	  Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe.
 
+config TARGET_MT7988
+	bool "MediaTek MT7988 SoC"
+	select ARM64
+	select CPU
+	help
+	  The MediaTek MT7988 is a ARM64-based SoC with a quad-core Cortex-A73.
+	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
+	  10 Gigabit Ethernet , I2C, and PCIe.
+
 config TARGET_MT8183
 	bool "MediaTek MT8183 SoC"
 	select ARM64
@@ -104,6 +113,7 @@ config SYS_BOARD
 	default "mt7629" if TARGET_MT7629
 	default "mt7981" if TARGET_MT7981
 	default "mt7986" if TARGET_MT7986
+	default "mt7988" if TARGET_MT7988
 	default "mt8183" if TARGET_MT8183
 	default "mt8512" if TARGET_MT8512
 	default "mt8516" if TARGET_MT8516
@@ -121,6 +131,7 @@ config SYS_CONFIG_NAME
 	default "mt7629" if TARGET_MT7629
 	default "mt7981" if TARGET_MT7981
 	default "mt7986" if TARGET_MT7986
+	default "mt7988" if TARGET_MT7988
 	default "mt8183" if TARGET_MT8183
 	default "mt8512" if TARGET_MT8512
 	default "mt8516" if TARGET_MT8516
@@ -135,7 +146,7 @@ config MTK_BROM_HEADER_INFO
 	string
 	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
 	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
-	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
+	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
 	default "lk=1" if TARGET_MT7623
 
 endif
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index fc85293f71..71aa341e34 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt7623/
 obj-$(CONFIG_TARGET_MT7629) += mt7629/
 obj-$(CONFIG_TARGET_MT7981) += mt7981/
 obj-$(CONFIG_TARGET_MT7986) += mt7986/
+obj-$(CONFIG_TARGET_MT7988) += mt7988/
 obj-$(CONFIG_TARGET_MT8183) += mt8183/
 obj-$(CONFIG_TARGET_MT8516) += mt8516/
 obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c
index e501907b53..00d3eb9ce7 100644
--- a/arch/arm/mach-mediatek/mt7622/init.c
+++ b/arch/arm/mach-mediatek/mt7622/init.c
@@ -4,11 +4,15 @@
  * Author: Sam Shih <sam.shih@mediatek.com>
  */
 
-#include <common.h>
 #include <fdtdec.h>
 #include <init.h>
 #include <asm/armv8/mmu.h>
-#include <asm/cache.h>
+#include <asm/system.h>
+#include <asm/global_data.h>
+#include <asm/u-boot.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 int print_cpuinfo(void)
 {
@@ -20,11 +24,13 @@ int dram_init(void)
 {
 	int ret;
 
-	ret = fdtdec_setup_memory_banksize();
+	ret = fdtdec_setup_mem_size_base();
 	if (ret)
 		return ret;
-	return fdtdec_setup_mem_size_base();
 
+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
+
+	return 0;
 }
 
 void reset_cpu(void)
diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c
index 3c921d6ad5..862f0ca479 100644
--- a/arch/arm/mach-mediatek/mt7981/init.c
+++ b/arch/arm/mach-mediatek/mt7981/init.c
@@ -4,18 +4,25 @@
  * Author: Sam Shih <sam.shih@mediatek.com>
  */
 
-#include <cpu_func.h>
+#include <fdtdec.h>
 #include <init.h>
 #include <asm/armv8/mmu.h>
 #include <asm/system.h>
 #include <asm/global_data.h>
+#include <asm/u-boot.h>
 #include <linux/sizes.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
+	int ret;
+
+	ret = fdtdec_setup_mem_size_base();
+	if (ret)
+		return ret;
+
+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G);
 
 	return 0;
 }
diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c
index 9d0c0cdcd0..905a3ab4e2 100644
--- a/arch/arm/mach-mediatek/mt7986/init.c
+++ b/arch/arm/mach-mediatek/mt7986/init.c
@@ -4,18 +4,25 @@
  * Author: Sam Shih <sam.shih@mediatek.com>
  */
 
-#include <cpu_func.h>
+#include <fdtdec.h>
 #include <init.h>
 #include <asm/armv8/mmu.h>
 #include <asm/system.h>
 #include <asm/global_data.h>
+#include <asm/u-boot.h>
 #include <linux/sizes.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
+	int ret;
+
+	ret = fdtdec_setup_mem_size_base();
+	if (ret)
+		return ret;
+
+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
 
 	return 0;
 }
diff --git a/arch/arm/mach-mediatek/mt7988/Makefile b/arch/arm/mach-mediatek/mt7988/Makefile
new file mode 100644
index 0000000000..007eb4a367
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7988/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c
new file mode 100644
index 0000000000..082f12bf65
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7988/init.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/u-boot.h>
+#include <asm/system.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SZ_8G				_AC(0x200000000, ULL)
+
+int dram_init(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_mem_size_base();
+	if (ret)
+		return ret;
+
+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G);
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = gd->ram_base;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
+
+static struct mm_region mt7988_mem_map[] = {
+	{
+		/* DDR */
+		.virt = 0x40000000UL,
+		.phys = 0x40000000UL,
+		.size = 0x200000000ULL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+	}, {
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 0x40000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		0,
+	}
+};
+
+struct mm_region *mem_map = mt7988_mem_map;
diff --git a/arch/arm/mach-mediatek/mt7988/lowlevel_init.S b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S
new file mode 100644
index 0000000000..2ae3cc4848
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/*
+ * Switch from AArch64 EL2 to AArch32 EL2
+ * @param inputs:
+ * x0: argument, zero
+ * x1: machine nr
+ * x2: fdt address
+ * x3: input argument
+ * x4: kernel entry point
+ * @param outputs for secure firmware:
+ * x0: function id
+ * x1: kernel entry point
+ * x2: machine nr
+ * x3: fdt address
+*/
+
+.global armv8_el2_to_aarch32
+armv8_el2_to_aarch32:
+	mov     x3, x2
+	mov     x2, x1
+	mov     x1, x4
+	mov	x4, #0
+	ldr x0, =0x82000200
+	SMC #0
+	ret
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 6cba2c40dd..669ca09a00 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -51,6 +51,12 @@ config MESON_G12A
 	help
 	  Select this if your SoC is an S905X/D2
 
+config MESON_A1
+	bool "A1"
+	select MESON64_COMMON
+	help
+	  Select this if your SoC is an A113L
+
 endchoice
 
 config SYS_SOC
@@ -69,6 +75,7 @@ config SYS_VENDOR
 
 config SYS_BOARD
 	string "Board name"
+	default "ad401" if MESON_A1
 	default "p200" if MESON_GXBB
 	default "p212" if MESON_GXL
 	default "q200" if MESON_GXM
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index a9e4046f80..535b0878b9 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -6,3 +6,4 @@ obj-y += board-common.o sm.o board-info.o
 obj-$(CONFIG_MESON_GX) += board-gx.o
 obj-$(CONFIG_MESON_AXG) += board-axg.o
 obj-$(CONFIG_MESON_G12A) += board-g12a.o
+obj-$(CONFIG_MESON_A1) += board-a1.o
diff --git a/arch/arm/mach-meson/board-a1.c b/arch/arm/mach-meson/board-a1.c
new file mode 100644
index 0000000000..967bb67182
--- /dev/null
+++ b/arch/arm/mach-meson/board-a1.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 SberDevices, Inc.
+ */
+
+#include <common.h>
+#include <asm/arch/a1.h>
+#include <asm/arch/boot.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <linux/sizes.h>
+
+phys_size_t get_effective_memsize(void)
+{
+	return ((readl(A1_SYSCTRL_SEC_STATUS_REG4) & A1_SYSCTRL_MEM_SIZE_MASK)
+		>> A1_SYSCTRL_MEM_SIZE_SHIFT) * SZ_1M;
+}
+
+void meson_init_reserved_memory(__maybe_unused void *fdt)
+{
+}
+
+int meson_get_boot_device(void)
+{
+	return -ENOSYS;
+}
+
+static struct mm_region a1_mem_map[] = {
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x7FE00000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/*
+		 * This mem region contains in/out shared memory with bl31,
+		 * hence it's marked as NORMAL memory type
+		 */
+		.virt = 0xFFE00000UL,
+		.phys = 0xFFE00000UL,
+		.size = 0x00200000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = a1_mem_map;
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index f2ca7e7693..d600c64d0b 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -24,6 +24,7 @@
 #define FN_EFUSE_READ			0x82000030
 #define FN_EFUSE_WRITE			0x82000031
 #define FN_CHIP_ID			0x82000044
+#define FN_PWRDM_SET			0x82000093
 
 static void *shmem_input;
 static void *shmem_output;
@@ -137,3 +138,16 @@ int meson_sm_get_reboot_reason(void)
 	/* The SMC call is not used, we directly use AO_SEC_SD_CFG15 */
 	return FIELD_GET(REBOOT_REASON_MASK, reason);
 }
+
+int meson_sm_pwrdm_set(size_t index, int cmd)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = FN_PWRDM_SET;
+	regs.regs[1] = index;
+	regs.regs[2] = cmd;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index ac484c73f6..5c7f4bf964 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -202,6 +202,10 @@ config TARGET_X530
 	bool "Support Allied Telesis x530"
 	select 88F6820
 
+config TARGET_X240
+	bool "Support Allied Telesis x240"
+	select ALLEYCAT_5
+
 config TARGET_DB_XC3_24G4XG
 	bool "Support DB-XC3-24G4XG"
 	select 98DX3336
@@ -274,6 +278,7 @@ config SYS_BOARD
 	default "theadorable" if TARGET_THEADORABLE
 	default "a38x" if TARGET_CONTROLCENTERDC
 	default "x530" if TARGET_X530
+	default "x240" if TARGET_X240
 	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
 	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
 	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
@@ -297,6 +302,7 @@ config SYS_CONFIG_NAME
 	default "turris_mox" if TARGET_TURRIS_MOX
 	default "controlcenterdc" if TARGET_CONTROLCENTERDC
 	default "x530" if TARGET_X530
+	default "x240" if TARGET_X240
 	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
 	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
 	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
@@ -320,6 +326,7 @@ config SYS_VENDOR
 	default "CZ.NIC" if TARGET_TURRIS_MOX
 	default "gdsys" if TARGET_CONTROLCENTERDC
 	default "alliedtelesis" if TARGET_X530
+	default "alliedtelesis" if TARGET_X240
 	default "mikrotik" if TARGET_CRS3XX_98DX3236
 	default "Marvell" if TARGET_MVEBU_ALLEYCAT5
 
diff --git a/arch/arm/mach-mvebu/alleycat5/soc.c b/arch/arm/mach-mvebu/alleycat5/soc.c
index dc69f46eed..734b0a87dd 100644
--- a/arch/arm/mach-mvebu/alleycat5/soc.c
+++ b/arch/arm/mach-mvebu/alleycat5/soc.c
@@ -255,6 +255,12 @@ void soc_print_clock_info(void)
 	printf("\tMSS     %4d MHz\n", 200);
 }
 
+/* Return NAND clock in Hz */
+u32 mvebu_get_nand_clock(void)
+{
+	return 400 * 1000000;
+}
+
 /*
  * Override of __weak int mach_cpu_init(void) :
  * SoC/machine dependent CPU setup
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index d3a95730be..4c67f1aba4 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #define USABLE_RAM_SIZE		0x80000000ULL
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
 
diff --git a/arch/arm/mach-npcm/npcm8xx/cpu.c b/arch/arm/mach-npcm/npcm8xx/cpu.c
index 2d839cfae9..af59452609 100644
--- a/arch/arm/mach-npcm/npcm8xx/cpu.c
+++ b/arch/arm/mach-npcm/npcm8xx/cpu.c
@@ -68,6 +68,9 @@ int print_cpuinfo(void)
 	case ARBEL_A1:
 		printf("A1 @ ");
 		break;
+	case ARBEL_A2:
+		printf("A2 @ ");
+		break;
 	default:
 		printf("Unknown\n");
 		break;
@@ -92,7 +95,7 @@ int arch_cpu_init(void)
 	return 0;
 }
 
-static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
+static struct mm_region npcm_mem_map[] = {
 	{
 		/* DRAM */
 		.phys = 0x0UL,
@@ -110,6 +113,13 @@ static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{
+		.phys = 0x100000000UL,
+		.virt = 0x100000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	},
+	{
 		/* List terminator */
 		0,
 	}
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 309b967b0d..8465b5426d 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -77,16 +77,6 @@ config OMAP54XX
 	imply SPL_SERIAL
 	imply SYS_I2C_OMAP24XX
 
-config TI816X
-	bool "TI816X SoC"
-	select SPECIFY_CONSOLE_INDEX
-	imply NAND_OMAP_ELM
-	imply NAND_OMAP_GPMC
-	help
-	  Support for AM335x SOC from Texas Instruments.
-	  The AM335x high performance SOC features a Cortex-A8
-	  ARM core and more.
-
 config AM43XX
 	bool "AM43XX SoC"
 	select SPECIFY_CONSOLE_INDEX
@@ -203,7 +193,6 @@ source "board/BuR/brppt1/Kconfig"
 source "board/siemens/draco/Kconfig"
 source "board/siemens/pxm2/Kconfig"
 source "board/siemens/rut/Kconfig"
-source "board/ti/ti816x/Kconfig"
 source "board/ti/am43xx/Kconfig"
 source "board/ti/am335x/Kconfig"
 source "board/compulab/cm_t43/Kconfig"
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 1299aec055..8cb0c57163 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -1,13 +1,3 @@
-if TI816X
-
-config TARGET_TI816X_EVM
-	bool "Support ti816x_evm"
-	help
-	  This option specifies support for the TI8168 EVM development platform
-	  with PG2.0 silicon and DDR3 DRAM.
-
-endif
-
 if AM33XX
 
 config AM33XX_CHILISOM
diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile
index bf94d345da..2aa8013527 100644
--- a/arch/arm/mach-omap2/am33xx/Makefile
+++ b/arch/arm/mach-omap2/am33xx/Makefile
@@ -9,13 +9,11 @@ ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
 obj-y	+= clock.o
 endif
 
-obj-$(CONFIG_TI816X)	+= clock_ti816x.o
 obj-y	+= sys_info.o
 obj-y	+= ddr.o
-ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
 obj-y	+= emif4.o
 endif
-obj-$(CONFIG_TI816X)	+= ti816x_emif4.o
 obj-y	+= board.o
 obj-y	+= mux.o
 obj-y	+= prcm-regs.o
diff --git a/arch/arm/mach-omap2/am33xx/clock_ti816x.c b/arch/arm/mach-omap2/am33xx/clock_ti816x.c
deleted file mode 100644
index ec4cc75381..0000000000
--- a/arch/arm/mach-omap2/am33xx/clock_ti816x.c
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * clock_ti816x.c
- *
- * Clocks for TI816X based boards
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * Based on TI-PSP-04.00.02.14 :
- *
- * Copyright (C) 2009, Texas Instruments, Incorporated
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-
-#include <asm/emif.h>
-
-#define CM_PLL_BASE		(CTRL_BASE + 0x0400)
-
-/* Main PLL */
-#define MAIN_N			64
-#define MAIN_P			0x1
-#define MAIN_INTFREQ1		0x8
-#define MAIN_FRACFREQ1		0x800000
-#define MAIN_MDIV1		0x2
-#define MAIN_INTFREQ2		0xE
-#define MAIN_FRACFREQ2		0x0
-#define MAIN_MDIV2		0x1
-#define MAIN_INTFREQ3		0x8
-#define MAIN_FRACFREQ3		0xAAAAB0
-#define MAIN_MDIV3		0x3
-#define MAIN_INTFREQ4		0x9
-#define MAIN_FRACFREQ4		0x55554F
-#define MAIN_MDIV4		0x3
-#define MAIN_INTFREQ5		0x9
-#define MAIN_FRACFREQ5		0x374BC6
-#define MAIN_MDIV5		0xC
-#define MAIN_MDIV6		0x48
-#define MAIN_MDIV7		0x4
-
-/* DDR PLL */
-#define DDR_N			59
-#define DDR_P			0x1
-#define DDR_MDIV1		0x2
-#define DDR_INTFREQ2		0x8
-#define DDR_FRACFREQ2		0xD99999
-#define DDR_MDIV2		0x1E
-#define DDR_INTFREQ3		0x8
-#define DDR_FRACFREQ3		0x0
-#define DDR_MDIV3		0x4
-#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ4		0x0
-#define DDR_MDIV4		0x4
-#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ5		0x0
-#define DDR_MDIV5		0x4
-
-#define CONTROL_STATUS			(CTRL_BASE + 0x40)
-#define DDR_RCD				(CTRL_BASE + 0x070C)
-#define CM_TIMER1_CLKSEL		(PRCM_BASE + 0x390)
-#define CM_ALWON_CUST_EFUSE_CLKCTRL	(PRCM_BASE + 0x1628)
-
-#define INTCPS_SYSCONFIG	0x48200010
-#define CM_SYSCLK10_CLKSEL	0x48180324
-
-struct cm_pll {
-	unsigned int mainpll_ctrl;	/* offset 0x400 */
-	unsigned int mainpll_pwd;
-	unsigned int mainpll_freq1;
-	unsigned int mainpll_div1;
-	unsigned int mainpll_freq2;
-	unsigned int mainpll_div2;
-	unsigned int mainpll_freq3;
-	unsigned int mainpll_div3;
-	unsigned int mainpll_freq4;
-	unsigned int mainpll_div4;
-	unsigned int mainpll_freq5;
-	unsigned int mainpll_div5;
-	unsigned int resv0[1];
-	unsigned int mainpll_div6;
-	unsigned int resv1[1];
-	unsigned int mainpll_div7;
-	unsigned int ddrpll_ctrl;	/* offset 0x440 */
-	unsigned int ddrpll_pwd;
-	unsigned int resv2[1];
-	unsigned int ddrpll_div1;
-	unsigned int ddrpll_freq2;
-	unsigned int ddrpll_div2;
-	unsigned int ddrpll_freq3;
-	unsigned int ddrpll_div3;
-	unsigned int ddrpll_freq4;
-	unsigned int ddrpll_div4;
-	unsigned int ddrpll_freq5;
-	unsigned int ddrpll_div5;
-	unsigned int videopll_ctrl;	/* offset 0x470 */
-	unsigned int videopll_pwd;
-	unsigned int videopll_freq1;
-	unsigned int videopll_div1;
-	unsigned int videopll_freq2;
-	unsigned int videopll_div2;
-	unsigned int videopll_freq3;
-	unsigned int videopll_div3;
-	unsigned int resv3[4];
-	unsigned int audiopll_ctrl;	/* offset 0x4A0 */
-	unsigned int audiopll_pwd;
-	unsigned int resv4[2];
-	unsigned int audiopll_freq2;
-	unsigned int audiopll_div2;
-	unsigned int audiopll_freq3;
-	unsigned int audiopll_div3;
-	unsigned int audiopll_freq4;
-	unsigned int audiopll_div4;
-	unsigned int audiopll_freq5;
-	unsigned int audiopll_div5;
-};
-
-const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
-const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
-const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
-const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
-void enable_dmm_clocks(void)
-{
-	writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
-	/* Wait for dmm to be fully functional, including OCP */
-	while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
-		;
-}
-
-void enable_emif_clocks(void)
-{
-	writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
-	writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
-	writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
-	writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
-
-	/* Wait for clocks to be active */
-	while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
-		;
-	/* Wait for emif0 to be fully functional, including OCP */
-	while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
-		;
-	/* Wait for emif1 to be fully functional, including OCP */
-	while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
-		;
-}
-
-/* assume delay is aprox at least 1us */
-static void ddr_delay(int d)
-{
-	int i;
-
-	/*
-	 * read a control register.
-	 * this is a bit more delay and cannot be optimized by the compiler
-	 * assuming one read takes 200 cycles and A8 is runing 1 GHz
-	 * somewhat conservative setting
-	 */
-	for (i = 0; i < 50*d; i++)
-		readl(CONTROL_STATUS);
-}
-
-static void main_pll_init_ti816x(void)
-{
-	u32 main_pll_ctrl = 0;
-
-	/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
-	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
-	main_pll_ctrl &= 0xFFFFFFFB;
-	main_pll_ctrl |= BIT(2);
-	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
-	/* Enable PLL by setting BIT3 in its ctrl reg */
-	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
-	main_pll_ctrl &= 0xFFFFFFF7;
-	main_pll_ctrl |= BIT(3);
-	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
-	/* Write the values of N,P in the CTRL reg  */
-	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
-	main_pll_ctrl &= 0xFF;
-	main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
-	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
-	/* Power up clock1-7 */
-	writel(0x0, &cmpll->mainpll_pwd);
-
-	/* Program the freq and divider values for clock1-7 */
-	writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
-		&cmpll->mainpll_freq1);
-	writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
-
-	writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
-		&cmpll->mainpll_freq2);
-	writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
-
-	writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
-		&cmpll->mainpll_freq3);
-	writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
-
-	writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
-		&cmpll->mainpll_freq4);
-	writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
-
-	writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
-		&cmpll->mainpll_freq5);
-	writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
-
-	writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
-
-	writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
-
-	/* Wait for PLL to lock */
-	while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
-		;
-
-	/* Put the PLL in normal mode, disable bypass */
-	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
-	main_pll_ctrl &= 0xFFFFFFFB;
-	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-}
-
-static void ddr_pll_bypass_ti816x(void)
-{
-	u32 ddr_pll_ctrl = 0;
-
-	/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
-	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
-	ddr_pll_ctrl &= 0xFFFFFFFB;
-	ddr_pll_ctrl |= BIT(2);
-	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-}
-
-static void ddr_pll_init_ti816x(void)
-{
-	u32 ddr_pll_ctrl = 0;
-	/* Enable PLL by setting BIT3 in its ctrl reg */
-	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
-	ddr_pll_ctrl &= 0xFFFFFFF7;
-	ddr_pll_ctrl |= BIT(3);
-	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-
-	/* Write the values of N,P in the CTRL reg  */
-	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
-	ddr_pll_ctrl &= 0xFF;
-	ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
-	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-
-	ddr_delay(10);
-
-	/* Power up clock1-5 */
-	writel(0x0, &cmpll->ddrpll_pwd);
-
-	/* Program the freq and divider values for clock1-3 */
-	writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
-	ddr_delay(1);
-	writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
-	writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
-		&cmpll->ddrpll_freq2);
-	writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
-	writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
-	ddr_delay(1);
-	writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
-	ddr_delay(1);
-	writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
-		&cmpll->ddrpll_freq3);
-	ddr_delay(1);
-	writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
-		&cmpll->ddrpll_freq3);
-
-	ddr_delay(5);
-
-	/* Wait for PLL to lock */
-	while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
-		;
-
-	/* Power up RCD */
-	writel(BIT(0), DDR_RCD);
-}
-
-static void peripheral_enable(void)
-{
-	/* Wake-up the l3_slow clock */
-	writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
-
-	/*
-	 * Note on Timers:
-	 * There are 8 timers(0-7) out of which timer 0 is a secure timer.
-	 * Timer 0 mux should not be changed
-	 *
-	 * To access the timer registers we need the to be
-	 * enabled which is what we do in the first step
-	 */
-
-	/* Enable timer1 */
-	writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
-	/* Select timer1 clock to be CLKIN (27MHz) */
-	writel(BIT(1), CM_TIMER1_CLKSEL);
-
-	/* Wait for timer1 to be ON-ACTIVE */
-	while (((readl(&cmalwon->l3slowclkstctrl)
-					& (0x80000<<1))>>20) != 1)
-		;
-	/* Wait for timer1 to be enabled */
-	while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
-		;
-	/* Active posted mode */
-	writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
-	while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
-		;
-	/* Start timer1  */
-	writel(BIT(0), (DM_TIMER1_BASE + 0x38));
-
-	/* eFuse */
-	writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
-	while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
-		;
-
-	/* Enable gpio0 */
-	writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
-	while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
-		;
-	writel((BIT(1) | BIT(8)), &cmalwon->gpio0clkctrl);
-
-	/* Enable gpio1 */
-	writel(PRCM_MOD_EN, &cmalwon->gpio1clkctrl);
-	while (readl(&cmalwon->gpio1clkctrl) != PRCM_MOD_EN)
-		;
-	writel((BIT(1) | BIT(8)), &cmalwon->gpio1clkctrl);
-
-	/* Enable spi */
-	writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
-	while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* Enable i2c0 */
-	writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
-	while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* Enable ethernet0 */
-	writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
-	writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
-	writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
-
-	/* Enable hsmmc */
-	writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
-	while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
-		;
-}
-
-void setup_clocks_for_console(void)
-{
-	/* Fix ROM code bug - from TI-PSP-04.00.02.14 */
-	writel(0x0, CM_SYSCLK10_CLKSEL);
-
-	ddr_pll_bypass_ti816x();
-
-	/* Enable uart0-2 */
-	writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
-	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
-		;
-	writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
-	while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
-		;
-	writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
-	while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
-		;
-	while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
-		;
-}
-
-void setup_early_clocks(void)
-{
-	setup_clocks_for_console();
-}
-
-void prcm_init(void)
-{
-	/* Enable the control */
-	writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
-
-	main_pll_init_ti816x();
-	ddr_pll_init_ti816x();
-
-	/*
-	 * With clk freqs setup to desired values,
-	 * enable the required peripherals
-	 */
-	peripheral_enable();
-}
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
index f8434ecf57..5f970d93f0 100644
--- a/arch/arm/mach-omap2/am33xx/ddr.c
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -182,14 +182,6 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
  */
 void config_sdram(const struct emif_regs *regs, int nr)
 {
-#ifdef CONFIG_TI816X
-	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
-	writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* initially a large refresh period */
-	writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* trigger initialization           */
-	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
-#else
 	if (regs->zq_config) {
 		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
@@ -211,7 +203,6 @@ void config_sdram(const struct emif_regs *regs, int nr)
 	/* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
 	if (regs->ocp_config)
 		writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
-#endif
 }
 
 /**
diff --git a/arch/arm/mach-omap2/am33xx/ti816x_emif4.c b/arch/arm/mach-omap2/am33xx/ti816x_emif4.c
deleted file mode 100644
index 707ea807ac..0000000000
--- a/arch/arm/mach-omap2/am33xx/ti816x_emif4.c
+++ /dev/null
@@ -1,165 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * ti816x_emif4.c
- *
- * TI816x emif4 configuration file
- *
- * Copyright (C) 2017, Konsulko Group
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <linux/delay.h>
-
-/*********************************************************************
- * Init DDR3 on TI816X EVM
- *********************************************************************/
-static void ddr_init_settings(const struct cmd_control *ctrl, int emif)
-{
-	/*
-	 * setup use_rank_delays to 1.  This is only necessary when
-	 * multiple ranks are in use.  Though the EVM does not have
-	 * multiple ranks, this is a good value to set.
-	 */
-	writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS
-	writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS
-	writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS
-	writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS
-
-	config_cmd_ctrl(ctrl, emif);
-
-	/* for ddr3 this needs to be set to 1 */
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x104);
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x19C);
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8);
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x240);
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x24C);
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4);
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0);
-
-	/*
-	 * This represents the initial value for the leveling process.  The
-	 * value is a ratio - so 0x100 represents one cycle.  The real delay
-	 * is determined through the leveling process.
-	 *
-	 * During the leveling process, 0x20 is subtracted from the value, so
-	 * we have added that to the value we want to set.  We also set the
-	 * values such that byte3 completes leveling after byte2 and byte1
-	 * after byte0.
-	 */
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0F0); /*  data0 writelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x0F4);   /*   */
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x194); /*  data1 writelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x198);   /*   */
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x238); /*  data2 writelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x23c);   /*   */
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2dc); /*  data3 writelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x2e0);   /*   */
-
-
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0FC); /*  data0 gatelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x100);
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x1A0); /*  data1 gatelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4);
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x244); /*  data2 gatelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x248);
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2E8); /*  data3 gatelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC);
-
-	writel(0x5, DDRPHY_CONFIG_BASE + 0x00C);     /* cmd0 io config - output impedance of pad */
-	writel(0x5, DDRPHY_CONFIG_BASE + 0x010);     /* cmd0 io clk config - output impedance of pad */
-	writel(0x5, DDRPHY_CONFIG_BASE + 0x040);     /* cmd1 io config - output impedance of pad */
-	writel(0x5, DDRPHY_CONFIG_BASE + 0x044);     /* cmd1 io clk config - output impedance of pad */
-	writel(0x5, DDRPHY_CONFIG_BASE + 0x074);     /* cmd2 io config - output impedance of pad */
-	writel(0x5, DDRPHY_CONFIG_BASE + 0x078);     /* cmd2 io clk config - output impedance of pad */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8);     /* data0 io config - output impedance of pad */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC);     /* data0 io clk config - output impedance of pad */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x14C);     /* data1 io config - output impedance of pa     */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x150);     /* data1 io clk config - output impedance of pad */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0);     /* data2 io config - output impedance of pa */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4);     /* data2 io clk config - output impedance of pad */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x294);     /* data3 io config - output impedance of pa */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x298);     /* data3 io clk config - output impedance of pad */
-}
-
-static void ddr3_sw_levelling(const struct ddr_data *data, int emif)
-{
-	/* Set the correct value to DDR_VTP_CTRL_0 */
-	writel(0x6, (DDRPHY_CONFIG_BASE + 0x358));
-
-	writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x108));
-	writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x1AC));
-	writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x250));
-	writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x2F4));
-
-	writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x0DC));
-	writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x180));
-	writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x224));
-	writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x2C8));
-
-	writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x120));
-	writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x1C4));
-	writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x268));
-	writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x30C));
-
-	writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x0C8));
-	writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x16C));
-	writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x210));
-	writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x2B4));
-}
-
-static struct dmm_lisa_map_regs *hw_lisa_map_regs =
-				(struct dmm_lisa_map_regs *)DMM_BASE;
-
-#define DMM_PAT_BASE_ADDR		(DMM_BASE + 0x420)
-void config_dmm(const struct dmm_lisa_map_regs *regs)
-{
-	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
-	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
-	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
-	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
-
-	writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
-	writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
-	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
-	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
-
-	/* Enable Tiled Access */
-	writel(0x80000000, DMM_PAT_BASE_ADDR);
-}
-
-void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
-		const struct emif_regs *regs,
-		const struct dmm_lisa_map_regs *lisa_regs, int nrs)
-{
-	int i;
-
-	enable_emif_clocks();
-
-	for (i = 0; i < nrs; i++)
-		ddr_init_settings(ctrl, i);
-
-	enable_dmm_clocks();
-
-	/* Program the DMM to for non-interleaved configuration */
-	config_dmm(lisa_regs);
-
-	/* Program EMIF CFG Registers */
-	for (i = 0; i < nrs; i++) {
-		set_sdram_timings(regs, i);
-		config_sdram(regs, i);
-	}
-
-	udelay(1000);
-	for (i = 0; i < nrs; i++)
-		ddr3_sw_levelling(data, i);
-
-	udelay(50000);	/* Some delay needed */
-}
diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c
index 9a342a1bf9..a2dd5f6df0 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -75,23 +75,6 @@ void save_omap_boot_params(void)
 	if (boot_device == BOOT_DEVICE_QSPI_4)
 		boot_device = BOOT_DEVICE_SPI;
 #endif
-#ifdef CONFIG_TI816X
-	/*
-	 * On PG2.0 and later TI816x the values we get when booting are not the
-	 * same as on PG1.0, which is what the defines are based on.  Update
-	 * them as needed.
-	 */
-	if (get_cpu_rev() != 1) {
-		if (boot_device == 0x05) {
-			omap_boot_params->boot_device = BOOT_DEVICE_NAND;
-			boot_device = BOOT_DEVICE_NAND;
-		}
-		if (boot_device == 0x08) {
-			omap_boot_params->boot_device = BOOT_DEVICE_MMC1;
-			boot_device = BOOT_DEVICE_MMC1;
-		}
-	}
-#endif
 	/*
 	 * When booting from peripheral booting, the boot device is not usable
 	 * as-is (unless there is support for it), so the boot device is instead
@@ -183,8 +166,7 @@ void save_omap_boot_params(void)
 
 	gd->arch.omap_boot_mode = boot_mode;
 
-#if !defined(CONFIG_TI816X) && \
-    !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
+#if !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
 
 	/* CH flags */
 
diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c
index a6a97af37d..9daaeef731 100644
--- a/arch/arm/mach-omap2/emif-common.c
+++ b/arch/arm/mach-omap2/emif-common.c
@@ -40,7 +40,7 @@ void set_lpmode_selfrefresh(u32 base)
 	readl(&emif->emif_pwr_mgmt_ctrl);
 }
 
-void force_emif_self_refresh()
+void force_emif_self_refresh(void)
 {
 	set_lpmode_selfrefresh(EMIF1_BASE);
 	if (!is_dra72x())
diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c
index 6e6791fc65..7d938724f8 100644
--- a/arch/arm/mach-omap2/utils.c
+++ b/arch/arm/mach-omap2/utils.c
@@ -100,8 +100,7 @@ static u32 omap_mmc_get_part_size(const char *part)
 		return 0;
 	}
 
-	/* Check only for EFI (GPT) partition table */
-	res = part_get_info_by_name_type(dev_desc, part, &info, PART_TYPE_EFI);
+	res = part_get_info_by_name(dev_desc, part, &info);
 	if (res < 0)
 		return 0;
 
diff --git a/arch/arm/mach-rmobile/Kconfig.rcar3 b/arch/arm/mach-rmobile/Kconfig.rcar3
index 5f338219b4..ad35d1058f 100644
--- a/arch/arm/mach-rmobile/Kconfig.rcar3
+++ b/arch/arm/mach-rmobile/Kconfig.rcar3
@@ -99,6 +99,11 @@ config TARGET_CONDOR
 	help
           Support for Renesas R-Car Gen3 Condor platform
 
+config TARGET_V3HSK
+	bool "V3HSK board"
+	help
+          Support for Renesas R-Car Gen3 V3HSK platform
+
 config TARGET_DRAAK
 	bool "Draak board"
 	imply R8A77995
@@ -111,6 +116,11 @@ config TARGET_EAGLE
 	help
           Support for Renesas R-Car Gen3 Eagle platform
 
+config TARGET_V3MSK
+	bool "V3MSK board"
+	help
+          Support for Renesas R-Car Gen3 V3MSK platform
+
 config TARGET_EBISU
 	bool "Ebisu board"
 	imply R8A77990
@@ -166,6 +176,8 @@ source "board/renesas/eagle/Kconfig"
 source "board/renesas/ebisu/Kconfig"
 source "board/renesas/salvator-x/Kconfig"
 source "board/renesas/ulcb/Kconfig"
+source "board/renesas/v3hsk/Kconfig"
+source "board/renesas/v3msk/Kconfig"
 source "board/beacon/beacon-rzg2m/Kconfig"
 source "board/hoperun/hihope-rzg2/Kconfig"
 source "board/silinux/ek874/Kconfig"
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 9d6d20bf8e..a279582f4f 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -106,6 +106,7 @@ config ROCKCHIP_RK322X
 	imply ROCKCHIP_COMMON_BOARD
 	imply SPL_SERIAL
 	imply SPL_ROCKCHIP_COMMON_BOARD
+	select SPL_OPTEE_IMAGE if SPL_FIT
 	imply TPL_SERIAL
 	imply TPL_ROCKCHIP_COMMON_BOARD
 	select TPL_LIBCOMMON_SUPPORT
@@ -152,7 +153,6 @@ config ROCKCHIP_RK3288
 config ROCKCHIP_RK3308
 	bool "Support Rockchip RK3308"
 	select ARM64
-	select DEBUG_UART_BOARD_INIT
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select SPL
@@ -250,7 +250,6 @@ config ROCKCHIP_RK3399
 	imply PRE_CONSOLE_BUFFER
 	imply ROCKCHIP_COMMON_BOARD
 	imply ROCKCHIP_SDRAM_COMMON
-	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
 	imply SPL_ROCKCHIP_COMMON_BOARD
 	imply TPL_SERIAL
 	imply TPL_LIBCOMMON_SUPPORT
@@ -360,6 +359,7 @@ config ROCKCHIP_RV1126
 	select PMIC_RK8XX
 	select BOARD_LATE_INIT
 	imply ROCKCHIP_COMMON_BOARD
+	imply OF_LIBFDT_OVERLAY
 	imply TPL_DM
 	imply TPL_LIBCOMMON_SUPPORT
 	imply TPL_LIBGENERIC_SUPPORT
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 45d9eae870..8d7b39ba15 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -41,7 +41,7 @@ static bool updatable_image(struct disk_partition *info)
 	uuid_str_to_bin(info->type_guid, image_type_guid.b,
 			UUID_STR_FORMAT_GUID);
 
-	for (i = 0; i < num_image_type_guids; i++) {
+	for (i = 0; i < update_info.num_images; i++) {
 		if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) {
 			ret = true;
 			break;
@@ -59,7 +59,7 @@ static void set_image_index(struct disk_partition *info, int index)
 	uuid_str_to_bin(info->type_guid, image_type_guid.b,
 			UUID_STR_FORMAT_GUID);
 
-	for (i = 0; i < num_image_type_guids; i++) {
+	for (i = 0; i < update_info.num_images; i++) {
 		if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) {
 			fw_images[i].image_index = index;
 			break;
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index ea94ad1142..69a5614b44 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -16,7 +16,9 @@ config TARGET_CHROMEBOOK_JERRY
 
 config TARGET_CHROMEBIT_MICKEY
 	bool "Google/Rockchip Veyron-Mickey Chromebit"
+	select HAS_ROM
 	select BOARD_LATE_INIT
+	select ROCKCHIP_SPI_IMAGE
 	help
 	  Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
 	  and WiFi. It has a separate power port and is designed to connect
@@ -26,7 +28,9 @@ config TARGET_CHROMEBIT_MICKEY
 
 config TARGET_CHROMEBOOK_MINNIE
 	bool "Google/Rockchip Veyron-Minnie Chromebook"
+	select HAS_ROM
 	select BOARD_LATE_INIT
+	select ROCKCHIP_SPI_IMAGE
 	help
 	  Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
 	  ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
@@ -37,7 +41,9 @@ config TARGET_CHROMEBOOK_MINNIE
 
 config TARGET_CHROMEBOOK_SPEEDY
 	bool "Google/Rockchip Veyron-Speedy Chromebook"
+	select HAS_ROM
 	select BOARD_LATE_INIT
+	select ROCKCHIP_SPI_IMAGE
 	help
 	  Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports,
 	  micro HDMI, an 11.6 inch display, micro-SD card,
diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c
index dd9109b7c3..5763604dc3 100644
--- a/arch/arm/mach-rockchip/rk3308/rk3308.c
+++ b/arch/arm/mach-rockchip/rk3308/rk3308.c
@@ -174,7 +174,7 @@ int rk_board_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_DEBUG_UART)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
 __weak void board_debug_uart_init(void)
 {
 	static struct rk3308_grf * const grf = (void *)GRF_BASE;
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index a7cc91a952..cbd2ea047d 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -280,15 +280,5 @@ void spl_board_init(void)
 		if (cru->glb_rst_st != 0)
 			rk3399_force_power_on_reset();
 	}
-
-	if (IS_ENABLED(CONFIG_SPL_DM_REGULATOR)) {
-		/*
-		 * Turning the eMMC and SPI back on (if disabled via the Qseven
-		 * BIOS_ENABLE) signal is done through a always-on regulator).
-		 */
-		if (regulators_enable_boot_on(false))
-			debug("%s: Cannot enable boot on regulator\n",
-			      __func__);
-	}
 }
 #endif
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig
index 94e04b79e7..baa51349f4 100644
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -17,6 +17,16 @@ config TARGET_ANBERNIC_RGXX3_RK3566
 	  and RG503. The correct device tree name will automatically
 	  be selected by the bootloader.
 
+config TARGET_ODROID_M1_RK3568
+	bool "ODROID-M1"
+	help
+	  Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC.
+
+config TARGET_QUARTZ64_RK3566
+	bool "Pine64 Quartz64"
+	help
+	  Pine64 Quartz64 single board computer with a RK3566 SoC.
+
 endchoice
 
 config ROCKCHIP_BOOT_MODE_REG
@@ -29,9 +39,11 @@ config SYS_SOC
 	default "rk3568"
 
 config SYS_MALLOC_F_LEN
-	default 0x2000
+	default 0x20000
 
 source "board/rockchip/evb_rk3568/Kconfig"
 source "board/anbernic/rgxx3_rk3566/Kconfig"
+source "board/hardkernel/odroid_m1/Kconfig"
+source "board/pine64/quartz64_rk3566/Kconfig"
 
 endif
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index 3596b82f1f..79fcc99b89 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -10,14 +10,50 @@ config TARGET_RK3588_NEU6
 	bool "Edgeble Neural Compute Module 6(Neu6) SoM"
 	select BOARD_LATE_INIT
 	help
-	  Neu6:
-	  Neural Compute Module 6A(Neu6a) is a 96boards SoM-CB compute module
+	  Neu6A:
+	  Neural Compute Module 6A(Neu6A) is a 96boards SoM-CB compute module
 	  based on Rockchip RK3588 from Edgeble AI.
 
-	  Neu6-IO:
-	  Neural Compute Module 6(Neu6) IO board is an industrial form factor
+	  Neu6A-IO:
+	  Neural Compute Module 6A(Neu6A) IO board is an industrial form factor
 	  IO board and Neu6a needs to mount on top of this IO board in order to
-	  create complete Edgeble Neural Compute Module 6(Neu6) IO platform.
+	  create complete Edgeble Neural Compute Module 6A(Neu6A) IO platform.
+
+	  Neu6B:
+	  Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module
+	  based on Rockchip RK3588J from Edgeble AI.
+
+	  Neu6A-IO:
+	  Neural Compute Module 6B(Neu6B) IO board is an industrial form factor
+	  IO board and Neu6a needs to mount on top of this IO board in order to
+	  create complete Edgeble Neural Compute Module 6B(Neu6B) IO platform.
+
+config TARGET_ROCK5A_RK3588
+	bool "Radxa ROCK5A RK3588 board"
+	select BOARD_LATE_INIT
+	help
+	  Radxa ROCK5A is a Rockchip RK3588S based SBC (Single Board Computer)
+	  by Radxa.
+
+	  There are tree variants depending on the DRAM size : 4G, 8G and 16G.
+
+	  Specification:
+
+	  Rockchip Rk3588S SoC
+	  4x ARM Cortex-A76, 4x ARM Cortex-A55
+	  4/8/16GB memory LPDDR4x
+	  Mali G610MC4 GPU
+	  MIPI CSI 2 multiple lanes connector
+	  4-lane MIPI DSI connector
+	  Audio – 3.5mm earphone jack
+	  eMMC module connector
+	  uSD slot (up to 128GB)
+	  2x USB 2.0, 2x USB 3.0
+	  2x micro HDMI 2.1 ports, one up to 8Kp60, the other up to 4Kp60
+	  Gigabit Ethernet RJ45 with optional PoE support
+	  40-pin IO header including UART, SPI, I2C and 5V DC power in
+	  USB PD over USB Type-C
+	  Size: 85mm x 56mm (Raspberry Pi 4 form factor)
 
 config TARGET_ROCK5B_RK3588
 	bool "Radxa ROCK5B RK3588 board"
@@ -34,15 +70,15 @@ config TARGET_ROCK5B_RK3588
 	  4x ARM Cortex-A76, 4x ARM Cortex-A55
 	  4/8/16GB memory LPDDR4x
 	  Mali G610MC4 GPU
-	  MIPI CSI 2 multiple lanes connector
+	  2x MIPI CSI 2 multiple lanes connector
 	  eMMC module connector
 	  uSD slot (up to 128GB)
-	  2x USB 2.0, 2x USB 3.0
-	  2x HDMI output, 1x HDMI input
-	  Ethernet port
+	  2x USB 2.0 Type-A, 2x USB 3.0 Type-A, 1x USB 3.0 Type-C
+	  2x HDMI 2.1 output, 1x micro HDMI input
+	  2.5 Gbps Ethernet port
 	  40-pin IO header including UART, SPI, I2C and 5V DC power in
 	  USB PD over USB Type-C
-	  Size: 85mm x 54mm
+	  Size: 100mm x 72mm (Pico-ITX form factor)
 
 config ROCKCHIP_BOOT_MODE_REG
 	default 0xfd588080
@@ -58,6 +94,7 @@ config SYS_MALLOC_F_LEN
 
 source board/edgeble/neural-compute-module-6/Kconfig
 source board/rockchip/evb_rk3588/Kconfig
+source board/radxa/rock5a-rk3588s/Kconfig
 source board/radxa/rock5b-rk3588/Kconfig
 
 endif
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 1d17a740ad..99ecbdc341 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -216,7 +216,7 @@ int dram_init(void)
 	return 0;
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
 
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index 30be640425..87280e2ba7 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -112,19 +112,6 @@ void board_init_f(ulong dummy)
 {
 	int ret;
 
-#ifdef CONFIG_DEBUG_UART
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug_uart_init();
-	debug("\nspl:debug uart enabled in %s\n", __func__);
-#endif
-
 	board_early_init_f();
 
 	ret = spl_early_init();
diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c
index f5f4b20d47..0dc1e5c3fd 100644
--- a/arch/arm/mach-stm32mp/bsec.c
+++ b/arch/arm/mach-stm32mp/bsec.c
@@ -622,7 +622,7 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset,
 		shadow = false;
 	}
 
-	if ((offs % 4) || (size % 4))
+	if ((offs % 4) || (size % 4) || !size)
 		return -EINVAL;
 
 	if (IS_ENABLED(CONFIG_OPTEE) && priv->tee) {
@@ -678,7 +678,7 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset,
 		shadow = false;
 	}
 
-	if ((offs % 4) || (size % 4))
+	if ((offs % 4) || (size % 4) || !size)
 		return -EINVAL;
 
 	if (IS_ENABLED(CONFIG_OPTEE) && priv->tee) {
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
index cfafa539ae..c695cc1123 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
@@ -180,15 +180,6 @@ U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog,
 	   "  <size> = size of flashlayout (optional for image with STM32 header)\n"
 );
 
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-bool stm32prog_get_tee_partitions(void)
-{
-	if (stm32prog_data)
-		return stm32prog_data->tee_detected;
-
-	return false;
-}
-#endif
 
 bool stm32prog_get_fsbl_nor(void)
 {
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
index 6f3641ccf5..9ba94be804 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
@@ -63,6 +63,12 @@ static const efi_guid_t uuid_mmc[3] = {
 	ROOTFS_MMC2_UUID
 };
 
+/*
+ * GUID value defined in the FWU specification for identification
+ * of the FWU metadata partition.
+ */
+#define FWU_MDATA_UUID "8a7a84a0-8387-40f6-ab41-a8b9a5a60d23"
+
 /* FIP type partition UUID used by TF-A*/
 #define FIP_TYPE_UUID "19D5DF83-11B0-457B-BE2C-7559C13142A5"
 
@@ -208,11 +214,6 @@ static int optee_ta_invoke(struct stm32prog_data *data, int cmd, int type,
 	return rc;
 }
 
-/* partition handling routines : CONFIG_CMD_MTDPARTS */
-int mtdparts_init(void);
-int find_dev_and_part(const char *id, struct mtd_device **dev,
-		      u8 *part_num, struct part_info **part);
-
 char *stm32prog_get_error(struct stm32prog_data *data)
 {
 	static const char error_msg[] = "Unspecified";
@@ -430,8 +431,14 @@ static int parse_type(struct stm32prog_data *data,
 		}
 	} else if (!strcmp(p, "FIP")) {
 		part->part_type = PART_FIP;
+	} else if (!strcmp(p, "FWU_MDATA")) {
+		part->part_type = PART_FWU_MDATA;
+	} else if (!strcmp(p, "ENV")) {
+		part->part_type = PART_ENV;
 	} else if (!strcmp(p, "System")) {
 		part->part_type = PART_SYSTEM;
+	} else if (!strcmp(p, "ESP")) {
+		part->part_type = PART_ESP;
 	} else if (!strcmp(p, "FileSystem")) {
 		part->part_type = PART_FILESYSTEM;
 	} else if (!strcmp(p, "RawImage")) {
@@ -514,7 +521,7 @@ static int parse_offset(struct stm32prog_data *data,
 			stm32prog_err("Layout line %d: invalid part '%s'",
 				      i, p);
 	} else {
-		part->addr = simple_strtoull(p, &tail, 0);
+		part->addr = simple_strtoull(p, &tail, 10);
 		if (tail == p || *tail != '\0') {
 			stm32prog_err("Layout line %d: invalid offset '%s'",
 				      i, p);
@@ -741,6 +748,7 @@ static int init_device(struct stm32prog_data *data,
 	struct mmc *mmc = NULL;
 	struct blk_desc *block_dev = NULL;
 	struct mtd_info *mtd = NULL;
+	struct mtd_info *partition;
 	char mtd_id[16];
 	int part_id;
 	int ret;
@@ -749,6 +757,7 @@ static int init_device(struct stm32prog_data *data,
 	u64 part_addr, part_size;
 	bool part_found;
 	const char *part_name;
+	u8 i;
 
 	switch (dev->target) {
 	case STM32PROG_MMC:
@@ -793,10 +802,11 @@ static int init_device(struct stm32prog_data *data,
 			stm32prog_err("unknown device type = %d", dev->target);
 			return -ENODEV;
 		}
+		/* register partitions with MTDIDS/MTDPARTS or OF fallback */
+		mtd_probe_devices();
 		get_mtd_by_target(mtd_id, dev->target, dev->dev_id);
 		log_debug("%s\n", mtd_id);
 
-		mtdparts_init();
 		mtd = get_mtd_device_nm(mtd_id);
 		if (IS_ERR(mtd)) {
 			stm32prog_err("MTD device %s not found", mtd_id);
@@ -943,25 +953,23 @@ static int init_device(struct stm32prog_data *data,
 		}
 
 		if (IS_ENABLED(CONFIG_MTD) && mtd) {
-			char mtd_part_id[32];
-			struct part_info *mtd_part;
-			struct mtd_device *mtd_dev;
-			u8 part_num;
-
-			sprintf(mtd_part_id, "%s,%d", mtd_id,
-				part->part_id - 1);
-			ret = find_dev_and_part(mtd_part_id, &mtd_dev,
-						&part_num, &mtd_part);
-			if (ret != 0) {
-				stm32prog_err("%s (0x%x): Invalid MTD partition %s",
-					      part->name, part->id,
-					      mtd_part_id);
+			i = 0;
+			list_for_each_entry(partition, &mtd->partitions, node) {
+				if ((part->part_id - 1) == i) {
+					part_found = true;
+					break;
+				}
+				i++;
+			}
+			if (part_found) {
+				part_addr = partition->offset;
+				part_size = partition->size;
+				part_name = partition->name;
+			} else {
+				stm32prog_err("%s (0x%x):Couldn't find part %d on device mtd %s",
+					      part->name, part->id, part->part_id, mtd_id);
 				return -ENODEV;
 			}
-			part_addr = mtd_part->offset;
-			part_size = mtd_part->size;
-			part_name = mtd_part->name;
-			part_found = true;
 		}
 
 		/* no partition for this device */
@@ -999,9 +1007,6 @@ static int treat_partition_list(struct stm32prog_data *data)
 		INIT_LIST_HEAD(&data->dev[j].part_list);
 	}
 
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-	data->tee_detected = false;
-#endif
 	data->fsbl_nor_detected = false;
 	for (i = 0; i < data->part_nb; i++) {
 		part = &data->part_array[i];
@@ -1053,14 +1058,6 @@ static int treat_partition_list(struct stm32prog_data *data)
 			    !strncmp(part->name, "fsbl", 4))
 				data->fsbl_nor_detected = true;
 			/* fallthrough */
-		case STM32PROG_NAND:
-		case STM32PROG_SPI_NAND:
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-			if (!data->tee_detected &&
-			    !strncmp(part->name, "tee", 3))
-				data->tee_detected = true;
-			break;
-#endif
 		default:
 			break;
 		}
@@ -1130,10 +1127,20 @@ static int create_gpt_partitions(struct stm32prog_data *data)
 			case PART_BINARY:
 				type_str = LINUX_RESERVED_UUID;
 				break;
+			case PART_ENV:
+				type_str = "u-boot-env";
+				break;
 			case PART_FIP:
 				type_str = FIP_TYPE_UUID;
 				break;
-			default:
+			case PART_FWU_MDATA:
+				type_str = FWU_MDATA_UUID;
+				break;
+			case PART_ESP:
+				/* EFI System Partition */
+				type_str = "system";
+				break;
+			default: /* PART_FILESYSTEM or PART_SYSTEM for distro */
 				type_str = "linux";
 				break;
 			}
@@ -1439,8 +1446,11 @@ int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer,
 
 	if (!data->otp_part) {
 		data->otp_part = memalign(CONFIG_SYS_CACHELINE_SIZE, otp_size);
-		if (!data->otp_part)
+		if (!data->otp_part) {
+			stm32prog_err("OTP write issue %d", -ENOMEM);
+
 			return -ENOMEM;
+		}
 	}
 
 	if (!offset)
@@ -1503,6 +1513,8 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
 	memcpy(buffer, (void *)((uintptr_t)data->otp_part + offset), *size);
 
 end_otp_read:
+	if (result)
+		stm32prog_err("OTP read issue %d", result);
 	log_debug("%s: result %i\n", __func__, result);
 
 	return result;
@@ -1556,6 +1568,8 @@ int stm32prog_otp_start(struct stm32prog_data *data)
 
 	free(data->otp_part);
 	data->otp_part = NULL;
+	if (result)
+		stm32prog_err("OTP write issue %d", result);
 	log_debug("%s: result %i\n", __func__, result);
 
 	return result;
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
index 58f4b96fa7..feba29501d 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
@@ -96,12 +96,20 @@ struct stm32_header_v2 {
 	u8 extension_padding[376];
 };
 
-/* partition type in flashlayout file */
+/*
+ * partition type in flashlayout file
+ * SYSTEM = linux partition, bootable
+ * FILESYSTEM = linux partition
+ * ESP = EFI system partition
+ */
 enum stm32prog_part_type {
 	PART_BINARY,
 	PART_FIP,
+	PART_FWU_MDATA,
+	PART_ENV,
 	PART_SYSTEM,
 	PART_FILESYSTEM,
+	PART_ESP,
 	RAW_IMAGE,
 };
 
@@ -149,9 +157,6 @@ struct stm32prog_data {
 	struct stm32prog_dev_t	dev[STM32PROG_MAX_DEV];	/* array of device */
 	int			part_nb;	/* nb of partition */
 	struct stm32prog_part_t	*part_array;	/* array of partition */
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-	bool			tee_detected;
-#endif
 	bool			fsbl_nor_detected;
 
 	/* command internal information */
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
index 80ba5c2774..7f37b0d2aa 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -40,7 +40,7 @@ int dram_init(void)
 	return 0;
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	phys_size_t size;
 	phys_addr_t reg;
diff --git a/arch/arm/mach-stm32mp/ecdsa_romapi.c b/arch/arm/mach-stm32mp/ecdsa_romapi.c
index 12b42b9d59..93c561c69b 100644
--- a/arch/arm/mach-stm32mp/ecdsa_romapi.c
+++ b/arch/arm/mach-stm32mp/ecdsa_romapi.c
@@ -5,6 +5,7 @@
  * Implements ECDSA signature verification via the STM32MP ROM.
  */
 #include <asm/system.h>
+#include <asm/arch/sys_proto.h>
 #include <dm/device.h>
 #include <linux/types.h>
 #include <u-boot/ecdsa.h>
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index c85ae6a34e..1cdc5e3b18 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -21,8 +21,10 @@
 #define STM32_DBGMCU_BASE		0x50081000
 #endif
 #define STM32_FMC2_BASE			0x58002000
+#define STM32_IWDG2_BASE		0x5A002000
 #define STM32_DDRCTRL_BASE		0x5A003000
 #define STM32_DDRPHYC_BASE		0x5A004000
+#define STM32_IWDG1_BASE		0x5C003000
 #define STM32_TZC_BASE			0x5C006000
 #define STM32_ETZPC_BASE		0x5C007000
 #define STM32_STGEN_BASE		0x5C008000
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32prog.h b/arch/arm/mach-stm32mp/include/mach/stm32prog.h
index 99be4e1d65..23d1adfbad 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32prog.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32prog.h
@@ -11,8 +11,4 @@ int stm32prog_read_medium_virt(struct dfu_entity *dfu, u64 offset,
 			       void *buf, long *len);
 int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size);
 
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-bool stm32prog_get_tee_partitions(void);
-#endif
-
 bool stm32prog_get_fsbl_nor(void);
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
index 0d39b67178..83fb32a45f 100644
--- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
@@ -44,6 +44,7 @@ u32 get_cpu_dev(void);
 #define CPU_REV1_2	0x1003
 #define CPU_REV2	0x2000
 #define CPU_REV2_1	0x2001
+#define CPU_REV2_2	0x2003
 
 /* return Silicon revision = REV_ID[15:0] of Device Version */
 u32 get_cpu_rev(void);
diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
index 1e69673e88..8cdeb0ab3f 100644
--- a/arch/arm/mach-stm32mp/psci.c
+++ b/arch/arm/mach-stm32mp/psci.c
@@ -161,6 +161,12 @@
 #define RCC_MP_GRSTCSETR_MPUP0RST		BIT(4)
 #define RCC_MP_GRSTCSETR_MPUP1RST		BIT(5)
 
+/* IWDG */
+#define IWDG_KR					0x00
+#define IWDG_KR_RELOAD_KEY			0xaaaa
+#define IWDG_EWCR				0x14
+#define IWDG_EWCR_EWIC				BIT(14)
+
 #define STM32MP1_PSCI_NR_CPUS			2
 #if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
 #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
@@ -696,7 +702,18 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
 				  u32 ep, u32 context_id)
 {
 	u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr;
+	u32 gicd_addr = stm32mp_get_gicd_base_address();
+	bool iwdg1_wake = false;
+	bool iwdg2_wake = false;
+	bool other_wake = false;
 	u32 saved_pwrctl, reg;
+	u32 gic_enabled[8];
+	u32 irqs;
+	int i;
+
+	/* Cache enable mask of all 256 SPI */
+	for (i = 0; i < ARRAY_SIZE(gic_enabled); i++)
+		gic_enabled[i] = readl(gicd_addr + GICD_ISENABLERn + 0x4 + 4 * i);
 
 	/* Disable IO compensation */
 
@@ -712,7 +729,7 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
 	setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF);
 
 	setbits_le32(STM32_PWR_BASE + PWR_MPUCR,
-		     PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS);
+		     PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS);
 
 	saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR);
 	saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR);
@@ -725,11 +742,57 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
 	setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRSREN);
 	writel(0x3, STM32_RCC_BASE + RCC_MP_SREQSETR);
 
-	/* Zzz, enter stop mode */
-	asm volatile(
-		"isb\n"
-		"dsb\n"
-		"wfi\n");
+	/* Ping the IWDG before entering suspend */
+	iwdg1_wake = !!(gic_enabled[4] & BIT(22));	/* SPI 150 */
+	iwdg2_wake = !!(gic_enabled[4] & BIT(23));	/* SPI 151 */
+
+	for (;;) {
+		/* Ping IWDG1 and ACK pretimer IRQ */
+		if (iwdg1_wake) {
+			writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR);
+			writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR);
+		}
+
+		/* Ping IWDG2 and ACK pretimer IRQ */
+		if (iwdg2_wake) {
+			writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR);
+			writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR);
+		}
+
+		iwdg1_wake = false;
+		iwdg2_wake = false;
+
+		/* Zzz, enter stop mode */
+		asm volatile(
+			"isb\n"
+			"dsb\n"
+			"wfi\n");
+
+		/* Determine the wake up source */
+		for (i = 0; i < ARRAY_SIZE(gic_enabled); i++) {
+			irqs = readl(gicd_addr + GICR_IGROUPMODRn + 0x4 + 4 * i);
+			irqs &= gic_enabled[i];
+			if (!irqs)
+				continue;
+
+			/* Test whether IWDG pretimeout triggered the wake up. */
+			if (i == 4) {	/* SPI Num 128..159 */
+				iwdg1_wake = !!(irqs & BIT(22));	/* SPI 150 */
+				iwdg2_wake = !!(irqs & BIT(23));	/* SPI 151 */
+				irqs &= ~(BIT(22) | BIT(23));
+			}
+
+			/* Test whether there is any other wake up trigger. */
+			if (irqs) {
+				other_wake = true;
+				break;
+			}
+		}
+
+		/* Other wake up triggers pending, let OS deal with all of it. */
+		if (other_wake)
+			break;
+	}
 
 	writel(0x3, STM32_RCC_BASE + RCC_MP_SREQCLRR);
 	ddr_sw_self_refresh_exit();
diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp15x.c
index 660c907a6b..afc56b02ee 100644
--- a/arch/arm/mach-stm32mp/stm32mp15x.c
+++ b/arch/arm/mach-stm32mp/stm32mp15x.c
@@ -266,7 +266,7 @@ static const char * const soc_type[] = {
 };
 
 static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" };
-static const char * const soc_rev[] = { "?", "A", "B", "Z" };
+static const char * const soc_rev[] = { "?", "A", "B", "Z", "Y"};
 
 static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
 				   unsigned int *rev)
@@ -307,6 +307,9 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
 	case CPU_REV2_1:
 		*rev = 3;
 		break;
+	case CPU_REV2_2:
+		*rev = 4;
+		break;
 	default:
 		*rev = 0;
 		break;
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 6dcbb096f7..e20c3a3ee9 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -207,7 +207,6 @@ endif
 
 config MACH_SUNXI_H3_H5
 	bool
-	select PHY_SUN4I_USB
 	select SUNXI_DE2
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_32BIT
@@ -236,7 +235,6 @@ config MACH_SUNIV
 config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7A
-	select PHY_SUN4I_USB
 	select DRAM_SUN4I
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
@@ -247,7 +245,6 @@ config MACH_SUN5I
 	bool "sun5i (Allwinner A13)"
 	select CPU_V7A
 	select DRAM_SUN4I
-	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 	imply SPL_SYS_I2C_LEGACY
@@ -261,7 +258,6 @@ config MACH_SUN6I
 	select ARCH_SUPPORT_PSCI
 	select SPL_ARMV7_SET_CORTEX_SMPEN
 	select DRAM_SUN6I
-	select PHY_SUN4I_USB
 	select SPL_I2C
 	select SUN6I_PRCM
 	select SUNXI_GEN_SUN6I
@@ -277,7 +273,6 @@ config MACH_SUN7I
 	select ARCH_SUPPORT_PSCI
 	select SPL_ARMV7_SET_CORTEX_SMPEN
 	select DRAM_SUN4I
-	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
@@ -291,7 +286,6 @@ config MACH_SUN8I_A23
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN8I_A23
-	select PHY_SUN4I_USB
 	select SPL_I2C
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
@@ -305,7 +299,6 @@ config MACH_SUN8I_A33
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN8I_A33
-	select PHY_SUN4I_USB
 	select SPL_I2C
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
@@ -316,7 +309,6 @@ config MACH_SUN8I_A83T
 	bool "sun8i (Allwinner A83T)"
 	select CPU_V7A
 	select DRAM_SUN8I_A83T
-	select PHY_SUN4I_USB
 	select SPL_I2C
 	select SUNXI_GEN_SUN6I
 	select MMC_SUNXI_HAS_NEW_MODE
@@ -344,7 +336,6 @@ config MACH_SUN8I_R40
 	select SUPPORT_SPL
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_32BIT
-	select PHY_SUN4I_USB
 	imply SPL_SYS_I2C_LEGACY
 
 config MACH_SUN8I_V3S
@@ -372,7 +363,6 @@ config MACH_SUN9I
 config MACH_SUN50I
 	bool "sun50i (Allwinner A64)"
 	select ARM64
-	select PHY_SUN4I_USB
 	select SUN6I_PRCM
 	select SUNXI_DE2
 	select SUNXI_GEN_SUN6I
@@ -395,7 +385,6 @@ config MACH_SUN50I_H5
 config MACH_SUN50I_H6
 	bool "sun50i (Allwinner H6)"
 	select ARM64
-	select PHY_SUN4I_USB
 	select DRAM_SUN50I_H6
 	select SUN50I_GEN_H6
 
@@ -442,7 +431,7 @@ config ARM_BOOT_HOOK_RMR
 	This allows both the SPL and the U-Boot proper to be entered in
 	either mode and switch to AArch64 if needed.
 
-if SUNXI_DRAM_DW || DRAM_SUN50I_H6
+if SUNXI_DRAM_DW || DRAM_SUN50I_H6 || DRAM_SUN50I_H616
 config SUNXI_DRAM_DDR3
 	bool
 
@@ -487,6 +476,22 @@ config SUNXI_DRAM_H6_DDR3_1333
 	This option is the DDR3 timing used by the boot0 on H6 TV boxes
 	which use a DDR3-1333 timing.
 
+config SUNXI_DRAM_H616_LPDDR3
+	bool "LPDDR3 DRAM chips on the H616 DRAM controller"
+	select SUNXI_DRAM_LPDDR3
+	depends on DRAM_SUN50I_H616
+	help
+	  This option is the LPDDR3 timing used by the stock boot0 by
+	  Allwinner.
+
+config SUNXI_DRAM_H616_DDR3_1333
+	bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
+	select SUNXI_DRAM_DDR3
+	depends on DRAM_SUN50I_H616
+	help
+	  This option is the DDR3 timing used by the boot0 on H616 TV boxes
+	  which use a DDR3-1333 timing.
+
 config SUNXI_DRAM_DDR2_V3S
 	bool "DDR2 found in V3s chip"
 	select SUNXI_DRAM_DDR2
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 391a65a549..78597ad932 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -64,7 +64,7 @@ static struct mm_region sunxi_mem_map[] = {
 };
 struct mm_region *mem_map = sunxi_mem_map;
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	/* Some devices (like the EMAC) have a 32-bit DMA limit. */
 	if (gd->ram_top > (1ULL << 32))
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index b332f3a3e4..bff2e42513 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -93,7 +93,8 @@ enum {
 	MBUS_QOS_HIGH,
 	MBUS_QOS_HIGHEST
 };
-inline void mbus_configure_port(u8 port,
+
+static void mbus_configure_port(u8 port,
 				bool bwlimit,
 				bool priority,
 				u8 qos,
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 1f9416d6ea..7e580b62dc 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -31,7 +31,7 @@ enum {
 	MBUS_QOS_HIGHEST
 };
 
-inline void mbus_configure_port(u8 port,
+static void mbus_configure_port(u8 port,
 				bool bwlimit,
 				bool priority,
 				u8 qos,
@@ -92,7 +92,7 @@ static void mctl_set_master_priority(void)
 	dmb();
 }
 
-static void mctl_sys_init(struct dram_para *para)
+static void mctl_sys_init(u32 clk_rate)
 {
 	struct sunxi_ccm_reg * const ccm =
 			(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
@@ -114,7 +114,7 @@ static void mctl_sys_init(struct dram_para *para)
 
 	/* Set PLL5 rate to doubled DRAM clock rate */
 	writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | CCM_PLL5_OUT_EN |
-	       CCM_PLL5_CTRL_N(para->clk * 2 / 24), &ccm->pll5_cfg);
+	       CCM_PLL5_CTRL_N(clk_rate * 2 / 24), &ccm->pll5_cfg);
 	mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
 
 	/* Configure DRAM mod clock */
@@ -141,15 +141,15 @@ static void mctl_sys_init(struct dram_para *para)
 	writel(0x8000, &mctl_ctl->clken);
 }
 
-static void mctl_set_addrmap(struct dram_para *para)
+static void mctl_set_addrmap(const struct dram_config *config)
 {
 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
 			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-	u8 cols = para->cols;
-	u8 rows = para->rows;
-	u8 ranks = para->ranks;
+	u8 cols = config->cols;
+	u8 rows = config->rows;
+	u8 ranks = config->ranks;
 
-	if (!para->bus_full_width)
+	if (!config->bus_full_width)
 		cols -= 1;
 
 	/* Ranks */
@@ -228,13 +228,20 @@ static void mctl_set_addrmap(struct dram_para *para)
 }
 
 static const u8 phy_init[] = {
+#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333
 	0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19,
 	0x0a, 0x15, 0x03, 0x13, 0x04, 0x0c, 0x10, 0x06,
 	0x0f, 0x11, 0x1a, 0x01, 0x12, 0x17, 0x00, 0x08,
 	0x09, 0x05, 0x18
+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)
+	0x18, 0x06, 0x00, 0x05, 0x04, 0x03, 0x09, 0x02,
+	0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
+	0x17, 0x19, 0x1a
+#endif
 };
 
-static void mctl_phy_configure_odt(struct dram_para *para)
+static void mctl_phy_configure_odt(const struct dram_para *para)
 {
 	unsigned int val;
 
@@ -263,25 +270,37 @@ static void mctl_phy_configure_odt(struct dram_para *para)
 	writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x34c);
 
 	val = para->dx_odt & 0x1f;
-	writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x380);
+	if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+		writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x380);
+	else
+		writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x380);
 	writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x384);
 
 	val = (para->dx_odt >> 8) & 0x1f;
-	writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c0);
+	if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+		writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x3c0);
+	else
+		writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c0);
 	writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c4);
 
 	val = (para->dx_odt >> 16) & 0x1f;
-	writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x400);
+	if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+		writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x400);
+	else
+		writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x400);
 	writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x404);
 
 	val = (para->dx_odt >> 24) & 0x1f;
-	writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x440);
+	if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+		writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x440);
+	else
+		writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x440);
 	writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x444);
 
 	dmb();
 }
 
-static bool mctl_phy_write_leveling(struct dram_para *para)
+static bool mctl_phy_write_leveling(const struct dram_config *config)
 {
 	bool result = true;
 	u32 val;
@@ -292,7 +311,7 @@ static bool mctl_phy_write_leveling(struct dram_para *para)
 
 	setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
 
-	if (para->bus_full_width)
+	if (config->bus_full_width)
 		val = 0xf;
 	else
 		val = 3;
@@ -316,12 +335,12 @@ static bool mctl_phy_write_leveling(struct dram_para *para)
 
 	clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0xc0);
 
-	if (para->ranks == 2) {
+	if (config->ranks == 2) {
 		clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0xc0, 0x40);
 
 		setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
 
-		if (para->bus_full_width)
+		if (config->bus_full_width)
 			val = 0xf;
 		else
 			val = 3;
@@ -336,7 +355,7 @@ static bool mctl_phy_write_leveling(struct dram_para *para)
 	return result;
 }
 
-static bool mctl_phy_read_calibration(struct dram_para *para)
+static bool mctl_phy_read_calibration(const struct dram_config *config)
 {
 	bool result = true;
 	u32 val, tmp;
@@ -345,7 +364,7 @@ static bool mctl_phy_read_calibration(struct dram_para *para)
 
 	setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
 
-	if (para->bus_full_width)
+	if (config->bus_full_width)
 		val = 0xf;
 	else
 		val = 3;
@@ -361,7 +380,7 @@ static bool mctl_phy_read_calibration(struct dram_para *para)
 
 	clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30);
 
-	if (para->ranks == 2) {
+	if (config->ranks == 2) {
 		clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30, 0x10);
 
 		setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
@@ -395,7 +414,7 @@ static bool mctl_phy_read_calibration(struct dram_para *para)
 	return result;
 }
 
-static bool mctl_phy_read_training(struct dram_para *para)
+static bool mctl_phy_read_training(const struct dram_config *config)
 {
 	u32 val1, val2, *ptr1, *ptr2;
 	bool result = true;
@@ -414,7 +433,7 @@ static bool mctl_phy_read_training(struct dram_para *para)
 	if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3)
 		result = false;
 
-	if (para->bus_full_width) {
+	if (config->bus_full_width) {
 		mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc);
 		if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3)
 			result = false;
@@ -437,7 +456,7 @@ static bool mctl_phy_read_training(struct dram_para *para)
 			result = false;
 	}
 
-	if (para->bus_full_width) {
+	if (config->bus_full_width) {
 		ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa98);
 		ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa50);
 		for (i = 0; i < 9; i++) {
@@ -459,7 +478,7 @@ static bool mctl_phy_read_training(struct dram_para *para)
 
 	clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 3);
 
-	if (para->ranks == 2) {
+	if (config->ranks == 2) {
 		/* maybe last parameter should be 1? */
 		clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 3, 2);
 
@@ -470,7 +489,7 @@ static bool mctl_phy_read_training(struct dram_para *para)
 		if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3)
 			result = false;
 
-		if (para->bus_full_width) {
+		if (config->bus_full_width) {
 			mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc);
 			if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3)
 				result = false;
@@ -484,7 +503,7 @@ static bool mctl_phy_read_training(struct dram_para *para)
 	return result;
 }
 
-static bool mctl_phy_write_training(struct dram_para *para)
+static bool mctl_phy_write_training(const struct dram_config *config)
 {
 	u32 val1, val2, *ptr1, *ptr2;
 	bool result = true;
@@ -504,7 +523,7 @@ static bool mctl_phy_write_training(struct dram_para *para)
 	if (readl(SUNXI_DRAM_PHY0_BASE + 0x8e0) & 0xc)
 		result = false;
 
-	if (para->bus_full_width) {
+	if (config->bus_full_width) {
 		mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3);
 		if (readl(SUNXI_DRAM_PHY0_BASE + 0xae0) & 0xc)
 			result = false;
@@ -527,7 +546,7 @@ static bool mctl_phy_write_training(struct dram_para *para)
 			result = false;
 	}
 
-	if (para->bus_full_width) {
+	if (config->bus_full_width) {
 		ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xb38);
 		ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xaf0);
 		for (i = 0; i < 9; i++) {
@@ -548,7 +567,7 @@ static bool mctl_phy_write_training(struct dram_para *para)
 
 	clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x60);
 
-	if (para->ranks == 2) {
+	if (config->ranks == 2) {
 		clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 0xc, 4);
 
 		setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
@@ -558,7 +577,7 @@ static bool mctl_phy_write_training(struct dram_para *para)
 		if (readl(SUNXI_DRAM_PHY0_BASE + 0x8e0) & 0xc)
 			result = false;
 
-		if (para->bus_full_width) {
+		if (config->bus_full_width) {
 			mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3);
 			if (readl(SUNXI_DRAM_PHY0_BASE + 0xae0) & 0xc)
 				result = false;
@@ -572,7 +591,7 @@ static bool mctl_phy_write_training(struct dram_para *para)
 	return result;
 }
 
-static void mctl_phy_bit_delay_compensation(struct dram_para *para)
+static void mctl_phy_bit_delay_compensation(const struct dram_para *para)
 {
 	u32 *ptr, val;
 	int i;
@@ -773,7 +792,8 @@ static void mctl_phy_bit_delay_compensation(struct dram_para *para)
 	}
 }
 
-static void mctl_phy_ca_bit_delay_compensation(struct dram_para *para)
+static void mctl_phy_ca_bit_delay_compensation(const struct dram_para *para,
+					       const struct dram_config *config)
 {
 	u32 val, *ptr;
 	int i;
@@ -793,36 +813,53 @@ static void mctl_phy_ca_bit_delay_compensation(struct dram_para *para)
 	writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e0);
 	writel(val, SUNXI_DRAM_PHY0_BASE + 0x7f4);
 
-	/* following configuration is DDR3 specific */
-	val = (para->tpr10 >> 7) & 0x1e;
-	if (para->tpr2 & 1) {
-		writel(val, SUNXI_DRAM_PHY0_BASE + 0x794);
-		if (para->ranks == 2) {
-			val = (para->tpr10 >> 11) & 0x1e;
-			writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e4);
-		}
-		if (para->tpr0 & BIT(31)) {
-			val = (para->tpr0 << 1) & 0x3e;
-			writel(val, SUNXI_DRAM_PHY0_BASE + 0x790);
-			writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
-			writel(val, SUNXI_DRAM_PHY0_BASE + 0x7cc);
-		}
-	} else {
-		writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d4);
-		if (para->ranks == 2) {
-			val = (para->tpr10 >> 11) & 0x1e;
-			writel(val, SUNXI_DRAM_PHY0_BASE + 0x79c);
+	if (para->type == SUNXI_DRAM_TYPE_DDR3) {
+		val = (para->tpr10 >> 7) & 0x1e;
+		if (para->tpr2 & 1) {
+			writel(val, SUNXI_DRAM_PHY0_BASE + 0x794);
+			if (config->ranks == 2) {
+				val = (para->tpr10 >> 11) & 0x1e;
+				writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e4);
+			}
+			if (para->tpr0 & BIT(31)) {
+				val = (para->tpr0 << 1) & 0x3e;
+				writel(val, SUNXI_DRAM_PHY0_BASE + 0x790);
+				writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
+				writel(val, SUNXI_DRAM_PHY0_BASE + 0x7cc);
+			}
+		} else {
+			writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d4);
+			if (config->ranks == 2) {
+				val = (para->tpr10 >> 11) & 0x1e;
+				writel(val, SUNXI_DRAM_PHY0_BASE + 0x79c);
+			}
+			if (para->tpr0 & BIT(31)) {
+				val = (para->tpr0 << 1) & 0x3e;
+				writel(val, SUNXI_DRAM_PHY0_BASE + 0x78c);
+				writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a4);
+				writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
+			}
 		}
-		if (para->tpr0 & BIT(31)) {
-			val = (para->tpr0 << 1) & 0x3e;
-			writel(val, SUNXI_DRAM_PHY0_BASE + 0x78c);
-			writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a4);
-			writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
+	} else if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
+		val = (para->tpr10 >> 7) & 0x1e;
+		if (para->tpr2 & 1) {
+			writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a0);
+			if (config->ranks == 2) {
+				val = (para->tpr10 >> 11) & 0x1e;
+				writel(val, SUNXI_DRAM_PHY0_BASE + 0x79c);
+			}
+		} else {
+			writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e8);
+			if (config->ranks == 2) {
+				val = (para->tpr10 >> 11) & 0x1e;
+				writel(val, SUNXI_DRAM_PHY0_BASE + 0x7f8);
+			}
 		}
 	}
 }
 
-static bool mctl_phy_init(struct dram_para *para)
+static bool mctl_phy_init(const struct dram_para *para,
+			  const struct dram_config *config)
 {
 	struct sunxi_mctl_com_reg * const mctl_com =
 			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
@@ -831,18 +868,29 @@ static bool mctl_phy_init(struct dram_para *para)
 	u32 val, val2, *ptr, mr0, mr2;
 	int i;
 
-	if (para->bus_full_width)
+	if (config->bus_full_width)
 		val = 0xf;
 	else
 		val = 3;
 	clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3c, 0xf, val);
 
 	if (para->tpr2 & 0x100) {
-		val = 9;
-		val2 = 7;
+		if (para->type == SUNXI_DRAM_TYPE_DDR3) {
+			val = 9;
+			val2 = 7;
+		} else if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
+			// untested setup: use some values for now
+			val = 14;
+			val2 = 8;
+		}
 	} else {
-		val = 13;
-		val2 = 9;
+		if (para->type == SUNXI_DRAM_TYPE_DDR3) {
+			val = 13;
+			val2 = 9;
+		} else if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
+			val = 14;
+			val2 = 8;
+		}
 	}
 
 	writel(val, SUNXI_DRAM_PHY0_BASE + 0x14);
@@ -865,14 +913,22 @@ static bool mctl_phy_init(struct dram_para *para)
 		writel(phy_init[i], &ptr[i]);
 
 	if (para->tpr10 & TPR10_CA_BIT_DELAY)
-		mctl_phy_ca_bit_delay_compensation(para);
+		mctl_phy_ca_bit_delay_compensation(para, config);
 
-	writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc);
-	writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c);
+	if (para->type == SUNXI_DRAM_TYPE_DDR3)
+		val = 0x80;
+	else if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+		val = 0xc0;
+	writel(val, SUNXI_DRAM_PHY0_BASE + 0x3dc);
+	writel(val, SUNXI_DRAM_PHY0_BASE + 0x45c);
 
 	mctl_phy_configure_odt(para);
 
-	clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, 0xa);
+	if (para->type == SUNXI_DRAM_TYPE_DDR3)
+		val = 0x0a;
+	else if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+		val = 0x0b;
+	clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 0x7, val);
 
 	if (para->clk <= 672)
 		writel(0xf, SUNXI_DRAM_PHY0_BASE + 0x20);
@@ -922,21 +978,39 @@ static bool mctl_phy_init(struct dram_para *para)
 		mr2 = 0x20;
 	}
 
-	writel(mr0, &mctl_ctl->mrctrl1);
-	writel(0x80000030, &mctl_ctl->mrctrl0);
-	mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
-
-	writel(4, &mctl_ctl->mrctrl1);
-	writel(0x80001030, &mctl_ctl->mrctrl0);
-	mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
-
-	writel(mr2, &mctl_ctl->mrctrl1);
-	writel(0x80002030, &mctl_ctl->mrctrl0);
-	mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
-
-	writel(0, &mctl_ctl->mrctrl1);
-	writel(0x80003030, &mctl_ctl->mrctrl0);
-	mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+	if (para->type == SUNXI_DRAM_TYPE_DDR3) {
+		writel(mr0, &mctl_ctl->mrctrl1);
+		writel(0x80000030, &mctl_ctl->mrctrl0);
+		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+		writel(4, &mctl_ctl->mrctrl1);
+		writel(0x80001030, &mctl_ctl->mrctrl0);
+		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+		writel(mr2, &mctl_ctl->mrctrl1);
+		writel(0x80002030, &mctl_ctl->mrctrl0);
+		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+		writel(0, &mctl_ctl->mrctrl1);
+		writel(0x80003030, &mctl_ctl->mrctrl0);
+		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+	} else if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
+		writel(mr0, &mctl_ctl->mrctrl1);
+		writel(0x800000f0, &mctl_ctl->mrctrl0);
+		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+		writel(4, &mctl_ctl->mrctrl1);
+		writel(0x800000f0, &mctl_ctl->mrctrl0);
+		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+		writel(mr2, &mctl_ctl->mrctrl1);
+		writel(0x800000f0, &mctl_ctl->mrctrl0);
+		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+		writel(0x301, &mctl_ctl->mrctrl1);
+		writel(0x800000f0, &mctl_ctl->mrctrl0);
+		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+	}
 
 	writel(0, SUNXI_DRAM_PHY0_BASE + 0x54);
 
@@ -946,7 +1020,7 @@ static bool mctl_phy_init(struct dram_para *para)
 
 	if (para->tpr10 & TPR10_WRITE_LEVELING) {
 		for (i = 0; i < 5; i++)
-			if (mctl_phy_write_leveling(para))
+			if (mctl_phy_write_leveling(config))
 				break;
 		if (i == 5) {
 			debug("write leveling failed!\n");
@@ -956,7 +1030,7 @@ static bool mctl_phy_init(struct dram_para *para)
 
 	if (para->tpr10 & TPR10_READ_CALIBRATION) {
 		for (i = 0; i < 5; i++)
-			if (mctl_phy_read_calibration(para))
+			if (mctl_phy_read_calibration(config))
 				break;
 		if (i == 5) {
 			debug("read calibration failed!\n");
@@ -966,7 +1040,7 @@ static bool mctl_phy_init(struct dram_para *para)
 
 	if (para->tpr10 & TPR10_READ_TRAINING) {
 		for (i = 0; i < 5; i++)
-			if (mctl_phy_read_training(para))
+			if (mctl_phy_read_training(config))
 				break;
 		if (i == 5) {
 			debug("read training failed!\n");
@@ -976,7 +1050,7 @@ static bool mctl_phy_init(struct dram_para *para)
 
 	if (para->tpr10 & TPR10_WRITE_TRAINING) {
 		for (i = 0; i < 5; i++)
-			if (mctl_phy_write_training(para))
+			if (mctl_phy_write_training(config))
 				break;
 		if (i == 5) {
 			debug("write training failed!\n");
@@ -991,7 +1065,8 @@ static bool mctl_phy_init(struct dram_para *para)
 	return true;
 }
 
-static bool mctl_ctrl_init(struct dram_para *para)
+static bool mctl_ctrl_init(const struct dram_para *para,
+			   const struct dram_config *config)
 {
 	struct sunxi_mctl_com_reg * const mctl_com =
 			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
@@ -1010,27 +1085,34 @@ static bool mctl_ctrl_init(struct dram_para *para)
 
 	setbits_le32(&mctl_com->unk_0x008, 0xff00);
 
-	reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
-	reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
-	if (para->bus_full_width)
+	reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(config->ranks);
+	if (para->type == SUNXI_DRAM_TYPE_DDR3)
+		reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
+	else if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+		reg_val |= MSTR_DEVICETYPE_LPDDR3;
+	if (config->bus_full_width)
 		reg_val |= MSTR_BUSWIDTH_FULL;
 	else
 		reg_val |= MSTR_BUSWIDTH_HALF;
 	writel(BIT(31) | BIT(30) | reg_val, &mctl_ctl->mstr);
 
-	if (para->ranks == 2)
+	if (config->ranks == 2)
 		writel(0x0303, &mctl_ctl->odtmap);
 	else
 		writel(0x0201, &mctl_ctl->odtmap);
 
-	writel(0x06000400, &mctl_ctl->odtcfg);
-	writel(0x06000400, &mctl_ctl->unk_0x2240);
-	writel(0x06000400, &mctl_ctl->unk_0x3240);
-	writel(0x06000400, &mctl_ctl->unk_0x4240);
+	if (para->type == SUNXI_DRAM_TYPE_DDR3)
+		reg_val = 0x06000400;
+	else if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+		reg_val = 0x09020400;
+	writel(reg_val, &mctl_ctl->odtcfg);
+	writel(reg_val, &mctl_ctl->unk_0x2240);
+	writel(reg_val, &mctl_ctl->unk_0x3240);
+	writel(reg_val, &mctl_ctl->unk_0x4240);
 
 	writel(BIT(31), &mctl_com->cr);
 
-	mctl_set_addrmap(para);
+	mctl_set_addrmap(config);
 
 	mctl_set_timing_params(para);
 
@@ -1056,7 +1138,7 @@ static bool mctl_ctrl_init(struct dram_para *para)
 	/* this write seems to enable PHY MMIO region */
 	setbits_le32(&mctl_com->unk_0x500, BIT(24));
 
-	if (!mctl_phy_init(para))
+	if (!mctl_phy_init(para, config))
 		return false;
 
 	writel(0, &mctl_ctl->swctl);
@@ -1073,18 +1155,20 @@ static bool mctl_ctrl_init(struct dram_para *para)
 	return true;
 }
 
-static bool mctl_core_init(struct dram_para *para)
+static bool mctl_core_init(const struct dram_para *para,
+			   const struct dram_config *config)
 {
-	mctl_sys_init(para);
+	mctl_sys_init(para->clk);
 
-	return mctl_ctrl_init(para);
+	return mctl_ctrl_init(para, config);
 }
 
-static void mctl_auto_detect_rank_width(struct dram_para *para)
+static void mctl_auto_detect_rank_width(const struct dram_para *para,
+					struct dram_config *config)
 {
 	/* this is minimum size that it's supported */
-	para->cols = 8;
-	para->rows = 13;
+	config->cols = 8;
+	config->rows = 13;
 
 	/*
 	 * Strategy here is to test most demanding combination first and least
@@ -1095,94 +1179,101 @@ static void mctl_auto_detect_rank_width(struct dram_para *para)
 	 */
 
 	debug("testing 32-bit width, rank = 2\n");
-	para->bus_full_width = 1;
-	para->ranks = 2;
-	if (mctl_core_init(para))
+	config->bus_full_width = 1;
+	config->ranks = 2;
+	if (mctl_core_init(para, config))
 		return;
 
 	debug("testing 32-bit width, rank = 1\n");
-	para->bus_full_width = 1;
-	para->ranks = 1;
-	if (mctl_core_init(para))
+	config->bus_full_width = 1;
+	config->ranks = 1;
+	if (mctl_core_init(para, config))
 		return;
 
 	debug("testing 16-bit width, rank = 2\n");
-	para->bus_full_width = 0;
-	para->ranks = 2;
-	if (mctl_core_init(para))
+	config->bus_full_width = 0;
+	config->ranks = 2;
+	if (mctl_core_init(para, config))
 		return;
 
 	debug("testing 16-bit width, rank = 1\n");
-	para->bus_full_width = 0;
-	para->ranks = 1;
-	if (mctl_core_init(para))
+	config->bus_full_width = 0;
+	config->ranks = 1;
+	if (mctl_core_init(para, config))
 		return;
 
 	panic("This DRAM setup is currently not supported.\n");
 }
 
-static void mctl_auto_detect_dram_size(struct dram_para *para)
+static void mctl_auto_detect_dram_size(const struct dram_para *para,
+				       struct dram_config *config)
 {
 	/* detect row address bits */
-	para->cols = 8;
-	para->rows = 18;
-	mctl_core_init(para);
+	config->cols = 8;
+	config->rows = 18;
+	mctl_core_init(para, config);
 
-	for (para->rows = 13; para->rows < 18; para->rows++) {
+	for (config->rows = 13; config->rows < 18; config->rows++) {
 		/* 8 banks, 8 bit per byte and 16/32 bit width */
-		if (mctl_mem_matches((1 << (para->rows + para->cols +
-					    4 + para->bus_full_width))))
+		if (mctl_mem_matches((1 << (config->rows + config->cols +
+					    4 + config->bus_full_width))))
 			break;
 	}
 
 	/* detect column address bits */
-	para->cols = 11;
-	mctl_core_init(para);
+	config->cols = 11;
+	mctl_core_init(para, config);
 
-	for (para->cols = 8; para->cols < 11; para->cols++) {
+	for (config->cols = 8; config->cols < 11; config->cols++) {
 		/* 8 bits per byte and 16/32 bit width */
-		if (mctl_mem_matches(1 << (para->cols + 1 +
-					   para->bus_full_width)))
+		if (mctl_mem_matches(1 << (config->cols + 1 +
+					   config->bus_full_width)))
 			break;
 	}
 }
 
-static unsigned long mctl_calc_size(struct dram_para *para)
+static unsigned long mctl_calc_size(const struct dram_config *config)
 {
-	u8 width = para->bus_full_width ? 4 : 2;
+	u8 width = config->bus_full_width ? 4 : 2;
 
 	/* 8 banks */
-	return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
+	return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks;
 }
 
+static const struct dram_para para = {
+	.clk = CONFIG_DRAM_CLK,
+#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333
+	.type = SUNXI_DRAM_TYPE_DDR3,
+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)
+	.type = SUNXI_DRAM_TYPE_LPDDR3,
+#endif
+	.dx_odt = CONFIG_DRAM_SUN50I_H616_DX_ODT,
+	.dx_dri = CONFIG_DRAM_SUN50I_H616_DX_DRI,
+	.ca_dri = CONFIG_DRAM_SUN50I_H616_CA_DRI,
+	.odt_en = CONFIG_DRAM_SUN50I_H616_ODT_EN,
+	.tpr0 = CONFIG_DRAM_SUN50I_H616_TPR0,
+	.tpr2 = CONFIG_DRAM_SUN50I_H616_TPR2,
+	.tpr10 = CONFIG_DRAM_SUN50I_H616_TPR10,
+	.tpr11 = CONFIG_DRAM_SUN50I_H616_TPR11,
+	.tpr12 = CONFIG_DRAM_SUN50I_H616_TPR12,
+};
+
 unsigned long sunxi_dram_init(void)
 {
 	struct sunxi_prcm_reg *const prcm =
 		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
-	struct dram_para para = {
-		.clk = CONFIG_DRAM_CLK,
-		.type = SUNXI_DRAM_TYPE_DDR3,
-		.dx_odt = CONFIG_DRAM_SUN50I_H616_DX_ODT,
-		.dx_dri = CONFIG_DRAM_SUN50I_H616_DX_DRI,
-		.ca_dri = CONFIG_DRAM_SUN50I_H616_CA_DRI,
-		.odt_en = CONFIG_DRAM_SUN50I_H616_ODT_EN,
-		.tpr0 = CONFIG_DRAM_SUN50I_H616_TPR0,
-		.tpr2 = CONFIG_DRAM_SUN50I_H616_TPR2,
-		.tpr10 = CONFIG_DRAM_SUN50I_H616_TPR10,
-		.tpr11 = CONFIG_DRAM_SUN50I_H616_TPR11,
-		.tpr12 = CONFIG_DRAM_SUN50I_H616_TPR12,
-	};
+	struct dram_config config;
 	unsigned long size;
 
 	setbits_le32(&prcm->res_cal_ctrl, BIT(8));
 	clrbits_le32(&prcm->ohms240, 0x3f);
 
-	mctl_auto_detect_rank_width(&para);
-	mctl_auto_detect_dram_size(&para);
+	mctl_auto_detect_rank_width(&para, &config);
+	mctl_auto_detect_dram_size(&para, &config);
 
-	mctl_core_init(&para);
+	mctl_core_init(&para, &config);
 
-	size = mctl_calc_size(&para);
+	size = mctl_calc_size(&config);
 
 	mctl_set_master_priority();
 
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 4af5922f33..9382d3d0be 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -81,15 +81,15 @@ enum {
 	MBUS_QOS_HIGHEST
 };
 
-static inline void mbus_configure_port(u8 port,
-				       bool bwlimit,
-				       bool priority,
-				       u8 qos,         /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */
-				       u8 waittime,    /* 0 .. 0xf */
-				       u8 acs,         /* 0 .. 0xff */
-				       u16 bwl0,       /* 0 .. 0xffff, bandwidth limit in MB/s */
-				       u16 bwl1,
-				       u16 bwl2)
+static void mbus_configure_port(u8 port,
+				bool bwlimit,
+				bool priority,
+				u8 qos,         /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */
+				u8 waittime,    /* 0 .. 0xf */
+				u8 acs,         /* 0 .. 0xff */
+				u16 bwl0,       /* 0 .. 0xffff, bandwidth limit in MB/s */
+				u16 bwl1,
+				u16 bwl2)
 {
 	struct sunxi_mctl_com_reg * const mctl_com =
 			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile
index 39a8756c29..8bfd99448a 100644
--- a/arch/arm/mach-sunxi/dram_timings/Makefile
+++ b/arch/arm/mach-sunxi/dram_timings/Makefile
@@ -3,5 +3,5 @@ obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK)	+= lpddr3_stock.o
 obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S)	+= ddr2_v3s.o
 obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3)	+= h6_lpddr3.o
 obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333)	+= h6_ddr3_1333.o
-# currently only DDR3 is supported on H616
-obj-$(CONFIG_MACH_SUN50I_H616)		+= h616_ddr3_1333.o
+obj-$(CONFIG_SUNXI_DRAM_H616_DDR3_1333)	+= h616_ddr3_1333.o
+obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR3)	+= h616_lpddr3.o
diff --git a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c
index eea4d6abec..232b4fe2df 100644
--- a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c
+++ b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c
@@ -15,7 +15,7 @@
 #include <asm/arch/dram.h>
 #include <asm/arch/cpu.h>
 
-void mctl_set_timing_params(struct dram_para *para)
+void mctl_set_timing_params(const struct dram_para *para)
 {
 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
 			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c
new file mode 100644
index 0000000000..b6d6a68746
--- /dev/null
+++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c
@@ -0,0 +1,95 @@
+/*
+ * sun50i H616 LPDDR3 timings, as programmed by Allwinner's boot0
+ *
+ * The chips are probably able to be driven by a faster clock, but boot0
+ * uses a more conservative timing (as usual).
+ *
+ * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
+ * Based on H6 DDR3 timings:
+ * (C) Copyright 2018,2019 Arm Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/cpu.h>
+
+void mctl_set_timing_params(const struct dram_para *para)
+{
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+	u8 tccd		= 2;
+	u8 tfaw		= ns_to_t(50);
+	u8 trrd		= max(ns_to_t(6), 4);
+	u8 trcd		= ns_to_t(24);
+	u8 trc		= ns_to_t(70);
+	u8 txp		= max(ns_to_t(8), 3);
+	u8 trtp		= max(ns_to_t(8), 2);
+	u8 trp		= ns_to_t(27);
+	u8 tras		= ns_to_t(41);
+	u16 trefi	= ns_to_t(7800) / 64;
+	u16 trfc	= ns_to_t(210);
+	u16 txsr	= 88;
+
+	u8 tmrw		= 5;
+	u8 tmrd		= 5;
+	u8 tmod		= max(ns_to_t(15), 12);
+	u8 tcke		= max(ns_to_t(6), 3);
+	u8 tcksrx	= max(ns_to_t(12), 4);
+	u8 tcksre	= max(ns_to_t(12), 4);
+	u8 tckesr	= tcke + 2;
+	u8 trasmax	= (para->clk / 2) / 16;
+	u8 txs		= ns_to_t(360) / 32;
+	u8 txsdll	= 16;
+	u8 txsabort	= 4;
+	u8 txsfast	= 4;
+	u8 tcl		= 7;
+	u8 tcwl		= 4;
+	u8 t_rdata_en	= 12;
+	u8 t_wr_lat	= 6;
+
+	u8 twtp		= 16;
+	u8 twr2rd	= trtp + 9;
+	u8 trd2wr	= 13;
+
+	/* DRAM timing grabbed from tvbox with LPDDR3 memory */
+	writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
+	       &mctl_ctl->dramtmg[0]);
+	writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
+	writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
+	       &mctl_ctl->dramtmg[2]);
+	writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
+	writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
+	       &mctl_ctl->dramtmg[4]);
+	writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
+	       &mctl_ctl->dramtmg[5]);
+	/* Value suggested by ZynqMP manual and used by libdram */
+	writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
+	writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
+	       &mctl_ctl->dramtmg[8]);
+	writel(0x00020208, &mctl_ctl->dramtmg[9]);
+	writel(0xE0C05, &mctl_ctl->dramtmg[10]);
+	writel(0x440C021C, &mctl_ctl->dramtmg[11]);
+	writel(8, &mctl_ctl->dramtmg[12]);
+	writel(0xA100002, &mctl_ctl->dramtmg[13]);
+	writel(txsr, &mctl_ctl->dramtmg[14]);
+
+	writel(0x4f0112, &mctl_ctl->init[0]);
+	writel(0x420000, &mctl_ctl->init[1]);
+	writel(0xd05, &mctl_ctl->init[2]);
+	writel(0x83001c, &mctl_ctl->init[3]);
+	writel(0x00010000, &mctl_ctl->init[4]);
+
+	writel(0, &mctl_ctl->dfimisc);
+	clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
+
+	/* Configure DFI timing */
+	writel(t_wr_lat | 0x2000000 | (t_rdata_en << 16) | 0x808000,
+	       &mctl_ctl->dfitmg0);
+	writel(0x100202, &mctl_ctl->dfitmg1);
+
+	/* set refresh timing */
+	writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
+}
diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c
index d45b1faaa2..ea4eac392d 100644
--- a/arch/arm/mach-tegra/arm64-mmu.c
+++ b/arch/arm/mach-tegra/arm64-mmu.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  * (This file derived from arch/arm/mach-zynqmp/cpu.c)
  *
  * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 0df18360ca..981768bb0e 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -403,7 +403,7 @@ int dram_init_banksize(void)
  * This function is called before dram_init_banksize(), so we can't simply
  * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
  */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	ulong ram_top;
 
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-init.h b/arch/arm/mach-uniphier/dram/ddrphy-init.h
index 09981f6e06..4431f5c0ba 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-init.h
+++ b/arch/arm/mach-uniphier/dram/ddrphy-init.h
@@ -4,7 +4,7 @@
  */
 
 #ifndef ARCH_DDRPHY_INIT_H
-#define ARCH_DDRPHY_INTT_H
+#define ARCH_DDRPHY_INIT_H
 
 #include <linux/compiler.h>
 #include <linux/types.h>
diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h
index c5e4e22040..9bddb8b007 100644
--- a/arch/arm/mach-versal-net/include/mach/hardware.h
+++ b/arch/arm/mach-versal-net/include/mach/hardware.h
@@ -27,7 +27,13 @@ struct iou_scntrs_regs {
 	u32 base_frequency_id_register; /* 0x20 */
 };
 
+struct crp_regs {
+	u32 reserved0[128];
+	u32 boot_mode_usr;	/* 0x200 */
+};
+
 #define VERSAL_NET_CRL_APB_BASEADDR		0xEB5E0000
+#define VERSAL_NET_CRP_BASEADDR			0xF1260000
 #define VERSAL_NET_IOU_SCNTR_SECURE		0xEC920000
 
 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT	BIT(25)
@@ -36,6 +42,7 @@ struct iou_scntrs_regs {
 #define IOU_SCNTRS_CONTROL_EN			1
 
 #define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR)
+#define crp_base ((struct crp_regs *)VERSAL_NET_CRP_BASEADDR)
 #define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_NET_IOU_SCNTR_SECURE)
 
 #define PMC_TAP	0xF11A0000
@@ -44,11 +51,26 @@ struct iou_scntrs_regs {
 #define PMC_TAP_VERSION		(PMC_TAP + 0x4)
 # define PMC_VERSION_MASK	GENMASK(7, 0)
 # define PS_VERSION_MASK	GENMASK(15, 8)
+# define PS_VERSION_PRODUCTION	0x20
 # define RTL_VERSION_MASK	GENMASK(23, 16)
 # define PLATFORM_MASK		GENMASK(27, 24)
 # define PLATFORM_VERSION_MASK	GENMASK(31, 28)
 #define PMC_TAP_USERCODE	(PMC_TAP + 0x8)
 
+/* Bootmode setting values */
+#define BOOT_MODES_MASK	0x0000000F
+#define QSPI_MODE_24BIT	0x00000001
+#define QSPI_MODE_32BIT	0x00000002
+#define SD_MODE		0x00000003 /* sd 0 */
+#define SD_MODE1	0x00000005 /* sd 1 */
+#define EMMC_MODE	0x00000006
+#define USB_MODE	0x00000007
+#define OSPI_MODE	0x00000008
+#define SD1_LSHFT_MODE	0x0000000E /* SD1 Level shifter */
+#define JTAG_MODE	0x00000000
+#define BOOT_MODE_USE_ALT	0x100
+#define BOOT_MODE_ALT_SHIFT	12
+
 enum versal_net_platform {
 	VERSAL_NET_SILICON = 0,
 	VERSAL_NET_SPP = 1,
@@ -59,3 +81,14 @@ enum versal_net_platform {
 #define VERSAL_SLCR_BASEADDR	0xF1060000
 #define VERSAL_AXI_MUX_SEL	(VERSAL_SLCR_BASEADDR + 0x504)
 #define VERSAL_OSPI_LINEAR_MODE	BIT(1)
+
+#define FLASH_RESET_GPIO	0xc
+#define WPROT_CRP	0xF126001C
+#define RST_GPIO	0xF1260318
+#define WPROT_LPD_MIO	0xFF080728
+#define WPROT_PMC_MIO	0xF1060828
+#define BOOT_MODE_DIR	0xF1020204
+#define BOOT_MODE_OUT	0xF1020208
+#define MIO_PIN_12	0xF1060030
+#define BANK0_OUTPUT	0xF1020040
+#define BANK0_TRI	0xF1060200
diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h
index a20cf02712..23374d10a6 100644
--- a/arch/arm/mach-versal-net/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h
@@ -7,5 +7,3 @@
 #include <linux/build_bug.h>
 
 void mem_map_fill(void);
-
-int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
diff --git a/arch/arm/mach-versal/Makefile b/arch/arm/mach-versal/Makefile
index ca12e29170..864b3053d6 100644
--- a/arch/arm/mach-versal/Makefile
+++ b/arch/arm/mach-versal/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2016 - 2018 Xilinx, Inc.
-# Michal Simek <michal.simek@xilinx.com>
+# Michal Simek <michal.simek@amd.com>
 #
 
 obj-y	+= clk.o
diff --git a/arch/arm/mach-versal/clk.c b/arch/arm/mach-versal/clk.c
index 249e050cc8..5e3f44c778 100644
--- a/arch/arm/mach-versal/clk.c
+++ b/arch/arm/mach-versal/clk.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2016 - 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <common.h>
diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c
index 9dc308bbc3..e4dc305d92 100644
--- a/arch/arm/mach-versal/cpu.c
+++ b/arch/arm/mach-versal/cpu.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2016 - 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <common.h>
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h
index 3f01508ecb..757bd873fb 100644
--- a/arch/arm/mach-versal/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal/include/mach/sys_proto.h
@@ -10,7 +10,6 @@ enum {
 	TCM_SPLIT,
 };
 
+void initialize_tcm(bool mode);
 void tcm_init(u8 mode);
 void mem_map_fill(void);
-
-int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c
index 9b0518d6a2..7bd39289fa 100644
--- a/arch/arm/mach-versal/mp.c
+++ b/arch/arm/mach-versal/mp.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * (C) Copyright 2019 Xilinx, Inc.
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
  */
 
 #include <common.h>
@@ -23,7 +23,7 @@
 #define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK	0x10
 #define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK	0x1000000
 
-void set_r5_halt_mode(u8 halt, u8 mode)
+static void set_r5_halt_mode(u8 halt, u8 mode)
 {
 	u32 tmp;
 
@@ -44,7 +44,7 @@ void set_r5_halt_mode(u8 halt, u8 mode)
 	}
 }
 
-void set_r5_tcm_mode(u8 mode)
+static void set_r5_tcm_mode(u8 mode)
 {
 	u32 tmp;
 
@@ -62,7 +62,7 @@ void set_r5_tcm_mode(u8 mode)
 	writel(tmp, &rpu_base->rpu_glbl_ctrl);
 }
 
-void release_r5_reset(u8 mode)
+static void release_r5_reset(u8 mode)
 {
 	u32 tmp;
 
@@ -77,7 +77,7 @@ void release_r5_reset(u8 mode)
 	writel(tmp, &crlapb_base->rst_cpu_r5);
 }
 
-void enable_clock_r5(void)
+static void enable_clock_r5(void)
 {
 	u32 tmp;
 
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index bb1830c846..3f25554943 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2014 - 2015 Xilinx, Inc.
-# Michal Simek <michal.simek@xilinx.com>
+# Michal Simek <michal.simek@amd.com>
 
 obj-y	+= clk.o
 obj-y	+= cpu.o
diff --git a/arch/arm/mach-zynqmp/clk.c b/arch/arm/mach-zynqmp/clk.c
index 1e6e726e87..3b05f8455b 100644
--- a/arch/arm/mach-zynqmp/clk.c
+++ b/arch/arm/mach-zynqmp/clk.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <common.h>
diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c
index 26e285c24f..6ae27894ec 100644
--- a/arch/arm/mach-zynqmp/cpu.c
+++ b/arch/arm/mach-zynqmp/cpu.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <common.h>
diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c
index b9e0c6c536..dce9243892 100644
--- a/arch/arm/mach-zynqmp/handoff.c
+++ b/arch/arm/mach-zynqmp/handoff.c
@@ -2,13 +2,14 @@
 /*
  * Copyright 2016 - 2017 Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include <spl.h>
 
 /*
  * atfhandoffparams
diff --git a/arch/arm/mach-zynqmp/include/mach/clk.h b/arch/arm/mach-zynqmp/include/mach/clk.h
index cfd44c8e0f..9918d46912 100644
--- a/arch/arm/mach-zynqmp/include/mach/clk.h
+++ b/arch/arm/mach-zynqmp/include/mach/clk.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #ifndef _ASM_ARCH_CLK_H_
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index 70221e0305..634bf169c6 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #ifndef _ASM_ARCH_HARDWARE_H
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index c6733ed1bb..15b69e7771 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #ifndef _ASM_ARCH_SYS_PROTO_H
@@ -48,9 +48,6 @@ enum {
 
 unsigned int zynqmp_get_silicon_version(void);
 
-int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
-int zynqmp_mmio_read(const u32 address, u32 *value);
-
 void initialize_tcm(bool mode);
 void mem_map_fill(void);
 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c
index 7a12f4b2b6..aff9054212 100644
--- a/arch/arm/mach-zynqmp/mp.c
+++ b/arch/arm/mach-zynqmp/mp.c
@@ -1,12 +1,13 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <common.h>
 #include <cpu_func.h>
 #include <log.h>
+#include <zynqmp_firmware.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
@@ -326,6 +327,10 @@ int cpu_release(u32 nr, int argc, char *const argv[])
 		flush_dcache_all();
 
 		if (!strncmp(argv[1], "lockstep", 8)) {
+			if (nr != ZYNQMP_CORE_RPU0) {
+				printf("Lockstep mode should run on ZYNQMP_CORE_RPU0\n");
+				return 1;
+			}
 			printf("R5 lockstep mode\n");
 			set_r5_reset(nr, LOCK);
 			set_r5_tcm_mode(LOCK);
diff --git a/arch/arm/mach-zynqmp/psu_spl_init.c b/arch/arm/mach-zynqmp/psu_spl_init.c
index 5c5c7d136e..b4d7f44bbe 100644
--- a/arch/arm/mach-zynqmp/psu_spl_init.c
+++ b/arch/arm/mach-zynqmp/psu_spl_init.c
@@ -2,7 +2,7 @@
 /*
  * Copyright 2018 Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 #include <common.h>
 #include <asm/io.h>
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index b428fd5312..a0f35f36fa 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -2,7 +2,7 @@
 /*
  * Copyright 2015 - 2016 Xilinx, Inc.
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <common.h>
diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c
index ba2c228911..bef67767b4 100644
--- a/arch/m68k/cpu/mcf523x/cpu.c
+++ b/arch/m68k/cpu/mcf523x/cpu.c
@@ -12,7 +12,6 @@
 #include <init.h>
 #include <net.h>
 #include <vsprintf.h>
-#include <watchdog.h>
 #include <command.h>
 #include <netdev.h>
 #include <asm/global_data.h>
@@ -62,47 +61,6 @@ int print_cpuinfo(void)
 };
 #endif /* CONFIG_DISPLAY_CPUINFO */
 
-#if defined(CONFIG_WATCHDOG)
-/* Called by macro WATCHDOG_RESET */
-void watchdog_reset(void)
-{
-	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
-
-	/* Count register */
-	out_be16(&wdp->sr, 0x5555);
-	asm("nop");
-	out_be16(&wdp->sr, 0xaaaa);
-}
-
-int watchdog_disable(void)
-{
-	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
-
-	/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
-	/* halted watchdog timer */
-	setbits_be16(&wdp->cr, WTM_WCR_HALTED);
-
-	puts("WATCHDOG:disabled\n");
-	return (0);
-}
-
-int watchdog_init(void)
-{
-	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
-	u32 wdog_module = 0;
-
-	/* set timeout and enable watchdog */
-	wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT_MSECS);
-	wdog_module |= (wdog_module / 8192);
-	out_be16(&wdp->mr, wdog_module);
-
-	out_be16(&wdp->cr, WTM_WCR_EN);
-	puts("WATCHDOG:enabled\n");
-
-	return (0);
-}
-#endif				/* CONFIG_WATCHDOG */
-
 #if defined(CONFIG_MCFFEC)
 /* Default initializations for MCFFEC controllers.  To override,
  * create a board-specific function called:
diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c
index d7cbf11e25..5042a38b3e 100644
--- a/arch/m68k/cpu/mcf52x2/cpu.c
+++ b/arch/m68k/cpu/mcf52x2/cpu.c
@@ -17,7 +17,6 @@
 #include <init.h>
 #include <net.h>
 #include <vsprintf.h>
-#include <watchdog.h>
 #include <command.h>
 #include <asm/global_data.h>
 #include <asm/immap.h>
@@ -53,51 +52,7 @@ int print_cpuinfo(void)
 	return 0;
 };
 #endif /* CONFIG_DISPLAY_CPUINFO */
-
-#if defined(CONFIG_WATCHDOG)
-/* Called by macro WATCHDOG_RESET */
-void watchdog_reset(void)
-{
-	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
-	out_be16(&wdt->sr, 0x5555);
-	out_be16(&wdt->sr, 0xaaaa);
-}
-
-int watchdog_disable(void)
-{
-	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
-	/* reset watchdog counter */
-	out_be16(&wdt->sr, 0x5555);
-	out_be16(&wdt->sr, 0xaaaa);
-	/* disable watchdog timer */
-	out_be16(&wdt->cr, 0);
-
-	puts("WATCHDOG:disabled\n");
-	return (0);
-}
-
-int watchdog_init(void)
-{
-	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
-	/* disable watchdog */
-	out_be16(&wdt->cr, 0);
-
-	/* set timeout and enable watchdog */
-	out_be16(&wdt->mr,
-		(CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
-
-	/* reset watchdog counter */
-	out_be16(&wdt->sr, 0x5555);
-	out_be16(&wdt->sr, 0xaaaa);
-
-	puts("WATCHDOG:enabled\n");
-	return (0);
-}
-#endif				/* #ifdef CONFIG_WATCHDOG */
-#endif				/* #ifdef CONFIG_M5208 */
+#endif /* #ifdef CONFIG_M5208 */
 
 #ifdef  CONFIG_M5271
 #if defined(CONFIG_DISPLAY_CPUINFO)
diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c
index 548cbca36a..18d20a8926 100644
--- a/arch/m68k/cpu/mcf532x/cpu.c
+++ b/arch/m68k/cpu/mcf532x/cpu.c
@@ -12,7 +12,6 @@
 #include <init.h>
 #include <net.h>
 #include <vsprintf.h>
-#include <watchdog.h>
 #include <command.h>
 #include <netdev.h>
 #include <asm/global_data.h>
@@ -102,49 +101,6 @@ int print_cpuinfo(void)
 };
 #endif /* CONFIG_DISPLAY_CPUINFO */
 
-#if defined(CONFIG_WATCHDOG)
-/* Called by macro WATCHDOG_RESET */
-void watchdog_reset(void)
-{
-	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
-
-	/* Count register */
-	out_be16(&wdp->sr, 0x5555);
-	out_be16(&wdp->sr, 0xaaaa);
-}
-
-int watchdog_disable(void)
-{
-	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
-
-	/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
-	/* halted watchdog timer */
-	setbits_be16(&wdp->cr, WTM_WCR_HALTED);
-
-	puts("WATCHDOG:disabled\n");
-	return (0);
-}
-
-int watchdog_init(void)
-{
-	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
-	u32 wdog_module = 0;
-
-	/* set timeout and enable watchdog */
-	wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT_MSECS);
-#ifdef CONFIG_M5329
-	out_be16(&wdp->mr, wdog_module / 8192);
-#else
-	out_be16(&wdp->mr, wdog_module / 4096);
-#endif
-
-	out_be16(&wdp->cr, WTM_WCR_EN);
-	puts("WATCHDOG:enabled\n");
-
-	return (0);
-}
-#endif				/* CONFIG_WATCHDOG */
-
 #if defined(CONFIG_MCFFEC)
 /* Default initializations for MCFFEC controllers.  To override,
  * create a board-specific function called:
diff --git a/arch/m68k/dts/M5208EVBE.dts b/arch/m68k/dts/M5208EVBE.dts
index 1c32718af4..ec203e8b69 100644
--- a/arch/m68k/dts/M5208EVBE.dts
+++ b/arch/m68k/dts/M5208EVBE.dts
@@ -15,6 +15,11 @@
 	};
 };
 
+&wdog0 {
+	timeout-sec = <32>;
+	status = "okay";
+};
+
 &uart0 {
 	bootph-all;
 	status = "okay";
diff --git a/arch/m68k/dts/mcf5208.dtsi b/arch/m68k/dts/mcf5208.dtsi
index 9392facfa8..c61dbf3557 100644
--- a/arch/m68k/dts/mcf5208.dtsi
+++ b/arch/m68k/dts/mcf5208.dtsi
@@ -16,6 +16,12 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		wdog0: watchdog@fc08c000 {
+			compatible = "fsl,mcf5208-wdt";
+			reg = <0xfc08c000 0x10>;
+			status = "disabled";
+		};
+
 		uart0: uart@fc060000 {
 			compatible = "fsl,mcf-uart";
 			reg = <0xfc060000 0x40>;
diff --git a/arch/m68k/dts/mcf523x.dtsi b/arch/m68k/dts/mcf523x.dtsi
index 41c7b9b2d1..cae7b4f861 100644
--- a/arch/m68k/dts/mcf523x.dtsi
+++ b/arch/m68k/dts/mcf523x.dtsi
@@ -23,6 +23,12 @@
 			ranges = <0x00000000 0x40000000 0x40000000>;
 			reg = <0x40000000 0x40000000>;
 
+			wdog0: watchdog@140000 {
+				compatible = "fsl,mcf5208-wdt";
+				reg = <0x140000 0x10>;
+				status = "disabled";
+			};
+
 			uart0: uart@200 {
 				compatible = "fsl,mcf-uart";
 				reg = <0x200 0x40>;
diff --git a/arch/m68k/dts/mcf5271.dtsi b/arch/m68k/dts/mcf5271.dtsi
index fc82bd3c24..5acf6994af 100644
--- a/arch/m68k/dts/mcf5271.dtsi
+++ b/arch/m68k/dts/mcf5271.dtsi
@@ -23,6 +23,12 @@
 			ranges = <0x00000000 0x40000000 0x40000000>;
 			reg = <0x40000000 0x40000000>;
 
+			wdog0: watchdog@140000 {
+				compatible = "fsl,mcf5208-wdt";
+				reg = <0x140000 0x10>;
+				status = "disabled";
+			};
+
 			uart0: uart@200 {
 				compatible = "fsl,mcf-uart";
 				reg = <0x200 0x40>;
diff --git a/arch/m68k/dts/mcf5275.dtsi b/arch/m68k/dts/mcf5275.dtsi
index 402517cdec..3df17b445c 100644
--- a/arch/m68k/dts/mcf5275.dtsi
+++ b/arch/m68k/dts/mcf5275.dtsi
@@ -24,6 +24,12 @@
 			ranges = <0x00000000 0x40000000 0x40000000>;
 			reg = <0x40000000 0x40000000>;
 
+			wdog0: watchdog@140000 {
+				compatible = "fsl,mcf5208-wdt";
+				reg = <0x140000 0x10>;
+				status = "disabled";
+			};
+
 			uart0: uart@200 {
 				compatible = "fsl,mcf-uart";
 				reg = <0x200 0x40>;
diff --git a/arch/m68k/dts/mcf5282.dtsi b/arch/m68k/dts/mcf5282.dtsi
index 883c0d0324..640c1a32e4 100644
--- a/arch/m68k/dts/mcf5282.dtsi
+++ b/arch/m68k/dts/mcf5282.dtsi
@@ -23,6 +23,12 @@
 			ranges = <0x00000000 0x40000000 0x40000000>;
 			reg = <0x40000000 0x40000000>;
 
+			wdog0: watchdog@140000 {
+				compatible = "fsl,mcf5282-wdt";
+				reg = <0x140000 0x10>;
+				status = "disabled";
+			};
+
 			uart0: uart@200 {
 				compatible = "fsl,mcf-uart";
 				reg = <0x200 0x40>;
diff --git a/arch/m68k/dts/mcf5329.dtsi b/arch/m68k/dts/mcf5329.dtsi
index 7501cc4b01..991985e48c 100644
--- a/arch/m68k/dts/mcf5329.dtsi
+++ b/arch/m68k/dts/mcf5329.dtsi
@@ -16,6 +16,12 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		wdog0: watchdog@fc098000 {
+			compatible = "fsl,mcf5208-wdt";
+			reg = <0xfc08c000 0x10>;
+			status = "disabled";
+		};
+
 		uart0: uart@fc060000 {
 			compatible = "fsl,mcf-uart";
 			reg = <0xfc060000 0x40>;
diff --git a/arch/m68k/dts/mcf537x.dtsi b/arch/m68k/dts/mcf537x.dtsi
index 338b8b4583..4fa0f4bc3d 100644
--- a/arch/m68k/dts/mcf537x.dtsi
+++ b/arch/m68k/dts/mcf537x.dtsi
@@ -16,6 +16,12 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		wdog0: watchdog@fc098000 {
+			compatible = "fsl,mcf5208-wdt";
+			reg = <0xfc08c000 0x10>;
+			status = "disabled";
+		};
+
 		uart0: uart@fc060000 {
 			compatible = "fsl,mcf-uart";
 			reg = <0xfc060000 0x40>;
diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h
index 328aa0c316..7fb482abc3 100644
--- a/arch/m68k/include/asm/unaligned.h
+++ b/arch/m68k/include/asm/unaligned.h
@@ -1,15 +1,2 @@
-#ifndef _ASM_M68K_UNALIGNED_H
-#define _ASM_M68K_UNALIGNED_H
-
-#ifdef CONFIG_COLDFIRE
-#include <linux/unaligned/be_byteshift.h>
-#else
-#include <linux/unaligned/access_ok.h>
-#endif
-
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned	__get_unaligned_be
-#define put_unaligned	__put_unaligned_be
-
-#endif /* _ASM_M68K_UNALIGNED_H */
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <asm-generic/unaligned.h>
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index eaa095ba99..c21beafdb8 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -2,7 +2,7 @@
 /*
  * (C) Copyright 2013 - 2014 Xilinx, Inc
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <common.h>
diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds
index 4ac5a21524..09abbea84d 100644
--- a/arch/microblaze/cpu/u-boot-spl.lds
+++ b/arch/microblaze/cpu/u-boot-spl.lds
@@ -2,7 +2,7 @@
 /*
  * (C) Copyright 2013 - 2014 Xilinx, Inc
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <asm-offsets.h>
@@ -54,6 +54,7 @@ SECTIONS
 		__bss_end = .;
 	}
 	_end = . ;
+	_image_binary_end = .;
 }
 
 #if defined(CONFIG_SPL_MAX_FOOTPRINT)
diff --git a/arch/microblaze/include/asm/spl.h b/arch/microblaze/include/asm/spl.h
index 350d283124..7557dc2a5a 100644
--- a/arch/microblaze/include/asm/spl.h
+++ b/arch/microblaze/include/asm/spl.h
@@ -2,7 +2,7 @@
 /*
  * (C) Copyright 2013 - 2014 Xilinx, Inc
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #ifndef _ASM_MICROBLAZE_SPL_H_
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index b304026a67..f0e20da28f 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -15,7 +15,7 @@
 #if !CONFIG_IS_ENABLED(SYSRESET)
 void __weak _machine_restart(void)
 {
-	fprintf(stderr, "*** reset failed ***\n");
+	puts("*** reset failed ***\n");
 
 	while (1)
 		/* NOP */;
diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h
index debb9cf7ab..7fb482abc3 100644
--- a/arch/mips/include/asm/unaligned.h
+++ b/arch/mips/include/asm/unaligned.h
@@ -1,23 +1,2 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef _ASM_MIPS_UNALIGNED_H
-#define _ASM_MIPS_UNALIGNED_H
-
-#include <linux/compiler.h>
-#if defined(__MIPSEB__)
-#define get_unaligned	__get_unaligned_be
-#define put_unaligned	__put_unaligned_be
-#elif defined(__MIPSEL__)
-#define get_unaligned	__get_unaligned_le
-#define put_unaligned	__put_unaligned_le
-#else
-#error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
-#endif
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-#endif /* _ASM_MIPS_UNALIGNED_H */
+#include <asm-generic/unaligned.h>
diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c
index 15d1eff2ba..676c305fd3 100644
--- a/arch/mips/mach-jz47xx/jz4780/jz4780.c
+++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c
@@ -76,7 +76,7 @@ void board_init_f(ulong dummy)
 }
 #endif /* CONFIG_SPL_BUILD */
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024);
 }
diff --git a/arch/mips/mach-octeon/cvmx-pko3-queue.c b/arch/mips/mach-octeon/cvmx-pko3-queue.c
index e28afdf8dd..53f2e4dd18 100644
--- a/arch/mips/mach-octeon/cvmx-pko3-queue.c
+++ b/arch/mips/mach-octeon/cvmx-pko3-queue.c
@@ -761,7 +761,7 @@ int cvmx_pko3_pq_config(unsigned int node, unsigned int mac_num,
  * The Scheduler Queues in Levels 3 to 5 and Descriptor Queues are
  * configured one-to-one or many-to-one to a single parent Scheduler
  * Queues. The level of the parent SQ is specified in an argument,
- * as well as the number of childer to attach to the specific parent.
+ * as well as the number of children to attach to the specific parent.
  * The children can have fair round-robin or priority-based scheduling
  * when multiple children are assigned a single parent.
  *
diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c
index 85cb084c13..5b1311d8b5 100644
--- a/arch/mips/mach-octeon/dram.c
+++ b/arch/mips/mach-octeon/dram.c
@@ -77,7 +77,7 @@ phys_size_t get_effective_memsize(void)
 	return UBOOT_RAM_SIZE_MAX;
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	if (IS_ENABLED(CONFIG_RAM_OCTEON)) {
 		/* Map a maximum of 256MiB - return not size but address */
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pko3-queue.h b/arch/mips/mach-octeon/include/mach/cvmx-pko3-queue.h
index b3f61d75f2..3931191fe2 100644
--- a/arch/mips/mach-octeon/include/mach/cvmx-pko3-queue.h
+++ b/arch/mips/mach-octeon/include/mach/cvmx-pko3-queue.h
@@ -6,6 +6,8 @@
 #ifndef __CVMX_PKO3_QUEUE_H__
 #define __CVMX_PKO3_QUEUE_H__
 
+enum cvmx_pko3_level_e;
+
 /**
  * @INTERNAL
  *
@@ -46,11 +48,10 @@ int cvmx_pko3_get_port_queue(int xiface, int index);
  * The children can have fair round-robin or priority-based scheduling
  * when multiple children are assigned a single parent.
  *
- * @param node is the OCI node location for the queues to be configured
- * @param parent_level is the level of the parent queue, 2 to 5.
+ * @param node on which to operate
+ * @param child_level  is the level of the child queue
  * @param parent_queue is the number of the parent Scheduler Queue
  * @param child_base is the number of the first child SQ or DQ to assign to
- * @param parent
  * @param child_count is the number of consecutive children to assign
  * @param stat_prio_count is the priority setting for the children L2 SQs
  *
@@ -65,8 +66,10 @@ int cvmx_pko3_get_port_queue(int xiface, int index);
  *
  * Note: this function supports the configuration of node-local unit.
  */
-int cvmx_pko3_sq_config_children(unsigned int node, unsigned int parent_level,
-				 unsigned int parent_queue, unsigned int child_base,
+int cvmx_pko3_sq_config_children(unsigned int node,
+				 enum cvmx_pko3_level_e child_level,
+				 unsigned int parent_queue,
+				 unsigned int child_base,
 				 unsigned int child_count, int stat_prio_count);
 
 /*
diff --git a/arch/powerpc/dts/t1023si-post.dtsi b/arch/powerpc/dts/t1023si-post.dtsi
index 6f666a1554..0cd34fe488 100644
--- a/arch/powerpc/dts/t1023si-post.dtsi
+++ b/arch/powerpc/dts/t1023si-post.dtsi
@@ -3,13 +3,15 @@
  * T1023 Silicon/SoC Device Tree Source (post include)
  *
  * Copyright 2014 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2023 NXP
  *
  */
 
 &soc {
 
 /include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-gpio-1.dtsi"
 /include/ "qoriq-gpio-2.dtsi"
diff --git a/arch/powerpc/dts/t1024rdb-u-boot.dtsi b/arch/powerpc/dts/t1024rdb-u-boot.dtsi
new file mode 100644
index 0000000000..b50b922aeb
--- /dev/null
+++ b/arch/powerpc/dts/t1024rdb-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+&serial0 {
+	bootph-all;
+};
+
+&serial1 {
+	bootph-all;
+};
+
+#include "u-boot.dtsi"
diff --git a/arch/powerpc/dts/t1024rdb.dts b/arch/powerpc/dts/t1024rdb.dts
index eeba99f84d..afaf90cb59 100644
--- a/arch/powerpc/dts/t1024rdb.dts
+++ b/arch/powerpc/dts/t1024rdb.dts
@@ -3,7 +3,7 @@
  * T1024RDB Device Tree Source
  *
  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2023 NXP
  */
 
 /include/ "t102x.dtsi"
@@ -17,6 +17,10 @@
 
 	aliases {
 		sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
 		spi0 = &espi0;
 	};
 
diff --git a/arch/powerpc/dts/t1042d4rdb-u-boot.dtsi b/arch/powerpc/dts/t1042d4rdb-u-boot.dtsi
new file mode 100644
index 0000000000..b50b922aeb
--- /dev/null
+++ b/arch/powerpc/dts/t1042d4rdb-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+&serial0 {
+	bootph-all;
+};
+
+&serial1 {
+	bootph-all;
+};
+
+#include "u-boot.dtsi"
diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts
index 5e9fab7a10..0230d3ba67 100644
--- a/arch/powerpc/dts/t1042d4rdb.dts
+++ b/arch/powerpc/dts/t1042d4rdb.dts
@@ -3,7 +3,7 @@
  * T1042D4RDB Device Tree Source
  *
  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2021 NXP
+ * Copyright 2019-2023 NXP
  */
 
 /include/ "t104x.dtsi"
@@ -17,6 +17,10 @@
 
 	aliases {
 		spi0 = &espi0;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
 	};
 };
 
diff --git a/arch/powerpc/dts/t1042si-post.dtsi b/arch/powerpc/dts/t1042si-post.dtsi
index eebbbaf0e1..9f4fd7216a 100644
--- a/arch/powerpc/dts/t1042si-post.dtsi
+++ b/arch/powerpc/dts/t1042si-post.dtsi
@@ -3,11 +3,13 @@
  * T1042 Silicon/SoC Device Tree Source (post include)
  *
  * Copyright 2013 - 2014 Freescale Semiconductor Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2023 NXP
  *
  */
 &soc {
 /include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-gpio-1.dtsi"
 /include/ "qoriq-gpio-2.dtsi"
diff --git a/arch/powerpc/dts/t2080rdb-u-boot.dtsi b/arch/powerpc/dts/t2080rdb-u-boot.dtsi
new file mode 100644
index 0000000000..b50b922aeb
--- /dev/null
+++ b/arch/powerpc/dts/t2080rdb-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+&serial0 {
+	bootph-all;
+};
+
+&serial1 {
+	bootph-all;
+};
+
+#include "u-boot.dtsi"
diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts
index 4de814ea8d..c0b0bd6f2c 100644
--- a/arch/powerpc/dts/t2080rdb.dts
+++ b/arch/powerpc/dts/t2080rdb.dts
@@ -3,7 +3,7 @@
  * T2080RDB Device Tree Source
  *
  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2021 NXP
+ * Copyright 2019-2023 NXP
  */
 
 /include/ "t2080.dtsi"
@@ -17,6 +17,10 @@
 
 	aliases {
 		spi0 = &espi0;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
 	};
 };
 
diff --git a/arch/powerpc/dts/t2080si-post.dtsi b/arch/powerpc/dts/t2080si-post.dtsi
index c06526b3db..46053c6b87 100644
--- a/arch/powerpc/dts/t2080si-post.dtsi
+++ b/arch/powerpc/dts/t2080si-post.dtsi
@@ -3,12 +3,14 @@
  * T2080 Silicon/SoC Device Tree Source (post include)
  *
  * Copyright 2013 Freescale Semiconductor Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2023 NXP
  *
  */
 &soc {
 
 /include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-gpio-1.dtsi"
 /include/ "qoriq-gpio-2.dtsi"
diff --git a/arch/powerpc/dts/t4240rdb-u-boot.dtsi b/arch/powerpc/dts/t4240rdb-u-boot.dtsi
new file mode 100644
index 0000000000..b50b922aeb
--- /dev/null
+++ b/arch/powerpc/dts/t4240rdb-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+&serial0 {
+	bootph-all;
+};
+
+&serial1 {
+	bootph-all;
+};
+
+#include "u-boot.dtsi"
diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts
index b3251e330d..c33b4982ba 100644
--- a/arch/powerpc/dts/t4240rdb.dts
+++ b/arch/powerpc/dts/t4240rdb.dts
@@ -3,7 +3,7 @@
  * T4240RDB Device Tree Source
  *
  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2021 NXP
+ * Copyright 2019-2023 NXP
  */
 
 /include/ "t4240.dtsi"
@@ -17,6 +17,10 @@
 
 	aliases {
 		spi0 = &espi0;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
 	};
 };
 
diff --git a/arch/powerpc/dts/t4240si-post.dtsi b/arch/powerpc/dts/t4240si-post.dtsi
index 9fa99ae771..bd93345d38 100644
--- a/arch/powerpc/dts/t4240si-post.dtsi
+++ b/arch/powerpc/dts/t4240si-post.dtsi
@@ -3,11 +3,13 @@
  * T4240 Silicon/SoC Device Tree Source (post include)
  *
  * Copyright 2012 - 2015 Freescale Semiconductor Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2023 NXP
  *
  */
 &soc {
 /include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-gpio-1.dtsi"
 /include/ "qoriq-gpio-2.dtsi"
diff --git a/arch/powerpc/include/asm/mc146818rtc.h b/arch/powerpc/include/asm/mc146818rtc.h
deleted file mode 100644
index 5f806c4ec2..0000000000
--- a/arch/powerpc/include/asm/mc146818rtc.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Machine dependent access functions for RTC registers.
- */
-#ifndef __ASM_PPC_MC146818RTC_H
-#define __ASM_PPC_MC146818RTC_H
-
-#include <asm/io.h>
-
-#ifndef RTC_PORT
-#define RTC_PORT(x) (0x70 + (x))
-#define RTC_ALWAYS_BCD  1   /* RTC operates in binary mode */
-#endif
-
-/*
- * The yet supported machines all access the RTC index register via
- * an ISA port access but the way to access the date register differs ...
- */
-#define CMOS_READ(addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-inb_p(RTC_PORT(1)); \
-})
-#define CMOS_WRITE(val, addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-outb_p((val),RTC_PORT(1)); \
-})
-
-#endif /* __ASM_PPC_MC146818RTC_H */
diff --git a/arch/powerpc/include/asm/pci_io.h b/arch/powerpc/include/asm/pci_io.h
deleted file mode 100644
index 9b738c383f..0000000000
--- a/arch/powerpc/include/asm/pci_io.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* originally from linux source (asm-ppc/io.h).
- * Sanity added by Rob Taylor, Flying Pig Systems, 2000
- */
-#ifndef _PCI_IO_H_
-#define _PCI_IO_H_
-
-#include "io.h"
-
-
-#define pci_read_le16(addr, dest) \
-    __asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \
-		  "r" (addr), "m" (*addr));
-
-#define pci_write_le16(addr, val) \
-    __asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \
-		  "r" (val), "r" (addr));
-
-
-#define pci_read_le32(addr, dest) \
-    __asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \
-		 "r" (addr), "m" (*addr));
-
-#define pci_write_le32(addr, val) \
-__asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \
-		 "r" (val), "r" (addr));
-
-#define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr))
-#define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
-
-#if !defined(__BIG_ENDIAN)
-#define pci_readw(addr,b) ((b) = *(volatile u16 *) (addr))
-#define pci_readl(addr,b) ((b) = *(volatile u32 *) (addr))
-#define pci_writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
-#define pci_writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
-#else
-#define pci_readw(addr,b) pci_read_le16((volatile u16 *)(addr),(b))
-#define pci_readl(addr,b) pci_read_le32((volatile u32 *)(addr),(b))
-#define pci_writew(b,addr) pci_write_le16((volatile u16 *)(addr),(b))
-#define pci_writel(b,addr) pci_write_le32((volatile u32 *)(addr),(b))
-#endif
-
-
-#endif /* _PCI_IO_H_ */
diff --git a/arch/powerpc/include/asm/unaligned.h b/arch/powerpc/include/asm/unaligned.h
index 5f1b1e3c21..7fb482abc3 100644
--- a/arch/powerpc/include/asm/unaligned.h
+++ b/arch/powerpc/include/asm/unaligned.h
@@ -1,16 +1,2 @@
-#ifndef _ASM_POWERPC_UNALIGNED_H
-#define _ASM_POWERPC_UNALIGNED_H
-
-#ifdef __KERNEL__
-
-/*
- * The PowerPC can do unaligned accesses itself in big endian mode.
- */
-#include <linux/unaligned/access_ok.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned	__get_unaligned_be
-#define put_unaligned	__put_unaligned_be
-
-#endif	/* __KERNEL__ */
-#endif	/* _ASM_POWERPC_UNALIGNED_H */
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <asm-generic/unaligned.h>
diff --git a/arch/powerpc/lib/Kconfig b/arch/powerpc/lib/Kconfig
index b30b5edf7c..d38ba45a99 100644
--- a/arch/powerpc/lib/Kconfig
+++ b/arch/powerpc/lib/Kconfig
@@ -1,9 +1,9 @@
 config CACHE_FLUSH_WATCHDOG_THRESHOLD
-	int "Bytes to flush between WATCHDOG_RESET calls"
-	default 0
+	int "Bytes to flush between schedule() calls"
+	default 4096
 	help
 	  The flush_cache() function periodically, and by default for
-	  every cache line, calls WATCHDOG_RESET(). When flushing a
-	  large area, that may add a significant amount of
+	  every 4k block, calls schedule() to reset watchdog. When
+	  flushing a large area, that may add a significant amount of
 	  overhead. This option allows you to set a threshold for how
-	  many bytes to flush between each WATCHDOG_RESET call.
+	  many bytes to flush between each schedule() call.
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f6ed05906a..6771d8d919 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED
 config TARGET_STARFIVE_VISIONFIVE2
 	bool "Support StarFive VisionFive2 Board"
 
+config TARGET_TH1520_LPI4A
+	bool "Support Sipeed's TH1520 Lichee PI 4A Board"
+	select SYS_CACHE_SHIFT_6
+
 config TARGET_SIPEED_MAIX
 	bool "Support Sipeed Maix Board"
 	select SYS_CACHE_SHIFT_6
@@ -60,12 +64,21 @@ config SPL_SYS_DCACHE_OFF
 	help
 	  Do not enable data cache in SPL.
 
+config SPL_ZERO_MEM_BEFORE_USE
+	bool "Zero memory before use"
+	depends on SPL
+	default n
+	help
+	  Zero stack/GD/malloc area in SPL before using them, this is needed for
+	  Sifive core devices that uses L2 cache to store SPL.
+
 # board-specific options below
 source "board/AndesTech/ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/unleashed/Kconfig"
 source "board/sifive/unmatched/Kconfig"
+source "board/thead/th1520_lpi4a/Kconfig"
 source "board/openpiton/riscv64/Kconfig"
 source "board/sipeed/maix/Kconfig"
 source "board/starfive/visionfive2/Kconfig"
@@ -185,18 +198,22 @@ config DMA_ADDR_T_64BIT
 	bool
 	default y if 64BIT
 
-config SIFIVE_CLINT
+config RISCV_ACLINT
 	bool
 	depends on RISCV_MMODE
+	select REGMAP
+	select SYSCON
 	help
-	  The SiFive CLINT block holds memory-mapped control and status registers
+	  The RISC-V ACLINT block holds memory-mapped control and status registers
 	  associated with software and timer interrupts.
 
-config SPL_SIFIVE_CLINT
+config SPL_RISCV_ACLINT
 	bool
 	depends on SPL_RISCV_MMODE
+	select SPL_REGMAP
+	select SPL_SYSCON
 	help
-	  The SiFive CLINT block holds memory-mapped control and status registers
+	  The RISC-V ACLINT block holds memory-mapped control and status registers
 	  associated with software and timer interrupts.
 
 config SIFIVE_CACHE
diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 1604b412b4..c68209d8fb 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -11,7 +11,7 @@ config SIFIVE_FU540
 	imply CPU
 	imply CPU_RISCV
 	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
-	imply SPL_SIFIVE_CLINT
+	imply SPL_RISCV_ACLINT
 	imply CMD_CPU
 	imply SPL_CPU
 	imply SPL_OPENSBI
diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c
index 44e11bd56c..94d8018407 100644
--- a/arch/riscv/cpu/fu540/dram.c
+++ b/arch/riscv/cpu/fu540/dram.c
@@ -21,7 +21,7 @@ int dram_init_banksize(void)
 	return fdtdec_setup_memory_banksize();
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	/*
 	 * Ensure that we run from first 4GB so that all
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
index 3e0c1fddc8..d7ca968717 100644
--- a/arch/riscv/cpu/fu740/Kconfig
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -11,7 +11,7 @@ config SIFIVE_FU740
 	imply CPU
 	imply CPU_RISCV
 	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
-	imply SPL_SIFIVE_CLINT
+	imply SPL_RISCV_ACLINT
 	imply CMD_CPU
 	imply SPL_CPU
 	imply SPL_OPENSBI
diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c
index d6d4a41d25..8657fcd165 100644
--- a/arch/riscv/cpu/fu740/dram.c
+++ b/arch/riscv/cpu/fu740/dram.c
@@ -20,7 +20,7 @@ int dram_init_banksize(void)
 	return fdtdec_setup_memory_banksize();
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 #ifdef CONFIG_64BIT
 	/*
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index e025134b23..2baba22992 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -6,11 +6,12 @@ config GENERIC_RISCV
 	bool
 	select BINMAN if SPL
 	select ARCH_EARLY_INIT_R
+	select SYS_CACHE_SHIFT_6
 	imply CPU
 	imply CPU_RISCV
 	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
-	imply SIFIVE_CLINT if RISCV_MMODE
-	imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
+	imply RISCV_ACLINT if RISCV_MMODE
+	imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
 	imply CMD_CPU
 	imply SPL_CPU
 	imply SPL_OPENSBI
diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 44e11bd56c..94d8018407 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -21,7 +21,7 @@ int dram_init_banksize(void)
 	return fdtdec_setup_memory_banksize();
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	/*
 	 * Ensure that we run from first 4GB so that all
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 3f145415eb..8469ee7de5 100644
--- a/arch/riscv/cpu/jh7110/Kconfig
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -13,6 +13,8 @@ config STARFIVE_JH7110
 	select SUPPORT_SPL
 	select SPL_RAM if SPL
 	select SPL_STARFIVE_DDR
+	select SYS_CACHE_SHIFT_6
+	select SPL_ZERO_MEM_BEFORE_USE
 	select PINCTRL_STARFIVE_JH7110
 	imply MMC
 	imply MMC_BROKEN_CD
@@ -25,4 +27,4 @@ config STARFIVE_JH7110
 	imply SPL_CPU
 	imply SPL_LOAD_FIT
 	imply SPL_OPENSBI
-	imply SPL_SIFIVE_CLINT
+	imply SPL_RISCV_ACLINT
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
index 2ad3f2044a..1a9fa46d14 100644
--- a/arch/riscv/cpu/jh7110/dram.c
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -21,7 +21,7 @@ int dram_init_banksize(void)
 	return fdtdec_setup_memory_banksize();
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	/*
 	 * Ensure that we run from first 4GB so that all
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 104f0fe949..4047b10efe 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -3,19 +3,48 @@
  * Copyright (C) 2022 StarFive Technology Co., Ltd.
  * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
  */
-
+#include <common.h>
+#include <asm/arch/eeprom.h>
 #include <asm/csr.h>
 #include <asm/sections.h>
 #include <dm.h>
+#include <linux/sizes.h>
 #include <log.h>
+#include <init.h>
 
 #define CSR_U74_FEATURE_DISABLE	0x7c1
-#define L2_LIM_MEM_END	0x81FFFFFUL
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool check_ddr_size(phys_size_t size)
+{
+	switch (size) {
+	case SZ_2:
+	case SZ_4:
+	case SZ_8:
+	case SZ_16:
+		return true;
+	default:
+		return false;
+	}
+}
 
 int spl_soc_init(void)
 {
 	int ret;
 	struct udevice *dev;
+	phys_size_t size;
+
+	ret = fdtdec_setup_mem_size_base();
+	if (ret)
+		return ret;
+
+	/* Read the definition of the DDR size from eeprom, and if not,
+	 * use the definition in DT
+	 */
+	size = (get_ddr_size_from_eeprom() >> 16) & 0xFF;
+	if (check_ddr_size(size))
+		gd->ram_size = size << 30;
 
 	/* DDR init */
 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
@@ -29,9 +58,6 @@ int spl_soc_init(void)
 
 void harts_early_init(void)
 {
-	ulong *ptr;
-	u8 *tmp;
-	ulong len, remain;
 	/*
 	 * Feature Disable CSR
 	 *
@@ -40,25 +66,4 @@ void harts_early_init(void)
 	 */
 	if (CONFIG_IS_ENABLED(RISCV_MMODE))
 		csr_write(CSR_U74_FEATURE_DISABLE, 0);
-
-	/* clear L2 LIM  memory
-	 * set __bss_end to 0x81FFFFF region to zero
-	 * The L2 Cache Controller supports ECC. ECC is applied to SRAM.
-	 * If it is not cleared, the ECC part is invalid, and an ECC error
-	 * will be reported when reading data.
-	 */
-	ptr = (ulong *)&__bss_end;
-	len = L2_LIM_MEM_END - (ulong)&__bss_end;
-	remain = len % sizeof(ulong);
-	len /= sizeof(ulong);
-
-	while (len--)
-		*ptr++ = 0;
-
-	/* clear the remain bytes */
-	if (remain) {
-		tmp = (u8 *)ptr;
-		while (remain--)
-			*tmp++ = 0;
-	}
 }
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index dad22bfea8..30cf674370 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -91,16 +91,47 @@ _start:
  * Set stackpointer in internal/ex RAM to call board_init_f
  */
 call_board_init_f:
-	li	t0, -16
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
-	li	t1, CONFIG_SPL_STACK
+	li	t0, CONFIG_SPL_STACK
 #else
-	li	t1, SYS_INIT_SP_ADDR
+	li	t0, SYS_INIT_SP_ADDR
+#endif
+	and	t0, t0, -16		/* force 16 byte alignment */
+
+	/* setup stack */
+#if CONFIG_IS_ENABLED(SMP)
+	/* tp: hart id */
+	slli	t1, tp, CONFIG_STACK_SIZE_SHIFT
+	sub	sp, t0, t1
+#else
+	mv	sp, t0
+#endif
+/*
+ * Now sp points to the right stack belonging to current CPU.
+ * It's essential before any function call, otherwise, we get data-race.
+ */
+
+/* clear stack if necessary */
+#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
+clear_stack:
+	li	t1, 1
+	slli	t1, t1, CONFIG_STACK_SIZE_SHIFT
+	sub	t1, sp, t1
+clear_stack_loop:
+	SREG	zero, 0(t1)		/* t1 is always 16 byte aligned */
+	addi	t1, t1, REGBYTES
+	blt	t1, sp, clear_stack_loop
 #endif
-	and	sp, t1, t0		/* force 16 byte alignment */
 
 call_board_init_f_0:
-	mv	a0, sp
+	/* find top of reserve space */
+#if CONFIG_IS_ENABLED(SMP)
+	li	t1, CONFIG_NR_CPUS
+#else
+	li	t1, 1
+#endif
+	slli	t1, t1, CONFIG_STACK_SIZE_SHIFT
+	sub	a0, t0, t1		/* t1 -> size of all CPU stacks */
 	jal	board_init_f_alloc_reserve
 
 	/*
@@ -109,14 +140,6 @@ call_board_init_f_0:
 	 */
 	mv	s0, a0
 
-	/* setup stack */
-#if CONFIG_IS_ENABLED(SMP)
-	/* tp: hart id */
-	slli	t0, tp, CONFIG_STACK_SIZE_SHIFT
-	sub	sp, a0, t0
-#else
-	mv	sp, a0
-#endif
 
 	/* Configure proprietary settings and customized CSRs of harts */
 call_harts_early_init:
diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index 15b5cbc585..2ffe6ba3c8 100644
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -48,7 +48,7 @@ SECTIONS
 		KEEP(*(SORT(__u_boot_list*)));
 	}
 
-	. = ALIGN(4);
+	. = ALIGN(8);
 
 	.efi_runtime_rel : {
 		__efi_runtime_rel_start = .;
@@ -57,8 +57,6 @@ SECTIONS
 		__efi_runtime_rel_stop = .;
 	}
 
-	. = ALIGN(8);
-
 	/DISCARD/ : { *(.rela.plt*) }
 	.rela.dyn : {
 		__rel_dyn_start = .;
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 79a58694f5..f1525cb668 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,14 +1,14 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
-dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
 dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
 dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
+dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
 include $(srctree)/scripts/Makefile.dts
 
 targets += $(dtb-y)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 3c322c5c97..13f69da31e 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0 OR MIT
 /*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
  */
 
 #include "binman.dtsi"
@@ -67,3 +67,40 @@
 	};
 };
 
+&i2c5_pins {
+	bootph-pre-ram;
+	i2c-pins {
+		bootph-pre-ram;
+	};
+};
+
+&i2c5 {
+	bootph-pre-ram;
+	eeprom@50 {
+		bootph-pre-ram;
+	};
+};
+
+&binman {
+	itb {
+		fit {
+			images {
+				fdt-1 {
+					description = "NAME";
+					load = <0x40400000>;
+					compression = "none";
+
+					uboot_fdt_blob: blob-ext {
+						filename = "u-boot.dtb";
+					};
+				};
+			};
+
+			configurations {
+				conf-1 {
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
deleted file mode 100644
index 3c322c5c97..0000000000
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-#include "binman.dtsi"
-#include "jh7110-u-boot.dtsi"
-/ {
-	chosen {
-		bootph-pre-ram;
-	};
-
-	firmware {
-		spi0 = &qspi;
-		bootph-pre-ram;
-	};
-
-	config {
-		bootph-pre-ram;
-		u-boot,spl-payload-offset = <0x100000>;
-	};
-
-	memory@40000000 {
-		bootph-pre-ram;
-	};
-};
-
-&uart0 {
-	bootph-pre-ram;
-};
-
-&mmc0 {
-	bootph-pre-ram;
-};
-
-&mmc1 {
-	bootph-pre-ram;
-};
-
-&qspi {
-	bootph-pre-ram;
-
-	nor-flash@0 {
-		bootph-pre-ram;
-	};
-};
-
-&sysgpio {
-	bootph-pre-ram;
-};
-
-&mmc0_pins {
-	bootph-pre-ram;
-	mmc0-pins-rest {
-		bootph-pre-ram;
-	};
-};
-
-&mmc1_pins {
-	bootph-pre-ram;
-	mmc1-pins0 {
-		bootph-pre-ram;
-	};
-
-	mmc1-pins1 {
-		bootph-pre-ram;
-	};
-};
-
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
deleted file mode 100644
index b9d26d7af7..0000000000
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-/dts-v1/;
-#include "jh7110-starfive-visionfive-2.dtsi"
-
-/ {
-	model = "StarFive VisionFive 2 v1.2A";
-	compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
-};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/dts/jh7110-starfive-visionfive-2.dts
index 3b3b3453a1..288ea39493 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dts
@@ -1,12 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0 OR MIT
 /*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
  */
 
 /dts-v1/;
 #include "jh7110-starfive-visionfive-2.dtsi"
 
 / {
-	model = "StarFive VisionFive 2 v1.3B";
 	compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
 };
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..e40f57a150 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -7,6 +7,7 @@
 
 #include "jh7110.dtsi"
 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
 	aliases {
 		serial0 = &uart0;
@@ -17,6 +18,8 @@
 		i2c2 = &i2c2;
 		i2c5 = &i2c5;
 		i2c6 = &i2c6;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
 	};
 
 	chosen {
@@ -118,6 +121,12 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c5_pins>;
 	status = "okay";
+
+	eeprom@50 {
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
 };
 
 &i2c6 {
@@ -300,14 +309,24 @@
 	};
 };
 
+&pcie0 {
+	reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie1 {
+	reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
 &syscrg {
 	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
 			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
 			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
 			  <&syscrg JH7110_SYSCLK_QSPI_REF>;
-	assigned-clock-parents = <&syscrg JH7110_SYSCLK_PLL0_OUT>,
-				 <&syscrg JH7110_SYSCLK_PLL2_OUT>,
-				 <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+	assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>,
+				 <&pllclk JH7110_SYSCLK_PLL2_OUT>,
+				 <&pllclk JH7110_SYSCLK_PLL2_OUT>,
 				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
 	assigned-clock-rates = <0>, <0>, <0>, <0>;
 };
@@ -317,3 +336,35 @@
 	assigned-clock-parents = <&osc>;
 	assigned-clock-rates = <0>;
 };
+
+&gmac0 {
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+
+		phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
+
+&gmac1 {
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+
+		phy1: ethernet-phy@1 {
+			reg = <0>;
+		};
+	};
+};
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index c22119518c..2f560e7296 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -83,7 +83,6 @@
 
 &syscrg {
 	bootph-pre-ram;
-	starfive,sys-syscon = <&sys_syscon>;
 };
 
 &stgcrg {
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..081b833331 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -235,6 +235,13 @@
 		#clock-cells = <0>;
 	};
 
+	stmmac_axi_setup: stmmac-axi-config {
+		snps,lpi_en;
+		snps,wr_osr_lmt = <4>;
+		snps,rd_osr_lmt = <4>;
+		snps,blen = <256 128 64 32 0 0 0>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
@@ -480,19 +487,29 @@
 				 <&gmac1_rgmii_rxin>,
 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
-				 <&tdm_ext>, <&mclk_ext>;
+				 <&tdm_ext>, <&mclk_ext>,
+				 <&pllclk JH7110_SYSCLK_PLL0_OUT>,
+				 <&pllclk JH7110_SYSCLK_PLL1_OUT>,
+				 <&pllclk JH7110_SYSCLK_PLL2_OUT>;
 			clock-names = "osc", "gmac1_rmii_refin",
 				      "gmac1_rgmii_rxin",
 				      "i2stx_bclk_ext", "i2stx_lrck_ext",
 				      "i2srx_bclk_ext", "i2srx_lrck_ext",
-				      "tdm_ext", "mclk_ext";
+				      "tdm_ext", "mclk_ext",
+				      "pll0_out", "pll1_out", "pll2_out";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
 
 		sys_syscon: sys_syscon@13030000 {
-			compatible = "starfive,jh7110-sys-syscon","syscon";
+			compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd";
 			reg = <0x0 0x13030000 0x0 0x1000>;
+
+			pllclk: clock-controller {
+				compatible = "starfive,jh7110-pll";
+				clocks = <&osc>;
+				#clock-cells = <1>;
+			};
 		};
 
 		sysgpio: pinctrl@13040000 {
@@ -539,6 +556,68 @@
 			status = "disabled";
 		};
 
+		gmac0: ethernet@16030000 {
+			compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+			reg = <0x0 0x16030000 0x0 0x10000>;
+			clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
+				 <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
+				 <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
+				 <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
+				 <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
+			clock-names = "stmmaceth", "pclk", "ptp_ref",
+				      "tx", "gtx";
+			resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
+				 <&aoncrg JH7110_AONRST_GMAC0_AHB>;
+			reset-names = "stmmaceth", "ahb";
+			interrupts = <7>, <6>, <5>;
+			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+			snps,multicast-filter-bins = <64>;
+			snps,perfect-filter-entries = <8>;
+			rx-fifo-depth = <2048>;
+			tx-fifo-depth = <2048>;
+			snps,fixed-burst;
+			snps,no-pbl-x8;
+			snps,force_thresh_dma_mode;
+			snps,axi-config = <&stmmac_axi_setup>;
+			snps,tso;
+			snps,en-tx-lpi-clockgating;
+			snps,txpbl = <16>;
+			snps,rxpbl = <16>;
+			starfive,syscon = <&aon_syscon 0xc 0x12>;
+			status = "disabled";
+		};
+
+		gmac1: ethernet@16040000 {
+			compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+			reg = <0x0 0x16040000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
+				 <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
+				 <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
+				 <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
+				 <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
+			clock-names = "stmmaceth", "pclk", "ptp_ref",
+				      "tx", "gtx";
+			resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
+				 <&syscrg JH7110_SYSRST_GMAC1_AHB>;
+			reset-names = "stmmaceth", "ahb";
+			interrupts = <78>, <77>, <76>;
+			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+			snps,multicast-filter-bins = <64>;
+			snps,perfect-filter-entries = <8>;
+			rx-fifo-depth = <2048>;
+			tx-fifo-depth = <2048>;
+			snps,fixed-burst;
+			snps,no-pbl-x8;
+			snps,force_thresh_dma_mode;
+			snps,axi-config = <&stmmac_axi_setup>;
+			snps,tso;
+			snps,en-tx-lpi-clockgating;
+			snps,txpbl = <16>;
+			snps,rxpbl = <16>;
+			starfive,syscon = <&sys_syscon 0x90 0x2>;
+			status = "disabled";
+		};
+
 		aoncrg: clock-controller@17000000 {
 			compatible = "starfive,jh7110-aoncrg";
 			reg = <0x0 0x17000000 0x0 0x10000>;
@@ -569,5 +648,79 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
+
+		pcie0: pcie@2b000000 {
+			compatible = "starfive,jh7110-pcie";
+			reg = <0x0 0x2b000000 0x0 0x1000000
+			       0x9 0x40000000 0x0 0x10000000>;
+			reg-names = "reg", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
+				 <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
+			interrupts = <56>;
+			interrupt-parent = <&plic>;
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+					<0x0 0x0 0x0 0x2 &plic 0x2>,
+					<0x0 0x0 0x0 0x3 &plic 0x3>,
+					<0x0 0x0 0x0 0x4 &plic 0x4>;
+			msi-parent = <&plic>;
+			device_type = "pci";
+			starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
+			bus-range = <0x0 0xff>;
+			clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+				 <&stgcrg JH7110_STGCLK_PCIE0_TL>,
+				 <&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+				 <&stgcrg JH7110_STGCLK_PCIE0_APB>;
+			clock-names = "noc", "tl", "axi", "apb";
+			resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+				 <&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+				 <&stgcrg JH7110_STGRST_PCIE0_SLV>,
+				 <&stgcrg JH7110_STGRST_PCIE0_BRG>,
+				 <&stgcrg JH7110_STGRST_PCIE0_CORE>,
+				 <&stgcrg JH7110_STGRST_PCIE0_APB>;
+			reset-names = "mst0", "slv0", "slv", "brg",
+				      "core", "apb";
+			status = "disabled";
+		};
+
+		pcie1: pcie@2c000000 {
+			compatible = "starfive,jh7110-pcie";
+			reg = <0x0 0x2c000000 0x0 0x1000000
+			       0x9 0xc0000000 0x0 0x10000000>;
+			reg-names = "reg", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
+				 <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
+			interrupts = <57>;
+			interrupt-parent = <&plic>;
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+					<0x0 0x0 0x0 0x2 &plic 0x2>,
+					<0x0 0x0 0x0 0x3 &plic 0x3>,
+					<0x0 0x0 0x0 0x4 &plic 0x4>;
+			msi-parent = <&plic>;
+			device_type = "pci";
+			starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
+			bus-range = <0x0 0xff>;
+			clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+				 <&stgcrg JH7110_STGCLK_PCIE1_TL>,
+				 <&stgcrg JH7110_STGCLK_PCIE1_AXI>,
+				 <&stgcrg JH7110_STGCLK_PCIE1_APB>;
+			clock-names = "noc", "tl", "axi", "apb";
+			resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>,
+				 <&stgcrg JH7110_STGRST_PCIE1_SLV0>,
+				 <&stgcrg JH7110_STGRST_PCIE1_SLV>,
+				 <&stgcrg JH7110_STGRST_PCIE1_BRG>,
+				 <&stgcrg JH7110_STGRST_PCIE1_CORE>,
+				 <&stgcrg JH7110_STGRST_PCIE1_APB>;
+			reset-names = "mst0", "slv0", "slv", "brg",
+				      "core", "apb";
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
deleted file mode 100644
index c3f58e2d56..0000000000
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ /dev/null
@@ -1,136 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2021-2022 Microchip Technology Inc.
- * Padmarao Begari <padmarao.begari@microchip.com>
- */
-
-/dts-v1/;
-
-#include "microchip-mpfs.dtsi"
-
-/* Clock frequency (in Hz) of the rtcclk */
-#define RTCCLK_FREQ		1000000
-
-/ {
-	model = "Microchip PolarFire-SoC Icicle Kit";
-	compatible = "microchip,mpfs-icicle-reference-rtlv2210",
-		     "microchip,mpfs-icicle-kit", "microchip,mpfs";
-
-	aliases {
-		serial1 = &uart1;
-		ethernet0 = &mac1;
-		spi0 = &qspi;
-	};
-
-	chosen {
-		stdout-path = "serial1";
-	};
-
-	cpus {
-		timebase-frequency = <RTCCLK_FREQ>;
-	};
-
-	ddrc_cache_lo: memory@80000000 {
-		device_type = "memory";
-		reg = <0x0 0x80000000 0x0 0x40000000>;
-		status = "okay";
-	};
-
-	ddrc_cache_hi: memory@1040000000 {
-		device_type = "memory";
-		reg = <0x10 0x40000000 0x0 0x40000000>;
-		status = "okay";
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		hss_payload: region@BFC00000 {
-			reg = <0x0 0xBFC00000 0x0 0x400000>;
-			no-map;
-		};
-	};
-};
-
-&refclk {
-	clock-frequency = <125000000>;
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&mmc {
-	status = "okay";
-
-	bus-width = <4>;
-	disable-wp;
-	cap-mmc-highspeed;
-	cap-sd-highspeed;
-	card-detect-delay = <200>;
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr50;
-	sd-uhs-sdr104;
-};
-
-&i2c1 {
-	status = "okay";
-	clock-frequency = <100000>;
-
-	pac193x: pac193x@10 {
-		compatible = "microchip,pac1934";
-		reg = <0x10>;
-		samp-rate = <64>;
-		status = "okay";
-		ch1: channel0 {
-			uohms-shunt-res = <10000>;
-			rail-name = "VDDREG";
-			channel_enabled;
-		};
-		ch2: channel1 {
-			uohms-shunt-res = <10000>;
-			rail-name = "VDDA25";
-			channel_enabled;
-		};
-		ch3: channel2 {
-			uohms-shunt-res = <10000>;
-			rail-name = "VDD25";
-			channel_enabled;
-		};
-		ch4: channel3 {
-			uohms-shunt-res = <10000>;
-			rail-name = "VDDA_REG";
-			channel_enabled;
-		};
-	};
-};
-
-&mac1 {
-	status = "okay";
-	phy-mode = "sgmii";
-	phy-handle = <&phy1>;
-	phy1: ethernet-phy@9 {
-		reg = <9>;
-		ti,fifo-depth = <0x1>;
-	};
-};
-
-&qspi {
-	status = "okay";
-	num-cs = <1>;
-
-	flash0: flash@0 {
-		compatible = "spi-nand";
-		reg = <0x0>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-		spi-max-frequency = <20000000>;
-		spi-cpol;
-		spi-cpha;
-	};
-};
diff --git a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
new file mode 100644
index 0000000000..1069134f2e
--- /dev/null
+++ b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/ {
+	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
+		     "microchip,mpfs";
+
+	core_pwm0: pwm@40000000 {
+		compatible = "microchip,corepwm-rtl-v4";
+		reg = <0x0 0x40000000 0x0 0xF0>;
+		microchip,sync-update-mask = /bits/ 32 <0>;
+		#pwm-cells = <3>;
+		clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@40000200 {
+		compatible = "microchip,corei2c-rtl-v7";
+		reg = <0x0 0x40000200 0x0 0x100>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
+		interrupt-parent = <&plic>;
+		interrupts = <122>;
+		clock-frequency = <100000>;
+		status = "disabled";
+	};
+
+	pcie: pcie@3000000000 {
+		compatible = "microchip,pcie-host-1.0";
+		#address-cells = <0x3>;
+		#interrupt-cells = <0x1>;
+		#size-cells = <0x2>;
+		device_type = "pci";
+		reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+		reg-names = "cfg", "apb";
+		bus-range = <0x0 0x7f>;
+		interrupt-parent = <&plic>;
+		interrupts = <119>;
+		interrupt-map = <0 0 0 1 &pcie_intc 0>,
+				<0 0 0 2 &pcie_intc 1>,
+				<0 0 0 3 &pcie_intc 2>,
+				<0 0 0 4 &pcie_intc 3>;
+		interrupt-map-mask = <0 0 0 7>;
+		clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
+		clock-names = "fic1", "fic3";
+		ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
+		dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
+		msi-parent = <&pcie>;
+		msi-controller;
+		status = "disabled";
+		pcie_intc: interrupt-controller {
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+		};
+	};
+
+	refclk_ccc: cccrefclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+};
+
+&ccc_nw {
+	clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
+		 <&refclk_ccc>, <&refclk_ccc>;
+	clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
+		      "dll0_ref", "dll1_ref";
+	status = "okay";
+};
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi
index f60283fb6b..f60283fb6b 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
+++ b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi
diff --git a/arch/riscv/dts/mpfs-icicle-kit.dts b/arch/riscv/dts/mpfs-icicle-kit.dts
new file mode 100644
index 0000000000..8aa5fb17d6
--- /dev/null
+++ b/arch/riscv/dts/mpfs-icicle-kit.dts
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021-2022 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-icicle-kit-fabric.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ		1000000
+
+/ {
+	model = "Microchip PolarFire-SoC Icicle Kit";
+	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
+		     "microchip,mpfs";
+
+	aliases {
+		ethernet0 = &mac1;
+		serial0 = &mmuart0;
+		serial1 = &mmuart1;
+		serial2 = &mmuart2;
+		serial3 = &mmuart3;
+		serial4 = &mmuart4;
+	};
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	cpus {
+		timebase-frequency = <RTCCLK_FREQ>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-1 {
+			gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_RED>;
+			label = "led1";
+		};
+
+		led-2 {
+			gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_RED>;
+			label = "led2";
+		};
+
+		led-3 {
+			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_AMBER>;
+			label = "led3";
+		};
+
+		led-4 {
+			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_AMBER>;
+			label = "led4";
+		};
+	};
+
+	ddrc_cache_lo: memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x40000000>;
+		status = "okay";
+	};
+
+	ddrc_cache_hi: memory@1040000000 {
+		device_type = "memory";
+		reg = <0x10 0x40000000 0x0 0x40000000>;
+		status = "okay";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hss_payload: region@BFC00000 {
+			reg = <0x0 0xBFC00000 0x0 0x400000>;
+			no-map;
+		};
+	};
+};
+
+&core_pwm0 {
+	status = "okay";
+};
+
+&gpio2 {
+	interrupts = <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&mac0 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy0>;
+	status = "enabled";
+};
+
+&mac1 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy@9 {
+		reg = <9>;
+	};
+
+	phy0: ethernet-phy@8 {
+		reg = <8>;
+	};
+};
+
+&mbox {
+	status = "okay";
+};
+
+&mmc {
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&mmuart1 {
+	status = "okay";
+};
+
+&mmuart2 {
+	status = "okay";
+};
+
+&mmuart3 {
+	status = "okay";
+};
+
+&mmuart4 {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+};
+
+&refclk {
+	clock-frequency = <125000000>;
+};
+
+&refclk_ccc {
+	clock-frequency = <50000000>;
+};
+
+&rtc {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&syscontroller {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+	dr_mode = "host";
+};
diff --git a/arch/riscv/dts/microchip-mpfs.dtsi b/arch/riscv/dts/mpfs.dtsi
index 891dd0918b..6012a28507 100644
--- a/arch/riscv/dts/microchip-mpfs.dtsi
+++ b/arch/riscv/dts/mpfs.dtsi
@@ -2,8 +2,6 @@
 /* Copyright (c) 2020-2021 Microchip Technology Inc */
 
 #include "dt-bindings/clock/microchip-mpfs-clock.h"
-#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h"
-#include "dt-bindings/interrupt-controller/riscv-hart.h"
 
 / {
 	#address-cells = <2>;
@@ -11,9 +9,6 @@
 	model = "Microchip PolarFire SoC";
 	compatible = "microchip,mpfs";
 
-	chosen {
-	};
-
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -28,12 +23,7 @@
 			riscv,isa = "rv64imac";
 			clocks = <&clkcfg CLK_CPU>;
 			status = "disabled";
-			operating-points = <
-				/* kHz	uV */
-				600000  1100000
-				300000   950000
-				150000   750000
-			>;
+
 			cpu0_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -59,13 +49,9 @@
 			riscv,isa = "rv64imafdc";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
+			next-level-cache = <&cctrllr>;
 			status = "okay";
-			operating-points = <
-				/* kHz	uV */
-				600000  1100000
-				300000   950000
-				150000   750000
-			>;
+
 			cpu1_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -91,13 +77,9 @@
 			riscv,isa = "rv64imafdc";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
+			next-level-cache = <&cctrllr>;
 			status = "okay";
-			operating-points = <
-				/* kHz	uV */
-				600000  1100000
-				300000   950000
-				150000   750000
-			>;
+
 			cpu2_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -123,13 +105,9 @@
 			riscv,isa = "rv64imafdc";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
+			next-level-cache = <&cctrllr>;
 			status = "okay";
-			operating-points = <
-				/* kHz	uV */
-				600000  1100000
-				300000   950000
-				150000   750000
-			>;
+
 			cpu3_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -155,273 +133,322 @@
 			riscv,isa = "rv64imafdc";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
+			next-level-cache = <&cctrllr>;
 			status = "okay";
-			operating-points = <
-				/* kHz	uV */
-				600000  1100000
-				300000   950000
-				150000   750000
-			>;
 			cpu4_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
 				interrupt-controller;
 			};
 		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+
+				core4 {
+					cpu = <&cpu4>;
+				};
+			};
+		};
 	};
 
-	refclk: refclk {
+	refclk: mssrefclk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 	};
 
+	syscontroller: syscontroller {
+		compatible = "microchip,mpfs-sys-controller";
+		mboxes = <&mbox 0>;
+	};
+
 	soc {
 		#address-cells = <2>;
 		#size-cells = <2>;
-		compatible = "microchip,mpfs-soc", "simple-bus";
+		compatible = "simple-bus";
 		ranges;
 
-		clint: clint@2000000 {
-			compatible = "sifive,clint0";
-			reg = <0x0 0x2000000 0x0 0xC000>;
-			interrupts-extended =
-					<&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER
-					 &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER
-					 &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER
-					 &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER
-					 &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>;
-		};
-
-		cachecontroller: cache-controller@2010000 {
-			compatible = "sifive,fu540-c000-ccache", "cache";
+		cctrllr: cache-controller@2010000 {
+			compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
 			reg = <0x0 0x2010000 0x0 0x1000>;
-			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_L2_METADATA_CORR
-				PLIC_INT_L2_METADATA_UNCORR
-				PLIC_INT_L2_DATA_CORR>;
 			cache-block-size = <64>;
 			cache-level = <2>;
 			cache-sets = <1024>;
 			cache-size = <2097152>;
 			cache-unified;
+			interrupt-parent = <&plic>;
+			interrupts = <1>, <3>, <4>, <2>;
 		};
 
-		pdma: pdma@3000000 {
-			compatible = "microchip,mpfs-pdma-uio","sifive,fu540-c000-pdma";
-			reg = <0x0 0x3000000 0x0 0x8000>;
-			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_DMA_CH0_DONE PLIC_INT_DMA_CH0_ERR
-				PLIC_INT_DMA_CH1_DONE PLIC_INT_DMA_CH1_ERR
-				PLIC_INT_DMA_CH2_DONE PLIC_INT_DMA_CH2_ERR
-				PLIC_INT_DMA_CH3_DONE PLIC_INT_DMA_CH3_ERR>;
-			#dma-cells = <1>;
+		clint: clint@2000000 {
+			compatible = "sifive,fu540-c000-clint", "sifive,clint0";
+			reg = <0x0 0x2000000 0x0 0xC000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>,
+					      <&cpu4_intc 3>, <&cpu4_intc 7>;
 		};
 
 		plic: interrupt-controller@c000000 {
-			compatible = "sifive,plic-1.0.0";
+			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
+			#address-cells = <0>;
 			#interrupt-cells = <1>;
-			riscv,ndev = <186>;
 			interrupt-controller;
-			interrupts-extended = <&cpu0_intc HART_INT_M_EXT
-					&cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT
-					&cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT
-					&cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT
-					&cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>;
+			interrupts-extended = <&cpu0_intc 11>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>,
+					      <&cpu4_intc 11>, <&cpu4_intc 9>;
+			riscv,ndev = <186>;
+		};
+
+		pdma: dma-controller@3000000 {
+			compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
+			reg = <0x0 0x3000000 0x0 0x8000>;
+			interrupt-parent = <&plic>;
+			interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
+			dma-channels = <4>;
+			#dma-cells = <1>;
 		};
 
 		clkcfg: clkcfg@20002000 {
 			compatible = "microchip,mpfs-clkcfg";
 			reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
-			reg-names = "mss_sysreg";
 			clocks = <&refclk>;
 			#clock-cells = <1>;
-			clock-output-names = "cpu", "axi", "ahb", "envm",	/* 0-3   */
-				"mac0", "mac1", "mmc", "timer",				/* 4-7   */
-				"mmuart0", "mmuart1", "mmuart2", "mmuart3",	/* 8-11  */
-				"mmuart4", "spi0", "spi1", "i2c0",			/* 12-15 */
-				"i2c1", "can0", "can1", "usb",				/* 16-19 */
-				"rsvd", "rtc", "qspi", "gpio0",				/* 20-23 */
-				"gpio1", "gpio2", "ddrc", "fic0",			/* 24-27 */
-				"fic1", "fic2", "fic3", "athena", "cfm";	/* 28-32 */
+			#reset-cells = <1>;
 		};
 
-		/* Common node entry for eMMC/SD */
-		mmc: mmc@20008000 {
-			compatible = "microchip,mpfs-sd4hc","cdns,sd4hc";
-			reg = <0x0 0x20008000 0x0 0x1000>;
-			clocks = <&clkcfg CLK_MMC>;
-			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_MMC_MAIN PLIC_INT_MMC_WAKEUP>;
-			max-frequency = <200000000>;
+		ccc_se: clock-controller@38010000 {
+			compatible = "microchip,mpfs-ccc";
+			reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
+			      <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>;
+			#clock-cells = <1>;
+			status = "disabled";
+		};
+
+		ccc_ne: clock-controller@38040000 {
+			compatible = "microchip,mpfs-ccc";
+			reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>,
+			      <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>;
+			#clock-cells = <1>;
 			status = "disabled";
 		};
 
-		uart0: serial@20000000 {
+		ccc_nw: clock-controller@38100000 {
+			compatible = "microchip,mpfs-ccc";
+			reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>,
+			      <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>;
+			#clock-cells = <1>;
+			status = "disabled";
+		};
+
+		ccc_sw: clock-controller@38400000 {
+			compatible = "microchip,mpfs-ccc";
+			reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>,
+			      <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>;
+			#clock-cells = <1>;
+			status = "disabled";
+		};
+
+		mmuart0: serial@20000000 {
 			compatible = "ns16550a";
 			reg = <0x0 0x20000000 0x0 0x400>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_MMUART0>;
+			interrupts = <90>;
+			current-speed = <115200>;
 			clocks = <&clkcfg CLK_MMUART0>;
 			status = "disabled"; /* Reserved for the HSS */
 		};
 
-		uart1: serial@20100000 {
+		mmuart1: serial@20100000 {
 			compatible = "ns16550a";
 			reg = <0x0 0x20100000 0x0 0x400>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_MMUART1>;
+			interrupts = <91>;
+			current-speed = <115200>;
 			clocks = <&clkcfg CLK_MMUART1>;
 			status = "disabled";
 		};
 
-		uart2: serial@20102000 {
+		mmuart2: serial@20102000 {
 			compatible = "ns16550a";
 			reg = <0x0 0x20102000 0x0 0x400>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_MMUART2>;
+			interrupts = <92>;
+			current-speed = <115200>;
 			clocks = <&clkcfg CLK_MMUART2>;
 			status = "disabled";
 		};
 
-		uart3: serial@20104000 {
+		mmuart3: serial@20104000 {
 			compatible = "ns16550a";
 			reg = <0x0 0x20104000 0x0 0x400>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_MMUART3>;
+			interrupts = <93>;
+			current-speed = <115200>;
 			clocks = <&clkcfg CLK_MMUART3>;
 			status = "disabled";
 		};
 
-		uart4: serial@20106000 {
+		mmuart4: serial@20106000 {
 			compatible = "ns16550a";
 			reg = <0x0 0x20106000 0x0 0x400>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_MMUART4>;
+			interrupts = <94>;
 			clocks = <&clkcfg CLK_MMUART4>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		/* Common node entry for emmc/sd */
+		mmc: mmc@20008000 {
+			compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
+			reg = <0x0 0x20008000 0x0 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <88>;
+			clocks = <&clkcfg CLK_MMC>;
+			max-frequency = <200000000>;
 			status = "disabled";
 		};
 
 		spi0: spi@20108000 {
 			compatible = "microchip,mpfs-spi";
-			reg = <0x0 0x20108000 0x0 0x1000>;
-			clocks = <&clkcfg CLK_SPI0>;
-			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_SPI0>;
-			num-cs = <8>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			reg = <0x0 0x20108000 0x0 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <54>;
+			clocks = <&clkcfg CLK_SPI0>;
 			status = "disabled";
 		};
 
 		spi1: spi@20109000 {
 			compatible = "microchip,mpfs-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
 			reg = <0x0 0x20109000 0x0 0x1000>;
-			clocks = <&clkcfg CLK_SPI1>;
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_SPI1>;
-			num-cs = <8>;
+			interrupts = <55>;
+			clocks = <&clkcfg CLK_SPI1>;
+			status = "disabled";
+		};
+
+		qspi: spi@21000000 {
+			compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			reg = <0x0 0x21000000 0x0 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <85>;
+			clocks = <&clkcfg CLK_QSPI>;
 			status = "disabled";
 		};
 
 		i2c0: i2c@2010a000 {
-			compatible = "microchip,mpfs-i2c";
+			compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
 			reg = <0x0 0x2010a000 0x0 0x1000>;
-			clocks = <&clkcfg CLK_I2C0>;
-			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_I2C0_MAIN>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			interrupt-parent = <&plic>;
+			interrupts = <58>;
+			clocks = <&clkcfg CLK_I2C0>;
+			clock-frequency = <100000>;
 			status = "disabled";
 		};
 
 		i2c1: i2c@2010b000 {
-			compatible = "microchip,mpfs-i2c";
+			compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
 			reg = <0x0 0x2010b000 0x0 0x1000>;
-			clocks = <&clkcfg CLK_I2C1>;
-			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_I2C1_MAIN>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			interrupt-parent = <&plic>;
+			interrupts = <61>;
+			clocks = <&clkcfg CLK_I2C1>;
+			clock-frequency = <100000>;
 			status = "disabled";
 		};
 
 		can0: can@2010c000 {
-			compatible = "microchip,mpfs-can-uio";
+			compatible = "microchip,mpfs-can";
 			reg = <0x0 0x2010c000 0x0 0x1000>;
 			clocks = <&clkcfg CLK_CAN0>;
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_CAN0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
+			interrupts = <56>;
 			status = "disabled";
 		};
 
 		can1: can@2010d000 {
-			compatible = "microchip,mpfs-can-uio";
+			compatible = "microchip,mpfs-can";
 			reg = <0x0 0x2010d000 0x0 0x1000>;
 			clocks = <&clkcfg CLK_CAN1>;
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_CAN1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
+			interrupts = <57>;
 			status = "disabled";
 		};
 
 		mac0: ethernet@20110000 {
-			compatible = "cdns,macb";
+			compatible = "microchip,mpfs-macb", "cdns,macb";
 			reg = <0x0 0x20110000 0x0 0x2000>;
-			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
-			clock-names = "pclk", "hclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_MAC0_INT
-				PLIC_INT_MAC0_QUEUE1
-				PLIC_INT_MAC0_QUEUE2
-				PLIC_INT_MAC0_QUEUE3
-				PLIC_INT_MAC0_EMAC
-				PLIC_INT_MAC0_MMSL>;
+			interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
 			local-mac-address = [00 00 00 00 00 00];
+			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
+			clock-names = "pclk", "hclk";
+			resets = <&clkcfg CLK_MAC0>;
 			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
 		};
 
 		mac1: ethernet@20112000 {
-			compatible = "cdns,macb";
+			compatible = "microchip,mpfs-macb", "cdns,macb";
 			reg = <0x0 0x20112000 0x0 0x2000>;
-			clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
-			clock-names = "pclk", "hclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_MAC1_INT
-				PLIC_INT_MAC1_QUEUE1
-				PLIC_INT_MAC1_QUEUE2
-				PLIC_INT_MAC1_QUEUE3
-				PLIC_INT_MAC1_EMAC
-				PLIC_INT_MAC1_MMSL>;
+			interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
 			local-mac-address = [00 00 00 00 00 00];
+			clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
+			clock-names = "pclk", "hclk";
+			resets = <&clkcfg CLK_MAC1>;
 			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
 		};
 
 		gpio0: gpio@20120000 {
 			compatible = "microchip,mpfs-gpio";
 			reg = <0x0 0x20120000 0x0 0x1000>;
-			reg-names = "control";
-			clocks = <&clkcfg CLK_GPIO0>;
 			interrupt-parent = <&plic>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			clocks = <&clkcfg CLK_GPIO0>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			status = "disabled";
@@ -429,10 +456,11 @@
 
 		gpio1: gpio@20121000 {
 			compatible = "microchip,mpfs-gpio";
-			reg = <000 0x20121000 0x0 0x1000>;
-			reg-names = "control";
-			clocks = <&clkcfg CLK_GPIO1>;
+			reg = <0x0 0x20121000 0x0 0x1000>;
 			interrupt-parent = <&plic>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			clocks = <&clkcfg CLK_GPIO1>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			status = "disabled";
@@ -441,9 +469,10 @@
 		gpio2: gpio@20122000 {
 			compatible = "microchip,mpfs-gpio";
 			reg = <0x0 0x20122000 0x0 0x1000>;
-			reg-names = "control";
-			clocks = <&clkcfg CLK_GPIO2>;
 			interrupt-parent = <&plic>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			clocks = <&clkcfg CLK_GPIO2>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			status = "disabled";
@@ -452,118 +481,31 @@
 		rtc: rtc@20124000 {
 			compatible = "microchip,mpfs-rtc";
 			reg = <0x0 0x20124000 0x0 0x1000>;
-			clocks = <&clkcfg CLK_RTC>;
-			clock-names = "rtc";
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_RTC_WAKEUP PLIC_INT_RTC_MATCH>;
-			#address-cells = <1>;
-			#size-cells = <0>;
+			interrupts = <80>, <81>;
+			clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
+			clock-names = "rtc", "rtcref";
 			status = "disabled";
 		};
 
 		usb: usb@20201000 {
-			compatible = "microchip,mpfs-usb-host";
+			compatible = "microchip,mpfs-musb";
 			reg = <0x0 0x20201000 0x0 0x1000>;
-			reg-names = "mc","control";
-			clocks = <&clkcfg CLK_USB>;
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>;
+			interrupts = <86>, <87>;
+			clocks = <&clkcfg CLK_USB>;
 			interrupt-names = "dma","mc";
-			dr_mode = "host";
-			status = "disabled";
-		};
-
-		qspi: qspi@21000000 {
-			compatible = "microchip,mpfs-qspi";
-			reg = <0x0 0x21000000 0x0 0x1000>;
-			clocks = <&clkcfg CLK_QSPI>;
-			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_QSPI>;
-			num-cs = <8>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 		};
 
 		mbox: mailbox@37020000 {
 			compatible = "microchip,mpfs-mailbox";
-			reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
+			reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
+			      <0x0 0x37020800 0x0 0x100>;
 			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_G5C_MESSAGE>;
+			interrupts = <96>;
 			#mbox-cells = <1>;
 			status = "disabled";
 		};
-
-		pcie: pcie@2000000000 {
-			compatible = "microchip,pcie-host-1.0";
-			#address-cells = <0x3>;
-			#interrupt-cells = <0x1>;
-			#size-cells = <0x2>;
-			device_type = "pci";
-			reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>;
-			reg-names = "cfg", "apb";
-			clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
-			clock-names = "fic0", "fic1", "fic3";
-			bus-range = <0x0 0x7f>;
-			interrupt-parent = <&plic>;
-			interrupts = <PLIC_INT_FABRIC_F2H_2>;
-			interrupt-map = <0 0 0 1 &pcie_intc 0>,
-					<0 0 0 2 &pcie_intc 1>,
-					<0 0 0 3 &pcie_intc 2>,
-					<0 0 0 4 &pcie_intc 3>;
-			interrupt-map-mask = <0 0 0 7>;
-			ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
-			msi-parent = <&pcie>;
-			msi-controller;
-			mchp,axi-m-atr0 = <0x10 0x0>;
-			status = "disabled";
-			pcie_intc: legacy-interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		syscontroller: syscontroller {
-			compatible = "microchip,mpfs-sys-controller";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			mboxes = <&mbox 0>;
-		};
-
-		hwrandom: hwrandom {
-			compatible = "microchip,mpfs-rng";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			syscontroller = <&syscontroller>;
-		};
-
-		serialnum: serialnum {
-			compatible = "microchip,mpfs-serial-number";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			syscontroller = <&syscontroller>;
-		};
-
-		fpgadigest: fpgadigest {
-			compatible = "microchip,mpfs-digest";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			syscontroller = <&syscontroller>;
-		};
-
-		devicecert: cert {
-			compatible = "microchip,mpfs-device-cert";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			syscontroller = <&syscontroller>;
-		};
-
-		signature: signature {
-			compatible = "microchip,mpfs-signature";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			syscontroller = <&syscontroller>;
-		};
 	};
 };
diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi
new file mode 100644
index 0000000000..dc00e3dfa0
--- /dev/null
+++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "th1520.dtsi"
+
+/ {
+	model = "Sipeed Lichee Module 4A";
+	compatible = "sipeed,lichee-module-4a", "thead,th1520";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x00000000 0x2 0x00000000>;
+	};
+};
+
+&osc {
+	clock-frequency = <24000000>;
+};
+
+&osc_32k {
+	clock-frequency = <32768>;
+};
+
+&apb_clk {
+	clock-frequency = <62500000>;
+};
+
+&uart_sclk {
+	clock-frequency = <100000000>;
+};
diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts
new file mode 100644
index 0000000000..a1248b2ee3
--- /dev/null
+++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include "th1520-lichee-module-4a.dtsi"
+
+/ {
+	model = "Sipeed Lichee Pi 4A";
+	compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
new file mode 100644
index 0000000000..f7bfa42243
--- /dev/null
+++ b/arch/riscv/dts/th1520.dtsi
@@ -0,0 +1,406 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "thead,th1520";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+
+		c910_0: cpu@0 {
+			compatible = "thead,c910", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <0>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		c910_1: cpu@1 {
+			compatible = "thead,c910", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <1>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		c910_2: cpu@2 {
+			compatible = "thead,c910", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <2>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		c910_3: cpu@3 {
+			compatible = "thead,c910", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <3>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		l2_cache: l2-cache {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+	};
+
+	osc: oscillator {
+		compatible = "fixed-clock";
+		clock-output-names = "osc_24m";
+		#clock-cells = <0>;
+	};
+
+	osc_32k: 32k-oscillator {
+		compatible = "fixed-clock";
+		clock-output-names = "osc_32k";
+		#clock-cells = <0>;
+	};
+
+	apb_clk: apb-clk-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "apb_clk";
+		#clock-cells = <0>;
+	};
+
+	uart_sclk: uart-sclk-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "uart_sclk";
+		#clock-cells = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		plic: interrupt-controller@ffd8000000 {
+			compatible = "thead,th1520-plic", "thead,c900-plic";
+			reg = <0xff 0xd8000000 0x0 0x01000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			riscv,ndev = <240>;
+		};
+
+		clint: timer@ffdc000000 {
+			compatible = "thead,th1520-clint", "thead,c900-clint";
+			reg = <0xff 0xdc000000 0x0 0x00010000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>;
+		};
+
+		uart0: serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x100>;
+			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart1: serial@ffe7f00000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7f00000 0x0 0x100>;
+			interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@ffe7f04000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7f04000 0x0 0x100>;
+			interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portc: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio3: gpio@ffe7f38000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f38000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portd: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portb: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		uart2: serial@ffec010000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xec010000 0x0 0x4000>;
+			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		timer0: timer@ffefc32000 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc32000 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer1: timer@ffefc32014 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc32014 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer2: timer@ffefc32028 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc32028 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer3: timer@ffefc3203c {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc3203c 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart4: serial@fff7f08000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xf7f08000 0x0 0x4000>;
+			interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart5: serial@fff7f0c000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xf7f0c000 0x0 0x4000>;
+			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_sclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		timer4: timer@ffffc33000 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc33000 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer5: timer@ffffc33014 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc33014 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer6: timer@ffffc33028 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc33028 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer7: timer@ffffc3303c {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc3303c 0x0 0x14>;
+			clocks = <&apb_clk>;
+			clock-names = "timer";
+			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		ao_gpio0: gpio@fffff41000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xfff41000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			porte: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		ao_gpio1: gpio@fffff52000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xfff52000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portf: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
diff --git a/arch/riscv/include/asm/acpi_table.h b/arch/riscv/include/asm/acpi_table.h
new file mode 100644
index 0000000000..cd851998b2
--- /dev/null
+++ b/arch/riscv/include/asm/acpi_table.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __ASM_ACPI_TABLE_H__
+#define __ASM_ACPI_TABLE_H__
+
+/*
+ * This file is needed by some drivers.
+ * We will fill it when adding ACPI support for RISC-V.
+ */
+
+#endif /* __ASM_ACPI_TABLE_H__ */
diff --git a/arch/riscv/include/asm/arch-fu740/eeprom.h b/arch/riscv/include/asm/arch-fu740/eeprom.h
deleted file mode 100644
index 0e1220e558..0000000000
--- a/arch/riscv/include/asm/arch-fu740/eeprom.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 SiFive, Inc.
- *
- * Zong Li <zong.li@sifve.com>
- */
-
-#ifndef _ASM_RISCV_EEPROM_H
-#define _ASM_RISCV_EEPROM_H
-
-#define PCB_REVISION_REV3	0x3
-
-u8 get_pcb_revision_from_eeprom(void);
-
-#endif /* _ASM_RISCV_EEPROM_H */
diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h
new file mode 100644
index 0000000000..f354d5c60c
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#ifndef _ASM_RISCV_EEPROM_H
+#define _ASM_RISCV_EEPROM_H
+
+u8 get_pcb_revision_from_eeprom(void);
+u32 get_ddr_size_from_eeprom(void);
+
+#endif /* _ASM_RISCV_EEPROM_H */
diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h
new file mode 100644
index 0000000000..f541fb4daa
--- /dev/null
+++ b/arch/riscv/include/asm/atomic.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 SiFive, Inc.
+ */
+
+#ifndef __RISCV_ATOMIC_H
+#define __RISCV_ATOMIC_H
+
+/* use the generic asm/atomic.h until we define a better one */
+
+#include <asm/system.h>
+#include <asm-generic/atomic.h>
+
+#endif
diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h
index 536629bbec..35f1368b83 100644
--- a/arch/riscv/include/asm/bitops.h
+++ b/arch/riscv/include/asm/bitops.h
@@ -158,6 +158,9 @@ static inline unsigned long ffz(unsigned long word)
 #define hweight16(x) generic_hweight16(x)
 #define hweight8(x) generic_hweight8(x)
 
+#define test_and_set_bit		__test_and_set_bit
+#define test_and_clear_bit		__test_and_clear_bit
+
 #define ext2_set_bit			test_and_set_bit
 #define ext2_clear_bit			test_and_clear_bit
 #define ext2_test_bit			test_bit
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 31ba72693d..9d97517e12 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -18,8 +18,8 @@
 struct arch_global_data {
 	long boot_hart;		/* boot hart id */
 	phys_addr_t firmware_fdt_addr;
-#if CONFIG_IS_ENABLED(SIFIVE_CLINT)
-	void __iomem *clint;	/* clint base address */
+#if CONFIG_IS_ENABLED(RISCV_ACLINT)
+	void __iomem *aclint;	/* aclint base address */
 #endif
 #ifdef CONFIG_ANDES_PLICSW
 	void __iomem *plicsw;	/* andes plicsw base address */
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 81fcfe0b36..009a26885c 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -28,6 +28,11 @@ enum sbi_ext_id {
 	SBI_EXT_HSM = 0x48534D,
 	SBI_EXT_SRST = 0x53525354,
 	SBI_EXT_PMU = 0x504D55,
+	SBI_EXT_DBCN = 0x4442434E,
+	SBI_EXT_SUSP = 0x53555350,
+	SBI_EXT_CPPC = 0x43505043,
+	SBI_EXT_NACL = 0x4E41434C,
+	SBI_EXT_STA = 0x535441,
 };
 
 enum sbi_ext_base_fid {
@@ -89,6 +94,12 @@ enum sbi_srst_reset_reason {
 	SBI_SRST_RESET_REASON_SYS_FAILURE,
 };
 
+enum sbi_ext_dbcn_fid {
+	SBI_EXT_DBCN_CONSOLE_WRITE = 0,
+	SBI_EXT_DBCN_CONSOLE_READ,
+	SBI_EXT_DBCN_CONSOLE_WRITE_BYTE,
+};
+
 #ifdef CONFIG_SBI_V01
 #define SBI_EXT_SET_TIMER		SBI_EXT_0_1_SET_TIMER
 #define SBI_FID_SET_TIMER		0
diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h
index 2898a770ee..9c0bf9755c 100644
--- a/arch/riscv/include/asm/spl.h
+++ b/arch/riscv/include/asm/spl.h
@@ -20,6 +20,7 @@ enum {
 	BOOT_DEVICE_SPI,
 	BOOT_DEVICE_USB,
 	BOOT_DEVICE_SATA,
+	BOOT_DEVICE_NVME,
 	BOOT_DEVICE_I2C,
 	BOOT_DEVICE_BOARD,
 	BOOT_DEVICE_DFU,
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index f2b37975f3..5787702e74 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -12,7 +12,7 @@
  */
 enum {
 	RISCV_NONE,
-	RISCV_SYSCON_CLINT,	/* Core Local Interruptor (CLINT) */
+	RISCV_SYSCON_ACLINT,	/* Advanced Core Local Interruptor (ACLINT) */
 	RISCV_SYSCON_PLICSW,	/* Andes PLICSW */
 };
 
diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h
index 9d8e43e394..ffa7649f3f 100644
--- a/arch/riscv/include/asm/system.h
+++ b/arch/riscv/include/asm/system.h
@@ -7,15 +7,24 @@
 #ifndef __ASM_RISCV_SYSTEM_H
 #define __ASM_RISCV_SYSTEM_H
 
+#include <asm/csr.h>
+
 struct event;
 
 /*
- * Interrupt configuring macros.
- *
- * TODO
- *
+ * Interupt configuration macros
  */
 
+#define local_irq_save(__flags)                                 \
+    do {                                                        \
+        __flags = csr_read_clear(CSR_SSTATUS, SR_SIE) & SR_SIE; \
+    } while (0)
+
+#define local_irq_restore(__flags)              \
+    do {                                        \
+        csr_set(CSR_SSTATUS, __flags & SR_SIE); \
+    } while (0)
+
 /* Hook to set up the CPU (called from SPL too) */
 int riscv_cpu_setup(void *ctx, struct event *event);
 
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index e5a81ba722..02c4d8fcc6 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
 obj-y	+= cache.o
 obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
 ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
-obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
+obj-$(CONFIG_$(SPL_)RISCV_ACLINT) += aclint_ipi.o
 obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o
 else
 obj-$(CONFIG_SBI) += sbi.o
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/aclint_ipi.c
index ab22395c55..90b8e128cb 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/aclint_ipi.c
@@ -10,9 +10,12 @@
 
 #include <common.h>
 #include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/smp.h>
+#include <asm/syscon.h>
 #include <linux/err.h>
 
 /* MSIP registers */
@@ -26,12 +29,16 @@ int riscv_init_ipi(void)
 	struct udevice *dev;
 
 	ret = uclass_get_device_by_driver(UCLASS_TIMER,
-					  DM_DRIVER_GET(sifive_clint), &dev);
+					  DM_DRIVER_GET(riscv_aclint_timer), &dev);
 	if (ret)
 		return ret;
 
-	gd->arch.clint = dev_read_addr_ptr(dev);
-	if (!gd->arch.clint)
+	if (dev_get_driver_data(dev) != 0)
+		gd->arch.aclint = dev_read_addr_ptr(dev);
+	else
+		gd->arch.aclint = syscon_get_first_range(RISCV_SYSCON_ACLINT);
+
+	if (!gd->arch.aclint)
 		return -EINVAL;
 
 	return 0;
@@ -39,21 +46,33 @@ int riscv_init_ipi(void)
 
 int riscv_send_ipi(int hart)
 {
-	writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
+	writel(1, (void __iomem *)MSIP_REG(gd->arch.aclint, hart));
 
 	return 0;
 }
 
 int riscv_clear_ipi(int hart)
 {
-	writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
+	writel(0, (void __iomem *)MSIP_REG(gd->arch.aclint, hart));
 
 	return 0;
 }
 
 int riscv_get_ipi(int hart, int *pending)
 {
-	*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
+	*pending = readl((void __iomem *)MSIP_REG(gd->arch.aclint, hart));
 
 	return 0;
 }
+
+static const struct udevice_id riscv_aclint_swi_ids[] = {
+	{ .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_ACLINT },
+	{ }
+};
+
+U_BOOT_DRIVER(riscv_aclint_swi) = {
+	.name		= "riscv_aclint_swi",
+	.id		= UCLASS_SYSCON,
+	.of_match	= riscv_aclint_swi_ids,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c
index 324eb445aa..7518408089 100644
--- a/arch/riscv/lib/andes_plicsw.c
+++ b/arch/riscv/lib/andes_plicsw.c
@@ -2,9 +2,10 @@
 /*
  * Copyright (C) 2019, Rick Chen <rick@andestech.com>
  *
- * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
- * The PLIC block holds memory-mapped claim and pending registers
- * associated with software interrupt.
+ * U-Boot syscon driver for Andes' PLICSW
+ * The PLICSW block is an Andes-specific design for software interrupts,
+ * contains memory-mapped priority, enable, claim and pending registers
+ * similar to RISC-V PLIC.
  */
 
 #include <common.h>
@@ -26,9 +27,13 @@
 #define ENABLE_REG(base, hart)	((ulong)(base) + 0x2000 + (hart) * 0x80)
 /* claim register */
 #define CLAIM_REG(base, hart)	((ulong)(base) + 0x200004 + (hart) * 0x1000)
+/* priority register */
+#define PRIORITY_REG(base)	((ulong)(base) + PLICSW_PRIORITY_BASE)
 
 #define ENABLE_HART_IPI         (0x01010101)
 #define SEND_IPI_TO_HART(hart)  (0x1 << (hart))
+#define PLICSW_PRIORITY_BASE        0x4
+#define PLICSW_INTERRUPT_PER_HART   0x8
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -43,9 +48,21 @@ static int enable_ipi(int hart)
 	return 0;
 }
 
+static void init_priority_ipi(int hart_num)
+{
+    uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw);
+
+    for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) {
+        writel(1, &priority[i]);
+    }
+
+    return;
+}
+
 int riscv_init_ipi(void)
 {
 	int ret;
+	int hart_num = 0;
 	long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW);
 	ofnode node;
 	struct udevice *dev;
@@ -79,8 +96,10 @@ int riscv_init_ipi(void)
 		ret = ofnode_read_u32(node, "reg", &reg);
 		if (ret == 0)
 			enable_ipi(reg);
+		hart_num++;
 	}
 
+	init_priority_ipi(hart_num);
 	return 0;
 }
 
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 51496338ad..a1c5c7c431 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -286,6 +286,11 @@ void sandbox_set_enable_pci_map(int enable)
 	enable_pci_map = enable;
 }
 
+int dcache_status(void)
+{
+	return 1;
+}
+
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
 }
diff --git a/arch/sandbox/cpu/sdl.c b/arch/sandbox/cpu/sdl.c
index 2c570ed8d1..590e406517 100644
--- a/arch/sandbox/cpu/sdl.c
+++ b/arch/sandbox/cpu/sdl.c
@@ -6,6 +6,7 @@
 #include <errno.h>
 #include <unistd.h>
 #include <stdbool.h>
+#include <sysreset.h>
 #include <linux/input.h>
 #include <SDL2/SDL.h>
 #include <asm/state.h>
@@ -81,7 +82,7 @@ static void sandbox_sdl_poll_events(void)
 		switch (event.type) {
 		case SDL_QUIT:
 			puts("LCD window closed - quitting\n");
-			reset_cpu();
+			sysreset_walk(SYSRESET_POWER_OFF);
 			break;
 		}
 	}
diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile
index b6a88479b2..f810b4752f 100644
--- a/arch/sandbox/dts/Makefile
+++ b/arch/sandbox/dts/Makefile
@@ -18,4 +18,4 @@ PHONY += dtbs
 dtbs: $(addprefix $(obj)/, $(dtb-y))
 	@:
 
-clean-files := *.dtb
+clean-files := *.dtb *.dtbo
diff --git a/arch/sandbox/dts/cedit.dtsi b/arch/sandbox/dts/cedit.dtsi
new file mode 100644
index 0000000000..a9eb4c2d59
--- /dev/null
+++ b/arch/sandbox/dts/cedit.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Expo definition for the configuration editor
+ *
+ * This used for testing building an expo from a data file. This devicetree
+ * provides a description of the objects to be created.
+ */
+
+#include <test/cedit-test.h>
+
+&cedit {
+	dynamic-start = <ID_DYNAMIC_START>;
+
+	scenes {
+		main {
+			id = <ID_SCENE1>;
+
+			/* value refers to the matching id in /strings */
+			title-id = <ID_SCENE1_TITLE>;
+
+			/* simple string is used as it is */
+			prompt = "UP and DOWN to choose, ENTER to select";
+
+			/* defines a menu within the scene */
+			cpu-speed {
+				type = "menu";
+				id = <ID_CPU_SPEED>;
+
+				/*
+				 * has both string and ID. The string is ignored
+				 * if the ID is present and points to a string
+				 */
+				title = "CPU speed";
+				title-id = <ID_CPU_SPEED_TITLE>;
+
+				/* menu items as simple strings */
+				item-label = "2 GHz", "2.5 GHz", "3 GHz";
+
+				/* IDs for the menu items */
+				item-id = <ID_CPU_SPEED_1 ID_CPU_SPEED_2
+					ID_CPU_SPEED_3>;
+			};
+
+			power-loss {
+				type = "menu";
+				id = <ID_POWER_LOSS>;
+
+				title = "AC Power";
+				item-label = "Always Off", "Always On",
+					"Memory";
+
+				item-id = <ID_AC_OFF ID_AC_ON ID_AC_MEMORY>;
+			};
+		};
+	};
+
+	strings {
+		title {
+			id = <ID_SCENE1_TITLE>;
+			value = "Test Configuration";
+			value-es = "configuración de prueba";
+		};
+	};
+};
diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
index 30a305c4d2..8aaf911a41 100644
--- a/arch/sandbox/dts/sandbox.dtsi
+++ b/arch/sandbox/dts/sandbox.dtsi
@@ -16,6 +16,12 @@
 		stdout-path = "/serial";
 	};
 
+	cedit-theme {
+		font-size = <30>;
+		menu-inset = <3>;
+		menuitem-gap-y = <1>;
+	};
+
 	alarm_wdt: alarm-wdt {
 		compatible = "sandbox,alarm-wdt";
 		timeout-sec = <5>;
@@ -445,6 +451,15 @@
 	thermal {
 		compatible = "sandbox,thermal";
 	};
+
+	arm-ffa-emul {
+		compatible = "sandbox,arm-ffa-emul";
+
+		sandbox-arm-ffa {
+				compatible = "sandbox,arm-ffa";
+		};
+	};
+
 };
 
 &cros_ec {
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index ff9f9222e6..f351d5cb84 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -96,6 +96,8 @@
 
 		theme {
 			font-size = <30>;
+			menu-inset = <3>;
+			menuitem-gap-y = <1>;
 		};
 
 		/*
@@ -139,6 +141,15 @@
 		};
 	};
 
+	cedit: cedit {
+	};
+
+	cedit-theme {
+		font-size = <30>;
+		menu-inset = <3>;
+		menuitem-gap-y = <1>;
+	};
+
 	fuzzing-engine {
 		compatible = "sandbox,fuzzing-engine";
 	};
@@ -1820,6 +1831,14 @@
 	extcon {
 		compatible = "sandbox,extcon";
 	};
+
+	arm-ffa-emul {
+		compatible = "sandbox,arm-ffa-emul";
+
+		sandbox-arm-ffa {
+				compatible = "sandbox,arm-ffa";
+		};
+	};
 };
 
 #include "sandbox_pmic.dtsi"
@@ -1828,3 +1847,5 @@
 #ifdef CONFIG_SANDBOX_VPL
 #include "sandbox_vpl.dtsi"
 #endif
+
+#include "cedit.dtsi"
diff --git a/arch/sandbox/include/asm/axi.h b/arch/sandbox/include/asm/axi.h
index d483f7b65a..5b94beda0a 100644
--- a/arch/sandbox/include/asm/axi.h
+++ b/arch/sandbox/include/asm/axi.h
@@ -14,8 +14,8 @@
  * @bus:     The AXI bus from which to retrieve a emulation device
  * @address: The address of a transfer that should be handled by a emulation
  *	     device
- * @length:  The data width of a transfer that should be handled by a emulation
- *	     device
+ * @size:    A constant indicating the data width of the transfer that
+ *	     should be handled by an emulation device
  * @emulp:   Pointer to a buffer receiving the emulation device that handles
  *	     the transfer specified by the address and length parameters
  *
@@ -45,8 +45,8 @@
  * Return: 0 of OK, -ENODEV if no device capable of handling the specified
  *	   transfer exists or the device could not be retrieved
  */
-int axi_sandbox_get_emul(struct udevice *bus, ulong address, uint length,
-			 struct udevice **emulp);
+int axi_sandbox_get_emul(struct udevice *bus, ulong address,
+			 const enum axi_size_t size, struct udevice **emulp);
 /**
  * axi_get_store() - Get address of internal storage of a emulated AXI device
  * @dev:	Emulated AXI device to get the pointer of the internal storage
diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h
index f4ce72d566..f0ab3ba5c1 100644
--- a/arch/sandbox/include/asm/global_data.h
+++ b/arch/sandbox/include/asm/global_data.h
@@ -13,6 +13,10 @@
 struct arch_global_data {
 	uint8_t		*ram_buf;	/* emulated RAM buffer */
 	void		*text_base;	/* pointer to base of text region */
+	ulong table_start;		/* Start address of x86 tables */
+	ulong table_end;		/* End address of x86 tables */
+	ulong table_start_high;		/* Start address of high x86 tables */
+	ulong table_end_high;		/* End address of high x86 tables */
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/sandbox/include/asm/sandbox_arm_ffa.h b/arch/sandbox/include/asm/sandbox_arm_ffa.h
new file mode 100644
index 0000000000..be2790f496
--- /dev/null
+++ b/arch/sandbox/include/asm/sandbox_arm_ffa.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#ifndef __SANDBOX_ARM_FFA_H
+#define __SANDBOX_ARM_FFA_H
+
+#include <arm_ffa.h>
+
+/*
+ * This header provides public sandbox FF-A emulator declarations
+ * and declarations needed by FF-A sandbox clients
+ */
+
+/* UUIDs strings of the emulated services */
+#define SANDBOX_SERVICE1_UUID	"ed32d533-4209-99e6-2d72-cdd998a79cc0"
+#define SANDBOX_SERVICE2_UUID	"ed32d544-4209-99e6-2d72-cdd998a79cc0"
+
+/* IDs of the emulated secure partitions (SPs) */
+#define SANDBOX_SP1_ID 0x1245
+#define SANDBOX_SP2_ID 0x9836
+#define SANDBOX_SP3_ID 0x6452
+#define SANDBOX_SP4_ID 0x7814
+
+/* Invalid service UUID (no matching SP) */
+#define SANDBOX_SERVICE3_UUID	"55d532ed-0942-e699-722d-c09ca798d9cd"
+
+/* Invalid service UUID (invalid UUID string format) */
+#define SANDBOX_SERVICE4_UUID	"32ed-0942-e699-722d-c09ca798d9cd"
+
+/* Number of valid services */
+#define SANDBOX_SP_COUNT_PER_VALID_SERVICE	2
+
+/**
+ * struct ffa_sandbox_data - query ABI state data structure
+ * @data0_size:	size of the first argument
+ * @data0:	pointer to the first argument
+ * @data1_size>:	size of the second argument
+ * @data1:	pointer to the second argument
+ *
+ * Used to pass various types of data with different sizes between
+ * the test cases and the sandbox emulator.
+ * The data is for querying FF-A ABIs state.
+ */
+struct ffa_sandbox_data {
+	u32 data0_size; /* size of the first argument */
+	void *data0; /* pointer to the first argument */
+	u32 data1_size; /* size of the second argument */
+	void *data1; /* pointer to the second argument */
+};
+
+/* The sandbox FF-A  emulator public functions */
+
+/**
+ * sandbox_query_ffa_emul_state() - Inspect the FF-A ABIs
+ * @queried_func_id:	The FF-A function to be queried
+ * @func_data:  Pointer to the FF-A function arguments container structure
+ *
+ * Query the status of FF-A ABI specified in the input argument.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int sandbox_query_ffa_emul_state(u32 queried_func_id,
+				 struct ffa_sandbox_data *func_data);
+
+#endif
diff --git a/arch/sandbox/include/asm/sandbox_arm_ffa_priv.h b/arch/sandbox/include/asm/sandbox_arm_ffa_priv.h
new file mode 100644
index 0000000000..b0881822d7
--- /dev/null
+++ b/arch/sandbox/include/asm/sandbox_arm_ffa_priv.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#ifndef __SANDBOX_ARM_FFA_PRV_H
+#define __SANDBOX_ARM_FFA_PRV_H
+
+#include <arm_ffa_priv.h>
+
+/* This header is exclusively used by the Sandbox FF-A driver and emulator */
+
+/* Non-secure physical FF-A instance */
+#define NS_PHYS_ENDPOINT_ID (0)
+
+#define GET_NS_PHYS_ENDPOINT_ID_MASK		GENMASK(31, 16)
+#define GET_NS_PHYS_ENDPOINT_ID(x)		\
+			((u16)(FIELD_GET(GET_NS_PHYS_ENDPOINT_ID_MASK, (x))))
+
+/* Helper macro for reading the destination partition ID */
+#define GET_DST_SP_ID_MASK		GENMASK(15, 0)
+#define GET_DST_SP_ID(x)		\
+			((u16)(FIELD_GET(GET_DST_SP_ID_MASK, (x))))
+
+/* Helper macro for setting the source partition ID */
+#define PREP_SRC_SP_ID_MASK		GENMASK(31, 16)
+#define PREP_SRC_SP_ID(x)		\
+			(FIELD_PREP(PREP_SRC_SP_ID_MASK, (x)))
+
+/* Helper macro for setting the destination endpoint ID */
+#define PREP_NS_PHYS_ENDPOINT_ID_MASK		GENMASK(15, 0)
+#define PREP_NS_PHYS_ENDPOINT_ID(x)		\
+			(FIELD_PREP(PREP_NS_PHYS_ENDPOINT_ID_MASK, (x)))
+
+/*  RX/TX buffers minimum size */
+#define RXTX_BUFFERS_MIN_SIZE (RXTX_4K)
+#define RXTX_BUFFERS_MIN_PAGES (1)
+
+/* MBZ registers info */
+
+/* x1-x7 MBZ */
+#define FFA_X1X7_MBZ_CNT (7)
+#define FFA_X1X7_MBZ_REG_START (&res->a1)
+
+/* x4-x7 MBZ */
+#define FFA_X4X7_MBZ_CNT (4)
+#define FFA_X4X7_MBZ_REG_START (&res->a4)
+
+/* x3-x7 MBZ */
+#define FFA_X3X7_MBZ_CNT (5)
+#define FFA_X3_MBZ_REG_START (&res->a3)
+
+/* number of emulated FF-A secure partitions (SPs) */
+#define SANDBOX_PARTITIONS_CNT (4)
+
+/* Binary data of the emulated services UUIDs */
+
+/* service 1  UUID binary data (little-endian format) */
+#define SANDBOX_SERVICE1_UUID_A1	0xed32d533
+#define SANDBOX_SERVICE1_UUID_A2	0x99e64209
+#define SANDBOX_SERVICE1_UUID_A3	0x9cc02d72
+#define SANDBOX_SERVICE1_UUID_A4	0xcdd998a7
+
+/* service 2  UUID binary data (little-endian format) */
+#define SANDBOX_SERVICE2_UUID_A1	0xed32d544
+#define SANDBOX_SERVICE2_UUID_A2	0x99e64209
+#define SANDBOX_SERVICE2_UUID_A3	0x9cc02d72
+#define SANDBOX_SERVICE2_UUID_A4	0xcdd998a7
+
+/**
+ * struct ffa_rxtxpair_info - structure hosting the RX/TX buffers flags
+ * @rxbuf_owned:	RX buffer ownership flag (the owner is non secure world)
+ * @rxbuf_mapped:	RX buffer mapping flag
+ * @txbuf_owned	TX buffer ownership flag
+ * @txbuf_mapped:	TX buffer mapping flag
+ * @rxtx_buf_size:	RX/TX buffers size
+ *
+ * Hosts the ownership/mapping flags of the RX/TX buffers
+ * When a buffer is owned/mapped its corresponding flag is set to 1 otherwise 0.
+ */
+struct ffa_rxtxpair_info {
+	u8 rxbuf_owned;
+	u8 rxbuf_mapped;
+	u8 txbuf_owned;
+	u8 txbuf_mapped;
+	u32 rxtx_buf_size;
+};
+
+/**
+ * struct sandbox_ffa_emul - emulator data
+ *
+ * @fwk_version:	FF-A framework version
+ * @id:	u-boot endpoint ID
+ * @partitions:	The partitions descriptors structure
+ * @pair:	The RX/TX buffers pair
+ * @pair_info:	The RX/TX buffers pair flags and size
+ * @test_ffa_data:	The data of the FF-A bus under test
+ *
+ * Hosts all the emulated secure world data.
+ */
+struct sandbox_ffa_emul {
+	u32 fwk_version;
+	u16 id;
+	struct ffa_partitions partitions;
+	struct ffa_rxtxpair pair;
+	struct ffa_rxtxpair_info pair_info;
+};
+
+/**
+ * ffa_emul_find() - Finds the FF-A emulator
+ * @dev:	the sandbox FF-A device (sandbox-arm-ffa)
+ * @emulp:	the FF-A emulator device (sandbox-ffa-emul)
+ * Return:
+ * 0 on success. Otherwise, failure
+ */
+int ffa_emul_find(struct udevice *dev, struct udevice **emulp);
+
+#endif
diff --git a/arch/sandbox/include/asm/sdl.h b/arch/sandbox/include/asm/sdl.h
index 56dcb84803..ee4991f7c2 100644
--- a/arch/sandbox/include/asm/sdl.h
+++ b/arch/sandbox/include/asm/sdl.h
@@ -7,6 +7,7 @@
 #define __SANDBOX_SDL_H
 
 #include <errno.h>
+#include <video.h>
 
 #ifdef CONFIG_SANDBOX_SDL
 
@@ -87,6 +88,22 @@ int sandbox_sdl_sound_stop(void);
  */
 int sandbox_sdl_sound_init(int rate, int channels);
 
+/**
+ * sandbox_sdl_set_bpp() - Set the depth of the sandbox display
+ *
+ * The device must not be active when this function is called. It activiates it
+ * before returning.
+ *
+ * This updates the depth value and adjusts a few other settings accordingly.
+ * It must be called before the display is probed.
+ *
+ * @dev: Device to adjust
+ * @l2bpp: depth to set
+ * Return: 0 if the device was already active, other error if it fails to probe
+ * after the change
+ */
+int sandbox_sdl_set_bpp(struct udevice *dev, enum video_log2_bpp l2bpp);
+
 #else
 static inline int sandbox_sdl_init_display(int width, int height, int log2_bpp,
 					   bool double_size)
@@ -134,6 +151,12 @@ static inline int sandbox_sdl_sound_init(int rate, int channels)
 	return -ENODEV;
 }
 
+static inline int sandbox_sdl_set_bpp(struct udevice *dev,
+				      enum video_log2_bpp l2bpp)
+{
+	return -ENOSYS;
+}
+
 #endif
 
 #endif
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index e482271fe9..17159f8d67 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_TEST_H
 #define __ASM_TEST_H
 
-#include <video.h>
 #include <pci_ids.h>
 
 struct unit_test_state;
@@ -300,30 +299,6 @@ void sandbox_cros_ec_set_test_flags(struct udevice *dev, uint flags);
  */
 int sandbox_cros_ec_get_pwm_duty(struct udevice *dev, uint index, uint *duty);
 
-#if IS_ENABLED(CONFIG_SANDBOX_SDL)
-/**
- * sandbox_sdl_set_bpp() - Set the depth of the sandbox display
- *
- * The device must not be active when this function is called. It activiates it
- * before returning.
- *
- * This updates the depth value and adjusts a few other settings accordingly.
- * It must be called before the display is probed.
- *
- * @dev: Device to adjust
- * @l2bpp: depth to set
- * Return: 0 if the device was already active, other error if it fails to probe
- * after the change
- */
-int sandbox_sdl_set_bpp(struct udevice *dev, enum video_log2_bpp l2bpp);
-#else
-static inline int sandbox_sdl_set_bpp(struct udevice *dev,
-				      enum video_log2_bpp l2bpp)
-{
-	return -ENOSYS;
-}
-#endif
-
 /**
  * sandbox_set_fake_efi_mgr_dev() - Control EFI bootmgr producing valid bootflow
  *
diff --git a/arch/sh/include/asm/mmc.h b/arch/sh/include/asm/mmc.h
deleted file mode 100644
index 5732b2bca3..0000000000
--- a/arch/sh/include/asm/mmc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Renesas SuperH MMCIF driver.
- *
- * Copyright (C)  2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * Copyright (C)  2012 Renesas Solutions Corp.
- *
- */
-#ifndef _SH_MMC_H_
-#define _SH_MMC_H_
-
-int mmcif_mmc_init(void);
-
-#endif /* _SH_MMC_H_ */
diff --git a/arch/sh/include/asm/unaligned.h b/arch/sh/include/asm/unaligned.h
index 5acf081962..7fb482abc3 100644
--- a/arch/sh/include/asm/unaligned.h
+++ b/arch/sh/include/asm/unaligned.h
@@ -1,20 +1,2 @@
-#ifndef _ASM_SH_UNALIGNED_H
-#define _ASM_SH_UNALIGNED_H
-
-/* Copy from linux-kernel. */
-
-/* Other than SH4A, SH can't handle unaligned accesses. */
-#include <linux/compiler.h>
-#if defined(__BIG_ENDIAN__)
-#define get_unaligned   __get_unaligned_be
-#define put_unaligned   __put_unaligned_be
-#elif defined(__LITTLE_ENDIAN__)
-#define get_unaligned   __get_unaligned_le
-#define put_unaligned   __put_unaligned_le
-#endif
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-#endif /* _ASM_SH_UNALIGNED_H */
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <asm-generic/unaligned.h>
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index 1295121ae5..f477d513ef 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -25,7 +25,7 @@
 #include <asm/arch/pei_data.h>
 #include <asm/arch/pm.h>
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	return mrc_common_board_get_usable_ram_top(total_size);
 }
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index f4ee4cdf5d..26352df421 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -27,7 +27,7 @@ unsigned int install_e820_map(unsigned int max_entries,
  * address, and how far U-Boot is moved by relocation are set in the global
  * data structure.
  */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	uintptr_t dest_addr = 0;
 	int i;
diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c
index 19a25dd640..d8920effd3 100644
--- a/arch/x86/cpu/efi/payload.c
+++ b/arch/x86/cpu/efi/payload.c
@@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
  * the relocation address, and how far U-Boot is moved by relocation are
  * set in the global data structure.
  */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	struct efi_mem_desc *desc, *end;
 	struct efi_entry_memmap *map;
diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c
index f3086db42c..56f3326146 100644
--- a/arch/x86/cpu/efi/sdram.c
+++ b/arch/x86/cpu/efi/sdram.c
@@ -11,7 +11,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	return (ulong)efi_get_ram_base() + gd->ram_size;
 }
diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
index fae2544c45..f3f3527237 100644
--- a/arch/x86/cpu/i386/interrupt.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -266,6 +266,10 @@ int interrupt_init(void)
 	struct udevice *dev;
 	int ret;
 
+	/*
+	 * When running as an EFI application we are not in control of
+	 * interrupts and should leave them alone.
+	 */
 	if (!ll_boot_init())
 		return 0;
 
@@ -274,11 +278,6 @@ int interrupt_init(void)
 	if (ret && ret != -ENODEV)
 		return ret;
 
-	/*
-	 * When running as an EFI application we are not in control of
-	 * interrupts and should leave them alone.
-	 */
-#ifndef CONFIG_EFI_APP
 	/* Just in case... */
 	disable_interrupts();
 
@@ -294,14 +293,8 @@ int interrupt_init(void)
 	/* Initialize core interrupt and exception functionality of CPU */
 	cpu_init_interrupts();
 
-	/*
-	 * It is now safe to enable interrupts.
-	 *
-	 * TODO(sjg@chromium.org): But we don't handle these correctly when
-	 * booted from EFI.
-	 */
+	/* It is now safe to enable interrupts */
 	enable_interrupts();
-#endif
 
 	return 0;
 }
diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c
index 69405d740b..56cc253831 100644
--- a/arch/x86/cpu/intel_common/mrc.c
+++ b/arch/x86/cpu/intel_common/mrc.c
@@ -3,6 +3,8 @@
  * Copyright (c) 2016 Google, Inc
  */
 
+#define LOG_CATEGORY	UCLASS_RAM
+
 #include <common.h>
 #include <dm.h>
 #include <init.h>
@@ -144,12 +146,10 @@ int mrc_locate_spd(struct udevice *dev, int size, const void **spd_datap)
 
 	ret = gpio_request_list_by_name(dev, "board-id-gpios", desc,
 					ARRAY_SIZE(desc), GPIOD_IS_IN);
-	if (ret < 0) {
-		debug("%s: gpio ret=%d\n", __func__, ret);
-		return ret;
-	}
+	if (ret < 0)
+		return log_msg_ret("gpio", ret);
 	spd_index = dm_gpio_get_values_as_int(desc, ret);
-	debug("spd index %d\n", spd_index);
+	log_debug("spd index %d\n", spd_index);
 
 	node = fdt_first_subnode(blob, dev_of_offset(dev));
 	if (node < 0)
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 1a0ec433e6..95a826da71 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -9,6 +9,8 @@
  * Copyright (C) 2011 Google Inc.
  */
 
+#define LOG_CATEGORY	UCLASS_RAM
+
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
@@ -44,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CMOS_OFFSET_MRC_SEED_S3		156
 #define CMOS_OFFSET_MRC_SEED_CHK	160
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	return mrc_common_board_get_usable_ram_top(total_size);
 }
@@ -213,7 +215,7 @@ static int copy_spd(struct udevice *dev, struct pei_data *peid)
 
 	ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data);
 	if (ret) {
-		debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret);
+		log_debug("Could not locate SPD (err=%d)\n", ret);
 		return ret;
 	}
 
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index e69dfb552b..9c24ae984e 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -30,6 +30,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
+	"Uncacheable",
+	"Combine",
+	"2",
+	"3",
+	"Through",
+	"Protect",
+	"Back",
+};
+
 /* Prepare to adjust MTRRs */
 void mtrr_open(struct mtrr_state *state, bool do_caches)
 {
@@ -156,8 +166,12 @@ int mtrr_commit(bool do_caches)
 	debug("open done\n");
 	qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr);
 	for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
-		mtrr_set_next_var(req->type, req->start, req->size);
+		set_var_mtrr(i, req->type, req->start, req->size);
 
+	/* Clear the ones that are unused */
+	debug("clear\n");
+	for (; i < mtrr_get_var_count(); i++)
+		wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
 	debug("close\n");
 	mtrr_close(&state, do_caches);
 	debug("mtrr done\n");
@@ -320,3 +334,54 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask)
 
 	return mtrr_start_op(cpu_select, &oper);
 }
+
+static void read_mtrrs_(void *arg)
+{
+	struct mtrr_info *info = arg;
+
+	mtrr_read_all(info);
+}
+
+int mtrr_list(int reg_count, int cpu_select)
+{
+	struct mtrr_info info;
+	int ret;
+	int i;
+
+	printf("Reg Valid Write-type   %-16s %-16s %-16s\n", "Base   ||",
+	       "Mask   ||", "Size   ||");
+	memset(&info, '\0', sizeof(info));
+	ret = mp_run_on_cpus(cpu_select, read_mtrrs_, &info);
+	if (ret)
+		return log_msg_ret("run", ret);
+	for (i = 0; i < reg_count; i++) {
+		const char *type = "Invalid";
+		u64 base, mask, size;
+		bool valid;
+
+		base = info.mtrr[i].base;
+		mask = info.mtrr[i].mask;
+		size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
+		size |= (1 << 12) - 1;
+		size += 1;
+		valid = mask & MTRR_PHYS_MASK_VALID;
+		type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
+		printf("%d   %-5s %-12s %016llx %016llx %016llx\n", i,
+		       valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
+		       mask & ~MTRR_PHYS_MASK_VALID, size);
+	}
+
+	return 0;
+}
+
+int mtrr_get_type_by_name(const char *typename)
+{
+	int i;
+
+	for (i = 0; i < MTRR_TYPE_COUNT; i++) {
+		if (*typename == *mtrr_type_name[i])
+			return i;
+	}
+
+	return -EINVAL;
+};
diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c
index 595c397d4a..d83abf0052 100644
--- a/arch/x86/cpu/qemu/dram.c
+++ b/arch/x86/cpu/qemu/dram.c
@@ -8,6 +8,7 @@
 #include <asm/global_data.h>
 #include <asm/post.h>
 #include <asm/arch/qemu.h>
+#include <linux/sizes.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -71,7 +72,7 @@ int dram_init_banksize(void)
  * the relocation address, and how far U-Boot is moved by relocation are
  * set in the global data structure.
  */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	return qemu_get_low_memory_size();
 }
diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c
index 19e54c5202..ebfe595644 100644
--- a/arch/x86/cpu/qemu/e820.c
+++ b/arch/x86/cpu/qemu/e820.c
@@ -12,6 +12,7 @@
 #include <asm/e820.h>
 #include <asm/arch/qemu.h>
 #include <asm/global_data.h>
+#include <linux/sizes.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index e54082df7f..7041455608 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -48,7 +48,7 @@ static void enable_pm_ich9(void)
 	pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
 }
 
-static void qemu_chipset_init(void)
+void qemu_chipset_init(void)
 {
 	u16 device, xbcs;
 	int pam, i;
@@ -97,7 +97,7 @@ static void qemu_chipset_init(void)
 	}
 }
 
-#if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
+#if CONFIG_IS_ENABLED(X86_32BIT_INIT)
 int arch_cpu_init(void)
 {
 	post_code(POST_CPU_INIT);
diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c
index 8b1ee2d5ae..ad98f3e07b 100644
--- a/arch/x86/cpu/quark/dram.c
+++ b/arch/x86/cpu/quark/dram.c
@@ -184,7 +184,7 @@ int dram_init_banksize(void)
  * the relocation address, and how far U-Boot is moved by relocation are
  * set in the global data structure.
  */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	return gd->ram_size;
 }
diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c
index d748d5c7d4..fbb33b246e 100644
--- a/arch/x86/cpu/slimbootloader/sdram.c
+++ b/arch/x86/cpu/slimbootloader/sdram.c
@@ -48,7 +48,7 @@ static struct sbl_memory_map_info *get_memory_map_info(void)
  * @total_size: The memory size that u-boot occupies
  * Return:    : The top available memory address lower than 4GB
  */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	struct sbl_memory_map_info *data;
 	int i;
diff --git a/arch/x86/cpu/start64.S b/arch/x86/cpu/start64.S
index 7be834788b..78e894d2a2 100644
--- a/arch/x86/cpu/start64.S
+++ b/arch/x86/cpu/start64.S
@@ -26,3 +26,22 @@ _start:
 
 	/* Should not return here */
 	jmp	.
+
+.globl board_init_f_r_trampoline64
+.type board_init_f_r_trampoline64, @function
+board_init_f_r_trampoline64:
+	/*
+	 * SDRAM has been initialised, U-Boot code has been copied into
+	 * RAM, BSS has been cleared and relocation adjustments have been
+	 * made. It is now time to jump into the in-RAM copy of U-Boot
+	 *
+	 * %eax = Address of top of new stack
+	 */
+
+	/* Stack grows down from top of SDRAM */
+	movq	%rsi, %rsp
+
+	/* New gd is in rdi */
+
+	/* Re-enter U-Boot by calling board_init_f_r() */
+	call	board_init_f_r
diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c
index 8a4b1c5d2d..ee74a1f043 100644
--- a/arch/x86/cpu/tangier/sdram.c
+++ b/arch/x86/cpu/tangier/sdram.c
@@ -204,7 +204,7 @@ unsigned int install_e820_map(unsigned int max_entries,
  * address, and how far U-Boot is moved by relocation are set in the global
  * data structure.
  */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	struct sfi_table_simple *sb;
 	struct sfi_mem_entry *mentry;
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 36956f40bd..c904b7d0b6 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -314,6 +314,7 @@
 						00 00 00 00 00 00 00 00];
 					};
 				micron_4Gb_1600_1.35v_x16 {
+					bootph-all;
 					reg = <2>;
 					data = [92 11 0b 03 04 19 02 02
 						03 11 01 08 0a 00 fe 00
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index ea816ca746..ac4865300f 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -62,7 +62,7 @@ struct setup_indirect {
 /**
  * struct setup_header - Information needed by Linux to boot
  *
- * See https://www.kernel.org/doc/html/latest/x86/boot.html
+ * See https://www.kernel.org/doc/html/latest/arch/x86/boot.html
  */
 struct setup_header {
 	__u8	setup_sects;
diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h
index 2c78b22d0d..12fa395ffd 100644
--- a/arch/x86/include/asm/cb_sysinfo.h
+++ b/arch/x86/include/asm/cb_sysinfo.h
@@ -138,6 +138,8 @@
  * @rsdp: Pointer to ACPI RSDP table
  * @unimpl_count: Number of entries in unimpl_map[]
  * @unimpl: List of unimplemented IDs (bottom 8 bits only)
+ * @table_size: Number of bytes taken up by the sysinfo table
+ * @rec_count: Number of records in the sysinfo table
  */
 struct sysinfo_t {
 	unsigned int cpu_khz;
@@ -219,6 +221,8 @@ struct sysinfo_t {
 	void *rsdp;
 	u32 unimpl_count;
 	u8 unimpl[SYSINFO_MAX_UNIMPL];
+	uint table_size;
+	uint rec_count;
 };
 
 extern struct sysinfo_t lib_sysinfo;
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 22d103df4e..ea58259ad7 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -123,6 +123,10 @@ struct arch_global_data {
 #endif
 	void *itss_priv;		/* Private ITSS data pointer */
 	ulong coreboot_table;		/* Address of coreboot table */
+	ulong table_start;		/* Start address of x86 tables */
+	ulong table_end;		/* End address of x86 tables */
+	ulong table_start_high;		/* Start address of high x86 tables */
+	ulong table_end_high;		/* End address of high x86 tables */
 };
 
 #endif
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index ca2edc7878..2e995f5406 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -190,6 +190,26 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask);
  */
 int mtrr_get_var_count(void);
 
+/**
+ * mtrr_list() - List the MTRRs
+ *
+ * Shows a list of all the MTRRs including their values
+ *
+ * @reg_count: Number of registers to show. You can use mtrr_get_var_count() for
+ * this
+ * @cpu_select: CPU to use. Use MP_SELECT_BSP for the boot CPU
+ * Returns: 0 if OK, -ve if the CPU was not found
+ */
+int mtrr_list(int reg_count, int cpu_select);
+
+/**
+ * mtrr_get_type_by_name() - Get the type of an MTRR given its type name
+ *
+ * @typename: Name to check
+ * Returns: MTRR type (MTRR_TYPE_...) or -EINVAL if invalid
+ */
+int mtrr_get_type_by_name(const char *typename);
+
 #endif
 
 #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
diff --git a/arch/x86/include/asm/qemu.h b/arch/x86/include/asm/qemu.h
new file mode 100644
index 0000000000..f1e95ffd7a
--- /dev/null
+++ b/arch/x86/include/asm/qemu.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Generic QEMU header
+ *
+ * Copyright 2023 Google LLC
+ */
+
+#ifndef __QEMU_H
+#define __QEMU_H
+
+/* set up the chipset for QEMU so that video can be used */
+void qemu_chipset_init(void);
+
+#endif
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 8f38c2d1c6..3acc58ad74 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -77,7 +77,7 @@ int x86_cleanup_before_linux(void);
 void x86_enable_caches(void);
 void x86_disable_caches(void);
 int x86_init_cache(void);
-phys_size_t board_get_usable_ram_top(phys_size_t total_size);
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size);
 int default_print_cpuinfo(void);
 
 /* Set up a UART which can be used with printch(), printhex8(), etc. */
@@ -102,8 +102,31 @@ int video_bios_init(void);
  */
 int fsp_save_s3_stack(void);
 
-void	board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
-void	board_init_f_r(void) __attribute__ ((noreturn));
+/**
+ * board_init_f_r_trampoline() - jump to relocated address with new stack
+ *
+ * @sp: New stack pointer to use
+ */
+void __noreturn board_init_f_r_trampoline(ulong sp);
+
+/**
+ * board_init_f_r() - jump to relocated U-Boot
+ *
+ * This is used to jump from pre-relocation to post-relocation U-Boot. It
+ * enables the cache and jump to the new location.
+ */
+void __noreturn board_init_f_r(void);
+
+/*
+ * board_init_f_r_trampoline64() - jump to relocated address with new stack
+ *
+ * This is the 64-bit version
+ *
+ * @new_gd: New global_data pointer to use
+ * @sp: New stack pointer to pass on to board_init_r()
+ */
+void __noreturn board_init_f_r_trampoline64(struct global_data *new_gd,
+					    ulong sp);
 
 int arch_misc_init(void);
 
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 000b38ea89..9ad74dc0b9 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -72,4 +72,31 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
  */
 void zimage_dump(struct boot_params *base_ptr);
 
+/**
+ * zboot_start() - Boot a zimage
+ *
+ * Boot a zimage, given the component parts
+ *
+ * @addr: Address where the bzImage is moved before booting, either
+ *	BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
+ * @base: Pointer to the boot parameters, typically at address
+ *	DEFAULT_SETUP_BASE
+ * @initrd: Address of the initial ramdisk, or 0 if none
+ * @initrd_size: Size of the initial ramdisk, or 0 if none
+ * @cmdline: Command line to use for booting
+ * Return: -EFAULT on error (normally it does not return)
+ */
+int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size,
+		ulong base, char *cmdline);
+
+/*
+ * zimage_get_kernel_version() - Get the version string from a kernel
+ *
+ * @params: boot_params pointer
+ * @kernel_base: base address of kernel
+ * Return: Kernel version as a NUL-terminated string
+ */
+const char *zimage_get_kernel_version(struct boot_params *params,
+				      void *kernel_base);
+
 #endif
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index b0612ae6dd..90a7618ecf 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -4,16 +4,17 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 obj-y	+= bdinfo.o
-ifndef CONFIG_X86_64
-ifndef CONFIG_TPL_BUILD
+
+ifndef CONFIG_$(SPL_TPL_)X86_64
 obj-y += bios.o
 obj-y += bios_asm.o
 obj-y += bios_interrupts.o
 endif
-endif
+
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_X86_32BIT_INIT) += string.o
 endif
+
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 endif
diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c
index 15390070fe..124058442c 100644
--- a/arch/x86/lib/bdinfo.c
+++ b/arch/x86/lib/bdinfo.c
@@ -22,6 +22,11 @@ void arch_print_bdinfo(void)
 	bdinfo_print_num_l("vendor", gd->arch.x86_vendor);
 	bdinfo_print_str(" name", cpu_vendor_name(gd->arch.x86_vendor));
 	bdinfo_print_num_l("model", gd->arch.x86_model);
+	bdinfo_print_num_l("phys_addr in bits", cpu_phys_address_size());
+	bdinfo_print_num_l("table start", gd->arch.table_start);
+	bdinfo_print_num_l("table end", gd->arch.table_end);
+	bdinfo_print_num_l(" high start", gd->arch.table_start_high);
+	bdinfo_print_num_l(" high end", gd->arch.table_end_high);
 
 	if (IS_ENABLED(CONFIG_EFI_STUB))
 		efi_show_bdinfo();
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
index 94349ba807..f146bbd542 100644
--- a/arch/x86/lib/bios.c
+++ b/arch/x86/lib/bios.c
@@ -23,7 +23,7 @@
 static int (*int_handler[256])(void);
 
 /* to have a common register file for interrupt handlers */
-#ifndef CONFIG_BIOSEMU
+#if !CONFIG_IS_ENABLED(BIOSEMU)
 X86EMU_sysEnv _X86EMU_env;
 #endif
 
@@ -78,7 +78,7 @@ static int int_exception_handler(void)
 	};
 	struct eregs *regs = &reg_info;
 
-	debug("Oops, exception %d while executing option rom\n", regs->vector);
+	log_err("Exception %d while executing option rom\n", regs->vector);
 	cpu_hlt();
 
 	return 0;
@@ -204,7 +204,7 @@ static u8 vbe_get_mode_info(struct vesa_state *mi)
 
 	realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode,
 			   0x0000, buffer_seg, buffer_adr);
-	memcpy(mi->mode_info_block, buffer, sizeof(struct vesa_state));
+	memcpy(mi->mode_info_block, buffer, sizeof(struct vesa_mode_info));
 	mi->valid = true;
 
 	return 0;
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 61cb7bc611..3196f9ddc2 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -258,7 +258,7 @@ static ulong get_sp(void)
 	ulong ret;
 
 #if CONFIG_IS_ENABLED(X86_64)
-	ret = gd->start_addr_sp;
+	asm("mov %%rsp, %0" : "=r"(ret) : );
 #else
 	asm("mov %%esp, %0" : "=r"(ret) : );
 #endif
diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib/coreboot/cb_sysinfo.c
index 42cc3a128d..dfbc80c430 100644
--- a/arch/x86/lib/coreboot/cb_sysinfo.c
+++ b/arch/x86/lib/coreboot/cb_sysinfo.c
@@ -447,6 +447,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 
 		ptr += rec->size;
 	}
+	info->table_size += (void *)ptr - (void *)header;
+	info->rec_count += header->table_entries;
 
 	return 1;
 }
@@ -462,6 +464,8 @@ int get_coreboot_info(struct sysinfo_t *info)
 	addr = locate_coreboot_table();
 	if (addr < 0)
 		return addr;
+	info->table_size = 0;
+	info->rec_count = 0;
 	ret = cb_parse_header((void *)addr, 0x1000, info);
 	if (!ret)
 		return -ENOENT;
diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
index 2bcc49f605..09d5da8c84 100644
--- a/arch/x86/lib/fsp/fsp_graphics.c
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -110,8 +110,7 @@ static int fsp_video_probe(struct udevice *dev)
 	if (ret)
 		goto err;
 
-	mtrr_add_request(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20);
-	mtrr_commit(true);
+	mtrr_set_next_var(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20);
 
 	printf("%dx%dx%d @ %x\n", uc_priv->xsize, uc_priv->ysize,
 	       vesa->bits_per_pixel, vesa->phys_base_ptr);
diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c
index 5825221d1e..eee9ce54b1 100644
--- a/arch/x86/lib/fsp1/fsp_dram.c
+++ b/arch/x86/lib/fsp1/fsp_dram.c
@@ -34,7 +34,7 @@ int dram_init(void)
  * the relocation address, and how far U-Boot is moved by relocation are
  * set in the global data structure.
  */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	return fsp_get_usable_lowmem_top(gd->arch.hob_list);
 }
diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c
index f9ea1ab3ba..a1432239cf 100644
--- a/arch/x86/lib/fsp2/fsp_dram.c
+++ b/arch/x86/lib/fsp2/fsp_dram.c
@@ -77,7 +77,7 @@ int dram_init(void)
 	return 0;
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	if (!ll_boot_init())
 		return gd->ram_size;
diff --git a/arch/x86/lib/i8254.c b/arch/x86/lib/i8254.c
index 0f97538910..a8d1db188e 100644
--- a/arch/x86/lib/i8254.c
+++ b/arch/x86/lib/i8254.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/i8254.h>
+#include <asm/ibmpc.h>
 
 #define TIMER1_VALUE		18	/* 15.6us */
 #define BEEP_FREQUENCY_HZ	440
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index f33194045f..60a2707dcf 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -21,8 +21,7 @@ int init_cache_f_r(void)
 	/*
 	 * Supported configurations:
 	 *
-	 * booting from slimbootloader - in that case the MTRRs are already set
-	 *	up
+	 * booting from slimbootloader - MTRRs are already set up
 	 * booting with FSPv1 - MTRRs are already set up
 	 * booting with FSPv2 - MTRRs must be set here
 	 * booting from coreboot - in this case there is no SPL, so we set up
@@ -30,8 +29,7 @@ int init_cache_f_r(void)
 	 * Note: if there is an SPL, then it has already set up MTRRs so we
 	 *	don't need to do that here
 	 */
-	do_mtrr &= !IS_ENABLED(CONFIG_SPL) &&
-		!IS_ENABLED(CONFIG_FSP_VERSION1) &&
+	do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
 		!IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
 
 	if (do_mtrr) {
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 2f6f688000..6494b8d263 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -6,6 +6,8 @@
  * Copyright (C) 2015 Bin Meng <bmeng.cn@gmail.com>
  */
 
+#define LOG_CATEGORY	UCLASS_RAM
+
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
@@ -197,8 +199,8 @@ static void mrccache_setup(struct mrc_output *mrc, void *data)
 	cache->signature = MRC_DATA_SIGNATURE;
 	cache->data_size = mrc->len;
 	checksum = compute_ip_checksum(mrc->buf, cache->data_size);
-	debug("Saving %d bytes for MRC output data, checksum %04x\n",
-	      cache->data_size, checksum);
+	log_debug("Saving %d bytes for MRC output data, checksum %04x\n",
+		  cache->data_size, checksum);
 	cache->checksum = checksum;
 	cache->reserved = 0;
 	memcpy(cache->data, mrc->buf, cache->data_size);
diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c
index 1eb97ac5bb..382f768149 100644
--- a/arch/x86/lib/physmem.c
+++ b/arch/x86/lib/physmem.c
@@ -14,6 +14,7 @@
 #include <asm/cpu.h>
 #include <asm/global_data.h>
 #include <linux/compiler.h>
+#include <linux/sizes.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -144,7 +145,7 @@ static void x86_phys_memset_page(phys_addr_t map_addr, uintptr_t offset, int c,
 
 	/* Make sure the window is below U-Boot. */
 	assert(window + LARGE_PAGE_SIZE <
-	       gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CFG_SYS_STACK_SIZE);
+	       gd->relocaddr - CONFIG_SYS_MALLOC_LEN - SZ_32K);
 	/* Map the page into the window and then memset the appropriate part. */
 	x86_phys_map_page(window, map_addr, 1);
 	memset((void *)(window + offset), c, size);
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index ca1645f9d6..f99df08fbe 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -3,6 +3,8 @@
  * Copyright (c) 2016 Google, Inc
  */
 
+#define LOG_CATEGORY	LOGC_BOOT
+
 #include <common.h>
 #include <cpu_func.h>
 #include <debug_uart.h>
@@ -15,14 +17,17 @@
 #include <malloc.h>
 #include <spl.h>
 #include <syscon.h>
+#include <vesa.h>
 #include <asm/cpu.h>
 #include <asm/cpu_common.h>
 #include <asm/fsp2/fsp_api.h>
 #include <asm/global_data.h>
+#include <asm/mp.h>
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
 #include <asm/processor.h>
+#include <asm/qemu.h>
 #include <asm/spl.h>
 #include <asm-generic/sections.h>
 
@@ -61,6 +66,8 @@ static int set_max_freq(void)
 
 static int x86_spl_init(void)
 {
+	struct udevice *dev;
+
 #ifndef CONFIG_TPL
 	/*
 	 * TODO(sjg@chromium.org): We use this area of RAM for the stack
@@ -74,46 +81,60 @@ static int x86_spl_init(void)
 #endif
 	int ret;
 
-	debug("%s starting\n", __func__);
+	log_debug("x86 spl starting\n");
 	if (IS_ENABLED(TPL))
 		ret = x86_cpu_reinit_f();
 	else
 		ret = x86_cpu_init_f();
 	ret = spl_init();
 	if (ret) {
-		debug("%s: spl_init() failed\n", __func__);
+		log_debug("spl_init() failed (err=%d)\n", ret);
 		return ret;
 	}
 	ret = arch_cpu_init();
 	if (ret) {
-		debug("%s: arch_cpu_init() failed\n", __func__);
+		log_debug("arch_cpu_init() failed (err=%d)\n", ret);
 		return ret;
 	}
 #ifndef CONFIG_TPL
 	ret = fsp_setup_pinctrl(NULL, NULL);
 	if (ret) {
-		debug("%s: fsp_setup_pinctrl() failed\n", __func__);
+		log_debug("fsp_setup_pinctrl() failed (err=%d)\n", ret);
 		return ret;
 	}
 #endif
-	preloader_console_init();
+	/*
+	 * spl_board_init() below sets up the console if enabled. If it isn't,
+	 * do it here. We cannot call this twice since it results in a double
+	 * banner and CI tests fail.
+	 */
+	if (!IS_ENABLED(CONFIG_SPL_BOARD_INIT))
+		preloader_console_init();
 #if !defined(CONFIG_TPL) && !CONFIG_IS_ENABLED(CPU)
 	ret = print_cpuinfo();
 	if (ret) {
-		debug("%s: print_cpuinfo() failed\n", __func__);
+		log_debug("print_cpuinfo() failed (err=%d)\n", ret);
 		return ret;
 	}
 #endif
+	/* probe the LPC so we get the GPIO_BASE set up correctly */
+	ret = uclass_first_device_err(UCLASS_LPC, &dev);
+	if (ret && ret != -ENODEV) {
+		log_debug("lpc probe failed\n");
+		return ret;
+	}
+
 	ret = dram_init();
 	if (ret) {
-		debug("%s: dram_init() failed\n", __func__);
+		log_debug("dram_init() failed (err=%d)\n", ret);
 		return ret;
 	}
+	log_debug("mrc\n");
 	if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
 		ret = mrccache_spl_save();
 		if (ret)
-			debug("%s: Failed to write to mrccache (err=%d)\n",
-			      __func__, ret);
+			log_debug("Failed to write to mrccache (err=%d)\n",
+				  ret);
 	}
 
 #ifndef CONFIG_SYS_COREBOOT
@@ -136,9 +157,29 @@ static int x86_spl_init(void)
 	 */
 	gd->new_gd = (struct global_data *)ptr;
 	memcpy(gd->new_gd, gd, sizeof(*gd));
+
+	log_debug("logging\n");
+	/*
+	 * Make sure logging is disabled when we switch, since the log system
+	 * list head will move
+	 */
+	gd->new_gd->flags &= ~GD_FLG_LOG_READY;
 	arch_setup_gd(gd->new_gd);
 	gd->start_addr_sp = (ulong)ptr;
 
+	/* start up logging again, with the new list-head location */
+	ret = log_init();
+	if (ret) {
+		log_debug("Log setup failed (err=%d)\n", ret);
+		return ret;
+	}
+
+	if (_LOG_DEBUG) {
+		ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP);
+		if (ret)
+			printf("mtrr_list failed\n");
+	}
+
 	/* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
 	ret = mtrr_add_request(MTRR_TYPE_WRBACK,
 			       (1ULL << 32) - CONFIG_XIP_ROM_SIZE,
@@ -157,6 +198,7 @@ static int x86_spl_init(void)
 		debug("Failed to set CPU frequency (err=%d)\n", ret);
 # endif
 #endif
+	log_debug("done\n");
 
 	return 0;
 }
@@ -250,4 +292,14 @@ void spl_board_init(void)
 #ifndef CONFIG_TPL
 	preloader_console_init();
 #endif
+	if (IS_ENABLED(CONFIG_QEMU))
+		qemu_chipset_init();
+
+	if (CONFIG_IS_ENABLED(VIDEO)) {
+		struct udevice *dev;
+
+		/* Set up PCI video in SPL if required */
+		uclass_first_device_err(UCLASS_PCI, &dev);
+		uclass_first_device_err(UCLASS_VIDEO, &dev);
+	}
 }
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index ea834a5035..67bc0a72ae 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -3,7 +3,7 @@
  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#define LOG_CATEGORY LOGC_BOARD
+#define LOG_CATEGORY LOGC_ACPI
 
 #include <common.h>
 #include <bloblist.h>
@@ -54,6 +54,10 @@ static struct table_info table_list[] = {
 #ifdef CONFIG_GENERATE_MP_TABLE
 	{ "mp", write_mp_table, },
 #endif
+	/*
+	 * tables which can go in the bloblist must be last in this list, so
+	 * that the calculation of gd->table_end works properly
+	 */
 #ifdef CONFIG_GENERATE_ACPI_TABLE
 	{ "acpi", write_acpi_tables, BLOBLISTT_ACPI_TABLES, 0x10000, 0x1000},
 #endif
@@ -78,33 +82,42 @@ void table_fill_string(char *dest, const char *src, size_t n, char pad)
 
 int write_tables(void)
 {
-	u32 rom_table_start;
-	u32 rom_table_end;
 	u32 high_table, table_size;
 	struct memory_area cfg_tables[ARRAY_SIZE(table_list) + 1];
+	bool use_high = false;
+	u32 rom_addr;
 	int i;
 
-	rom_table_start = ROM_TABLE_ADDR;
+	gd->arch.table_start = ROM_TABLE_ADDR;
+	rom_addr = gd->arch.table_start;
 
-	debug("Writing tables to %x:\n", rom_table_start);
+	debug("Writing tables to %x:\n", rom_addr);
 	for (i = 0; i < ARRAY_SIZE(table_list); i++) {
 		const struct table_info *table = &table_list[i];
 		int size = table->size ? : CONFIG_ROM_TABLE_SIZE;
+		u32 rom_table_end;
 
 		if (IS_ENABLED(CONFIG_BLOBLIST_TABLES) && table->tag) {
-			rom_table_start = (ulong)bloblist_add(table->tag, size,
-							      table->align);
-			if (!rom_table_start)
+			if (!gd->arch.table_end)
+				gd->arch.table_end = rom_addr;
+			rom_addr = (ulong)bloblist_add(table->tag, size,
+						       table->align);
+			if (!rom_addr)
 				return log_msg_ret("bloblist", -ENOBUFS);
+
+			/* the bloblist is always in high memory */
+			use_high = true;
+			if (!gd->arch.table_start_high)
+				gd->arch.table_start_high = rom_addr;
 		}
-		rom_table_end = table->write(rom_table_start);
+		rom_table_end = table->write(rom_addr);
 		if (!rom_table_end) {
 			log_err("Can't create configuration table %d\n", i);
 			return -EINTR;
 		}
 
 		if (IS_ENABLED(CONFIG_SEABIOS)) {
-			table_size = rom_table_end - rom_table_start;
+			table_size = rom_table_end - rom_addr;
 			high_table = (u32)(ulong)high_table_malloc(table_size);
 			if (high_table) {
 				if (!table->write(high_table)) {
@@ -123,15 +136,20 @@ int write_tables(void)
 		}
 
 		debug("- wrote '%s' to %x, end %x\n", table->name,
-		      rom_table_start, rom_table_end);
-		if (rom_table_end - rom_table_start > size) {
+		      rom_addr, rom_table_end);
+		if (rom_table_end - rom_addr > size) {
 			log_err("Out of space for configuration tables: need %x, have %x\n",
-				rom_table_end - rom_table_start, size);
+				rom_table_end - rom_addr, size);
 			return log_msg_ret("bloblist", -ENOSPC);
 		}
-		rom_table_start = rom_table_end;
+		rom_addr = rom_table_end;
 	}
 
+	if (use_high)
+		gd->arch.table_end_high = rom_addr;
+	else
+		gd->arch.table_end = rom_addr;
+
 	if (IS_ENABLED(CONFIG_SEABIOS)) {
 		/* make sure the last item is zero */
 		cfg_tables[i].size = 0;
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index e5ea5129c1..062e3d3e31 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -22,6 +22,7 @@
 #include <irq_func.h>
 #include <log.h>
 #include <malloc.h>
+#include <mapmem.h>
 #include <acpi/acpi_table.h>
 #include <asm/io.h>
 #include <asm/ptrace.h>
@@ -180,7 +181,7 @@ static int setup_device_tree(struct setup_header *hdr, const void *fdt_blob)
 	return 0;
 }
 
-static const char *get_kernel_version(struct boot_params *params,
+const char *zimage_get_kernel_version(struct boot_params *params,
 				      void *kernel_base)
 {
 	struct setup_header *hdr = &params->hdr;
@@ -188,10 +189,14 @@ static const char *get_kernel_version(struct boot_params *params,
 	const char *s, *end;
 
 	bootproto = get_boot_protocol(hdr, false);
+	log_debug("bootproto %x, hdr->setup_sects %x\n", bootproto,
+		  hdr->setup_sects);
 	if (bootproto < 0x0200 || hdr->setup_sects < 15)
 		return NULL;
 
 	/* sanity-check the kernel version in case it is missing */
+	log_debug("hdr->kernel_version %x, str at %p\n", hdr->kernel_version,
+		  kernel_base + hdr->kernel_version + 0x200);
 	for (s = kernel_base + hdr->kernel_version + 0x200, end = s + 0x100; *s;
 	     s++) {
 		if (!isprint(*s))
@@ -238,7 +243,7 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
 	log_debug("Using boot protocol version %x.%02x\n",
 		  (bootproto & 0xff00) >> 8, bootproto & 0xff);
 
-	version = get_kernel_version(params, image);
+	version = zimage_get_kernel_version(params, image);
 	if (version)
 		printf("Linux kernel version %s\n", version);
 	else
@@ -442,8 +447,7 @@ static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc,
 	return 0;
 }
 
-static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc,
-			 char *const argv[])
+static int zboot_load(void)
 {
 	struct boot_params *base_ptr;
 
@@ -460,31 +464,51 @@ static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc,
 				       &state.load_address);
 		if (!base_ptr) {
 			puts("## Kernel loading failed ...\n");
-			return CMD_RET_FAILURE;
+			return -EINVAL;
 		}
 	}
 	state.base_ptr = base_ptr;
-	if (env_set_hex("zbootbase", (ulong)base_ptr) ||
+
+	return 0;
+}
+
+static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	if (zboot_load())
+		return CMD_RET_FAILURE;
+
+	if (env_set_hex("zbootbase", map_to_sysmem(state.base_ptr)) ||
 	    env_set_hex("zbootaddr", state.load_address))
 		return CMD_RET_FAILURE;
 
 	return 0;
 }
 
+static int zboot_setup(void)
+{
+	struct boot_params *base_ptr = state.base_ptr;
+	int ret;
+
+	ret = setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET,
+			   0, state.initrd_addr, state.initrd_size,
+			   (ulong)state.cmdline);
+	if (ret)
+		return -EINVAL;
+
+	return 0;
+}
+
 static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc,
 			  char *const argv[])
 {
 	struct boot_params *base_ptr = state.base_ptr;
-	int ret;
 
 	if (!base_ptr) {
 		printf("base is not set: use 'zboot load' first\n");
 		return CMD_RET_FAILURE;
 	}
-	ret = setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET,
-			   0, state.initrd_addr, state.initrd_size,
-			   (ulong)state.cmdline);
-	if (ret) {
+	if (zboot_setup()) {
 		puts("Setting up boot parameters failed ...\n");
 		return CMD_RET_FAILURE;
 	}
@@ -501,8 +525,7 @@ static int do_zboot_info(struct cmd_tbl *cmdtp, int flag, int argc,
 	return 0;
 }
 
-static int do_zboot_go(struct cmd_tbl *cmdtp, int flag, int argc,
-		       char *const argv[])
+static int zboot_go(void)
 {
 	struct boot_params *params = state.base_ptr;
 	struct setup_header *hdr = &params->hdr;
@@ -522,11 +545,52 @@ static int do_zboot_go(struct cmd_tbl *cmdtp, int flag, int argc,
 
 	/* we assume that the kernel is in place */
 	ret = boot_linux_kernel((ulong)state.base_ptr, entry, image_64bit);
+
+	return ret;
+}
+
+static int do_zboot_go(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	int ret;
+
+	ret = zboot_go();
 	printf("Kernel returned! (err=%d)\n", ret);
 
 	return CMD_RET_FAILURE;
 }
 
+int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size,
+		ulong base, char *cmdline)
+{
+	int ret;
+
+	memset(&state, '\0', sizeof(state));
+
+	if (base) {
+		state.base_ptr = map_sysmem(base, 0);
+		state.load_address = addr;
+	} else {
+		state.bzimage_addr = addr;
+	}
+	state.bzimage_size = size;
+	state.initrd_addr = initrd;
+	state.initrd_size = initrd_size;
+	state.cmdline = cmdline;
+
+	ret = zboot_load();
+	if (ret)
+		return log_msg_ret("ld", ret);
+	ret = zboot_setup();
+	if (ret)
+		return log_msg_ret("set", ret);
+	ret = zboot_go();
+	if (ret)
+		return log_msg_ret("set", ret);
+
+	return -EFAULT;
+}
+
 static void print_num(const char *name, ulong value)
 {
 	printf("%-20s: %lx\n", name, value);
@@ -668,7 +732,8 @@ void zimage_dump(struct boot_params *base_ptr)
 	print_num("Real mode switch", hdr->realmode_swtch);
 	print_num("Start sys seg", hdr->start_sys_seg);
 	print_num("Kernel version", hdr->kernel_version);
-	version = get_kernel_version(base_ptr, (void *)state.bzimage_addr);
+	version = zimage_get_kernel_version(base_ptr,
+					    (void *)state.bzimage_addr);
 	if (version)
 		printf("   @%p: %s\n", version, version);
 	print_num("Type of loader", hdr->type_of_loader);
diff --git a/bin/travis-ci/conf.M5208EVBE_qemu b/bin/travis-ci/conf.M5208EVBE_qemu
deleted file mode 100644
index 947f13c790..0000000000
--- a/bin/travis-ci/conf.M5208EVBE_qemu
+++ /dev/null
@@ -1,27 +0,0 @@
-# Copyright (c) 2023 Marek Vasut <marek.vasut+renesas@mailbox.org>
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-# DEALINGS IN THE SOFTWARE.
-
-console_impl=qemu
-qemu_machine="mcf5208evb"
-qemu_binary="qemu-system-m68k"
-qemu_extra_args="-nographic -serial mon:stdio -net user,tftp=${UBOOT_TRAVIS_BUILD_DIR} -net nic,model=mcf-fec"
-qemu_kernel_args="-bios ${U_BOOT_BUILD_DIR}/u-boot.bin"
-reset_impl=none
-flash_impl=none
diff --git a/board/BuR/brppt1/MAINTAINERS b/board/BuR/brppt1/MAINTAINERS
index 6b45508f0f..a974a97c15 100644
--- a/board/BuR/brppt1/MAINTAINERS
+++ b/board/BuR/brppt1/MAINTAINERS
@@ -2,6 +2,7 @@ BRPPT1 BOARD
 M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
 S:	Maintained
 F:	board/BuR/brppt1/
+F:	board/BuR/common/
 F:	include/configs/brppt1.h
 F:	configs/brppt1_mmc_defconfig
 F:	configs/brppt1_nand_defconfig
diff --git a/board/BuR/brppt2/MAINTAINERS b/board/BuR/brppt2/MAINTAINERS
index fe65188f3d..bfeaa571a8 100644
--- a/board/BuR/brppt2/MAINTAINERS
+++ b/board/BuR/brppt2/MAINTAINERS
@@ -2,5 +2,6 @@ BUR_PPT2 BOARD
 M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
 S:	Maintained
 F:	board/BuR/brppt2/
+F:	board/BuR/common/
 F:	include/configs/brppt2.h
 F:	configs/brppt2_defconfig
diff --git a/board/BuR/brsmarc1/MAINTAINERS b/board/BuR/brsmarc1/MAINTAINERS
index 8d1fe216a4..7421f61fc4 100644
--- a/board/BuR/brsmarc1/MAINTAINERS
+++ b/board/BuR/brsmarc1/MAINTAINERS
@@ -2,5 +2,6 @@ BRSMARC1 BOARD
 M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
 S:	Maintained
 F:	board/BuR/brsmarc1/
+F:	board/BuR/common/
 F:	include/configs/brsmarc1.h
 F:	configs/brsmarc1_defconfig
diff --git a/board/BuR/brxre1/MAINTAINERS b/board/BuR/brxre1/MAINTAINERS
index 5aa36713d4..f826a44b6a 100644
--- a/board/BuR/brxre1/MAINTAINERS
+++ b/board/BuR/brxre1/MAINTAINERS
@@ -2,6 +2,7 @@ BRXRE1 BOARD
 M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
 S:	Maintained
 F:	board/BuR/brxre1/
+F:	board/BuR/common/
 F:	include/configs/brxre1.h
 F:	configs/brxre1_defconfig
 F:	arch/arm/dts/am335x-brxre1.dts
diff --git a/board/LaCie/net2big_v2/MAINTAINERS b/board/LaCie/net2big_v2/MAINTAINERS
index 7046e1b2c5..66e8219679 100644
--- a/board/LaCie/net2big_v2/MAINTAINERS
+++ b/board/LaCie/net2big_v2/MAINTAINERS
@@ -7,6 +7,7 @@ F:	arch/arm/dts/kirkwood-d2net.dtsi
 F:	arch/arm/dts/kirkwood-net2big.dts
 F:	arch/arm/dts/kirkwood-net2big-u-boot.dtsi
 F:	arch/arm/dts/kirkwood-netxbig.dtsi
+F:	board/LaCie/common/
 F:	board/LaCie/net2big_v2/
 F:	include/configs/lacie_kw.h
 F:	configs/d2net_v2_defconfig
diff --git a/board/LaCie/netspace_v2/MAINTAINERS b/board/LaCie/netspace_v2/MAINTAINERS
index 1cc4f7108b..03bc7874c1 100644
--- a/board/LaCie/netspace_v2/MAINTAINERS
+++ b/board/LaCie/netspace_v2/MAINTAINERS
@@ -12,6 +12,7 @@ F:	arch/arm/dts/kirkwood-ns2max-u-boot.dtsi
 F:	arch/arm/dts/kirkwood-ns2mini.dts
 F:	arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi
 F:	arch/arm/dts/kirkwood-ns2-u-boot.dtsi
+F:	board/LaCie/common/
 F:	board/LaCie/netspace_v2/
 F:	include/configs/lacie_kw.h
 F:	configs/inetspace_v2_defconfig
diff --git a/board/Marvell/db-88f6820-amc/MAINTAINERS b/board/Marvell/db-88f6820-amc/MAINTAINERS
index abf5b7efdc..d519eb47b8 100644
--- a/board/Marvell/db-88f6820-amc/MAINTAINERS
+++ b/board/Marvell/db-88f6820-amc/MAINTAINERS
@@ -4,3 +4,4 @@ S:	Maintained
 F:	board/Marvell/db-88f6820-amc/
 F:	include/configs/db-88f6820-amc.h
 F:	configs/db-88f6820-amc_defconfig
+F:	configs/db-88f6820-amc_nand_defconfig
diff --git a/board/Synology/ds109/MAINTAINERS b/board/Synology/ds109/MAINTAINERS
index 8783fdb1f2..2c50edc67d 100644
--- a/board/Synology/ds109/MAINTAINERS
+++ b/board/Synology/ds109/MAINTAINERS
@@ -2,5 +2,6 @@ DS109 BOARD
 M:	Walter Schweizer <swwa@users.sourceforge.net>
 S:	Maintained
 F:	board/Synology/ds109
+F:	board/Synology/common
 F:	configs/ds109_defconfig
 F:	include/configs/ds109.h
diff --git a/board/Synology/ds116/MAINTAINERS b/board/Synology/ds116/MAINTAINERS
index a5080b0d14..8d3cc24fbe 100644
--- a/board/Synology/ds116/MAINTAINERS
+++ b/board/Synology/ds116/MAINTAINERS
@@ -3,5 +3,6 @@ M:	Tony Dinh <mibodhi@gmail.com>
 S:	Maintained
 F:	arch/arm/dts/armada-385-synology-ds116.dts
 F:	board/Synology/ds116/
+F:	board/Synology/common
 F:	include/configs/ds116.h
 F:	configs/ds116_defconfig
diff --git a/board/Synology/ds414/MAINTAINERS b/board/Synology/ds414/MAINTAINERS
index 502cbd7758..22b7535734 100644
--- a/board/Synology/ds414/MAINTAINERS
+++ b/board/Synology/ds414/MAINTAINERS
@@ -2,5 +2,6 @@ DS414 BOARD
 M:	Phil Sutter <phil@nwl.cc>
 S:	Maintained
 F:	board/Synology/ds414/
+F:	board/Synology/common/
 F:	include/configs/ds414.h
 F:	configs/ds414_defconfig
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index 466174679e..b79a2380aa 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -54,10 +54,10 @@ struct efi_fw_image fw_images[] = {
 
 struct efi_capsule_update_info update_info = {
 	.dfu_string = "mmc 2=flash-bin raw 0 0x1B00 mmcpart 1",
+	.num_images = ARRAY_SIZE(fw_images),
 	.images = fw_images,
 };
 
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
 
 
diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c
index 7f2e972425..f36caece7d 100644
--- a/board/advantech/imx8qm_dmsse20_a1/spl.c
+++ b/board/advantech/imx8qm_dmsse20_a1/spl.c
@@ -111,7 +111,7 @@ int board_mmc_init(struct bd_info *bis)
 		switch (i) {
 		case 0:
 			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
-			if (ret != SC_ERR_NONE)
+			if (ret)
 				return ret;
 
 			imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
@@ -120,10 +120,10 @@ int board_mmc_init(struct bd_info *bis)
 			break;
 		case 1:
 			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
-			if (ret != SC_ERR_NONE)
+			if (ret)
 				return ret;
 			ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
-			if (ret != SC_ERR_NONE)
+			if (ret)
 				return ret;
 
 			imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c
index b602437c35..922bb0b7d4 100644
--- a/board/advantech/imx8qm_rom7720_a1/spl.c
+++ b/board/advantech/imx8qm_rom7720_a1/spl.c
@@ -112,7 +112,7 @@ int board_mmc_init(struct bd_info *bis)
 		switch (i) {
 		case 0:
 			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
-			if (ret != SC_ERR_NONE)
+			if (ret)
 				return ret;
 
 			imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
@@ -121,10 +121,10 @@ int board_mmc_init(struct bd_info *bis)
 			break;
 		case 1:
 			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
-			if (ret != SC_ERR_NONE)
+			if (ret)
 				return ret;
 			ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
-			if (ret != SC_ERR_NONE)
+			if (ret)
 				return ret;
 
 			imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
diff --git a/board/alliedtelesis/x240/MAINTAINERS b/board/alliedtelesis/x240/MAINTAINERS
new file mode 100644
index 0000000000..f1f78d9616
--- /dev/null
+++ b/board/alliedtelesis/x240/MAINTAINERS
@@ -0,0 +1,7 @@
+X240 BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/alliedtelesis/x240/
+F:	arch/arm/dts/ac5-98dx35xx-rd.dts
+F:	include/configs/x240.h
+F:	configs/x240_defconfig
diff --git a/board/alliedtelesis/x240/Makefile b/board/alliedtelesis/x240/Makefile
new file mode 100644
index 0000000000..7f20a47d6a
--- /dev/null
+++ b/board/alliedtelesis/x240/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 Allied Telesis
+#
+
+obj-y	+= x240.o
diff --git a/board/alliedtelesis/x240/x240.c b/board/alliedtelesis/x240/x240.c
new file mode 100644
index 0000000000..0c4f8e03b8
--- /dev/null
+++ b/board/alliedtelesis/x240/x240.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
diff --git a/board/amlogic/ad401/MAINTAINERS b/board/amlogic/ad401/MAINTAINERS
new file mode 100644
index 0000000000..52a44bd66c
--- /dev/null
+++ b/board/amlogic/ad401/MAINTAINERS
@@ -0,0 +1,6 @@
+AD401
+M:	Neil Armstrong <neil.armstrong@linaro.org>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/ad401/
+F:	configs/ad401_defconfig
diff --git a/board/amlogic/ad401/Makefile b/board/amlogic/ad401/Makefile
new file mode 100644
index 0000000000..e65c1215f6
--- /dev/null
+++ b/board/amlogic/ad401/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2023 SberDevices, Inc.
+
+obj-y	:= ad401.o
diff --git a/board/amlogic/ad401/ad401.c b/board/amlogic/ad401/ad401.c
new file mode 100644
index 0000000000..356b2880bd
--- /dev/null
+++ b/board/amlogic/ad401/ad401.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 SberDevices, Inc.
+ * Author: Igor Prusov <ivprusov@sberdevices.ru>
+ */
+
+#include <init.h>
+#include <asm/arch/eth.h>
+
+int misc_init_r(void)
+{
+	meson_generate_serial_ethaddr();
+
+	return 0;
+}
diff --git a/board/amlogic/p200/MAINTAINERS b/board/amlogic/p200/MAINTAINERS
index fe451dd7db..5cf0ce05dc 100644
--- a/board/amlogic/p200/MAINTAINERS
+++ b/board/amlogic/p200/MAINTAINERS
@@ -9,8 +9,10 @@ F:	configs/odroid-c2_defconfig
 F:	configs/p200_defconfig
 F:	configs/wetek-hub_defconfig
 F:	configs/wetek-play2_defconfig
+F:	configs/videostrong-kii-pro_defconfig
 F:	doc/board/amlogic/p200.rst
 F:	doc/board/amlogic/nanopi-k2.rst
 F:	doc/board/amlogic/odroid-c2.rst
+F:      doc/board/amlogic/videostrong-kii-pro.rst
 F:      doc/board/amlogic/wetek-hub.rst
 F:      doc/board/amlogic/wetek-play2.rst
diff --git a/board/amlogic/u200/MAINTAINERS b/board/amlogic/u200/MAINTAINERS
index f429c212ba..88c5038d94 100644
--- a/board/amlogic/u200/MAINTAINERS
+++ b/board/amlogic/u200/MAINTAINERS
@@ -4,7 +4,7 @@ S:	Maintained
 L:	u-boot-amlogic@groups.io
 F:	board/amlogic/u200/
 F:	configs/u200_defconfig
-F:	configs/bananapi-m2pro_defconfig
+F:	configs/bananapi-m2-pro_defconfig
 F:	configs/bananapi-m5_defconfig
 F:	configs/radxa-zero_defconfig
 F:	doc/board/amlogic/u200.rst
diff --git a/board/amlogic/w400/MAINTAINERS b/board/amlogic/w400/MAINTAINERS
index 117f79ea04..19b1f30e62 100644
--- a/board/amlogic/w400/MAINTAINERS
+++ b/board/amlogic/w400/MAINTAINERS
@@ -5,6 +5,7 @@ L:	u-boot-amlogic@groups.io
 F:	board/amlogic/w400/
 F:	configs/bananapi-cm4-cm4io_defconfig
 F:	configs/bananapi-m2s_defconfig
+F:	configs/odroid-n2l_defconfig
 F:	configs/radxa-zero2_defconfig
 F:	doc/board/amlogic/w400.rst
 F:	doc/board/amlogic/bananapi-cm4io.rst
diff --git a/board/anbernic/rgxx3_rk3566/MAINTAINERS b/board/anbernic/rgxx3_rk3566/MAINTAINERS
index 647e49d28a..6be16a47e8 100644
--- a/board/anbernic/rgxx3_rk3566/MAINTAINERS
+++ b/board/anbernic/rgxx3_rk3566/MAINTAINERS
@@ -1,6 +1,9 @@
 RGXX3-RK3566
 M:	Chris Morgan <macromorgan@hotmail.com>
 S:	Maintained
-F:	board/anbernic/rgxx3-rk3566
-F:	include/configs/anbernic-rgxx3-rk3566
+F:	board/anbernic/rgxx3_rk3566
+F:	include/configs/anbernic-rgxx3-rk3566.h
 F:	configs/anbernic-rgxx3_defconfig
+F:	arch/arm/dts/rk3566-anbernic-rgxx3.dts
+F:	arch/arm/dts/rk3566-anbernic-rgxx3.dtsi
+F:	arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
index decc46db78..3f1a42d184 100644
--- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
+++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
@@ -6,25 +6,37 @@
 #include <abuf.h>
 #include <adc.h>
 #include <asm/io.h>
+#include <display.h>
 #include <dm.h>
+#include <dm/lists.h>
+#include <env.h>
+#include <fdt_support.h>
 #include <linux/delay.h>
+#include <mipi_dsi.h>
+#include <mmc.h>
+#include <panel.h>
 #include <pwm.h>
 #include <rng.h>
 #include <stdlib.h>
-#include <mmc.h>
-#include <env.h>
+#include <video_bridge.h>
 
 #define GPIO0_BASE		0xfdd60000
+#define GPIO4_BASE		0xfe770000
+#define GPIO_SWPORT_DR_L	0x0000
 #define GPIO_SWPORT_DR_H	0x0004
+#define GPIO_SWPORT_DDR_L	0x0008
 #define GPIO_SWPORT_DDR_H	0x000c
-#define GPIO_A5			BIT(5)
-#define GPIO_A6			BIT(6)
+#define GPIO_A0			BIT(0)
+#define GPIO_C5			BIT(5)
+#define GPIO_C6			BIT(6)
+#define GPIO_C7			BIT(7)
 
 #define GPIO_WRITEMASK(bits)	((bits) << 16)
 
 #define DTB_DIR			"rockchip/"
 
 struct rg3xx_model {
+	const u16 adc_value;
 	const char *board;
 	const char *board_name;
 	const char *fdtfile;
@@ -34,49 +46,74 @@ enum rgxx3_device_id {
 	RG353M,
 	RG353P,
 	RG353V,
-	RG353VS,
 	RG503,
+	/* Devices with duplicate ADC value */
+	RG353PS,
+	RG353VS,
 };
 
 static const struct rg3xx_model rg3xx_model_details[] = {
 	[RG353M] = {
+		517, /* Observed average from device */
 		"rk3566-anbernic-rg353m",
 		"RG353M",
-		DTB_DIR "rk3566-anbernic-rg353m.dtb",
+		DTB_DIR "rk3566-anbernic-rg353p.dtb", /* Identical devices */
 	},
 	[RG353P] = {
+		860, /* Documented value of 860 */
 		"rk3566-anbernic-rg353p",
 		"RG353P",
 		DTB_DIR "rk3566-anbernic-rg353p.dtb",
 	},
 	[RG353V] = {
+		695, /* Observed average from device */
 		"rk3566-anbernic-rg353v",
 		"RG353V",
 		DTB_DIR "rk3566-anbernic-rg353v.dtb",
 	},
-	[RG353VS] = {
-		"rk3566-anbernic-rg353vs",
-		"RG353VS",
-		DTB_DIR "rk3566-anbernic-rg353vs.dtb",
-	},
 	[RG503] = {
+		1023, /* Observed average from device */
 		"rk3566-anbernic-rg503",
 		"RG503",
 		DTB_DIR "rk3566-anbernic-rg503.dtb",
 	},
+	/* Devices with duplicate ADC value */
+	[RG353PS] = {
+		860, /* Observed average from device */
+		"rk3566-anbernic-rg353ps",
+		"RG353PS",
+		DTB_DIR "rk3566-anbernic-rg353ps.dtb",
+	},
+	[RG353VS] = {
+		695, /* Gathered from second hand information */
+		"rk3566-anbernic-rg353vs",
+		"RG353VS",
+		DTB_DIR "rk3566-anbernic-rg353vs.dtb",
+	},
+};
+
+struct rg353_panel {
+	const u16 id;
+	const char *panel_compat;
+};
+
+static const struct rg353_panel rg353_panel_details[] = {
+	{ .id = 0x3052, .panel_compat = "newvision,nv3051d"},
+	{ .id = 0x3821, .panel_compat = "anbernic,rg353v-panel-v2"},
 };
 
 /*
  * Start LED very early so user knows device is on. Set color
- * to amber.
+ * to red.
  */
 void spl_board_init(void)
 {
-	/* Set GPIO0_A5 and GPIO0_A6 to output. */
-	writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | (GPIO_A6 | GPIO_A5),
+	/* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
+	writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
+	       (GPIO_C7 | GPIO_C6 | GPIO_C5),
 	       (GPIO0_BASE + GPIO_SWPORT_DDR_H));
-	/* Set GPIO0_A5 to 0 and GPIO0_A6 to 1. */
-	writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A6,
+	/* Set GPIO0_C5 and GPIO_C6 to 0 and GPIO0_C7 to 1. */
+	writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | GPIO_C7,
 	       (GPIO0_BASE + GPIO_SWPORT_DR_H));
 }
 
@@ -126,15 +163,159 @@ void __maybe_unused startup_buzz(void)
 	pwm_set_enable(dev, 0, 0);
 }
 
+/*
+ * Provide the bare minimum to identify the panel for the RG353
+ * series. Since we don't have a working framebuffer device, no
+ * need to init the panel; just identify it and provide the
+ * clocks so we know what to set the different clock values to.
+ */
+
+static const struct display_timing rg353_default_timing = {
+	.pixelclock.typ		= 24150000,
+	.hactive.typ		= 640,
+	.hfront_porch.typ	= 40,
+	.hback_porch.typ	= 80,
+	.hsync_len.typ		= 2,
+	.vactive.typ		= 480,
+	.vfront_porch.typ	= 18,
+	.vback_porch.typ	= 28,
+	.vsync_len.typ		= 2,
+	.flags			= DISPLAY_FLAGS_HSYNC_HIGH |
+				  DISPLAY_FLAGS_VSYNC_HIGH,
+};
+
+static int anbernic_rg353_panel_get_timing(struct udevice *dev,
+					   struct display_timing *timings)
+{
+	memcpy(timings, &rg353_default_timing, sizeof(*timings));
+
+	return 0;
+}
+
+static int anbernic_rg353_panel_probe(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+
+	plat->lanes = 4;
+	plat->format = MIPI_DSI_FMT_RGB888;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO |
+			   MIPI_DSI_MODE_VIDEO_BURST |
+			   MIPI_DSI_MODE_EOT_PACKET |
+			   MIPI_DSI_MODE_LPM;
+
+	return 0;
+}
+
+static const struct panel_ops anbernic_rg353_panel_ops = {
+	.get_display_timing = anbernic_rg353_panel_get_timing,
+};
+
+U_BOOT_DRIVER(anbernic_rg353_panel) = {
+	.name		= "anbernic_rg353_panel",
+	.id		= UCLASS_PANEL,
+	.ops		= &anbernic_rg353_panel_ops,
+	.probe		= anbernic_rg353_panel_probe,
+	.plat_auto	= sizeof(struct mipi_dsi_panel_plat),
+};
+
+int rgxx3_detect_display(void)
+{
+	struct udevice *dev;
+	struct mipi_dsi_device *dsi;
+	struct mipi_dsi_panel_plat *mplat;
+	const struct rg353_panel *panel;
+	int ret = 0;
+	int i;
+	u8 panel_id[2];
+
+	/*
+	 * Take panel out of reset status.
+	 * Set GPIO4_A0 to output.
+	 */
+	writel(GPIO_WRITEMASK(GPIO_A0) | GPIO_A0,
+	       (GPIO4_BASE + GPIO_SWPORT_DDR_L));
+	/* Set GPIO4_A0 to 1. */
+	writel(GPIO_WRITEMASK(GPIO_A0) | GPIO_A0,
+	       (GPIO4_BASE + GPIO_SWPORT_DR_L));
+
+	/* Probe the DSI controller. */
+	ret = uclass_get_device_by_name(UCLASS_VIDEO_BRIDGE,
+					"dsi@fe060000", &dev);
+	if (ret) {
+		printf("DSI host not probed: %d\n", ret);
+		return ret;
+	}
+
+	/* Probe the DSI panel. */
+	ret = device_bind_driver_to_node(dev, "anbernic_rg353_panel",
+					 "anbernic_rg353_panel",
+					 dev_ofnode(dev), NULL);
+	if (ret) {
+		printf("Failed to probe RG353 panel: %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * Attach the DSI controller which will also probe and attach
+	 * the DSIDPHY.
+	 */
+	ret = video_bridge_attach(dev);
+	if (ret) {
+		printf("Failed to attach DSI controller: %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * Get the panel which should have already been probed by the
+	 * video_bridge_attach() function.
+	 */
+	ret = uclass_first_device_err(UCLASS_PANEL, &dev);
+	if (ret) {
+		printf("Panel device error: %d\n", ret);
+		return ret;
+	}
+
+	/* Now call the panel via DSI commands to get the panel ID. */
+	mplat = dev_get_plat(dev);
+	dsi = mplat->device;
+	mipi_dsi_set_maximum_return_packet_size(dsi, sizeof(panel_id));
+	ret = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_ID, &panel_id,
+				sizeof(panel_id));
+	if (ret < 0) {
+		printf("Unable to read panel ID: %d\n", ret);
+		return ret;
+	}
+
+	/* Get the correct panel compatible from the table. */
+	for (i = 0; i < ARRAY_SIZE(rg353_panel_details); i++) {
+		if (rg353_panel_details[i].id == ((panel_id[0] << 8) |
+						 panel_id[1])) {
+			panel = &rg353_panel_details[i];
+			break;
+		}
+	}
+
+	if (!panel) {
+		printf("Unable to identify panel_id %x\n",
+		       (panel_id[0] << 8) | panel_id[1]);
+		env_set("panel", "unknown");
+		return -EINVAL;
+	}
+
+	env_set("panel", panel->panel_compat);
+
+	return 0;
+}
+
 /* Detect which Anbernic RGXX3 device we are using so as to load the
  * correct devicetree for Linux. Set an environment variable once
  * found. The detection depends on the value of ADC channel 1, the
- * presence of an eMMC on mmc0, and querying the DSI panel (TODO).
+ * presence of an eMMC on mmc0, and querying the DSI panel.
  */
 int rgxx3_detect_device(void)
 {
 	u32 adc_info;
-	int ret;
+	int ret, i;
 	int board_id = -ENXIO;
 	struct mmc *mmc;
 
@@ -144,30 +325,37 @@ int rgxx3_detect_device(void)
 		return ret;
 	}
 
-	/* Observed value 517. */
-	if (adc_info > 505 && adc_info < 530)
-		board_id = RG353M;
-	/* Observed value 695. */
-	if (adc_info > 680 && adc_info < 710)
-		board_id = RG353V;
-	/* Documented value 860. */
-	if (adc_info > 850 && adc_info < 870)
-		board_id = RG353P;
-	/* Observed value 1023. */
-	if (adc_info > 1010)
-		board_id = RG503;
+	/*
+	 * Get the correct device from the table. The ADC value is
+	 * determined by a resistor on ADC channel 0. The hardware
+	 * design calls for no more than a 1% variance on the
+	 * resistor, so assume a +- value of 15 should be enough.
+	 */
+	for (i = 0; i < ARRAY_SIZE(rg3xx_model_details); i++) {
+		u32 adc_min = rg3xx_model_details[i].adc_value - 15;
+		u32 adc_max = rg3xx_model_details[i].adc_value + 15;
+
+		if (adc_min < adc_info && adc_max > adc_info) {
+			board_id = i;
+			break;
+		}
+	}
 
 	/*
-	 * Try to access the eMMC on an RG353V. If it's missing, it's
-	 * an RG353VS. Note we could also check for a touchscreen at
-	 * 0x1a on i2c2.
+	 * Try to access the eMMC on an RG353V or RG353P. If it's
+	 * missing, it's an RG353VS or RG353PS. Note we could also
+	 * check for a touchscreen at 0x1a on i2c2.
 	 */
-	if (board_id == RG353V) {
+	if (board_id == RG353V || board_id == RG353P) {
 		mmc = find_mmc_device(0);
 		if (mmc) {
 			ret = mmc_init(mmc);
-			if (ret)
-				board_id = RG353VS;
+			if (ret) {
+				if (board_id == RG353V)
+					board_id = RG353VS;
+				else
+					board_id = RG353PS;
+			}
 		}
 	}
 
@@ -179,6 +367,14 @@ int rgxx3_detect_device(void)
 		rg3xx_model_details[board_id].board_name);
 	env_set("fdtfile", rg3xx_model_details[board_id].fdtfile);
 
+	/* Detect the panel type for any device that isn't a 503. */
+	if (board_id == RG503)
+		return 0;
+
+	ret = rgxx3_detect_display();
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
@@ -186,18 +382,64 @@ int rk_board_late_init(void)
 {
 	int ret;
 
-	/* Turn off orange LED and turn on green LED. */
-	writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A5,
-	       (GPIO0_BASE + GPIO_SWPORT_DR_H));
-
 	ret = rgxx3_detect_device();
 	if (ret) {
 		printf("Unable to detect device type: %d\n", ret);
 		return ret;
 	}
 
+	/* Turn off red LED and turn on orange LED. */
+	writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | GPIO_C6,
+	       (GPIO0_BASE + GPIO_SWPORT_DR_H));
+
 	if (IS_ENABLED(CONFIG_DM_PWM))
 		startup_buzz();
 
 	return 0;
 }
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int node, ret;
+	char *env;
+
+	/* No fixups necessary for the RG503 */
+	env = env_get("board_name");
+	if (env && (!strcmp(env, rg3xx_model_details[RG503].board_name)))
+		return 0;
+
+	/* Change the model name of the RG353M */
+	if (env && (!strcmp(env, rg3xx_model_details[RG353M].board_name)))
+		fdt_setprop(blob, 0, "model",
+			    rg3xx_model_details[RG353M].board_name,
+			    sizeof(rg3xx_model_details[RG353M].board_name));
+
+	/*
+	 * Check if the environment variable doesn't equal the panel.
+	 * If it doesn't, update the devicetree to the correct panel.
+	 */
+	node = fdt_path_offset(blob, "/dsi@fe060000/panel@0");
+	if (!(node > 0)) {
+		printf("Can't find the DSI node\n");
+		return -ENODEV;
+	}
+
+	env = env_get("panel");
+	if (!env) {
+		printf("Can't get panel env\n");
+		return -ENODEV;
+	}
+
+	ret = fdt_node_check_compatible(blob, node, env);
+	if (ret < 0)
+		return -ENODEV;
+
+	/* Panels match, return 0. */
+	if (!ret)
+		return 0;
+
+	do_fixup_by_path_string(blob, "/dsi@fe060000/panel@0",
+				"compatible", env);
+
+	return 0;
+}
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 770f3d7d0d..4dcf3f396b 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -30,7 +30,6 @@
 #include <bmp_logo.h>
 #include <dm/root.h>
 #include <env.h>
-#include <env_internal.h>
 #include <i2c_eeprom.h>
 #include <i2c.h>
 #include <micrel.h>
@@ -529,22 +528,3 @@ int embedded_dtb_select(void)
 	return 0;
 }
 #endif
-
-enum env_location env_get_location(enum env_operation op, int prio)
-{
-	if (op == ENVOP_SAVE || op == ENVOP_ERASE)
-		return ENVL_SPI_FLASH;
-
-	switch (prio) {
-	case 0:
-		return ENVL_NOWHERE;
-
-	case 1:
-		return ENVL_SPI_FLASH;
-
-	default:
-		return ENVL_UNKNOWN;
-	}
-
-	return ENVL_UNKNOWN;
-}
diff --git a/board/armadeus/opos6uldev/opos6uldev.env b/board/armadeus/opos6uldev/opos6uldev.env
index 585f28ca85..f900297871 100644
--- a/board/armadeus/opos6uldev/opos6uldev.env
+++ b/board/armadeus/opos6uldev/opos6uldev.env
@@ -42,8 +42,8 @@ flash_uboot_spl=
 		setexpr sz ${filesize} / 0x200;
 		setexpr sz ${sz} + 1;
 		if mmc write ${loadaddr} 0x2 ${sz}; then
-			echo Flashing of U-boot SPL succeed;
-		else echo Flashing of U-boot SPL failed;
+			echo Flashing of U-Boot SPL succeed;
+		else echo Flashing of U-Boot SPL failed;
 		fi;
 	fi;
 download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img
@@ -52,8 +52,8 @@ flash_uboot_img=
 		setexpr sz ${filesize} / 0x200;
 		setexpr sz ${sz} + 1;
 		if mmc write ${loadaddr} 0x8a ${sz}; then
-			echo Flashing of U-boot image succeed;
-		else echo Flashing of U-boot image failed;
+			echo Flashing of U-Boot image succeed;
+		else echo Flashing of U-Boot image failed;
 		fi;
 	fi;
 update_uboot=run download_uboot_spl flash_uboot_spl
diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS
index 8c905686de..1cc9aaa29a 100644
--- a/board/armltd/corstone1000/MAINTAINERS
+++ b/board/armltd/corstone1000/MAINTAINERS
@@ -1,6 +1,6 @@
 CORSTONE1000 BOARD
-M:	Rui Miguel Silva <rui.silva@linaro.org>
-M:	Vishnu Banavath <vishnu.banavath@arm.com>
+M:	Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+M:	Xueliang Zhong <xueliang.zhong@arm.com>
 S:	Maintained
 F:	board/armltd/corstone1000/
 F:	include/configs/corstone1000.h
diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c
index 6ec8e6144f..01c80aaf9d 100644
--- a/board/armltd/corstone1000/corstone1000.c
+++ b/board/armltd/corstone1000/corstone1000.c
@@ -5,14 +5,25 @@
  * Rui Miguel Silva <rui.silva@linaro.org>
  */
 
+#include <blk.h>
 #include <common.h>
 #include <cpu_func.h>
 #include <dm.h>
+#include <env.h>
+#include <fwu.h>
 #include <netdev.h>
+#include <nvmxip.h>
+#include <part.h>
 #include <dm/platform_data/serial_pl01x.h>
 #include <asm/armv8/mmu.h>
 #include <asm/global_data.h>
 
+#define CORSTONE1000_KERNEL_PARTS 2
+#define CORSTONE1000_KERNEL_PRIMARY "kernel_primary"
+#define CORSTONE1000_KERNEL_SECONDARY "kernel_secondary"
+
+static int corstone1000_boot_idx;
+
 static struct mm_region corstone1000_mem_map[] = {
 	{
 		/* CVM */
@@ -87,6 +98,66 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-void reset_cpu(void)
+void fwu_plat_get_bootidx(uint *boot_idx)
 {
+	int ret;
+
+	/*
+	 * in our platform, the Secure Enclave is the one who controls
+	 * all the boot tries and status, so, every time we get here
+	 * we know that the we are booting from the active index
+	 */
+	ret = fwu_get_active_index(boot_idx);
+	if (ret < 0) {
+		*boot_idx = CONFIG_FWU_NUM_BANKS;
+		log_err("corstone1000: failed to read active index\n");
+	}
+}
+
+int board_late_init(void)
+{
+	struct disk_partition part_info;
+	struct udevice *dev, *bdev;
+	struct nvmxip_plat *plat;
+	struct blk_desc *desc;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_NVMXIP, &dev);
+	if (ret < 0) {
+		log_err("Cannot find kernel device\n");
+		return ret;
+	}
+
+	plat = dev_get_plat(dev);
+	device_find_first_child(dev, &bdev);
+	desc = dev_get_uclass_plat(bdev);
+	ret = fwu_get_active_index(&corstone1000_boot_idx);
+	if (ret < 0) {
+		log_err("corstone1000: failed to read boot index\n");
+		return ret;
+	}
+
+	if (!corstone1000_boot_idx)
+		ret = part_get_info_by_name(desc, CORSTONE1000_KERNEL_PRIMARY,
+					    &part_info);
+	else
+		ret = part_get_info_by_name(desc, CORSTONE1000_KERNEL_SECONDARY,
+					    &part_info);
+
+	if (ret < 0) {
+		log_err("failed to fetch kernel partition index: %d\n",
+			corstone1000_boot_idx);
+		return ret;
+	}
+
+	ret = 0;
+
+	ret |= env_set_hex("kernel_addr", plat->phys_base +
+			   (part_info.start * part_info.blksz));
+	ret |= env_set_hex("kernel_size", part_info.size * part_info.blksz);
+
+	if (ret < 0)
+		log_err("failed to setup kernel addr and size\n");
+
+	return ret;
 }
diff --git a/board/armltd/corstone1000/corstone1000.env b/board/armltd/corstone1000/corstone1000.env
index b24ff07fc6..ee318b1b1c 100644
--- a/board/armltd/corstone1000/corstone1000.env
+++ b/board/armltd/corstone1000/corstone1000.env
@@ -1,13 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 
 usb_pgood_delay=250
-boot_bank_flag=0x08002000
-kernel_addr_bank_0=0x083EE000
-kernel_addr_bank_1=0x0936E000
-retrieve_kernel_load_addr=
-	if itest.l *${boot_bank_flag} == 0; then
-		setenv kernel_addr $kernel_addr_bank_0;
-	else
-		setenv kernel_addr $kernel_addr_bank_1;
-	fi;
+boot_bank_flag=0x08005006
 kernel_addr_r=0x88200000
diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS
index b3ecc9bba0..c38ab520c5 100644
--- a/board/armltd/vexpress64/MAINTAINERS
+++ b/board/armltd/vexpress64/MAINTAINERS
@@ -1,9 +1,10 @@
-VEXPRESS64 BOARD
+VEXPRESS64 PLATFORM
 M:	David Feng <fenghua@phytium.com.cn>
+M:	Linus Walleij <linus.walleij@linaro.org>
+M:	Peter Hoyes <Peter.Hoyes@arm.com>
 S:	Maintained
 F:	board/armltd/vexpress64/
-F:	include/configs/vexpress_aemv8a.h
-F:	configs/vexpress_aemv8a_defconfig
+F:	include/configs/vexpress_aemv8.h
 
 VEXPRESS_AEMV8A_SEMI BOARD
 M:	Linus Walleij <linus.walleij@linaro.org>
diff --git a/board/avionic-design/medcom-wide/MAINTAINERS b/board/avionic-design/medcom-wide/MAINTAINERS
index 0a00fcf719..3d2cdeca72 100644
--- a/board/avionic-design/medcom-wide/MAINTAINERS
+++ b/board/avionic-design/medcom-wide/MAINTAINERS
@@ -2,5 +2,6 @@ MEDCOM-WIDE BOARD
 M:	Alban Bedel <alban.bedel@avionic-design.de>
 S:	Maintained
 F:	board/avionic-design/medcom-wide/
+F:	board/avionic-design/common/
 F:	include/configs/medcom-wide.h
 F:	configs/medcom-wide_defconfig
diff --git a/board/avionic-design/plutux/MAINTAINERS b/board/avionic-design/plutux/MAINTAINERS
index e8ef5096e5..0275680d21 100644
--- a/board/avionic-design/plutux/MAINTAINERS
+++ b/board/avionic-design/plutux/MAINTAINERS
@@ -2,5 +2,6 @@ PLUTUX BOARD
 M:	Alban Bedel <alban.bedel@avionic-design.de>
 S:	Maintained
 F:	board/avionic-design/plutux/
+F:	board/avionic-design/common/
 F:	include/configs/plutux.h
 F:	configs/plutux_defconfig
diff --git a/board/avionic-design/tec-ng/MAINTAINERS b/board/avionic-design/tec-ng/MAINTAINERS
index 5cbdf8e7eb..645be8186a 100644
--- a/board/avionic-design/tec-ng/MAINTAINERS
+++ b/board/avionic-design/tec-ng/MAINTAINERS
@@ -2,5 +2,6 @@ TEC-NG BOARD
 M:	Alban Bedel <alban.bedel@avionic-design.de>
 S:	Maintained
 F:	board/avionic-design/tec-ng/
+F:	board/avionic-design/common/
 F:	include/configs/tec-ng.h
 F:	configs/tec-ng_defconfig
diff --git a/board/avionic-design/tec/MAINTAINERS b/board/avionic-design/tec/MAINTAINERS
index 10f1aac7a6..36088e7dac 100644
--- a/board/avionic-design/tec/MAINTAINERS
+++ b/board/avionic-design/tec/MAINTAINERS
@@ -2,5 +2,6 @@ TEC BOARD
 M:	Alban Bedel <alban.bedel@avionic-design.de>
 S:	Maintained
 F:	board/avionic-design/tec/
+F:	board/avionic-design/common/
 F:	include/configs/tec.h
 F:	configs/tec_defconfig
diff --git a/board/beacon/imx8mm/MAINTAINERS b/board/beacon/imx8mm/MAINTAINERS
index e887db20a2..d8a5d09736 100644
--- a/board/beacon/imx8mm/MAINTAINERS
+++ b/board/beacon/imx8mm/MAINTAINERS
@@ -5,3 +5,5 @@ S:	Maintained
 F:	board/beacon/imx8mm/
 F:	include/configs/imx8mm_beacon.h
 F:	configs/imx8mm_beacon_defconfig
+F:	configs/imx8mm_beacon_fspi_defconfig
+F:	doc/board/beacon/
diff --git a/board/beacon/imx8mm/README b/board/beacon/imx8mm/README
deleted file mode 100644
index 32b24bc03e..0000000000
--- a/board/beacon/imx8mm/README
+++ /dev/null
@@ -1,37 +0,0 @@
-U-Boot for the Beacon EmbeddedWorks Devkit
-
-Quick Start
-===========
-- Build the ARM Trusted firmware binary
-- Get ddr firmware
-- Build U-Boot
-- Boot
-
-Get and Build the ARM Trusted firmware
-======================================
-Note: $(srctree) is U-Boot source directory
-
-$ git clone https://github.com/nxp-imx/imx-atf
-$ git lf-5.10.72-2.2.0
-$ make PLAT=imx8mm bl31 CROSS_COMPILE=aarch64-linux-gnu-
-$ cp build/imx8mm/release/bl31.bin $(srctree)
-
-Get the DDR firmware
-====================
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
-$ chmod +x firmware-imx-8.9.bin
-$ ./firmware-imx-8.9
-$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
-
-Build U-Boot
-============
-$ make imx8mm_beacon_defconfig
-$ make CROSS_COMPILE=aarch64-linux-gnu-
-
-Burn U-Boot to microSD Card
-===========================
-$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
-
-Boot
-====
-Set Boot switch to SD boot
diff --git a/board/beacon/imx8mm/imx8mm_beacon.env b/board/beacon/imx8mm/imx8mm_beacon.env
new file mode 100644
index 0000000000..00bf67edd5
--- /dev/null
+++ b/board/beacon/imx8mm/imx8mm_beacon.env
@@ -0,0 +1,19 @@
+boot_fit=try
+bootscript=echo Running bootscript from mmc ...; source
+console=ttymxc1
+fdt_addr=0x45000000
+fdt_file=imx8mm-beacon-kit.dtb
+finduuid=part uuid mmc ${mmcdev}:2 uuid
+image=Image
+initrd_addr=0x46000000
+loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+mmcargs=setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}
+mmcautodetect=yes
+mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if run loadfdt; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi;
+netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+mmcdev=1
+mmcpart=1
+netboot=echo Booting from net ...; run netargs;  if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if ${get_cmd} ${fdt_addr} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; fi;
+script=boot.scr
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index a5f337aa17..b2830c5223 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -36,6 +36,8 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
 		return BOOT_DEVICE_MMC2;
 	case USB_BOOT:
 		return BOOT_DEVICE_BOARD;
+	case QSPI_BOOT:
+		return BOOT_DEVICE_NOR;
 	default:
 		return BOOT_DEVICE_NONE;
 	}
@@ -46,6 +48,11 @@ static void spl_dram_init(void)
 	ddr_init(&dram_timing);
 }
 
+void spl_board_init(void)
+{
+	arch_misc_init();
+}
+
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
diff --git a/board/beacon/imx8mn/MAINTAINERS b/board/beacon/imx8mn/MAINTAINERS
index 4805cb255c..6dcef21a65 100644
--- a/board/beacon/imx8mn/MAINTAINERS
+++ b/board/beacon/imx8mn/MAINTAINERS
@@ -5,3 +5,4 @@ F:	board/beacon/imx8mn/
 F:	include/configs/imx8mn_beacon.h
 F:	configs/imx8mn_beacon_defconfig
 F:	configs/imx8mn_beacon_2g_defconfig
+F:	configs/imx8mn_beacon_fspi_defconfig
diff --git a/board/beacon/imx8mn/README b/board/beacon/imx8mn/README
deleted file mode 100644
index 49da03c8d8..0000000000
--- a/board/beacon/imx8mn/README
+++ /dev/null
@@ -1,38 +0,0 @@
-U-Boot for the Beacon EmbeddedWorks i.MX8M Nano Devkit
-
-Quick Start
-===========
-- Build the ARM Trusted firmware binary
-- Get ddr firmware
-- Build U-Boot
-- Boot
-
-Get and Build the ARM Trusted firmware
-======================================
-Note: $(srctree) is U-Boot source directory
-
-$ git clone https://github.com/nxp-imx/imx-atf
-$ git lf-5.10.72-2.2.0
-$ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu-
-$ cp build/imx8mn/release/bl31.bin $(srctree)
-
-Get the DDR firmware
-====================
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
-$ chmod +x firmware-imx-8.9.bin
-$ ./firmware-imx-8.9
-$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
-
-Build U-Boot
-============
-$ make imx8mn_beacon_defconfig
-$ make CROSS_COMPILE=aarch64-linux-gnu-
-
-Burn U-Boot to microSD Card
-===========================
-$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
-
-Boot
-====
-Set baseboard DIP switch:
-S17: 1100XXXX
diff --git a/board/beacon/imx8mn/imx8mn_beacon.env b/board/beacon/imx8mn/imx8mn_beacon.env
new file mode 100644
index 0000000000..ca90053d47
--- /dev/null
+++ b/board/beacon/imx8mn/imx8mn_beacon.env
@@ -0,0 +1,25 @@
+boot_fdt=try
+bootdelay=2
+bootscript=echo Running bootscript from mmc ...; source
+console=ttymxc1
+fdt_addr=0x45000000
+fdt_file=imx8mn-beacon-kit.dtb
+finduuid=part uuid mmc ${mmcdev}:2 uuid
+image=Image
+initrd_addr=0x46000000
+loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadramdisk=load mmc ${mmcdev} ${ramdisk_addr} ${ramdiskimage}
+mmcargs=setenv bootargs console=${console},${baudrate}  root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}
+mmcautodetect=yes
+mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if run loadfdt; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; else echo wait for boot; fi;
+mmcdev=1
+mmcpart=1
+netargs=setenv bootargs console=${console},${baudrate}  root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=echo Booting from net ...; run netargs;  if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if ${get_cmd} ${fdt_addr} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; else booti; fi;
+ramargs=setenv bootargs console=${console},${baudrate}  root=/dev/ram rw  ${optargs}
+ramboot=echo Booting from RAMdisk...; run loadimage; run loadfdt; fdt addr $fdt_addr; run loadramdisk; run ramargs; booti ${loadaddr} ${ramdisk_addr} ${fdt_addr} ${optargs}
+ramdisk_addr=0x46000000
+ramdiskimage=rootfs.cpio.uboot
+script=boot.scr
diff --git a/board/birdland/bav335x/MAINTAINERS b/board/birdland/bav335x/MAINTAINERS
deleted file mode 100644
index 45dcfcb1e6..0000000000
--- a/board/birdland/bav335x/MAINTAINERS
+++ /dev/null
@@ -1,13 +0,0 @@
-BAV335x BOARD
-M:	Gilles Gameiro <gilles@gigadevices.com>
-S:	Maintained
-F:	include/configs/bav335x.h
-F:	board/birdland/bav335x/Kconfig
-F:	board/birdland/bav335x/Makefile
-F:	board/birdland/bav335x/README
-F:	board/birdland/bav335x/board.c
-F:	board/birdland/bav335x/board.h
-F:	board/birdland/bav335x/mux.c
-F:	board/birdland/bav335x/u-boot.lds
-F:	configs/birdland_bav335a_defconfig
-F:	configs/birdland_bav335b_defconfig
diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c
index 4a0603d0f3..7c49b206c1 100644
--- a/board/bosch/acc/acc.c
+++ b/board/bosch/acc/acc.c
@@ -12,7 +12,6 @@
 #include <dm/platform_data/serial_mxc.h>
 #include <dm/device-internal.h>
 #include <env.h>
-#include <env_internal.h>
 #include <hang.h>
 #include <init.h>
 #include <linux/delay.h>
@@ -236,22 +235,6 @@ static void unset_early_gpio(void)
 	gpio_set_value(GPIO_TOUCH_RESET, 1);
 }
 
-enum env_location env_get_location(enum env_operation op, int prio)
-{
-	if (op == ENVOP_SAVE || op == ENVOP_ERASE)
-		return ENVL_MMC;
-
-	switch (prio) {
-	case 0:
-		return ENVL_NOWHERE;
-
-	case 1:
-		return ENVL_MMC;
-	}
-
-	return ENVL_UNKNOWN;
-}
-
 int board_late_init(void)
 {
 	struct board_info *binfo = detect_board();
@@ -559,7 +542,7 @@ int board_mmc_init(struct bd_info *bis)
 	gpio_direction_input(USDHC2_CD_GPIO);
 	/*
 	 * According to the board_mmc_init() the following map is done:
-	 * (U-boot device node) (Physical Port)
+	 * (U-Boot device node) (Physical Port)
 	 * mmc0 USDHC2
 	 * mmc1 USDHC4
 	 */
diff --git a/board/bosch/shc/README b/board/bosch/shc/README
index 2f206e0d55..74704cdc11 100644
--- a/board/bosch/shc/README
+++ b/board/bosch/shc/README
@@ -68,7 +68,7 @@ Netboot
 - see also doc/SPL/README.am335x-network
 
 - set the jumper into netboot mode
-- compile the U-boot sources with:
+- compile the U-Boot sources with:
   make am335x_shc_netboot_defconfig
   make all
 - copy the images into your tftp boot directory
diff --git a/board/broadcom/bcm11130/MAINTAINERS b/board/broadcom/bcm11130/MAINTAINERS
deleted file mode 100644
index 54783501e6..0000000000
--- a/board/broadcom/bcm11130/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BCM11130 BOARD
-M:	Steve Rae <steve.rae@raedomain.com>
-S:	Maintained
-F:	board/broadcom/bcm28155_ap/
-F:	include/configs/bcm_ep_board.h
-F:	configs/bcm11130_defconfig
diff --git a/board/broadcom/bcm11130_nand/MAINTAINERS b/board/broadcom/bcm11130_nand/MAINTAINERS
deleted file mode 100644
index 4cf66b7e4a..0000000000
--- a/board/broadcom/bcm11130_nand/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BCM11130_NAND BOARD
-M:	Steve Rae <steve.rae@raedomain.com>
-S:	Maintained
-F:	board/broadcom/bcm28155_ap/
-F:	include/configs/bcm_ep_board.h
-F:	configs/bcm11130_nand_defconfig
diff --git a/board/broadcom/bcm28155_w1d/MAINTAINERS b/board/broadcom/bcm28155_w1d/MAINTAINERS
deleted file mode 100644
index c0558e7f25..0000000000
--- a/board/broadcom/bcm28155_w1d/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BCM28155_W1D BOARD
-M:	Steve Rae <steve.rae@raedomain.com>
-S:	Maintained
-F:	board/broadcom/bcm28155_ap/
-F:	include/configs/bcm28155_ap.h
-F:	configs/bcm28155_w1d_defconfig
diff --git a/board/broadcom/bcm_ep/Makefile b/board/broadcom/bcm_ep/Makefile
deleted file mode 100644
index 29a3ea7eda..0000000000
--- a/board/broadcom/bcm_ep/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2014 Broadcom Corporation.
-
-obj-y	+= board.o
diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c
deleted file mode 100644
index e91fa40e64..0000000000
--- a/board/broadcom/bcm_ep/board.c
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Broadcom Corporation.
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <init.h>
-#include <net.h>
-#include <asm/cache.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <config.h>
-#include <netdev.h>
-#include <asm/system.h>
-#include <asm/iproc-common/armpll.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * board_init - early hardware init
- */
-int board_init(void)
-{
-	/*
-	 * Address of boot parameters passed to kernel
-	 * Use default offset 0x100
-	 */
-	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
-/*
- * dram_init - sets u-boot's idea of sdram size
- */
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
-				    CFG_SYS_SDRAM_SIZE);
-	return 0;
-}
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = gd->ram_size;
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	uint32_t status = 0;
-
-	/* Setup PLL if required */
-#if defined(CONFIG_ARMCLK)
-	armpll_config(CONFIG_ARMCLK);
-#endif
-
-	return status;
-}
-
-#ifdef CONFIG_ARMV7_NONSEC
-void smp_set_core_boot_addr(unsigned long addr, int corenr)
-{
-}
-
-void smp_kick_all_cpus(void)
-{
-}
-
-void smp_waitloop(unsigned previous_address)
-{
-}
-#endif
-
-#ifdef CONFIG_BCM_SF2_ETH
-int board_eth_init(struct bd_info *bis)
-{
-	int rc = -1;
-	printf("Registering BCM sf2 eth\n");
-	rc = bcm_sf2_eth_register(bis, 0);
-	return rc;
-}
-#endif
diff --git a/board/broadcom/bcmns/MAINTAINERS b/board/broadcom/bcmns/MAINTAINERS
index fd37c334a5..63c6d8bb4a 100644
--- a/board/broadcom/bcmns/MAINTAINERS
+++ b/board/broadcom/bcmns/MAINTAINERS
@@ -1,6 +1,6 @@
 BCMNS BOARD
 M:	Linus Walleij <linus.walleij@linaro.org>
 S:	Maintained
-F:	board/broadcom/bcmnsp/
-F:	configs/bcmnsp_defconfig
-F:	include/configs/bcmnsp.h
+F:	board/broadcom/bcmns/
+F:	configs/bcmns_defconfig
+F:	include/configs/bcmns.h
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index 2a78df670c..7ae6742c4b 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -183,7 +183,7 @@ int dram_init_banksize(void)
 }
 
 /* Limit RAM used by U-Boot to the DDR first bank End region */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	return BCM_NS3_MEM_END;
 }
diff --git a/board/bsh/imx6ulz_smm_m2/MAINTAINERS b/board/bsh/imx6ulz_smm_m2/MAINTAINERS
index 8f3d79dbb8..77a033c6cb 100644
--- a/board/bsh/imx6ulz_smm_m2/MAINTAINERS
+++ b/board/bsh/imx6ulz_smm_m2/MAINTAINERS
@@ -1,6 +1,6 @@
 MX6ULZ_SMM_M2 BOARD
 M:	Michael Trimarchi <michael@amarulasolutions.com>
 S:	Maintained
-F:	board/bsh/mx6ulz_smm_m2/
+F:	board/bsh/imx6ulz_smm_m2/
 F:	include/configs/imx6ulz_smm_m2.h
 F:	configs/imx6ulz_smm_m2_defconfig
diff --git a/board/cei/cei-tk1-som/MAINTAINERS b/board/cei/cei-tk1-som/MAINTAINERS
index 192e1a34a7..f1817401a5 100644
--- a/board/cei/cei-tk1-som/MAINTAINERS
+++ b/board/cei/cei-tk1-som/MAINTAINERS
@@ -1,6 +1,6 @@
 TK1-SOM BOARD
 M:	Peter.Chubb@data61.csiro.au
 S:	Maintained
-F:	board/cei/tk1-som/
+F:	board/cei/cei-tk1-som/
 F:	include/configs/cei-tk1-som.h
 F:	configs/cei-tk1-som_defconfig
diff --git a/board/cobra5272/MAINTAINERS b/board/cobra5272/MAINTAINERS
index a064da2f15..1f398a7323 100644
--- a/board/cobra5272/MAINTAINERS
+++ b/board/cobra5272/MAINTAINERS
@@ -1,5 +1,5 @@
 COBRA5272 BOARD
-#M:	-
+M:      Angelo Dureghello <angelo@kernel-space.org>
 S:	Maintained
 F:	board/cobra5272/
 F:	include/configs/cobra5272.h
diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c
index 1b08a2c5ab..af19a658b5 100644
--- a/board/compulab/cl-som-imx7/cl-som-imx7.c
+++ b/board/compulab/cl-som-imx7/cl-som-imx7.c
@@ -86,7 +86,7 @@ int board_mmc_init(struct bd_info *bis)
 	int i, ret;
 	/*
 	 * According to the board_mmc_init() the following map is done:
-	 * (U-boot device node)    (Physical Port)
+	 * (U-Boot device node)    (Physical Port)
 	 * mmc0                    USDHC1
 	 * mmc2                    USDHC3 (eMMC)
 	 */
diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
index b373e45df9..af070ec315 100644
--- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
+++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
@@ -50,10 +50,10 @@ struct efi_fw_image fw_images[] = {
 
 struct efi_capsule_update_info update_info = {
 	.dfu_string = "mmc 2=flash-bin raw 0x42 0x1D00 mmcpart 1",
+	.num_images = ARRAY_SIZE(fw_images),
 	.images = fw_images,
 };
 
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
 
 int board_phys_sdram_size(phys_size_t *size)
diff --git a/board/comtrend/ar5315u/MAINTAINERS b/board/comtrend/ar5315u/MAINTAINERS
index 048073cb42..0515e03f60 100644
--- a/board/comtrend/ar5315u/MAINTAINERS
+++ b/board/comtrend/ar5315u/MAINTAINERS
@@ -1,6 +1,6 @@
 COMTREND AR-5315U BOARD
 M:	Álvaro Fernández Rojas <noltari@gmail.com>
 S:	Maintained
-F:	board/comtrend/ar-5315u/
+F:	board/comtrend/ar5315u/
 F:	include/configs/comtrend_ar5315u.h
 F:	configs/comtrend_ar5315u_ram_defconfig
diff --git a/board/comtrend/ar5387un/MAINTAINERS b/board/comtrend/ar5387un/MAINTAINERS
index bcaac64db0..48757c9fd7 100644
--- a/board/comtrend/ar5387un/MAINTAINERS
+++ b/board/comtrend/ar5387un/MAINTAINERS
@@ -1,6 +1,6 @@
 COMTREND AR-5387UN BOARD
 M:	Álvaro Fernández Rojas <noltari@gmail.com>
 S:	Maintained
-F:	board/comtrend/ar-5387un/
+F:	board/comtrend/ar5387un/
 F:	include/configs/comtrend_ar5387un.h
 F:	configs/comtrend_ar5387un_ram_defconfig
diff --git a/board/comtrend/ct5361/MAINTAINERS b/board/comtrend/ct5361/MAINTAINERS
index aea737a0bb..3373e5036b 100644
--- a/board/comtrend/ct5361/MAINTAINERS
+++ b/board/comtrend/ct5361/MAINTAINERS
@@ -1,6 +1,6 @@
 COMTREND CT-5361 BOARD
 M:	Álvaro Fernández Rojas <noltari@gmail.com>
 S:	Maintained
-F:	board/comtrend/ct-5361/
+F:	board/comtrend/ct5361/
 F:	include/configs/comtrend_ct5361.h
 F:	configs/comtrend_ct5361_ram_defconfig
diff --git a/board/comtrend/vr3032u/MAINTAINERS b/board/comtrend/vr3032u/MAINTAINERS
index 833d7da4af..132101f4cd 100644
--- a/board/comtrend/vr3032u/MAINTAINERS
+++ b/board/comtrend/vr3032u/MAINTAINERS
@@ -1,6 +1,6 @@
 COMTREND VR-3032U BOARD
 M:	Álvaro Fernández Rojas <noltari@gmail.com>
 S:	Maintained
-F:	board/comtrend/vr-3032u/
+F:	board/comtrend/vr3032u/
 F:	include/configs/comtrend_vr-3032u.h
 F:	configs/comtrend_vr3032u_ram_defconfig
diff --git a/board/comtrend/wap5813n/MAINTAINERS b/board/comtrend/wap5813n/MAINTAINERS
index f4d99796b4..c6764831b2 100644
--- a/board/comtrend/wap5813n/MAINTAINERS
+++ b/board/comtrend/wap5813n/MAINTAINERS
@@ -1,6 +1,6 @@
 COMTREND WAP-5813N BOARD
 M:	Álvaro Fernández Rojas <noltari@gmail.com>
 S:	Maintained
-F:	board/comtrend/wap-5813n/
+F:	board/comtrend/wap5813n/
 F:	include/configs/comtrend_wap-5813n.h
 F:	configs/comtrend_wap5813n_ram_defconfig
diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c
index bedd1e0330..26189ff66f 100644
--- a/board/congatec/cgtqmx8/cgtqmx8.c
+++ b/board/congatec/cgtqmx8/cgtqmx8.c
@@ -79,7 +79,7 @@ static void setup_iomux_uart(void)
 int board_early_init_f(void)
 {
 	/* sc_ipc_t ipcHndl = 0; */
-	sc_err_t scierr = 0;
+	int scierr;
 
 	/* When start u-boot in XEN VM, directly return */
 	/* if (IS_ENABLED(CONFIG_XEN)) */
@@ -89,19 +89,19 @@ int board_early_init_f(void)
 
 	/* Power up UART0, this is very early while power domain is not working */
 	scierr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
-	if (scierr != SC_ERR_NONE)
+	if (scierr)
 		return 0;
 
 	/* Set UART0 clock root to 80 MHz */
 	sc_pm_clock_rate_t rate = 80000000;
 
 	scierr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
-	if (scierr != SC_ERR_NONE)
+	if (scierr)
 		return 0;
 
 	/* Enable UART0 clock root */
 	scierr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
-	if (scierr != SC_ERR_NONE)
+	if (scierr)
 		return 0;
 
 	setup_iomux_uart();
diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
index ee12d32ce7..f777365800 100644
--- a/board/coreboot/coreboot/MAINTAINERS
+++ b/board/coreboot/coreboot/MAINTAINERS
@@ -1,13 +1,11 @@
 COREBOOT BOARD
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
-F:	board/coreboot/coreboot/
+F:	board/coreboot/
 F:	include/configs/coreboot.h
 F:	configs/coreboot_defconfig
 
 COREBOOT64 BOARD
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
-F:	board/coreboot/coreboot/
-F:	include/configs/coreboot.h
 F:	configs/coreboot64_defconfig
diff --git a/board/coreboot/coreboot/coreboot.env b/board/coreboot/coreboot/coreboot.env
new file mode 100644
index 0000000000..0f5bb6fb62
--- /dev/null
+++ b/board/coreboot/coreboot/coreboot.env
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
+
+splashsource=virtio_fs
+splashimage=0x1000000
diff --git a/board/data_modul/imx8mm_edm_sbc/MAINTAINERS b/board/data_modul/imx8mm_edm_sbc/MAINTAINERS
index 72659c081e..36af19b78f 100644
--- a/board/data_modul/imx8mm_edm_sbc/MAINTAINERS
+++ b/board/data_modul/imx8mm_edm_sbc/MAINTAINERS
@@ -3,6 +3,6 @@ M:	Marek Vasut <marex@denx.de>
 S:	Maintained
 F:	arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
 F:	arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
-F:	board/data_modul/imx8mm_data_modul_edm_sbc/
+F:	board/data_modul/imx8mm_edm_sbc/
 F:	configs/imx8mm_data_modul_edm_sbc_defconfig
 F:	include/configs/imx8mm_data_modul_edm_sbc.h
diff --git a/board/data_modul/imx8mp_edm_sbc/MAINTAINERS b/board/data_modul/imx8mp_edm_sbc/MAINTAINERS
index a67e104761..8a49c8a67d 100644
--- a/board/data_modul/imx8mp_edm_sbc/MAINTAINERS
+++ b/board/data_modul/imx8mp_edm_sbc/MAINTAINERS
@@ -3,6 +3,6 @@ M:	Marek Vasut <marex@denx.de>
 S:	Maintained
 F:	arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
 F:	arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
-F:	board/data_modul/imx8mp_data_modul_edm_sbc/
+F:	board/data_modul/imx8mp_edm_sbc/
 F:	configs/imx8mp_data_modul_edm_sbc_defconfig
 F:	include/configs/imx8mp_data_modul_edm_sbc.h
diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c
index c30185e48d..2fdd95a730 100644
--- a/board/data_modul/imx8mp_edm_sbc/spl.c
+++ b/board/data_modul/imx8mp_edm_sbc/spl.c
@@ -107,6 +107,20 @@ void board_boot_order(u32 *spl_boot_list)
 	spl_boot_list[4] = BOOT_DEVICE_NONE;
 }
 
+unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long sect)
+{
+	const u32 boot_dev = spl_boot_device();
+	int part;
+
+	if (boot_dev == BOOT_DEVICE_MMC2) {	/* eMMC */
+		part = spl_mmc_emmc_boot_partition(mmc);
+		if (part == 1 || part == 2)	/* eMMC BOOT1/BOOT2 HW partitions */
+			return sect - 0x40;
+	}
+
+	return sect;
+}
+
 static struct dram_timing_info *dram_timing_info[8] = {
 	&dmo_imx8mp_sbc_dram_timing_32_32,	/* 32 Gbit x32 */
 	NULL,					/* 32 Gbit x16 */
diff --git a/board/devboards/dbm-soc1/MAINTAINERS b/board/devboards/dbm-soc1/MAINTAINERS
index 625f2c8899..577eba5a28 100644
--- a/board/devboards/dbm-soc1/MAINTAINERS
+++ b/board/devboards/dbm-soc1/MAINTAINERS
@@ -1,5 +1,6 @@
 Devboards.de DBM-SoC1 BOARD
 M:	Marek Vasut <marex@denx.de>
 S:	Maintained
+F:	board/devboards/dbm-soc1/
 F:	include/configs/socfpga_dbm_soc1.h
 F:	configs/socfpga_dbm_soc1_defconfig
diff --git a/board/dhelectronics/dh_imx8mp/MAINTAINERS b/board/dhelectronics/dh_imx8mp/MAINTAINERS
index 7c70cfdd94..db69781a85 100644
--- a/board/dhelectronics/dh_imx8mp/MAINTAINERS
+++ b/board/dhelectronics/dh_imx8mp/MAINTAINERS
@@ -1,8 +1,8 @@
-DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus
+DH electronics DHCOM i.MX8M Plus and matching carrier boards
 M:	Marek Vasut <marex@denx.de>
+L:	u-boot@dh-electronics.com
 S:	Maintained
-F:	arch/arm/dts/imx8mp-dhcom-pdk2.dts
-F:	arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi
-F:	board/dhelectronics/imx8mp_dhcom_pdk2/
-F:	configs/imx8mp_dhcom_pdk2_defconfig
-F:	include/configs/imx8mp_dhcom_pdk2.h
+F:	arch/arm/dts/imx8mp-dhcom*
+F:	board/dhelectronics/dh_imx8mp/
+F:	configs/imx8mp_dhcom*defconfig
+F:	include/configs/imx8mp_dhcom*
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index 8d8104ad4b..f9cfabe242 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -184,9 +184,9 @@ int checkboard(void)
 }
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
-static u8 brdcode __section("data");
-static u8 ddr3code __section("data");
-static u8 somcode __section("data");
+static u8 brdcode __section(".data");
+static u8 ddr3code __section(".data");
+static u8 somcode __section(".data");
 static u32 opp_voltage_mv __section(".data");
 
 static void board_get_coding_straps(void)
diff --git a/board/edgeble/neural-compute-module-6/MAINTAINERS b/board/edgeble/neural-compute-module-6/MAINTAINERS
index 249df957f1..42e5df506b 100644
--- a/board/edgeble/neural-compute-module-6/MAINTAINERS
+++ b/board/edgeble/neural-compute-module-6/MAINTAINERS
@@ -4,3 +4,10 @@ S:	Maintained
 F:	board/edgeble/neural-compute-module-6
 F:	include/configs/neural-compute-module-6.h
 F:	configs/neu6a-io-rk3588_defconfig
+F:	configs/neu6b-io-rk3588_defconfig
+F:	arch/arm/dts/rk3588-edgeble-neu6a.dtsi
+F:	arch/arm/dts/rk3588-edgeble-neu6a-io.dts
+F:	arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+F:	arch/arm/dts/rk3588-edgeble-neu6b.dtsi
+F:	arch/arm/dts/rk3588-edgeble-neu6b-io.dts
+F:	arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
diff --git a/board/efi/efi-x86_app/MAINTAINERS b/board/efi/efi-x86_app/MAINTAINERS
index b292811a8f..584619c51d 100644
--- a/board/efi/efi-x86_app/MAINTAINERS
+++ b/board/efi/efi-x86_app/MAINTAINERS
@@ -1,6 +1,7 @@
 EFI-X86_APP32 BOARD
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
+F:	board/efi/Kconfig
 F:	board/efi/efi-x86_app/
 F:	include/configs/efi-x86_app.h
 F:	configs/efi-x86_app32_defconfig
@@ -8,6 +9,7 @@ F:	configs/efi-x86_app32_defconfig
 EFI-X86_APP64 BOARD
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
+F:	board/efi/Kconfig
 F:	board/efi/efi-x86_app/
 F:	include/configs/efi-x86_app.h
 F:	configs/efi-x86_app64_defconfig
diff --git a/board/efi/efi-x86_app/efi-x86_app.env b/board/efi/efi-x86_app/efi-x86_app.env
new file mode 100644
index 0000000000..106836af1f
--- /dev/null
+++ b/board/efi/efi-x86_app/efi-x86_app.env
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#include <env/x86.env>
diff --git a/board/efi/efi-x86_payload/MAINTAINERS b/board/efi/efi-x86_payload/MAINTAINERS
index abf3a1574b..d795d60e09 100644
--- a/board/efi/efi-x86_payload/MAINTAINERS
+++ b/board/efi/efi-x86_payload/MAINTAINERS
@@ -1,6 +1,7 @@
 EFI-X86_PAYLOAD BOARD
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
+F:	board/efi/Kconfig
 F:	board/efi/efi-x86_payload/
 F:	include/configs/efi-x86_payload.h
 F:	configs/efi-x86_payload32_defconfig
diff --git a/board/efi/efi-x86_payload/efi-x86_payload.env b/board/efi/efi-x86_payload/efi-x86_payload.env
new file mode 100644
index 0000000000..6a65628706
--- /dev/null
+++ b/board/efi/efi-x86_payload/efi-x86_payload.env
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
diff --git a/board/emulation/qemu-arm/MAINTAINERS b/board/emulation/qemu-arm/MAINTAINERS
index e757ffc64f..5154262f29 100644
--- a/board/emulation/qemu-arm/MAINTAINERS
+++ b/board/emulation/qemu-arm/MAINTAINERS
@@ -2,6 +2,7 @@ QEMU ARM 'VIRT' BOARD
 M:	Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
 S:	Maintained
 F:	board/emulation/qemu-arm/
+F:	board/emulation/common/
 F:	include/configs/qemu-arm.h
 F:	configs/qemu_arm_defconfig
 F:	configs/qemu_arm64_defconfig
diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c
index 34ed3e8ae6..dfea0d92a3 100644
--- a/board/emulation/qemu-arm/qemu-arm.c
+++ b/board/emulation/qemu-arm/qemu-arm.c
@@ -47,10 +47,10 @@ struct efi_fw_image fw_images[] = {
 };
 
 struct efi_capsule_update_info update_info = {
+	.num_images = ARRAY_SIZE(fw_images)
 	.images = fw_images,
 };
 
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
 
 static struct mm_region qemu_arm64_mem_map[] = {
diff --git a/board/emulation/qemu-ppce500/MAINTAINERS b/board/emulation/qemu-ppce500/MAINTAINERS
index 7317983d6a..348ae9085f 100644
--- a/board/emulation/qemu-ppce500/MAINTAINERS
+++ b/board/emulation/qemu-ppce500/MAINTAINERS
@@ -3,5 +3,6 @@ M:	Alexander Graf <agraf@csgraf.de>
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 F:	board/emulation/qemu-ppce500/
+F:	board/emulation/common/
 F:	include/configs/qemu-ppce500.h
 F:	configs/qemu-ppce500_defconfig
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 6114e1b812..d56b4b5bc1 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -25,6 +25,10 @@ config SPL_OPENSBI_LOAD_ADDR
 	hex
 	default 0x80100000
 
+config PRE_CON_BUF_ADDR
+	hex
+	default 0x81000000
+
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select GENERIC_RISCV
@@ -53,6 +57,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply NVME
 	imply PCI
 	imply PCIE_ECAM_GENERIC
+	imply DM_RNG
 	imply SCSI
 	imply DM_SCSI
 	imply SYS_NS16550
@@ -68,5 +73,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply MTD_NOR_FLASH
 	imply CFI_FLASH
 	imply OF_HAS_PRIOR_STAGE
+	imply VIDEO
+	imply VIDEO_BOCHS
+	imply SYS_WHITE_ON_BLACK
+	imply PRE_CONSOLE_BUFFER
+	imply USB
+	imply USB_XHCI_HCD
+	imply USB_XHCI_PCI
+	imply USB_KEYBOARD
+	imply CMD_USB
 
 endif
diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS
index 78969ed6bd..3d7453f1b4 100644
--- a/board/emulation/qemu-riscv/MAINTAINERS
+++ b/board/emulation/qemu-riscv/MAINTAINERS
@@ -2,6 +2,7 @@ QEMU RISC-V 'VIRT' BOARD
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 F:	board/emulation/qemu-riscv/
+F:	board/emulation/common/
 F:	include/configs/qemu-riscv.h
 F:	configs/qemu-riscv32_defconfig
 F:	configs/qemu-riscv32_smode_defconfig
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
index ae3b7a3295..181abbbf97 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -12,6 +12,7 @@
 #include <log.h>
 #include <spl.h>
 #include <init.h>
+#include <usb.h>
 #include <virtio_types.h>
 #include <virtio.h>
 
@@ -41,29 +42,9 @@ int board_init(void)
 
 int board_late_init(void)
 {
-	ulong kernel_start;
-	ofnode chosen_node;
-	int ret;
-
-	chosen_node = ofnode_path("/chosen");
-	if (!ofnode_valid(chosen_node)) {
-		debug("No chosen node found, can't get kernel start address\n");
-		return 0;
-	}
-
-#ifdef CONFIG_ARCH_RV64I
-	ret = ofnode_read_u64(chosen_node, "riscv,kernel-start",
-			      (u64 *)&kernel_start);
-#else
-	ret = ofnode_read_u32(chosen_node, "riscv,kernel-start",
-			      (u32 *)&kernel_start);
-#endif
-	if (ret) {
-		debug("Can't find kernel start address in device tree\n");
-		return 0;
-	}
-
-	env_set_hex("kernel_start", kernel_start);
+	/* start usb so that usb keyboard can be used as input device */
+	if (CONFIG_IS_ENABLED(USB_KEYBOARD))
+		usb_init();
 
 	return 0;
 }
diff --git a/board/emulation/qemu-x86/MAINTAINERS b/board/emulation/qemu-x86/MAINTAINERS
index 9a99d38ca0..e62585a65d 100644
--- a/board/emulation/qemu-x86/MAINTAINERS
+++ b/board/emulation/qemu-x86/MAINTAINERS
@@ -2,6 +2,7 @@ QEMU X86 BOARD
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 F:	board/emulation/qemu-x86/
+F:	board/emulation/common/
 F:	include/configs/qemu-x86.h
 F:	configs/qemu-x86_defconfig
 
@@ -9,5 +10,6 @@ QEMU X86 64-bit BOARD
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 F:	board/emulation/qemu-x86/
+F:	board/emulation/common/
 F:	include/configs/qemu-x86.h
 F:	configs/qemu-x86_64_defconfig
diff --git a/board/emulation/qemu-x86/qemu-x86.env b/board/emulation/qemu-x86/qemu-x86.env
new file mode 100644
index 0000000000..adcc1c53bd
--- /dev/null
+++ b/board/emulation/qemu-x86/qemu-x86.env
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
diff --git a/board/engicam/imx6q/MAINTAINERS b/board/engicam/imx6q/MAINTAINERS
index 6b46378c54..266da95ec0 100644
--- a/board/engicam/imx6q/MAINTAINERS
+++ b/board/engicam/imx6q/MAINTAINERS
@@ -2,6 +2,7 @@ MX6Q_ENGICAM BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/imx6q
+F:	board/engicam/common
 F:	include/configs/imx6-engicam.h
 F:	configs/imx6qdl_icore_mmc_defconfig
 F:	configs/imx6q_icore_nand_defconfig
diff --git a/board/engicam/imx6ul/MAINTAINERS b/board/engicam/imx6ul/MAINTAINERS
index 88db309aec..b9c6af2724 100644
--- a/board/engicam/imx6ul/MAINTAINERS
+++ b/board/engicam/imx6ul/MAINTAINERS
@@ -2,6 +2,7 @@ MX6UL_ENGICAM BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/imx6ul
+F:	board/engicam/common
 F:	include/configs/imx6-engicam.h
 F:	configs/imx6ul_geam_mmc_defconfig
 F:	configs/imx6ul_geam_nand_defconfig
diff --git a/board/engicam/imx8mm/MAINTAINERS b/board/engicam/imx8mm/MAINTAINERS
index 2e99a5995f..ec0ad51448 100644
--- a/board/engicam/imx8mm/MAINTAINERS
+++ b/board/engicam/imx8mm/MAINTAINERS
@@ -9,5 +9,6 @@ M:	Jagan Teki <jagan@amarulasolutions.com>
 M:	Matteo Lisi <matteo.lisi@engicam.com>
 S:	Maintained
 F:	board/engicam/imx8mm
+F:	board/engicam/common
 F:	include/configs/imx8mm_icore_mx8mm.h
 F:	configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
diff --git a/board/engicam/imx8mp/MAINTAINERS b/board/engicam/imx8mp/MAINTAINERS
index a25908a76c..c86f9bc915 100644
--- a/board/engicam/imx8mp/MAINTAINERS
+++ b/board/engicam/imx8mp/MAINTAINERS
@@ -3,5 +3,6 @@ M:	Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
 M:	Matteo Lisi <matteo.lisi@engicam.com>
 S:	Maintained
 F:	board/engicam/imx8mp
+F:	board/engicam/common
 F:	include/configs/imx8mp_icore_mx8mp.h
 F:	configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
diff --git a/board/engicam/px30_core/MAINTAINERS b/board/engicam/px30_core/MAINTAINERS
index 77f0c2dba5..99c5f283fc 100644
--- a/board/engicam/px30_core/MAINTAINERS
+++ b/board/engicam/px30_core/MAINTAINERS
@@ -15,5 +15,6 @@ M:	Jagan Teki <jagan@amarulasolutions.com>
 M:	Suniel Mahesh <sunil@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/px30_core
+F:	board/engicam/common
 F:	include/configs/px30_core.h
 F:	configs/px30-core-edimm2.2-px30_defconfig
diff --git a/board/engicam/stm32mp1/MAINTAINERS b/board/engicam/stm32mp1/MAINTAINERS
index 405ff99185..4ba2a76184 100644
--- a/board/engicam/stm32mp1/MAINTAINERS
+++ b/board/engicam/stm32mp1/MAINTAINERS
@@ -23,4 +23,5 @@ M:	Matteo Lisi <matteo.lisi@engicam.com>
 S:	Maintained
 F:	arch/arm/dts/stm32mp15*icore*
 F:	board/engicam/stm32mp1
+F:	board/engicam/common
 F:	configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
diff --git a/board/firefly/firefly-rk3308/MAINTAINERS b/board/firefly/firefly-rk3308/MAINTAINERS
index 199079717e..e584038a20 100644
--- a/board/firefly/firefly-rk3308/MAINTAINERS
+++ b/board/firefly/firefly-rk3308/MAINTAINERS
@@ -1,5 +1,6 @@
 ROC-RK3308-CC
 M:      Andy Yan <andy.yan@rock-chips.com>
 S:      Maintained
-F:      board/firefly/firefly-rk3308/roc_cc_rk3308.c
+F:      board/firefly/firefly-rk3308/
 F:      configs/roc-cc-rk3308_defconfig
+F:      include/configs/firefly_rk3308.h
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index b47ce05251..87ed814d6a 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -127,7 +127,7 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
 				   &img_addr);
 
 	if (res == 0)
-		printf("SPL: Validation of U-boot successful\n");
+		printf("SPL: Validation of U-Boot successful\n");
 }
 
 #ifdef CONFIG_SPL_FRAMEWORK
diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index 6dca22960b..a9288820b2 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -91,7 +91,7 @@ struct pmic *pfuze_common_init(unsigned char i2cbus)
 
 	return p;
 }
-#else
+#elif defined(CONFIG_DM_PMIC)
 int pfuze_mode_init(struct udevice *dev, u32 mode)
 {
 	unsigned char offset, i, switch_num;
diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h
index 49a684f9f4..8d343ba4d6 100644
--- a/board/freescale/common/vsc3316_3308.h
+++ b/board/freescale/common/vsc3316_3308.h
@@ -4,7 +4,7 @@
  */
 
 #ifndef __VSC_CROSSBAR_H_
-#define __VSC_CROSSBAR_H	1_
+#define __VSC_CROSSBAR_H_
 
 #include <common.h>
 #include <i2c.h>
diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index a0dad5f983..66d0f68cc6 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -19,7 +19,7 @@
 #include <asm/arch/ddr.h>
 #include <asm/arch/rdc.h>
 #include <asm/arch/upower.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -63,9 +63,9 @@ void display_ele_fw_version(void)
 	u32 fw_version, sha1, res;
 	int ret;
 
-	ret = ahab_get_fw_version(&fw_version, &sha1, &res);
+	ret = ele_get_fw_version(&fw_version, &sha1, &res);
 	if (ret) {
-		printf("ahab get firmware version failed %d, 0x%x\n", ret, res);
+		printf("ele get firmware version failed %d, 0x%x\n", ret, res);
 	} else {
 		printf("ELE firmware version %u.%u.%u-%x",
 		       (fw_version & (0x00ff0000)) >> 16,
@@ -120,9 +120,19 @@ void spl_board_init(void)
 	set_lpav_qos();
 
 	/* Enable A35 access to the CAAM */
-	ret = ahab_release_caam(0x7, &res);
+	ret = ele_release_caam(0x7, &res);
 	if (ret)
-		printf("ahab release caam failed %d, 0x%x\n", ret, res);
+		printf("ele release caam failed %d, 0x%x\n", ret, res);
+
+	/*
+	 * RNG start only available on the A1 soc revision.
+	 * Check some JTAG register for the SoC revision.
+	 */
+	if (!is_soc_rev(CHIP_REV_1_0)) {
+		ret = ele_start_rng();
+		if (ret)
+			printf("Fail to start RNG: %d\n", ret);
+	}
 }
 
 void board_init_f(ulong dummy)
diff --git a/board/freescale/imx93_evk/MAINTAINERS b/board/freescale/imx93_evk/MAINTAINERS
index 8ca4646f20..34ba278fcd 100644
--- a/board/freescale/imx93_evk/MAINTAINERS
+++ b/board/freescale/imx93_evk/MAINTAINERS
@@ -4,4 +4,4 @@ S:	Maintained
 F:	board/freescale/imx93_evk/
 F:	include/configs/imx93_evk.h
 F:	configs/imx93_11x11_evk_defconfig
-	configs/imx93_11x11_evk_ld_defconfig
+F:	configs/imx93_11x11_evk_ld_defconfig
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 352ad79cb6..63883b30dd 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -20,7 +20,6 @@
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/arch-mx7ulp/gpio.h>
 #include <asm/mach-imx/syscounter.h>
-#include <asm/mach-imx/s400_api.h>
 #include <dm/uclass.h>
 #include <dm/device.h>
 #include <dm/uclass-internal.h>
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
index 5fc7e93850..89d1085b00 100644
--- a/board/freescale/ls1012afrdm/MAINTAINERS
+++ b/board/freescale/ls1012afrdm/MAINTAINERS
@@ -1,5 +1,5 @@
 LS1012AFRDM BOARD
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M:	Pramod Kumar <pramod.kumar_1@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1012afrdm/
 F:	include/configs/ls1012afrdm.h
diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
index 382b668fbe..e60ed606ec 100644
--- a/board/freescale/ls1012afrdm/README
+++ b/board/freescale/ls1012afrdm/README
@@ -52,7 +52,7 @@ QSPI flash map
 Images		| Size	|QSPI Flash Address
 ------------------------------------------
 RCW + PBI	| 1MB	| 0x4000_0000
-U-boot		| 1MB	| 0x4010_0000
-U-boot Env	| 1MB	| 0x4020_0000
+U-Boot		| 1MB	| 0x4010_0000
+U-Boot Env	| 1MB	| 0x4020_0000
 PPA FIT image	| 2MB	| 0x4050_0000
 Linux ITB	| ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
index c1bb8d5150..eabf580576 100644
--- a/board/freescale/ls1012aqds/MAINTAINERS
+++ b/board/freescale/ls1012aqds/MAINTAINERS
@@ -1,5 +1,4 @@
 LS1012AQDS BOARD
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 M:	Pramod Kumar <pramod.kumar_1@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1012aqds/
diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
index c1956f9fd7..e9b80cad50 100644
--- a/board/freescale/ls1012aqds/README
+++ b/board/freescale/ls1012aqds/README
@@ -53,7 +53,7 @@ QSPI flash map
 Images		| Size	|QSPI Flash Address
 ------------------------------------------
 RCW + PBI	| 1MB	| 0x4000_0000
-U-boot		| 1MB	| 0x4010_0000
-U-boot Env	| 1MB	| 0x4020_0000
+U-Boot		| 1MB	| 0x4010_0000
+U-Boot Env	| 1MB	| 0x4020_0000
 PPA FIT image	| 2MB	| 0x4050_0000
 Linux ITB	| ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
index b0c008b5fc..ce2f9a16cc 100644
--- a/board/freescale/ls1012ardb/MAINTAINERS
+++ b/board/freescale/ls1012ardb/MAINTAINERS
@@ -1,5 +1,4 @@
 LS1012ARDB BOARD
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 M:	Pramod Kumar <pramod.kumar_1@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1012ardb/
diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
index 5b6f306a1d..26b0485a7f 100644
--- a/board/freescale/ls1012ardb/README
+++ b/board/freescale/ls1012ardb/README
@@ -48,8 +48,8 @@ QSPI flash map
 Images		| Size	|QSPI Flash Address
 ------------------------------------------
 RCW + PBI	| 1MB	| 0x4000_0000
-U-boot		| 1MB	| 0x4010_0000
-U-boot Env	| 1MB	| 0x4020_0000
+U-Boot		| 1MB	| 0x4010_0000
+U-Boot Env	| 1MB	| 0x4020_0000
 PPA FIT image	| 2MB	| 0x4050_0000
 Linux ITB	| ~53MB | 0x40A0_0000
 
@@ -90,8 +90,8 @@ QSPI flash map
 Images		| Size	|QSPI Flash Address
 ------------------------------------------
 RCW + PBI	| 1MB	| 0x4000_0000
-U-boot		| 1MB	| 0x4010_0000
-U-boot Env	| 1MB	| 0x4030_0000
+U-Boot		| 1MB	| 0x4010_0000
+U-Boot Env	| 1MB	| 0x4030_0000
 PPA FIT image	| 2MB	| 0x4040_0000
 PFE firmware	| 20K	| 0x00a0_0000
 Linux ITB	| ~53MB | 0x4100_0000
diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS
index 9e7b0697ff..551f6a0865 100644
--- a/board/freescale/ls1028a/MAINTAINERS
+++ b/board/freescale/ls1028a/MAINTAINERS
@@ -1,5 +1,4 @@
 LS1028AQDS BOARD
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 M:	Tang Yuantian <andy.tang@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1028a/
@@ -9,7 +8,6 @@ F:	configs/ls1028aqds_tfa_defconfig
 F:	configs/ls1028aqds_tfa_lpuart_defconfig
 
 LS1028ARDB BOARD
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 M:	Tang Yuantian <andy.tang@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1028a/
diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS
index 9fb6cc85cd..f7420ecd30 100644
--- a/board/freescale/ls1043aqds/MAINTAINERS
+++ b/board/freescale/ls1043aqds/MAINTAINERS
@@ -1,6 +1,5 @@
 LS1043AQDS BOARD
 M:	Mingkai Hu <mingkai.hu@nxp.com>
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1043aqds/
 F:	include/configs/ls1043aqds.h
diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS
index 36e7331538..06b23889f6 100644
--- a/board/freescale/ls1043ardb/MAINTAINERS
+++ b/board/freescale/ls1043ardb/MAINTAINERS
@@ -1,9 +1,7 @@
 LS1043A BOARD
 M:	Mingkai Hu <mingkai.hu@nxp.com>
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1043ardb/
-F:	board/freescale/ls1043ardb/ls1043ardb.c
 F:	include/configs/ls1043ardb.h
 F:	configs/ls1043ardb_defconfig
 F:	configs/ls1043ardb_nand_defconfig
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
index f6e5c122ea..899c22a367 100644
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -134,6 +134,9 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 	out_le32(SMMU_NSCR0, val);
 #endif
 
+	if (!IS_ENABLED(CONFIG_SYS_EARLY_PCI_INIT))
+		pci_init();
+
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 	return 0;
 }
diff --git a/board/freescale/ls1046aqds/MAINTAINERS b/board/freescale/ls1046aqds/MAINTAINERS
index 72c4253fcf..e1db2aaa8e 100644
--- a/board/freescale/ls1046aqds/MAINTAINERS
+++ b/board/freescale/ls1046aqds/MAINTAINERS
@@ -1,6 +1,5 @@
 LS1046AQDS BOARD
 M:	Mingkai Hu <Mingkai.Hu@nxp.com>
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1046aqds/
 F:	include/configs/ls1046aqds.h
diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS
index 3c8cfe720d..d5a6b26151 100644
--- a/board/freescale/ls1046ardb/MAINTAINERS
+++ b/board/freescale/ls1046ardb/MAINTAINERS
@@ -1,6 +1,5 @@
 LS1046A BOARD
 M:	Mingkai Hu <mingkai.hu@nxp.com>
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1046ardb/
 F:	board/freescale/ls1046ardb/ls1046ardb.c
diff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS
index 5c7925a95f..95a14149e4 100644
--- a/board/freescale/ls1088a/MAINTAINERS
+++ b/board/freescale/ls1088a/MAINTAINERS
@@ -1,6 +1,5 @@
 LS1088ARDB BOARD
 M:	Ashish Kumar <Ashish.Kumar@nxp.com>
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1088a/
 F:	include/configs/ls1088ardb.h
@@ -11,7 +10,6 @@ F:	configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
 
 LS1088AQDS BOARD
 M:	Ashish Kumar <Ashish.Kumar@nxp.com>
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 S:	Maintained
 F:	board/freescale/ls1088a/
 F:	include/configs/ls1088aqds.h
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 39d02ae3f4..fdad199ec2 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -1,6 +1,5 @@
 LS2080A BOARD
 M:	Priyanka Jain <priyanka.jain@nxp.com>
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 M:	Wasim Khan <wasim.khan@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080aqds/
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index f49d26af3a..f2f834ffbd 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -10,7 +10,6 @@ F:	configs/ls2080ardb_nand_defconfig
 
 LS2088A_QSPI-boot BOARD
 M:	Priyanka Jain <priyanka.jain@nxp.com>
-M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
 M:	Wasim Khan <wasim.khan@nxp.com>
 S:	Maintained
 F:	configs/ls2088ardb_qspi_defconfig
diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c
index 533f606eff..c5dfefe1f3 100644
--- a/board/freescale/lx2160a/eth_lx2160ardb.c
+++ b/board/freescale/lx2160a/eth_lx2160ardb.c
@@ -8,6 +8,7 @@
 #include <netdev.h>
 #include <exports.h>
 #include <fsl-mc/fsl_mc.h>
+#include "lx2160a.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -36,3 +37,109 @@ void reset_phy(void)
 #endif
 }
 #endif /* CONFIG_RESET_PHY_R */
+
+static int fdt_get_dpmac_node(void *fdt, int dpmac_id)
+{
+	char dpmac_str[11] = "dpmacs@00";
+	int offset, dpmacs_offset;
+
+	/* get the dpmac offset */
+	dpmacs_offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
+	if (dpmacs_offset < 0)
+		dpmacs_offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
+
+	if (dpmacs_offset < 0) {
+		printf("dpmacs node not found in device tree\n");
+		return dpmacs_offset;
+	}
+
+	sprintf(dpmac_str, "dpmac@%x", dpmac_id);
+	offset = fdt_subnode_offset(fdt, dpmacs_offset, dpmac_str);
+	if (offset < 0) {
+		sprintf(dpmac_str, "ethernet@%x", dpmac_id);
+		offset = fdt_subnode_offset(fdt, dpmacs_offset, dpmac_str);
+		if (offset < 0) {
+			printf("dpmac@%x/ethernet@%x node not found in device tree\n",
+			       dpmac_id, dpmac_id);
+			return offset;
+		}
+	}
+
+	return offset;
+}
+
+static int fdt_update_phy_addr(void *fdt, int dpmac_id, int phy_addr)
+{
+	char dpmac_str[] = "dpmacs@00";
+	const u32 *phyhandle;
+	int offset;
+	int err;
+
+	/* get the dpmac offset */
+	offset = fdt_get_dpmac_node(fdt, dpmac_id);
+	if (offset < 0)
+		return offset;
+
+	/* get dpmac phy-handle */
+	sprintf(dpmac_str, "dpmac@%x", dpmac_id);
+	phyhandle = (u32 *)fdt_getprop(fdt, offset, "phy-handle", NULL);
+	if (!phyhandle) {
+		printf("%s node not found in device tree\n", dpmac_str);
+		return offset;
+	}
+
+	offset = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyhandle));
+	if (offset < 0) {
+		printf("Could not get the ph node offset for dpmac %d\n",
+		       dpmac_id);
+		return offset;
+	}
+
+	phy_addr = cpu_to_fdt32(phy_addr);
+	err = fdt_setprop(fdt, offset, "reg", &phy_addr, sizeof(phy_addr));
+	if (err < 0) {
+		printf("Could not set phy node's reg for dpmac %d: %s.\n",
+		       dpmac_id, fdt_strerror(err));
+		return err;
+	}
+
+	return 0;
+}
+
+static int fdt_delete_phy_handle(void *fdt, int dpmac_id)
+{
+	const u32 *phyhandle;
+	int offset;
+
+	/* get the dpmac offset */
+	offset = fdt_get_dpmac_node(fdt, dpmac_id);
+	if (offset < 0)
+		return offset;
+
+	/* verify if the node has a phy-handle */
+	phyhandle = (u32 *)fdt_getprop(fdt, offset, "phy-handle", NULL);
+	if (!phyhandle)
+		return 0;
+
+	return fdt_delprop(fdt, offset, "phy-handle");
+}
+
+int fdt_fixup_board_phy_revc(void *fdt)
+{
+	int ret;
+
+	if (get_board_rev() < 'C')
+		return 0;
+
+	/* DPMACs 3,4 have their Aquantia PHYs at new addresses */
+	ret = fdt_update_phy_addr(fdt, 3, AQR113C_PHY_ADDR1);
+	if (ret)
+		return ret;
+
+	ret = fdt_update_phy_addr(fdt, 4, AQR113C_PHY_ADDR2);
+	if (ret)
+		return ret;
+
+	/* There is no PHY for the DPMAC2, so remove the phy-handle */
+	return fdt_delete_phy_handle(fdt, 2);
+}
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 2a752054cd..d631a11ff6 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -133,6 +133,11 @@ int board_fix_fdt(void *fdt)
 		fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 	}
 
+	/* Fixup u-boot's DTS in case this is a revC board and
+	 * we're using DM_ETH.
+	 */
+	if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB) && IS_ENABLED(CONFIG_DM_ETH))
+		fdt_fixup_board_phy_revc(fdt);
 	return 0;
 }
 #endif
@@ -487,6 +492,15 @@ int config_board_mux(void)
 }
 #endif
 
+#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB)
+u8 get_board_rev(void)
+{
+	u8 board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A';
+
+	return board_rev;
+}
+#endif
+
 unsigned long get_board_sys_clk(void)
 {
 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
@@ -627,6 +641,8 @@ void fdt_fixup_board_enet(void *fdt)
 	if (get_mc_boot_status() == 0 &&
 	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 		fdt_status_okay(fdt, offset);
+		if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB))
+			fdt_fixup_board_phy_revc(fdt);
 	} else {
 		fdt_status_fail(fdt, offset);
 	}
@@ -760,9 +776,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	u64 mc_memory_size = 0;
 	u16 total_memory_banks;
 	int err;
-#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB)
-	u8 board_rev;
-#endif
 
 	err = fdt_increase_size(blob, 512);
 	if (err) {
@@ -825,8 +838,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	fdt_fixup_icid(blob);
 
 #if IS_ENABLED(CONFIG_TARGET_LX2160ARDB)
-	board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A';
-	if (board_rev == 'C')
+	if (get_board_rev() == 'C')
 		fdt_fixup_i2c_thermal_node(blob);
 #endif
 
diff --git a/board/freescale/lx2160a/lx2160a.h b/board/freescale/lx2160a/lx2160a.h
index 52b020765d..61a8bb9590 100644
--- a/board/freescale/lx2160a/lx2160a.h
+++ b/board/freescale/lx2160a/lx2160a.h
@@ -58,4 +58,19 @@
 #endif
 #endif
 
+#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB)
+u8 get_board_rev(void);
+int fdt_fixup_board_phy_revc(void *fdt);
+#else
+static inline u8 get_board_rev(void)
+{
+	return 0;
+}
+
+static inline int fdt_fixup_board_phy_revc(void *fdt)
+{
+	return 0;
+}
+#endif
+
 #endif /* __LX2160_H */
diff --git a/board/freescale/m5208evbe/MAINTAINERS b/board/freescale/m5208evbe/MAINTAINERS
index c9c3c882e6..ff153034a4 100644
--- a/board/freescale/m5208evbe/MAINTAINERS
+++ b/board/freescale/m5208evbe/MAINTAINERS
@@ -1,5 +1,5 @@
 M5208EVBE BOARD
-#M:	-
+M:      Angelo Dureghello <angelo@kernel-space.org>
 S:	Maintained
 F:	board/freescale/m5208evbe/
 F:	include/configs/M5208EVBE.h
diff --git a/board/freescale/m5249evb/MAINTAINERS b/board/freescale/m5249evb/MAINTAINERS
index c2273c35e1..619e0cd20d 100644
--- a/board/freescale/m5249evb/MAINTAINERS
+++ b/board/freescale/m5249evb/MAINTAINERS
@@ -1,5 +1,5 @@
 M5249EVB BOARD
-#M:	-
+M:      Angelo Dureghello <angelo@kernel-space.org>
 S:	Maintained
 F:	board/freescale/m5249evb/
 F:	include/configs/M5249EVB.h
diff --git a/board/freescale/m5272c3/MAINTAINERS b/board/freescale/m5272c3/MAINTAINERS
index e58663096d..692ab5b582 100644
--- a/board/freescale/m5272c3/MAINTAINERS
+++ b/board/freescale/m5272c3/MAINTAINERS
@@ -1,5 +1,5 @@
 M5272C3 BOARD
-#M:	-
+M:      Angelo Dureghello <angelo@kernel-space.org>
 S:	Maintained
 F:	board/freescale/m5272c3/
 F:	include/configs/M5272C3.h
diff --git a/board/freescale/m5275evb/MAINTAINERS b/board/freescale/m5275evb/MAINTAINERS
index 4e6dbb12d9..065ae7bb1d 100644
--- a/board/freescale/m5275evb/MAINTAINERS
+++ b/board/freescale/m5275evb/MAINTAINERS
@@ -1,5 +1,5 @@
 M5275EVB BOARD
-#M:	-
+M:      Angelo Dureghello <angelo@kernel-space.org>
 S:	Maintained
 F:	board/freescale/m5275evb/
 F:	include/configs/M5275EVB.h
diff --git a/board/freescale/m5282evb/MAINTAINERS b/board/freescale/m5282evb/MAINTAINERS
index 305e748e74..f141c89c3a 100644
--- a/board/freescale/m5282evb/MAINTAINERS
+++ b/board/freescale/m5282evb/MAINTAINERS
@@ -1,5 +1,5 @@
 M5282EVB BOARD
-#M:	-
+M:      Angelo Dureghello <angelo@kernel-space.org>
 S:	Maintained
 F:	board/freescale/m5282evb/
 F:	include/configs/M5282EVB.h
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index 2777ae13bc..cff2e6a871 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -292,6 +292,7 @@ int power_init_board(void)
 int board_late_init(void)
 {
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+	unsigned char eth1addr[6];
 
 	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 
@@ -303,6 +304,11 @@ int board_late_init(void)
 	 */
 	clrsetbits_le16(&wdog->wcr, 0, 0x10);
 
+	/* Get the second MAC address */
+	imx_get_mac_from_fuse(1, eth1addr);
+	if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
+		eth_env_set_enetaddr("eth1addr", eth1addr);
+
 	return 0;
 }
 
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index baa59615b3..73f9d3ac72 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2023 NXP
  */
 
 #include <common.h>
@@ -20,6 +20,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_liodn.h>
+#include <clock_legacy.h>
 #include <fm_eth.h>
 #include "t102xrdb.h"
 #ifdef CONFIG_TARGET_T1024RDB
@@ -45,6 +46,13 @@ enum {
 };
 #endif
 
+#if CONFIG_IS_ENABLED(DM_SERIAL)
+int get_serial_clock(void)
+{
+	return get_bus_freq(0) / 2;
+}
+#endif
+
 int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
@@ -159,6 +167,8 @@ int board_early_init_r(void)
 	board_mux_lane();
 #endif
 
+	pci_init();
+
 	return 0;
 }
 
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
index 4e82f7f2ee..55fdb600a1 100644
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -24,8 +24,3 @@ F:	configs/T1040RDB_SDCARD_defconfig
 F:	configs/T1040D4RDB_SDCARD_defconfig
 F:	configs/T1042D4RDB_SDCARD_defconfig
 F:	configs/T1042RDB_PI_SDCARD_defconfig
-
-T1042D4RDB_SECURE_BOOT BOARD
-M:	Ruchika Gupta <ruchika.gupta@nxp.com>
-S:	Maintained
-F:	configs/T1042D4RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 8cec71217a..b308049271 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2023 NXP
  */
 
 #include <common.h>
@@ -22,6 +23,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_liodn.h>
+#include <clock_legacy.h>
 #include <fm_eth.h>
 #include "../common/sleep.h"
 #include "t104xrdb.h"
@@ -29,6 +31,13 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if CONFIG_IS_ENABLED(DM_SERIAL)
+int get_serial_clock(void)
+{
+	return get_bus_freq(0) / 2;
+}
+#endif
+
 int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
@@ -88,6 +97,9 @@ int board_early_init_r(void)
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 #endif
+
+	pci_init();
+
 	return 0;
 }
 
diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS
index 6e9b25fa04..5be7a25c03 100644
--- a/board/freescale/t208xrdb/MAINTAINERS
+++ b/board/freescale/t208xrdb/MAINTAINERS
@@ -12,8 +12,3 @@ F:	configs/T2080RDB_revD_defconfig
 F:	configs/T2080RDB_revD_NAND_defconfig
 F:	configs/T2080RDB_revD_SDCARD_defconfig
 F:	configs/T2080RDB_revD_SPIFLASH_defconfig
-
-T2080RDB_SECURE_BOOT BOARD
-M:	Ruchika Gupta <ruchika.gupta@nxp.com>
-S:	Maintained
-F:	configs/T2080RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index 04cb313e8c..e33e5d082d 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2013 Freescale Semiconductor, Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2023 NXP
  */
 
 #include <common.h>
@@ -20,6 +20,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_liodn.h>
+#include <clock_legacy.h>
 #include <fm_eth.h>
 #include "t208xrdb.h"
 #include "cpld.h"
@@ -42,6 +43,13 @@ u8 get_hw_revision(void)
 	}
 }
 
+#if CONFIG_IS_ENABLED(DM_SERIAL)
+int get_serial_clock(void)
+{
+	return get_bus_freq(0) / 2;
+}
+#endif
+
 int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
@@ -106,6 +114,9 @@ int board_early_init_r(void)
 	 */
 	if (adjust_vdd(0))
 		printf("Warning: Adjusting core voltage failed.\n");
+
+	pci_init();
+
 	return 0;
 }
 
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index 0bd0ba9396..ab717769ed 100644
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2023 NXP
  */
 
 #include <common.h>
@@ -20,6 +21,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_liodn.h>
+#include <clock_legacy.h>
 #include <fm_eth.h>
 
 #include "t4rdb.h"
@@ -28,6 +30,13 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if CONFIG_IS_ENABLED(DM_SERIAL)
+int get_serial_clock(void)
+{
+	return get_bus_freq(0) / 2;
+}
+#endif
+
 int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
@@ -86,6 +95,8 @@ int board_early_init_r(void)
 	if (adjust_vdd(0))
 		printf("Warning: Adjusting core voltage failed.\n");
 
+	pci_init();
+
 	return 0;
 }
 
diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c
index 6aea60ad05..241be4ee63 100644
--- a/board/gateworks/venice/eeprom.c
+++ b/board/gateworks/venice/eeprom.c
@@ -218,6 +218,11 @@ const char *eeprom_get_dtb_name(int level, char *buf, int sz)
 		int rev_base_bom = get_bom_rev(base_info.model);
 
 		snprintf(buf, sz, "%s%2dxx-%dx", pre, base, som);
+		/* GW79xx baseboards have no build options */
+		if (base == 79) {
+			base = (int)strtoul(base_info.model + 2, NULL, 10);
+			snprintf(buf, sz, "%s%4d-%dx", pre, base, som);
+		}
 		switch (level) {
 		case 0: /* full model (ie gw73xx-0x-a1a1) */
 			if (rev_base_bom)
diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h
index 62b860610c..d19902f10e 100644
--- a/board/gateworks/venice/lpddr4_timing.h
+++ b/board/gateworks/venice/lpddr4_timing.h
@@ -16,6 +16,7 @@ extern struct dram_timing_info dram_timing_1gb_single_die;
 extern struct dram_timing_info dram_timing_2gb_single_die;
 extern struct dram_timing_info dram_timing_2gb_dual_die;
 #elif CONFIG_IMX8MP
+extern struct dram_timing_info dram_timing_1gb_single_die;
 extern struct dram_timing_info dram_timing_4gb_dual_die;
 #endif
 
diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c
index 2e96332f8b..7bfd1b556b 100644
--- a/board/gateworks/venice/lpddr4_timing_imx8mp.c
+++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c
@@ -1315,6 +1315,538 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 };
 
 /*
+ * Generated code from MX8M_DDR_tool v3.30 using MX8MP Plus RPAv9
+ * - 1GiB: ixm8mp-gw7020 1x Micron MT53E256M32D2DS 2-ch single-die per channel
+ */
+struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400020, 0x1203 },
+	{ 0x3d400024, 0x16e3600 },
+	{ 0x3d400064, 0x5b0087 },
+	{ 0x3d400070, 0x7027f90 },
+	{ 0x3d400074, 0x790 },
+	{ 0x3d4000d0, 0xc00305ba },
+	{ 0x3d4000d4, 0x940000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x660048 },
+	{ 0x3d4000ec, 0x160048 },
+	{ 0x3d400100, 0x191e1920 },
+	{ 0x3d400104, 0x60630 },
+	{ 0x3d40010c, 0xb0b000 },
+	{ 0x3d400110, 0xe04080e },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x402 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0x8d },
+	{ 0x3d400144, 0x96004b },
+	{ 0x3d400180, 0x2ee0017 },
+	{ 0x3d400184, 0x2605b8e },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0x699 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d400208, 0x0 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0xf070707 },
+	{ 0x3d40021c, 0xf0f },
+	{ 0x3d400250, 0x1705 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400404, 0x72ff },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x1001 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d000 },
+	{ 0x3d402064, 0xc0012 },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x330000 },
+	{ 0x3d4020e8, 0x660048 },
+	{ 0x3d4020ec, 0x160048 },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x302 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x13 },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0x599 },
+	{ 0x3d403020, 0x1001 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d000 },
+	{ 0x3d403064, 0x30005 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x330000 },
+	{ 0x3d4030e8, 0x660048 },
+	{ 0x3d4030ec, 0x160048 },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x302 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x5 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0x599 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x3 },
+	{ 0x100a3, 0x2 },
+	{ 0x100a4, 0x5 },
+	{ 0x100a5, 0x4 },
+	{ 0x100a6, 0x7 },
+	{ 0x100a7, 0x6 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x2 },
+	{ 0x110a3, 0x3 },
+	{ 0x110a4, 0x4 },
+	{ 0x110a5, 0x5 },
+	{ 0x110a6, 0x6 },
+	{ 0x110a7, 0x7 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x2 },
+	{ 0x120a3, 0x3 },
+	{ 0x120a4, 0x4 },
+	{ 0x120a5, 0x5 },
+	{ 0x120a6, 0x6 },
+	{ 0x120a7, 0x7 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x3 },
+	{ 0x130a3, 0x4 },
+	{ 0x130a4, 0x5 },
+	{ 0x130a5, 0x2 },
+	{ 0x130a6, 0x7 },
+	{ 0x130a7, 0x6 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x2ee },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x1204a, 0x500 },
+	{ 0x1304a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg_1gb_single_die[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg_1gb_single_die[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg_1gb_single_die,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1gb_single_die),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg_1gb_single_die,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_1gb_single_die),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg_1gb_single_die,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1gb_single_die),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg_1gb_single_die,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1gb_single_die),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_1gb_single_die = {
+	.ddrc_cfg = ddr_ddrc_cfg_1gb_single_die,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die),
+	.ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg_1gb_single_die),
+	.fsp_msg = ddr_dram_fsp_msg_1gb_single_die,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_1gb_single_die),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
+
+/*
  * Generated code from MX8M_DDR_tool v3.30 using MX8M Plus RPAv7
  * - 4GiB: imx8mp-gw7401 1x Micron MT53D1024M32D4DT 2-ch dual-die per channel
  */
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index 4eb7bdfcee..5aa209578b 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -71,6 +71,9 @@ static void spl_dram_init(int size)
 		dram_timing = &dram_timing_2gb_dual_die;
 		size = 2048;
 #elif CONFIG_IMX8MP
+	case 1024:
+		dram_timing = &dram_timing_1gb_single_die;
+		break;
 	case 4096:
 		dram_timing = &dram_timing_4gb_dual_die;
 		break;
@@ -83,9 +86,12 @@ static void spl_dram_init(int size)
 
 	printf("DRAM    : LPDDR4 ");
 	if (size > 512)
-		printf("%d GiB\n", size / 1024);
+		printf("%d GiB", size / 1024);
 	else
-		printf("%d MiB\n", size);
+		printf("%d MiB", size);
+	printf(" %dMT/s %dMHz\n",
+	       dram_timing->fsp_msg[0].drate,
+	       dram_timing->fsp_msg[0].drate / 2);
 	ddr_init(dram_timing);
 }
 
@@ -121,7 +127,8 @@ static int power_init_board(void)
 
 	if ((!strncmp(model, "GW71", 4)) ||
 	    (!strncmp(model, "GW72", 4)) ||
-	    (!strncmp(model, "GW73", 4))) {
+	    (!strncmp(model, "GW73", 4)) ||
+	    (!strncmp(model, "GW7905", 6))) {
 		ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
 		if (ret) {
 			printf("PMIC    : failed I2C1 probe: %d\n", ret);
@@ -132,11 +139,22 @@ static int power_init_board(void)
 			printf("PMIC    : failed probe: %d\n", ret);
 			return ret;
 		}
-		puts("PMIC    : MP5416\n");
+#ifdef CONFIG_IMX8MM
+		puts("PMIC    : MP5416 (IMX8MM)\n");
 
 		/* set VDD_ARM SW3 to 0.92V for 1.6GHz */
 		dm_i2c_reg_write(dev, MP5416_VSET_SW3,
 				 BIT(7) | MP5416_VSET_SW3_SVAL(920000));
+#elif CONFIG_IMX8MP
+		puts("PMIC    : MP5416 (IMX8MP)\n");
+
+		/* set VDD_ARM SW3 to 0.95V for 1.6GHz */
+		dm_i2c_reg_write(dev, MP5416_VSET_SW3,
+				 BIT(7) | MP5416_VSET_SW3_SVAL(950000));
+		/* set VDD_SOC SW1 to 0.95V for 1.6GHz */
+		dm_i2c_reg_write(dev, MP5416_VSET_SW1,
+				 BIT(7) | MP5416_VSET_SW1_SVAL(950000));
+#endif
 	}
 
 	else if (!strncmp(model, "GW74", 4)) {
@@ -327,6 +345,21 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
 	}
 }
 
+unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect)
+{
+	if (!IS_SD(mmc)) {
+		switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
+		case 1:
+		case 2:
+			if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP))
+				raw_sect -= 32 * 2;
+			break;
+		}
+	}
+
+	return raw_sect;
+}
+
 const char *spl_board_loader_name(u32 boot_device)
 {
 	switch (boot_device) {
@@ -340,3 +373,8 @@ const char *spl_board_loader_name(u32 boot_device)
 		return NULL;
 	}
 }
+
+void spl_board_init(void)
+{
+	arch_misc_init();
+}
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index ca62f0be6d..a39ae58c8a 100644
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -6,9 +6,12 @@
 #include <fdt_support.h>
 #include <init.h>
 #include <led.h>
+#include <mmc.h>
 #include <miiphy.h>
+#include <mmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
 
 #include "eeprom.h"
 
@@ -17,7 +20,7 @@ int board_phys_sdram_size(phys_size_t *size)
 	if (!size)
 		return -EINVAL;
 
-	*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+	*size = get_ram_size((void *)PHYS_SDRAM, (long)PHYS_SDRAM_SIZE + (long)PHYS_SDRAM_2_SIZE);
 
 	return 0;
 }
@@ -93,10 +96,12 @@ int board_init(void)
 int board_late_init(void)
 {
 	const char *str;
+	struct mmc *mmc = NULL;
 	char env[32];
 	int ret, i;
 	u8 enetaddr[6];
 	char fdt[64];
+	int bootdev;
 
 	/* Set board serial/model */
 	if (!env_get("serial#"))
@@ -131,6 +136,74 @@ int board_late_init(void)
 		i++;
 	} while (!ret);
 
+	/*
+	 * set bootdev/bootblk/bootpart (used in firmware_update script)
+	 * dynamically depending on boot device and SoC
+	 */
+	bootdev = -1;
+	switch (get_boot_device()) {
+	case SD1_BOOT:
+	case MMC1_BOOT: /* SDHC1 */
+		bootdev = 0;
+		break;
+	case SD2_BOOT:
+	case MMC2_BOOT: /* SDHC2 */
+		bootdev = 1;
+		break;
+	case SD3_BOOT:
+	case MMC3_BOOT: /* SDHC3 */
+		bootdev = 2;
+		break;
+	default:
+		bootdev = 2; /* assume SDHC3 (eMMC) if booting over SDP */
+		break;
+	}
+	if (bootdev != -1)
+		mmc = find_mmc_device(bootdev);
+	if (mmc) {
+		int bootblk;
+
+		if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP))
+			bootblk = 32 * SZ_1K / 512;
+		else
+			bootblk = 33 * SZ_1K / 512;
+		mmc_init(mmc);
+		if (!IS_SD(mmc)) {
+			int bootpart;
+
+			switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
+			case 1: /* boot0 */
+				bootpart = 1;
+				break;
+			case 2: /* boot1 */
+				bootpart = 2;
+				break;
+			case 7: /* user */
+			default:
+				bootpart = 0;
+				break;
+			}
+			/* IMX8MP/IMX8MN BOOTROM v2 uses offset=0 for boot parts */
+			if ((IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) &&
+			    (bootpart == 1 || bootpart == 2))
+				bootblk = 0;
+			env_set_hex("bootpart", bootpart);
+			env_set_hex("bootblk", bootblk);
+		} else { /* SD */
+			env_set("bootpart", "");
+			env_set_hex("bootblk", bootblk);
+		}
+		env_set_hex("dev", bootdev);
+	}
+
+	/* override soc=imx8m to provide a more specific soc name */
+	if (IS_ENABLED(CONFIG_IMX8MN))
+		env_set("soc", "imx8mn");
+	else if (IS_ENABLED(CONFIG_IMX8MP))
+		env_set("soc", "imx8mp");
+	else if (IS_ENABLED(CONFIG_IMX8MM))
+		env_set("soc", "imx8mm");
+
 	return 0;
 }
 
@@ -139,6 +212,20 @@ int board_mmc_get_env_dev(int devno)
 	return devno;
 }
 
+uint mmc_get_env_part(struct mmc *mmc)
+{
+	if (!IS_SD(mmc)) {
+		switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
+		case 1:
+			return 1;
+		case 2:
+			return 2;
+		}
+	}
+
+	return 0;
+}
+
 int ft_board_setup(void *fdt, struct bd_info *bd)
 {
 	const char *base_model = eeprom_get_baseboard_model();
diff --git a/board/gateworks/venice/venice.env b/board/gateworks/venice/venice.env
index f81804ca12..a0d6c43325 100644
--- a/board/gateworks/venice/venice.env
+++ b/board/gateworks/venice/venice.env
@@ -8,11 +8,11 @@ bootm_size=0x10000000
 dev=2
 preboot=gsc wd-disable
 console=ttymxc1,115200
-update_firmware=tftpboot $loadaddr $image &&
+update_firmware=tftpboot $loadaddr $dir/venice-$soc-flash.bin &&
 	setexpr blkcnt $filesize + 0x1ff &&
 	setexpr blkcnt $blkcnt / 0x200 &&
-	mmc dev $dev &&
-	mmc write $loadaddr $splblk $blkcnt
+	mmc dev $dev $bootpart &&
+	mmc write $loadaddr $bootblk $blkcnt
 loadfdt=if $fsload $fdt_addr_r $dir/$fdt_file1;
 	then echo loaded $fdt_file1;
 	elif $fsload $fdt_addr_r $dir/$fdt_file2;
@@ -31,4 +31,3 @@ update_rootfs=tftpboot $loadaddr $image &&
 	gzwrite mmc $dev $loadaddr $filesize 100000 1000000
 update_all=tftpboot $loadaddr $image &&
 	gzwrite mmc $dev $loadaddr $filesize
-erase_env=mmc dev $dev; mmc erase 0x7f08 0x40
diff --git a/board/gdsys/a38x/MAINTAINERS b/board/gdsys/a38x/MAINTAINERS
index 6492e79541..bd8172065f 100644
--- a/board/gdsys/a38x/MAINTAINERS
+++ b/board/gdsys/a38x/MAINTAINERS
@@ -2,5 +2,6 @@ A38X BOARD
 M:	Mario Six <mario.six@gdsys.cc>
 S:	Maintained
 F:	board/gdsys/a38x/
+F:	board/gdsys/common/
 F:	include/configs/controlcenterdc.h
 F:	configs/controlcenterdc_defconfig
diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS
index 57faba4695..514cde521b 100644
--- a/board/gdsys/mpc8308/MAINTAINERS
+++ b/board/gdsys/mpc8308/MAINTAINERS
@@ -2,5 +2,6 @@ MPC8308 BOARD
 M:	Mario Six <mario.six@gdsys.cc>
 S:	Maintained
 F:	board/gdsys/mpc8308/
+F:	board/gdsys/common/
 F:	include/configs/gazerbeam.h
 F:	configs/gazerbeam_defconfig
diff --git a/board/google/Kconfig b/board/google/Kconfig
index a0f1a60976..e4f9b5b68a 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -4,13 +4,6 @@
 
 if VENDOR_GOOGLE
 
-config BIOSEMU
-	bool
-	select X86EMU_RAW_IO
-
-config X86EMU_RAW_IO
-	bool
-
 choice
 	prompt "Mainboard model"
 	optional
diff --git a/board/google/chromebox_panther/MAINTAINERS b/board/google/chromebox_panther/MAINTAINERS
index c88774bc86..4963a895bb 100644
--- a/board/google/chromebox_panther/MAINTAINERS
+++ b/board/google/chromebox_panther/MAINTAINERS
@@ -1,6 +1,6 @@
 CHROMEBOX PANTHER BOARD
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
-F:	board/google/chromebook_panther/
+F:	board/google/chromebox_panther/
 F:	include/configs/chromebox_panther.h
 F:	configs/chromebox_panther_defconfig
diff --git a/board/hardkernel/odroid_go2/MAINTAINERS b/board/hardkernel/odroid_go2/MAINTAINERS
index eab622a70b..4d4c6e8fef 100644
--- a/board/hardkernel/odroid_go2/MAINTAINERS
+++ b/board/hardkernel/odroid_go2/MAINTAINERS
@@ -1,6 +1,6 @@
 GO2
 M:      Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
 S:      Maintained
-F:      board/odroid/go2
+F:      board/hardkernel/odroid_go2/
 F:      include/configs/odroid_go2.h
 F:      configs/odroid-go2_defconfig
diff --git a/board/hardkernel/odroid_go2/go2.c b/board/hardkernel/odroid_go2/go2.c
index 29464ae63e..a0338ead3b 100644
--- a/board/hardkernel/odroid_go2/go2.c
+++ b/board/hardkernel/odroid_go2/go2.c
@@ -2,3 +2,106 @@
 /*
  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  */
+
+#include <linux/stddef.h>
+#include <adc.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <env.h>
+#include <stdlib.h>
+
+#define DTB_DIR			"rockchip/"
+
+struct oga_model {
+	const u16 adc_value;
+	const char *board;
+	const char *board_name;
+	const char *fdtfile;
+};
+
+enum oga_device_id {
+	OGA,
+	OGA_V11,
+	OGS,
+};
+
+/*
+ * All ADC values from schematic of Odroid Go Advance Black Edition.
+ * Value for OGS is inferred based on schematic and observed values.
+ */
+static const struct oga_model oga_model_details[] = {
+	[OGA] = {
+		856,
+		"rk3326-odroid-go2",
+		"ODROID-GO Advance",
+		DTB_DIR "rk3326-odroid-go2.dtb",
+	},
+	[OGA_V11] = {
+		677,
+		"rk3326-odroid-go2-v11",
+		"ODROID-GO Advance Black Edition",
+		DTB_DIR "rk3326-odroid-go2-v11.dtb",
+	},
+	[OGS] = {
+		85,
+		"rk3326-odroid-go3",
+		"ODROID-GO Super",
+		DTB_DIR "rk3326-odroid-go3.dtb",
+	},
+};
+
+/* Detect which Odroid Go Advance device we are using so as to load the
+ * correct devicetree for Linux. Set an environment variable once
+ * found. The detection depends on the value of ADC channel 0.
+ */
+int oga_detect_device(void)
+{
+	u32 adc_info;
+	int ret, i;
+	int board_id = -ENXIO;
+
+	ret = adc_channel_single_shot("saradc@ff288000", 0, &adc_info);
+	if (ret) {
+		printf("Read SARADC failed with error %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * Get the correct device from the table. The ADC value is
+	 * determined by a resistor on ADC channel 0. The manufacturer
+	 * accounted for this with a 5% tolerance, so assume a +- value
+	 * of 50 should be enough.
+	 */
+	for (i = 0; i < ARRAY_SIZE(oga_model_details); i++) {
+		u32 adc_min = oga_model_details[i].adc_value - 50;
+		u32 adc_max = oga_model_details[i].adc_value + 50;
+
+		if (adc_min < adc_info && adc_max > adc_info) {
+			board_id = i;
+			break;
+		}
+	}
+
+	if (board_id < 0)
+		return board_id;
+
+	env_set("board", oga_model_details[board_id].board);
+	env_set("board_name",
+		oga_model_details[board_id].board_name);
+	env_set("fdtfile", oga_model_details[board_id].fdtfile);
+
+	return 0;
+}
+
+int rk_board_late_init(void)
+{
+	int ret;
+
+	ret = oga_detect_device();
+	if (ret) {
+		printf("Unable to detect device type: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
diff --git a/board/hardkernel/odroid_m1/Kconfig b/board/hardkernel/odroid_m1/Kconfig
new file mode 100644
index 0000000000..999c4944a8
--- /dev/null
+++ b/board/hardkernel/odroid_m1/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ODROID_M1_RK3568
+
+config SYS_BOARD
+	default "odroid_m1"
+
+config SYS_VENDOR
+	default "hardkernel"
+
+config SYS_CONFIG_NAME
+	default "odroid_m1"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/hardkernel/odroid_m1/MAINTAINERS b/board/hardkernel/odroid_m1/MAINTAINERS
new file mode 100644
index 0000000000..165d2d9674
--- /dev/null
+++ b/board/hardkernel/odroid_m1/MAINTAINERS
@@ -0,0 +1,8 @@
+ODROID-M1
+M:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	board/hardkernel/odroid_m1/
+F:	include/configs/odroid_m1.h
+F:	configs/odroid-m1-rk3568_defconfig
+F:	arch/arm/dts/rk3568-odroid-m1.dts
+F:	arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
diff --git a/board/hardkernel/odroid_m1/Makefile b/board/hardkernel/odroid_m1/Makefile
new file mode 100644
index 0000000000..ae8ea3d978
--- /dev/null
+++ b/board/hardkernel/odroid_m1/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	+= odroid_m1.o
diff --git a/board/hardkernel/odroid_m1/odroid_m1.c b/board/hardkernel/odroid_m1/odroid_m1.c
new file mode 100644
index 0000000000..4c027f2a7a
--- /dev/null
+++ b/board/hardkernel/odroid_m1/odroid_m1.c
@@ -0,0 +1 @@
+// SPDX-License-Identifier: GPL-2.0+
diff --git a/board/hisilicon/poplar/README b/board/hisilicon/poplar/README
index 99ed6ce295..77dcc3ba11 100644
--- a/board/hisilicon/poplar/README
+++ b/board/hisilicon/poplar/README
@@ -30,7 +30,7 @@ CONNECTORS  One connector for Smart Card One connector for TSI
 Note of warning:
 ================
 
-U-boot has a *strong* dependency with the l-loader and the arm trusted firmware
+U-Boot has a *strong* dependency with the l-loader and the arm trusted firmware
 repositories.
 
 The boot sequence is:
diff --git a/board/imgtec/boston/checkboard.c b/board/imgtec/boston/checkboard.c
index 1b8a47d254..c246a7b9d4 100644
--- a/board/imgtec/boston/checkboard.c
+++ b/board/imgtec/boston/checkboard.c
@@ -16,7 +16,7 @@ int checkboard(void)
 {
 	u32 changelist;
 
-	lowlevel_display("U-boot  ");
+	lowlevel_display("U-Boot  ");
 
 	printf("Board: MIPS Boston\n");
 
diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c
index 8532225dc0..cecf454011 100644
--- a/board/imgtec/boston/ddr.c
+++ b/board/imgtec/boston/ddr.c
@@ -23,7 +23,7 @@ int dram_init(void)
 	return 0;
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/intel/bayleybay/bayleybay.env b/board/intel/bayleybay/bayleybay.env
new file mode 100644
index 0000000000..89e1849fa8
--- /dev/null
+++ b/board/intel/bayleybay/bayleybay.env
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
+
+/* don't use i8042-kbd */
+stdin=serial,usbkbd
diff --git a/board/intel/cherryhill/cherryhill.env b/board/intel/cherryhill/cherryhill.env
new file mode 100644
index 0000000000..929b6a18a7
--- /dev/null
+++ b/board/intel/cherryhill/cherryhill.env
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
+
+/* don't use i8042-kbd */
+stdin=serial,usbkbd
diff --git a/board/intel/cougarcanyon2/cougarcanyon2.env b/board/intel/cougarcanyon2/cougarcanyon2.env
new file mode 100644
index 0000000000..6329b0f330
--- /dev/null
+++ b/board/intel/cougarcanyon2/cougarcanyon2.env
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
diff --git a/board/intel/crownbay/crownbay.env b/board/intel/crownbay/crownbay.env
new file mode 100644
index 0000000000..9e95414c00
--- /dev/null
+++ b/board/intel/crownbay/crownbay.env
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
diff --git a/board/intel/edison/edison.env b/board/intel/edison/edison.env
new file mode 100644
index 0000000000..c7d4de7b03
--- /dev/null
+++ b/board/intel/edison/edison.env
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Intel Corp.
+ */
+
+/* empty environment */
diff --git a/board/intel/galileo/galileo.env b/board/intel/galileo/galileo.env
new file mode 100644
index 0000000000..83e77bb300
--- /dev/null
+++ b/board/intel/galileo/galileo.env
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
+
+/* use just serial */
+stdin=serial
+stdout=serial
+stderr=serial
diff --git a/board/intel/minnowmax/minnowmax.env b/board/intel/minnowmax/minnowmax.env
new file mode 100644
index 0000000000..71f3607843
--- /dev/null
+++ b/board/intel/minnowmax/minnowmax.env
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Google, Inc
+ */
+
+#include <env/x86.env>
+
+/* don't use i8042-kbd */
+stdin=usbkbd,serial
+
+usb_pgood_delay=40
diff --git a/board/intel/slimbootloader/slimbootloader.env b/board/intel/slimbootloader/slimbootloader.env
new file mode 100644
index 0000000000..3fce487d16
--- /dev/null
+++ b/board/intel/slimbootloader/slimbootloader.env
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <env/x86.env>
+
+/* don't use video */
+stdout=serial
+stderr=serial
+
+usb_pgood_delay=40
+
+ramdiskaddr=0x4000000
+ramdiskfile=initrd
+bootdev=usb
+bootdevnum=0
+bootdevpart=0
+bootfsload=fatload
+bootusb=setenv bootdev usb; boot
+bootscsi=setenv bootdev scsi; boot
+bootmmc=setenv bootdev mmc; boot
+bootargs=console=ttyS0,115200 console=tty0
diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c
index 5462a3dea2..7dbb080089 100644
--- a/board/isee/igep003x/board.c
+++ b/board/isee/igep003x/board.c
@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
  * and control IGEP0034 green and red LEDs.
- * U-boot configures these pins as input pullup to detect board revision:
+ * U-Boot configures these pins as input pullup to detect board revision:
  * IGEP0034-LITE = 0b00
  * IGEP0034 (FULL) = 0b01
  * IGEP0033 = 0b1X
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index f1599306e6..0f0a9c592f 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -47,7 +47,7 @@ U_BOOT_DRVINFO(igep_uart) = {
  * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from
  * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because
  * this functionality is shared by USB HOST.
- * Once USB reset is applied, U-boot configures these pins as input pullup to
+ * Once USB reset is applied, U-Boot configures these pins as input pullup to
  * detect board and revision:
  * IGEP0020-RF = 0b00
  * IGEP0020-RC = 0b01
diff --git a/board/k+p/kp_imx53/MAINTAINERS b/board/k+p/kp_imx53/MAINTAINERS
index c105a93e70..daf861160a 100644
--- a/board/k+p/kp_imx53/MAINTAINERS
+++ b/board/k+p/kp_imx53/MAINTAINERS
@@ -1,6 +1,7 @@
 KP_IMX53_HSC BOARD
 M:	Lukasz Majewski <lukma@denx.de>
 S:	Maintained
-F:	board/k+p/kp_imx53/
+F:	board/k\+p/kp_imx53/
+F:	board/k\+p/bootscripts/tpcboot.cmd
 F:	include/configs/kp_imx53.h
 F:	configs/kp_imx53_defconfig
diff --git a/board/k+p/kp_imx6q_tpc/MAINTAINERS b/board/k+p/kp_imx6q_tpc/MAINTAINERS
index 6c4c8dd28e..e54f4604c3 100644
--- a/board/k+p/kp_imx6q_tpc/MAINTAINERS
+++ b/board/k+p/kp_imx6q_tpc/MAINTAINERS
@@ -1,6 +1,7 @@
 KP_IMX6Q_TPC BOARD
 M:	Lukasz Majewski <lukma@denx.de>
 S:	Maintained
-F:	board/k+p/kp_imx6q_tpc/
+F:	board/k\+p/kp_imx6q_tpc/
+F:	board/k\+p/bootscripts/tpcboot.cmd
 F:	include/configs/kp_imx6q_tpc.h
 F:	configs/kp_imx6q_tpc_defconfig
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index bf899d005c..c6576aa652 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -123,7 +123,7 @@ config SYS_IVM_EEPROM_PAGE_LEN
 	  Page size of inventory in EEPROM.
 
 config PG_WCOM_UBOOT_UPDATE_SUPPORTED
-	bool "Enable U-boot Field Fail-Safe Update Functionality"
+	bool "Enable U-Boot Field Fail-Safe Update Functionality"
 	select EVENT
 	default n
 	help
@@ -132,7 +132,7 @@ config PG_WCOM_UBOOT_UPDATE_SUPPORTED
 	  from parallel NOR flash.
 
 config PG_WCOM_UBOOT_BOOTPACKAGE
-	bool "U-boot Is Part Of Factory Boot-Package Image"
+	bool "U-Boot Is Part Of Factory Boot-Package Image"
 	default n
 	help
 	  Indicates that u-boot will be a part of the factory programmed
@@ -140,7 +140,7 @@ config PG_WCOM_UBOOT_BOOTPACKAGE
 	  Has to be set for original u-boot programmed at factory.
 
 config PG_WCOM_UBOOT_UPDATE_TEXT_BASE
-	hex "Text Base For U-boot Programmed Outside Factory"
+	hex "Text Base For U-Boot Programmed Outside Factory"
 	default 0xFFFFFFFF
 	help
 	  Text base of an updated u-boot that is not factory programmed but
@@ -148,7 +148,7 @@ config PG_WCOM_UBOOT_UPDATE_TEXT_BASE
 	  Has to be set for original u-boot programmed at factory.
 
 config PG_WCOM_UBOOT_UPDATE
-	bool "U-boot Is Part Of Factory Boot-Package Image"
+	bool "U-Boot Is Part Of Factory Boot-Package Image"
 	default n
 	help
 	  Indicates that u-boot will be a part of the embedded software and
diff --git a/board/keymile/README b/board/keymile/README
index 4e5cfb142a..99f27e576a 100644
--- a/board/keymile/README
+++ b/board/keymile/README
@@ -1,4 +1,4 @@
-Field Fail-Save U-boot Update
+Field Fail-Save U-Boot Update
 -----------------------------
 Field Fail-Save u-boot update is a feature that allows save u-boot update
 of FOX and XMC products that are rolled out in the field.
diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS
index ac1f8cbd88..8822e5d915 100644
--- a/board/keymile/km83xx/MAINTAINERS
+++ b/board/keymile/km83xx/MAINTAINERS
@@ -3,6 +3,8 @@ M:	Holger Brunck <holger.brunck@hitachienergy.com>
 M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 F:	board/keymile/km83xx/
+F:	board/keymile/common/
+F:	board/keymile/scripts/
 F:	include/configs/km8360.h
 F:	configs/kmcoge5ne_defconfig
 F:	configs/kmeter1_defconfig
diff --git a/board/keymile/km83xx/km83xx.env b/board/keymile/km83xx/km83xx.env
index ed2487c028..1f13aaa882 100644
--- a/board/keymile/km83xx/km83xx.env
+++ b/board/keymile/km83xx/km83xx.env
@@ -13,8 +13,8 @@ netdev=eth0
 uimage=uImage
 #endif
 
-#include <environment/pg-wcom/common.env>
-#include <environment/pg-wcom/powerpc.env>
+#include <env/pg-wcom/common.env>
+#include <env/pg-wcom/powerpc.env>
 
 #if CONFIG_TARGET_KMCOGE5NE
 add_default+= eccmode=bch
diff --git a/board/keymile/kmcent2/MAINTAINERS b/board/keymile/kmcent2/MAINTAINERS
index 1426475556..1026188b94 100644
--- a/board/keymile/kmcent2/MAINTAINERS
+++ b/board/keymile/kmcent2/MAINTAINERS
@@ -2,6 +2,8 @@ KMCENT2 BOARD
 M:	Niel Fourie <lusus@denx.de>
 S:	Maintained
 F:	board/keymile/kmcent2/
+F:	board/keymile/common/
+F:	board/keymile/scripts/
 F:	include/configs/kmcent2.h
 F:	configs/kmcent2_defconfig
 F:	arch/powerpc/dts/kmcent2.dts
diff --git a/board/keymile/kmcent2/kmcent2.env b/board/keymile/kmcent2/kmcent2.env
index 6b676a4ceb..efa762e558 100644
--- a/board/keymile/kmcent2/kmcent2.env
+++ b/board/keymile/kmcent2/kmcent2.env
@@ -1,4 +1,4 @@
-#include <environment/pg-wcom/common.env>
+#include <env/pg-wcom/common.env>
 
 EEprom_ivm=pca9547:70:9
 arch=ppc_82xx
diff --git a/board/keymile/pg-wcom-ls102xa/MAINTAINERS b/board/keymile/pg-wcom-ls102xa/MAINTAINERS
index 33db2b2bea..ed5baf269a 100644
--- a/board/keymile/pg-wcom-ls102xa/MAINTAINERS
+++ b/board/keymile/pg-wcom-ls102xa/MAINTAINERS
@@ -3,6 +3,8 @@ M:	Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
 M:	Rainer Boschung <rainer.boschung@hitachienergy.com>
 S:	Maintained
 F:	board/keymile/pg-wcom-ls102xa/
+F:	board/keymile/common/
+F:	board/keymile/scripts/
 F:	include/configs/km/pg-wcom-ls102xa.h
 F:	include/configs/pg-wcom-seli8.h
 F:	include/configs/pg-wcom-expu1.h
diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env
index d960de6bfe..1054dbf9f5 100644
--- a/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env
+++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env
@@ -1,3 +1,3 @@
-#include <environment/pg-wcom/ls102xa.env>
+#include <env/pg-wcom/ls102xa.env>
 
 hostname=EXPU1
diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env
index 4031f8bee9..1232fe9da8 100644
--- a/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env
+++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env
@@ -1,3 +1,3 @@
-#include <environment/pg-wcom/ls102xa.env>
+#include <env/pg-wcom/ls102xa.env>
 
 hostname=SELI8
diff --git a/board/keymile/secu1/MAINTAINERS b/board/keymile/secu1/MAINTAINERS
index 833b3fdeab..e441f252aa 100644
--- a/board/keymile/secu1/MAINTAINERS
+++ b/board/keymile/secu1/MAINTAINERS
@@ -1,5 +1,8 @@
 Hitachi Power Grids SECU1 BOARD
 M:	Holger Brunck <holger.brunck@hitachienergy.com>
 S:	Maintained
+F:	board/keymile/secu1/
+F:	board/keymile/common/
+F:	board/keymile/scripts/
 F:	include/configs/socfpga_arria5_secu1.h
 F:	configs/socfpga_secu1_defconfig
diff --git a/board/kontron/pitx_imx8m/pitx_imx8m.c b/board/kontron/pitx_imx8m/pitx_imx8m.c
index fcda86bc1b..4548e7c1df 100644
--- a/board/kontron/pitx_imx8m/pitx_imx8m.c
+++ b/board/kontron/pitx_imx8m/pitx_imx8m.c
@@ -43,10 +43,10 @@ struct efi_fw_image fw_images[] = {
 
 struct efi_capsule_update_info update_info = {
 	.dfu_string = "mmc 0=flash-bin raw 0x42 0x1000 mmcpart 1",
+	.num_images = ARRAY_SIZE(fw_images),
 	.images = fw_images,
 };
 
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
 
 int board_early_init_f(void)
diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c
index bae0e70a65..a9d370bc85 100644
--- a/board/kontron/sl-mx6ul/spl.c
+++ b/board/kontron/sl-mx6ul/spl.c
@@ -101,7 +101,7 @@ int board_mmc_init(struct bd_info *bis)
 
 	/*
 	 * According to the board_mmc_init() the following map is done:
-	 * (U-boot device node)    (Physical Port)
+	 * (U-Boot device node)    (Physical Port)
 	 * mmc0                    USDHC1
 	 * mmc1                    USDHC2
 	 */
diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c
index 250195694b..8dcc2ea54f 100644
--- a/board/kontron/sl-mx8mm/sl-mx8mm.c
+++ b/board/kontron/sl-mx8mm/sl-mx8mm.c
@@ -29,15 +29,15 @@ struct efi_fw_image fw_images[] = {
 
 struct efi_capsule_update_info update_info = {
 	.dfu_string = "sf 0:0=flash-bin raw 0x400 0x1f0000",
+	.num_images = ARRAY_SIZE(fw_images),
 	.images = fw_images,
 };
 
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
 
 int board_phys_sdram_size(phys_size_t *size)
 {
-	u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR);
+	u32 ddr_size = readl(MCU_BOOTROM_BASE_ADDR);
 
 	if (ddr_size == 4) {
 		*size = 0x100000000;
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c
index 3a919d0a9c..b49373442a 100644
--- a/board/kontron/sl-mx8mm/spl.c
+++ b/board/kontron/sl-mx8mm/spl.c
@@ -106,7 +106,7 @@ static void spl_dram_init(void)
 	}
 
 	gd->ram_size = size;
-	writel(size, M4_BOOTROM_BASE_ADDR);
+	writel(size, MCU_BOOTROM_BASE_ADDR);
 }
 
 int do_board_detect(void)
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c
index 89948e087f..4ab221c12b 100644
--- a/board/kontron/sl28/sl28.c
+++ b/board/kontron/sl28/sl28.c
@@ -40,10 +40,10 @@ struct efi_fw_image fw_images[] = {
 struct efi_capsule_update_info update_info = {
 	.dfu_string = "sf 0:0=u-boot-bin raw 0x210000 0x1d0000;"
 			"u-boot-env raw 0x3e0000 0x20000",
+	.num_images = ARRAY_SIZE(fw_images),
 	.images = fw_images,
 };
 
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
 
 int board_early_init_f(void)
diff --git a/board/l+g/vinco/MAINTAINERS b/board/l+g/vinco/MAINTAINERS
index 0cd6044172..14b76b14d8 100644
--- a/board/l+g/vinco/MAINTAINERS
+++ b/board/l+g/vinco/MAINTAINERS
@@ -1,6 +1,6 @@
 VInCo Platform
 M:	Gregory CLEMENT <gregory.clement@free-electrons.com>
 S:	Maintained
-F:	board/l+g/vinco
+F:	board/l\+g/vinco/
 F:	include/configs/vinco.h
 F:	configs/vinco_defconfig
diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c
index 38e841c5f6..e4d2eb65cc 100644
--- a/board/liebherr/xea/xea.c
+++ b/board/liebherr/xea/xea.c
@@ -62,6 +62,7 @@ static void init_clocks(void)
 void board_init_f(ulong arg)
 {
 	init_clocks();
+	spl_early_init();
 	preloader_console_init();
 }
 
@@ -203,5 +204,22 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	return 0;
 }
 #endif
-
+/*
+ * NOTE:
+ *
+ * IMX28 clock "stub" DM driver!
+ *
+ * Only used for SPL stage, which is NOT using DM; serial and
+ * eMMC configuration.
+ */
+static const struct udevice_id imx28_clk_ids[] = {
+	{ .compatible = "fsl,imx28-clkctrl", },
+	{ }
+};
+
+U_BOOT_DRIVER(fsl_imx28_clkctrl) = {
+	.name           = "fsl_imx28_clkctrl",
+	.id             = UCLASS_CLK,
+	.of_match       = imx28_clk_ids,
+};
 #endif	/* CONFIG_SPL_BUILD */
diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c
index ff233e920a..2cc73bc35d 100644
--- a/board/mediatek/mt7622/mt7622_rfb.c
+++ b/board/mediatek/mt7622/mt7622_rfb.c
@@ -14,7 +14,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 	return 0;
 }
 
diff --git a/board/mediatek/mt7988/MAINTAINERS b/board/mediatek/mt7988/MAINTAINERS
new file mode 100644
index 0000000000..a45bfff26c
--- /dev/null
+++ b/board/mediatek/mt7988/MAINTAINERS
@@ -0,0 +1,7 @@
+MT7988
+M:	Sam Shih <sam.shih@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt7988
+F:	include/configs/mt7988.h
+F:	configs/mt7988_rfb_defconfig
+F:	configs/mt7988_sd_rfb_defconfig
diff --git a/board/mediatek/mt7988/Makefile b/board/mediatek/mt7988/Makefile
new file mode 100644
index 0000000000..f1249ab371
--- /dev/null
+++ b/board/mediatek/mt7988/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y	+= mt7988_rfb.o
diff --git a/board/mediatek/mt7988/mt7988_rfb.c b/board/mediatek/mt7988/mt7988_rfb.c
new file mode 100644
index 0000000000..846c715ca0
--- /dev/null
+++ b/board/mediatek/mt7988/mt7988_rfb.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c
index 14324c7087..b8dffb0e48 100644
--- a/board/menlo/m53menlo/m53menlo.c
+++ b/board/menlo/m53menlo/m53menlo.c
@@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static u32 mx53_dram_size[2];
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	/*
 	 * WARNING: We must override get_effective_memsize() function here
@@ -264,6 +264,7 @@ void board_preboot_os(void)
 	gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
 }
 
+#if CONFIG_IS_ENABLED(OF_LIBFDT)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
 	if (lvds_compat_string)
@@ -272,6 +273,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 
 	return 0;
 }
+#endif
 
 struct display_info_t const displays[] = {
 	{
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c
index e74c9fb03c..0f5f82924e 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -80,7 +80,7 @@ int board_late_init(void)
 	char icicle_mac_addr[20];
 	void *blob = (void *)gd->fdt_blob;
 
-	node = fdt_path_offset(blob, "ethernet0");
+	node = fdt_path_offset(blob, "/soc/ethernet@20112000");
 	if (node < 0) {
 		printf("No ethernet0 path offset\n");
 		return -ENODEV;
@@ -88,7 +88,7 @@ int board_late_init(void)
 
 	ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr, 6);
 	if (ret) {
-		printf("No local-mac-address property\n");
+		printf("No local-mac-address property for ethernet@20112000\n");
 		return -EINVAL;
 	}
 
@@ -104,7 +104,7 @@ int board_late_init(void)
 
 	ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
 	if (ret) {
-		printf("Error setting local-mac-address property\n");
+		printf("Error setting local-mac-address property for ethernet@20112000\n");
 		return -ENODEV;
 	}
 
@@ -123,6 +123,15 @@ int board_late_init(void)
 
 	mac_addr[5] = device_serial_number[0] + 1;
 
+	node = fdt_path_offset(blob, "/soc/ethernet@20110000");
+	if (node >= 0) {
+		ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+		if (ret) {
+			printf("Error setting local-mac-address property for ethernet@20110000\n");
+			return -ENODEV;
+		}
+	}
+
 	icicle_mac_addr[0] = '[';
 
 	sprintf(&icicle_mac_addr[1], "%pM", mac_addr);
diff --git a/board/nuvoton/arbel_evb/Kconfig b/board/nuvoton/arbel_evb/Kconfig
index efe85974a2..33c589f1fb 100644
--- a/board/nuvoton/arbel_evb/Kconfig
+++ b/board/nuvoton/arbel_evb/Kconfig
@@ -11,8 +11,8 @@ config SYS_CONFIG_NAME
 
 config SYS_MEM_TOP_HIDE
 	hex "Reserved TOP memory"
-	default 0xB000000
+	default 0x0
 	help
-	  Reserve memory for ECC/GFX/VCD/ECE.
+	  Reserve memory for ECC/GFX/OPTEE/TIP/CP.
 
 endif
diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c
index cd12ce3834..e52e0a59ab 100644
--- a/board/nuvoton/arbel_evb/arbel_evb.c
+++ b/board/nuvoton/arbel_evb/arbel_evb.c
@@ -8,6 +8,17 @@
 #include <asm/io.h>
 #include <asm/arch/gcr.h>
 
+#define SR_MII_CTRL_SWR_BIT15	15
+
+#define DRAM_512MB_ECC_SIZE	0x1C000000ULL
+#define DRAM_512MB_SIZE		0x20000000ULL
+#define DRAM_1GB_ECC_SIZE	0x38000000ULL
+#define DRAM_1GB_SIZE		0x40000000ULL
+#define DRAM_2GB_ECC_SIZE	0x70000000ULL
+#define DRAM_2GB_SIZE		0x80000000ULL
+#define DRAM_4GB_ECC_SIZE	0xE00000000ULL
+#define DRAM_4GB_SIZE		0x100000000ULL
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
@@ -18,12 +29,65 @@ int board_init(void)
 int dram_init(void)
 {
 	struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
+	uint64_t delta = 0ULL;
 
 	/*
-	 * Get dram size from bootblock.
-	 * The value is stored in scrpad_02 register.
+	 * get dram active size value from bootblock.
+	 * Value sent using scrpad_03 register.
+	 * feature available in bootblock 0.0.6 and above.
 	 */
-	gd->ram_size = readl(&gcr->scrpad_b);
+
+	gd->ram_size = readl(&gcr->scrpad_c);
+	debug("%s: scrpad_c: %llx ", __func__, gd->ram_size);
+
+	if (gd->ram_size == 0) {
+		gd->ram_size = readl(&gcr->scrpad_b);
+		debug("%s: scrpad_b: %llx ", __func__, gd->ram_size);
+	} else {
+		gd->ram_size *= 0x100000ULL;
+	}
+
+	gd->bd->bi_dram[0].start = 0;
+	debug("ram_size: %llx ", gd->ram_size);
+
+	switch (gd->ram_size) {
+	case DRAM_512MB_ECC_SIZE:
+	case DRAM_512MB_SIZE:
+	case DRAM_1GB_ECC_SIZE:
+	case DRAM_1GB_SIZE:
+	case DRAM_2GB_ECC_SIZE:
+	case DRAM_2GB_SIZE:
+		gd->bd->bi_dram[0].size = gd->ram_size;
+		gd->bd->bi_dram[1].start = 0;
+		gd->bd->bi_dram[1].size = 0;
+		break;
+	case DRAM_4GB_ECC_SIZE:
+		gd->bd->bi_dram[0].size = DRAM_2GB_ECC_SIZE;
+		gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
+		gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
+		delta = DRAM_4GB_SIZE - DRAM_2GB_ECC_SIZE;
+		break;
+	case DRAM_4GB_SIZE:
+		gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
+		gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
+		gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
+		delta = DRAM_4GB_SIZE - DRAM_2GB_SIZE;
+		break;
+	default:
+		gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
+		gd->bd->bi_dram[1].start = 0;
+		gd->bd->bi_dram[1].size = 0;
+		break;
+	}
+
+	gd->ram_size -= delta;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	dram_init();
 
 	return 0;
 }
diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c
index aef142a881..2052af6649 100644
--- a/board/nuvoton/poleg_evb/poleg_evb.c
+++ b/board/nuvoton/poleg_evb/poleg_evb.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <env.h>
 #include <asm/io.h>
 #include <asm/arch/gcr.h>
 #include <asm/mach-types.h>
@@ -19,6 +20,7 @@ int board_init(void)
 
 int dram_init(void)
 {
+	char value[32];
 	struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
 
 	int ramsize = (readl(&gcr->intcr3) >> 8) & 0x7;
@@ -44,5 +46,10 @@ int dram_init(void)
 	break;
 	}
 
+	if (gd->ram_size > 0) {
+                sprintf(value, "%ldM", (gd->ram_size / 0x100000));
+                env_set("mem", value);
+        }
+
 	return 0;
 }
diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig
index eb0db8a64c..21da1dc346 100644
--- a/board/openpiton/riscv64/Kconfig
+++ b/board/openpiton/riscv64/Kconfig
@@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SUPPORT_SPL
 	imply CPU_RISCV
 	imply RISCV_TIMER
-	imply SPL_SIFIVE_CLINT
+	imply SPL_RISCV_ACLINT
 	imply CMD_CPU
 	imply SPL_CPU_SUPPORT
 	imply SPL_SMP
diff --git a/board/phytec/pcm058/README b/board/phytec/pcm058/README
index 687366bffb..4b6984cd54 100644
--- a/board/phytec/pcm058/README
+++ b/board/phytec/pcm058/README
@@ -37,12 +37,12 @@ not supported.
 Flashing U-Boot onto an SD card
 -------------------------------
 
-After a successful build, the generated SPL and U-boot binaries can be copied
+After a successful build, the generated SPL and U-Boot binaries can be copied
 to an SD card. Adjust the SD card device as necessary:
 
 $ sudo dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=1k seek=1
 
-This is equivalent to separately copying the SPL and U-boot using:
+This is equivalent to separately copying the SPL and U-Boot using:
 
 $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1
 $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197
@@ -50,11 +50,11 @@ $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197
 The default bootscripts expect a kernel fit-image file named "fitImage" in the
 first partition and Linux ext4 rootfs in the second partition.
 
-Flashing U-boot to the SPI Flash, for booting Linux from NAND
+Flashing U-Boot to the SPI Flash, for booting Linux from NAND
 -------------------------------------------------------------
 
-The SD card created above can also be used to install the SPL and U-boot into
-the SPI flash. Boot U-boot from the SD card as above, and stop at the autoboot.
+The SD card created above can also be used to install the SPL and U-Boot into
+the SPI flash. Boot U-Boot from the SD card as above, and stop at the autoboot.
 
 Then, clear the SPI flash:
 
@@ -64,13 +64,13 @@ Then, clear the SPI flash:
 Load the equivalent of u-boot-with-spl.imx from the raw MMC into memory and
 copy to the SPI. The SPL is expected at an offset of 0x400, and its size is
 maximum 392*512-byte blocks in size, therefore 0x188 blocks, totaling 0x31000
-bytes. Assume U-boot should fit into 640KiB, therefore 0x500 512-byte blocks,
+bytes. Assume U-Boot should fit into 640KiB, therefore 0x500 512-byte blocks,
 totalling 0xA0000 bytes. Adding these together:
 
 => mmc read ${loadaddr} 0x2 0x688
 => sf write ${loadaddr} 0x400 0xD1000
 
-The SPL is located at offset 0x400, and U-boot at 0x31400 in SPI flash, as to
+The SPL is located at offset 0x400, and U-Boot at 0x31400 in SPI flash, as to
 match the SD Card layout. This would allow, instead of reading from the SD Card
 above, with networking and TFTP correctly configured, the equivalent of:
 
@@ -84,7 +84,7 @@ image) and "root" (which contains a ubifs root filesystem).
 The "bootm_size" variable in the environment
 --------------------------------------------
 
-By default, U-boot relocates the device tree towards the upper end of the RAM,
+By default, U-Boot relocates the device tree towards the upper end of the RAM,
 which kernels using CONFIG_HIGHMEM=y may not be able to access during early
-boot. With the bootm_size variable set to 0x30000000, U-boot relocates the
+boot. With the bootm_size variable set to 0x30000000, U-Boot relocates the
 device tree to below this address instead.
diff --git a/board/phytec/phycore_imx8mm/lpddr4_timing.c b/board/phytec/phycore_imx8mm/lpddr4_timing.c
index 811ac26415..f5a2f3268b 100644
--- a/board/phytec/phycore_imx8mm/lpddr4_timing.c
+++ b/board/phytec/phycore_imx8mm/lpddr4_timing.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Copyright (C) 2020 PHYTEC Messtechnik GmbH
+ * Copyright 2019 NXP
+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH
  *
  * Generated code from MX8M_DDR_tool
  */
@@ -13,22 +14,22 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d400304, 0x1},
 	{0x3d400030, 0x1},
 	{0x3d400000, 0xa1080020},
-	{0x3d400020, 0x223},
+	{0x3d400020, 0x222},
 	{0x3d400024, 0x3a980},
-	{0x3d400064, 0x5b00d2},
+	{0x3d400064, 0x2d00d2},
 	{0x3d4000d0, 0xc00305ba},
 	{0x3d4000d4, 0x940000},
 	{0x3d4000dc, 0xd4002d},
 	{0x3d4000e0, 0x310000},
 	{0x3d4000e8, 0x66004d},
 	{0x3d4000ec, 0x16004d},
-	{0x3d400100, 0x191e1920},
+	{0x3d400100, 0x191e0c20},
 	{0x3d400104, 0x60630},
 	{0x3d40010c, 0xb0b000},
 	{0x3d400110, 0xe04080e},
 	{0x3d400114, 0x2040c0c},
 	{0x3d400118, 0x1010007},
-	{0x3d40011c, 0x401},
+	{0x3d40011c, 0x402},
 	{0x3d400130, 0x20600},
 	{0x3d400134, 0xc100002},
 	{0x3d400138, 0xd8},
@@ -45,7 +46,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d4001b0, 0x11},
 	{0x3d4001c0, 0x1},
 	{0x3d4001c4, 0x1},
-	{0x3d4000f4, 0xc99},
+	{0x3d4000f4, 0x699},
 	{0x3d400108, 0x70e1617},
 	{0x3d400200, 0x1f},
 	{0x3d40020c, 0x0},
@@ -53,6 +54,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d400204, 0x80808},
 	{0x3d400214, 0x7070707},
 	{0x3d400218, 0x7070707},
+	{0x3d40021c, 0xf0f},
 	{0x3d400250, 0x29001701},
 	{0x3d400254, 0x2c},
 	{0x3d40025c, 0x4000030},
@@ -64,22 +66,22 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d400498, 0x620096},
 	{0x3d40049c, 0x1100e07},
 	{0x3d4004a0, 0xc8012c},
-	{0x3d402020, 0x21},
+	{0x3d402020, 0x20},
 	{0x3d402024, 0x7d00},
 	{0x3d402050, 0x20d040},
-	{0x3d402064, 0xc001c},
+	{0x3d402064, 0x6001c},
 	{0x3d4020dc, 0x840000},
 	{0x3d4020e0, 0x310000},
 	{0x3d4020e8, 0x66004d},
 	{0x3d4020ec, 0x16004d},
-	{0x3d402100, 0xa040305},
+	{0x3d402100, 0xa040105},
 	{0x3d402104, 0x30407},
 	{0x3d402108, 0x203060b},
 	{0x3d40210c, 0x505000},
 	{0x3d402110, 0x2040202},
 	{0x3d402114, 0x2030202},
 	{0x3d402118, 0x1010004},
-	{0x3d40211c, 0x301},
+	{0x3d40211c, 0x302},
 	{0x3d402130, 0x20300},
 	{0x3d402134, 0xa100002},
 	{0x3d402138, 0x1d},
@@ -88,8 +90,8 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d402190, 0x3818200},
 	{0x3d402194, 0x80303},
 	{0x3d4021b4, 0x100},
-	{0x3d4020f4, 0xc99},
-	{0x3d403020, 0x21},
+	{0x3d4020f4, 0x599},
+	{0x3d403020, 0x20},
 	{0x3d403024, 0x1f40},
 	{0x3d403050, 0x20d040},
 	{0x3d403064, 0x30007},
@@ -104,7 +106,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d403110, 0x2040202},
 	{0x3d403114, 0x2030202},
 	{0x3d403118, 0x1010004},
-	{0x3d40311c, 0x301},
+	{0x3d40311c, 0x302},
 	{0x3d403130, 0x20300},
 	{0x3d403134, 0xa100002},
 	{0x3d403138, 0x8},
@@ -113,7 +115,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d403190, 0x3818200},
 	{0x3d403194, 0x80303},
 	{0x3d4031b4, 0x100},
-	{0x3d4030f4, 0xc99},
+	{0x3d4030f4, 0x599},
 	{0x3d400028, 0x0},
 };
 
@@ -201,8 +203,8 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{0x220024, 0x1ab},
 	{0x2003a, 0x0},
 	{0x20056, 0x3},
-	{0x120056, 0xa},
-	{0x220056, 0xa},
+	{0x120056, 0x3},
+	{0x220056, 0x3},
 	{0x1004d, 0xe00},
 	{0x1014d, 0xe00},
 	{0x1104d, 0xe00},
@@ -323,727 +325,726 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
 
 /* ddr phy trained csr */
 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
-	{ 0x200b2, 0x0 },
-	{ 0x1200b2, 0x0 },
-	{ 0x2200b2, 0x0 },
-	{ 0x200cb, 0x0 },
-	{ 0x10043, 0x0 },
-	{ 0x110043, 0x0 },
-	{ 0x210043, 0x0 },
-	{ 0x10143, 0x0 },
-	{ 0x110143, 0x0 },
-	{ 0x210143, 0x0 },
-	{ 0x11043, 0x0 },
-	{ 0x111043, 0x0 },
-	{ 0x211043, 0x0 },
-	{ 0x11143, 0x0 },
-	{ 0x111143, 0x0 },
-	{ 0x211143, 0x0 },
-	{ 0x12043, 0x0 },
-	{ 0x112043, 0x0 },
-	{ 0x212043, 0x0 },
-	{ 0x12143, 0x0 },
-	{ 0x112143, 0x0 },
-	{ 0x212143, 0x0 },
-	{ 0x13043, 0x0 },
-	{ 0x113043, 0x0 },
-	{ 0x213043, 0x0 },
-	{ 0x13143, 0x0 },
-	{ 0x113143, 0x0 },
-	{ 0x213143, 0x0 },
-	{ 0x80, 0x0 },
-	{ 0x100080, 0x0 },
-	{ 0x200080, 0x0 },
-	{ 0x1080, 0x0 },
-	{ 0x101080, 0x0 },
-	{ 0x201080, 0x0 },
-	{ 0x2080, 0x0 },
-	{ 0x102080, 0x0 },
-	{ 0x202080, 0x0 },
-	{ 0x3080, 0x0 },
-	{ 0x103080, 0x0 },
-	{ 0x203080, 0x0 },
-	{ 0x4080, 0x0 },
-	{ 0x104080, 0x0 },
-	{ 0x204080, 0x0 },
-	{ 0x5080, 0x0 },
-	{ 0x105080, 0x0 },
-	{ 0x205080, 0x0 },
-	{ 0x6080, 0x0 },
-	{ 0x106080, 0x0 },
-	{ 0x206080, 0x0 },
-	{ 0x7080, 0x0 },
-	{ 0x107080, 0x0 },
-	{ 0x207080, 0x0 },
-	{ 0x8080, 0x0 },
-	{ 0x108080, 0x0 },
-	{ 0x208080, 0x0 },
-	{ 0x9080, 0x0 },
-	{ 0x109080, 0x0 },
-	{ 0x209080, 0x0 },
-	{ 0x10080, 0x0 },
-	{ 0x110080, 0x0 },
-	{ 0x210080, 0x0 },
-	{ 0x10180, 0x0 },
-	{ 0x110180, 0x0 },
-	{ 0x210180, 0x0 },
-	{ 0x11080, 0x0 },
-	{ 0x111080, 0x0 },
-	{ 0x211080, 0x0 },
-	{ 0x11180, 0x0 },
-	{ 0x111180, 0x0 },
-	{ 0x211180, 0x0 },
-	{ 0x12080, 0x0 },
-	{ 0x112080, 0x0 },
-	{ 0x212080, 0x0 },
-	{ 0x12180, 0x0 },
-	{ 0x112180, 0x0 },
-	{ 0x212180, 0x0 },
-	{ 0x13080, 0x0 },
-	{ 0x113080, 0x0 },
-	{ 0x213080, 0x0 },
-	{ 0x13180, 0x0 },
-	{ 0x113180, 0x0 },
-	{ 0x213180, 0x0 },
-	{ 0x10081, 0x0 },
-	{ 0x110081, 0x0 },
-	{ 0x210081, 0x0 },
-	{ 0x10181, 0x0 },
-	{ 0x110181, 0x0 },
-	{ 0x210181, 0x0 },
-	{ 0x11081, 0x0 },
-	{ 0x111081, 0x0 },
-	{ 0x211081, 0x0 },
-	{ 0x11181, 0x0 },
-	{ 0x111181, 0x0 },
-	{ 0x211181, 0x0 },
-	{ 0x12081, 0x0 },
-	{ 0x112081, 0x0 },
-	{ 0x212081, 0x0 },
-	{ 0x12181, 0x0 },
-	{ 0x112181, 0x0 },
-	{ 0x212181, 0x0 },
-	{ 0x13081, 0x0 },
-	{ 0x113081, 0x0 },
-	{ 0x213081, 0x0 },
-	{ 0x13181, 0x0 },
-	{ 0x113181, 0x0 },
-	{ 0x213181, 0x0 },
-	{ 0x100d0, 0x0 },
-	{ 0x1100d0, 0x0 },
-	{ 0x2100d0, 0x0 },
-	{ 0x101d0, 0x0 },
-	{ 0x1101d0, 0x0 },
-	{ 0x2101d0, 0x0 },
-	{ 0x110d0, 0x0 },
-	{ 0x1110d0, 0x0 },
-	{ 0x2110d0, 0x0 },
-	{ 0x111d0, 0x0 },
-	{ 0x1111d0, 0x0 },
-	{ 0x2111d0, 0x0 },
-	{ 0x120d0, 0x0 },
-	{ 0x1120d0, 0x0 },
-	{ 0x2120d0, 0x0 },
-	{ 0x121d0, 0x0 },
-	{ 0x1121d0, 0x0 },
-	{ 0x2121d0, 0x0 },
-	{ 0x130d0, 0x0 },
-	{ 0x1130d0, 0x0 },
-	{ 0x2130d0, 0x0 },
-	{ 0x131d0, 0x0 },
-	{ 0x1131d0, 0x0 },
-	{ 0x2131d0, 0x0 },
-	{ 0x100d1, 0x0 },
-	{ 0x1100d1, 0x0 },
-	{ 0x2100d1, 0x0 },
-	{ 0x101d1, 0x0 },
-	{ 0x1101d1, 0x0 },
-	{ 0x2101d1, 0x0 },
-	{ 0x110d1, 0x0 },
-	{ 0x1110d1, 0x0 },
-	{ 0x2110d1, 0x0 },
-	{ 0x111d1, 0x0 },
-	{ 0x1111d1, 0x0 },
-	{ 0x2111d1, 0x0 },
-	{ 0x120d1, 0x0 },
-	{ 0x1120d1, 0x0 },
-	{ 0x2120d1, 0x0 },
-	{ 0x121d1, 0x0 },
-	{ 0x1121d1, 0x0 },
-	{ 0x2121d1, 0x0 },
-	{ 0x130d1, 0x0 },
-	{ 0x1130d1, 0x0 },
-	{ 0x2130d1, 0x0 },
-	{ 0x131d1, 0x0 },
-	{ 0x1131d1, 0x0 },
-	{ 0x2131d1, 0x0 },
-	{ 0x10068, 0x0 },
-	{ 0x10168, 0x0 },
-	{ 0x10268, 0x0 },
-	{ 0x10368, 0x0 },
-	{ 0x10468, 0x0 },
-	{ 0x10568, 0x0 },
-	{ 0x10668, 0x0 },
-	{ 0x10768, 0x0 },
-	{ 0x10868, 0x0 },
-	{ 0x11068, 0x0 },
-	{ 0x11168, 0x0 },
-	{ 0x11268, 0x0 },
-	{ 0x11368, 0x0 },
-	{ 0x11468, 0x0 },
-	{ 0x11568, 0x0 },
-	{ 0x11668, 0x0 },
-	{ 0x11768, 0x0 },
-	{ 0x11868, 0x0 },
-	{ 0x12068, 0x0 },
-	{ 0x12168, 0x0 },
-	{ 0x12268, 0x0 },
-	{ 0x12368, 0x0 },
-	{ 0x12468, 0x0 },
-	{ 0x12568, 0x0 },
-	{ 0x12668, 0x0 },
-	{ 0x12768, 0x0 },
-	{ 0x12868, 0x0 },
-	{ 0x13068, 0x0 },
-	{ 0x13168, 0x0 },
-	{ 0x13268, 0x0 },
-	{ 0x13368, 0x0 },
-	{ 0x13468, 0x0 },
-	{ 0x13568, 0x0 },
-	{ 0x13668, 0x0 },
-	{ 0x13768, 0x0 },
-	{ 0x13868, 0x0 },
-	{ 0x10069, 0x0 },
-	{ 0x10169, 0x0 },
-	{ 0x10269, 0x0 },
-	{ 0x10369, 0x0 },
-	{ 0x10469, 0x0 },
-	{ 0x10569, 0x0 },
-	{ 0x10669, 0x0 },
-	{ 0x10769, 0x0 },
-	{ 0x10869, 0x0 },
-	{ 0x11069, 0x0 },
-	{ 0x11169, 0x0 },
-	{ 0x11269, 0x0 },
-	{ 0x11369, 0x0 },
-	{ 0x11469, 0x0 },
-	{ 0x11569, 0x0 },
-	{ 0x11669, 0x0 },
-	{ 0x11769, 0x0 },
-	{ 0x11869, 0x0 },
-	{ 0x12069, 0x0 },
-	{ 0x12169, 0x0 },
-	{ 0x12269, 0x0 },
-	{ 0x12369, 0x0 },
-	{ 0x12469, 0x0 },
-	{ 0x12569, 0x0 },
-	{ 0x12669, 0x0 },
-	{ 0x12769, 0x0 },
-	{ 0x12869, 0x0 },
-	{ 0x13069, 0x0 },
-	{ 0x13169, 0x0 },
-	{ 0x13269, 0x0 },
-	{ 0x13369, 0x0 },
-	{ 0x13469, 0x0 },
-	{ 0x13569, 0x0 },
-	{ 0x13669, 0x0 },
-	{ 0x13769, 0x0 },
-	{ 0x13869, 0x0 },
-	{ 0x1008c, 0x0 },
-	{ 0x11008c, 0x0 },
-	{ 0x21008c, 0x0 },
-	{ 0x1018c, 0x0 },
-	{ 0x11018c, 0x0 },
-	{ 0x21018c, 0x0 },
-	{ 0x1108c, 0x0 },
-	{ 0x11108c, 0x0 },
-	{ 0x21108c, 0x0 },
-	{ 0x1118c, 0x0 },
-	{ 0x11118c, 0x0 },
-	{ 0x21118c, 0x0 },
-	{ 0x1208c, 0x0 },
-	{ 0x11208c, 0x0 },
-	{ 0x21208c, 0x0 },
-	{ 0x1218c, 0x0 },
-	{ 0x11218c, 0x0 },
-	{ 0x21218c, 0x0 },
-	{ 0x1308c, 0x0 },
-	{ 0x11308c, 0x0 },
-	{ 0x21308c, 0x0 },
-	{ 0x1318c, 0x0 },
-	{ 0x11318c, 0x0 },
-	{ 0x21318c, 0x0 },
-	{ 0x1008d, 0x0 },
-	{ 0x11008d, 0x0 },
-	{ 0x21008d, 0x0 },
-	{ 0x1018d, 0x0 },
-	{ 0x11018d, 0x0 },
-	{ 0x21018d, 0x0 },
-	{ 0x1108d, 0x0 },
-	{ 0x11108d, 0x0 },
-	{ 0x21108d, 0x0 },
-	{ 0x1118d, 0x0 },
-	{ 0x11118d, 0x0 },
-	{ 0x21118d, 0x0 },
-	{ 0x1208d, 0x0 },
-	{ 0x11208d, 0x0 },
-	{ 0x21208d, 0x0 },
-	{ 0x1218d, 0x0 },
-	{ 0x11218d, 0x0 },
-	{ 0x21218d, 0x0 },
-	{ 0x1308d, 0x0 },
-	{ 0x11308d, 0x0 },
-	{ 0x21308d, 0x0 },
-	{ 0x1318d, 0x0 },
-	{ 0x11318d, 0x0 },
-	{ 0x21318d, 0x0 },
-	{ 0x100c0, 0x0 },
-	{ 0x1100c0, 0x0 },
-	{ 0x2100c0, 0x0 },
-	{ 0x101c0, 0x0 },
-	{ 0x1101c0, 0x0 },
-	{ 0x2101c0, 0x0 },
-	{ 0x102c0, 0x0 },
-	{ 0x1102c0, 0x0 },
-	{ 0x2102c0, 0x0 },
-	{ 0x103c0, 0x0 },
-	{ 0x1103c0, 0x0 },
-	{ 0x2103c0, 0x0 },
-	{ 0x104c0, 0x0 },
-	{ 0x1104c0, 0x0 },
-	{ 0x2104c0, 0x0 },
-	{ 0x105c0, 0x0 },
-	{ 0x1105c0, 0x0 },
-	{ 0x2105c0, 0x0 },
-	{ 0x106c0, 0x0 },
-	{ 0x1106c0, 0x0 },
-	{ 0x2106c0, 0x0 },
-	{ 0x107c0, 0x0 },
-	{ 0x1107c0, 0x0 },
-	{ 0x2107c0, 0x0 },
-	{ 0x108c0, 0x0 },
-	{ 0x1108c0, 0x0 },
-	{ 0x2108c0, 0x0 },
-	{ 0x110c0, 0x0 },
-	{ 0x1110c0, 0x0 },
-	{ 0x2110c0, 0x0 },
-	{ 0x111c0, 0x0 },
-	{ 0x1111c0, 0x0 },
-	{ 0x2111c0, 0x0 },
-	{ 0x112c0, 0x0 },
-	{ 0x1112c0, 0x0 },
-	{ 0x2112c0, 0x0 },
-	{ 0x113c0, 0x0 },
-	{ 0x1113c0, 0x0 },
-	{ 0x2113c0, 0x0 },
-	{ 0x114c0, 0x0 },
-	{ 0x1114c0, 0x0 },
-	{ 0x2114c0, 0x0 },
-	{ 0x115c0, 0x0 },
-	{ 0x1115c0, 0x0 },
-	{ 0x2115c0, 0x0 },
-	{ 0x116c0, 0x0 },
-	{ 0x1116c0, 0x0 },
-	{ 0x2116c0, 0x0 },
-	{ 0x117c0, 0x0 },
-	{ 0x1117c0, 0x0 },
-	{ 0x2117c0, 0x0 },
-	{ 0x118c0, 0x0 },
-	{ 0x1118c0, 0x0 },
-	{ 0x2118c0, 0x0 },
-	{ 0x120c0, 0x0 },
-	{ 0x1120c0, 0x0 },
-	{ 0x2120c0, 0x0 },
-	{ 0x121c0, 0x0 },
-	{ 0x1121c0, 0x0 },
-	{ 0x2121c0, 0x0 },
-	{ 0x122c0, 0x0 },
-	{ 0x1122c0, 0x0 },
-	{ 0x2122c0, 0x0 },
-	{ 0x123c0, 0x0 },
-	{ 0x1123c0, 0x0 },
-	{ 0x2123c0, 0x0 },
-	{ 0x124c0, 0x0 },
-	{ 0x1124c0, 0x0 },
-	{ 0x2124c0, 0x0 },
-	{ 0x125c0, 0x0 },
-	{ 0x1125c0, 0x0 },
-	{ 0x2125c0, 0x0 },
-	{ 0x126c0, 0x0 },
-	{ 0x1126c0, 0x0 },
-	{ 0x2126c0, 0x0 },
-	{ 0x127c0, 0x0 },
-	{ 0x1127c0, 0x0 },
-	{ 0x2127c0, 0x0 },
-	{ 0x128c0, 0x0 },
-	{ 0x1128c0, 0x0 },
-	{ 0x2128c0, 0x0 },
-	{ 0x130c0, 0x0 },
-	{ 0x1130c0, 0x0 },
-	{ 0x2130c0, 0x0 },
-	{ 0x131c0, 0x0 },
-	{ 0x1131c0, 0x0 },
-	{ 0x2131c0, 0x0 },
-	{ 0x132c0, 0x0 },
-	{ 0x1132c0, 0x0 },
-	{ 0x2132c0, 0x0 },
-	{ 0x133c0, 0x0 },
-	{ 0x1133c0, 0x0 },
-	{ 0x2133c0, 0x0 },
-	{ 0x134c0, 0x0 },
-	{ 0x1134c0, 0x0 },
-	{ 0x2134c0, 0x0 },
-	{ 0x135c0, 0x0 },
-	{ 0x1135c0, 0x0 },
-	{ 0x2135c0, 0x0 },
-	{ 0x136c0, 0x0 },
-	{ 0x1136c0, 0x0 },
-	{ 0x2136c0, 0x0 },
-	{ 0x137c0, 0x0 },
-	{ 0x1137c0, 0x0 },
-	{ 0x2137c0, 0x0 },
-	{ 0x138c0, 0x0 },
-	{ 0x1138c0, 0x0 },
-	{ 0x2138c0, 0x0 },
-	{ 0x100c1, 0x0 },
-	{ 0x1100c1, 0x0 },
-	{ 0x2100c1, 0x0 },
-	{ 0x101c1, 0x0 },
-	{ 0x1101c1, 0x0 },
-	{ 0x2101c1, 0x0 },
-	{ 0x102c1, 0x0 },
-	{ 0x1102c1, 0x0 },
-	{ 0x2102c1, 0x0 },
-	{ 0x103c1, 0x0 },
-	{ 0x1103c1, 0x0 },
-	{ 0x2103c1, 0x0 },
-	{ 0x104c1, 0x0 },
-	{ 0x1104c1, 0x0 },
-	{ 0x2104c1, 0x0 },
-	{ 0x105c1, 0x0 },
-	{ 0x1105c1, 0x0 },
-	{ 0x2105c1, 0x0 },
-	{ 0x106c1, 0x0 },
-	{ 0x1106c1, 0x0 },
-	{ 0x2106c1, 0x0 },
-	{ 0x107c1, 0x0 },
-	{ 0x1107c1, 0x0 },
-	{ 0x2107c1, 0x0 },
-	{ 0x108c1, 0x0 },
-	{ 0x1108c1, 0x0 },
-	{ 0x2108c1, 0x0 },
-	{ 0x110c1, 0x0 },
-	{ 0x1110c1, 0x0 },
-	{ 0x2110c1, 0x0 },
-	{ 0x111c1, 0x0 },
-	{ 0x1111c1, 0x0 },
-	{ 0x2111c1, 0x0 },
-	{ 0x112c1, 0x0 },
-	{ 0x1112c1, 0x0 },
-	{ 0x2112c1, 0x0 },
-	{ 0x113c1, 0x0 },
-	{ 0x1113c1, 0x0 },
-	{ 0x2113c1, 0x0 },
-	{ 0x114c1, 0x0 },
-	{ 0x1114c1, 0x0 },
-	{ 0x2114c1, 0x0 },
-	{ 0x115c1, 0x0 },
-	{ 0x1115c1, 0x0 },
-	{ 0x2115c1, 0x0 },
-	{ 0x116c1, 0x0 },
-	{ 0x1116c1, 0x0 },
-	{ 0x2116c1, 0x0 },
-	{ 0x117c1, 0x0 },
-	{ 0x1117c1, 0x0 },
-	{ 0x2117c1, 0x0 },
-	{ 0x118c1, 0x0 },
-	{ 0x1118c1, 0x0 },
-	{ 0x2118c1, 0x0 },
-	{ 0x120c1, 0x0 },
-	{ 0x1120c1, 0x0 },
-	{ 0x2120c1, 0x0 },
-	{ 0x121c1, 0x0 },
-	{ 0x1121c1, 0x0 },
-	{ 0x2121c1, 0x0 },
-	{ 0x122c1, 0x0 },
-	{ 0x1122c1, 0x0 },
-	{ 0x2122c1, 0x0 },
-	{ 0x123c1, 0x0 },
-	{ 0x1123c1, 0x0 },
-	{ 0x2123c1, 0x0 },
-	{ 0x124c1, 0x0 },
-	{ 0x1124c1, 0x0 },
-	{ 0x2124c1, 0x0 },
-	{ 0x125c1, 0x0 },
-	{ 0x1125c1, 0x0 },
-	{ 0x2125c1, 0x0 },
-	{ 0x126c1, 0x0 },
-	{ 0x1126c1, 0x0 },
-	{ 0x2126c1, 0x0 },
-	{ 0x127c1, 0x0 },
-	{ 0x1127c1, 0x0 },
-	{ 0x2127c1, 0x0 },
-	{ 0x128c1, 0x0 },
-	{ 0x1128c1, 0x0 },
-	{ 0x2128c1, 0x0 },
-	{ 0x130c1, 0x0 },
-	{ 0x1130c1, 0x0 },
-	{ 0x2130c1, 0x0 },
-	{ 0x131c1, 0x0 },
-	{ 0x1131c1, 0x0 },
-	{ 0x2131c1, 0x0 },
-	{ 0x132c1, 0x0 },
-	{ 0x1132c1, 0x0 },
-	{ 0x2132c1, 0x0 },
-	{ 0x133c1, 0x0 },
-	{ 0x1133c1, 0x0 },
-	{ 0x2133c1, 0x0 },
-	{ 0x134c1, 0x0 },
-	{ 0x1134c1, 0x0 },
-	{ 0x2134c1, 0x0 },
-	{ 0x135c1, 0x0 },
-	{ 0x1135c1, 0x0 },
-	{ 0x2135c1, 0x0 },
-	{ 0x136c1, 0x0 },
-	{ 0x1136c1, 0x0 },
-	{ 0x2136c1, 0x0 },
-	{ 0x137c1, 0x0 },
-	{ 0x1137c1, 0x0 },
-	{ 0x2137c1, 0x0 },
-	{ 0x138c1, 0x0 },
-	{ 0x1138c1, 0x0 },
-	{ 0x2138c1, 0x0 },
-	{ 0x10020, 0x0 },
-	{ 0x110020, 0x0 },
-	{ 0x210020, 0x0 },
-	{ 0x11020, 0x0 },
-	{ 0x111020, 0x0 },
-	{ 0x211020, 0x0 },
-	{ 0x12020, 0x0 },
-	{ 0x112020, 0x0 },
-	{ 0x212020, 0x0 },
-	{ 0x13020, 0x0 },
-	{ 0x113020, 0x0 },
-	{ 0x213020, 0x0 },
-	{ 0x20072, 0x0 },
-	{ 0x20073, 0x0 },
-	{ 0x20074, 0x0 },
-	{ 0x100aa, 0x0 },
-	{ 0x110aa, 0x0 },
-	{ 0x120aa, 0x0 },
-	{ 0x130aa, 0x0 },
-	{ 0x20010, 0x0 },
-	{ 0x120010, 0x0 },
-	{ 0x220010, 0x0 },
-	{ 0x20011, 0x0 },
-	{ 0x120011, 0x0 },
-	{ 0x220011, 0x0 },
-	{ 0x100ae, 0x0 },
-	{ 0x1100ae, 0x0 },
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+	{0x130c0, 0x0},
+	{0x1130c0, 0x0},
+	{0x2130c0, 0x0},
+	{0x131c0, 0x0},
+	{0x1131c0, 0x0},
+	{0x2131c0, 0x0},
+	{0x132c0, 0x0},
+	{0x1132c0, 0x0},
+	{0x2132c0, 0x0},
+	{0x133c0, 0x0},
+	{0x1133c0, 0x0},
+	{0x2133c0, 0x0},
+	{0x134c0, 0x0},
+	{0x1134c0, 0x0},
+	{0x2134c0, 0x0},
+	{0x135c0, 0x0},
+	{0x1135c0, 0x0},
+	{0x2135c0, 0x0},
+	{0x136c0, 0x0},
+	{0x1136c0, 0x0},
+	{0x2136c0, 0x0},
+	{0x137c0, 0x0},
+	{0x1137c0, 0x0},
+	{0x2137c0, 0x0},
+	{0x138c0, 0x0},
+	{0x1138c0, 0x0},
+	{0x2138c0, 0x0},
+	{0x100c1, 0x0},
+	{0x1100c1, 0x0},
+	{0x2100c1, 0x0},
+	{0x101c1, 0x0},
+	{0x1101c1, 0x0},
+	{0x2101c1, 0x0},
+	{0x102c1, 0x0},
+	{0x1102c1, 0x0},
+	{0x2102c1, 0x0},
+	{0x103c1, 0x0},
+	{0x1103c1, 0x0},
+	{0x2103c1, 0x0},
+	{0x104c1, 0x0},
+	{0x1104c1, 0x0},
+	{0x2104c1, 0x0},
+	{0x105c1, 0x0},
+	{0x1105c1, 0x0},
+	{0x2105c1, 0x0},
+	{0x106c1, 0x0},
+	{0x1106c1, 0x0},
+	{0x2106c1, 0x0},
+	{0x107c1, 0x0},
+	{0x1107c1, 0x0},
+	{0x2107c1, 0x0},
+	{0x108c1, 0x0},
+	{0x1108c1, 0x0},
+	{0x2108c1, 0x0},
+	{0x110c1, 0x0},
+	{0x1110c1, 0x0},
+	{0x2110c1, 0x0},
+	{0x111c1, 0x0},
+	{0x1111c1, 0x0},
+	{0x2111c1, 0x0},
+	{0x112c1, 0x0},
+	{0x1112c1, 0x0},
+	{0x2112c1, 0x0},
+	{0x113c1, 0x0},
+	{0x1113c1, 0x0},
+	{0x2113c1, 0x0},
+	{0x114c1, 0x0},
+	{0x1114c1, 0x0},
+	{0x2114c1, 0x0},
+	{0x115c1, 0x0},
+	{0x1115c1, 0x0},
+	{0x2115c1, 0x0},
+	{0x116c1, 0x0},
+	{0x1116c1, 0x0},
+	{0x2116c1, 0x0},
+	{0x117c1, 0x0},
+	{0x1117c1, 0x0},
+	{0x2117c1, 0x0},
+	{0x118c1, 0x0},
+	{0x1118c1, 0x0},
+	{0x2118c1, 0x0},
+	{0x120c1, 0x0},
+	{0x1120c1, 0x0},
+	{0x2120c1, 0x0},
+	{0x121c1, 0x0},
+	{0x1121c1, 0x0},
+	{0x2121c1, 0x0},
+	{0x122c1, 0x0},
+	{0x1122c1, 0x0},
+	{0x2122c1, 0x0},
+	{0x123c1, 0x0},
+	{0x1123c1, 0x0},
+	{0x2123c1, 0x0},
+	{0x124c1, 0x0},
+	{0x1124c1, 0x0},
+	{0x2124c1, 0x0},
+	{0x125c1, 0x0},
+	{0x1125c1, 0x0},
+	{0x2125c1, 0x0},
+	{0x126c1, 0x0},
+	{0x1126c1, 0x0},
+	{0x2126c1, 0x0},
+	{0x127c1, 0x0},
+	{0x1127c1, 0x0},
+	{0x2127c1, 0x0},
+	{0x128c1, 0x0},
+	{0x1128c1, 0x0},
+	{0x2128c1, 0x0},
+	{0x130c1, 0x0},
+	{0x1130c1, 0x0},
+	{0x2130c1, 0x0},
+	{0x131c1, 0x0},
+	{0x1131c1, 0x0},
+	{0x2131c1, 0x0},
+	{0x132c1, 0x0},
+	{0x1132c1, 0x0},
+	{0x2132c1, 0x0},
+	{0x133c1, 0x0},
+	{0x1133c1, 0x0},
+	{0x2133c1, 0x0},
+	{0x134c1, 0x0},
+	{0x1134c1, 0x0},
+	{0x2134c1, 0x0},
+	{0x135c1, 0x0},
+	{0x1135c1, 0x0},
+	{0x2135c1, 0x0},
+	{0x136c1, 0x0},
+	{0x1136c1, 0x0},
+	{0x2136c1, 0x0},
+	{0x137c1, 0x0},
+	{0x1137c1, 0x0},
+	{0x2137c1, 0x0},
+	{0x138c1, 0x0},
+	{0x1138c1, 0x0},
+	{0x2138c1, 0x0},
+	{0x10020, 0x0},
+	{0x110020, 0x0},
+	{0x210020, 0x0},
+	{0x11020, 0x0},
+	{0x111020, 0x0},
+	{0x211020, 0x0},
+	{0x12020, 0x0},
+	{0x112020, 0x0},
+	{0x212020, 0x0},
+	{0x13020, 0x0},
+	{0x113020, 0x0},
+	{0x213020, 0x0},
+	{0x20072, 0x0},
+	{0x20073, 0x0},
+	{0x20074, 0x0},
+	{0x100aa, 0x0},
+	{0x110aa, 0x0},
+	{0x120aa, 0x0},
+	{0x130aa, 0x0},
+	{0x20010, 0x0},
+	{0x120010, 0x0},
+	{0x220010, 0x0},
+	{0x20011, 0x0},
+	{0x120011, 0x0},
+	{0x220011, 0x0},
+	{0x100ae, 0x0},
+	{0x1100ae, 0x0},
+	{0x2100ae, 0x0},
+	{0x100af, 0x0},
+	{0x1100af, 0x0},
+	{0x2100af, 0x0},
+	{0x110ae, 0x0},
+	{0x1110ae, 0x0},
+	{0x2110ae, 0x0},
+	{0x110af, 0x0},
+	{0x1110af, 0x0},
+	{0x2110af, 0x0},
+	{0x120ae, 0x0},
+	{0x1120ae, 0x0},
+	{0x2120ae, 0x0},
+	{0x120af, 0x0},
+	{0x1120af, 0x0},
+	{0x2120af, 0x0},
+	{0x130ae, 0x0},
+	{0x1130ae, 0x0},
+	{0x2130ae, 0x0},
+	{0x130af, 0x0},
+	{0x1130af, 0x0},
+	{0x2130af, 0x0},
+	{0x20020, 0x0},
+	{0x120020, 0x0},
+	{0x220020, 0x0},
+	{0x100a0, 0x0},
+	{0x100a1, 0x0},
+	{0x100a2, 0x0},
+	{0x100a3, 0x0},
+	{0x100a4, 0x0},
+	{0x100a5, 0x0},
+	{0x100a6, 0x0},
+	{0x100a7, 0x0},
+	{0x110a0, 0x0},
+	{0x110a1, 0x0},
+	{0x110a2, 0x0},
+	{0x110a3, 0x0},
+	{0x110a4, 0x0},
+	{0x110a5, 0x0},
+	{0x110a6, 0x0},
+	{0x110a7, 0x0},
+	{0x120a0, 0x0},
+	{0x120a1, 0x0},
+	{0x120a2, 0x0},
+	{0x120a3, 0x0},
+	{0x120a4, 0x0},
+	{0x120a5, 0x0},
+	{0x120a6, 0x0},
+	{0x120a7, 0x0},
+	{0x130a0, 0x0},
+	{0x130a1, 0x0},
+	{0x130a2, 0x0},
+	{0x130a3, 0x0},
+	{0x130a4, 0x0},
+	{0x130a5, 0x0},
+	{0x130a6, 0x0},
+	{0x130a7, 0x0},
+	{0x2007c, 0x0},
+	{0x12007c, 0x0},
+	{0x22007c, 0x0},
+	{0x2007d, 0x0},
+	{0x12007d, 0x0},
+	{0x22007d, 0x0},
+	{0x400fd, 0x0},
+	{0x400c0, 0x0},
+	{0x90201, 0x0},
+	{0x190201, 0x0},
+	{0x290201, 0x0},
+	{0x90202, 0x0},
+	{0x190202, 0x0},
+	{0x290202, 0x0},
+	{0x90203, 0x0},
+	{0x190203, 0x0},
+	{0x290203, 0x0},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x90205, 0x0},
+	{0x190205, 0x0},
+	{0x290205, 0x0},
+	{0x90206, 0x0},
+	{0x190206, 0x0},
+	{0x290206, 0x0},
+	{0x90207, 0x0},
+	{0x190207, 0x0},
+	{0x290207, 0x0},
+	{0x90208, 0x0},
+	{0x190208, 0x0},
+	{0x290208, 0x0},
+	{0x10062, 0x0},
+	{0x10162, 0x0},
+	{0x10262, 0x0},
+	{0x10362, 0x0},
+	{0x10462, 0x0},
+	{0x10562, 0x0},
+	{0x10662, 0x0},
+	{0x10762, 0x0},
+	{0x10862, 0x0},
+	{0x11062, 0x0},
+	{0x11162, 0x0},
+	{0x11262, 0x0},
+	{0x11362, 0x0},
+	{0x11462, 0x0},
+	{0x11562, 0x0},
+	{0x11662, 0x0},
+	{0x11762, 0x0},
+	{0x11862, 0x0},
+	{0x12062, 0x0},
+	{0x12162, 0x0},
+	{0x12262, 0x0},
+	{0x12362, 0x0},
+	{0x12462, 0x0},
+	{0x12562, 0x0},
+	{0x12662, 0x0},
+	{0x12762, 0x0},
+	{0x12862, 0x0},
+	{0x13062, 0x0},
+	{0x13162, 0x0},
+	{0x13262, 0x0},
+	{0x13362, 0x0},
+	{0x13462, 0x0},
+	{0x13562, 0x0},
+	{0x13662, 0x0},
+	{0x13762, 0x0},
+	{0x13862, 0x0},
+	{0x20077, 0x0},
+	{0x10001, 0x0},
+	{0x11001, 0x0},
+	{0x12001, 0x0},
+	{0x13001, 0x0},
+	{0x10040, 0x0},
+	{0x10140, 0x0},
+	{0x10240, 0x0},
+	{0x10340, 0x0},
+	{0x10440, 0x0},
+	{0x10540, 0x0},
+	{0x10640, 0x0},
+	{0x10740, 0x0},
+	{0x10840, 0x0},
+	{0x10030, 0x0},
+	{0x10130, 0x0},
+	{0x10230, 0x0},
+	{0x10330, 0x0},
+	{0x10430, 0x0},
+	{0x10530, 0x0},
+	{0x10630, 0x0},
+	{0x10730, 0x0},
+	{0x10830, 0x0},
+	{0x11040, 0x0},
+	{0x11140, 0x0},
+	{0x11240, 0x0},
+	{0x11340, 0x0},
+	{0x11440, 0x0},
+	{0x11540, 0x0},
+	{0x11640, 0x0},
+	{0x11740, 0x0},
+	{0x11840, 0x0},
+	{0x11030, 0x0},
+	{0x11130, 0x0},
+	{0x11230, 0x0},
+	{0x11330, 0x0},
+	{0x11430, 0x0},
+	{0x11530, 0x0},
+	{0x11630, 0x0},
+	{0x11730, 0x0},
+	{0x11830, 0x0},
+	{0x12040, 0x0},
+	{0x12140, 0x0},
+	{0x12240, 0x0},
+	{0x12340, 0x0},
+	{0x12440, 0x0},
+	{0x12540, 0x0},
+	{0x12640, 0x0},
+	{0x12740, 0x0},
+	{0x12840, 0x0},
+	{0x12030, 0x0},
+	{0x12130, 0x0},
+	{0x12230, 0x0},
+	{0x12330, 0x0},
+	{0x12430, 0x0},
+	{0x12530, 0x0},
+	{0x12630, 0x0},
+	{0x12730, 0x0},
+	{0x12830, 0x0},
+	{0x13040, 0x0},
+	{0x13140, 0x0},
+	{0x13240, 0x0},
+	{0x13340, 0x0},
+	{0x13440, 0x0},
+	{0x13540, 0x0},
+	{0x13640, 0x0},
+	{0x13740, 0x0},
+	{0x13840, 0x0},
+	{0x13030, 0x0},
+	{0x13130, 0x0},
+	{0x13230, 0x0},
+	{0x13330, 0x0},
+	{0x13430, 0x0},
+	{0x13530, 0x0},
+	{0x13630, 0x0},
+	{0x13730, 0x0},
+	{0x13830, 0x0},
 };
-
 /* P0 message block paremeter for training firmware */
 struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{0xd0000, 0x0},
@@ -1054,7 +1055,6 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{0x54008, 0x131f},
 	{0x54009, 0xc8},
 	{0x5400b, 0x2},
-	{0x5400d, 0x100},
 	{0x54012, 0x110},
 	{0x54019, 0x2dd4},
 	{0x5401a, 0x31},
@@ -1094,7 +1094,6 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{0x54008, 0x121f},
 	{0x54009, 0xc8},
 	{0x5400b, 0x2},
-	{0x5400d, 0x100},
 	{0x54012, 0x110},
 	{0x54019, 0x84},
 	{0x5401a, 0x31},
@@ -1134,7 +1133,6 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
 	{0x54008, 0x121f},
 	{0x54009, 0xc8},
 	{0x5400b, 0x2},
-	{0x5400d, 0x100},
 	{0x54012, 0x110},
 	{0x54019, 0x84},
 	{0x5401a, 0x31},
@@ -1200,7 +1198,7 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{0x5403b, 0x4d},
 	{0x5403c, 0x4d},
 	{0x5403d, 0x1600},
-	{ 0xd0000, 0x1 },
+	{0xd0000, 0x1},
 };
 
 /* DRAM PHY init engine image */
@@ -1693,15 +1691,15 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{0x400d6, 0x20a},
 	{0x400d7, 0x20b},
 	{0x2003a, 0x2},
-	{0x2000b, 0x5d},
+	{0x2000b, 0x34b},
 	{0x2000c, 0xbb},
 	{0x2000d, 0x753},
 	{0x2000e, 0x2c},
-	{0x12000b, 0xc},
+	{0x12000b, 0x70},
 	{0x12000c, 0x19},
 	{0x12000d, 0xfa},
 	{0x12000e, 0x10},
-	{0x22000b, 0x3},
+	{0x22000b, 0x1c},
 	{0x22000c, 0x6},
 	{0x22000d, 0x3e},
 	{0x22000e, 0x10},
@@ -1842,5 +1840,5 @@ struct dram_timing_info dram_timing = {
 	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
 	.ddrphy_pie = ddr_phy_pie,
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
-	.fsp_table = { 3000, 400, 100, },
+	.fsp_table = { 3000, 400, 100,},
 };
diff --git a/board/pine64/pinebook-pro-rk3399/MAINTAINERS b/board/pine64/pinebook-pro-rk3399/MAINTAINERS
index 227c1c0bea..7300ca1b1b 100644
--- a/board/pine64/pinebook-pro-rk3399/MAINTAINERS
+++ b/board/pine64/pinebook-pro-rk3399/MAINTAINERS
@@ -1,7 +1,7 @@
 PINEBOOK_PRO
 M:	Peter Robinson <pbrobinson@gmail.com>
 S:	Maintained
-F:	board/pine64/rk3399-pinebook-pro/
+F:	board/pine64/pinebook-pro-rk3399/
 F:	include/configs/rk3399-pinebook-pro.h
 F:	arch/arm/dts/rk3399-pinebook-pro.dts
 F:	arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
index c923ff1be3..bc2dcdd8d4 100644
--- a/board/pine64/pinephone-pro-rk3399/MAINTAINERS
+++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
@@ -1,7 +1,7 @@
 PINEPHONE_PRO
 M:	Peter Robinson <pbrobinson@gmail.com>
 S:	Maintained
-F:	board/pine64/rk3399-pinephone-pro/
+F:	board/pine64/pinephone-pro-rk3399/
 F:	include/configs/rk3399-pinephone-pro.h
 F:	arch/arm/dts/rk3399-pinephone-pro.dts
 F:	arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
index eb639cd0d0..b6ccbb9c1c 100644
--- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
@@ -15,7 +15,8 @@
 #include <asm/arch-rockchip/misc.h>
 #include <power/regulator.h>
 
-#define GRF_IO_VSEL_BT565_SHIFT 0
+#define GRF_IO_VSEL_BT565_GPIO2AB 1
+#define GRF_IO_VSEL_AUDIO_GPIO3D4A 2
 #define PMUGRF_CON0_VSEL_SHIFT 8
 
 #ifndef CONFIG_SPL_BUILD
@@ -48,7 +49,8 @@ static void setup_iodomain(void)
 	   syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 
 	/* BT565 is in 1.8v domain */
-	rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
+	rk_setreg(&grf->io_vsel,
+		  GRF_IO_VSEL_BT565_GPIO2AB | GRF_IO_VSEL_AUDIO_GPIO3D4A);
 
 	/* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
 	rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
diff --git a/board/pine64/quartz64_rk3566/Kconfig b/board/pine64/quartz64_rk3566/Kconfig
new file mode 100644
index 0000000000..3de1d8f7a9
--- /dev/null
+++ b/board/pine64/quartz64_rk3566/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_QUARTZ64_RK3566
+
+config SYS_BOARD
+	default "quartz64_rk3566"
+
+config SYS_VENDOR
+	default "pine64"
+
+config SYS_CONFIG_NAME
+	default "quartz64_rk3566"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS
new file mode 100644
index 0000000000..6b75b35a12
--- /dev/null
+++ b/board/pine64/quartz64_rk3566/MAINTAINERS
@@ -0,0 +1,23 @@
+QUARTZ64-RK3566
+M:	Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+R:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	board/pine64/quartz64_rk3566/
+F:	include/configs/quartz64_rk3566.h
+F:	configs/quartz64-a-rk3566_defconfig
+F:	configs/quartz64-b-rk3566_defconfig
+F:	configs/soquartz-blade-rk3566_defconfig
+F:	configs/soquartz-cm4-rk3566_defconfig
+F:	configs/soquartz-model-a-rk3566_defconfig
+F:	arch/arm/dts/rk3566-quartz64-a.dts
+F:	arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+F:	arch/arm/dts/rk3566-quartz64-b.dts
+F:	arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
+F:	arch/arm/dts/rk3566-soquartz.dtsi
+F:	arch/arm/dts/rk3566-soquartz-u-boot.dtsi
+F:	arch/arm/dts/rk3566-soquartz-blade.dts
+F:	arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi
+F:	arch/arm/dts/rk3566-soquartz-cm4.dts
+F:	arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi
+F:	arch/arm/dts/rk3566-soquartz-model-a.dts
+F:	arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi
diff --git a/board/pine64/quartz64_rk3566/Makefile b/board/pine64/quartz64_rk3566/Makefile
new file mode 100644
index 0000000000..c24a40e724
--- /dev/null
+++ b/board/pine64/quartz64_rk3566/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	+= quartz64-rk3566.o
diff --git a/board/pine64/quartz64_rk3566/quartz64-rk3566.c b/board/pine64/quartz64_rk3566/quartz64-rk3566.c
new file mode 100644
index 0000000000..4c027f2a7a
--- /dev/null
+++ b/board/pine64/quartz64_rk3566/quartz64-rk3566.c
@@ -0,0 +1 @@
+// SPDX-License-Identifier: GPL-2.0+
diff --git a/board/radxa/rock5a-rk3588s/Kconfig b/board/radxa/rock5a-rk3588s/Kconfig
new file mode 100644
index 0000000000..2d7fc85df4
--- /dev/null
+++ b/board/radxa/rock5a-rk3588s/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROCK5A_RK3588
+
+config SYS_BOARD
+	default "rock5a-rk3588s"
+
+config SYS_VENDOR
+	default "radxa"
+
+config SYS_CONFIG_NAME
+	default "rock5a-rk3588s"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS b/board/radxa/rock5a-rk3588s/MAINTAINERS
new file mode 100644
index 0000000000..a569efa74e
--- /dev/null
+++ b/board/radxa/rock5a-rk3588s/MAINTAINERS
@@ -0,0 +1,9 @@
+ROCK5A-RK3588
+M:	Eugen Hristev <eugen.hristev@collabora.com>
+R:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	board/radxa/rock5a-rk3588s
+F:	include/configs/rock5a-rk3588s.h
+F:	configs/rock5a-rk3588s_defconfig
+F:	arch/arm/dts/rk3588s-rock-5a.dts
+F:	arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
diff --git a/board/radxa/rock5a-rk3588s/Makefile b/board/radxa/rock5a-rk3588s/Makefile
new file mode 100644
index 0000000000..48dd512455
--- /dev/null
+++ b/board/radxa/rock5a-rk3588s/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier:     GPL-2.0+
+#
+# Copyright (c) 2023 Collabora Ltd.
+#
+
+obj-y += rock5a-rk3588s.o
diff --git a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
new file mode 100644
index 0000000000..2d7a8c07dc
--- /dev/null
+++ b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ */
+
+#include <fdtdec.h>
+#include <fdt_support.h>
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int rock5a_add_reserved_memory_fdt_nodes(void *new_blob)
+{
+	struct fdt_memory gap1 = {
+		.start = 0x3fc000000,
+		.end = 0x3fc4fffff,
+	};
+	struct fdt_memory gap2 = {
+		.start = 0x3fff00000,
+		.end = 0x3ffffffff,
+	};
+	unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
+	unsigned int ret;
+
+	/*
+	 * Inject the reserved-memory nodes into the DTS
+	 */
+	ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1,  NULL, 0,
+					 NULL, flags);
+	if (ret)
+		return ret;
+
+	return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2,  NULL, 0,
+					  NULL, flags);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return rock5a_add_reserved_memory_fdt_nodes(blob);
+}
+#endif
diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS
index 693751e583..4460c9971a 100644
--- a/board/radxa/rock5b-rk3588/MAINTAINERS
+++ b/board/radxa/rock5b-rk3588/MAINTAINERS
@@ -1,6 +1,9 @@
 ROCK5B-RK3588
 M:	Eugen Hristev <eugen.hristev@collabora.com>
+R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	board/radxa/rock5b-rk3588
-F:	include/configs/rock5b-rk3588
+F:	include/configs/rock5b-rk3588.h
 F:	configs/rock5b-rk3588_defconfig
+F:	arch/arm/dts/rk3588-rock-5b.dts
+F:	arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 1057ebb994..cd823ad746 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -334,7 +334,7 @@ static void set_fdt_addr(void)
 /*
  * Prevent relocation from stomping on a firmware provided FDT blob.
  */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	if ((gd->ram_top - fw_dtb_pointer) > SZ_64M)
 		return gd->ram_top;
@@ -561,6 +561,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer");
 	if (node < 0)
 		fdt_simplefb_add_node(blob);
+	else
+		fdt_simplefb_enable_and_mem_rsv(blob);
 
 #ifdef CONFIG_EFI_LOADER
 	/* Reserve the spin table */
diff --git a/board/renesas/alt/MAINTAINERS b/board/renesas/alt/MAINTAINERS
index 6ec140b225..ee84678d2f 100644
--- a/board/renesas/alt/MAINTAINERS
+++ b/board/renesas/alt/MAINTAINERS
@@ -1,6 +1,8 @@
 ALT BOARD
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 M:	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 S:	Maintained
+F:	arch/arm/dts/r8a7794-alt*
 F:	board/renesas/alt/
-F:	include/configs/alt.h
 F:	configs/alt_defconfig
+F:	include/configs/alt.h
diff --git a/board/renesas/blanche/MAINTAINERS b/board/renesas/blanche/MAINTAINERS
index 4b3114aceb..39fb93ed08 100644
--- a/board/renesas/blanche/MAINTAINERS
+++ b/board/renesas/blanche/MAINTAINERS
@@ -1,7 +1,8 @@
 BLANCHE BOARD
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 M:	Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com>
 S:	Maintained
+F:	arch/arm/dts/r8a7792*
 F:	board/renesas/blanche/
-F:	include/configs/blanche.h
 F:	configs/blanche_defconfig
-
+F:	include/configs/blanche.h
diff --git a/board/renesas/condor/MAINTAINERS b/board/renesas/condor/MAINTAINERS
index 73b010b9e7..6bc987693b 100644
--- a/board/renesas/condor/MAINTAINERS
+++ b/board/renesas/condor/MAINTAINERS
@@ -1,6 +1,7 @@
 CONDOR BOARD
-M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 S:	Maintained
+F:	arch/arm/dts/r8a77980-condor*
 F:	board/renesas/condor/
-F:	include/configs/condor.h
 F:	configs/r8a77980_condor_defconfig
+F:	include/configs/condor.h
diff --git a/board/renesas/condor/Makefile b/board/renesas/condor/Makefile
index cf6d566a9b..19e6038430 100644
--- a/board/renesas/condor/Makefile
+++ b/board/renesas/condor/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_SPL_BUILD
 obj-y	:= ../rcar-common/gen3-spl.o
 else
-obj-y	:= condor.o ../rcar-common/common.o
+obj-y	:= ../rcar-common/common.o
 endif
diff --git a/board/renesas/condor/condor.c b/board/renesas/condor/condor.c
deleted file mode 100644
index 2dd2c1534c..0000000000
--- a/board/renesas/condor/condor.c
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/condor/condor.c
- *     This file is Condor board support.
- *
- * Copyright (C) 2019 Marek Vasut <marek.vasut+renesas@gmail.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/processor.h>
-#include <asm/mach-types.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	return 0;
-}
-
-#define RST_BASE	0xE6160000
-#define RST_CA57RESCNT	(RST_BASE + 0x40)
-#define RST_CA53RESCNT	(RST_BASE + 0x44)
-#define RST_RSTOUTCR	(RST_BASE + 0x58)
-#define RST_CA57_CODE	0xA5A5000F
-#define RST_CA53_CODE	0x5A5A000F
-
-void reset_cpu(void)
-{
-	unsigned long midr, cputype;
-
-	asm volatile("mrs %0, midr_el1" : "=r" (midr));
-	cputype = (midr >> 4) & 0xfff;
-
-	if (cputype == 0xd03)
-		writel(RST_CA53_CODE, RST_CA53RESCNT);
-	else if (cputype == 0xd07)
-		writel(RST_CA57_CODE, RST_CA57RESCNT);
-	else
-		hang();
-}
diff --git a/board/renesas/draak/MAINTAINERS b/board/renesas/draak/MAINTAINERS
index 1dbcc2811c..646478428a 100644
--- a/board/renesas/draak/MAINTAINERS
+++ b/board/renesas/draak/MAINTAINERS
@@ -1,6 +1,7 @@
 DRAAK BOARD
-M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 S:	Maintained
+F:	arch/arm/dts/r8a77995*
 F:	board/renesas/draak/
-F:	include/configs/draak.h
 F:	configs/r8a77995_draak_defconfig
+F:	include/configs/draak.h
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index 71efeaf313..1ed72d34a7 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -67,12 +67,3 @@ int board_init(void)
 
 	return 0;
 }
-
-#define RST_BASE	0xE6160000
-#define RST_CA53RESCNT	(RST_BASE + 0x44)
-#define RST_CA53_CODE	0x5A5A000F
-
-void reset_cpu(void)
-{
-	writel(RST_CA53_CODE, RST_CA53RESCNT);
-}
diff --git a/board/renesas/eagle/Kconfig b/board/renesas/eagle/Kconfig
index 1e0710e73e..4d12843b4e 100644
--- a/board/renesas/eagle/Kconfig
+++ b/board/renesas/eagle/Kconfig
@@ -10,6 +10,6 @@ config SYS_VENDOR
 	default "renesas"
 
 config SYS_CONFIG_NAME
-	default "eagle"
+	default "rcar-gen3-common"
 
 endif
diff --git a/board/renesas/eagle/MAINTAINERS b/board/renesas/eagle/MAINTAINERS
index f387c13616..c28b650247 100644
--- a/board/renesas/eagle/MAINTAINERS
+++ b/board/renesas/eagle/MAINTAINERS
@@ -1,6 +1,7 @@
 EAGLE BOARD
-M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 S:	Maintained
+F:	arch/arm/dts/r8a77970-eagle*
 F:	board/renesas/eagle/
-F:	include/configs/eagle.h
 F:	configs/r8a77970_eagle_defconfig
+F:	include/configs/eagle.h
diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile
index 062c46ba24..9fb6a7c0f0 100644
--- a/board/renesas/eagle/Makefile
+++ b/board/renesas/eagle/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_SPL_BUILD
 obj-y	:= ../rcar-common/gen3-spl.o
 else
-obj-y	:= eagle.o ../rcar-common/common.o
+obj-y	:= ../rcar-common/v3-common.o ../rcar-common/common.o
 endif
diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c
deleted file mode 100644
index 9af935c33f..0000000000
--- a/board/renesas/eagle/eagle.c
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/eagle/eagle.c
- *     This file is Eagle board support.
- *
- * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <init.h>
-#include <malloc.h>
-#include <netdev.h>
-#include <dm.h>
-#include <asm/global_data.h>
-#include <dm/platform_data/serial_sh.h>
-#include <asm/processor.h>
-#include <asm/mach-types.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/rmobile.h>
-#include <asm/arch/rcar-mstp.h>
-#include <asm/arch/sh_sdhi.h>
-#include <i2c.h>
-#include <mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CPGWPR  0xE6150900
-#define CPGWPCR	0xE6150904
-
-/* PLL */
-#define PLL0CR		0xE61500D8
-#define PLL0_STC_MASK	0x7F000000
-#define PLL0_STC_OFFSET	24
-
-#define CLK2MHZ(clk)	(clk / 1000 / 1000)
-void s_init(void)
-{
-	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
-	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-	u32 stc;
-
-	/* Watchdog init */
-	writel(0xA5A5A500, &rwdt->rwtcsra);
-	writel(0xA5A5A500, &swdt->swtcsra);
-
-	/* CPU frequency setting. Set to 0.8GHz */
-	stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
-	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
-}
-
-int board_early_init_f(void)
-{
-	/* Unlock CPG access */
-	writel(0xA5A5FFFF, CPGWPR);
-	writel(0x5A5A0000, CPGWPCR);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	return 0;
-}
-
-#define RST_BASE	0xE6160000
-#define RST_CA57RESCNT	(RST_BASE + 0x40)
-#define RST_CA53RESCNT	(RST_BASE + 0x44)
-#define RST_RSTOUTCR	(RST_BASE + 0x58)
-#define RST_CA57_CODE	0xA5A5000F
-#define RST_CA53_CODE	0x5A5A000F
-
-void reset_cpu(void)
-{
-	unsigned long midr, cputype;
-
-	asm volatile("mrs %0, midr_el1" : "=r" (midr));
-	cputype = (midr >> 4) & 0xfff;
-
-	if (cputype == 0xd03)
-		writel(RST_CA53_CODE, RST_CA53RESCNT);
-	else if (cputype == 0xd07)
-		writel(RST_CA57_CODE, RST_CA57RESCNT);
-	else
-		hang();
-}
diff --git a/board/renesas/ebisu/MAINTAINERS b/board/renesas/ebisu/MAINTAINERS
index facad520ca..c41aa1ef64 100644
--- a/board/renesas/ebisu/MAINTAINERS
+++ b/board/renesas/ebisu/MAINTAINERS
@@ -1,6 +1,7 @@
 EBISU BOARD
-M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 S:	Maintained
+F:	arch/arm/dts/r8a77990*
 F:	board/renesas/ebisu/
-F:	include/configs/ebisu.h
 F:	configs/r8a77990_ebisu_defconfig
+F:	include/configs/ebisu.h
diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile
index 1fd9a03ecc..956ce8a90f 100644
--- a/board/renesas/ebisu/Makefile
+++ b/board/renesas/ebisu/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_SPL_BUILD
 obj-y	:= ../rcar-common/gen3-spl.o
 else
-obj-y	:= ebisu.o ../rcar-common/common.o
+obj-y	:= ../rcar-common/common.o
 endif
diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c
deleted file mode 100644
index 9a70192596..0000000000
--- a/board/renesas/ebisu/ebisu.c
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/ebisu/ebisu.c
- *     This file is Ebisu board support.
- *
- * Copyright (C) 2018 Marek Vasut <marek.vasut+renesas@gmail.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <init.h>
-#include <malloc.h>
-#include <netdev.h>
-#include <dm.h>
-#include <asm/global_data.h>
-#include <dm/platform_data/serial_sh.h>
-#include <asm/processor.h>
-#include <asm/mach-types.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/rmobile.h>
-#include <asm/arch/rcar-mstp.h>
-#include <asm/arch/sh_sdhi.h>
-#include <i2c.h>
-#include <mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	return 0;
-}
-
-#define RST_BASE	0xE6160000
-#define RST_CA53RESCNT	(RST_BASE + 0x44)
-#define RST_CA53_CODE	0x5A5A000F
-
-void reset_cpu(void)
-{
-	writel(RST_CA53_CODE, RST_CA53RESCNT);
-}
diff --git a/board/renesas/falcon/MAINTAINERS b/board/renesas/falcon/MAINTAINERS
index 2cacc91494..861f068686 100644
--- a/board/renesas/falcon/MAINTAINERS
+++ b/board/renesas/falcon/MAINTAINERS
@@ -1,6 +1,7 @@
 FALCON BOARD
-M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 S:	Maintained
+F:	arch/arm/dts/r8a779a0*
 F:	board/renesas/falcon/
-F:	include/configs/falcon.h
 F:	configs/r8a779a0_falcon_defconfig
+F:	include/configs/falcon.h
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c
index ab7464d0ee..0aa0f1afcb 100644
--- a/board/renesas/falcon/falcon.c
+++ b/board/renesas/falcon/falcon.c
@@ -84,8 +84,6 @@ int board_early_init_f(void)
 }
 
 #define RST_BASE	0xE6160000 /* Domain0 */
-#define RST_SRESCR0	(RST_BASE + 0x18)
-#define RST_SPRES	0x5AA58000
 #define RST_WDTRSTCR	(RST_BASE + 0x10)
 #define RST_RWDT	0xA55A8002
 
@@ -103,8 +101,3 @@ int board_init(void)
 
 	return 0;
 }
-
-void reset_cpu(void)
-{
-	writel(RST_SPRES, RST_SRESCR0);
-}
diff --git a/board/renesas/gose/MAINTAINERS b/board/renesas/gose/MAINTAINERS
index cad5be99b1..c6b9902fd8 100644
--- a/board/renesas/gose/MAINTAINERS
+++ b/board/renesas/gose/MAINTAINERS
@@ -1,6 +1,8 @@
-ALT BOARD
+GOSE BOARD
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 M:	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 S:	Maintained
+F:	arch/arm/dts/r8a7793*
 F:	board/renesas/gose/
-F:	include/configs/gose.h
 F:	configs/gose_defconfig
+F:	include/configs/gose.h
diff --git a/board/renesas/grpeach/MAINTAINERS b/board/renesas/grpeach/MAINTAINERS
index 4ab7773b0a..c0f4fbcbae 100644
--- a/board/renesas/grpeach/MAINTAINERS
+++ b/board/renesas/grpeach/MAINTAINERS
@@ -1,6 +1,16 @@
 GRPEACH BOARD
-M:	Marek Vasut <marek.vasut@gmail.com>
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 S:	Maintained
+F:	arch/arm/dts/r7s72100*
 F:	board/renesas/grpeach/
-F:	include/configs/grpeach.h
 F:	configs/grpeach_defconfig
+F:	drivers/gpio/gpio-rza1.c
+F:	drivers/mtd/renesas_rpc_hf.c
+F:	drivers/net/sh_eth*
+F:	drivers/pinctrl/renesas/pfc-r7s72100.c
+F:	drivers/serial/serial_sh*
+F:	drivers/spi/renesas_rpc_spi.c
+F:	drivers/timer/ostm_timer.c
+F:	drivers/usb/host/r8a66597-hcd.c
+F:	drivers/usb/host/r8a66597.h
+F:	include/configs/grpeach.h
diff --git a/board/renesas/koelsch/MAINTAINERS b/board/renesas/koelsch/MAINTAINERS
index 5267b9fadf..788f01ae9f 100644
--- a/board/renesas/koelsch/MAINTAINERS
+++ b/board/renesas/koelsch/MAINTAINERS
@@ -1,6 +1,8 @@
 KOELSCH BOARD
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 M:	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 S:	Maintained
+F:	arch/arm/dts/r8a7791-koelsch*
 F:	board/renesas/koelsch/
-F:	include/configs/koelsch.h
 F:	configs/koelsch_defconfig
+F:	include/configs/koelsch.h
diff --git a/board/renesas/lager/MAINTAINERS b/board/renesas/lager/MAINTAINERS
index a09868614a..48b690dfa0 100644
--- a/board/renesas/lager/MAINTAINERS
+++ b/board/renesas/lager/MAINTAINERS
@@ -1,6 +1,8 @@
 LAGER BOARD
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 M:	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 S:	Maintained
+F:	arch/arm/dts/r8a7790-lager*
 F:	board/renesas/lager/
-F:	include/configs/lager.h
 F:	configs/lager_defconfig
+F:	include/configs/lager.h
diff --git a/board/renesas/porter/MAINTAINERS b/board/renesas/porter/MAINTAINERS
index 1dc6a1caf2..4671b5b03c 100644
--- a/board/renesas/porter/MAINTAINERS
+++ b/board/renesas/porter/MAINTAINERS
@@ -1,6 +1,8 @@
 PORTER BOARD
 M:	Cogent Embedded, Inc. <source@cogentembedded.com>
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 S:	Maintained
+F:	arch/arm/dts/r8a7791-porter*
 F:	board/renesas/porter/
-F:	include/configs/porter.h
 F:	configs/porter_defconfig
+F:	include/configs/porter.h
diff --git a/board/renesas/r2dplus/MAINTAINERS b/board/renesas/r2dplus/MAINTAINERS
index 58877c509e..a5cc2f0895 100644
--- a/board/renesas/r2dplus/MAINTAINERS
+++ b/board/renesas/r2dplus/MAINTAINERS
@@ -1,7 +1,11 @@
 R2DPLUS BOARD
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 M:	Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 S:	Maintained
+F:	arch/sh/dts/sh7751-r2dplus*
 F:	board/renesas/r2dplus/
-F:	include/configs/r2dplus.h
 F:	configs/r2dplus_defconfig
+F:	drivers/pci/pci_sh7751.c
+F:	drivers/serial/serial_sh*
+F:	include/configs/r2dplus.h
diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c
index f976c99028..ed3f093bf3 100644
--- a/board/renesas/rcar-common/common.c
+++ b/board/renesas/rcar-common/common.c
@@ -10,8 +10,10 @@
 #include <common.h>
 #include <dm.h>
 #include <fdt_support.h>
+#include <hang.h>
 #include <init.h>
 #include <asm/global_data.h>
+#include <asm/io.h>
 #include <dm/uclass-internal.h>
 #include <asm/arch/rmobile.h>
 #include <linux/libfdt.h>
@@ -52,6 +54,46 @@ int dram_init_banksize(void)
 	return 0;
 }
 
+int __weak board_init(void)
+{
+	return 0;
+}
+
+#if defined(CONFIG_RCAR_GEN3)
+#define RST_BASE	0xE6160000
+#define RST_CA57RESCNT	(RST_BASE + 0x40)
+#define RST_CA53RESCNT	(RST_BASE + 0x44)
+#define RST_RSTOUTCR	(RST_BASE + 0x58)
+#define RST_CA57_CODE	0xA5A5000F
+#define RST_CA53_CODE	0x5A5A000F
+
+void __weak reset_cpu(void)
+{
+	unsigned long midr, cputype;
+
+	asm volatile("mrs %0, midr_el1" : "=r" (midr));
+	cputype = (midr >> 4) & 0xfff;
+
+	if (cputype == 0xd03)
+		writel(RST_CA53_CODE, RST_CA53RESCNT);
+	else if (cputype == 0xd07)
+		writel(RST_CA57_CODE, RST_CA57RESCNT);
+	else
+		hang();
+}
+#elif defined(CONFIG_RCAR_GEN4)
+#define RST_BASE	0xE6160000 /* Domain0 */
+#define RST_SRESCR0	(RST_BASE + 0x18)
+#define RST_SPRES	0x5AA58000
+
+void __weak reset_cpu(void)
+{
+	writel(RST_SPRES, RST_SRESCR0);
+}
+#else
+#error Neither CONFIG_RCAR_GEN3 nor CONFIG_RCAR_GEN4 are set
+#endif
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node)
 {
diff --git a/board/renesas/rcar-common/v3-common.c b/board/renesas/rcar-common/v3-common.c
new file mode 100644
index 0000000000..7c6202ea49
--- /dev/null
+++ b/board/renesas/rcar-common/v3-common.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2023 Marek Vasut <marek.vasut+renesas@mailbox.org>
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <asm/io.h>
+
+#define CPGWPR  0xE6150900
+#define CPGWPCR	0xE6150904
+
+/* PLL */
+#define PLL0CR		0xE61500D8
+#define PLL0_STC_MASK	0x7F000000
+#define PLL0_STC_OFFSET	24
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+	u32 stc;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* CPU frequency setting. Set to 0.8GHz */
+	stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
+	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+}
+
+int board_early_init_f(void)
+{
+	/* Unlock CPG access */
+	writel(0xA5A5FFFF, CPGWPR);
+	writel(0x5A5A0000, CPGWPCR);
+
+	return 0;
+}
diff --git a/board/renesas/salvator-x/MAINTAINERS b/board/renesas/salvator-x/MAINTAINERS
index 7335bc3cd8..a85e9d98d3 100644
--- a/board/renesas/salvator-x/MAINTAINERS
+++ b/board/renesas/salvator-x/MAINTAINERS
@@ -1,6 +1,8 @@
 SALVATOR_X BOARD
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 S:	Maintained
+F:	arch/arm/dts/*salvator-x*
 F:	board/renesas/salvator-x/
-F:	include/configs/salvator-x.h
 F:	configs/rcar3_salvator-x_defconfig
+F:	include/configs/salvator-x.h
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index c27eb3f17d..939b48ee30 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -67,21 +67,12 @@ int board_init(void)
 	return 0;
 }
 
-#define RST_BASE	0xE6160000
-#define RST_CA57RESCNT	(RST_BASE + 0x40)
-#define RST_CA53RESCNT	(RST_BASE + 0x44)
-#define RST_RSTOUTCR	(RST_BASE + 0x58)
-#define RST_CODE	0xA5A5000F
-
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
 void reset_cpu(void)
 {
-#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
 	i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
-#else
-	/* only CA57 ? */
-	writel(RST_CODE, RST_CA57RESCNT);
-#endif
 }
+#endif
 
 #ifdef CONFIG_MULTI_DTB_FIT
 int board_fit_config_name_match(const char *name)
diff --git a/board/renesas/silk/MAINTAINERS b/board/renesas/silk/MAINTAINERS
index b566ccfbd9..40fa271027 100644
--- a/board/renesas/silk/MAINTAINERS
+++ b/board/renesas/silk/MAINTAINERS
@@ -1,6 +1,8 @@
 SILK BOARD
 M:	Cogent Embedded, Inc. <source@cogentembedded.com>
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 S:	Maintained
+F:	arch/arm/dts/r8a7794-silk*
 F:	board/renesas/silk/
-F:	include/configs/silk.h
 F:	configs/silk_defconfig
+F:	include/configs/silk.h
diff --git a/board/renesas/spider/MAINTAINERS b/board/renesas/spider/MAINTAINERS
new file mode 100644
index 0000000000..731ca35ba9
--- /dev/null
+++ b/board/renesas/spider/MAINTAINERS
@@ -0,0 +1,7 @@
+SPIDER BOARD
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
+S:	Maintained
+F:	arch/arm/dts/r8a779f0*
+F:	board/renesas/spider/
+F:	configs/r8a779f0_spider_defconfig
+F:	include/configs/spider.h
diff --git a/board/renesas/spider/spider.c b/board/renesas/spider/spider.c
index caf88dcc32..fd83a72229 100644
--- a/board/renesas/spider/spider.c
+++ b/board/renesas/spider/spider.c
@@ -65,8 +65,3 @@ int board_init(void)
 
 	return 0;
 }
-
-void reset_cpu(void)
-{
-	writel(RST_SPRES, RST_SRESCR0);
-}
diff --git a/board/renesas/stout/MAINTAINERS b/board/renesas/stout/MAINTAINERS
index b7098e7955..a6042d8b71 100644
--- a/board/renesas/stout/MAINTAINERS
+++ b/board/renesas/stout/MAINTAINERS
@@ -1,6 +1,8 @@
 STOUT BOARD
 M:	Cogent Embedded, Inc. <source@cogentembedded.com>
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 S:	Maintained
+F:	arch/arm/dts/r8a7790-stout*
 F:	board/renesas/stout/
-F:	include/configs/stout.h
 F:	configs/stout_defconfig
+F:	include/configs/stout.h
diff --git a/board/renesas/ulcb/MAINTAINERS b/board/renesas/ulcb/MAINTAINERS
index 564eb561b1..18b9b426ef 100644
--- a/board/renesas/ulcb/MAINTAINERS
+++ b/board/renesas/ulcb/MAINTAINERS
@@ -1,6 +1,7 @@
 ULCB BOARD
-M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 S:	Maintained
+F:	arch/arm/dts/*ulcb*
 F:	board/renesas/ulcb/
-F:	include/configs/ulcb.h
 F:	configs/rcar3_ulcb_defconfig
+F:	include/configs/ulcb.h
diff --git a/board/renesas/v3hsk/Kconfig b/board/renesas/v3hsk/Kconfig
new file mode 100644
index 0000000000..531ceb788f
--- /dev/null
+++ b/board/renesas/v3hsk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_V3HSK
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "v3hsk"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "v3hsk"
+
+endif
diff --git a/board/renesas/v3hsk/MAINTAINERS b/board/renesas/v3hsk/MAINTAINERS
new file mode 100644
index 0000000000..8a5af85402
--- /dev/null
+++ b/board/renesas/v3hsk/MAINTAINERS
@@ -0,0 +1,7 @@
+V3HSK BOARD
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
+S:	Maintained
+F:	arch/arm/dts/r8a77980-v3hsk*
+F:	board/renesas/v3hsk/
+F:	configs/r8a77980_v3hsk_defconfig
+F:	include/configs/v3hsk.h
diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile
new file mode 100644
index 0000000000..a9d597edd5
--- /dev/null
+++ b/board/renesas/v3hsk/Makefile
@@ -0,0 +1,15 @@
+#
+# board/renesas/v3hsk/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+# Copyright (C) 2019 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= ../rcar-common/gen3-spl.o
+else
+obj-y	:= ../rcar-common/v3-common.o ../rcar-common/common.o
+obj-$(CONFIG_SYSRESET)	+= cpld.o
+endif
diff --git a/board/renesas/v3hsk/cpld.c b/board/renesas/v3hsk/cpld.c
new file mode 100644
index 0000000000..6016f6daef
--- /dev/null
+++ b/board/renesas/v3hsk/cpld.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * V3HSK board CPLD access support
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <linux/err.h>
+#include <sysreset.h>
+#include <command.h>
+
+#define CPLD_ADDR_PRODUCT_0		0x0000 /* R */
+#define CPLD_ADDR_PRODUCT_1		0x0001 /* R */
+#define CPLD_ADDR_PRODUCT_2		0x0002 /* R */
+#define CPLD_ADDR_PRODUCT_3		0x0003 /* R */
+#define CPLD_ADDR_CPLD_VERSION_D	0x0004 /* R */
+#define CPLD_ADDR_CPLD_VERSION_M	0x0005 /* R */
+#define CPLD_ADDR_CPLD_VERSION_Y_0	0x0006 /* R */
+#define CPLD_ADDR_CPLD_VERSION_Y_1	0x0007 /* R */
+#define CPLD_ADDR_MODE_SET_0		0x0008 /* R */
+#define CPLD_ADDR_MODE_SET_1		0x0009 /* R */
+#define CPLD_ADDR_MODE_SET_2		0x000A /* R */
+#define CPLD_ADDR_MODE_SET_3		0x000B /* R */
+#define CPLD_ADDR_MODE_SET_4		0x000C /* R */
+#define CPLD_ADDR_MODE_LAST_0		0x0018 /* R */
+#define CPLD_ADDR_MODE_LAST_1		0x0019 /* R */
+#define CPLD_ADDR_MODE_LAST_2		0x001A /* R */
+#define CPLD_ADDR_MODE_LAST_3		0x001B /* R */
+#define CPLD_ADDR_MODE_LAST_4		0x001C /* R */
+#define CPLD_ADDR_DIPSW4		0x0020 /* R */
+#define CPLD_ADDR_DIPSW5		0x0021 /* R */
+#define CPLD_ADDR_RESET			0x0024 /* R/W */
+#define CPLD_ADDR_POWER_CFG		0x0025 /* R/W */
+#define CPLD_ADDR_PERI_CFG_0		0x0030 /* R/W */
+#define CPLD_ADDR_PERI_CFG_1		0x0031 /* R/W */
+#define CPLD_ADDR_PERI_CFG_2		0x0032 /* R/W */
+#define CPLD_ADDR_PERI_CFG_3		0x0033 /* R/W */
+#define CPLD_ADDR_LEDS			0x0034 /* R/W */
+#define CPLD_ADDR_LEDS_CFG		0x0035 /* R/W */
+#define CPLD_ADDR_UART_CFG		0x0036 /* R/W */
+#define CPLD_ADDR_UART_STATUS		0x0037 /* R */
+
+#define CPLD_ADDR_PCB_VERSION_0		0x1000 /* R */
+#define CPLD_ADDR_PCB_VERSION_1		0x1001 /* R */
+#define CPLD_ADDR_SOC_VERSION_0		0x1002 /* R */
+#define CPLD_ADDR_SOC_VERSION_1		0x1003 /* R */
+#define CPLD_ADDR_PCB_SN_0		0x1004 /* R */
+#define CPLD_ADDR_PCB_SN_1		0x1005 /* R */
+
+static u16 cpld_read(struct udevice *dev, u16 addr)
+{
+	u8 data[2];
+
+	/* Random flash reads require 2 reads: first read is unreliable */
+	if (addr >= CPLD_ADDR_PCB_VERSION_0)
+		dm_i2c_read(dev, addr, data, 2);
+
+	/* Only the second byte read is valid */
+	dm_i2c_read(dev, addr, data, 2);
+	return data[1];
+}
+
+static void cpld_write(struct udevice *dev, u16 addr, u8 data)
+{
+	dm_i2c_write(dev, addr, &data, 1);
+}
+
+static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct udevice *dev;
+	u16 addr, val;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
+					  DM_DRIVER_GET(sysreset_renesas_v3hsk),
+					  &dev);
+	if (ret)
+		return ret;
+
+	if (argc == 2 && strcmp(argv[1], "info") == 0) {
+		printf("Product:                0x%08x\n",
+		       (cpld_read(dev, CPLD_ADDR_PRODUCT_3) << 24) |
+		       (cpld_read(dev, CPLD_ADDR_PRODUCT_2) << 16) |
+		       (cpld_read(dev, CPLD_ADDR_PRODUCT_1) << 8) |
+		       cpld_read(dev, CPLD_ADDR_PRODUCT_0));
+		printf("CPLD version:           0x%08x\n",
+		       (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_1) << 24) |
+		       (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_0) << 16) |
+		       (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_M) << 8) |
+		       cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
+		printf("Mode setting (MD0..26): 0x%08x\n",
+		       (cpld_read(dev, CPLD_ADDR_MODE_LAST_3) << 24) |
+		       (cpld_read(dev, CPLD_ADDR_MODE_LAST_2) << 16) |
+		       (cpld_read(dev, CPLD_ADDR_MODE_LAST_1) << 8) |
+		       cpld_read(dev, CPLD_ADDR_MODE_LAST_0));
+		printf("DIPSW (SW4, SW5):       0x%02x, 0x%x\n",
+		       cpld_read(dev, CPLD_ADDR_DIPSW4) ^ 0xff,
+		       (cpld_read(dev, CPLD_ADDR_DIPSW5) ^ 0xff) & 0xf);
+		printf("Power config:           0x%08x\n",
+		       cpld_read(dev, CPLD_ADDR_POWER_CFG));
+		printf("Periferals config:      0x%08x\n",
+		       (cpld_read(dev, CPLD_ADDR_PERI_CFG_3) << 24) |
+		       (cpld_read(dev, CPLD_ADDR_PERI_CFG_2) << 16) |
+		       (cpld_read(dev, CPLD_ADDR_PERI_CFG_1) << 8) |
+		       cpld_read(dev, CPLD_ADDR_PERI_CFG_0));
+		printf("PCB version:            %d.%d\n",
+		       cpld_read(dev, CPLD_ADDR_PCB_VERSION_1),
+		       cpld_read(dev, CPLD_ADDR_PCB_VERSION_0));
+		printf("SOC version:            %d.%d\n",
+		       cpld_read(dev, CPLD_ADDR_SOC_VERSION_1),
+		       cpld_read(dev, CPLD_ADDR_SOC_VERSION_0));
+		printf("PCB S/N:                %d\n",
+		       (cpld_read(dev, CPLD_ADDR_PCB_SN_1) << 8) |
+		       cpld_read(dev, CPLD_ADDR_PCB_SN_0));
+		return 0;
+	}
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	if (!(addr >= CPLD_ADDR_PRODUCT_0 && addr <= CPLD_ADDR_UART_STATUS)) {
+		printf("cpld invalid addr\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (argc == 3 && strcmp(argv[1], "read") == 0) {
+		printf("0x%x\n", cpld_read(dev, addr));
+	} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+		val = simple_strtoul(argv[3], NULL, 16);
+		cpld_write(dev, addr, val);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(cpld, 4, 1, do_cpld,
+	   "CPLD access",
+	   "info\n"
+	   "cpld read addr\n"
+	   "cpld write addr val\n"
+);
+
+static int renesas_v3hsk_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	cpld_write(dev, CPLD_ADDR_RESET, 1);
+
+	return -EINPROGRESS;
+}
+
+static int renesas_v3hsk_sysreset_probe(struct udevice *dev)
+{
+	if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
+		return -EPROTONOSUPPORT;
+
+	return 0;
+}
+
+static struct sysreset_ops renesas_v3hsk_sysreset = {
+	.request	= renesas_v3hsk_sysreset_request,
+};
+
+static const struct udevice_id renesas_v3hsk_sysreset_ids[] = {
+	{ .compatible = "renesas,v3hsk-cpld" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sysreset_renesas_v3hsk) = {
+	.name		= "renesas_v3hsk_sysreset",
+	.id		= UCLASS_SYSRESET,
+	.ops		= &renesas_v3hsk_sysreset,
+	.probe		= renesas_v3hsk_sysreset_probe,
+	.of_match	= renesas_v3hsk_sysreset_ids,
+};
diff --git a/board/renesas/v3msk/Kconfig b/board/renesas/v3msk/Kconfig
new file mode 100644
index 0000000000..fe037fd98f
--- /dev/null
+++ b/board/renesas/v3msk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_V3MSK
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "v3msk"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "rcar-gen3-common"
+
+endif
diff --git a/board/renesas/v3msk/MAINTAINERS b/board/renesas/v3msk/MAINTAINERS
new file mode 100644
index 0000000000..c198cf8c9b
--- /dev/null
+++ b/board/renesas/v3msk/MAINTAINERS
@@ -0,0 +1,8 @@
+V3MSK BOARD
+M:	Cogent Embedded, Inc. <source@cogentembedded.com>
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
+S:	Maintained
+F:	arch/arm/dts/r8a77970-v3msk*
+F:	board/renesas/v3msk/
+F:	configs/r8a77970_v3msk_defconfig
+F:	include/configs/v3msk.h
diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile
new file mode 100644
index 0000000000..ec493e572f
--- /dev/null
+++ b/board/renesas/v3msk/Makefile
@@ -0,0 +1,15 @@
+#
+# board/renesas/v3msk/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+# Copyright (C) 2019 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= ../rcar-common/gen3-spl.o
+else
+obj-y	:= ../rcar-common/v3-common.o ../rcar-common/common.o
+obj-$(CONFIG_SYSRESET)	+= cpld.o
+endif
diff --git a/board/renesas/v3msk/cpld.c b/board/renesas/v3msk/cpld.c
new file mode 100644
index 0000000000..aed616ac85
--- /dev/null
+++ b/board/renesas/v3msk/cpld.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * V3MSK board CPLD access support
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ *
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/err.h>
+#include <sysreset.h>
+#include <linux/delay.h>
+#include <command.h>
+
+#define CPLD_ADDR_PRODUCT_L		0x000 /* R */
+#define CPLD_ADDR_PRODUCT_H		0x001 /* R */
+#define CPLD_ADDR_CPLD_VERSION_D	0x002 /* R */
+#define CPLD_ADDR_CPLD_VERSION_Y	0x003 /* R */
+#define CPLD_ADDR_MODE_SET_L		0x004 /* R/W */
+#define CPLD_ADDR_MODE_SET_H		0x005 /* R/W */
+#define CPLD_ADDR_MODE_APPLIED_L	0x006 /* R */
+#define CPLD_ADDR_MODE_APPLIED_H	0x007 /* R */
+#define CPLD_ADDR_DIPSW			0x008 /* R */
+#define CPLD_ADDR_RESET			0x00A /* R/W */
+#define CPLD_ADDR_POWER_CFG		0x00B /* R/W */
+#define CPLD_ADDR_PERI_CFG1		0x00C /* R/W */
+#define CPLD_ADDR_PERI_CFG2		0x00D /* R/W */
+#define CPLD_ADDR_LEDS			0x00E /* R/W */
+#define CPLD_ADDR_PCB_VERSION		0x300 /* R */
+#define CPLD_ADDR_SOC_VERSION		0x301 /* R */
+#define CPLD_ADDR_PCB_SN_L		0x302 /* R */
+#define CPLD_ADDR_PCB_SN_H		0x303 /* R */
+
+#define MDIO_DELAY			10 /* microseconds */
+
+#define CPLD_MAX_GPIOS			2
+
+struct renesas_v3msk_sysreset_priv {
+	struct gpio_desc	miso;
+	struct gpio_desc	mosi;
+	struct gpio_desc	mdc;
+	struct gpio_desc	enablez;
+	/*
+	 * V3MSK Videobox Mini board has CANFD PHY connected
+	 * we must shutdown this chip to use bb pins
+	 */
+	struct gpio_desc	gpios[CPLD_MAX_GPIOS];
+};
+
+static void mdio_bb_active_mdio(struct renesas_v3msk_sysreset_priv *priv)
+{
+	dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
+
+static void mdio_bb_tristate_mdio(struct renesas_v3msk_sysreset_priv *priv)
+{
+	dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_IN);
+}
+
+static void mdio_bb_set_mdio(struct renesas_v3msk_sysreset_priv *priv, int val)
+{
+	dm_gpio_set_value(&priv->mosi, val);
+}
+
+static int mdio_bb_get_mdio(struct renesas_v3msk_sysreset_priv *priv)
+{
+	return dm_gpio_get_value(&priv->miso);
+}
+
+static void mdio_bb_set_mdc(struct renesas_v3msk_sysreset_priv *priv, int val)
+{
+	dm_gpio_set_value(&priv->mdc, val);
+}
+
+static void mdio_bb_delay(void)
+{
+	udelay(MDIO_DELAY);
+}
+
+/* Send the preamble, address, and register (common to read and write) */
+static void mdio_bb_pre(struct renesas_v3msk_sysreset_priv *priv,
+			u8 op, u8 addr, u8 reg)
+{
+	int i;
+
+	/* 32-bit preamble */
+	mdio_bb_active_mdio(priv);
+	mdio_bb_set_mdio(priv, 1);
+	for (i = 0; i < 32; i++) {
+		mdio_bb_set_mdc(priv, 0);
+		mdio_bb_delay();
+		mdio_bb_set_mdc(priv, 1);
+		mdio_bb_delay();
+	}
+	/* send the ST (2-bits of '01') */
+	mdio_bb_set_mdio(priv, 0);
+	mdio_bb_set_mdc(priv, 0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(priv, 1);
+	mdio_bb_delay();
+	mdio_bb_set_mdio(priv, 1);
+	mdio_bb_set_mdc(priv, 0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(priv, 1);
+	mdio_bb_delay();
+	/* send the OP (2-bits of Opcode: '10'-read, '01'-write) */
+	mdio_bb_set_mdio(priv, op >> 1);
+	mdio_bb_set_mdc(priv, 0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(priv, 1);
+	mdio_bb_delay();
+	mdio_bb_set_mdio(priv, op & 1);
+	mdio_bb_set_mdc(priv, 0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(priv, 1);
+	mdio_bb_delay();
+	/* send the PA5 (5-bits of PHY address) */
+	for (i = 0; i < 5; i++) {
+		mdio_bb_set_mdio(priv, addr & 0x10); /* MSB first */
+		mdio_bb_set_mdc(priv, 0);
+		mdio_bb_delay();
+		mdio_bb_set_mdc(priv, 1);
+		mdio_bb_delay();
+		addr <<= 1;
+	}
+	/* send the RA5 (5-bits of register address) */
+	for (i = 0; i < 5; i++) {
+		mdio_bb_set_mdio(priv, reg & 0x10); /* MSB first */
+		mdio_bb_set_mdc(priv, 0);
+		mdio_bb_delay();
+		mdio_bb_set_mdc(priv, 1);
+		mdio_bb_delay();
+		reg <<= 1;
+	}
+}
+
+static int mdio_bb_read(struct renesas_v3msk_sysreset_priv *priv,
+			u8 addr, u8 reg)
+{
+	int i;
+	u16 data = 0;
+
+	mdio_bb_pre(priv, 2, addr, reg);
+	/* tri-state MDIO */
+	mdio_bb_tristate_mdio(priv);
+	/* read TA (2-bits of turn-around, last bit must be '0') */
+	mdio_bb_set_mdc(priv, 0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(priv, 1);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(priv, 0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(priv, 1);
+	mdio_bb_delay();
+	/* check the turnaround bit: the PHY should drive line to zero */
+	if (mdio_bb_get_mdio(priv) != 0) {
+		printf("PHY didn't drive TA low\n");
+		for (i = 0; i < 32; i++) {
+			mdio_bb_set_mdc(priv, 0);
+			mdio_bb_delay();
+			mdio_bb_set_mdc(priv, 1);
+			mdio_bb_delay();
+		}
+		/* There is no PHY, set value to 0xFFFF */
+		return 0xFFFF;
+	}
+	mdio_bb_set_mdc(priv, 0);
+	mdio_bb_delay();
+	/* read 16-bits of data */
+	for (i = 0; i < 16; i++) {
+		mdio_bb_set_mdc(priv, 1);
+		mdio_bb_delay();
+		data <<= 1;
+		data |= mdio_bb_get_mdio(priv);
+		mdio_bb_set_mdc(priv, 0);
+		mdio_bb_delay();
+	}
+
+	mdio_bb_set_mdc(priv, 1);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(priv, 0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(priv, 1);
+	mdio_bb_delay();
+
+	debug("cpld_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, data);
+
+	return data;
+}
+
+static void mdio_bb_write(struct renesas_v3msk_sysreset_priv *priv,
+			  u8 addr, u8 reg, u16 val)
+{
+	int i;
+
+	mdio_bb_pre(priv, 1, addr, reg);
+	/* send the TA (2-bits of turn-around '10') */
+	mdio_bb_set_mdio(priv, 1);
+	mdio_bb_set_mdc(priv, 0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(priv, 1);
+	mdio_bb_delay();
+	mdio_bb_set_mdio(priv, 0);
+	mdio_bb_set_mdc(priv, 0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(priv, 1);
+	mdio_bb_delay();
+	/* write 16-bits of data */
+	for (i = 0; i < 16; i++) {
+		mdio_bb_set_mdio(priv, val & 0x8000); /* MSB first */
+		mdio_bb_set_mdc(priv, 0);
+		mdio_bb_delay();
+		mdio_bb_set_mdc(priv, 1);
+		mdio_bb_delay();
+		val <<= 1;
+	}
+	/* tri-state MDIO */
+	mdio_bb_tristate_mdio(priv);
+	mdio_bb_set_mdc(priv, 0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(priv, 1);
+	mdio_bb_delay();
+}
+
+static u16 cpld_read(struct udevice *dev, u16 addr)
+{
+	struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
+
+	/* random flash reads require 2 reads: first read is unreliable */
+	if (addr >= CPLD_ADDR_PCB_VERSION)
+		mdio_bb_read(priv, addr >> 5, addr & 0x1f);
+
+	return mdio_bb_read(priv, addr >> 5, addr & 0x1f);
+}
+
+static void cpld_write(struct udevice *dev, u16 addr, u16 data)
+{
+	struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
+
+	mdio_bb_write(priv, addr >> 5, addr & 0x1f, data);
+}
+
+static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct udevice *dev;
+	u16 addr, val;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
+					  DM_DRIVER_GET(sysreset_renesas_v3msk),
+					  &dev);
+	if (ret)
+		return ret;
+
+	if (argc == 2 && strcmp(argv[1], "info") == 0) {
+		printf("Product:                0x%08x\n",
+		       (cpld_read(dev, CPLD_ADDR_PRODUCT_H) << 16) |
+			cpld_read(dev, CPLD_ADDR_PRODUCT_L));
+		printf("CPLD version:           0x%08x\n",
+		       (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y) << 16) |
+			cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
+		printf("Mode setting (MD0..26): 0x%08x\n",
+		       (cpld_read(dev, CPLD_ADDR_MODE_APPLIED_H) << 16) |
+			cpld_read(dev, CPLD_ADDR_MODE_APPLIED_L));
+		printf("DIPSW (SW4, SW5):       0x%02x, 0x%x\n",
+		       (cpld_read(dev, CPLD_ADDR_DIPSW) & 0xff) ^ 0xff,
+		       (cpld_read(dev, CPLD_ADDR_DIPSW) >> 8) ^ 0xf);
+		printf("Power config:           0x%08x\n",
+		       cpld_read(dev, CPLD_ADDR_POWER_CFG));
+		printf("Periferals config:      0x%08x\n",
+		       (cpld_read(dev, CPLD_ADDR_PERI_CFG2) << 16) |
+			cpld_read(dev, CPLD_ADDR_PERI_CFG1));
+		printf("PCB version:            %d.%d\n",
+		       cpld_read(dev, CPLD_ADDR_PCB_VERSION) >> 8,
+		       cpld_read(dev, CPLD_ADDR_PCB_VERSION) & 0xff);
+		printf("SOC version:            %d.%d\n",
+		       cpld_read(dev, CPLD_ADDR_SOC_VERSION) >> 8,
+		       cpld_read(dev, CPLD_ADDR_SOC_VERSION) & 0xff);
+		printf("PCB S/N:                %d\n",
+		       (cpld_read(dev, CPLD_ADDR_PCB_SN_H) << 16) |
+			cpld_read(dev, CPLD_ADDR_PCB_SN_L));
+		return 0;
+	}
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	if (!(addr >= CPLD_ADDR_PRODUCT_L && addr <= CPLD_ADDR_LEDS)) {
+		printf("cpld invalid addr\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (argc == 3 && strcmp(argv[1], "read") == 0) {
+		printf("0x%x\n", cpld_read(dev, addr));
+	} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+		val = simple_strtoul(argv[3], NULL, 16);
+		cpld_write(dev, addr, val);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(cpld, 4, 1, do_cpld,
+	   "CPLD access",
+	   "info\n"
+	   "cpld read addr\n"
+	   "cpld write addr val\n"
+);
+
+static int renesas_v3msk_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	cpld_write(dev, CPLD_ADDR_RESET, 1);
+
+	return -EINPROGRESS;
+}
+
+static int renesas_v3msk_sysreset_probe(struct udevice *dev)
+{
+	struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
+
+	if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
+				 GPIOD_IS_IN))
+		return -EINVAL;
+
+	if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
+				 GPIOD_IS_OUT))
+		return -EINVAL;
+
+	if (gpio_request_by_name(dev, "gpio-mdc", 0, &priv->mdc,
+				 GPIOD_IS_OUT))
+		return -EINVAL;
+
+	if (gpio_request_by_name(dev, "gpio-enablez", 0, &priv->enablez,
+				 GPIOD_IS_OUT))
+		return -EINVAL;
+
+	/* V3MSK Videobox Mini board has CANFD PHY connected
+	 * we must shutdown this chip to use bb pins
+	 */
+	gpio_request_list_by_name(dev, "gpios", priv->gpios, CPLD_MAX_GPIOS,
+				  GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	return 0;
+}
+
+static struct sysreset_ops renesas_v3msk_sysreset = {
+	.request	= renesas_v3msk_sysreset_request,
+};
+
+static const struct udevice_id renesas_v3msk_sysreset_ids[] = {
+	{ .compatible = "renesas,v3msk-cpld" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sysreset_renesas_v3msk) = {
+	.name		= "renesas_v3msk_sysreset",
+	.id		= UCLASS_SYSRESET,
+	.ops		= &renesas_v3msk_sysreset,
+	.probe		= renesas_v3msk_sysreset_probe,
+	.of_match	= renesas_v3msk_sysreset_ids,
+	.priv_auto	= sizeof(struct renesas_v3msk_sysreset_priv),
+};
diff --git a/board/renesas/whitehawk/MAINTAINERS b/board/renesas/whitehawk/MAINTAINERS
new file mode 100644
index 0000000000..f893abff1a
--- /dev/null
+++ b/board/renesas/whitehawk/MAINTAINERS
@@ -0,0 +1,7 @@
+WHITEHAWK BOARD
+M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
+S:	Maintained
+F:	arch/arm/dts/r8a779g0*
+F:	board/renesas/whitehawk/
+F:	configs/r8a779g0_whitehawk_defconfig
+F:	include/configs/whitehawk.h
diff --git a/board/renesas/whitehawk/whitehawk.c b/board/renesas/whitehawk/whitehawk.c
index 19f09e009b..32284b2ecc 100644
--- a/board/renesas/whitehawk/whitehawk.c
+++ b/board/renesas/whitehawk/whitehawk.c
@@ -65,8 +65,3 @@ int board_init(void)
 
 	return 0;
 }
-
-void reset_cpu(void)
-{
-	writel(RST_SPRES, RST_SRESCR0);
-}
diff --git a/board/rockchip/evb_rk3229/README b/board/rockchip/evb_rk3229/README
index 9068225e27..a8dcc40f09 100644
--- a/board/rockchip/evb_rk3229/README
+++ b/board/rockchip/evb_rk3229/README
@@ -13,25 +13,23 @@ Compile the OP-TEE
 
   > cd optee_os
   > make clean
-  > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x
-  Get tee.bin in this step, copy it to U-Boot root dir:
-  > cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin
+  > make CROSS_COMPILE=arm-none-eabi- PLATFORM=rockchip-rk322x
+  Get tee-raw.bin in this step, copy it to U-Boot root dir:
+  > cp out/arm-plat-rockchip/core/tee-raw.bin ../u-boot/tee.bin
 
 Compile the U-Boot
 ==================
 
   > cd ../u-boot
-  > export CROSS_COMPILE=arm-linux-gnueabihf-
   > make evb-rk3229_defconfig
-  > make
-  > make u-boot.itb
+  > TEE=tee.bin CROSS_COMPILE=arm-linux-gnueabihf- make
 
-  Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step.
+  Get u-boot-rockchip.bin in this step.
 
 Compile the rkdeveloptool
 =======================
   Follow instructions in latest README
-  > cd ../rkflashtool
+  > cd ../rkdeveloptool
   > autoreconf -i
   > ./configure
   > make
@@ -42,30 +40,56 @@ Compile the rkdeveloptool
 Both origin binaries and Tool are ready now, choose either option 1 or
 option 2 to deploy U-Boot.
 
-Package the image
-=================
-
-  > cd ../u-boot
-  > tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img
-  > cat spl/u-boot-spl.bin >> idbloader.img
-
-  Get idbloader.img in this step.
-
 Flash the image to eMMC
 =======================
 Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
   > cd ..
-  > rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin
-  > rkdeveloptool wl 64 u-boot/idbloader.img
-  > rkdeveloptool wl 0x4000 u-boot/u-boot.itb
-  > rkdeveloptool rd
+  > rkdeveloptool/rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin
+  > rkdeveloptool/rkdeveloptool wl 64 u-boot/u-boot-rockchip.bin
+  > rkdeveloptool/rkdeveloptool rd
 
 Flash the image to SD card
 ==========================
-  > dd if=u-boot/idbloader.img of=/dev/sdb seek=64
-  > dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384
+  > dd if=u-boot/u-boot-rockchip.bin of=/dev/sdb seek=64
+
+You should be able to get U-Boot log message with OP-TEE boot info:
+
+U-Boot TPL 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51)
+Trying to boot from BOOTROM
+Returning to boot ROM...
+
+U-Boot SPL 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51 +0200)
+Trying to boot from MMC1
+I/TC:
+I/TC: Non-secure external DT found
+I/TC: Switching console to device: /serial@11030000
+I/TC: OP-TEE version: 3.22.0-27-g893a762d1 (gcc version 10.3.1 20210621 (release) (15:10.3-2021.07-4)) #1 Sat Jul 15 12:14:36 UTC 2023 arm
+I/TC: WARNING: This OP-TEE configuration might be insecure!
+I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
+I/TC: Primary CPU initializing
+M/TC: Not protecting region 1: 0x68400000-0x68600000
+I/TC: Primary CPU switching to normal world boot
+
+
+U-Boot 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51 +0200)
+
+Model: Rockchip RK3229 Evaluation board
+DRAM:  1 GiB (effective 992 MiB)
+Core:  113 devices, 16 uclasses, devicetree: separate
+MMC:   mmc@30000000: 1, mmc@30020000: 0
+Loading Environment from MMC... Card did not respond to voltage select! : -110
+*** Warning - No block device, using default environment
+
+In:    serial@11030000
+Out:   serial@11030000
+Err:   serial@11030000
+Model: Rockchip RK3229 Evaluation board
+Net:
+Warning: ethernet@30200000 (eth0) using random MAC address - 72:65:2b:f1:c5:0a
+eth0: ethernet@30200000
+Hit any key to stop autoboot:  0
+=>
 
-You should be able to get U-Boot log message with OP-TEE boot info.
 
 For more detail, please reference to:
 http://opensource.rock-chips.com/wiki_Boot_option
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS
index 3c46613ab5..8a19eb373d 100644
--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -18,6 +18,18 @@ F:      configs/nanopi-r2s-rk3328_defconfig
 F:      arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
 F:      arch/arm/dts/rk3328-nanopi-r2s.dts
 
+ORANGEPI-R1-PLUS-RK3328
+M:      Tianling Shen <cnsztl@gmail.com>
+S:      Maintained
+F:      configs/orangepi-r1-plus-rk3328_defconfig
+F:      arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+
+ORANGEPI-R1-PLUS-LTS-RK3328
+M:      Tianling Shen <cnsztl@gmail.com>
+S:      Maintained
+F:      configs/orangepi-r1-plus-lts-rk3328_defconfig
+F:      arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+
 ROC-RK3328-CC
 M:      Loic Devulder <ldevulder@suse.com>
 M:      Chen-Yu Tsai <wens@csie.org>
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS
index 5be58f80f9..c7e412b54e 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -80,6 +80,18 @@ F:	configs/orangepi-rk3399_defconfig
 F:	arch/arm/dts/rk3399-u-boot.dtsi
 F:	arch/arm/dts/rk3399-orangepi-u-boot.dtsi
 
+ROCK-4C+
+M:	FUKAUMI Naoki <naoki@radxa.com>
+S:	Maintained
+F:	configs/rock-4c-plus-rk3399_defconfig
+F:	arch/arm/dts/rk3399-rock-4c-plus.dts
+
+ROCK-4SE
+M:	Christopher Obbard <chris.obbard@collabora.com>
+S:	Maintained
+F:	configs/rock-4se-rk3399_defconfig
+F:	arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
+
 ROCK-PI-4
 M:	Akash Gajjar <akash@openedev.com>
 M:	Jagan Teki <jagan@amarulasolutions.com>
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
index c99ffdd75e..3c773d0930 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -18,10 +18,10 @@
 static struct efi_fw_image fw_images[ROCKPI4_UPDATABLE_IMAGES] = {0};
 
 struct efi_capsule_update_info update_info = {
+	.num_images = ROCKPI4_UPDATABLE_IMAGES,
 	.images = fw_images,
 };
 
-u8 num_image_type_guids = ROCKPI4_UPDATABLE_IMAGES;
 #endif
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS
index 6b2e7c7575..cc9eb432a8 100644
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -1,20 +1,57 @@
 EVB-RK3568
-M:      Joseph Chen <chenjh@rock-chips.com>
-S:      Maintained
-F:      board/rockchip/evb_rk3568
-F:      include/configs/evb_rk3568.h
-F:      configs/evb-rk3568_defconfig
-F:	arch/arm/dts/rk3568-evb-boot.dtsi
+M:	Joseph Chen <chenjh@rock-chips.com>
+S:	Maintained
+F:	board/rockchip/evb_rk3568
+F:	include/configs/evb_rk3568.h
+F:	configs/evb-rk3568_defconfig
+F:	arch/arm/dts/rk3568-evb-u-boot.dtsi
 F:	arch/arm/dts/rk3568-evb.dts
 
-RADXA-CM3
+LUBANCAT-2
+M:	Andy Yan <andyshrk@163.com>
+S:	Maintained
+F:	configs/lubancat-2-rk3568_defconfig
+F:	arch/arm/dts/rk3568-lubancat-2.dts
+F:	arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
+
+NANOPI-R5C
+M:	Tianling Shen <cnsztl@gmail.com>
+R:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	configs/nanopi-r5c-rk3568_defconfig
+F:	arch/arm/dts/rk3568-nanopi-r5c.dts
+F:	arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
+
+NANOPI-R5S
+M:	Tianling Shen <cnsztl@gmail.com>
+R:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	configs/nanopi-r5s-rk3568_defconfig
+F:	arch/arm/dts/rk3568-nanopi-r5s.dts
+F:	arch/arm/dts/rk3568-nanopi-r5s.dtsi
+F:	arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
+
+RADXA-CM3-IO
 M:	Jagan Teki <jagan@amarulasolutions.com>
+R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/radxa-cm3-io-rk3566_defconfig
+F:	arch/arm/dts/rk3566-radxa-cm3.dtsi
+F:	arch/arm/dts/rk3566-radxa-cm3-io.dts
+F:	arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+
+RADXA-E25
+M:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	configs/radxa-e25-rk3568_defconfig
+F:	arch/arm/dts/rk3568-radxa-cm3i.dtsi
+F:	arch/arm/dts/rk3568-radxa-e25.dts
+F:	arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
 
 ROCK-3A
-M:      Akash Gajjar <gajjar04akash@gmail.com>
-S:      Maintained
-F:      configs/rock-3a-rk3568_defconfig
-F:      arch/arm/dts/rk3568-rock-3a.dts
-F:      arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+M:	Akash Gajjar <gajjar04akash@gmail.com>
+R:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	configs/rock-3a-rk3568_defconfig
+F:	arch/arm/dts/rk3568-rock-3a.dts
+F:	arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS
index 7b7df3c5a8..6b2c257a17 100644
--- a/board/rockchip/evb_rk3588/MAINTAINERS
+++ b/board/rockchip/evb_rk3588/MAINTAINERS
@@ -4,4 +4,5 @@ S:	Maintained
 F:	board/rockchip/evb_rk3588
 F:	include/configs/evb_rk3588.h
 F:	configs/evb-rk3588_defconfig
-F:	arch/arm/dts/rk3588-evb-u-boot.dtsi
+F:	arch/arm/dts/rk3588-evb1-v10.dts
+F:	arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
diff --git a/board/ronetix/imx7-cm/MAINTAINERS b/board/ronetix/imx7-cm/MAINTAINERS
index 184c887463..158c2b7cd0 100644
--- a/board/ronetix/imx7-cm/MAINTAINERS
+++ b/board/ronetix/imx7-cm/MAINTAINERS
@@ -1,6 +1,6 @@
 i.MX7-CM BOARD
 M:	Ilko Iliev <iliev@ronetix.com>
 S:	Maintained
-F:	board/ronetix/imx7_cm/
-F:	include/configs/imx7_cm.h
-F:	configs/imx7_cm_defconfig
\ No newline at end of file
+F:	board/ronetix/imx7-cm/
+F:	include/configs/imx7-cm.h
+F:	configs/imx7_cm_defconfig
diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c
index 2e44bdf0df..9d58860451 100644
--- a/board/sandbox/sandbox.c
+++ b/board/sandbox/sandbox.c
@@ -11,16 +11,18 @@
 #include <efi.h>
 #include <efi_loader.h>
 #include <env_internal.h>
+#include <extension_board.h>
 #include <init.h>
 #include <led.h>
+#include <malloc.h>
+#include <mapmem.h>
 #include <os.h>
+#include <acpi/acpi_table.h>
 #include <asm/global_data.h>
 #include <asm/test.h>
 #include <asm/u-boot-sandbox.h>
 #include <linux/kernel.h>
-#include <malloc.h>
-
-#include <extension_board.h>
+#include <linux/sizes.h>
 
 /*
  * Pointer to initial global data area
@@ -67,10 +69,10 @@ struct efi_fw_image fw_images[] = {
 struct efi_capsule_update_info update_info = {
 	.dfu_string = "sf 0:0=u-boot-bin raw 0x100000 0x50000;"
 		"u-boot-env raw 0x150000 0x200000",
+	.num_images = ARRAY_SIZE(fw_images),
 	.images = fw_images,
 };
 
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
 
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
@@ -154,6 +156,8 @@ int extension_board_scan(struct list_head *extension_list)
 int board_late_init(void)
 {
 	struct udevice *dev;
+	ulong addr, end;
+	void *ptr;
 	int ret;
 
 	ret = uclass_first_device_err(UCLASS_CROS_EC, &dev);
@@ -166,6 +170,18 @@ int board_late_init(void)
 		panic("Cannot init cros-ec device");
 		return -1;
 	}
+
+	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
+		/* Reserve 64K for ACPI tables, aligned to a 4K boundary */
+		ptr = memalign(SZ_4K, SZ_64K);
+		addr = map_to_sysmem(ptr);
+
+		/* Generate ACPI tables */
+		end = write_acpi_tables(addr);
+		gd->arch.table_start = addr;
+		gd->arch.table_end = addr;
+	}
+
 	return 0;
 }
 #endif
diff --git a/board/schneider/rzn1-snarc/MAINTAINERS b/board/schneider/rzn1-snarc/MAINTAINERS
new file mode 100644
index 0000000000..a39b96c116
--- /dev/null
+++ b/board/schneider/rzn1-snarc/MAINTAINERS
@@ -0,0 +1,9 @@
+RZN1 SNARC
+M:	Ralph Siemsen <ralph.siemsen@linaro.org>
+S:	Maintained
+F:	board/schneider/rzn1-snarc/
+F:	arch/arm/dts/r9a06g032-ddr.dtsi
+F:	arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
+F:	arch/arm/dts/r9a06g032-rzn1-snarc.dts
+F:	configs/rzn1_snarc_defconfig
+F:	include/configs/rzn1-snarc.h
diff --git a/board/seeed/npi_imx6ull/MAINTAINERS b/board/seeed/npi_imx6ull/MAINTAINERS
index c6a915c79b..ddf49849de 100644
--- a/board/seeed/npi_imx6ull/MAINTAINERS
+++ b/board/seeed/npi_imx6ull/MAINTAINERS
@@ -4,6 +4,6 @@ S:	Maintained
 F:	arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts
 F:	arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi
 F:	arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi
-F:	board/seeed/npi-imx6ull/
+F:	board/seeed/npi_imx6ull/
 F:	configs/seeed_npi_imx6ull_defconfig
 F:	include/configs/npi_imx6ull.h
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c
index a0c62e0fc4..924c88e8fa 100644
--- a/board/siemens/capricorn/board.c
+++ b/board/siemens/capricorn/board.c
@@ -147,7 +147,7 @@ static void enet_device_phy_reset(void)
 int setup_gpr_fec(void)
 {
 	sc_ipc_t ipc_handle = -1;
-	sc_err_t err = 0;
+	int err = 0;
 	unsigned int test;
 
 	/*
@@ -175,35 +175,35 @@ int setup_gpr_fec(void)
 	 */
 
 	err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1);
-	if (err != SC_ERR_NONE)
+	if (err)
 		printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK);
 
 	sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
 	debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test);
 
 	err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0);
-	if (err != SC_ERR_NONE)
+	if (err)
 		printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV);
 
 	sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, &test);
 	debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test);
 
 	err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0);
-	if (err != SC_ERR_NONE)
+	if (err)
 		printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50);
 
 	sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
 	debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test);
 
 	err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1);
-	if (err != SC_ERR_NONE)
+	if (err)
 		printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125);
 
 	sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
 	debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test);
 
 	err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1);
-	if (err != SC_ERR_NONE)
+	if (err)
 		printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125);
 
 	sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, &test);
diff --git a/board/siemens/iot2050/Kconfig b/board/siemens/iot2050/Kconfig
index e66b2427d9..a6170aae80 100644
--- a/board/siemens/iot2050/Kconfig
+++ b/board/siemens/iot2050/Kconfig
@@ -1,40 +1,22 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
-# Copyright (c) Siemens AG, 2018-2022
+# Copyright (c) Siemens AG, 2018-2023
 #
 # Authors:
 #   Le Jin <le.jin@siemens.com>
 #   Jan Kiszka <jan.kiszka@siemens.com>
 
-choice
-        prompt "Siemens SIMATIC IOT2050 boards"
-        optional
-
-config TARGET_IOT2050_A53_PG1
-	bool "IOT2050 PG1 running on A53"
-	select IOT2050_A53_COMMON
-	help
-	  This builds U-Boot for the Product Generation 1 (PG1) of the IOT2050
-	  devices.
-
-config TARGET_IOT2050_A53_PG2
-	bool "IOT2050 PG2 running on A53"
-	select IOT2050_A53_COMMON
-	help
-	  This builds U-Boot for the Product Generation 2 (PG2) of the IOT2050
-	  devices.
-
-endchoice
-
-config IOT2050_A53_COMMON
-	bool
+config TARGET_IOT2050_A53
+	bool "IOT2050 running on A53"
 	select ARM64
 	select SOC_K3_AM654
 	select BOARD_LATE_INIT
 	select SYS_DISABLE_DCACHE_OPS
 	select BINMAN
+	help
+	  This builds U-Boot for the IOT2050 devices.
 
-if IOT2050_A53_COMMON
+if TARGET_IOT2050_A53
 
 config SYS_BOARD
 	default "iot2050"
diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index 2653e10745..15f5310c7b 100644
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Board specific initialization for IOT2050
- * Copyright (c) Siemens AG, 2018-2022
+ * Copyright (c) Siemens AG, 2018-2023
  *
  * Authors:
  *   Le Jin <le.jin@siemens.com>
@@ -147,21 +147,28 @@ static void set_pinvalue(const char *gpio_name, const char *label, int value)
 	dm_gpio_set_value(&gpio, value);
 }
 
-static bool board_is_m2(void)
+static bool board_is_advanced(void)
 {
 	struct iot2050_info *info = IOT2050_INFO_DATA;
 
-	return IS_ENABLED(CONFIG_TARGET_IOT2050_A53_PG2) &&
-		info->magic == IOT2050_INFO_MAGIC &&
-		strcmp((char *)info->name, "IOT2050-ADVANCED-M2") == 0;
+	return info->magic == IOT2050_INFO_MAGIC &&
+		strstr((char *)info->name, "IOT2050-ADVANCED") != NULL;
 }
 
-static bool board_is_advanced(void)
+static bool board_is_sr1(void)
 {
 	struct iot2050_info *info = IOT2050_INFO_DATA;
 
 	return info->magic == IOT2050_INFO_MAGIC &&
-		strstr((char *)info->name, "IOT2050-ADVANCED") != NULL;
+		strstr((char *)info->name, "-PG2") != NULL;
+}
+
+static bool board_is_m2(void)
+{
+	struct iot2050_info *info = IOT2050_INFO_DATA;
+
+	return !board_is_sr1() && info->magic == IOT2050_INFO_MAGIC &&
+		strcmp((char *)info->name, "IOT2050-ADVANCED-M2") == 0;
 }
 
 static void remove_mmc1_target(void)
@@ -210,14 +217,14 @@ void set_board_info_env(void)
 	}
 
 	if (board_is_advanced()) {
-		if (IS_ENABLED(CONFIG_TARGET_IOT2050_A53_PG1))
+		if (board_is_sr1())
 			fdtfile = "ti/k3-am6548-iot2050-advanced.dtb";
 		else if(board_is_m2())
 			fdtfile = "ti/k3-am6548-iot2050-advanced-m2.dtb";
 		else
 			fdtfile = "ti/k3-am6548-iot2050-advanced-pg2.dtb";
 	} else {
-		if (IS_ENABLED(CONFIG_TARGET_IOT2050_A53_PG1))
+		if (board_is_sr1())
 			fdtfile = "ti/k3-am6528-iot2050-basic.dtb";
 		else
 			fdtfile = "ti/k3-am6528-iot2050-basic-pg2.dtb";
diff --git a/board/siemens/iot2050/iot2050.env b/board/siemens/iot2050/iot2050.env
index 02958798b4..caa9f80e3f 100644
--- a/board/siemens/iot2050/iot2050.env
+++ b/board/siemens/iot2050/iot2050.env
@@ -6,6 +6,8 @@
  *   Jan Kiszka <jan.kiszka@siemens.com>
  */
 
+#include <env/ti/ti_armv7_common.env>
+
 usb_pgood_delay=900
 
 watchdog_timeout_ms=CONFIG_WATCHDOG_TIMEOUT_MSECS
diff --git a/board/sifive/unmatched/MAINTAINERS b/board/sifive/unmatched/MAINTAINERS
index 94c9510bfa..e601a0f328 100644
--- a/board/sifive/unmatched/MAINTAINERS
+++ b/board/sifive/unmatched/MAINTAINERS
@@ -1,6 +1,5 @@
 SiFive HiFive Unmatched FU740 BOARD
 M:	Paul Walmsley <paul.walmsley@sifive.com>
-M:	Pragnesh Patel <pragnesh.patel@sifive.com>
 M:	Green Wan <green.wan@sifive.com>
 S:	Maintained
 F:	board/sifive/unmatched/
diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
index 2d212ec5a3..d34ea4be71 100644
--- a/board/sipeed/maix/Kconfig
+++ b/board/sipeed/maix/Kconfig
@@ -34,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS
 	imply SMP
 	imply DM_SERIAL
 	imply SIFIVE_SERIAL
-	imply SIFIVE_CLINT
+	imply RISCV_ACLINT
 	imply POWER_DOMAIN
 	imply SIMPLE_PM_BUS
 	imply CLK_K210
diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile
index 4a46de995a..1acd067a7e 100644
--- a/board/socionext/developerbox/Makefile
+++ b/board/socionext/developerbox/Makefile
@@ -7,3 +7,4 @@
 #
 
 obj-y	:= developerbox.o
+obj-$(CONFIG_FWU_MDATA_MTD) += fwu_plat.o
diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c
index 16e14d4f7f..204e5a41a5 100644
--- a/board/socionext/developerbox/developerbox.c
+++ b/board/socionext/developerbox/developerbox.c
@@ -20,6 +20,13 @@
 
 #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
 struct efi_fw_image fw_images[] = {
+#if CONFIG_IS_ENABLED(FWU_MULTI_BANK_UPDATE)
+	{
+		.image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID,
+		.fw_name = u"DEVELOPERBOX-FIP",
+		.image_index = 1,
+	},
+#else
 	{
 		.image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID,
 		.fw_name = u"DEVELOPERBOX-UBOOT",
@@ -35,16 +42,17 @@ struct efi_fw_image fw_images[] = {
 		.fw_name = u"DEVELOPERBOX-OPTEE",
 		.image_index = 3,
 	},
+#endif
 };
 
 struct efi_capsule_update_info update_info = {
 	.dfu_string = "mtd nor1=u-boot.bin raw 200000 100000;"
 			"fip.bin raw 180000 78000;"
 			"optee.bin raw 500000 100000",
+	.num_images = ARRAY_SIZE(fw_images),
 	.images = fw_images,
 };
 
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
 
 static struct mm_region sc2a11_mem_map[] = {
diff --git a/board/socionext/developerbox/fwu_plat.c b/board/socionext/developerbox/fwu_plat.c
new file mode 100644
index 0000000000..e724e702bd
--- /dev/null
+++ b/board/socionext/developerbox/fwu_plat.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <efi_loader.h>
+#include <fwu.h>
+#include <fwu_mdata.h>
+#include <memalign.h>
+#include <mtd.h>
+
+#define DFU_ALT_BUF_LEN 256
+
+/* Generate dfu_alt_info from partitions */
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+	struct mtd_info *mtd;
+	int ret;
+
+	memset(buf, 0, sizeof(buf));
+
+	mtd_probe_devices();
+
+	mtd = get_mtd_device_nm("nor1");
+	if (IS_ERR_OR_NULL(mtd))
+		return;
+
+	ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd);
+	if (ret < 0) {
+		log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret);
+		return;
+	}
+	log_debug("Make dfu_alt_info: '%s'\n", buf);
+
+	env_set("dfu_alt_info", buf);
+}
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 02e6afb099..1d63c81a9c 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -13,7 +13,6 @@
 #include <common.h>
 #include <clock_legacy.h>
 #include <env.h>
-#include <env_internal.h>
 #include <init.h>
 #include <pci.h>
 #include <uuid.h>
@@ -222,19 +221,3 @@ int get_serial_clock(void)
 {
 	return 333333330;
 }
-
-enum env_location env_get_location(enum env_operation op, int prio)
-{
-	if (op == ENVOP_SAVE || op == ENVOP_ERASE)
-		return ENVL_FLASH;
-
-	switch (prio) {
-	case 0:
-		return ENVL_NOWHERE;
-	case 1:
-		return ENVL_FLASH;
-	default:
-		return ENVL_UNKNOWN;
-	}
-	return ENVL_UNKNOWN;
-}
diff --git a/board/softing/vining_fpga/MAINTAINERS b/board/softing/vining_fpga/MAINTAINERS
index c2002fe3ce..ed44b09f32 100644
--- a/board/softing/vining_fpga/MAINTAINERS
+++ b/board/softing/vining_fpga/MAINTAINERS
@@ -1,5 +1,6 @@
 VINING FPGA BOARD
 M:	Marek Vasut <marex@denx.de>
 S:	Maintained
+F:	board/softing/vining_fpga/
 F:	include/configs/socfpga_vining_fpga.h
 F:	configs/socfpga_vining_fpga_defconfig
diff --git a/board/solidrun/clearfog/MAINTAINERS b/board/solidrun/clearfog/MAINTAINERS
index 6646d96206..6b2d5d1146 100644
--- a/board/solidrun/clearfog/MAINTAINERS
+++ b/board/solidrun/clearfog/MAINTAINERS
@@ -1,7 +1,9 @@
 CLEARFOG BOARD
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
-F:	board/soldrun/clearfog/
+F:	board/solidrun/clearfog/
 F:	include/configs/clearfog.h
 F:	configs/clearfog_defconfig
 F:	configs/clearfog_gt_8k_defconfig
+F:	configs/clearfog_sata_defconfig
+F:	configs/clearfog_spi_defconfig
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index cb14c2f30c..6fa5cf4d27 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -275,9 +275,8 @@ int board_early_init_f(void)
 {
 	setup_iomux_uart();
 
-#ifdef CONFIG_SATA
-	setup_sata();
-#endif
+	if (CONFIG_IS_ENABLED(SATA))
+		setup_sata();
 	setup_fec();
 
 	return 0;
diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig
index aba3590866..c1c254d073 100644
--- a/board/st/common/Kconfig
+++ b/board/st/common/Kconfig
@@ -6,72 +6,6 @@ config CMD_STBOARD
 	  This compile the stboard command to
 	  read and write the board in the OTP.
 
-config MTDPARTS_NAND0_BOOT
-	string "mtd boot partitions for nand0"
-	default "2m(fsbl),2m(ssbl1),2m(ssbl2)" if STM32MP15x_STM32IMAGE || \
-						  !TFABOOT
-	default "2m(fsbl),4m(fip1),4m(fip2)"
-	depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
-	help
-	  This define the partitions of nand0 used to build mtparts dynamically
-	  for boot from nand0.
-	  Each partition need to be aligned with the device erase block size,
-	  512KB is the max size for the NAND supported by stm32mp1 platform.
-	  The fsbl partition support multiple copy of the same binary, one by
-	  erase block.
-
-config MTDPARTS_NAND0_TEE
-	string "mtd tee partitions for nand0"
-	default "512k(teeh),512k(teed),512k(teex)"
-	depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE
-	help
-	  This define the tee partitions added in mtparts dynamically
-	  when tee is supported with boot from nand0.
-	  Each partition need to be aligned with the device erase block size,
-	  512KB is the max size for the NAND supported by stm32mp1 platform.
-
-config MTDPARTS_NOR0_BOOT
-	string "mtd boot partitions for nor0"
-	default "256k(fsbl1),256k(fsbl2),2m(ssbl),512k(u-boot-env)" if STM32MP15x_STM32IMAGE || \
-								       !TFABOOT
-	default "256k(fsbl1),256k(fsbl2),4m(fip),512k(u-boot-env)"
-	depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
-	help
-	  This define the partitions of nand0 used to build mtparts dynamically
-	  for boot from nor0.
-	  Each partition need to be aligned with the device erase block size,
-	  with 256KB we support all the NOR.
-	  U-Boot env partition (512kB) use 2 erase block for redundancy.
-
-config MTDPARTS_NOR0_TEE
-	string "mtd tee partitions for nor0"
-	default "256k(teeh),512k(teed),256k(teex)"
-	depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE
-	help
-	  This define the tee partitions added in mtparts dynamically
-	  when tee is supported with boot from nor0.
-
-config MTDPARTS_SPINAND0_BOOT
-	string "mtd boot partitions for spi-nand0"
-	default "2m(fsbl),2m(ssbl1),2m(ssbl2)" if STM32MP15x_STM32IMAGE || !TFABOOT
-	default "2m(fsbl),4m(fip1),4m(fip2)"
-	depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
-	help
-	  This define the partitions of nand0 used to build mtparts dynamically
-	  for boot from spi-nand0,
-	  512KB is the max size for the NAND supported by stm32mp1 platform.
-	  The fsbl partition support multiple copy of the same binary, one by
-	  erase block.
-
-config MTDPARTS_SPINAND0_TEE
-	string "mtd tee partitions for spi-nand0"
-	default "512k(teeh),512k(teed),512k(teex)"
-	depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE
-	help
-	  This define the tee partitions added in mtparts dynamically
-	  when tee is supported with boot from spi-nand0,
-	  512KB is the max size for the NAND supported by stm32mp1 platform.
-
 config DFU_ALT_RAM0
 	string "dfu for ram0"
 	default "uImage ram 0xc2000000 0x2000000;devicetree.dtb ram 0xc4000000 0x100000;uramdisk.image.gz ram 0xc4400000 0x10000000"
diff --git a/board/st/common/Makefile b/board/st/common/Makefile
index 65bbebd6ab..c960829726 100644
--- a/board/st/common/Makefile
+++ b/board/st/common/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o
 obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
 
 ifeq ($(CONFIG_ARCH_STM32MP),y)
-obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += stm32mp_mtdparts.o
 obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o
 endif
 
diff --git a/board/st/common/stm32mp_mtdparts.c b/board/st/common/stm32mp_mtdparts.c
deleted file mode 100644
index 67a56a2623..0000000000
--- a/board/st/common/stm32mp_mtdparts.c
+++ /dev/null
@@ -1,177 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
- */
-
-#include <common.h>
-#include <dfu.h>
-#include <dm.h>
-#include <env.h>
-#include <env_internal.h>
-#include <log.h>
-#include <mtd.h>
-#include <mtd_node.h>
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-#include <tee.h>
-#endif
-#include <asm/arch/stm32prog.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/global_data.h>
-
-#define MTDPARTS_LEN		256
-#define MTDIDS_LEN		128
-
-/*
- * Get a global data pointer
- */
-DECLARE_GLOBAL_DATA_PTR;
-
-/**
- * update the variables "mtdids" and "mtdparts" with boot, tee and user strings
- */
-static void board_set_mtdparts(const char *dev,
-			       char *mtdids,
-			       char *mtdparts,
-			       const char *boot,
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-			       const char *tee,
-#endif
-			       const char *user)
-{
-	/* mtdids: "<dev>=<dev>, ...." */
-	if (mtdids[0] != '\0')
-		strcat(mtdids, ",");
-	strcat(mtdids, dev);
-	strcat(mtdids, "=");
-	strcat(mtdids, dev);
-
-	/* mtdparts: "mtdparts=<dev>:<mtdparts_<dev>>;..." */
-	if (mtdparts[0] != '\0')
-		strncat(mtdparts, ";", MTDPARTS_LEN);
-	else
-		strcat(mtdparts, "mtdparts=");
-
-	strncat(mtdparts, dev, MTDPARTS_LEN);
-	strncat(mtdparts, ":", MTDPARTS_LEN);
-
-	if (boot) {
-		strncat(mtdparts, boot, MTDPARTS_LEN);
-		strncat(mtdparts, ",", MTDPARTS_LEN);
-	}
-
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-	if (tee) {
-		strncat(mtdparts, tee, MTDPARTS_LEN);
-		strncat(mtdparts, ",", MTDPARTS_LEN);
-	}
-#endif
-
-	strncat(mtdparts, user, MTDPARTS_LEN);
-}
-
-void board_mtdparts_default(const char **mtdids, const char **mtdparts)
-{
-	struct mtd_info *mtd;
-	struct udevice *dev;
-	static char parts[3 * MTDPARTS_LEN + 1];
-	static char ids[MTDIDS_LEN + 1];
-	static bool mtd_initialized;
-	bool nor, nand, spinand, serial;
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-	bool tee = false;
-#endif
-
-	if (mtd_initialized) {
-		*mtdids = ids;
-		*mtdparts = parts;
-		return;
-	}
-
-	nor = false;
-	nand = false;
-	spinand = false;
-	serial = false;
-
-	switch (get_bootmode() & TAMP_BOOT_DEVICE_MASK) {
-	case BOOT_SERIAL_UART:
-	case BOOT_SERIAL_USB:
-		serial = true;
-		if (IS_ENABLED(CONFIG_CMD_STM32PROG)) {
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-			tee = stm32prog_get_tee_partitions();
-#endif
-			nor = stm32prog_get_fsbl_nor();
-		}
-		nand = true;
-		spinand = true;
-		break;
-	case BOOT_FLASH_NAND:
-		nand = true;
-		break;
-	case BOOT_FLASH_SPINAND:
-		spinand = true;
-		break;
-	case BOOT_FLASH_NOR:
-		nor = true;
-		break;
-	default:
-		break;
-	}
-
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-	if (!serial && tee_find_device(NULL, NULL, NULL, NULL))
-		tee = true;
-#endif
-
-	memset(parts, 0, sizeof(parts));
-	memset(ids, 0, sizeof(ids));
-
-	/* probe all MTD devices */
-	for (uclass_first_device(UCLASS_MTD, &dev);
-	     dev;
-	     uclass_next_device(&dev)) {
-		log_debug("mtd device = %s\n", dev->name);
-	}
-
-	if (nand) {
-		mtd = get_mtd_device_nm("nand0");
-		if (!IS_ERR_OR_NULL(mtd)) {
-			board_set_mtdparts("nand0", ids, parts,
-					   CONFIG_MTDPARTS_NAND0_BOOT,
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-					   !nor && tee ? CONFIG_MTDPARTS_NAND0_TEE : NULL,
-#endif
-					   "-(UBI)");
-			put_mtd_device(mtd);
-		}
-	}
-
-	if (spinand) {
-		mtd = get_mtd_device_nm("spi-nand0");
-		if (!IS_ERR_OR_NULL(mtd)) {
-			board_set_mtdparts("spi-nand0", ids, parts,
-					   CONFIG_MTDPARTS_SPINAND0_BOOT,
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-					   !nor && tee ? CONFIG_MTDPARTS_SPINAND0_TEE : NULL,
-#endif
-					   "-(UBI)");
-			put_mtd_device(mtd);
-		}
-	}
-
-	if (nor) {
-		if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) {
-			board_set_mtdparts("nor0", ids, parts,
-					   CONFIG_MTDPARTS_NOR0_BOOT,
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
-					   tee ? CONFIG_MTDPARTS_NOR0_TEE : NULL,
-#endif
-					   "-(nor_user)");
-		}
-	}
-
-	mtd_initialized = true;
-	*mtdids = ids;
-	*mtdparts = parts;
-	log_debug("mtdids=%s & mtdparts=%s\n", ids, parts);
-}
diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
index d52dce4f65..969ad48486 100644
--- a/board/st/common/stpmic1.c
+++ b/board/st/common/stpmic1.c
@@ -185,21 +185,17 @@ static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv)
 }
 
 /* early init of PMIC */
-void stpmic1_init(u32 voltage_mv)
+struct udevice *stpmic1_init(u32 voltage_mv)
 {
 	struct udevice *dev;
 
 	if (uclass_get_device_by_driver(UCLASS_PMIC,
 					DM_DRIVER_GET(pmic_stpmic1), &dev))
-		return;
+		return NULL;
 
 	/* update VDDCORE = BUCK1 */
 	if (voltage_mv)
 		stmpic_buck1_set(dev, voltage_mv);
 
-	/* Keep vdd on during the reset cycle */
-	pmic_clrsetbits(dev,
-			STPMIC1_BUCKS_MRST_CR,
-			STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
-			STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
+	return dev;
 }
diff --git a/board/st/common/stpmic1.h b/board/st/common/stpmic1.h
index b17d6f1633..7a7169d7ce 100644
--- a/board/st/common/stpmic1.h
+++ b/board/st/common/stpmic1.h
@@ -3,4 +3,4 @@
  * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
  */
 
-void stpmic1_init(u32 voltage_mv);
+struct udevice *stpmic1_init(u32 voltage_mv);
diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c
index 747ec7e445..8b4a529f75 100644
--- a/board/st/stm32mp1/spl.c
+++ b/board/st/stm32mp1/spl.c
@@ -5,6 +5,8 @@
 
 #include <config.h>
 #include <common.h>
+#include <power/pmic.h>
+#include <power/stpmic1.h>
 #include <asm/arch/sys_proto.h>
 #include "../common/stpmic1.h"
 
@@ -19,8 +21,15 @@ void board_vddcore_init(u32 voltage_mv)
 
 int board_early_init_f(void)
 {
-	if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER))
-		stpmic1_init(opp_voltage_mv);
+	if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) {
+		struct udevice *dev = stpmic1_init(opp_voltage_mv);
+
+		/* Keep vdd on during the reset cycle */
+		pmic_clrsetbits(dev,
+				STPMIC1_BUCKS_MRST_CR,
+				STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
+				STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
+	}
 
 	return 0;
 }
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 1a1b1844c8..3205a31c6d 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -25,7 +25,6 @@
 #include <log.h>
 #include <malloc.h>
 #include <misc.h>
-#include <mtd_node.h>
 #include <net.h>
 #include <netdev.h>
 #include <phy.h>
@@ -92,10 +91,10 @@
 struct efi_fw_image fw_images[1];
 
 struct efi_capsule_update_info update_info = {
+	.num_images = ARRAY_SIZE(fw_images),
 	.images = fw_images,
 };
 
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
 
 int board_early_init_f(void)
@@ -915,20 +914,7 @@ int mmc_get_env_dev(void)
 #if defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
-	static const struct node_info nodes[] = {
-		{ "jedec,spi-nor",		MTD_DEV_TYPE_NOR,  },
-		{ "spi-nand",			MTD_DEV_TYPE_SPINAND},
-		{ "st,stm32mp15-fmc2",		MTD_DEV_TYPE_NAND, },
-		{ "st,stm32mp1-fmc2-nfc",	MTD_DEV_TYPE_NAND, },
-	};
-	char *boot_device;
-
-	/* Check the boot-source and don't update MTD for serial or usb boot */
-	boot_device = env_get("boot_device");
-	if (!boot_device ||
-	    (strcmp(boot_device, "serial") && strcmp(boot_device, "usb")))
-		if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS))
-			fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+	fdt_copy_fixed_partitions(blob);
 
 	if (IS_ENABLED(CONFIG_FDT_SIMPLEFB))
 		fdt_simplefb_enable_and_mem_rsv(blob);
diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS
index c5369086d8..600ff9575b 100644
--- a/board/starfive/visionfive2/MAINTAINERS
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -1,5 +1,5 @@
 STARFIVE JH7110 VISIONFIVE2 BOARD
-M: startfive
+M:	Yanhong Wang <yanhong.wang@starfivetech.com>
 S:	Maintained
 F:	arch/riscv/include/asm/arch-jh7110/
 F:	board/starfive/visionfive2/
diff --git a/board/starfive/visionfive2/Makefile b/board/starfive/visionfive2/Makefile
index 66c854df39..c7ba4f7ed6 100644
--- a/board/starfive/visionfive2/Makefile
+++ b/board/starfive/visionfive2/Makefile
@@ -5,3 +5,4 @@
 
 obj-y	:= starfive_visionfive2.o
 obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_ID_EEPROM) += visionfive2-i2c-eeprom.o
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index db0b4cb433..7acd3995aa 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -5,16 +5,173 @@
  */
 
 #include <common.h>
+#include <asm/arch/eeprom.h>
 #include <asm/arch/regs.h>
 #include <asm/arch/spl.h>
 #include <asm/io.h>
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
 #include <log.h>
 #include <spl.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 #define JH7110_CLK_CPU_ROOT_OFFSET		0x0U
 #define JH7110_CLK_CPU_ROOT_SHIFT		24
 #define JH7110_CLK_CPU_ROOT_MASK		GENMASK(29, 24)
 
+struct starfive_vf2_pro {
+	const char *path;
+	const char *name;
+	const char *value;
+};
+
+static const struct starfive_vf2_pro starfive_vera[] = {
+	{"/soc/ethernet@16030000/mdio/ethernet-phy@0", "rx-internal-delay-ps",
+		"1900"},
+	{"/soc/ethernet@16030000/mdio/ethernet-phy@0", "tx-internal-delay-ps",
+		"1350"}
+};
+
+static const struct starfive_vf2_pro starfive_verb[] = {
+	{"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
+	{"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
+
+	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+		"motorcomm,tx-clk-adj-enabled", NULL},
+	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+		"motorcomm,tx-clk-100-inverted", NULL},
+	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+		"motorcomm,tx-clk-1000-inverted", NULL},
+	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+		"rx-internal-delay-ps", "1900"},
+	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+		"tx-internal-delay-ps", "1500"},
+
+	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+		"motorcomm,tx-clk-adj-enabled", NULL},
+	{ "/soc/ethernet@16040000/mdio/ethernet-phy@1",
+		"motorcomm,tx-clk-100-inverted", NULL},
+	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+		"rx-internal-delay-ps", "0"},
+	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+		"tx-internal-delay-ps", "0"},
+};
+
+void spl_fdt_fixup_version_a(void *fdt)
+{
+	u32 phandle;
+	u8 i;
+	int offset;
+	int ret;
+
+	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+			   "StarFive VisionFive 2 v1.2A");
+
+	offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
+	phandle = fdt_get_phandle(fdt, offset);
+	offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
+
+	fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
+	fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle);
+	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_RX);
+
+	fdt_setprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
+	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
+			   JH7110_SYSCLK_GMAC1_RMII_RTX);
+	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
+	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
+			   JH7110_SYSCLK_GMAC1_RMII_RTX);
+
+	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"),
+			   "phy-mode", "rmii");
+
+	for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) {
+		offset = fdt_path_offset(fdt, starfive_vera[i].path);
+
+		if (starfive_vera[i].value)
+			ret = fdt_setprop_u32(fdt, offset,  starfive_vera[i].name,
+					      dectoul(starfive_vera[i].value, NULL));
+		else
+			ret = fdt_setprop_empty(fdt, offset, starfive_vera[i].name);
+
+		if (ret) {
+			pr_err("%s set prop %s fail.\n", __func__, starfive_vera[i].name);
+				break;
+		}
+	}
+}
+
+void spl_fdt_fixup_version_b(void *fdt)
+{
+	u32 phandle;
+	u8 i;
+	int offset;
+	int ret;
+
+	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+			   "StarFive VisionFive 2 v1.3B");
+
+	/* gmac0 */
+	offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
+	phandle = fdt_get_phandle(fdt, offset);
+	offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
+
+	fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
+	fdt_setprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
+	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
+			   JH7110_AONCLK_GMAC0_RMII_RTX);
+
+	/* gmac1 */
+	offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
+	phandle = fdt_get_phandle(fdt, offset);
+	offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
+
+	fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
+	fdt_setprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
+	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
+			   JH7110_SYSCLK_GMAC1_RMII_RTX);
+
+	for (i = 0; i < ARRAY_SIZE(starfive_verb); i++) {
+		offset = fdt_path_offset(fdt, starfive_verb[i].path);
+
+		if (starfive_verb[i].value)
+			ret = fdt_setprop_u32(fdt, offset,  starfive_verb[i].name,
+					      dectoul(starfive_verb[i].value, NULL));
+		else
+			ret = fdt_setprop_empty(fdt, offset, starfive_verb[i].name);
+
+		if (ret) {
+			pr_err("%s set prop %s fail.\n", __func__, starfive_verb[i].name);
+				break;
+		}
+	}
+}
+
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	u8 version;
+
+	version = get_pcb_revision_from_eeprom();
+	switch (version) {
+	case 'a':
+	case 'A':
+		spl_fdt_fixup_version_a(spl_image->fdt_addr);
+		break;
+
+	case 'b':
+	case 'B':
+	default:
+		spl_fdt_fixup_version_b(spl_image->fdt_addr);
+		break;
+	};
+
+	/* Update the memory size which read form eeprom or DT */
+	fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size);
+}
 int spl_board_init_f(void)
 {
 	int ret;
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
index 613fe793c4..07dcca26b3 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -6,7 +6,9 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/sections.h>
 #include <cpu_func.h>
+#include <dm.h>
 #include <linux/bitops.h>
 
 #define JH7110_L2_PREFETCHER_BASE_ADDR		0x2030000
@@ -38,3 +40,14 @@ int board_init(void)
 
 	return 0;
 }
+
+void *board_fdt_blob_setup(int *err)
+{
+	*err = 0;
+	if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
+		if (gd->arch.firmware_fdt_addr)
+			return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
+	}
+
+	return (ulong *)&_end;
+}
diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
new file mode 100644
index 0000000000..befe7888c4
--- /dev/null
+++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
@@ -0,0 +1,561 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <u-boot/crc.h>
+#include <linux/delay.h>
+
+#define FORMAT_VERSION		0x2
+#define PCB_VERSION		0xB1
+#define BOM_VERSION		'A'
+/*
+ * BYTES_PER_EEPROM_PAGE: the 24FC04H datasheet says that data can
+ * only be written in page mode, which means 16 bytes at a time:
+ * 16-Byte Page Write Buffer
+ */
+#define BYTES_PER_EEPROM_PAGE		16
+
+/*
+ * EEPROM_WRITE_DELAY_MS: the 24FC04H datasheet says it takes up to
+ * 5ms to complete a given write:
+ * Write Cycle Time (byte or page) ro Page Write Time 5 ms, Maximum
+ */
+#define EEPROM_WRITE_DELAY_MS		5000
+/*
+ * StarFive OUI. Registration Date is 20xx-xx-xx
+ */
+#define STARFIVE_OUI_PREFIX		"6C:CF:39:"
+#define STARFIVE_DEFAULT_MAC0		"6C:CF:39:6C:DE:AD"
+#define STARFIVE_DEFAULT_MAC1		"6C:CF:39:6C:DE:AE"
+
+/* Magic number at the first four bytes of EEPROM HATs */
+#define STARFIVE_EEPROM_HATS_SIG	"SFVF" /* StarFive VisionFive */
+
+#define STARFIVE_EEPROM_HATS_SIZE_MAX	256 /* Header + Atom1&4(v1) */
+#define STARFIVE_EEPROM_WP_OFFSET	0 /* Read only field */
+#define STARFIVE_EEPROM_ATOM1_PSTR	"VF7110A1-2228-D008E000-00000001\0"
+#define STARFIVE_EEPROM_ATOM1_PSTR_SIZE	32
+#define STARFIVE_EEPROM_ATOM1_SN_OFFSET	23
+#define STARFIVE_EEPROM_ATOM1_VSTR	"StarFive Technology Co., Ltd.\0\0\0"
+#define STARFIVE_EEPROM_ATOM1_VSTR_SIZE	32
+
+#define MAGIC_NUMBER_BYTES	4
+#define MAC_ADDR_BYTES		6
+#define MAC_ADDR_STRLEN		17
+
+/*
+ * Atom Types
+ * 0x0000 = invalid
+ * 0x0001 = vendor info
+ * 0x0002 = GPIO map
+ * 0x0003 = Linux device tree blob
+ * 0x0004 = manufacturer custom data
+ * 0x0005-0xfffe = reserved for future use
+ * 0xffff = invalid
+ */
+
+#define HATS_ATOM_INVALID	0x0000
+#define HATS_ATOM_VENDOR	0x0001
+#define HATS_ATOM_GPIO		0x0002
+#define HATS_ATOM_DTB		0x0003
+#define HATS_ATOM_CUSTOM	0x0004
+#define HATS_ATOM_INVALID_END	0xffff
+
+struct eeprom_header {
+	char signature[MAGIC_NUMBER_BYTES];	/* ASCII table signature */
+	u8 version;		/* EEPROM data format version */
+				/* (0x00 reserved, 0x01 = first version) */
+	u8 reversed;		/* 0x00, Reserved field */
+	u16 numatoms;		/* total atoms in EEPROM */
+	u32 eeplen;		/* total length in bytes of all eeprom data */
+				/* (including this header) */
+};
+
+struct eeprom_atom_header {
+	u16 type;
+	u16 count;
+	u32 dlen;
+};
+
+struct eeprom_atom1_data {
+	u8 uuid[16];
+	u16 pid;
+	u16 pver;
+	u8 vslen;
+	u8 pslen;
+	uchar vstr[STARFIVE_EEPROM_ATOM1_VSTR_SIZE];
+	uchar pstr[STARFIVE_EEPROM_ATOM1_PSTR_SIZE]; /* product SN */
+};
+
+struct starfive_eeprom_atom1 {
+	struct eeprom_atom_header header;
+	struct eeprom_atom1_data data;
+	u16 crc;
+};
+
+struct eeprom_atom4_data {
+	u16 version;
+	u8 pcb_revision;		/* PCB version */
+	u8 bom_revision;		/* BOM version */
+	u8 mac0_addr[MAC_ADDR_BYTES];	/* Ethernet0 MAC */
+	u8 mac1_addr[MAC_ADDR_BYTES];	/* Ethernet1 MAC */
+	u8 reserved[2];
+};
+
+struct starfive_eeprom_atom4 {
+	struct eeprom_atom_header header;
+	struct eeprom_atom4_data data;
+	u16 crc;
+};
+
+struct starfive_eeprom {
+	struct eeprom_header header;
+	struct starfive_eeprom_atom1 atom1;
+	struct starfive_eeprom_atom4 atom4;
+};
+
+static union {
+	struct starfive_eeprom eeprom;
+	uchar buf[STARFIVE_EEPROM_HATS_SIZE_MAX];
+} pbuf __section(".data");
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read __section(".data");
+
+static inline int is_match_magic(void)
+{
+	return strncmp(pbuf.eeprom.header.signature, STARFIVE_EEPROM_HATS_SIG,
+				MAGIC_NUMBER_BYTES);
+}
+
+/* Calculate the current CRC */
+static inline u32 calculate_crc16(struct eeprom_atom_header *head)
+{
+	uint len = sizeof(struct eeprom_atom_header) + head->dlen - sizeof(u16);
+
+	return crc16(0, (void *)head, len);
+}
+
+/* This function should be called after each update to the EEPROM structure */
+static inline void update_crc(void)
+{
+	pbuf.eeprom.atom1.crc = calculate_crc16(&pbuf.eeprom.atom1.header);
+	pbuf.eeprom.atom4.crc = calculate_crc16(&pbuf.eeprom.atom4.header);
+}
+
+static void dump_raw_eeprom(void)
+{
+	unsigned int i;
+	u32 len;
+
+	len = sizeof(struct starfive_eeprom);
+	for (i = 0; i < len; i++) {
+		if ((i % 16) == 0)
+			printf("%02X: ", i);
+		printf("%02X ", ((u8 *)pbuf.buf)[i]);
+		if (((i % 16) == 15) || (i == len - 1))
+			printf("\n");
+	}
+}
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+	if (has_been_read != 1)
+		return;
+
+	printf("\n--------EEPROM INFO--------\n");
+	printf("Vendor : %s\n", pbuf.eeprom.atom1.data.vstr);
+	printf("Product full SN: %s\n", pbuf.eeprom.atom1.data.pstr);
+	printf("data version: 0x%x\n", pbuf.eeprom.atom4.data.version);
+	if (pbuf.eeprom.atom4.data.version == 2) {
+		printf("PCB revision: 0x%x\n", pbuf.eeprom.atom4.data.pcb_revision);
+		printf("BOM revision: %c\n", pbuf.eeprom.atom4.data.bom_revision);
+		printf("Ethernet MAC0 address: %02x:%02x:%02x:%02x:%02x:%02x\n",
+		       pbuf.eeprom.atom4.data.mac0_addr[0], pbuf.eeprom.atom4.data.mac0_addr[1],
+		       pbuf.eeprom.atom4.data.mac0_addr[2], pbuf.eeprom.atom4.data.mac0_addr[3],
+		       pbuf.eeprom.atom4.data.mac0_addr[4], pbuf.eeprom.atom4.data.mac0_addr[5]);
+		printf("Ethernet MAC1 address: %02x:%02x:%02x:%02x:%02x:%02x\n",
+		       pbuf.eeprom.atom4.data.mac1_addr[0], pbuf.eeprom.atom4.data.mac1_addr[1],
+		       pbuf.eeprom.atom4.data.mac1_addr[2], pbuf.eeprom.atom4.data.mac1_addr[3],
+		       pbuf.eeprom.atom4.data.mac1_addr[4], pbuf.eeprom.atom4.data.mac1_addr[5]);
+	} else {
+		printf("Custom data v%d is not Supported\n", pbuf.eeprom.atom4.data.version);
+	}
+	printf("--------EEPROM INFO--------\n\n");
+}
+
+/**
+ * set_mac_address() - stores a MAC address into the local EEPROM copy
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number),
+ * stores it in the MAC address field of the EEPROM local copy, and
+ * updates the local copy of the CRC.
+ */
+static void set_mac_address(char *string, int index)
+{
+	u8 i;
+	u8 *mac;
+
+	if (strncasecmp(STARFIVE_OUI_PREFIX, string,
+			strlen(STARFIVE_OUI_PREFIX))) {
+		printf("The MAC address doesn't match StarFive OUI %s\n",
+		       STARFIVE_OUI_PREFIX);
+		return;
+	}
+	mac = (index == 0) ? pbuf.eeprom.atom4.data.mac0_addr :
+			pbuf.eeprom.atom4.data.mac1_addr;
+
+	for (i = 0; *string && (i < MAC_ADDR_BYTES); i++) {
+		mac[i] = hextoul(string, &string);
+
+		if (*string == ':')
+			string++;
+	}
+
+	update_crc();
+}
+
+/**
+ * init_local_copy() - initialize the in-memory EEPROM copy
+ *
+ * Initialize the in-memory EEPROM copy with the magic number.  Must
+ * be done when preparing to initialize a blank EEPROM, or overwrite
+ * one with a corrupted magic number.
+ */
+static void init_local_copy(void)
+{
+	memset((void *)pbuf.buf, 0, sizeof(struct starfive_eeprom));
+	memcpy(pbuf.eeprom.header.signature, STARFIVE_EEPROM_HATS_SIG,
+	       strlen(STARFIVE_EEPROM_HATS_SIG));
+	pbuf.eeprom.header.version = FORMAT_VERSION;
+	pbuf.eeprom.header.numatoms = 2;
+	pbuf.eeprom.header.eeplen = sizeof(struct starfive_eeprom);
+
+	pbuf.eeprom.atom1.header.type = HATS_ATOM_VENDOR;
+	pbuf.eeprom.atom1.header.count = 1;
+	pbuf.eeprom.atom1.header.dlen = sizeof(struct eeprom_atom1_data) + sizeof(u16);
+	pbuf.eeprom.atom1.data.vslen = STARFIVE_EEPROM_ATOM1_VSTR_SIZE;
+	pbuf.eeprom.atom1.data.pslen = STARFIVE_EEPROM_ATOM1_PSTR_SIZE;
+	memcpy(pbuf.eeprom.atom1.data.vstr, STARFIVE_EEPROM_ATOM1_VSTR,
+	       strlen(STARFIVE_EEPROM_ATOM1_VSTR));
+	memcpy(pbuf.eeprom.atom1.data.pstr, STARFIVE_EEPROM_ATOM1_PSTR,
+	       strlen(STARFIVE_EEPROM_ATOM1_PSTR));
+
+	pbuf.eeprom.atom4.header.type = HATS_ATOM_CUSTOM;
+	pbuf.eeprom.atom4.header.count = 2;
+	pbuf.eeprom.atom4.header.dlen = sizeof(struct eeprom_atom4_data) + sizeof(u16);
+	pbuf.eeprom.atom4.data.version = FORMAT_VERSION;
+	pbuf.eeprom.atom4.data.pcb_revision = PCB_VERSION;
+	pbuf.eeprom.atom4.data.bom_revision = BOM_VERSION;
+	set_mac_address(STARFIVE_DEFAULT_MAC0, 0);
+	set_mac_address(STARFIVE_DEFAULT_MAC1, 1);
+}
+
+/**
+ * prog_eeprom() - write the EEPROM from memory
+ */
+static int prog_eeprom(unsigned int size)
+{
+	unsigned int i;
+	void *p;
+	uchar tmp_buff[STARFIVE_EEPROM_HATS_SIZE_MAX];
+	struct udevice *dev;
+	int ret;
+
+	if (is_match_magic()) {
+		printf("MAGIC ERROR, Please check the data@%p.\n", pbuf.buf);
+		return -1;
+	}
+
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+				      CONFIG_SYS_I2C_EEPROM_ADDR,
+				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+				      &dev);
+	if (ret) {
+		printf("Get i2c bus:%d addr:%d fail.\n", CONFIG_SYS_EEPROM_BUS_NUM,
+		       CONFIG_SYS_I2C_EEPROM_ADDR);
+		return ret;
+	}
+
+	for (i = 0, p = (u8 *)pbuf.buf; i < size; ) {
+		if (!ret)
+			ret = dm_i2c_write(dev, i, p, min((int)(size - i),
+							  BYTES_PER_EEPROM_PAGE));
+		if (ret)
+			break;
+
+		udelay(EEPROM_WRITE_DELAY_MS);
+		i += BYTES_PER_EEPROM_PAGE;
+		p += BYTES_PER_EEPROM_PAGE;
+	}
+
+	if (!ret) {
+		/* Verify the write by reading back the EEPROM and comparing */
+		ret = dm_i2c_read(dev,
+				  STARFIVE_EEPROM_WP_OFFSET,
+				  tmp_buff,
+				  STARFIVE_EEPROM_HATS_SIZE_MAX);
+		if (!ret && memcmp((void *)pbuf.buf, (void *)tmp_buff,
+				   STARFIVE_EEPROM_HATS_SIZE_MAX))
+			ret = -1;
+	}
+
+	if (ret) {
+		has_been_read = -1;
+		printf("Programming failed.\n");
+		return -1;
+	}
+
+	printf("Programming passed.\n");
+	return 0;
+}
+
+/**
+ * read_eeprom() - read the EEPROM into memory, if it hasn't been read already
+ */
+static int read_eeprom(void)
+{
+	int ret;
+	struct udevice *dev;
+
+	if (has_been_read == 1)
+		return 0;
+
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+				      CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_read(dev, 0, (u8 *)pbuf.buf,
+				  STARFIVE_EEPROM_HATS_SIZE_MAX);
+
+	has_been_read = (ret == 0) ? 1 : 0;
+
+	return ret;
+}
+
+/**
+ * set_pcb_revision() - stores a StarFive PCB revision into the local EEPROM copy
+ *
+ * Takes a pointer to a string representing the numeric PCB revision in
+ * decimal ("0" - "255"), stores it in the pcb_revision field of the
+ * EEPROM local copy, and updates the CRC of the local copy.
+ */
+static void set_pcb_revision(char *string)
+{
+	u32 p;
+
+	p = simple_strtoul(string, &string, 16);
+	if (p > U8_MAX) {
+		printf("%s must not be greater than %d\n", "PCB revision",
+		       U8_MAX);
+		return;
+	}
+
+	pbuf.eeprom.atom4.data.pcb_revision = p;
+
+	update_crc();
+}
+
+/**
+ * set_bom_revision() - stores a StarFive BOM revision into the local EEPROM copy
+ *
+ * Takes a pointer to a uppercase ASCII character representing the BOM
+ * revision ("A" - "Z"), stores it in the bom_revision field of the
+ * EEPROM local copy, and updates the CRC of the local copy.
+ */
+static void set_bom_revision(char *string)
+{
+	if (string[0] < 'A' || string[0] > 'Z') {
+		printf("BOM revision must be an uppercase letter between A and Z\n");
+		return;
+	}
+
+	pbuf.eeprom.atom4.data.bom_revision = string[0];
+
+	update_crc();
+}
+
+/**
+ * set_product_id() - stores a StarFive product ID into the local EEPROM copy
+ *
+ * Takes a pointer to a string representing the numeric product ID  in
+ * string ("VF7100A1-2150-D008E000-00000001\0"), stores it in the product string
+ * field of the EEPROM local copy, and updates the CRC of the local copy.
+ */
+static void set_product_id(char *string)
+{
+	u32 len;
+
+	len = (strlen(string) > STARFIVE_EEPROM_ATOM1_PSTR_SIZE) ?
+		STARFIVE_EEPROM_ATOM1_PSTR_SIZE : strlen(string);
+
+	memcpy((void *)pbuf.eeprom.atom1.data.pstr, (void *)string, len);
+
+	update_crc();
+}
+
+static int print_usage(void)
+{
+	printf("display and program the system ID and MAC addresses in EEPROM\n"
+	"[read_eeprom|initialize|write_eeprom|mac_address|pcb_revision|bom_revision|product_id]\n"
+	"mac read_eeprom\n"
+	"    - read EEPROM content into memory data structure\n"
+	"mac write_eeprom\n"
+	"    - save memory data structure to the EEPROM\n"
+	"mac initialize\n"
+	"    - initialize the in-memory EEPROM copy with default data\n"
+	"mac mac0_address <xx:xx:xx:xx:xx:xx>\n"
+	"    - stores a MAC0 address into the local EEPROM copy\n"
+	"mac mac1_address <xx:xx:xx:xx:xx:xx>\n"
+	"    - stores a MAC1 address into the local EEPROM copy\n"
+	"mac pcb_revision <?>\n"
+	"    - stores a StarFive PCB revision into the local EEPROM copy\n"
+	"mac bom_revision <A>\n"
+	"    - stores a StarFive BOM revision into the local EEPROM copy\n"
+	"mac product_id <VF7110A1-2228-D008E000-xxxxxxxx>\n"
+	"    - stores a StarFive product ID into the local EEPROM copy\n");
+	return 0;
+}
+
+int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	char *cmd;
+
+	if (argc == 1) {
+		show_eeprom();
+		return 0;
+	}
+
+	if (argc > 3)
+		return print_usage();
+
+	cmd = argv[1];
+
+	/* Commands with no argument */
+	if (!strcmp(cmd, "read_eeprom")) {
+		has_been_read = 0;
+		return read_eeprom();
+	} else if (!strcmp(cmd, "initialize")) {
+		init_local_copy();
+		return 0;
+	} else if (!strcmp(cmd, "write_eeprom")) {
+		return prog_eeprom(STARFIVE_EEPROM_HATS_SIZE_MAX);
+	}
+
+	if (argc != 3)
+		return print_usage();
+
+	if (is_match_magic()) {
+		printf("Please read the EEPROM ('read_eeprom') and/or initialize the EEPROM ('initialize') first.\n");
+		return 0;
+	}
+
+	if (!strcmp(cmd, "mac0_address")) {
+		set_mac_address(argv[2], 0);
+		return 0;
+	} else if (!strcmp(cmd, "mac1_address")) {
+		set_mac_address(argv[2], 1);
+		return 0;
+	} else if (!strcmp(cmd, "pcb_revision")) {
+		set_pcb_revision(argv[2]);
+		return 0;
+	} else if (!strcmp(cmd, "bom_revision")) {
+		set_bom_revision(argv[2]);
+		return 0;
+	} else if (!strcmp(cmd, "product_id")) {
+		set_product_id(argv[2]);
+		return 0;
+	}
+
+	return print_usage();
+}
+
+/**
+ * mac_read_from_eeprom() - read the MAC address & the serial number in EEPROM
+ *
+ * This function reads the MAC address and the serial number from EEPROM and
+ * sets the appropriate environment variables for each one read.
+ *
+ * The environment variables are only set if they haven't been set already.
+ * This ensures that any user-saved variables are never overwritten.
+ *
+ * If CONFIG_ID_EEPROM is enabled, this function will be called in
+ * "static init_fnc_t init_sequence_r[]" of u-boot/common/board_r.c.
+ */
+int mac_read_from_eeprom(void)
+{
+	/**
+	 * try to fill the buff from EEPROM,
+	 * always return SUCCESS, even some error happens.
+	 */
+	if (read_eeprom()) {
+		dump_raw_eeprom();
+		return 0;
+	}
+
+	// 1, setup ethaddr env
+	eth_env_set_enetaddr("eth0addr", pbuf.eeprom.atom4.data.mac0_addr);
+	eth_env_set_enetaddr("eth1addr", pbuf.eeprom.atom4.data.mac1_addr);
+
+	/**
+	 * 2, setup serial# env, reference to hifive-platform-i2c-eeprom.c,
+	 * serial# can be a ASCII string, but not just a hex number, so we
+	 * setup serial# in the 32Byte format:
+	 * "VF7100A1-2201-D008E000-00000001;"
+	 * "<product>-<date>-<DDR&eMMC>-<serial_number>"
+	 * <date>: 4Byte, should be the output of `date +%y%W`
+	 * <DDR&eMMC>: 8Byte, "D008" means 8GB, "D01T" means 1TB;
+	 *     "E000" means no eMMC，"E032" means 32GB, "E01T" means 1TB.
+	 * <serial_number>: 8Byte, the Unique Identifier of board in hex.
+	 */
+	if (!env_get("serial#"))
+		env_set("serial#", pbuf.eeprom.atom1.data.pstr);
+
+	printf("StarFive EEPROM format v%u\n", pbuf.eeprom.header.version);
+	show_eeprom();
+	return 0;
+}
+
+/**
+ * get_pcb_revision_from_eeprom - get the PCB revision
+ *
+ * 1.2A return 'A'/'a', 1.3B return 'B'/'b',other values are illegal
+ */
+u8 get_pcb_revision_from_eeprom(void)
+{
+	u8 pv = 0xFF;
+
+	if (read_eeprom())
+		return pv;
+
+	return pbuf.eeprom.atom1.data.pstr[6];
+}
+
+/**
+ * get_ddr_size_from_eeprom - get the DDR size
+ * pstr:  VF7110A1-2228-D008E000-00000001
+ * VF7110A1/VF7110B1 : VisionFive JH7110A /VisionFive JH7110B
+ * D008:　8GB LPDDR4
+ * E000: No emmc device, ECxx: include emmc device, xx: Capacity size[GB]
+ * return: the field of 'D008E000'
+ */
+
+u32 get_ddr_size_from_eeprom(void)
+{
+	u32 pv = 0xFFFFFFFF;
+
+	if (read_eeprom())
+		return pv;
+
+	return hextoul(&pbuf.eeprom.atom1.data.pstr[14], NULL);
+}
diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c
index 20c09700bf..7b2c50a61e 100644
--- a/board/storopack/smegw01/smegw01.c
+++ b/board/storopack/smegw01/smegw01.c
@@ -102,7 +102,7 @@ int board_late_init(void)
 	return 0;
 }
 
-uint board_mmc_get_env_part(struct mmc *mmc)
+uint mmc_get_env_part(struct mmc *mmc)
 {
 	uint part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
 
diff --git a/board/storopack/smegw01/smegw01.env b/board/storopack/smegw01/smegw01.env
index 25bc7cdbd2..1263ddac8e 100644
--- a/board/storopack/smegw01/smegw01.env
+++ b/board/storopack/smegw01/smegw01.env
@@ -29,7 +29,16 @@ altbootcmd=
 	run bootcmd;
 boot_emmc=setenv mmcdev_wanted 1; run persist_mmcdev; run bootcmd;
 boot_sd=setenv mmcdev_wanted 0; run persist_mmcdev; run bootcmd;
-bootcmd=run finduuid; run distro_bootcmd
+bootcmd=
+	if test "${bootcount}" -gt "${bootlimit}"; then
+		run altbootcmd;
+	else
+		if test "${ustate}" = 1; then
+			setenv upgrade_available 1;
+			saveenv;
+		fi;
+		run mmcboot;
+	fi;
 bootdelay=2
 bootlimit=3
 bootm_size=0x10000000
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 80e3f4be4b..98bbd2dd25 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -211,6 +211,11 @@ M:	Aleksandr Aleksandrov <aleksandr.aleksandrov@emlid.com>
 S:	Maintained
 F:	configs/emlid_neutis_n5_devboard_defconfig
 
+LCTECH PI F1C200S
+M:	Andre Przywara <andre.przywara@arm.com>
+S:	Maintained
+F:	configs/lctech_pi_f1c200s_defconfig
+
 GEMEI-G9 TABLET
 M:	Priit Laes <plaes@plaes.org>
 S:	Maintained
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 4308c7e440..6cbc89ae78 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -583,7 +583,7 @@ enum hsdk_axi_masters {
  *
  * Please read ARC HS Development IC Specification, section 17.2 for more
  * information about apertures configuration.
- * NOTE: we intentionally modify default settings in U-boot. Default settings
+ * NOTE: we intentionally modify default settings in U-Boot. Default settings
  * are specified in "Table 111 CREG Address Decoder register reset values".
  */
 
@@ -942,7 +942,7 @@ static int do_hsdk_go(struct cmd_tbl *cmdtp, int flag, int argc,
 	int ret;
 
 	if (board_mismatch()) {
-		printf("ERR: U-boot is not configured for this board!\n");
+		printf("ERR: U-Boot is not configured for this board!\n");
 		return CMD_RET_FAILURE;
 	}
 
@@ -983,10 +983,10 @@ U_BOOT_CMD(
 
 /*
  * We may simply use static variable here to store init status, but we also want
- * to avoid the situation when we reload U-boot via MDB after previous
+ * to avoid the situation when we reload U-Boot via MDB after previous
  * init is done but HW reset (board reset) isn't done. So let's store the
  * init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will
- * survive after U-boot is reloaded via MDB.
+ * survive after U-Boot is reloaded via MDB.
  */
 #define INIT_MARKER_REGISTER		((void __iomem *)CREG_CPU_0_ENTRY)
 /* must be equal to INIT_MARKER_REGISTER reset value */
@@ -1008,7 +1008,7 @@ static int do_hsdk_init(struct cmd_tbl *cmdtp, int flag, int argc,
 	int ret;
 
 	if (board_mismatch()) {
-		printf("ERR: U-boot is not configured for this board!\n");
+		printf("ERR: U-Boot is not configured for this board!\n");
 		return CMD_RET_FAILURE;
 	}
 
@@ -1258,11 +1258,11 @@ int checkboard(void)
 	printf("Board: Synopsys %s\n", board_name(get_board_type_runtime()));
 
 	if (board_mismatch())
-		printf("WARN: U-boot is configured NOT for this board but for %s!\n",
+		printf("WARN: U-Boot is configured NOT for this board but for %s!\n",
 		       board_name(get_board_type_config()));
 
 	reg = readl(CREG_AXI_M_HS_CORE_BOOT) & CREG_CORE_BOOT_IMAGE;
-	printf("U-boot autostart: %s\n", reg ? "enabled" : "disabled");
+	printf("U-Boot autostart: %s\n", reg ? "enabled" : "disabled");
 
 	return 0;
 };
diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c b/board/technexion/pico-imx8mq/pico-imx8mq.c
index 951e3e1985..2be3206f78 100644
--- a/board/technexion/pico-imx8mq/pico-imx8mq.c
+++ b/board/technexion/pico-imx8mq/pico-imx8mq.c
@@ -54,7 +54,7 @@ int board_early_init_f(void)
 
 int board_phys_sdram_size(phys_size_t *size)
 {
-	int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
+	int ddr_size = readl(MCU_BOOTROM_BASE_ADDR);
 
 	if (ddr_size == 0x4) {
 		*size = 0x100000000;
diff --git a/board/technexion/pico-imx8mq/spl.c b/board/technexion/pico-imx8mq/spl.c
index 8b853a914e..2afb4d3760 100644
--- a/board/technexion/pico-imx8mq/spl.c
+++ b/board/technexion/pico-imx8mq/spl.c
@@ -89,7 +89,7 @@ static void spl_dram_init(void)
 
 	printf("%s: LPDDR4 %d GiB\n", __func__, size);
 	ddr_init(dram_timing);
-	writel(size, M4_BOOTROM_BASE_ADDR);
+	writel(size, MCU_BOOTROM_BASE_ADDR);
 }
 
 #define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
diff --git a/board/terasic/de0-nano-soc/MAINTAINERS b/board/terasic/de0-nano-soc/MAINTAINERS
index 7f4cf1e7f5..6ffa0c0738 100644
--- a/board/terasic/de0-nano-soc/MAINTAINERS
+++ b/board/terasic/de0-nano-soc/MAINTAINERS
@@ -1,5 +1,6 @@
 SOCFPGA ATLAS BOARD
 M:	Dinh Nguyen <dinguyen@kernel.org>
 S:	Maintained
+F:	board/terasic/de0-nano-soc/
 F:	include/configs/socfpga_de0_nano_soc.h
 F:	configs/socfpga_de0_nano_soc_defconfig
diff --git a/board/terasic/de1-soc/MAINTAINERS b/board/terasic/de1-soc/MAINTAINERS
index bd7a8d5f4c..1e726e9360 100644
--- a/board/terasic/de1-soc/MAINTAINERS
+++ b/board/terasic/de1-soc/MAINTAINERS
@@ -1,5 +1,6 @@
 DE1-SoC BOARD
 M:	Anatolij Gustschin <agust@denx.de>
 S:	Maintained
+F:	board/terasic/de1-soc/
 F:	include/configs/socfpga_de1_soc.h
 F:	configs/socfpga_de1_soc_defconfig
diff --git a/board/terasic/de10-nano/MAINTAINERS b/board/terasic/de10-nano/MAINTAINERS
index f4dd0dff3b..ebfd3b209d 100644
--- a/board/terasic/de10-nano/MAINTAINERS
+++ b/board/terasic/de10-nano/MAINTAINERS
@@ -1,5 +1,6 @@
 DE10-NANO BOARD
 M:	Dalon Westergreen <dwesterg@gmail.com>
 S:	Maintained
+F:	board/terasic/de10-nano/
 F:	include/configs/socfpga_de10_nano.h
 F:	configs/socfpga_de10_nano_defconfig
diff --git a/board/terasic/de10-standard/MAINTAINERS b/board/terasic/de10-standard/MAINTAINERS
index 94bf1e03ee..49fdc7516c 100644
--- a/board/terasic/de10-standard/MAINTAINERS
+++ b/board/terasic/de10-standard/MAINTAINERS
@@ -1,5 +1,6 @@
 DE10-STANDARD BOARD
 M:	Humberto Naves <hsnaves@gmail.com>
 S:	Maintained
+F:	board/terasic/de10-standard/
 F:	include/configs/socfpga_de10_standard.h
 F:	configs/socfpga_de10_standard_defconfig
diff --git a/board/terasic/sockit/MAINTAINERS b/board/terasic/sockit/MAINTAINERS
index 792f18474f..e301751fbd 100644
--- a/board/terasic/sockit/MAINTAINERS
+++ b/board/terasic/sockit/MAINTAINERS
@@ -1,5 +1,6 @@
 SOCKIT BOARD
 M:	Marek Vasut <marex@denx.de>
 S:	Maintained
+F:	board/terasic/sockit/
 F:	include/configs/socfpga_sockit.h
 F:	configs/socfpga_sockit_defconfig
diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig
new file mode 100644
index 0000000000..622246127c
--- /dev/null
+++ b/board/thead/th1520_lpi4a/Kconfig
@@ -0,0 +1,42 @@
+if TARGET_TH1520_LPI4A
+
+config ARCH_THEAD
+	bool
+	default y
+
+config SYS_BOARD
+	default "th1520_lpi4a"
+
+config SYS_VENDOR
+	default "thead"
+
+config SYS_CPU
+	default "generic"
+
+config SYS_CONFIG_NAME
+	default "th1520_lpi4a"
+
+config TEXT_BASE
+	default 0x01b00000 if SPL
+	default 0x01c00000 if !RISCV_SMODE
+	default 0x01c00000 if RISCV_SMODE
+
+config SPL_TEXT_BASE
+	default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x80000000
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select ARCH_EARLY_INIT_R
+	imply CPU
+	imply CPU_RISCV
+	imply RISCV_TIMER if RISCV_SMODE
+	imply CMD_CPU
+	imply SMP
+	imply SUPPORT_OF_CONTROL
+	imply OF_CONTROL
+	imply OF_REAL
+
+endif
diff --git a/board/thead/th1520_lpi4a/MAINTAINERS b/board/thead/th1520_lpi4a/MAINTAINERS
new file mode 100644
index 0000000000..36c7ab7cc3
--- /dev/null
+++ b/board/thead/th1520_lpi4a/MAINTAINERS
@@ -0,0 +1,7 @@
+Lichee PI 4A
+M:	Wei Fu <wefu@redhat.com>
+M:	Yixun Lan <dlan@gentoo.org>
+S:	Maintained
+F:	board/thead/th1520_lpi4a/
+F:	configs/th1520_lpi4a_defconfig
+F:	doc/board/thead/lpi4a.rst
diff --git a/board/thead/th1520_lpi4a/Makefile b/board/thead/th1520_lpi4a/Makefile
new file mode 100644
index 0000000000..9671b3bbb0
--- /dev/null
+++ b/board/thead/th1520_lpi4a/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2023, Yixun Lan <dlan@gentoo.org>
+
+obj-y += board.o
diff --git a/board/thead/th1520_lpi4a/board.c b/board/thead/th1520_lpi4a/board.c
new file mode 100644
index 0000000000..16c3e456b3
--- /dev/null
+++ b/board/thead/th1520_lpi4a/board.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023, Yixun Lan <dlan@gentoo.org>
+ *
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+
+int board_init(void)
+{
+	enable_caches();
+
+	return 0;
+}
diff --git a/board/thecus/n2350/n2350.c b/board/thecus/n2350/n2350.c
index fd8f95f944..05b125fd7f 100644
--- a/board/thecus/n2350/n2350.c
+++ b/board/thecus/n2350/n2350.c
@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define N2350_GPP_OUT_ENA_LOW	(~(BIT(20) | BIT(21) | BIT(24)))
 #define N2350_GPP_OUT_ENA_MID	(~(BIT(12) | BIT(13) | BIT(16) | BIT(19) | BIT(22)))
 #define N2350_GPP_OUT_VAL_LOW	(BIT(21) | BIT(24))
-#define N2350_GPP_OUT_VAL_MID	(BIT(0) | BIT(12) | BIT(13))
+#define N2350_GPP_OUT_VAL_MID	(BIT(0) | BIT(12) | BIT(13) | BIT(16))
 #define N2350_GPP_POL_LOW	0x0
 #define N2350_GPP_POL_MID	0x0
 
diff --git a/board/ti/am62ax/Kconfig b/board/ti/am62ax/Kconfig
index 9b868e4553..61f289facc 100644
--- a/board/ti/am62ax/Kconfig
+++ b/board/ti/am62ax/Kconfig
@@ -10,6 +10,7 @@ choice
 config TARGET_AM62A7_A53_EVM
 	bool "TI K3 based AM62A7 EVM running on A53"
 	select ARM64
+	select BINMAN
 	imply BOARD
 	imply SPL_BOARD
 	imply TI_I2C_BOARD_DETECT
@@ -22,6 +23,7 @@ config TARGET_AM62A7_R5_EVM
 	select RAM
 	select SPL_RAM
 	select K3_DDRSS
+	select BINMAN
 	imply SYS_K3_SPL_ATF
 	imply TI_I2C_BOARD_DETECT
 
diff --git a/board/ti/am62ax/am62ax.env b/board/ti/am62ax/am62ax.env
index 8c1c26e9a2..3f7c333fa4 100644
--- a/board/ti/am62ax/am62ax.env
+++ b/board/ti/am62ax/am62ax.env
@@ -1,7 +1,7 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/mmc.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/mmc.env>
 
-default_device_tree=k3-am62a7-sk.dtb
+default_device_tree=ti/k3-am62a7-sk.dtb
 findfdt=
 	setenv name_fdt ${default_device_tree};
 	setenv fdtfile ${name_fdt}
@@ -17,7 +17,6 @@ bootpart=1:2
 bootdir=/boot
 rd_spec=-
 init_mmc=run args_all args_mmc
-get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
 get_overlay_mmc=
 	fdt address ${fdtaddr};
 	fdt resize 0x100000;
diff --git a/board/ti/am62ax/board-cfg.yaml b/board/ti/am62ax/board-cfg.yaml
new file mode 100644
index 0000000000..4aa8ddd104
--- /dev/null
+++ b/board/ti/am62ax/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62ax
+#
+
+---
+
+board-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
+    control:
+        subhdr:
+            magic: 0xC1D3
+            size: 7
+        main_isolation_enable : 0x5A
+        main_isolation_hostid : 0x2
+    secproxy:
+        subhdr:
+            magic: 0x1207
+            size: 7
+        scaling_factor : 0x1
+        scaling_profile : 0x1
+        disable_main_nav_secure_proxy : 0
+    msmc:
+        subhdr:
+            magic: 0xA5C3
+            size: 5
+        msmc_cache_size : 0x10
+    debug_cfg:
+        subhdr:
+            magic: 0x020C
+            size: 8
+        trace_dst_enables : 0x00
+        trace_src_enables : 0x00
diff --git a/board/ti/am62ax/pm-cfg.yaml b/board/ti/am62ax/pm-cfg.yaml
new file mode 100644
index 0000000000..3ad182ae17
--- /dev/null
+++ b/board/ti/am62ax/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62ax
+#
+
+---
+
+pm-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml
new file mode 100644
index 0000000000..15c4017bda
--- /dev/null
+++ b/board/ti/am62ax/rm-cfg.yaml
@@ -0,0 +1,1151 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62ax
+#
+
+---
+
+rm-cfg:
+    rm_boardcfg:
+        rev:
+            boardcfg_abi_maj : 0x0
+            boardcfg_abi_min : 0x1
+        host_cfg:
+            subhdr:
+                magic: 0x4C41
+                size : 356
+            host_cfg_entries:
+                - #1
+                    host_id: 12
+                    allowed_atype : 0x2A
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+                - #8
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+                - #10
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+                - #13
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+                - #15
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+                - #16
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+                - #17
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+                - #18
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+                - #19
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+                - #21
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+                - #23
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+                - #24
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+                - #25
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+                - #26
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+                - #32
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+                start_resource: 0
+                num_resource: 1
+                type: 12739
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 6
+                type: 12750
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 6
+                type: 12769
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 8
+                type: 12810
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 12288
+                num_resource: 128
+                type: 12813
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 3072
+                num_resource: 6
+                type: 12828
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 3584
+                num_resource: 6
+                type: 12829
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 4096
+                num_resource: 6
+                type: 12830
+                host_id: 128
+                reserved: 0
diff --git a/board/ti/am62ax/sec-cfg.yaml b/board/ti/am62ax/sec-cfg.yaml
new file mode 100644
index 0000000000..f0ad20c5a6
--- /dev/null
+++ b/board/ti/am62ax/sec-cfg.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security configuration for AM62ax
+#
+
+---
+
+sec-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
+    processor_acl_list:
+        subhdr:
+            magic: 0xF1EA
+            size: 164
+        proc_acl_entries:
+            - #1
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #2
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #3
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #4
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #5
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #6
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #7
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #8
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #9
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #10
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #11
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #12
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #13
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #14
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #15
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #16
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #17
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #18
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #19
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #20
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #21
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #22
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #23
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #24
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #25
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #26
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #27
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #28
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #29
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #30
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #31
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #32
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+    host_hierarchy:
+        subhdr:
+            magic: 0x8D27
+            size: 68
+        host_hierarchy_entries:
+            - #1
+                host_id: 0
+                supervisor_host_id: 0
+            - #2
+                host_id: 0
+                supervisor_host_id: 0
+            - #3
+                host_id: 0
+                supervisor_host_id: 0
+            - #4
+                host_id: 0
+                supervisor_host_id: 0
+            - #5
+                host_id: 0
+                supervisor_host_id: 0
+            - #6
+                host_id: 0
+                supervisor_host_id: 0
+            - #7
+                host_id: 0
+                supervisor_host_id: 0
+            - #8
+                host_id: 0
+                supervisor_host_id: 0
+            - #9
+                host_id: 0
+                supervisor_host_id: 0
+            - #10
+                host_id: 0
+                supervisor_host_id: 0
+            - #11
+                host_id: 0
+                supervisor_host_id: 0
+            - #12
+                host_id: 0
+                supervisor_host_id: 0
+            - #13
+                host_id: 0
+                supervisor_host_id: 0
+            - #14
+                host_id: 0
+                supervisor_host_id: 0
+            - #15
+                host_id: 0
+                supervisor_host_id: 0
+            - #16
+                host_id: 0
+                supervisor_host_id: 0
+            - #17
+                host_id: 0
+                supervisor_host_id: 0
+            - #18
+                host_id: 0
+                supervisor_host_id: 0
+            - #19
+                host_id: 0
+                supervisor_host_id: 0
+            - #20
+                host_id: 0
+                supervisor_host_id: 0
+            - #21
+                host_id: 0
+                supervisor_host_id: 0
+            - #22
+                host_id: 0
+                supervisor_host_id: 0
+            - #23
+                host_id: 0
+                supervisor_host_id: 0
+            - #24
+                host_id: 0
+                supervisor_host_id: 0
+            - #25
+                host_id: 0
+                supervisor_host_id: 0
+            - #26
+                host_id: 0
+                supervisor_host_id: 0
+            - #27
+                host_id: 0
+                supervisor_host_id: 0
+            - #28
+                host_id: 0
+                supervisor_host_id: 0
+            - #29
+                host_id: 0
+                supervisor_host_id: 0
+            - #30
+                host_id: 0
+                supervisor_host_id: 0
+            - #31
+                host_id: 0
+                supervisor_host_id: 0
+            - #32
+                host_id: 0
+                supervisor_host_id: 0
+    otp_config:
+        subhdr:
+            magic: 0x4081
+            size: 69
+        write_host_id : 0
+        otp_entry:
+            - #1
+                host_id: 0
+                host_perms: 0
+            - #2
+                host_id: 0
+                host_perms: 0
+            - #3
+                host_id: 0
+                host_perms: 0
+            - #4
+                host_id: 0
+                host_perms: 0
+            - #5
+                host_id: 0
+                host_perms: 0
+            - #6
+                host_id: 0
+                host_perms: 0
+            - #7
+                host_id: 0
+                host_perms: 0
+            - #8
+                host_id: 0
+                host_perms: 0
+            - #9
+                host_id: 0
+                host_perms: 0
+            - #10
+                host_id: 0
+                host_perms: 0
+            - #11
+                host_id: 0
+                host_perms: 0
+            - #12
+                host_id: 0
+                host_perms: 0
+            - #13
+                host_id: 0
+                host_perms: 0
+            - #14
+                host_id: 0
+                host_perms: 0
+            - #15
+                host_id: 0
+                host_perms: 0
+            - #16
+                host_id: 0
+                host_perms: 0
+            - #17
+                host_id: 0
+                host_perms: 0
+            - #18
+                host_id: 0
+                host_perms: 0
+            - #19
+                host_id: 0
+                host_perms: 0
+            - #20
+                host_id: 0
+                host_perms: 0
+            - #21
+                host_id: 0
+                host_perms: 0
+            - #22
+                host_id: 0
+                host_perms: 0
+            - #23
+                host_id: 0
+                host_perms: 0
+            - #24
+                host_id: 0
+                host_perms: 0
+            - #25
+                host_id: 0
+                host_perms: 0
+            - #26
+                host_id: 0
+                host_perms: 0
+            - #27
+                host_id: 0
+                host_perms: 0
+            - #28
+                host_id: 0
+                host_perms: 0
+            - #29
+                host_id: 0
+                host_perms: 0
+            - #30
+                host_id: 0
+                host_perms: 0
+            - #31
+                host_id: 0
+                host_perms: 0
+            - #32
+                host_id: 0
+                host_perms: 0
+    dkek_config:
+        subhdr:
+            magic: 0x5170
+            size: 12
+        allowed_hosts: [128, 0, 0, 0]
+        allow_dkek_export_tisci : 0x5A
+        rsvd: [0, 0, 0]
+    sa2ul_cfg:
+        subhdr:
+            magic: 0x23BE
+            size : 0
+        auth_resource_owner: 0
+        enable_saul_psil_global_config_writes: 0x5A
+        rsvd: [0, 0]
+    sec_dbg_config:
+        subhdr:
+            magic: 0x42AF
+            size: 16
+        allow_jtag_unlock : 0x5A
+        allow_wildcard_unlock : 0x5A
+        allowed_debug_level_rsvd: 0
+        rsvd: 0
+        min_cert_rev : 0x0
+        jtag_unlock_hosts: [0, 0, 0, 0]
+    sec_handover_cfg:
+        subhdr:
+            magic: 0x608F
+            size: 10
+        handover_msg_sender : 0
+        handover_to_host_id : 0
+        rsvd: [0, 0, 0, 0]
diff --git a/board/ti/am62ax/tifs-rm-cfg.yaml b/board/ti/am62ax/tifs-rm-cfg.yaml
new file mode 100644
index 0000000000..0b1980eb7b
--- /dev/null
+++ b/board/ti/am62ax/tifs-rm-cfg.yaml
@@ -0,0 +1,1011 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62AX
+#
+
+---
+
+tifs-rm-cfg:
+    rm_boardcfg:
+        rev:
+            boardcfg_abi_maj : 0x0
+            boardcfg_abi_min : 0x1
+        host_cfg:
+            subhdr:
+                magic: 0x4C41
+                size : 356
+            host_cfg_entries:
+                - #1
+                    host_id: 12
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #2
+                    host_id: 30
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #3
+                    host_id: 36
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #4
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #5
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #6
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #7
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #8
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #9
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #10
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #11
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #12
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #13
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #14
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #15
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #16
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #17
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #18
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #19
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #20
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #21
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #22
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #23
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #24
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #25
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #26
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #27
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #28
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #29
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #30
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #31
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #32
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+        resasg:
+            subhdr:
+                magic: 0x7B25
+                size : 8
+            resasg_entries_size: 872
+            reserved : 0
+    resasg_entries:
+        -
+                start_resource: 0
+                num_resource: 18
+                type: 1677
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 18
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+                type: 1677
+                host_id: 35
+                reserved: 0
+
+        -
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+                num_resource: 6
+                type: 1677
+                host_id: 36
+                reserved: 0
+
+        -
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+                num_resource: 2
+                type: 1677
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 26
+                num_resource: 6
+                type: 1677
+                host_id: 128
+                reserved: 0
+
+        -
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+                type: 1678
+                host_id: 12
+                reserved: 0
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+        -
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+                type: 1678
+                host_id: 35
+                reserved: 0
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+        -
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+                num_resource: 6
+                type: 1678
+                host_id: 36
+                reserved: 0
+
+        -
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+                num_resource: 2
+                type: 1678
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 80
+                num_resource: 2
+                type: 1678
+                host_id: 128
+                reserved: 0
+
+        -
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+                num_resource: 12
+                type: 1679
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 44
+                num_resource: 6
+                type: 1679
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 44
+                num_resource: 6
+                type: 1679
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 50
+                num_resource: 2
+                type: 1679
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 52
+                num_resource: 2
+                type: 1679
+                host_id: 128
+                reserved: 0
+
+        -
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+                type: 1696
+                host_id: 12
+                reserved: 0
+
+        -
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+                num_resource: 6
+                type: 1696
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 18
+                num_resource: 6
+                type: 1696
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 24
+                num_resource: 2
+                type: 1696
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 26
+                num_resource: 6
+                type: 1696
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 18
+                type: 1697
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 18
+                num_resource: 6
+                type: 1697
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 18
+                num_resource: 6
+                type: 1697
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 24
+                num_resource: 2
+                type: 1697
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 26
+                num_resource: 2
+                type: 1697
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 12
+                type: 1698
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 12
+                num_resource: 6
+                type: 1698
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 12
+                num_resource: 6
+                type: 1698
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 18
+                num_resource: 2
+                type: 1698
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 20
+                num_resource: 2
+                type: 1698
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 6
+                num_resource: 34
+                type: 1802
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 44
+                num_resource: 36
+                type: 1802
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 44
+                num_resource: 36
+                type: 1802
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 168
+                num_resource: 8
+                type: 1802
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 1024
+                type: 1807
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 4096
+                num_resource: 29
+                type: 1808
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 4608
+                num_resource: 99
+                type: 1809
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 5120
+                num_resource: 24
+                type: 1810
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 5632
+                num_resource: 51
+                type: 1811
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 6144
+                num_resource: 51
+                type: 1812
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 6656
+                num_resource: 51
+                type: 1813
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 8192
+                num_resource: 32
+                type: 1814
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 8704
+                num_resource: 32
+                type: 1815
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 9216
+                num_resource: 32
+                type: 1816
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 9728
+                num_resource: 22
+                type: 1817
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 10240
+                num_resource: 22
+                type: 1818
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 10752
+                num_resource: 22
+                type: 1819
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 11264
+                num_resource: 28
+                type: 1820
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 11776
+                num_resource: 28
+                type: 1821
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 12288
+                num_resource: 28
+                type: 1822
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 10
+                type: 1936
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1936
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1936
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 13
+                num_resource: 3
+                type: 1936
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 16
+                num_resource: 3
+                type: 1936
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 64
+                type: 1937
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 64
+                type: 1937
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 83
+                num_resource: 8
+                type: 1938
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 91
+                num_resource: 8
+                type: 1939
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 99
+                num_resource: 10
+                type: 1942
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 109
+                num_resource: 3
+                type: 1942
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 109
+                num_resource: 3
+                type: 1942
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 112
+                num_resource: 3
+                type: 1942
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 115
+                num_resource: 3
+                type: 1942
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 118
+                num_resource: 16
+                type: 1943
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 118
+                num_resource: 16
+                type: 1943
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 134
+                num_resource: 8
+                type: 1944
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 134
+                num_resource: 8
+                type: 1945
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 142
+                num_resource: 8
+                type: 1946
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 142
+                num_resource: 8
+                type: 1947
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 10
+                type: 1955
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1955
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1955
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 13
+                num_resource: 3
+                type: 1955
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 16
+                num_resource: 3
+                type: 1955
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 8
+                type: 1956
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 8
+                type: 1956
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 27
+                num_resource: 1
+                type: 1957
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 28
+                num_resource: 1
+                type: 1958
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 10
+                type: 1961
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1961
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1961
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 13
+                num_resource: 3
+                type: 1961
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 16
+                num_resource: 3
+                type: 1961
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 10
+                type: 1962
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1962
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1962
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 13
+                num_resource: 3
+                type: 1962
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 16
+                num_resource: 3
+                type: 1962
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 1
+                type: 1963
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 1
+                type: 1963
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 16
+                type: 1964
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 16
+                type: 1964
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 20
+                num_resource: 1
+                type: 1965
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 35
+                num_resource: 8
+                type: 1966
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 21
+                num_resource: 1
+                type: 1967
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 35
+                num_resource: 8
+                type: 1968
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 22
+                num_resource: 1
+                type: 1969
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 43
+                num_resource: 8
+                type: 1970
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 23
+                num_resource: 1
+                type: 1971
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 43
+                num_resource: 8
+                type: 1972
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 1
+                type: 2112
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 2
+                num_resource: 2
+                type: 2122
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 6
+                type: 12750
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 6
+                type: 12769
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 8
+                type: 12810
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 3072
+                num_resource: 6
+                type: 12828
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 3584
+                num_resource: 6
+                type: 12829
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 4096
+                num_resource: 6
+                type: 12830
+                host_id: 128
+                reserved: 0
diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig
index 5e8dfa3cc4..cd17e939e5 100644
--- a/board/ti/am62x/Kconfig
+++ b/board/ti/am62x/Kconfig
@@ -10,6 +10,7 @@ choice
 config TARGET_AM625_A53_EVM
 	bool "TI K3 based AM625 EVM running on A53"
 	select ARM64
+	select BINMAN
 
 config TARGET_AM625_R5_EVM
 	bool "TI K3 based AM625 EVM running on R5"
@@ -19,6 +20,7 @@ config TARGET_AM625_R5_EVM
 	select RAM
 	select SPL_RAM
 	select K3_DDRSS
+	select BINMAN
 	imply SYS_K3_SPL_ATF
 
 endchoice
diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env
index 5ac15fd240..f2dc87893a 100644
--- a/board/ti/am62x/am62x.env
+++ b/board/ti/am62x/am62x.env
@@ -1,7 +1,7 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/mmc.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/mmc.env>
 
-default_device_tree=k3-am625-sk.dtb
+default_device_tree=ti/k3-am625-sk.dtb
 findfdt=
 	setenv name_fdt ${default_device_tree};
 	setenv fdtfile ${name_fdt}
@@ -16,21 +16,6 @@ mmcdev=1
 bootpart=1:2
 bootdir=/boot
 rd_spec=-
-init_mmc=run args_all args_mmc
-get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
-get_overlay_mmc=
-	fdt address ${fdtaddr};
-	fdt resize 0x100000;
-	for overlay in $name_overlays;
-	do;
-	load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} &&
-	fdt apply ${dtboaddr};
-	done;
-get_kern_mmc=load mmc ${bootpart} ${loadaddr}
-	${bootdir}/${name_kern}
-get_fit_mmc=load mmc ${bootpart} ${addr_fit}
-	${bootdir}/${name_fit}
-partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
 
 splashfile=ti.gz
 splashimage=0x80200000
diff --git a/board/ti/am62x/board-cfg.yaml b/board/ti/am62x/board-cfg.yaml
new file mode 100644
index 0000000000..36cfb550ad
--- /dev/null
+++ b/board/ti/am62x/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62
+#
+
+---
+
+board-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
+    control:
+        subhdr:
+            magic: 0xC1D3
+            size: 7
+        main_isolation_enable : 0x5A
+        main_isolation_hostid : 0x2
+    secproxy:
+        subhdr:
+            magic: 0x1207
+            size: 7
+        scaling_factor : 0x1
+        scaling_profile : 0x1
+        disable_main_nav_secure_proxy : 0
+    msmc:
+        subhdr:
+            magic: 0xA5C3
+            size: 5
+        msmc_cache_size : 0x0
+    debug_cfg:
+        subhdr:
+            magic: 0x020C
+            size: 8
+        trace_dst_enables : 0x00
+        trace_src_enables : 0x00
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index 34830f445f..ad93908840 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -12,6 +12,7 @@
 #include <init.h>
 #include <video.h>
 #include <splash.h>
+#include <cpu_func.h>
 #include <k3-ddrss.h>
 #include <fdt_support.h>
 #include <asm/io.h>
@@ -59,42 +60,31 @@ int dram_init_banksize(void)
 }
 
 #if defined(CONFIG_SPL_BUILD)
-#ifdef CONFIG_SPL_VIDEO_TIDSS
-static int setup_dram(void)
-{
-	dram_init();
-	dram_init_banksize();
-	gd->ram_base = CFG_SYS_SDRAM_BASE;
-	gd->ram_top = gd->ram_base + gd->ram_size;
-	gd->relocaddr = gd->ram_top;
-	return 0;
-}
-
 static int video_setup(void)
 {
-	ulong addr;
-	int ret;
-	addr = gd->relocaddr;
+	if (CONFIG_IS_ENABLED(VIDEO)) {
+		ulong addr;
+		int ret;
+
+		addr = gd->relocaddr;
+		ret = video_reserve(&addr);
+		if (ret)
+			return ret;
+		debug("Reserving %luk for video at: %08lx\n",
+		      ((unsigned long)gd->relocaddr - addr) >> 10, addr);
+		gd->relocaddr = addr;
+	}
 
-	ret = video_reserve(&addr);
-	if (ret)
-		return ret;
-	debug("Reserving %luk for video at: %08lx\n",
-	      ((unsigned long)gd->relocaddr - addr) >> 10, addr);
-	gd->relocaddr = addr;
 	return 0;
 }
 
-#endif
 void spl_board_init(void)
 {
-#if defined(CONFIG_SPL_VIDEO_TIDSS)
-	setup_dram();
-	arch_reserve_mmu();
 	video_setup();
 	enable_caches();
-	splash_display();
-#endif
+	if (IS_ENABLED(CONFIG_SPL_SPLASH_SCREEN) && IS_ENABLED(CONFIG_SPL_BMP))
+		splash_display();
+
 }
 
 #if defined(CONFIG_K3_AM64_DDRSS)
diff --git a/board/ti/am62x/pm-cfg.yaml b/board/ti/am62x/pm-cfg.yaml
new file mode 100644
index 0000000000..5d04cf82ef
--- /dev/null
+++ b/board/ti/am62x/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62
+#
+
+---
+
+pm-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
diff --git a/board/ti/am62x/rm-cfg.yaml b/board/ti/am62x/rm-cfg.yaml
new file mode 100644
index 0000000000..c28707be8e
--- /dev/null
+++ b/board/ti/am62x/rm-cfg.yaml
@@ -0,0 +1,1088 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62
+#
+
+---
+
+rm-cfg:
+    rm_boardcfg:
+        rev:
+            boardcfg_abi_maj : 0x0
+            boardcfg_abi_min : 0x1
+        host_cfg:
+            subhdr:
+                magic: 0x4C41
+                size : 356
+            host_cfg_entries:
+                - #1
+                    host_id: 12
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #2
+                    host_id: 30
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #3
+                    host_id: 36
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #4
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #5
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #6
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #7
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #8
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #9
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #10
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #11
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #12
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #13
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #14
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #15
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #16
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #17
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #18
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #19
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #20
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #21
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #22
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #23
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #24
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #25
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #26
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #27
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
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+                - #28
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+                    allowed_atype : 0
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+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #29
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+                    allowed_orderid : 0
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+                    allowed_sched_priority : 0
+                - #30
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+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #31
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+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #32
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+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
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diff --git a/board/ti/am62x/sec-cfg.yaml b/board/ti/am62x/sec-cfg.yaml
new file mode 100644
index 0000000000..07081ce06c
--- /dev/null
+++ b/board/ti/am62x/sec-cfg.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for AM62
+#
+
+---
+
+sec-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
+    processor_acl_list:
+        subhdr:
+            magic: 0xF1EA
+            size: 164
+        proc_acl_entries:
+            - #1
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #2
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #3
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #4
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #5
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #6
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #7
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #8
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #9
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #10
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #11
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #12
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #13
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #14
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #15
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #16
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #17
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #18
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #19
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #20
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #21
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #22
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #23
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #24
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #25
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #26
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #27
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #28
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #29
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #30
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #31
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #32
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+    host_hierarchy:
+        subhdr:
+            magic: 0x8D27
+            size: 68
+        host_hierarchy_entries:
+            - #1
+                host_id: 0
+                supervisor_host_id: 0
+            - #2
+                host_id: 0
+                supervisor_host_id: 0
+            - #3
+                host_id: 0
+                supervisor_host_id: 0
+            - #4
+                host_id: 0
+                supervisor_host_id: 0
+            - #5
+                host_id: 0
+                supervisor_host_id: 0
+            - #6
+                host_id: 0
+                supervisor_host_id: 0
+            - #7
+                host_id: 0
+                supervisor_host_id: 0
+            - #8
+                host_id: 0
+                supervisor_host_id: 0
+            - #9
+                host_id: 0
+                supervisor_host_id: 0
+            - #10
+                host_id: 0
+                supervisor_host_id: 0
+            - #11
+                host_id: 0
+                supervisor_host_id: 0
+            - #12
+                host_id: 0
+                supervisor_host_id: 0
+            - #13
+                host_id: 0
+                supervisor_host_id: 0
+            - #14
+                host_id: 0
+                supervisor_host_id: 0
+            - #15
+                host_id: 0
+                supervisor_host_id: 0
+            - #16
+                host_id: 0
+                supervisor_host_id: 0
+            - #17
+                host_id: 0
+                supervisor_host_id: 0
+            - #18
+                host_id: 0
+                supervisor_host_id: 0
+            - #19
+                host_id: 0
+                supervisor_host_id: 0
+            - #20
+                host_id: 0
+                supervisor_host_id: 0
+            - #21
+                host_id: 0
+                supervisor_host_id: 0
+            - #22
+                host_id: 0
+                supervisor_host_id: 0
+            - #23
+                host_id: 0
+                supervisor_host_id: 0
+            - #24
+                host_id: 0
+                supervisor_host_id: 0
+            - #25
+                host_id: 0
+                supervisor_host_id: 0
+            - #26
+                host_id: 0
+                supervisor_host_id: 0
+            - #27
+                host_id: 0
+                supervisor_host_id: 0
+            - #28
+                host_id: 0
+                supervisor_host_id: 0
+            - #29
+                host_id: 0
+                supervisor_host_id: 0
+            - #30
+                host_id: 0
+                supervisor_host_id: 0
+            - #31
+                host_id: 0
+                supervisor_host_id: 0
+            - #32
+                host_id: 0
+                supervisor_host_id: 0
+    otp_config:
+        subhdr:
+            magic: 0x4081
+            size: 69
+        write_host_id : 0
+        otp_entry:
+            - #1
+                host_id: 0
+                host_perms: 0
+            - #2
+                host_id: 0
+                host_perms: 0
+            - #3
+                host_id: 0
+                host_perms: 0
+            - #4
+                host_id: 0
+                host_perms: 0
+            - #5
+                host_id: 0
+                host_perms: 0
+            - #6
+                host_id: 0
+                host_perms: 0
+            - #7
+                host_id: 0
+                host_perms: 0
+            - #8
+                host_id: 0
+                host_perms: 0
+            - #9
+                host_id: 0
+                host_perms: 0
+            - #10
+                host_id: 0
+                host_perms: 0
+            - #11
+                host_id: 0
+                host_perms: 0
+            - #12
+                host_id: 0
+                host_perms: 0
+            - #13
+                host_id: 0
+                host_perms: 0
+            - #14
+                host_id: 0
+                host_perms: 0
+            - #15
+                host_id: 0
+                host_perms: 0
+            - #16
+                host_id: 0
+                host_perms: 0
+            - #17
+                host_id: 0
+                host_perms: 0
+            - #18
+                host_id: 0
+                host_perms: 0
+            - #19
+                host_id: 0
+                host_perms: 0
+            - #20
+                host_id: 0
+                host_perms: 0
+            - #21
+                host_id: 0
+                host_perms: 0
+            - #22
+                host_id: 0
+                host_perms: 0
+            - #23
+                host_id: 0
+                host_perms: 0
+            - #24
+                host_id: 0
+                host_perms: 0
+            - #25
+                host_id: 0
+                host_perms: 0
+            - #26
+                host_id: 0
+                host_perms: 0
+            - #27
+                host_id: 0
+                host_perms: 0
+            - #28
+                host_id: 0
+                host_perms: 0
+            - #29
+                host_id: 0
+                host_perms: 0
+            - #30
+                host_id: 0
+                host_perms: 0
+            - #31
+                host_id: 0
+                host_perms: 0
+            - #32
+                host_id: 0
+                host_perms: 0
+    dkek_config:
+        subhdr:
+            magic: 0x5170
+            size: 12
+        allowed_hosts: [128, 0, 0, 0]
+        allow_dkek_export_tisci : 0x5A
+        rsvd: [0, 0, 0]
+    sa2ul_cfg:
+        subhdr:
+            magic: 0x23BE
+            size : 0
+        auth_resource_owner: 0
+        enable_saul_psil_global_config_writes: 0x5A
+        rsvd: [0, 0]
+    sec_dbg_config:
+        subhdr:
+            magic: 0x42AF
+            size: 16
+        allow_jtag_unlock : 0x5A
+        allow_wildcard_unlock : 0x5A
+        allowed_debug_level_rsvd: 0
+        rsvd: 0
+        min_cert_rev : 0x0
+        jtag_unlock_hosts: [0, 0, 0, 0]
+    sec_handover_cfg:
+        subhdr:
+            magic: 0x608F
+            size: 10
+        handover_msg_sender : 0
+        handover_to_host_id : 0
+        rsvd: [0, 0, 0, 0]
diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig
index afb54f8cda..fb596e4adf 100644
--- a/board/ti/am64x/Kconfig
+++ b/board/ti/am64x/Kconfig
@@ -9,6 +9,7 @@ choice
 config TARGET_AM642_A53_EVM
 	bool "TI K3 based AM642 EVM running on A53"
 	select ARM64
+	select BINMAN
 	imply BOARD
 	imply SPL_BOARD
 	imply TI_I2C_BOARD_DETECT
@@ -21,6 +22,7 @@ config TARGET_AM642_R5_EVM
 	select RAM
 	select SPL_RAM
 	select K3_DDRSS
+	select BINMAN
 	imply SYS_K3_SPL_ATF
 	imply TI_I2C_BOARD_DETECT
 
diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env
index c3960be38e..1567907fcb 100644
--- a/board/ti/am64x/am64x.env
+++ b/board/ti/am64x/am64x.env
@@ -1,14 +1,15 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/mmc.env>
-#include <environment/ti/k3_dfu.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
 
 findfdt=
 	if test $board_name = am64x_gpevm; then
-		setenv name_fdt k3-am642-evm.dtb; fi;
+		setenv name_fdt ti/k3-am642-evm.dtb; fi;
 	if test $board_name = am64x_skevm; then
-		setenv name_fdt k3-am642-sk.dtb; fi;
+		setenv name_fdt ti/k3-am642-sk.dtb; fi;
 	if test $name_fdt = undefined; then
 		echo WARNING: Could not determine device tree to use; fi;
+	setenv fdtfile ${name_fdt}
 name_kern=Image
 console=ttyS2,115200n8
 args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 ${mtdparts}
@@ -19,21 +20,6 @@ mmcdev=1
 bootpart=1:2
 bootdir=/boot
 rd_spec=-
-init_mmc=run args_all args_mmc
-get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
-get_overlay_mmc=
-	fdt address ${fdtaddr};
-	fdt resize 0x100000;
-	for overlay in $name_overlays;
-	do;
-	load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} &&
-	fdt apply ${dtboaddr};
-	done;
-get_kern_mmc=load mmc ${bootpart} ${loadaddr}
-	${bootdir}/${name_kern}
-get_fit_mmc=load mmc ${bootpart} ${addr_fit}
-	${bootdir}/${name_fit}
-partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
 
 args_usb=run finduuid;setenv bootargs console=${console}
 	${optargs}
diff --git a/board/ti/am64x/board-cfg.yaml b/board/ti/am64x/board-cfg.yaml
new file mode 100644
index 0000000000..62947c0820
--- /dev/null
+++ b/board/ti/am64x/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM64x
+#
+
+---
+
+board-cfg:
+        rev:
+                boardcfg_abi_maj : 0x0
+                boardcfg_abi_min : 0x1
+        control:
+                subhdr:
+                        magic: 0xC1D3
+                        size: 7
+                main_isolation_enable : 0x5A
+                main_isolation_hostid : 0x2
+        secproxy:
+                subhdr:
+                        magic: 0x1207
+                        size: 7
+                scaling_factor : 0x1
+                scaling_profile : 0x1
+                disable_main_nav_secure_proxy : 0
+        msmc:
+                subhdr:
+                        magic: 0xA5C3
+                        size: 5
+                msmc_cache_size : 0x0
+        debug_cfg:
+                subhdr:
+                        magic: 0x020C
+                        size: 8
+                trace_dst_enables : 0x00
+                trace_src_enables : 0x00
diff --git a/board/ti/am64x/pm-cfg.yaml b/board/ti/am64x/pm-cfg.yaml
new file mode 100644
index 0000000000..83c6a039f2
--- /dev/null
+++ b/board/ti/am64x/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM64x
+#
+
+---
+
+pm-cfg:
+        rev:
+                boardcfg_abi_maj : 0x0
+                boardcfg_abi_min : 0x1
diff --git a/board/ti/am64x/rm-cfg.yaml b/board/ti/am64x/rm-cfg.yaml
new file mode 100644
index 0000000000..1f4c6cf770
--- /dev/null
+++ b/board/ti/am64x/rm-cfg.yaml
@@ -0,0 +1,1400 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM64x
+#
+
+---
+
+rm-cfg:
+        rm_boardcfg:
+                rev:
+                        boardcfg_abi_maj : 0x0
+                        boardcfg_abi_min : 0x1
+                host_cfg:
+                        subhdr:
+                                magic: 0x4C41
+                                size : 356
+                        host_cfg_entries:
+                                - #1
+                                        host_id: 12
+                                        allowed_atype : 0x2A
+                                        allowed_qos : 0xAAAA
+                                        allowed_orderid : 0xAAAAAAAA
+                                        allowed_priority : 0xAAAA
+                                        allowed_sched_priority : 0xAA
+                                - #2
+                                        host_id: 30
+                                        allowed_atype : 0x2A
+                                        allowed_qos : 0xAAAA
+                                        allowed_orderid : 0xAAAAAAAA
+                                        allowed_priority : 0xAAAA
+                                        allowed_sched_priority : 0xAA
+                                - #3
+                                        host_id: 36
+                                        allowed_atype : 0x2A
+                                        allowed_qos : 0xAAAA
+                                        allowed_orderid : 0xAAAAAAAA
+                                        allowed_priority : 0xAAAA
+                                        allowed_sched_priority : 0xAA
+                                - #4
+                                        host_id: 38
+                                        allowed_atype : 0x2A
+                                        allowed_qos : 0xAAAA
+                                        allowed_orderid : 0xAAAAAAAA
+                                        allowed_priority : 0xAAAA
+                                        allowed_sched_priority : 0xAA
+                                - #5
+                                        host_id: 41
+                                        allowed_atype : 0x2A
+                                        allowed_qos : 0xAAAA
+                                        allowed_orderid : 0xAAAAAAAA
+                                        allowed_priority : 0xAAAA
+                                        allowed_sched_priority : 0xAA
+                                - #6
+                                        host_id: 43
+                                        allowed_atype : 0x2A
+                                        allowed_qos : 0xAAAA
+                                        allowed_orderid : 0xAAAAAAAA
+                                        allowed_priority : 0xAAAA
+                                        allowed_sched_priority : 0xAA
+                                - #7
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #8
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #9
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #10
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #11
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #12
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #13
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #14
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #15
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #16
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #17
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #18
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #19
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #20
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #21
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #22
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #23
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #24
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #25
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #26
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #27
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #28
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #29
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #30
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #31
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #32
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                resasg:
+                        subhdr:
+                                magic: 0x7B25
+                                size : 8
+                        resasg_entries_size: 1288
+                        reserved : 0
+        resasg_entries:
+        -
+                start_resource: 0
+                num_resource: 16
+                type: 64
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 16
+                num_resource: 4
+                type: 64
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 16
+                num_resource: 4
+                type: 64
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 20
+                num_resource: 4
+                type: 64
+                host_id: 38
+                reserved: 0
+
+        -
+                start_resource: 24
+                num_resource: 4
+                type: 64
+                host_id: 41
+                reserved: 0
+
+        -
+                start_resource: 28
+                num_resource: 4
+                type: 64
+                host_id: 43
+                reserved: 0
+
+        -
+                start_resource: 32
+                num_resource: 8
+                type: 64
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 12
+                type: 192
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 12
+                num_resource: 2
+                type: 192
+                host_id: 41
+                reserved: 0
+
+        -
+                start_resource: 14
+                num_resource: 2
+                type: 192
+                host_id: 43
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 4
+                type: 320
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 4
+                num_resource: 4
+                type: 320
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 41
+                type: 384
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 50176
+                num_resource: 136
+                type: 1666
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 1
+                type: 1667
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 12
+                type: 1677
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 12
+                num_resource: 6
+                type: 1677
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 12
+                num_resource: 6
+                type: 1677
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 18
+                num_resource: 2
+                type: 1677
+                host_id: 38
+                reserved: 0
+
+        -
+                start_resource: 20
+                num_resource: 4
+                type: 1677
+                host_id: 41
+                reserved: 0
+
+        -
+                start_resource: 24
+                num_resource: 2
+                type: 1677
+                host_id: 43
+                reserved: 0
+
+        -
+                start_resource: 26
+                num_resource: 1
+                type: 1677
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 27
+                num_resource: 1
+                type: 1677
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 48
+                num_resource: 6
+                type: 1678
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 54
+                num_resource: 6
+                type: 1678
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 54
+                num_resource: 6
+                type: 1678
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 60
+                num_resource: 2
+                type: 1678
+                host_id: 38
+                reserved: 0
+
+        -
+                start_resource: 62
+                num_resource: 4
+                type: 1678
+                host_id: 41
+                reserved: 0
+
+        -
+                start_resource: 66
+                num_resource: 2
+                type: 1678
+                host_id: 43
+                reserved: 0
+
+        -
+                start_resource: 28
+                num_resource: 6
+                type: 1679
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 34
+                num_resource: 6
+                type: 1679
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 34
+                num_resource: 6
+                type: 1679
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 40
+                num_resource: 2
+                type: 1679
+                host_id: 38
+                reserved: 0
+
+        -
+                start_resource: 42
+                num_resource: 4
+                type: 1679
+                host_id: 41
+                reserved: 0
+
+        -
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diff --git a/board/ti/am64x/sec-cfg.yaml b/board/ti/am64x/sec-cfg.yaml
new file mode 100644
index 0000000000..7c51fd3406
--- /dev/null
+++ b/board/ti/am64x/sec-cfg.yaml
@@ -0,0 +1,380 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security configuration for AM64x
+#
+
+---
+
+sec-cfg:
+        rev:
+                boardcfg_abi_maj : 0x0
+                boardcfg_abi_min : 0x1
+        processor_acl_list:
+                subhdr:
+                        magic: 0xF1EA
+                        size: 164
+                proc_acl_entries:
+                        - #1
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #2
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #3
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #4
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #5
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #6
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #7
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #8
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #9
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #10
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #11
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #12
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #13
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #14
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #15
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #16
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #17
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #18
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #19
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #20
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #21
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #22
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #23
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #24
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #25
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #26
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #27
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #28
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #29
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #30
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #31
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #32
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+
+        host_hierarchy:
+                subhdr:
+                        magic: 0x8D27
+                        size: 68
+                host_hierarchy_entries:
+                        - #1
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #2
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #3
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #4
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #5
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #6
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #7
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #8
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #9
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #10
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #11
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #12
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #13
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #14
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #15
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #16
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #17
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #18
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #19
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #20
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #21
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #22
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #23
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #24
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #25
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #26
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #27
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #28
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #29
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #30
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #31
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #32
+                                host_id: 0
+                                supervisor_host_id: 0
+        otp_config:
+                subhdr:
+                        magic: 0x4081
+                        size: 69
+                write_host_id : 0
+                otp_entry:
+                        - #1
+                                host_id: 0
+                                host_perms: 0
+                        - #2
+                                host_id: 0
+                                host_perms: 0
+                        - #3
+                                host_id: 0
+                                host_perms: 0
+                        - #4
+                                host_id: 0
+                                host_perms: 0
+                        - #5
+                                host_id: 0
+                                host_perms: 0
+                        - #6
+                                host_id: 0
+                                host_perms: 0
+                        - #7
+                                host_id: 0
+                                host_perms: 0
+                        - #8
+                                host_id: 0
+                                host_perms: 0
+                        - #9
+                                host_id: 0
+                                host_perms: 0
+                        - #10
+                                host_id: 0
+                                host_perms: 0
+                        - #11
+                                host_id: 0
+                                host_perms: 0
+                        - #12
+                                host_id: 0
+                                host_perms: 0
+                        - #13
+                                host_id: 0
+                                host_perms: 0
+                        - #14
+                                host_id: 0
+                                host_perms: 0
+                        - #15
+                                host_id: 0
+                                host_perms: 0
+                        - #16
+                                host_id: 0
+                                host_perms: 0
+                        - #17
+                                host_id: 0
+                                host_perms: 0
+                        - #18
+                                host_id: 0
+                                host_perms: 0
+                        - #19
+                                host_id: 0
+                                host_perms: 0
+                        - #20
+                                host_id: 0
+                                host_perms: 0
+                        - #21
+                                host_id: 0
+                                host_perms: 0
+                        - #22
+                                host_id: 0
+                                host_perms: 0
+                        - #23
+                                host_id: 0
+                                host_perms: 0
+                        - #24
+                                host_id: 0
+                                host_perms: 0
+                        - #25
+                                host_id: 0
+                                host_perms: 0
+                        - #26
+                                host_id: 0
+                                host_perms: 0
+                        - #27
+                                host_id: 0
+                                host_perms: 0
+                        - #28
+                                host_id: 0
+                                host_perms: 0
+                        - #29
+                                host_id: 0
+                                host_perms: 0
+                        - #30
+                                host_id: 0
+                                host_perms: 0
+                        - #31
+                                host_id: 0
+                                host_perms: 0
+                        - #32
+                                host_id: 0
+                                host_perms: 0
+        dkek_config:
+                subhdr:
+                        magic: 0x5170
+                        size: 12
+                allowed_hosts: [128, 0, 0, 0]
+                allow_dkek_export_tisci : 0x5A
+                rsvd: [0, 0, 0]
+        sa2ul_cfg:
+                subhdr:
+                        magic: 0x23BE
+                        size : 0
+                auth_resource_owner: 0
+                enable_saul_psil_global_config_writes: 0
+                rsvd: [0, 0]
+        sec_dbg_config:
+                subhdr:
+                        magic: 0x42AF
+                        size: 16
+                allow_jtag_unlock : 0x5A
+                allow_wildcard_unlock : 0x5A
+                allowed_debug_level_rsvd : 0
+                rsvd : 0
+                min_cert_rev : 0x0
+                jtag_unlock_hosts: [0, 0, 0, 0]
+        sec_handover_cfg:
+                subhdr:
+                        magic: 0x608F
+                        size: 10
+                handover_msg_sender : 0
+                handover_to_host_id : 0
+                rsvd: [0, 0, 0, 0]
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index 220dd0234c..5fd19d652a 100644
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -12,6 +12,7 @@ config TARGET_AM654_A53_EVM
 	select ARM64
 	select SYS_DISABLE_DCACHE_OPS
 	select BOARD_LATE_INIT
+	select BINMAN
 	imply TI_I2C_BOARD_DETECT
 
 config TARGET_AM654_R5_EVM
@@ -20,6 +21,7 @@ config TARGET_AM654_R5_EVM
 	select SYS_THUMB_BUILD
 	select K3_LOAD_SYSFW
 	select K3_AM654_DDRSS
+	select BINMAN
 	imply SYS_K3_SPL_ATF
 	imply TI_I2C_BOARD_DETECT
 
diff --git a/board/ti/am65x/README b/board/ti/am65x/README
deleted file mode 100644
index 67081ce349..0000000000
--- a/board/ti/am65x/README
+++ /dev/null
@@ -1,350 +0,0 @@
-Introduction:
--------------
-The AM65x family of SoCs is the first device family from K3 Multicore
-SoC architecture, targeted for broad market and industrial control with
-aim to meet the complex processing needs of modern embedded products.
-
-The device is built over three domains, each containing specific processing
-cores, voltage domains and peripherals:
-1. Wake-up (WKUP) domain:
-	- Device Management and Security Controller (DMSC)
-2. Microcontroller (MCU) domain:
-	- Dual Core ARM Cortex-R5F processor
-3. MAIN domain:
-	- Quad core 64-bit ARM Cortex-A53
-
-More info can be found in TRM: http://www.ti.com/lit/pdf/spruid7
-
-Boot Flow:
-----------
-On AM65x family devices, ROM supports boot only via MCU(R5). This means that
-bootloader has to run on R5 core. In order to meet this constraint, and for
-the following reasons the boot flow is designed as mentioned:
-1. Need to move away from R5 asap, so that we want to start *any*
-firmware on the r5 cores like.... autosar can be loaded to receive CAN
-response and other safety operations to be started. This operation is
-very time critical and is applicable for all automotive use cases.
-2. U-Boot on A53 should start other remotecores for various
-applications. This should happen before running Linux.
-3. In production boot flow, we might not like to use full u-boot,
-instead use Flacon boot flow to reduce boot time.
-
-+------------------------------------------------------------------------+
-|        DMSC            |         R5            |        A53            |
-+------------------------------------------------------------------------+
-|    +--------+          |                       |                       |
-|    |  Reset |          |                       |                       |
-|    +--------+          |                       |                       |
-|         :              |                       |                       |
-|    +--------+          |   +-----------+       |                       |
-|    | *ROM*  |----------|-->| Reset rls |       |                       |
-|    +--------+          |   +-----------+       |                       |
-|    |        |          |         :             |                       |
-|    |  ROM   |          |         :             |                       |
-|    |services|          |         :             |                       |
-|    |        |          |   +-------------+     |                       |
-|    |        |          |   |  *R5 ROM*   |     |                       |
-|    |        |          |   +-------------+     |                       |
-|    |        |<---------|---|Load and auth|     |                       |
-|    |        |          |   | tiboot3.bin |     |                       |
-|    |        |          |   +-------------+     |                       |
-|    |        |          |         :             |                       |
-|    |        |          |         :             |                       |
-|    |        |          |         :             |                       |
-|    |        |          |   +-------------+     |                       |
-|    |        |          |   |  *R5 SPL*   |     |                       |
-|    |        |          |   +-------------+     |                       |
-|    |        |          |   |    Load     |     |                       |
-|    |        |          |   |  sysfw.itb  |     |                       |
-|    | Start  |          |   +-------------+     |                       |
-|    | System |<---------|---|    Start    |     |                       |
-|    |Firmware|          |   |    SYSFW    |     |                       |
-|    +--------+          |   +-------------+     |                       |
-|        :               |   |             |     |                       |
-|    +---------+         |   |   Load      |     |                       |
-|    | *SYSFW* |         |   |   system    |     |                       |
-|    +---------+         |   | Config data |     |                       |
-|    |         |<--------|---|             |     |                       |
-|    |         |         |   +-------------+     |                       |
-|    |         |         |   |             |     |                       |
-|    |         |         |   |    DDR      |     |                       |
-|    |         |         |   |   config    |     |                       |
-|    |         |         |   +-------------+     |                       |
-|    |         |         |   |             |     |                       |
-|    |         |<--------|---| Start A53   |     |                       |
-|    |         |         |   |  and Reset  |     |                       |
-|    |         |         |   +-------------+     |                       |
-|    |         |         |                       |     +-----------+     |
-|    |         |---------|-----------------------|---->| Reset rls |     |
-|    |         |         |                       |     +-----------+     |
-|    |  DMSC   |         |                       |          :            |
-|    |Services |         |                       |     +-----------+     |
-|    |         |<--------|-----------------------|---->|*ATF/OPTEE*|     |
-|    |         |         |                       |     +-----------+     |
-|    |         |         |                       |          :            |
-|    |         |         |                       |     +-----------+     |
-|    |         |<--------|-----------------------|---->| *A53 SPL* |     |
-|    |         |         |                       |     +-----------+     |
-|    |         |         |                       |     |   Load    |     |
-|    |         |         |                       |     | u-boot.img|     |
-|    |         |         |                       |     +-----------+     |
-|    |         |         |                       |          :            |
-|    |         |         |                       |     +-----------+     |
-|    |         |<--------|-----------------------|---->| *U-Boot*  |     |
-|    |         |         |                       |     +-----------+     |
-|    |         |         |                       |     |  prompt   |     |
-|    |         |         |                       |     +-----------+     |
-|    +---------+         |                       |                       |
-|                        |                       |                       |
-+------------------------------------------------------------------------+
-
-- Here DMSC acts as master and provides all the critical services. R5/A53
-requests DMSC to get these services done as shown in the above diagram.
-
-Sources:
---------
-1. SYSFW:
-	Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git
-	Branch: master
-
-2. ATF:
-	Tree: https://github.com/ARM-software/arm-trusted-firmware.git
-	Branch: master
-
-3. OPTEE:
-	Tree: https://github.com/OP-TEE/optee_os.git
-	Branch: master
-
-4. U-Boot:
-	Tree: http://git.denx.de/u-boot.git
-	Branch: master
-
-Build procedure:
-----------------
-1. SYSFW:
-$ make CROSS_COMPILE=arm-linux-gnueabihf-
-
-2. ATF:
-$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed
-
-3. OPTEE:
-$ make PLATFORM=k3-am65x CFG_ARM64_core=y
-
-4. U-Boot:
-
-4.1. R5:
-$ make CROSS_COMPILE=arm-linux-gnueabihf- am65x_evm_r5_defconfig O=/tmp/r5
-$ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
-
-4.2. A53:
-$ make CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig O=/tmp/a53
-$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a53
-
-Target Images
---------------
-Copy the below images to an SD card and boot:
-- sysfw.itb from step 1
-- tiboot3.bin from step 4.1
-- tispl.bin, u-boot.img from 4.2
-
-Image formats:
---------------
-
-- tiboot3.bin:
-                +-----------------------+
-                |        X.509          |
-                |      Certificate      |
-                | +-------------------+ |
-                | |                   | |
-                | |        R5         | |
-                | |   u-boot-spl.bin  | |
-                | |                   | |
-                | +-------------------+ |
-                | |                   | |
-                | |     FIT header    | |
-                | | +---------------+ | |
-                | | |               | | |
-                | | |   DTB 1...N   | | |
-                | | +---------------+ | |
-                | +-------------------+ |
-                +-----------------------+
-
-- tispl.bin
-                +-----------------------+
-                |                       |
-                |       FIT HEADER      |
-                | +-------------------+ |
-                | |                   | |
-                | |      A53 ATF      | |
-                | +-------------------+ |
-                | |                   | |
-                | |     A53 OPTEE     | |
-                | +-------------------+ |
-                | |                   | |
-                | |      A53 SPL      | |
-                | +-------------------+ |
-                | |                   | |
-                | |   SPL DTB 1...N   | |
-                | +-------------------+ |
-                +-----------------------+
-
-- sysfw.itb
-                +-----------------------+
-                |                       |
-                |       FIT HEADER      |
-                | +-------------------+ |
-                | |                   | |
-                | |     sysfw.bin     | |
-                | +-------------------+ |
-                | |                   | |
-                | |    board config   | |
-                | +-------------------+ |
-                | |                   | |
-                | |     PM config     | |
-                | +-------------------+ |
-                | |                   | |
-                | |     RM config     | |
-                | +-------------------+ |
-                | |                   | |
-                | |    Secure config  | |
-                | +-------------------+ |
-                +-----------------------+
-
-eMMC:
------
-ROM supports booting from eMMC from boot0 partition offset 0x0
-
-Flashing images to eMMC:
-
-The following commands can be used to download tiboot3.bin, tispl.bin,
-u-boot.img, and sysfw.itb from an SD card and write them to the eMMC boot0
-partition at respective addresses.
-
-=> mmc dev 0 1
-=> fatload mmc 1 ${loadaddr} tiboot3.bin
-=> mmc write ${loadaddr} 0x0 0x400
-=> fatload mmc 1 ${loadaddr} tispl.bin
-=> mmc write ${loadaddr} 0x400 0x1000
-=> fatload mmc 1 ${loadaddr} u-boot.img
-=> mmc write ${loadaddr} 0x1400 0x2000
-=> fatload mmc 1 ${loadaddr} sysfw.itb
-=> mmc write ${loadaddr} 0x3600 0x800
-
-To give the ROM access to the boot partition, the following commands must be
-used for the first time:
-=> mmc partconf 0 1 1 1
-=> mmc bootbus 0 1 0 0
-
-To create a software partition for the rootfs, the following command can be
-used:
-=> gpt write mmc 0 ${partitions}
-
-eMMC layout:
-
-           boot0 partition (8 MB)                        user partition
-   0x0+----------------------------------+      0x0+-------------------------+
-      |     tiboot3.bin (512 KB)         |         |                         |
- 0x400+----------------------------------+         |                         |
-      |       tispl.bin (2 MB)           |         |                         |
-0x1400+----------------------------------+         |        rootfs           |
-      |       u-boot.img (4 MB)          |         |                         |
-0x3400+----------------------------------+         |                         |
-      |      environment (128 KB)        |         |                         |
-0x3500+----------------------------------+         |                         |
-      |   backup environment (128 KB)    |         |                         |
-0x3600+----------------------------------+         |                         |
-      |          sysfw (1 MB)            |         |                         |
-0x3E00+----------------------------------+         +-------------------------+
-
-Kernel image and DT are expected to be present in the /boot folder of rootfs.
-To boot kernel from eMMC, use the following commands:
-=> setenv mmcdev 0
-=> setenv bootpart 0
-=> boot
-
-OSPI:
------
-ROM supports booting from OSPI from offset 0x0.
-
-Flashing images to OSPI:
-
-Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
-and sysfw.itb over tftp and then flash those to OSPI at their respective
-addresses.
-
-=> sf probe
-=> tftp ${loadaddr} tiboot3.bin
-=> sf update $loadaddr 0x0 $filesize
-=> tftp ${loadaddr} tispl.bin
-=> sf update $loadaddr 0x80000 $filesize
-=> tftp ${loadaddr} u-boot.img
-=> sf update $loadaddr 0x280000 $filesize
-=> tftp ${loadaddr} sysfw.itb
-=> sf update $loadaddr 0x6C0000 $filesize
-
-Flash layout for OSPI:
-
-         0x0 +----------------------------+
-             |     ospi.tiboot3(512K)     |
-             |                            |
-     0x80000 +----------------------------+
-             |     ospi.tispl(2M)         |
-             |                            |
-    0x280000 +----------------------------+
-             |     ospi.u-boot(4M)        |
-             |                            |
-    0x680000 +----------------------------+
-             |     ospi.env(128K)         |
-             |                            |
-    0x6A0000 +----------------------------+
-	     |	 ospi.env.backup (128K)   |
-	     |                            |
-    0x6C0000 +----------------------------+
-             |      ospi.sysfw(1M)        |
-             |                            |
-    0x7C0000 +----------------------------+
-	     |      padding (256k)        |
-    0x800000 +----------------------------+
-             |     ospi.rootfs(UBIFS)     |
-             |                            |
-             +----------------------------+
-
-Kernel Image and DT are expected to be present in the /boot folder of UBIFS
-ospi.rootfs just like in SD card case. U-Boot looks for UBI volume named
-"rootfs" for rootfs.
-
-To boot kernel from OSPI, at the U-Boot prompt:
-=> setenv boot ubi
-=> boot
-
-UART:
------
-ROM supports booting from MCU_UART0 via X-Modem protocol. The entire UART-based
-boot process up to U-Boot (proper) prompt goes through different stages and uses
-different UART peripherals as follows:
-
-  WHO     | Loading WHAT  |  HW Module  |  Protocol
-----------+---------------+-------------+------------
-Boot ROM  |  tiboot3.bin  |  MCU_UART0  |  X-Modem(*)
-R5 SPL    |  sysfw.itb    |  MCU_UART0  |  Y-Modem(*)
-R5 SPL    |  tispl.bin    |  MAIN_UART0 |  Y-Modem
-A53 SPL   |  u-boot.img   |  MAIN_UART0 |  Y-Modem
-
-(*) Note that in addition to X/Y-Modem related protocol timeouts the DMSC
-    watchdog timeout of 3min (typ.) needs to be observed until System Firmware
-    is fully loaded (from sysfw.itb) and started.
-
-Example bash script sequence for running on a Linux host PC feeding all boot
-artifacts needed to the device:
-
-MCU_DEV=/dev/ttyUSB1
-MAIN_DEV=/dev/ttyUSB0
-
-stty -F $MCU_DEV 115200 cs8 -cstopb -parenb
-stty -F $MAIN_DEV 115200 cs8 -cstopb -parenb
-
-sb --xmodem tiboot3.bin > $MCU_DEV < $MCU_DEV
-sb --ymodem sysfw.itb > $MCU_DEV < $MCU_DEV
-sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV
-sleep 1
-sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV
diff --git a/board/ti/am65x/am65x.env b/board/ti/am65x/am65x.env
index a048b47071..755bff2707 100644
--- a/board/ti/am65x/am65x.env
+++ b/board/ti/am65x/am65x.env
@@ -1,12 +1,12 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/mmc.env>
-#include <environment/ti/k3_dfu.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
 #if CONFIG_CMD_REMOTEPROC
-#include <environment/ti/k3_rproc.env>
+#include <env/ti/k3_rproc.env>
 #endif
 
 findfdt=
-	setenv name_fdt k3-am654-base-board.dtb;
+	setenv name_fdt ti/k3-am654-base-board.dtb;
 	setenv fdtfile ${name_fdt}
 name_kern=Image
 console=ttyS2,115200n8
@@ -19,21 +19,6 @@ mmcdev=1
 bootpart=1:2
 bootdir=/boot
 rd_spec=-
-init_mmc=run args_all args_mmc
-get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
-get_overlay_mmc=
-	fdt address ${fdtaddr};
-	fdt resize 0x100000;
-	for overlay in $name_overlays;
-	do;
-	load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} &&
-	fdt apply ${dtboaddr};
-	done;
-get_kern_mmc=load mmc ${bootpart} ${loadaddr}
-	${bootdir}/${name_kern}
-get_fit_mmc=load mmc ${bootpart} ${addr_fit}
-	${bootdir}/${name_fit}
-partitions=name=root,start=0,size=-,uuid=${uuid_gpt_rootfs}
 
 init_ubi=
     run args_all args_ubi;
diff --git a/board/ti/am65x/board-cfg.yaml b/board/ti/am65x/board-cfg.yaml
new file mode 100644
index 0000000000..a8e06166d5
--- /dev/null
+++ b/board/ti/am65x/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM65x
+#
+
+---
+
+board-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
+    control:
+        subhdr:
+            magic: 0xC1D3
+            size: 7
+        main_isolation_enable : 0x5A
+        main_isolation_hostid : 0x2
+    secproxy:
+        subhdr:
+            magic: 0x1207
+            size: 7
+        scaling_factor : 0x1
+        scaling_profile : 0x1
+        disable_main_nav_secure_proxy : 0
+    msmc:
+        subhdr:
+            magic: 0xA5C3
+            size: 5
+        msmc_cache_size : 0x10
+    debug_cfg:
+        subhdr:
+            magic: 0x020C
+            size: 8
+        trace_dst_enables : 0x00
+        trace_src_enables : 0x00
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index 706b219818..d52ac332f8 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -59,7 +59,7 @@ int dram_init(void)
 	return 0;
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 #ifdef CONFIG_PHYS_64BIT
 	/* Limit RAM used by U-Boot to the DDR low region */
diff --git a/board/ti/am65x/pm-cfg.yaml b/board/ti/am65x/pm-cfg.yaml
new file mode 100644
index 0000000000..73fe86c29a
--- /dev/null
+++ b/board/ti/am65x/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM65x
+#
+
+---
+
+pm-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
diff --git a/board/ti/am65x/rm-cfg.yaml b/board/ti/am65x/rm-cfg.yaml
new file mode 100644
index 0000000000..5903773e81
--- /dev/null
+++ b/board/ti/am65x/rm-cfg.yaml
@@ -0,0 +1,2068 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM65x
+#
+
+---
+
+rm-cfg:
+    rm_boardcfg:
+        rev:
+            boardcfg_abi_maj : 0x0
+            boardcfg_abi_min : 0x1
+        host_cfg:
+            subhdr:
+                magic: 0x4C41
+                size : 356
+            host_cfg_entries:
+                - #1
+                    host_id: 3
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #2
+                    host_id: 5
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #3
+                    host_id: 12
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #4
+                    host_id: 13
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #5
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #6
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #7
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #8
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #9
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #10
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #11
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #12
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #13
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #14
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #15
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #16
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #17
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #18
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #19
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #20
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #21
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #22
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #23
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #24
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #25
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #26
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #27
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #28
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #29
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #30
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #31
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #32
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+        resasg:
+            subhdr:
+                magic: 0x7B25
+                size : 8
+            resasg_entries_size: 2080
+            reserved : 0
+    resasg_entries:
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+
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diff --git a/board/ti/am65x/sec-cfg.yaml b/board/ti/am65x/sec-cfg.yaml
new file mode 100644
index 0000000000..7fa12f0bed
--- /dev/null
+++ b/board/ti/am65x/sec-cfg.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for AM65x
+#
+
+---
+
+sec-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
+    processor_acl_list:
+        subhdr:
+            magic: 0xF1EA
+            size: 164
+        proc_acl_entries:
+            - #1
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #2
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #3
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #4
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #5
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #6
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #7
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #8
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #9
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #10
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #11
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #12
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #13
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #14
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #15
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #16
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #17
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #18
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #19
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #20
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #21
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #22
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #23
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #24
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #25
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #26
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #27
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #28
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #29
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #30
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #31
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #32
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+    host_hierarchy:
+        subhdr:
+            magic: 0x8D27
+            size: 68
+        host_hierarchy_entries:
+            - #1
+                host_id: 0
+                supervisor_host_id: 0
+            - #2
+                host_id: 0
+                supervisor_host_id: 0
+            - #3
+                host_id: 0
+                supervisor_host_id: 0
+            - #4
+                host_id: 0
+                supervisor_host_id: 0
+            - #5
+                host_id: 0
+                supervisor_host_id: 0
+            - #6
+                host_id: 0
+                supervisor_host_id: 0
+            - #7
+                host_id: 0
+                supervisor_host_id: 0
+            - #8
+                host_id: 0
+                supervisor_host_id: 0
+            - #9
+                host_id: 0
+                supervisor_host_id: 0
+            - #10
+                host_id: 0
+                supervisor_host_id: 0
+            - #11
+                host_id: 0
+                supervisor_host_id: 0
+            - #12
+                host_id: 0
+                supervisor_host_id: 0
+            - #13
+                host_id: 0
+                supervisor_host_id: 0
+            - #14
+                host_id: 0
+                supervisor_host_id: 0
+            - #15
+                host_id: 0
+                supervisor_host_id: 0
+            - #16
+                host_id: 0
+                supervisor_host_id: 0
+            - #17
+                host_id: 0
+                supervisor_host_id: 0
+            - #18
+                host_id: 0
+                supervisor_host_id: 0
+            - #19
+                host_id: 0
+                supervisor_host_id: 0
+            - #20
+                host_id: 0
+                supervisor_host_id: 0
+            - #21
+                host_id: 0
+                supervisor_host_id: 0
+            - #22
+                host_id: 0
+                supervisor_host_id: 0
+            - #23
+                host_id: 0
+                supervisor_host_id: 0
+            - #24
+                host_id: 0
+                supervisor_host_id: 0
+            - #25
+                host_id: 0
+                supervisor_host_id: 0
+            - #26
+                host_id: 0
+                supervisor_host_id: 0
+            - #27
+                host_id: 0
+                supervisor_host_id: 0
+            - #28
+                host_id: 0
+                supervisor_host_id: 0
+            - #29
+                host_id: 0
+                supervisor_host_id: 0
+            - #30
+                host_id: 0
+                supervisor_host_id: 0
+            - #31
+                host_id: 0
+                supervisor_host_id: 0
+            - #32
+                host_id: 0
+                supervisor_host_id: 0
+    otp_config:
+        subhdr:
+            magic: 0x4081
+            size: 69
+        write_host_id : 0
+        otp_entry:
+            - #1
+                host_id: 0
+                host_perms: 0
+            - #2
+                host_id: 0
+                host_perms: 0
+            - #3
+                host_id: 0
+                host_perms: 0
+            - #4
+                host_id: 0
+                host_perms: 0
+            - #5
+                host_id: 0
+                host_perms: 0
+            - #6
+                host_id: 0
+                host_perms: 0
+            - #7
+                host_id: 0
+                host_perms: 0
+            - #8
+                host_id: 0
+                host_perms: 0
+            - #9
+                host_id: 0
+                host_perms: 0
+            - #10
+                host_id: 0
+                host_perms: 0
+            - #11
+                host_id: 0
+                host_perms: 0
+            - #12
+                host_id: 0
+                host_perms: 0
+            - #13
+                host_id: 0
+                host_perms: 0
+            - #14
+                host_id: 0
+                host_perms: 0
+            - #15
+                host_id: 0
+                host_perms: 0
+            - #16
+                host_id: 0
+                host_perms: 0
+            - #17
+                host_id: 0
+                host_perms: 0
+            - #18
+                host_id: 0
+                host_perms: 0
+            - #19
+                host_id: 0
+                host_perms: 0
+            - #20
+                host_id: 0
+                host_perms: 0
+            - #21
+                host_id: 0
+                host_perms: 0
+            - #22
+                host_id: 0
+                host_perms: 0
+            - #23
+                host_id: 0
+                host_perms: 0
+            - #24
+                host_id: 0
+                host_perms: 0
+            - #25
+                host_id: 0
+                host_perms: 0
+            - #26
+                host_id: 0
+                host_perms: 0
+            - #27
+                host_id: 0
+                host_perms: 0
+            - #28
+                host_id: 0
+                host_perms: 0
+            - #29
+                host_id: 0
+                host_perms: 0
+            - #30
+                host_id: 0
+                host_perms: 0
+            - #31
+                host_id: 0
+                host_perms: 0
+            - #32
+                host_id: 0
+                host_perms: 0
+    dkek_config:
+        subhdr:
+            magic: 0x5170
+            size: 12
+        allowed_hosts: [128, 0, 0, 0]
+        allow_dkek_export_tisci : 0x5A
+        rsvd: [0, 0, 0]
+    sa2ul_cfg:
+        subhdr:
+            magic: 0x23BE
+            size : 0
+        auth_resource_owner: 0
+        enable_saul_psil_global_config_writes: 0
+        rsvd: [0, 0]
+    sec_dbg_config:
+        subhdr:
+            magic: 0x42AF
+            size: 16
+        allow_jtag_unlock : 0x5A
+        allow_wildcard_unlock : 0x5A
+        allowed_debug_level_rsvd: 0
+        rsvd: 0
+        min_cert_rev : 0x0
+        jtag_unlock_hosts: [0, 0, 0, 0]
+    sec_handover_cfg:
+        subhdr:
+            magic: 0x608F
+            size: 10
+        handover_msg_sender : 0
+        handover_to_host_id : 0
+        rsvd: [0, 0, 0, 0]
diff --git a/board/ti/common/schema.yaml b/board/ti/common/schema.yaml
new file mode 100644
index 0000000000..c8dd2e79e7
--- /dev/null
+++ b/board/ti/common/schema.yaml
@@ -0,0 +1,436 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Config schema for TI K3 devices
+#
+
+---
+
+definitions:
+    u8:
+        type: integer
+        minimum: 0
+        maximum: 0xff
+    u16:
+        type: integer
+        minimum: 0
+        maximum: 0xffff
+    u32:
+        type: integer
+        minimum: 0
+        maximum: 0xffffffff
+
+
+
+type: object
+properties:
+    pm-cfg:
+        type: object
+        properties:
+            rev:
+                type: object
+                properties:
+                    boardcfg_abi_maj:
+                        $ref: "#/definitions/u8"
+                    boardcfg_abi_min:
+                        $ref: "#/definitions/u8"
+    board-cfg:
+        type: object
+        properties:
+            rev:
+                type: object
+                properties:
+                    boardcfg_abi_maj:
+                        $ref: "#/definitions/u8"
+                    boardcfg_abi_min:
+                        $ref: "#/definitions/u8"
+            control:
+                type: object
+                properties:
+                    subhdr:
+                        type: object
+                        properties:
+                            magic:
+                                $ref: "#/definitions/u16"
+                            size:
+                                $ref: "#/definitions/u16"
+                    main_isolation_enable:
+                        $ref: "#/definitions/u8"
+                    main_isolation_hostid:
+                        $ref: "#/definitions/u16"
+
+
+            secproxy:
+                type: object
+                properties:
+                    subhdr:
+                        type: object
+                        properties:
+                            magic:
+                                $ref: "#/definitions/u16"
+                            size:
+                                $ref: "#/definitions/u16"
+                    scaling_factor:
+                        $ref: "#/definitions/u8"
+                    scaling_profile:
+                        $ref: "#/definitions/u8"
+                    disable_main_nav_secure_proxy:
+                        $ref: "#/definitions/u8"
+
+            msmc:
+                type: object
+                properties:
+                    subhdr:
+                        type: object
+                        properties:
+                            magic:
+                                $ref: "#/definitions/u16"
+                            size:
+                                $ref: "#/definitions/u16"
+                    msmc_cache_size:
+                        $ref: "#/definitions/u8"
+            debug_cfg:
+                type: object
+                properties:
+                    subhdr:
+                        type: object
+                        properties:
+                            magic:
+                                $ref: "#/definitions/u16"
+                            size:
+                                $ref: "#/definitions/u16"
+                    trace_dst_enables:
+                        $ref: "#/definitions/u16"
+                    trace_src_enables:
+                        $ref: "#/definitions/u16"
+
+    sec-cfg:
+        type: object
+        properties:
+            rev:
+                type: object
+                properties:
+                    boardcfg_abi_maj:
+                        $ref: "#/definitions/u8"
+                    boardcfg_abi_min:
+                        $ref: "#/definitions/u8"
+
+            processor_acl_list:
+                type: object
+                properties:
+                    subhdr:
+                        type: object
+                        properties:
+                            magic:
+                                $ref: "#/definitions/u16"
+                            size:
+                                $ref: "#/definitions/u16"
+                    proc_acl_entries:
+                        type: array
+                        minItems: 32
+                        maxItems: 32
+                        items:
+                            type: object
+                            properties:
+                                processor_id:
+                                    $ref: "#/definitions/u8"
+                                proc_access_master:
+                                    $ref: "#/definitions/u8"
+                                proc_access_secondary:
+                                    type: array
+                                    minItems: 3
+                                    maxItems: 3
+                                    items:
+                                        $ref: "#/definitions/u8"
+            host_hierarchy:
+                type: object
+                properties:
+                    subhdr:
+                        type: object
+                        properties:
+                            magic:
+                                $ref: "#/definitions/u16"
+                            size:
+                                $ref: "#/definitions/u16"
+                    host_hierarchy_entries:
+                        type: array
+                        minItems: 32
+                        maxItems: 32
+                        items:
+                            type: object
+                            properties:
+                                host_id:
+                                    $ref: "#/definitions/u8"
+                                supervisor_host_id:
+                                    $ref: "#/definitions/u8"
+
+            otp_config:
+                type: object
+                properties:
+                    subhdr:
+                        type: object
+                        properties:
+                            magic:
+                                $ref: "#/definitions/u16"
+                            size:
+                                $ref: "#/definitions/u16"
+                    otp_entry:
+                        type: array
+                        minItems: 32
+                        maxItems: 32
+                        items:
+                            type: object
+                            properties:
+                                host_id:
+                                    $ref: "#/definitions/u8"
+                                host_perms:
+                                    $ref: "#/definitions/u8"
+                    write_host_id:
+                        $ref: "#/definitions/u8"
+
+            dkek_config:
+                type: object
+                properties:
+                    subhdr:
+                        type: object
+                        properties:
+                            magic:
+                                $ref: "#/definitions/u16"
+                            size:
+                                $ref: "#/definitions/u16"
+                    allowed_hosts:
+                        type: array
+                        minItems: 4
+                        maxItems: 4
+                        items:
+                            $ref: "#/definitions/u8"
+                    allow_dkek_export_tisci:
+                        $ref: "#/definitions/u8"
+                    rsvd:
+                        type: array
+                        minItems: 3
+                        maxItems: 3
+                        items:
+                            $ref: "#/definitions/u8"
+
+            sa2ul_cfg:
+                type: object
+                properties:
+                    subhdr:
+                        type: object
+                        properties:
+                            magic:
+                                $ref: "#/definitions/u16"
+                            size:
+                                $ref: "#/definitions/u16"
+                    rsvd:
+                        type: array
+                        minItems: 2
+                        maxItems: 4
+                        items:
+                            $ref: "#/definitions/u8"
+                    enable_saul_psil_global_config_writes:
+                        $ref: "#/definitions/u8"
+                    auth_resource_owner:
+                        $ref: "#/definitions/u8"
+
+            sec_dbg_config:
+                type: object
+                properties:
+                    subhdr:
+                        type: object
+                        properties:
+                            magic:
+                                $ref: "#/definitions/u16"
+                            size:
+                                $ref: "#/definitions/u16"
+                    allow_jtag_unlock:
+                        $ref: "#/definitions/u8"
+                    allow_wildcard_unlock:
+                        $ref: "#/definitions/u8"
+                    allowed_debug_level_rsvd:
+                        $ref: "#/definitions/u8"
+                    rsvd:
+                        $ref: "#/definitions/u8"
+                    min_cert_rev:
+                        $ref: "#/definitions/u32"
+                    jtag_unlock_hosts:
+                        type: array
+                        minItems: 4
+                        maxItems: 4
+                        items:
+                            $ref: "#/definitions/u8"
+
+
+            sec_handover_cfg:
+                type: object
+                properties:
+                    subhdr:
+                        type: object
+                        properties:
+                            magic:
+                                $ref: "#/definitions/u16"
+                            size:
+                                $ref: "#/definitions/u16"
+                    handover_msg_sender:
+                        $ref: "#/definitions/u8"
+                    handover_to_host_id:
+                        $ref: "#/definitions/u8"
+                    rsvd:
+                        type: array
+                        minItems: 4
+                        maxItems: 4
+                        items:
+                            $ref: "#/definitions/u8"
+
+    rm-cfg:
+        type: object
+        properties:
+            rm_boardcfg:
+                type: object
+                properties:
+                    rev:
+                        type: object
+                        properties:
+                            boardcfg_abi_maj:
+                                $ref: "#/definitions/u8"
+                            boardcfg_abi_min:
+                                $ref: "#/definitions/u8"
+
+                    host_cfg:
+                        type: object
+                        properties:
+                            subhdr:
+                                type: object
+                                properties:
+                                    magic:
+                                        $ref: "#/definitions/u16"
+                                    size:
+                                        $ref: "#/definitions/u16"
+                            host_cfg_entries:
+                                type: array
+                                minItems: 0
+                                maxItems: 32
+                                items:
+                                    type: object
+                                    properties:
+                                        host_id:
+                                            $ref: "#/definitions/u8"
+                                        allowed_atype:
+                                            $ref: "#/definitions/u8"
+                                        allowed_qos:
+                                            $ref: "#/definitions/u16"
+                                        allowed_orderid:
+                                            $ref: "#/definitions/u32"
+                                        allowed_priority:
+                                            $ref: "#/definitions/u16"
+                                        allowed_sched_priority:
+                                            $ref: "#/definitions/u8"
+                    resasg:
+                        type: object
+                        properties:
+                            subhdr:
+                                type: object
+                                properties:
+                                    magic:
+                                        $ref: "#/definitions/u16"
+                                    size:
+                                        $ref: "#/definitions/u16"
+                            resasg_entries_size:
+                                        $ref: "#/definitions/u16"
+                            reserved:
+                                        $ref: "#/definitions/u16"
+
+            resasg_entries:
+                type: array
+                minItems: 0
+                maxItems: 468
+                items:
+                    type: object
+                    properties:
+                        start_resource:
+                            $ref: "#/definitions/u16"
+                        num_resource:
+                            $ref: "#/definitions/u16"
+                        type:
+                            $ref: "#/definitions/u16"
+                        host_id:
+                            $ref: "#/definitions/u8"
+                        reserved:
+                            $ref: "#/definitions/u8"
+
+    tifs-rm-cfg:
+        type: object
+        properties:
+            rm_boardcfg:
+                type: object
+                properties:
+                    rev:
+                        type: object
+                        properties:
+                            boardcfg_abi_maj:
+                                $ref: "#/definitions/u8"
+                            boardcfg_abi_min:
+                                $ref: "#/definitions/u8"
+
+                    host_cfg:
+                        type: object
+                        properties:
+                            subhdr:
+                                type: object
+                                properties:
+                                    magic:
+                                        $ref: "#/definitions/u16"
+                                    size:
+                                        $ref: "#/definitions/u16"
+                            host_cfg_entries:
+                                type: array
+                                minItems: 0
+                                maxItems: 32
+                                items:
+                                    type: object
+                                    properties:
+                                        host_id:
+                                            $ref: "#/definitions/u8"
+                                        allowed_atype:
+                                            $ref: "#/definitions/u8"
+                                        allowed_qos:
+                                            $ref: "#/definitions/u16"
+                                        allowed_orderid:
+                                            $ref: "#/definitions/u32"
+                                        allowed_priority:
+                                            $ref: "#/definitions/u16"
+                                        allowed_sched_priority:
+                                            $ref: "#/definitions/u8"
+                    resasg:
+                        type: object
+                        properties:
+                            subhdr:
+                                type: object
+                                properties:
+                                    magic:
+                                        $ref: "#/definitions/u16"
+                                    size:
+                                        $ref: "#/definitions/u16"
+                            resasg_entries_size:
+                                        $ref: "#/definitions/u16"
+                            reserved:
+                                        $ref: "#/definitions/u16"
+
+            resasg_entries:
+                type: array
+                minItems: 0
+                maxItems: 468
+                items:
+                    type: object
+                    properties:
+                        start_resource:
+                            $ref: "#/definitions/u16"
+                        num_resource:
+                            $ref: "#/definitions/u16"
+                        type:
+                            $ref: "#/definitions/u16"
+                        host_id:
+                            $ref: "#/definitions/u8"
+                        reserved:
+                            $ref: "#/definitions/u8"
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index 84bca32712..e6cb21f77b 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -13,6 +13,7 @@ config TARGET_J721E_A72_EVM
 	select BOARD_LATE_INIT
 	imply TI_I2C_BOARD_DETECT
 	select SYS_DISABLE_DCACHE_OPS
+	select BINMAN
 
 config TARGET_J721E_R5_EVM
 	bool "TI K3 based J721E EVM running on R5"
@@ -22,6 +23,7 @@ config TARGET_J721E_R5_EVM
 	select RAM
 	select SPL_RAM
 	select K3_DDRSS
+	select BINMAN
 	imply SYS_K3_SPL_ATF
 	imply TI_I2C_BOARD_DETECT
 
@@ -31,6 +33,7 @@ config TARGET_J7200_A72_EVM
 	select BOARD_LATE_INIT
 	imply TI_I2C_BOARD_DETECT
 	select SYS_DISABLE_DCACHE_OPS
+	select BINMAN
 
 config TARGET_J7200_R5_EVM
 	bool "TI K3 based J7200 EVM running on R5"
@@ -40,6 +43,7 @@ config TARGET_J7200_R5_EVM
 	select RAM
 	select SPL_RAM
 	select K3_DDRSS
+	select BINMAN
 	imply SYS_K3_SPL_ATF
 	imply TI_I2C_BOARD_DETECT
 
diff --git a/board/ti/j721e/board-cfg.yaml b/board/ti/j721e/board-cfg.yaml
new file mode 100644
index 0000000000..1375dcad35
--- /dev/null
+++ b/board/ti/j721e/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J721E
+#
+
+---
+
+board-cfg:
+        rev:
+                boardcfg_abi_maj: 0x0
+                boardcfg_abi_min: 0x1
+        control:
+                subhdr:
+                        magic: 0xC1D3
+                        size: 7
+                main_isolation_enable: 0x5A
+                main_isolation_hostid: 0x2
+        secproxy:
+                subhdr:
+                        magic: 0x1207
+                        size: 7
+                scaling_factor: 0x1
+                scaling_profile: 0x1
+                disable_main_nav_secure_proxy: 0
+        msmc:
+                subhdr:
+                        magic: 0xA5C3
+                        size: 5
+                msmc_cache_size: 0x0
+        debug_cfg:
+                subhdr:
+                        magic: 0x020C
+                        size: 8
+                trace_dst_enables: 0x00
+                trace_src_enables: 0x00
diff --git a/board/ti/j721e/board-cfg_j7200.yaml b/board/ti/j721e/board-cfg_j7200.yaml
new file mode 100644
index 0000000000..0ac1ae93fe
--- /dev/null
+++ b/board/ti/j721e/board-cfg_j7200.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J7200
+#
+
+---
+
+board-cfg:
+        rev:
+                boardcfg_abi_maj : 0x0
+                boardcfg_abi_min : 0x1
+        control:
+                subhdr:
+                        magic: 0xC1D3
+                        size: 7
+                main_isolation_enable : 0x5A
+                main_isolation_hostid : 0x2
+        secproxy:
+                subhdr:
+                        magic: 0x1207
+                        size: 7
+                scaling_factor : 0x1
+                scaling_profile : 0x1
+                disable_main_nav_secure_proxy : 0
+        msmc:
+                subhdr:
+                        magic: 0xA5C3
+                        size: 5
+                msmc_cache_size : 0x10
+        debug_cfg:
+                subhdr:
+                        magic: 0x020C
+                        size: 8
+                trace_dst_enables : 0x00
+                trace_src_enables : 0x00
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 2398bead78..38fe447d8f 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -55,7 +55,7 @@ int dram_init(void)
 	return 0;
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 #ifdef CONFIG_PHYS_64BIT
 	/* Limit RAM used by U-Boot to the DDR low region */
diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env
index c181741ca5..2f2fb05912 100644
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -1,21 +1,21 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/mmc.env>
-#include <environment/ti/ufs.env>
-#include <environment/ti/k3_dfu.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/mmc.env>
+#include <env/ti/ufs.env>
+#include <env/ti/k3_dfu.env>
 
 #if CONFIG_CMD_REMOTEPROC
-#include <environment/ti/k3_rproc.env>
+#include <env/ti/k3_rproc.env>
 #endif
 
-default_device_tree=k3-j721e-common-proc-board.dtb
+default_device_tree=ti/k3-j721e-common-proc-board.dtb
 findfdt=
 	setenv name_fdt ${default_device_tree};
 	if test $board_name = j721e; then
-		setenv name_fdt k3-j721e-common-proc-board.dtb; fi;
+		setenv name_fdt ti/k3-j721e-common-proc-board.dtb; fi;
 	if test $board_name = j7200; then
-		setenv name_fdt k3-j7200-common-proc-board.dtb; fi;
+		setenv name_fdt ti/k3-j7200-common-proc-board.dtb; fi;
 	if test $board_name = j721e-eaik || test $board_name = j721e-sk; then
-		setenv name_fdt k3-j721e-sk.dtb; fi;
+		setenv name_fdt ti/k3-j721e-sk.dtb; fi;
 	setenv fdtfile ${name_fdt}
 name_kern=Image
 console=ttyS2,115200n8
@@ -36,22 +36,6 @@ mmcdev=1
 bootpart=1:2
 bootdir=/boot
 rd_spec=-
-init_mmc=run args_all args_mmc
-get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
-get_overlay_mmc=
-	fdt address ${fdtaddr};
-	fdt resize 0x100000;
-	for overlay in $name_overlays;
-	do;
-	load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} &&
-	fdt apply ${dtboaddr};
-	done;
-partitions=uuid_disk=${uuid_gpt_disk};
-	name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
-get_kern_mmc=load mmc ${bootpart} ${loadaddr}
-	${bootdir}/${name_kern}
-get_fit_mmc=load mmc ${bootpart} ${addr_fit}
-	${bootdir}/${name_fit}
 
 #if CONFIG_TARGET_J7200_A72_EVM
 do_main_cpsw0_qsgmii_phyinit=1
diff --git a/board/ti/j721e/pm-cfg.yaml b/board/ti/j721e/pm-cfg.yaml
new file mode 100644
index 0000000000..7ae52b3358
--- /dev/null
+++ b/board/ti/j721e/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for J721E
+#
+
+---
+
+pm-cfg:
+        rev:
+                boardcfg_abi_maj: 0x0
+                boardcfg_abi_min: 0x1
diff --git a/board/ti/j721e/pm-cfg_j7200.yaml b/board/ti/j721e/pm-cfg_j7200.yaml
new file mode 100644
index 0000000000..daaefb1318
--- /dev/null
+++ b/board/ti/j721e/pm-cfg_j7200.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for J7200
+#
+
+---
+
+pm-cfg:
+        rev:
+                boardcfg_abi_maj : 0x0
+                boardcfg_abi_min : 0x1
diff --git a/board/ti/j721e/rm-cfg.yaml b/board/ti/j721e/rm-cfg.yaml
new file mode 100644
index 0000000000..9f604cf1aa
--- /dev/null
+++ b/board/ti/j721e/rm-cfg.yaml
@@ -0,0 +1,3174 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J721E
+#
+
+---
+
+rm-cfg:
+        rm_boardcfg:
+                rev:
+                        boardcfg_abi_maj: 0x0
+                        boardcfg_abi_min: 0x1
+                host_cfg:
+                        subhdr:
+                                magic: 0x4C41
+                                size: 356
+                        host_cfg_entries:
+                                - #1
+                                        host_id: 3
+                                        allowed_atype: 0x2A
+                                        allowed_qos: 0xAAAA
+                                        allowed_orderid: 0xAAAAAAAA
+                                        allowed_priority: 0xAAAA
+                                        allowed_sched_priority: 0xAA
+                                - #2
+                                        host_id: 5
+                                        allowed_atype: 0x2A
+                                        allowed_qos: 0xAAAA
+                                        allowed_orderid: 0xAAAAAAAA
+                                        allowed_priority: 0xAAAA
+                                        allowed_sched_priority: 0xAA
+                                - #3
+                                        host_id: 12
+                                        allowed_atype: 0x2A
+                                        allowed_qos: 0xAAAA
+                                        allowed_orderid: 0xAAAAAAAA
+                                        allowed_priority: 0xAAAA
+                                        allowed_sched_priority: 0xAA
+                                - #4
+                                        host_id: 13
+                                        allowed_atype: 0x2A
+                                        allowed_qos: 0xAAAA
+                                        allowed_orderid: 0xAAAAAAAA
+                                        allowed_priority: 0xAAAA
+                                        allowed_sched_priority: 0xAA
+                                - #5
+                                        host_id: 21
+                                        allowed_atype: 0x2A
+                                        allowed_qos: 0xAAAA
+                                        allowed_orderid: 0xAAAAAAAA
+                                        allowed_priority: 0xAAAA
+                                        allowed_sched_priority: 0xAA
+                                - #6
+                                        host_id: 26
+                                        allowed_atype: 0x2A
+                                        allowed_qos: 0xAAAA
+                                        allowed_orderid: 0xAAAAAAAA
+                                        allowed_priority: 0xAAAA
+                                        allowed_sched_priority: 0xAA
+                                - #7
+                                        host_id: 28
+                                        allowed_atype: 0x2A
+                                        allowed_qos: 0xAAAA
+                                        allowed_orderid: 0xAAAAAAAA
+                                        allowed_priority: 0xAAAA
+                                        allowed_sched_priority: 0xAA
+                                - #8
+                                        host_id: 35
+                                        allowed_atype: 0x2A
+                                        allowed_qos: 0xAAAA
+                                        allowed_orderid: 0xAAAAAAAA
+                                        allowed_priority: 0xAAAA
+                                        allowed_sched_priority: 0xAA
+                                - #9
+                                        host_id: 37
+                                        allowed_atype: 0x2A
+                                        allowed_qos: 0xAAAA
+                                        allowed_orderid: 0xAAAAAAAA
+                                        allowed_priority: 0xAAAA
+                                        allowed_sched_priority: 0xAA
+                                - #10
+                                        host_id: 40
+                                        allowed_atype: 0x2A
+                                        allowed_qos: 0xAAAA
+                                        allowed_orderid: 0xAAAAAAAA
+                                        allowed_priority: 0xAAAA
+                                        allowed_sched_priority: 0xAA
+                                - #11
+                                        host_id: 42
+                                        allowed_atype: 0x2A
+                                        allowed_qos: 0xAAAA
+                                        allowed_orderid: 0xAAAAAAAA
+                                        allowed_priority: 0xAAAA
+                                        allowed_sched_priority: 0xAA
+                                - #12
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #13
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #14
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #15
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #16
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #17
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #18
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #19
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #20
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #21
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #22
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #23
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #24
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #25
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #26
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #27
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #28
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #29
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #30
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #31
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                                - #32
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                resasg:
+                        subhdr:
+                                magic: 0x7B25
+                                size: 8
+                        resasg_entries_size: 3344
+                        reserved: 0
+        resasg_entries:
+                -
+                        start_resource: 4
+                        num_resource: 93
+                        type: 7744
+                        host_id: 26
+                        reserved: 0
+
+                -
+                        start_resource: 4
+                        num_resource: 93
+                        type: 7808
+                        host_id: 28
+                        reserved: 0
+
+                -
+                        start_resource: 0
+                        num_resource: 32
+                        type: 7872
+                        host_id: 128
+                        reserved: 0
+
+                -
+                        start_resource: 0
+                        num_resource: 32
+                        type: 8192
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 32
+                        num_resource: 32
+                        type: 8192
+                        host_id: 5
+                        reserved: 0
+
+                -
+                        start_resource: 0
+                        num_resource: 24
+                        type: 8320
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 24
+                        num_resource: 24
+                        type: 8320
+                        host_id: 5
+                        reserved: 0
+
+                -
+                        start_resource: 0
+                        num_resource: 8
+                        type: 8384
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 8
+                        num_resource: 8
+                        type: 8384
+                        host_id: 5
+                        reserved: 0
+
+                -
+                        start_resource: 16
+                        num_resource: 4
+                        type: 8384
+                        host_id: 40
+                        reserved: 0
+
+                -
+                        start_resource: 20
+                        num_resource: 4
+                        type: 8384
+                        host_id: 42
+                        reserved: 0
+
+                -
+                        start_resource: 24
+                        num_resource: 4
+                        type: 8384
+                        host_id: 35
+                        reserved: 0
+
+                -
+                        start_resource: 28
+                        num_resource: 4
+                        type: 8384
+                        host_id: 37
+                        reserved: 0
+
+                -
+                        start_resource: 32
+                        num_resource: 4
+                        type: 8384
+                        host_id: 26
+                        reserved: 0
+
+                -
+                        start_resource: 36
+                        num_resource: 4
+                        type: 8384
+                        host_id: 28
+                        reserved: 0
+
+                -
+                        start_resource: 40
+                        num_resource: 12
+                        type: 8384
+                        host_id: 12
+                        reserved: 0
+
+                -
+                        start_resource: 52
+                        num_resource: 12
+                        type: 8384
+                        host_id: 13
+                        reserved: 0
+
+                -
+                        start_resource: 0
+                        num_resource: 128
+                        type: 8576
+                        host_id: 35
+                        reserved: 0
+
+                -
+                        start_resource: 128
+                        num_resource: 128
+                        type: 8576
+                        host_id: 37
+                        reserved: 0
+
+                -
+                        start_resource: 0
+                        num_resource: 128
+                        type: 8640
+                        host_id: 40
+                        reserved: 0
+
+                -
+                        start_resource: 128
+                        num_resource: 128
+                        type: 8640
+                        host_id: 42
+                        reserved: 0
+
+                -
+                        start_resource: 0
+                        num_resource: 48
+                        type: 8704
+                        host_id: 128
+                        reserved: 0
+
+                -
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+                        num_resource: 8
+                        type: 8768
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 8
+                        num_resource: 8
+                        type: 8768
+                        host_id: 5
+                        reserved: 0
+
+                -
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+                        reserved: 0
+
+                -
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+                        num_resource: 6
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+                        reserved: 0
+
+                -
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+                        num_resource: 2
+                        type: 8768
+                        host_id: 35
+                        reserved: 0
+
+                -
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+                        type: 8768
+                        host_id: 37
+                        reserved: 0
+
+                -
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+                        host_id: 128
+                        reserved: 0
+
+                -
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+                        type: 13261
+                        host_id: 128
+                        reserved: 0
+
+                -
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+                        host_id: 128
+                        reserved: 0
+
+                -
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+                        num_resource: 1024
+                        type: 13325
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+                        reserved: 0
+
+                -
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+                        host_id: 12
+                        reserved: 0
+
+                -
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+                        reserved: 0
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+                -
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+                        reserved: 0
+
+                -
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+                        num_resource: 12
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+                        reserved: 0
+
+                -
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+                -
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+                        reserved: 0
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+
+                -
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+                -
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+                        reserved: 0
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+                -
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+                -
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+                        num_resource: 32
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+                        reserved: 0
+
+                -
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+                        num_resource: 32
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+                        reserved: 0
+
+                -
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+
+                -
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+                        num_resource: 256
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+                        reserved: 0
+
+                -
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+                        num_resource: 256
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+                        reserved: 0
+
+                -
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+                        reserved: 0
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+
+                -
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+                        reserved: 0
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+                        num_resource: 1
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+                        reserved: 0
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+                        num_resource: 1
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+                        reserved: 0
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+                        num_resource: 2
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+                        reserved: 0
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+                        num_resource: 1
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+                        reserved: 0
+
+                -
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+                        num_resource: 2
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+                        reserved: 0
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+                -
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+                        num_resource: 0
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+                        reserved: 0
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+                        num_resource: 2
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+                        reserved: 0
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+                -
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+                        reserved: 0
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+                        num_resource: 0
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+                        reserved: 0
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+                -
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+                        num_resource: 0
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+                        host_id: 5
+                        reserved: 0
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+                -
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+                        num_resource: 1
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+                        reserved: 0
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+                -
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+                        num_resource: 1
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+                        num_resource: 1
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+                        host_id: 3
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+                        num_resource: 28
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+                        reserved: 0
diff --git a/board/ti/j721e/rm-cfg_j7200.yaml b/board/ti/j721e/rm-cfg_j7200.yaml
new file mode 100644
index 0000000000..263285ff42
--- /dev/null
+++ b/board/ti/j721e/rm-cfg_j7200.yaml
@@ -0,0 +1,2065 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J7200
+#
+
+---
+
+rm-cfg:
+        rm_boardcfg:
+                rev:
+                        boardcfg_abi_maj : 0x0
+                        boardcfg_abi_min : 0x1
+                host_cfg:
+                        subhdr:
+                                magic: 0x4C41
+                                size : 356
+                        host_cfg_entries:
+                                - #1
+                                        host_id: 3
+                                        allowed_atype : 0b101010
+                                        allowed_qos : 0xAAAA
+                                        allowed_orderid : 0xAAAAAAAA
+                                        allowed_priority : 0xAAAA
+                                        allowed_sched_priority : 0xAA
+                                - #2
+                                        host_id: 5
+                                        allowed_atype : 0b101010
+                                        allowed_qos : 0xAAAA
+                                        allowed_orderid : 0xAAAAAAAA
+                                        allowed_priority : 0xAAAA
+                                        allowed_sched_priority : 0xAA
+                                - #3
+                                        host_id: 12
+                                        allowed_atype : 0b101010
+                                        allowed_qos : 0xAAAA
+                                        allowed_orderid : 0xAAAAAAAA
+                                        allowed_priority : 0xAAAA
+                                        allowed_sched_priority : 0xAA
+                                - #4
+                                        host_id: 13
+                                        allowed_atype : 0b101010
+                                        allowed_qos : 0xAAAA
+                                        allowed_orderid : 0xAAAAAAAA
+                                        allowed_priority : 0xAAAA
+                                        allowed_sched_priority : 0xAA
+                                - #5
+                                        host_id: 35
+                                        allowed_atype : 0b101010
+                                        allowed_qos : 0xAAAA
+                                        allowed_orderid : 0xAAAAAAAA
+                                        allowed_priority : 0xAAAA
+                                        allowed_sched_priority : 0xAA
+                                - #6
+                                        host_id: 37
+                                        allowed_atype : 0b101010
+                                        allowed_qos : 0xAAAA
+                                        allowed_orderid : 0xAAAAAAAA
+                                        allowed_priority : 0xAAAA
+                                        allowed_sched_priority : 0xAA
+                                - #7
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #8
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #9
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #10
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #11
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #12
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #13
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #14
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #15
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #16
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #17
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #18
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #19
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #20
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #21
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #22
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #23
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #24
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #25
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #26
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #27
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #28
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #29
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #30
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #31
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+
+                                - #32
+                                        host_id: 0
+                                        allowed_atype: 0
+                                        allowed_qos: 0
+                                        allowed_orderid: 0
+                                        allowed_priority: 0
+                                        allowed_sched_priority: 0
+                resasg:
+                        subhdr:
+                                magic: 0x7B25
+                                size : 8
+                        resasg_entries_size: 2048
+                        reserved : 0
+        resasg_entries:
+                -
+                        start_resource: 0
+                        num_resource: 32
+                        type: 8192
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 32
+                        num_resource: 32
+                        type: 8192
+                        host_id: 5
+                        reserved: 0
+
+                -
+                        start_resource: 0
+                        num_resource: 24
+                        type: 8320
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 24
+                        num_resource: 24
+                        type: 8320
+                        host_id: 5
+                        reserved: 0
+
+                -
+                        start_resource: 0
+                        num_resource: 8
+                        type: 8384
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 8
+                        num_resource: 8
+                        type: 8384
+                        host_id: 5
+                        reserved: 0
+
+                -
+                        start_resource: 16
+                        num_resource: 8
+                        type: 8384
+                        host_id: 35
+                        reserved: 0
+
+                -
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+                        num_resource: 8
+                        type: 8384
+                        host_id: 37
+                        reserved: 0
+
+                -
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+                        num_resource: 16
+                        type: 8384
+                        host_id: 12
+                        reserved: 0
+
+                -
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+                        num_resource: 16
+                        type: 8384
+                        host_id: 13
+                        reserved: 0
+
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+                        type: 8704
+                        host_id: 128
+                        reserved: 0
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+                        reserved: 0
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+                        host_id: 128
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+                        reserved: 0
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+                        reserved: 0
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+                        type: 15115
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 2
+                        num_resource: 3
+                        type: 15117
+                        host_id: 12
+                        reserved: 0
+
+                -
+                        start_resource: 5
+                        num_resource: 2
+                        type: 15117
+                        host_id: 13
+                        reserved: 0
+
+                -
+                        start_resource: 7
+                        num_resource: 2
+                        type: 15117
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 9
+                        num_resource: 2
+                        type: 15117
+                        host_id: 5
+                        reserved: 0
+
+                -
+                        start_resource: 11
+                        num_resource: 2
+                        type: 15117
+                        host_id: 35
+                        reserved: 0
+
+                -
+                        start_resource: 13
+                        num_resource: 2
+                        type: 15117
+                        host_id: 37
+                        reserved: 0
+
+                -
+                        start_resource: 15
+                        num_resource: 9
+                        type: 15117
+                        host_id: 12
+                        reserved: 0
+
+                -
+                        start_resource: 24
+                        num_resource: 4
+                        type: 15117
+                        host_id: 13
+                        reserved: 0
+
+                -
+                        start_resource: 28
+                        num_resource: 4
+                        type: 15117
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 32
+                        num_resource: 4
+                        type: 15117
+                        host_id: 5
+                        reserved: 0
+
+                -
+                        start_resource: 36
+                        num_resource: 4
+                        type: 15117
+                        host_id: 35
+                        reserved: 0
+
+                -
+                        start_resource: 40
+                        num_resource: 4
+                        type: 15117
+                        host_id: 37
+                        reserved: 0
+
+                -
+                        start_resource: 44
+                        num_resource: 2
+                        type: 15117
+                        host_id: 128
+                        reserved: 0
+
+                -
+                        start_resource: 0
+                        num_resource: 0
+                        type: 15119
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 0
+                        num_resource: 0
+                        type: 15119
+                        host_id: 12
+                        reserved: 0
+
+                -
+                        start_resource: 0
+                        num_resource: 1
+                        type: 15119
+                        host_id: 12
+                        reserved: 0
+
+                -
+                        start_resource: 1
+                        num_resource: 1
+                        type: 15119
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 11
+                        num_resource: 20
+                        type: 15168
+                        host_id: 3
+                        reserved: 0
+
+                -
+                        start_resource: 36
+                        num_resource: 28
+                        type: 15168
+                        host_id: 5
+                        reserved: 0
diff --git a/board/ti/j721e/sec-cfg.yaml b/board/ti/j721e/sec-cfg.yaml
new file mode 100644
index 0000000000..1eab5883a7
--- /dev/null
+++ b/board/ti/j721e/sec-cfg.yaml
@@ -0,0 +1,380 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security configuration for J721E
+#
+
+---
+
+sec-cfg:
+        rev:
+                boardcfg_abi_maj: 0x0
+                boardcfg_abi_min: 0x1
+        processor_acl_list:
+                subhdr:
+                        magic: 0xF1EA
+                        size: 164
+                proc_acl_entries:
+                        - #1
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #2
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #3
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #4
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #5
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #6
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #7
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #8
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #9
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #10
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #11
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #12
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #13
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #14
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #15
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #16
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #17
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #18
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #19
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #20
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #21
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #22
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #23
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #24
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #25
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #26
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #27
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #28
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #29
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #30
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #31
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #32
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+
+        host_hierarchy:
+                subhdr:
+                        magic: 0x8D27
+                        size: 68
+                host_hierarchy_entries:
+                        - #1
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #2
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #3
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #4
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #5
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #6
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #7
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #8
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #9
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #10
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #11
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #12
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #13
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #14
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #15
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #16
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #17
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #18
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #19
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #20
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #21
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #22
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #23
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #24
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #25
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #26
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #27
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #28
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #29
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #30
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #31
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #32
+                                host_id: 0
+                                supervisor_host_id: 0
+        otp_config:
+                subhdr:
+                        magic: 0x4081
+                        size: 69
+                otp_entry:
+                        - #1
+                                host_id: 0
+                                host_perms: 0
+                        - #2
+                                host_id: 0
+                                host_perms: 0
+                        - #3
+                                host_id: 0
+                                host_perms: 0
+                        - #4
+                                host_id: 0
+                                host_perms: 0
+                        - #5
+                                host_id: 0
+                                host_perms: 0
+                        - #6
+                                host_id: 0
+                                host_perms: 0
+                        - #7
+                                host_id: 0
+                                host_perms: 0
+                        - #8
+                                host_id: 0
+                                host_perms: 0
+                        - #9
+                                host_id: 0
+                                host_perms: 0
+                        - #10
+                                host_id: 0
+                                host_perms: 0
+                        - #11
+                                host_id: 0
+                                host_perms: 0
+                        - #12
+                                host_id: 0
+                                host_perms: 0
+                        - #13
+                                host_id: 0
+                                host_perms: 0
+                        - #14
+                                host_id: 0
+                                host_perms: 0
+                        - #15
+                                host_id: 0
+                                host_perms: 0
+                        - #16
+                                host_id: 0
+                                host_perms: 0
+                        - #17
+                                host_id: 0
+                                host_perms: 0
+                        - #18
+                                host_id: 0
+                                host_perms: 0
+                        - #19
+                                host_id: 0
+                                host_perms: 0
+                        - #20
+                                host_id: 0
+                                host_perms: 0
+                        - #21
+                                host_id: 0
+                                host_perms: 0
+                        - #22
+                                host_id: 0
+                                host_perms: 0
+                        - #23
+                                host_id: 0
+                                host_perms: 0
+                        - #24
+                                host_id: 0
+                                host_perms: 0
+                        - #25
+                                host_id: 0
+                                host_perms: 0
+                        - #26
+                                host_id: 0
+                                host_perms: 0
+                        - #27
+                                host_id: 0
+                                host_perms: 0
+                        - #28
+                                host_id: 0
+                                host_perms: 0
+                        - #29
+                                host_id: 0
+                                host_perms: 0
+                        - #30
+                                host_id: 0
+                                host_perms: 0
+                        - #31
+                                host_id: 0
+                                host_perms: 0
+                        - #32
+                                host_id: 0
+                                host_perms: 0
+                write_host_id: 0
+        dkek_config:
+                subhdr:
+                        magic: 0x5170
+                        size: 12
+                allowed_hosts: [128, 0, 0, 0]
+                allow_dkek_export_tisci: 0x5A
+                rsvd: [0, 0, 0]
+        sa2ul_cfg:
+                subhdr:
+                        magic: 0x23BE
+                        size: 0
+                auth_resource_owner: 0
+                enable_saul_psil_global_config_writes: 0
+                rsvd: [0, 0]
+        sec_dbg_config:
+                subhdr:
+                        magic: 0x42AF
+                        size: 16
+                allow_jtag_unlock: 0x5A
+                allow_wildcard_unlock: 0x5A
+                allowed_debug_level_rsvd: 0
+                rsvd: 0
+                min_cert_rev: 0x0
+                jtag_unlock_hosts: [0, 0, 0, 0]
+        sec_handover_cfg:
+                subhdr:
+                        magic: 0x608F
+                        size: 10
+                handover_msg_sender: 0
+                handover_to_host_id: 0
+                rsvd: [0, 0, 0, 0]
diff --git a/board/ti/j721e/sec-cfg_j7200.yaml b/board/ti/j721e/sec-cfg_j7200.yaml
new file mode 100644
index 0000000000..c346087a81
--- /dev/null
+++ b/board/ti/j721e/sec-cfg_j7200.yaml
@@ -0,0 +1,380 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for J7200
+#
+
+---
+
+sec-cfg:
+        rev:
+                boardcfg_abi_maj : 0x0
+                boardcfg_abi_min : 0x1
+        processor_acl_list:
+                subhdr:
+                        magic: 0xF1EA
+                        size: 164
+                proc_acl_entries:
+                        - #1
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #2
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #3
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #4
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #5
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #6
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #7
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #8
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #9
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #10
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #11
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #12
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #13
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #14
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #15
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #16
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #17
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #18
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #19
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #20
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #21
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #22
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #23
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #24
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #25
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #26
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #27
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #28
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #29
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #30
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #31
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+                        - #32
+                                processor_id: 0
+                                proc_access_master: 0
+                                proc_access_secondary: [0, 0, 0]
+
+        host_hierarchy:
+                subhdr:
+                        magic: 0x8D27
+                        size: 68
+                host_hierarchy_entries:
+                        - #1
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #2
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #3
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #4
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #5
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #6
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #7
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #8
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #9
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #10
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #11
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #12
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #13
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #14
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #15
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #16
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #17
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #18
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #19
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #20
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #21
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #22
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #23
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #24
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #25
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #26
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #27
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #28
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #29
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #30
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #31
+                                host_id: 0
+                                supervisor_host_id: 0
+                        - #32
+                                host_id: 0
+                                supervisor_host_id: 0
+        otp_config:
+                subhdr:
+                        magic: 0x4081
+                        size: 69
+                write_host_id : 0
+                otp_entry:
+                        - #1
+                                host_id: 0
+                                host_perms: 0
+                        - #2
+                                host_id: 0
+                                host_perms: 0
+                        - #3
+                                host_id: 0
+                                host_perms: 0
+                        - #4
+                                host_id: 0
+                                host_perms: 0
+                        - #5
+                                host_id: 0
+                                host_perms: 0
+                        - #6
+                                host_id: 0
+                                host_perms: 0
+                        - #7
+                                host_id: 0
+                                host_perms: 0
+                        - #8
+                                host_id: 0
+                                host_perms: 0
+                        - #9
+                                host_id: 0
+                                host_perms: 0
+                        - #10
+                                host_id: 0
+                                host_perms: 0
+                        - #11
+                                host_id: 0
+                                host_perms: 0
+                        - #12
+                                host_id: 0
+                                host_perms: 0
+                        - #13
+                                host_id: 0
+                                host_perms: 0
+                        - #14
+                                host_id: 0
+                                host_perms: 0
+                        - #15
+                                host_id: 0
+                                host_perms: 0
+                        - #16
+                                host_id: 0
+                                host_perms: 0
+                        - #17
+                                host_id: 0
+                                host_perms: 0
+                        - #18
+                                host_id: 0
+                                host_perms: 0
+                        - #19
+                                host_id: 0
+                                host_perms: 0
+                        - #20
+                                host_id: 0
+                                host_perms: 0
+                        - #21
+                                host_id: 0
+                                host_perms: 0
+                        - #22
+                                host_id: 0
+                                host_perms: 0
+                        - #23
+                                host_id: 0
+                                host_perms: 0
+                        - #24
+                                host_id: 0
+                                host_perms: 0
+                        - #25
+                                host_id: 0
+                                host_perms: 0
+                        - #26
+                                host_id: 0
+                                host_perms: 0
+                        - #27
+                                host_id: 0
+                                host_perms: 0
+                        - #28
+                                host_id: 0
+                                host_perms: 0
+                        - #29
+                                host_id: 0
+                                host_perms: 0
+                        - #30
+                                host_id: 0
+                                host_perms: 0
+                        - #31
+                                host_id: 0
+                                host_perms: 0
+                        - #32
+                                host_id: 0
+                                host_perms: 0
+        dkek_config:
+                subhdr:
+                        magic: 0x5170
+                        size: 12
+                allowed_hosts: [128, 0, 0, 0]
+                allow_dkek_export_tisci : 0x5A
+                rsvd: [0, 0, 0]
+        sa2ul_cfg:
+                subhdr:
+                        magic: 0x23BE
+                        size : 0
+                auth_resource_owner: 0
+                enable_saul_psil_global_config_writes: 0
+                rsvd: [0, 0]
+        sec_dbg_config:
+                subhdr:
+                        magic: 0x42AF
+                        size: 16
+                allow_jtag_unlock : 0x5A
+                allow_wildcard_unlock : 0x5A
+                allowed_debug_level_rsvd : 0
+                rsvd : 0
+                min_cert_rev : 0x0
+                jtag_unlock_hosts: [0, 0, 0, 0]
+        sec_handover_cfg:
+                subhdr:
+                        magic: 0x608F
+                        size: 10
+                handover_msg_sender : 0
+                handover_to_host_id : 0
+                rsvd: [0, 0, 0, 0]
diff --git a/board/ti/j721s2/Kconfig b/board/ti/j721s2/Kconfig
index a24641f8cf..f6d1cb5765 100644
--- a/board/ti/j721s2/Kconfig
+++ b/board/ti/j721s2/Kconfig
@@ -13,6 +13,7 @@ config TARGET_J721S2_A72_EVM
 	select BOARD_LATE_INIT
 	imply TI_I2C_BOARD_DETECT
 	select SYS_DISABLE_DCACHE_OPS
+	select BINMAN
 
 config TARGET_J721S2_R5_EVM
 	bool "TI K3 based J721S2 EVM running on R5"
@@ -22,6 +23,7 @@ config TARGET_J721S2_R5_EVM
 	select RAM
 	select SPL_RAM
 	select K3_DDRSS
+	select BINMAN
 	imply SYS_K3_SPL_ATF
 	imply TI_I2C_BOARD_DETECT
 
diff --git a/board/ti/j721s2/board-cfg.yaml b/board/ti/j721s2/board-cfg.yaml
new file mode 100644
index 0000000000..dd024110e7
--- /dev/null
+++ b/board/ti/j721s2/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J721S2
+#
+
+---
+
+board-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
+    control:
+        subhdr:
+            magic: 0xC1D3
+            size: 7
+        main_isolation_enable : 0x5A
+        main_isolation_hostid : 0x2
+    secproxy:
+        subhdr:
+            magic: 0x1207
+            size: 7
+        scaling_factor : 0x1
+        scaling_profile : 0x1
+        disable_main_nav_secure_proxy : 0
+    msmc:
+        subhdr:
+            magic: 0xA5C3
+            size: 5
+        msmc_cache_size : 0x0
+    debug_cfg:
+        subhdr:
+            magic: 0x020C
+            size: 8
+        trace_dst_enables : 0x00
+        trace_src_enables : 0x00
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 8eaca9d5af..7795300abc 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -43,7 +43,7 @@ int dram_init(void)
 	return 0;
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 #ifdef CONFIG_PHYS_64BIT
 	/* Limit RAM used by U-Boot to the DDR low region */
diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env
index f4467770e4..6825b14698 100644
--- a/board/ti/j721s2/j721s2.env
+++ b/board/ti/j721s2/j721s2.env
@@ -1,19 +1,19 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/mmc.env>
-#include <environment/ti/ufs.env>
-#include <environment/ti/k3_dfu.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/mmc.env>
+#include <env/ti/ufs.env>
+#include <env/ti/k3_dfu.env>
 
 #if CONFIG_CMD_REMOTEPROC
-#include <environment/ti/k3_rproc.env>
+#include <env/ti/k3_rproc.env>
 #endif
 
-default_device_tree=k3-j721s2-common-proc-board.dtb
+default_device_tree=ti/k3-j721s2-common-proc-board.dtb
 findfdt=
 	setenv name_fdt ${default_device_tree};
 	if test $board_name = j721s2; then			\
-		setenv name_fdt k3-j721s2-common-proc-board.dtb; fi;
+		setenv name_fdt ti/k3-j721s2-common-proc-board.dtb; fi;
 	if test $board_name = am68-sk; then
-		setenv name_fdt k3-am68-sk-base-board.dtb; fi;
+		setenv name_fdt ti/k3-am68-sk-base-board.dtb; fi;
 	setenv fdtfile ${name_fdt}
 name_kern=Image
 console=ttyS2,115200n8
@@ -30,24 +30,6 @@ addr_mcur5f0_0load=0x89000000
 name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw
 #endif
 rd_spec=-
-init_mmc=run args_all args_mmc
-get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
-get_overlay_mmc=
-	fdt address ${fdtaddr};
-	fdt resize 0x100000;
-	for overlay in $name_overlays;
-	do;
-	load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} &&
-	fdt apply ${dtboaddr};
-	done;
-partitions=uuid_disk=${uuid_gpt_disk};
-	name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
-get_kern_mmc=load mmc ${bootpart} ${loadaddr}
-	${bootdir}/${name_kern}
-get_fit_mmc=load mmc ${bootpart} ${addr_fit}
-	${bootdir}/${name_fit}
-partitions=uuid_disk=${uuid_gpt_disk};
-	name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
 
 rproc_fw_binaries= 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw
 
diff --git a/board/ti/j721s2/pm-cfg.yaml b/board/ti/j721s2/pm-cfg.yaml
new file mode 100644
index 0000000000..a640460d30
--- /dev/null
+++ b/board/ti/j721s2/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for J721S2
+#
+
+---
+
+pm-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
diff --git a/board/ti/j721s2/rm-cfg.yaml b/board/ti/j721s2/rm-cfg.yaml
new file mode 100644
index 0000000000..f772832f19
--- /dev/null
+++ b/board/ti/j721s2/rm-cfg.yaml
@@ -0,0 +1,2901 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J721S2
+#
+
+---
+
+rm-cfg:
+    rm_boardcfg:
+        rev:
+            boardcfg_abi_maj : 0x0
+            boardcfg_abi_min : 0x1
+        host_cfg:
+            subhdr:
+                magic: 0x4C41
+                size : 356
+            host_cfg_entries:
+                - #1
+                    host_id: 3
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #2
+                    host_id: 5
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #3
+                    host_id: 12
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #4
+                    host_id: 13
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #5
+                    host_id: 21
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #6
+                    host_id: 23
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #7
+                    host_id: 35
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #8
+                    host_id: 37
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #9
+                    host_id: 40
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #10
+                    host_id: 42
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #11
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #12
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #13
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #14
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #15
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #16
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #17
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #18
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #19
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #20
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #21
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #22
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #23
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #24
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #25
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #26
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #27
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #28
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #29
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #30
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #31
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #32
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+        resasg:
+            subhdr:
+                magic: 0x7B25
+                size : 8
+            resasg_entries_size: 3032
+            reserved : 0
+    resasg_entries:
+        -
+                start_resource: 0
+                num_resource: 32
+                type: 7744
+                host_id: 3
+                reserved: 0
+
+        -
+                start_resource: 32
+                num_resource: 24
+                type: 7744
+                host_id: 5
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 24
+                type: 7808
+                host_id: 3
+                reserved: 0
+
+        -
+                start_resource: 24
+                num_resource: 16
+                type: 7808
+                host_id: 5
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 48
+                type: 7936
+                host_id: 128
+                reserved: 0
+
+        -
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+                num_resource: 8
+                type: 8000
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+                reserved: 0
+
+        -
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+                num_resource: 8
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+                host_id: 5
+                reserved: 0
+
+        -
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+                num_resource: 6
+                type: 8000
+                host_id: 12
+                reserved: 0
+
+        -
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+                num_resource: 6
+                type: 8000
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+                reserved: 0
+
+        -
+                start_resource: 28
+                num_resource: 2
+                type: 8000
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 30
+                num_resource: 2
+                type: 8000
+                host_id: 37
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 4
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+                reserved: 0
+
+        -
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+                num_resource: 4
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+                reserved: 0
+
+        -
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+                reserved: 0
+
+        -
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+                reserved: 0
+
+        -
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+                reserved: 0
+
+        -
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+                reserved: 0
+
+        -
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+                num_resource: 12
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+                host_id: 12
+                reserved: 0
+
+        -
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+                host_id: 13
+                reserved: 0
+
+        -
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+                host_id: 128
+                reserved: 0
+
+        -
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+                host_id: 128
+                reserved: 0
+
+        -
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+                reserved: 0
+
+        -
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+
+        -
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+
+        -
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+
+        -
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+
+        -
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+
+        -
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+
+        -
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+
+        -
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+
+        -
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+
+        -
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+        -
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+
+        -
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+
+        -
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+        -
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+        -
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+        -
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+
+        -
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+
+        -
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+
+        -
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+
+        -
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+        -
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+
+        -
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+
+        -
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+        -
+                start_resource: 17174
+                num_resource: 128
+                type: 17613
+                host_id: 42
+                reserved: 0
+
+        -
+                start_resource: 17302
+                num_resource: 256
+                type: 17613
+                host_id: 3
+                reserved: 0
+
+        -
+                start_resource: 17558
+                num_resource: 64
+                type: 17613
+                host_id: 5
+                reserved: 0
+
+        -
+                start_resource: 17622
+                num_resource: 298
+                type: 17613
+                host_id: 128
+                reserved: 0
diff --git a/board/ti/j721s2/sec-cfg.yaml b/board/ti/j721s2/sec-cfg.yaml
new file mode 100644
index 0000000000..b3601d2a1c
--- /dev/null
+++ b/board/ti/j721s2/sec-cfg.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for J721S2
+#
+
+---
+
+sec-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
+    processor_acl_list:
+        subhdr:
+            magic: 0xF1EA
+            size: 164
+        proc_acl_entries:
+            - #1
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #2
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #3
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #4
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #5
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #6
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #7
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #8
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #9
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #10
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #11
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #12
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #13
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #14
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #15
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #16
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #17
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #18
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #19
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #20
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #21
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #22
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #23
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #24
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #25
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #26
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #27
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #28
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #29
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #30
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #31
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #32
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+    host_hierarchy:
+        subhdr:
+            magic: 0x8D27
+            size: 68
+        host_hierarchy_entries:
+            - #1
+                host_id: 0
+                supervisor_host_id: 0
+            - #2
+                host_id: 0
+                supervisor_host_id: 0
+            - #3
+                host_id: 0
+                supervisor_host_id: 0
+            - #4
+                host_id: 0
+                supervisor_host_id: 0
+            - #5
+                host_id: 0
+                supervisor_host_id: 0
+            - #6
+                host_id: 0
+                supervisor_host_id: 0
+            - #7
+                host_id: 0
+                supervisor_host_id: 0
+            - #8
+                host_id: 0
+                supervisor_host_id: 0
+            - #9
+                host_id: 0
+                supervisor_host_id: 0
+            - #10
+                host_id: 0
+                supervisor_host_id: 0
+            - #11
+                host_id: 0
+                supervisor_host_id: 0
+            - #12
+                host_id: 0
+                supervisor_host_id: 0
+            - #13
+                host_id: 0
+                supervisor_host_id: 0
+            - #14
+                host_id: 0
+                supervisor_host_id: 0
+            - #15
+                host_id: 0
+                supervisor_host_id: 0
+            - #16
+                host_id: 0
+                supervisor_host_id: 0
+            - #17
+                host_id: 0
+                supervisor_host_id: 0
+            - #18
+                host_id: 0
+                supervisor_host_id: 0
+            - #19
+                host_id: 0
+                supervisor_host_id: 0
+            - #20
+                host_id: 0
+                supervisor_host_id: 0
+            - #21
+                host_id: 0
+                supervisor_host_id: 0
+            - #22
+                host_id: 0
+                supervisor_host_id: 0
+            - #23
+                host_id: 0
+                supervisor_host_id: 0
+            - #24
+                host_id: 0
+                supervisor_host_id: 0
+            - #25
+                host_id: 0
+                supervisor_host_id: 0
+            - #26
+                host_id: 0
+                supervisor_host_id: 0
+            - #27
+                host_id: 0
+                supervisor_host_id: 0
+            - #28
+                host_id: 0
+                supervisor_host_id: 0
+            - #29
+                host_id: 0
+                supervisor_host_id: 0
+            - #30
+                host_id: 0
+                supervisor_host_id: 0
+            - #31
+                host_id: 0
+                supervisor_host_id: 0
+            - #32
+                host_id: 0
+                supervisor_host_id: 0
+    otp_config:
+        subhdr:
+            magic: 0x4081
+            size: 69
+        write_host_id : 0
+        otp_entry:
+            - #1
+                host_id: 0
+                host_perms: 0
+            - #2
+                host_id: 0
+                host_perms: 0
+            - #3
+                host_id: 0
+                host_perms: 0
+            - #4
+                host_id: 0
+                host_perms: 0
+            - #5
+                host_id: 0
+                host_perms: 0
+            - #6
+                host_id: 0
+                host_perms: 0
+            - #7
+                host_id: 0
+                host_perms: 0
+            - #8
+                host_id: 0
+                host_perms: 0
+            - #9
+                host_id: 0
+                host_perms: 0
+            - #10
+                host_id: 0
+                host_perms: 0
+            - #11
+                host_id: 0
+                host_perms: 0
+            - #12
+                host_id: 0
+                host_perms: 0
+            - #13
+                host_id: 0
+                host_perms: 0
+            - #14
+                host_id: 0
+                host_perms: 0
+            - #15
+                host_id: 0
+                host_perms: 0
+            - #16
+                host_id: 0
+                host_perms: 0
+            - #17
+                host_id: 0
+                host_perms: 0
+            - #18
+                host_id: 0
+                host_perms: 0
+            - #19
+                host_id: 0
+                host_perms: 0
+            - #20
+                host_id: 0
+                host_perms: 0
+            - #21
+                host_id: 0
+                host_perms: 0
+            - #22
+                host_id: 0
+                host_perms: 0
+            - #23
+                host_id: 0
+                host_perms: 0
+            - #24
+                host_id: 0
+                host_perms: 0
+            - #25
+                host_id: 0
+                host_perms: 0
+            - #26
+                host_id: 0
+                host_perms: 0
+            - #27
+                host_id: 0
+                host_perms: 0
+            - #28
+                host_id: 0
+                host_perms: 0
+            - #29
+                host_id: 0
+                host_perms: 0
+            - #30
+                host_id: 0
+                host_perms: 0
+            - #31
+                host_id: 0
+                host_perms: 0
+            - #32
+                host_id: 0
+                host_perms: 0
+    dkek_config:
+        subhdr:
+            magic: 0x5170
+            size: 12
+        allowed_hosts: [128, 0, 0, 0]
+        allow_dkek_export_tisci : 0x5A
+        rsvd: [0, 0, 0]
+    sa2ul_cfg:
+        subhdr:
+            magic: 0x23BE
+            size : 0
+        auth_resource_owner: 0
+        enable_saul_psil_global_config_writes: 0
+        rsvd: [0, 0]
+    sec_dbg_config:
+        subhdr:
+            magic: 0x42AF
+            size: 16
+        allow_jtag_unlock : 0x0
+        allow_wildcard_unlock : 0x0
+        allowed_debug_level_rsvd: 0
+        rsvd: 0
+        min_cert_rev : 0x0
+        jtag_unlock_hosts: [0, 0, 0, 0]
+    sec_handover_cfg:
+        subhdr:
+            magic: 0x608F
+            size: 10
+        handover_msg_sender : 0
+        handover_to_host_id : 0
+        rsvd: [0, 0, 0, 0]
diff --git a/board/ti/keys/custMpk.crt b/board/ti/keys/custMpk.crt
new file mode 100644
index 0000000000..01bd64aae5
--- /dev/null
+++ b/board/ti/keys/custMpk.crt
@@ -0,0 +1,33 @@
+-----BEGIN CERTIFICATE-----
+MIIFwzCCA6sCFHKW0ueol0+vsilVaZyqKhppo9ryMA0GCSqGSIb3DQEBCwUAMIGd
+MQswCQYDVQQGEwJVUzELMAkGA1UECAwCVFgxDzANBgNVBAcMBkRhbGxhczEnMCUG
+A1UECgweVGV4YXMgSW5zdHJ1bWVudHMgSW5jb3Jwb3JhdGVkMRMwEQYDVQQLDApQ
+cm9jZXNzb3JzMRMwEQYDVQQDDApUSSBTdXBwb3J0MR0wGwYJKoZIhvcNAQkBFg5z
+dXBwb3J0QHRpLmNvbTAeFw0yMzA2MDEwNTIxMTZaFw0zMzA1MjkwNTIxMTZaMIGd
+MQswCQYDVQQGEwJVUzELMAkGA1UECAwCVFgxDzANBgNVBAcMBkRhbGxhczEnMCUG
+A1UECgweVGV4YXMgSW5zdHJ1bWVudHMgSW5jb3Jwb3JhdGVkMRMwEQYDVQQLDApQ
+cm9jZXNzb3JzMRMwEQYDVQQDDApUSSBTdXBwb3J0MR0wGwYJKoZIhvcNAQkBFg5z
+dXBwb3J0QHRpLmNvbTCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAL8U
+rknYf3LTayPN60gOZdwiTfIOT4L27bXy3dt8kfpuWf/V97beBB2KzNKV2dHgxMH4
+UL//SAyRIlCaTHuL85YKKCazpNngqVVBGvs+Wydsv8rAca8vciLuRgElYq0+xwT2
+sRi2LMASbg/imz7lpqCoBkUDQRdOFh+pdNaETtZ5pxC4EakOkh8l3X+x8tG58mjY
+M1lLgn13zNGc+iO0+1iI8s3q1RbyLHUt+mLDwQlu4AZw4LUHCZli2dbk52xtyIIH
+UJP34tjt0V/j0J7Pk1TZX91dzjdg8asUigR7Zae6f99FRXxLoVuuTsaUPYxOh9KU
+PKTzn9r88jZ85w2tWkI38SqB0G6hp2cDHoftALtzSmgoMaKCmqMEweiH/0V+qsGf
+1DsFx4P9IXH+vX84yRYZUg7mAzONHR7JNhzNTp2CKYjNmyq+bF97srI6eQBqffWt
+Gp0ezVgqz170ToCrO0/d+NTeNKLEINlZGS2FAl4faLFMjbkRBuktdrVYjFCoN25m
+eG+DMEZNNJ+0GEq5u/p7xa7WMhCEhGw/moAzNfxNvNVuYFRQz35tgJcE+o8LIP29
+mCuhN71Z/UrsRaEJixfJchQztwVeEl3iWh3OIVT24erVVaon600J3xlAgi5miRdl
+2W6z1jhOjWEW1nTU3hZfURnVQriD0sjeS6lpl7aNAgMBAAEwDQYJKoZIhvcNAQEL
+BQADggIBAHy+h1FQKedFTJWgqGJkTwtcym5LyXD6ig8LyhJpVEbXmqK7ZKY2F2hB
+PqVbfCZNogszIvl8q3ykz+tcGbfBk3rq+KMUwbk5E29mSMmAJ9DNNozudgKkKq9w
+RmcO1bXCEspFgNvNEkYAQCBvMOyH/nCyFu9QzOzN35XIzf0fI3jM6rueLxSXq3xO
+7yHUZ3mzAZp6e1Qo6cuABAw1q6KqKYJCnJ3Nq6F42bmGp8mSD+2AuGV8cU+7Z3sh
+k/ooFMCsulj1R5+TlKgEfqspQXbefEsvRW3n3ZD8bcQF0ytiX7XVmDMFVpQkTzps
+92fjZ08Zcj7bCZQsFXXACIQkMiTiiMW6NwLFZDyq11/B1oe1bhjFUuqqUkHC/PKx
+gdWRwluGRt+onFRD5/upXnugKT99j/hQ7sy80a64A1xoCcKVbwcHU7YBQG1vLk6D
+idg0vI3gj7v+/jZEPkv/KrqAI6YuvpplkcHkEKuAUFAkozvVJ5pPK3K0xHBJGNMK
+kJ9FMAakFj6jfZaR5Ay3ZuOAn5oPMwd6RaauNOzVpBll6DFOyw2rU6fbId/gi841
+drmBfM6ufue6ecslkp9zSOpPLXhjt2g9NRVKPE20CmRetVSDLcMFet7ZImbxqggw
+yjDxA7oR+Px+o+xr+djcDlfj6500Rys6W1SNHe99HXOCcpQqivX0
+-----END CERTIFICATE-----
diff --git a/board/ti/keys/custMpk.key b/board/ti/keys/custMpk.key
new file mode 100644
index 0000000000..adba378c80
--- /dev/null
+++ b/board/ti/keys/custMpk.key
@@ -0,0 +1,51 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIJKQIBAAKCAgEAvxSuSdh/ctNrI83rSA5l3CJN8g5PgvbttfLd23yR+m5Z/9X3
+tt4EHYrM0pXZ0eDEwfhQv/9IDJEiUJpMe4vzlgooJrOk2eCpVUEa+z5bJ2y/ysBx
+ry9yIu5GASVirT7HBPaxGLYswBJuD+KbPuWmoKgGRQNBF04WH6l01oRO1nmnELgR
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+Kr5sX3uysjp5AGp99a0anR7NWCrPXvROgKs7T9341N40osQg2VkZLYUCXh9osUyN
+uREG6S12tViMUKg3bmZ4b4MwRk00n7QYSrm7+nvFrtYyEISEbD+agDM1/E281W5g
+VFDPfm2AlwT6jwsg/b2YK6E3vVn9SuxFoQmLF8lyFDO3BV4SXeJaHc4hVPbh6tVV
+qifrTQnfGUCCLmaJF2XZbrPWOE6NYRbWdNTeFl9RGdVCuIPSyN5LqWmXto0CAwEA
+AQKCAgAzkAwcJ0z1GnId/lJQZno8NhGckRoJuEKbR8dwlCP8VUz6Ca5H7Y9kvXDa
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+TuZa48bm4v8VMQvQZOjIZpkIFwao8c6HTwKAnHTB5IN/48I2hCt+Cn3RhfoOZ7Rm
+4gkpaSkt+7GXlhXHb82YfujNO+hbktEamhUYlQ9EK70Wa8aqmf3gHxO0JgsEFjW8
+lJaSnultlTW8SDcx3LMUUjCYumECk4oX/VlJfmKYjPlVjkr3QQ+Cm3nNucb4K4hc
+c+JL+2ERhSj8RjXL7VgbNgdPnIjvQDJuTNqecTU8xWPYrkOLQpNibbLjnutLkhJz
+fMyRtmDtrsey8WiCDuCHkPJ8/f8RjL2zWI9fzTDDIzdlEKouUFGOovaHVnbua6pn
+hymcu9d9FV3p2rcbj0ivCs7e8j+vhSxFJEJoAbcQdXCTi/n2uR7pLtoMNiUzsejy
+d46Uz+KEU920NTwE2z6JJq8I2vegnxjc7PDDrV3/5rK04B93aXiqvwWseCpxelrI
+xaMkRHbXrIXRO6MXQ3N+zNq8Dg3hjGTTvaBKuwgvqLwlXY8+Aa3ooFzEOInIOSsI
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+XBwVB2CrY96qT6Hj9Sq7tGgdskqGkOQkAivBLBizUdcWv0t1yenOsSgasQeMlvlh
+B8md9cLvpKXPB3HM3rTDH/xNXe0TpVKLf7SXC8HfDyIweHwMW3QgO2DWrvI4BV/T
+ckBatRNQ90HxkqGFhC/Mp529lQlyg3ifxPxJsvZOyPMUnrflAvsKQk5c2ZiQg3nZ
+h7I2pjSYgCl+Ib52l8p9bf1kcrVGgPM+auzm496i0RPobFeDBoBvSoznJktHJ7+3
+NnZH+jLiZCODiQPGtQUi+T6eIZUIJF0YASpsCCtUzXCxwW3lYIDNy7UlMivF
+-----END RSA PRIVATE KEY-----
diff --git a/board/ti/keys/custMpk.pem b/board/ti/keys/custMpk.pem
new file mode 100644
index 0000000000..adba378c80
--- /dev/null
+++ b/board/ti/keys/custMpk.pem
@@ -0,0 +1,51 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIJKQIBAAKCAgEAvxSuSdh/ctNrI83rSA5l3CJN8g5PgvbttfLd23yR+m5Z/9X3
+tt4EHYrM0pXZ0eDEwfhQv/9IDJEiUJpMe4vzlgooJrOk2eCpVUEa+z5bJ2y/ysBx
+ry9yIu5GASVirT7HBPaxGLYswBJuD+KbPuWmoKgGRQNBF04WH6l01oRO1nmnELgR
+qQ6SHyXdf7Hy0bnyaNgzWUuCfXfM0Zz6I7T7WIjyzerVFvIsdS36YsPBCW7gBnDg
+tQcJmWLZ1uTnbG3IggdQk/fi2O3RX+PQns+TVNlf3V3ON2DxqxSKBHtlp7p/30VF
+fEuhW65OxpQ9jE6H0pQ8pPOf2vzyNnznDa1aQjfxKoHQbqGnZwMeh+0Au3NKaCgx
+ooKaowTB6If/RX6qwZ/UOwXHg/0hcf69fzjJFhlSDuYDM40dHsk2HM1OnYIpiM2b
+Kr5sX3uysjp5AGp99a0anR7NWCrPXvROgKs7T9341N40osQg2VkZLYUCXh9osUyN
+uREG6S12tViMUKg3bmZ4b4MwRk00n7QYSrm7+nvFrtYyEISEbD+agDM1/E281W5g
+VFDPfm2AlwT6jwsg/b2YK6E3vVn9SuxFoQmLF8lyFDO3BV4SXeJaHc4hVPbh6tVV
+qifrTQnfGUCCLmaJF2XZbrPWOE6NYRbWdNTeFl9RGdVCuIPSyN5LqWmXto0CAwEA
+AQKCAgAzkAwcJ0z1GnId/lJQZno8NhGckRoJuEKbR8dwlCP8VUz6Ca5H7Y9kvXDa
+Hs/hn+rYgP6hYOz7XyrIX2rmJ/T6dxEwqGeC1+o59FConcIRWHpE5zuGT6JYJL5F
+TuZa48bm4v8VMQvQZOjIZpkIFwao8c6HTwKAnHTB5IN/48I2hCt+Cn3RhfoOZ7Rm
+4gkpaSkt+7GXlhXHb82YfujNO+hbktEamhUYlQ9EK70Wa8aqmf3gHxO0JgsEFjW8
+lJaSnultlTW8SDcx3LMUUjCYumECk4oX/VlJfmKYjPlVjkr3QQ+Cm3nNucb4K4hc
+c+JL+2ERhSj8RjXL7VgbNgdPnIjvQDJuTNqecTU8xWPYrkOLQpNibbLjnutLkhJz
+fMyRtmDtrsey8WiCDuCHkPJ8/f8RjL2zWI9fzTDDIzdlEKouUFGOovaHVnbua6pn
+hymcu9d9FV3p2rcbj0ivCs7e8j+vhSxFJEJoAbcQdXCTi/n2uR7pLtoMNiUzsejy
+d46Uz+KEU920NTwE2z6JJq8I2vegnxjc7PDDrV3/5rK04B93aXiqvwWseCpxelrI
+xaMkRHbXrIXRO6MXQ3N+zNq8Dg3hjGTTvaBKuwgvqLwlXY8+Aa3ooFzEOInIOSsI
+XcWqXxt/tgZgsj9RwpC42t8kbA+BkbNk9EIUa+P5kEr2P/fO7QKCAQEA4EtArnOX
+D6tQF8uTw8USOZC2P9s/ez1z4jRq3oKP0Kv4tJiuIObJ/dUvGVD7aM5v2xaCfhm8
+xpk09VPUgghfG5jR5qVvQr75kCNToJQudWi4ngk1HwKJzzTO11giFEdybvTUA+Pj
+fmxCM0dYYqRWZoj0hLqXlUCwxE74BFIhJVjeYbf+nTQrqpllTLoW7MTZHzGx5SXx
+4dNzyVAUH49Yt2D8mgXXCkf5sGLh762wj34b/rR10Kr4O5utGMZrfTRIbuQ1pNjU
+m66baPzq+mC0BzqZEW70TgEb7lOr8rcVXLOi3r36omfd9/MHx7iZD6o3K1axSO15
+grD4ZrN7Ac3QJwKCAQEA2heCoBdpvy6YUk8AO2k8qDygTdmPQRuwjjT+Z2fMslBt
+D7DkpKwZ6Bl9OclcpiiLHmH+hv65KqYg+tR0RRb7PcogB9El9x7yKkGTPZEYWGky
+n8P84rJpKwjnwWQvPQktI1cs3YGvZA9DQTFBavRrwuzgd1oSJq5aPQ2tme0kMvWp
+l1/B/cPK+PKCi/Wfisaze1TjijP9qIeUwkdNN6WLrLU3QgsGppcg2I7RQtAIikT6
+GkuiOQAvWMsrJVV6PNrVKz4fJDJ59Rz6jbDHZNi1MEYNxQoB/Pl7QIakbfjWpHLv
+8Ey7cB2JKxjQy8tmyl8WNQVbXbE6daPXcMTUmaRAKwKCAQBv1lYMJmq+T2eCVen6
+BbvOpE+bi5EdvEiaFBTtmiBnpjg+pJq+oRU60h/H+c9CNR0lGxY6Fk9An4f+g6xE
+ojP6KLsQzJCrsVny+wpp2TlJJcxYULMCIVvhy60PR0zG29E9biqBPhJjKUvhEcQK
+e3LxcXyq6fdHXphFajLUxLbuTl+kTgBRFoBnclFGbsubh5PTsA3J+p+fQLZNPPar
+veg4l82cZykQYU8pGkUaI3sUMYd3+zd7sqRP5JHs9pMGPRmY4YW2CsAIWIn5UZNB
+ARMDP76vKKn8cyUgMuxb+9pU/OVLN2NPs4bEaZQJjAwV+YPEwldny7F47xEM9JVz
+EtKlAoIBAQDUt62u3GdGE/p5/ZgqWoDRTyDEDfmN9aYFbmbdEP80xQE7FrxMaZhz
+K7laja6SWmUm40nQ/c45bQQp4uLtKHcxU15egX7YRBTLZl5o5IasZR79ebnEm2O8
+l9kEZeU1USf3mmWmP4GExOZCRfqaiYA6BbUCdJXTqKdXeWnkAssV8UrS3JFoJHpq
+yo7OWGqefyQ8nRW6jO9SW7uaqtUD+7H6aF5XSk3YWvusfdBZrHNH+fM/hpnZovaL
+Us7ogTDS/laA8PyK37jYfMVdQhmZoU1Iomt3zkUWK3gt/aWPpfAlQf4Jka4YspZB
+tNiijefaZ1hPqsPs5Joyd/YAhdsfaHc1AoIBAQCn/9j6RRjRaw0ip756oad4AXHz
+XBwVB2CrY96qT6Hj9Sq7tGgdskqGkOQkAivBLBizUdcWv0t1yenOsSgasQeMlvlh
+B8md9cLvpKXPB3HM3rTDH/xNXe0TpVKLf7SXC8HfDyIweHwMW3QgO2DWrvI4BV/T
+ckBatRNQ90HxkqGFhC/Mp529lQlyg3ifxPxJsvZOyPMUnrflAvsKQk5c2ZiQg3nZ
+h7I2pjSYgCl+Ib52l8p9bf1kcrVGgPM+auzm496i0RPobFeDBoBvSoznJktHJ7+3
+NnZH+jLiZCODiQPGtQUi+T6eIZUIJF0YASpsCCtUzXCxwW3lYIDNy7UlMivF
+-----END RSA PRIVATE KEY-----
diff --git a/board/ti/keys/ti-degenerate-key.pem b/board/ti/keys/ti-degenerate-key.pem
new file mode 100644
index 0000000000..bd7d3745ad
--- /dev/null
+++ b/board/ti/keys/ti-degenerate-key.pem
@@ -0,0 +1,10 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIBWwIBAAKBgQDRfrnXQaP0k6vRK/gZ+bDflSU6y1JagGeQ/b+QYuiDz14japog
+8fRSu5WBsAxaSaySAUwS3L9Ppw+hGMecmyIJ494aMfZTtk1g49gU58joduiRnu7e
+QSZHMnehhuNlfD7A2tAAKnxIYuabs8zHYM/SS9Ne7t3kIQMbKfUSzNy6qQIBAQIB
+AQJBAOelUA376o6w3HkShXfN+shaOZYqFuTJ9exLMwsLp7DZKXB5F9I4JJ+Vkvho
+k6QWs7vkhleLSYUZknXHYm26ZE0CQQDnhTtd4PTBoZPjPXOeYMJFtEdMNy0XP6ey
+bcce389ugoY7BEkvASrd8PHgJQHziepgWOG4DGp33c64Hfq4zI3NAgEBAgEBAkA0
+RbK4uqoLciQluesTPU6lBy7Se3Dw0F9xBqlF5SR4KI6q+zQrHpBKyFOofMHZgizR
+iCrL55cxEM146zMw3AnF
+-----END RSA PRIVATE KEY-----
diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig
index 9477f5336b..8b3a43a5aa 100644
--- a/board/ti/ks2_evm/Kconfig
+++ b/board/ti/ks2_evm/Kconfig
@@ -9,6 +9,9 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "k2e_evm"
 
+config ENV_SOURCE_FILE
+       default "k2e_evm"
+
 endif
 
 if TARGET_K2HK_EVM
@@ -22,6 +25,9 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "k2hk_evm"
 
+config ENV_SOURCE_FILE
+       default "k2hk_evm"
+
 endif
 
 if TARGET_K2L_EVM
@@ -35,6 +41,9 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "k2l_evm"
 
+config ENV_SOURCE_FILE
+       default "k2l_evm"
+
 endif
 
 if TARGET_K2G_EVM
@@ -48,6 +57,9 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "k2g_evm"
 
+config ENV_SOURCE_FILE
+       default "k2g_evm"
+
 endif
 
 source "board/ti/common/Kconfig"
diff --git a/board/ti/ks2_evm/MAINTAINERS b/board/ti/ks2_evm/MAINTAINERS
index 999ef0ae39..637feec8d1 100644
--- a/board/ti/ks2_evm/MAINTAINERS
+++ b/board/ti/ks2_evm/MAINTAINERS
@@ -1,12 +1,9 @@
-KS2_EVM BOARD
-M:	Vitaly Andrianov <vitalya@ti.com>
+KeyStone II EVM Boards
+M:	Andrew Davis <afd@ti.com>
 S:	Maintained
+F:	arch/arm/mach-keystone/
 F:	board/ti/ks2_evm/
-F:	include/configs/k2hk_evm.h
-F:	configs/k2hk_evm_defconfig
-F:	include/configs/k2e_evm.h
-F:	configs/k2e_evm_defconfig
-F:	include/configs/k2l_evm.h
-F:	configs/k2l_evm_defconfig
-F:	include/configs/k2g_evm.h
-F:	configs/k2g_evm_defconfig
+N:	k2hk
+N:	k2e
+N:	k2l
+N:	k2g
diff --git a/board/ti/ks2_evm/k2e_evm.env b/board/ti/ks2_evm/k2e_evm.env
new file mode 100644
index 0000000000..a145db53e5
--- /dev/null
+++ b/board/ti/ks2_evm/k2e_evm.env
@@ -0,0 +1,12 @@
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_armv7_keystone2.env>
+
+findfdt=setenv fdtfile ${name_fdt}
+boot=ubi
+args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048
+
+name_fdt=keystone-k2e-evm.dtb
+name_mon=skern-k2e.bin
+name_ubi=k2e-evm-ubifs.ubi
+name_uboot=u-boot-spi-k2e-evm.gph
+name_fs=arago-console-image-k2e-evm.cpio.gz
diff --git a/board/ti/ks2_evm/k2g_evm.env b/board/ti/ks2_evm/k2g_evm.env
new file mode 100644
index 0000000000..4f4941dd09
--- /dev/null
+++ b/board/ti/ks2_evm/k2g_evm.env
@@ -0,0 +1,45 @@
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_armv7_keystone2.env>
+#include <env/ti/mmc.env>
+
+set_name_pmmc=setenv name_pmmc ti-sci-firmware-k2g.bin
+dev_pmmc=0
+get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}
+get_pmmc_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_pmmc}
+get_pmmc_ramfs=run get_pmmc_net
+get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} ${bootdir}/${name_pmmc}
+get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}
+run_pmmc=rproc init;
+	rproc list;
+	rproc load ${dev_pmmc} ${loadaddr} 0x${filesize};
+	rproc start ${dev_pmmc}
+
+boot=mmc
+console=ttyS0,115200n8
+bootpart=0:2
+bootdir=/boot
+rd_spec=-
+args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048
+
+findfdt=
+	if test $board_name = 66AK2GGP; then
+		setenv name_fdt keystone-k2g-evm.dtb; fi;
+	if test $board_name = 66AK2GG1; then
+		setenv name_fdt keystone-k2g-evm.dtb; fi;
+	if test $board_name = 66AK2GIC; then
+		setenv name_fdt keystone-k2g-ice.dtb; fi;
+	if test $board_name = 66AK2GI1; then
+		setenv name_fdt keystone-k2g-ice.dtb; fi;
+	if test $name_fdt = undefined; then
+		echo WARNING: Could not determine device tree to use; fi;
+	setenv fdtfile ${name_fdt}
+
+name_mon=skern-k2g.bin
+name_ubi=k2g-evm-ubifs.ubi
+name_uboot=u-boot-spi-k2g-evm.gph
+init_mmc=run args_all args_mmc
+init_fw_rd_mmc=load mmc ${bootpart} ${rdaddr} ${bootdir}/${name_fw_rd}; run set_rd_spec
+get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
+get_kern_mmc=load mmc ${bootpart} ${loadaddr} ${bootdir}/${name_kern}
+get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}
+name_fs=arago-base-tisdk-image-k2g-evm.cpio
diff --git a/board/ti/ks2_evm/k2hk_evm.env b/board/ti/ks2_evm/k2hk_evm.env
new file mode 100644
index 0000000000..0714a51090
--- /dev/null
+++ b/board/ti/ks2_evm/k2hk_evm.env
@@ -0,0 +1,12 @@
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_armv7_keystone2.env>
+
+findfdt=setenv fdtfile ${name_fdt}
+boot=ubi
+args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048
+
+name_fdt=keystone-k2hk-evm.dtb
+name_mon=skern-k2hk.bin
+name_ubi=k2hk-evm-ubifs.ubi
+name_uboot=u-boot-spi-k2hk-evm.gph
+name_fs=arago-console-image-k2hk-evm.cpio.gz
diff --git a/board/ti/ks2_evm/k2l_evm.env b/board/ti/ks2_evm/k2l_evm.env
new file mode 100644
index 0000000000..e8a803a4ed
--- /dev/null
+++ b/board/ti/ks2_evm/k2l_evm.env
@@ -0,0 +1,12 @@
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_armv7_keystone2.env>
+
+findfdt=setenv fdtfile ${name_fdt}
+boot=ubi
+args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096
+
+name_fdt=keystone-k2l-evm.dtb
+name_mon=skern-k2l.bin
+name_ubi=k2l-evm-ubifs.ubi
+name_uboot=u-boot-spi-k2l-evm.gph
+name_fs=arago-console-image-k2l-evm.cpio.gz\0"
diff --git a/board/ti/ti816x/Kconfig b/board/ti/ti816x/Kconfig
deleted file mode 100644
index 95973b47f1..0000000000
--- a/board/ti/ti816x/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_TI816X_EVM
-
-config SYS_BOARD
-	default "ti816x"
-
-config SYS_VENDOR
-	default "ti"
-
-config SYS_SOC
-	default "am33xx"
-
-config SYS_CONFIG_NAME
-	default "ti816x_evm"
-
-endif
diff --git a/board/ti/ti816x/MAINTAINERS b/board/ti/ti816x/MAINTAINERS
deleted file mode 100644
index fd9a98fc76..0000000000
--- a/board/ti/ti816x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TI816X BOARD
-M:	Tom Rini <trini@konsulko.com>
-S:	Maintained
-F:	board/ti/ti816x/
-F:	include/configs/ti816x_evm.h
-F:	configs/ti816x_evm_defconfig
diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile
deleted file mode 100644
index f12712aea6..0000000000
--- a/board/ti/ti816x/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
-# Antoine Tenart, <atenart@adeneo-embedded.com>
-#
-# Based on TI-PSP-04.00.02.14 :
-#
-# Copyright (C) 2009, Texas Instruments, Incorporated
-
-obj-y	:= evm.o
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
deleted file mode 100644
index 8c708355d4..0000000000
--- a/board/ti/ti816x/evm.c
+++ /dev/null
@@ -1,140 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * evm.c
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- */
-
-#include <common.h>
-#include <env.h>
-#include <init.h>
-#include <net.h>
-#include <spl.h>
-#include <asm/cache.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
-#if defined(CONFIG_MTD_RAW_NAND)
-	gpmc_init();
-#endif
-	return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	uint8_t mac_addr[6];
-	uint32_t mac_hi, mac_lo;
-	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
-		printf("<ethaddr> not set. Reading from E-fuse\n");
-		/* try reading mac address from efuse */
-		mac_lo = readl(&cdev->macid0l);
-		mac_hi = readl(&cdev->macid0h);
-		mac_addr[0] = mac_hi & 0xFF;
-		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-		mac_addr[4] = mac_lo & 0xFF;
-		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-		if (is_valid_ethaddr(mac_addr))
-			eth_env_set_enetaddr("ethaddr", mac_addr);
-		else
-			printf("Unable to read MAC address. Set <ethaddr>\n");
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-static struct module_pin_mux mmc_pin_mux[] = {
-	{ OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
-	{ OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
-	{ OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
-	{ OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
-	{ OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
-	{ OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
-	{ OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
-	{ -1 },
-};
-
-void set_uart_mux_conf(void) {}
-
-void set_mux_conf_regs(void)
-{
-	configure_module_pin_mux(mmc_pin_mux);
-}
-
-/*
- * EMIF Paramters.  Refer the EMIF register documentation and the
- * memory datasheet for details.  This is for 796 MHz.
- */
-#define EMIF_TIM1   0x1779C9FE
-#define EMIF_TIM2   0x50608074
-#define EMIF_TIM3   0x009F857F
-#define EMIF_SDREF  0x10001841
-#define EMIF_SDCFG  0x62A73832
-#define EMIF_PHYCFG 0x00000110
-static const struct emif_regs ddr3_emif_regs = {
-	.sdram_config		= EMIF_SDCFG,
-	.ref_ctrl		= EMIF_SDREF,
-	.sdram_tim1		= EMIF_TIM1,
-	.sdram_tim2		= EMIF_TIM2,
-	.sdram_tim3		= EMIF_TIM3,
-	.emif_ddr_phy_ctlr_1	= EMIF_PHYCFG,
-};
-
-static const struct cmd_control ddr3_ctrl = {
-	.cmd0csratio	= 0x100,
-	.cmd0iclkout	= 0x001,
-	.cmd1csratio	= 0x100,
-	.cmd1iclkout	= 0x001,
-	.cmd2csratio	= 0x100,
-	.cmd2iclkout	= 0x001,
-};
-
-/* These values are obtained from the CCS app */
-#define RD_DQS_GATE	(0x1B3)
-#define RD_DQS		(0x35)
-#define WR_DQS		(0x93)
-static struct ddr_data ddr3_data = {
-	.datardsratio0		= ((RD_DQS<<10) | (RD_DQS<<0)),
-	.datawdsratio0		= ((WR_DQS<<10) | (WR_DQS<<0)),
-	.datawiratio0		= ((0x20<<10) | 0x20<<0),
-	.datagiratio0		= ((0x20<<10) | 0x20<<0),
-	.datafwsratio0		= ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
-	.datawrsratio0		= (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
-};
-
-static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
-	.dmm_lisa_map_0 = 0x00000000,
-	.dmm_lisa_map_1 = 0x00000000,
-	.dmm_lisa_map_2 = 0x80640300,
-	.dmm_lisa_map_3 = 0xC0640320,
-};
-
-void sdram_init(void)
-{
-	/*
-	 * Pass in our DDR3 config information and that we have 2 EMIFs to
-	 * configure.
-	 */
-	config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
-			&evm_lisa_map_regs, 2);
-}
-#endif /* CONFIG_SPL_BUILD */
diff --git a/board/toradex/apalis-imx8/MAINTAINERS b/board/toradex/apalis-imx8/MAINTAINERS
index 03b0fda0e1..198399c879 100644
--- a/board/toradex/apalis-imx8/MAINTAINERS
+++ b/board/toradex/apalis-imx8/MAINTAINERS
@@ -5,6 +5,7 @@ S:	Maintained
 F:	arch/arm/dts/fsl-imx8qm-apalis.dts
 F:	arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
 F:	board/toradex/apalis-imx8/
+F:	board/toradex/common/
 F:	configs/apalis-imx8_defconfig
 F:	doc/board/toradex/apalis-imx8.rst
 F:	include/configs/apalis-imx8.h
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c
index aa76c486ee..e2bbaba8b8 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -85,18 +85,18 @@ static void setup_iomux_uart(void)
 
 static uint32_t do_get_tdx_user_fuse(int a, int b)
 {
-	sc_err_t sciErr;
+	int sciErr;
 	u32 val_a = 0;
 	u32 val_b = 0;
 
 	sciErr = sc_misc_otp_fuse_read(-1, a, &val_a);
-	if (sciErr != SC_ERR_NONE) {
+	if (sciErr) {
 		printf("Error reading out user fuse %d\n", a);
 		return 0;
 	}
 
 	sciErr = sc_misc_otp_fuse_read(-1, b, &val_b);
-	if (sciErr != SC_ERR_NONE) {
+	if (sciErr) {
 		printf("Error reading out user fuse %d\n", b);
 		return 0;
 	}
@@ -131,9 +131,9 @@ void board_mem_get_layout(u64 *phys_sdram_1_start,
 {
 	u32 is_quadplus = 0, val = 0;
 	struct tdx_user_fuses tdxramfuses;
-	sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+	int scierr = sc_misc_otp_fuse_read(-1, 6, &val);
 
-	if (scierr == SC_ERR_NONE) {
+	if (scierr) {
 		/* QP has one A72 core disabled */
 		is_quadplus = ((val >> 4) & 0x3) != 0x0;
 	}
diff --git a/board/toradex/apalis-tk1/MAINTAINERS b/board/toradex/apalis-tk1/MAINTAINERS
index 3c908e1192..e2c6f63dcc 100644
--- a/board/toradex/apalis-tk1/MAINTAINERS
+++ b/board/toradex/apalis-tk1/MAINTAINERS
@@ -2,6 +2,7 @@ Apalis TK1
 M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
 S:	Maintained
 F:	board/toradex/apalis-tk1/
+F:	board/toradex/common/
 F:	include/configs/apalis-tk1.h
 F:	configs/apalis-tk1_defconfig
 F:	arch/arm/dts/tegra124-apalis.dtb
diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS
index 9c36ae19a8..0b2907bbe7 100644
--- a/board/toradex/apalis_imx6/MAINTAINERS
+++ b/board/toradex/apalis_imx6/MAINTAINERS
@@ -7,5 +7,6 @@ F:	arch/arm/dts/imx6q-apalis-eval.dts
 F:	arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi
 F:	arch/arm/dts/imx6qdl-apalis.dtsi
 F:	board/toradex/apalis_imx6/
+F:	board/toradex/common/
 F:	configs/apalis_imx6_defconfig
 F:	include/configs/apalis_imx6.h
diff --git a/board/toradex/apalis_t30/MAINTAINERS b/board/toradex/apalis_t30/MAINTAINERS
index 01bc73e46d..097db7deb0 100644
--- a/board/toradex/apalis_t30/MAINTAINERS
+++ b/board/toradex/apalis_t30/MAINTAINERS
@@ -2,6 +2,7 @@ Apalis T30
 M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
 S:	Maintained
 F:	board/toradex/apalis_t30/
+F:	board/toradex/common/
 F:	include/configs/apalis_t30.h
 F:	configs/apalis_t30_defconfig
 F:	arch/arm/dts/tegra30-apalis.dtb
diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS
index 37c485aa6b..ee6fe6c13e 100644
--- a/board/toradex/colibri-imx6ull/MAINTAINERS
+++ b/board/toradex/colibri-imx6ull/MAINTAINERS
@@ -11,6 +11,7 @@ F:	arch/arm/dts/imx6ull-colibri-eval-v3.dtsi
 F:	arch/arm/dts/imx6ull-colibri-nonwifi.dtsi
 F:	arch/arm/dts/imx6ull-colibri-u-boot.dtsi
 F:	board/toradex/colibri-imx6ull/
+F:	board/toradex/common/
 F:	configs/colibri-imx6ull_defconfig
 F:	configs/colibri-imx6ull-emmc_defconfig
 F:	include/configs/colibri-imx6ull.h
diff --git a/board/toradex/colibri-imx8x/MAINTAINERS b/board/toradex/colibri-imx8x/MAINTAINERS
index de62f87a56..8c9bf1f63f 100644
--- a/board/toradex/colibri-imx8x/MAINTAINERS
+++ b/board/toradex/colibri-imx8x/MAINTAINERS
@@ -5,6 +5,7 @@ S:	Maintained
 F:	arch/arm/dts/fsl-imx8x-colibri.dts
 F:	arch/arm/dts/fsl-imx8x-colibri-u-boot.dtsi
 F:	board/toradex/colibri-imx8x/
+F:	board/toradex/common/
 F:	configs/colibri-imx8x_defconfig
 F:	doc/board/toradex/colibri-imx8x.rst
 F:	include/configs/colibri-imx8x.h
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c
index 52fc7a391b..6c0b09787c 100644
--- a/board/toradex/colibri-imx8x/colibri-imx8x.c
+++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -12,6 +12,7 @@
 #include <asm/arch/imx8-pins.h>
 #include <asm/arch/iomux.h>
 #include <firmware/imx/sci/sci.h>
+#include <asm/arch/snvs_security_sc.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -43,9 +44,9 @@ static void setup_iomux_uart(void)
 static int is_imx8dx(void)
 {
 	u32 val = 0;
-	sc_err_t sc_err = sc_misc_otp_fuse_read(-1, 6, &val);
+	int sc_err = sc_misc_otp_fuse_read(-1, 6, &val);
 
-	if (sc_err == SC_ERR_NONE) {
+	if (sc_err) {
 		/* DX has two A35 cores disabled */
 		return (val & 0xf) != 0x0;
 	}
@@ -70,7 +71,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start,
 int board_early_init_f(void)
 {
 	sc_pm_clock_rate_t rate;
-	sc_err_t err = 0;
+	int err;
 
 	/*
 	 * This works around that having only UART3 up the baudrate is 1.2M
@@ -78,13 +79,13 @@ int board_early_init_f(void)
 	 */
 	rate = 80000000;
 	err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
-	if (err != SC_ERR_NONE)
+	if (err)
 		return 0;
 
 	/* Set UART3 clock root to 80 MHz and enable it */
 	rate = SC_80MHZ;
 	err = sc_pm_setup_uart(SC_R_UART_3, rate);
-	if (err != SC_ERR_NONE)
+	if (err)
 		return 0;
 
 	setup_iomux_uart();
@@ -139,6 +140,13 @@ int board_init(void)
 {
 	board_gpio_init();
 
+	if (IS_ENABLED(CONFIG_IMX_SNVS_SEC_SC_AUTO)) {
+		int ret = snvs_security_sc_init();
+
+		if (ret)
+			return ret;
+	}
+
 	return 0;
 }
 
@@ -170,6 +178,8 @@ int board_late_init(void)
 	env_set("board_rev", "v1.0");
 #endif
 
+	build_info();
+
 	select_dt_from_module_version();
 
 	return 0;
diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS
index f7a5ad59f8..25d3a06a85 100644
--- a/board/toradex/colibri_imx6/MAINTAINERS
+++ b/board/toradex/colibri_imx6/MAINTAINERS
@@ -4,6 +4,7 @@ W:	http://developer.toradex.com/software/linux/linux-software
 W:      https://www.toradex.com/community
 S:	Maintained
 F:	board/toradex/colibri_imx6/
+F:	board/toradex/common/
 F:	include/configs/colibri_imx6.h
 F:	configs/colibri_imx6_defconfig
 F:	arch/arm/dts/imx6dl-colibri-eval-v3.dts
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 65e0e9a156..677caa4a4e 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -767,8 +767,7 @@ MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 /*
  * MDMISC	mirroring	interleaved (row/bank/col)
  */
-/* TODO: check what the RALAT field does */
-MX6_MMDC_P0_MDMISC, 0x00081740,
+MX6_MMDC_P0_MDMISC, 0x000b17c0,
 
 /*
  * MDSCR	con_req
@@ -900,8 +899,7 @@ MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 /*
  * MDMISC	mirroring	interleaved (row/bank/col)
  */
-/* TODO: check what the RALAT field does */
-MX6_MMDC_P0_MDMISC, 0x00081740,
+MX6_MMDC_P0_MDMISC, 0x000b17c0,
 
 /*
  * MDSCR	con_req
diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS
index 513679a41c..e4583d5a86 100644
--- a/board/toradex/colibri_imx7/MAINTAINERS
+++ b/board/toradex/colibri_imx7/MAINTAINERS
@@ -10,6 +10,7 @@ F:	arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
 F:	arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts
 F:	arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
 F:	board/toradex/colibri_imx7/
+F:	board/toradex/common/
 F:	configs/colibri_imx7_defconfig
 F:	configs/colibri_imx7_emmc_defconfig
 F:	doc/board/toradex/colibri_imx7.rst
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index 3e79ab93a9..119e67b47f 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -311,10 +311,23 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 #ifdef CONFIG_USB_EHCI_MX7
 int board_fix_fdt(void *rw_fdt_blob)
 {
+	int ret;
+
 	/* i.MX 7Solo has only one single USB OTG1 but no USB host port */
 	if (is_cpu_type(MXC_CPU_MX7S)) {
 		int offset = fdt_path_offset(rw_fdt_blob, "/soc/bus@30800000/usb@30b20000");
 
+		/*
+		 * We're changing from status = "okay" to status = "disabled".
+		 * In this case we'll need more space, so increase the size
+		 * a little bit.
+		 */
+		ret = fdt_increase_size(rw_fdt_blob, 32);
+		if (ret < 0) {
+			printf("Cannot increase FDT size: %d\n", ret);
+			return ret;
+		}
+
 		return fdt_status_disabled(rw_fdt_blob, offset);
 	}
 
diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS
index 77c2fc39e6..d0c5b11333 100644
--- a/board/toradex/colibri_t20/MAINTAINERS
+++ b/board/toradex/colibri_t20/MAINTAINERS
@@ -2,6 +2,7 @@ COLIBRI_T20
 M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
 S:	Maintained
 F:	board/toradex/colibri_t20/
+F:	board/toradex/common/
 F:	include/configs/colibri_t20.h
 F:	configs/colibri_t20_defconfig
 F:	arch/arm/dts/tegra20-colibri.dtb
diff --git a/board/toradex/colibri_t30/MAINTAINERS b/board/toradex/colibri_t30/MAINTAINERS
index c2d6587ed0..006a0e55f1 100644
--- a/board/toradex/colibri_t30/MAINTAINERS
+++ b/board/toradex/colibri_t30/MAINTAINERS
@@ -2,6 +2,7 @@ Colibri T30
 M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
 S:	Maintained
 F:	board/toradex/colibri_t30/
+F:	board/toradex/common/
 F:	include/configs/colibri_t30.h
 F:	configs/colibri_t30_defconfig
 F:	arch/arm/dts/tegra30-colibri.dtb
diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS
index f821a3334b..2e1a74c2db 100644
--- a/board/toradex/colibri_vf/MAINTAINERS
+++ b/board/toradex/colibri_vf/MAINTAINERS
@@ -8,5 +8,6 @@ F:	arch/arm/dts/vf-colibri-eval-v3.dtsi
 F:	arch/arm/dts/vf610-colibri-eval-v3-u-boot.dtsi
 F:	arch/arm/dts/vf610-colibri.dts
 F:	board/toradex/colibri_vf/
+F:	board/toradex/common/
 F:	configs/colibri_vf_defconfig
 F:	include/configs/colibri_vf.h
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index 11f4d5e14a..7187e1ba37 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -139,18 +139,34 @@ const struct toradex_som toradex_modules[] = {
 	[66] = { "Verdin iMX8M Plus Quad 8GB WB",        TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
 	[67] = { "Apalis iMX8QM 8GB WB IT",              TARGET_IS_ENABLED(APALIS_IMX8)     },
 	[68] = { "Verdin iMX8M Mini Quad 2GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
+	[69] = { "Verdin AM62 Quad 1GB WB IT",           TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	[70] = { "Verdin iMX8M Plus Quad 8GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
+	[71] = { "Verdin AM62 Solo 512MB",               TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	[72] = { "Verdin AM62 Solo 512MB WB IT",         TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	[73] = { "Verdin AM62 Dual 1GB ET",              TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	[74] = { "Verdin AM62 Dual 1GB IT",              TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	[75] = { "Verdin AM62 Dual 1GB WB IT",           TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	[76] = { "Verdin AM62 Quad 2GB WB IT",           TARGET_IS_ENABLED(VERDIN_AM62_A53) },
 };
 
-const char * const toradex_carrier_boards[] = {
-	[0] = "UNKNOWN CARRIER BOARD",
-	[155] = "Dahlia",
-	[156] = "Verdin Development Board",
+struct pid4list {
+	int pid4;
+	char * const name;
 };
 
-const char * const toradex_display_adapters[] = {
-	[0] = "UNKNOWN DISPLAY ADAPTER",
-	[157] = "Verdin DSI to HDMI Adapter",
-	[159] = "Verdin DSI to LVDS Adapter",
+const struct pid4list toradex_carrier_boards[] = {
+	/* the code assumes unknown at index 0 */
+	{0,				"UNKNOWN CARRIER BOARD"},
+	{DAHLIA,			"Dahlia"},
+	{VERDIN_DEVELOPMENT_BOARD,	"Verdin Development Board"},
+	{YAVIA,				"Yavia"},
+};
+
+const struct pid4list toradex_display_adapters[] = {
+	/* the code assumes unknown at index 0 */
+	{0,				"UNKNOWN DISPLAY ADAPTER"},
+	{VERDIN_DSI_TO_HDMI_ADAPTER,	"Verdin DSI to HDMI Adapter"},
+	{VERDIN_DSI_TO_LVDS_ADAPTER,	"Verdin DSI to LVDS Adapter"},
 };
 
 const u32 toradex_ouis[] = {
@@ -158,6 +174,32 @@ const u32 toradex_ouis[] = {
 	[1] = 0x8c06cbUL,
 };
 
+const char * const get_toradex_carrier_boards(int pid4)
+{
+	int i, index = 0;
+
+	for (i = 1; i < ARRAY_SIZE(toradex_carrier_boards); i++) {
+		if (pid4 == toradex_carrier_boards[i].pid4) {
+			index = i;
+			break;
+		}
+	}
+	return toradex_carrier_boards[index].name;
+}
+
+const char * const get_toradex_display_adapters(int pid4)
+{
+	int i, index = 0;
+
+	for (i = 1; i < ARRAY_SIZE(toradex_display_adapters); i++) {
+		if (pid4 == toradex_display_adapters[i].pid4) {
+			index = i;
+			break;
+		}
+	}
+	return toradex_display_adapters[index].name;
+}
+
 static u32 get_serial_from_mac(struct toradex_eth_addr *eth_addr)
 {
 	int i;
@@ -637,10 +679,11 @@ static int get_cfgblock_carrier_interactive(void)
 	int ret = 0;
 
 	printf("Supported carrier boards:\n");
-	printf("CARRIER BOARD NAME\t\t [ID]\n");
+	printf("%30s\t[ID]\n", "CARRIER BOARD NAME");
 	for (int i = 0; i < ARRAY_SIZE(toradex_carrier_boards); i++)
-		if (toradex_carrier_boards[i])
-			printf("%s \t\t [%d]\n", toradex_carrier_boards[i], i);
+		printf("%30s\t[%d]\n",
+		       toradex_carrier_boards[i].name,
+		       toradex_carrier_boards[i].pid4);
 
 	sprintf(message, "Choose your carrier board (provide ID): ");
 	len = cli_readline(message);
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index 32e4c6f687..ea58bd43b1 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -94,11 +94,20 @@ enum {
 	VERDIN_IMX8MPQ_8GB_WIFI_BT,
 	APALIS_IMX8QM_8GB_WIFI_BT_IT,
 	VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN,
+	VERDIN_AM62Q_WIFI_BT_IT,
+	VERDIN_IMX8MPQ_8GB_WIFI_BT_IT, /* 70 */
+	VERDIN_AM62S_512MB,
+	VERDIN_AM62S_512MB_WIFI_BT_IT,
+	VERDIN_AM62D_1G_ET,
+	VERDIN_AM62D_1G_IT,
+	VERDIN_AM62D_1G_WIFI_BT_IT, /* 75 */
+	VERDIN_AM62Q_2G_WIFI_BT_IT,
 };
 
 enum {
 	DAHLIA = 155,
 	VERDIN_DEVELOPMENT_BOARD = 156,
+	YAVIA = 173,
 };
 
 enum {
@@ -107,7 +116,6 @@ enum {
 };
 
 extern const struct toradex_som toradex_modules[];
-extern const char * const toradex_carrier_boards[];
 extern bool valid_cfgblock;
 extern struct toradex_hw tdx_hw_tag;
 extern struct toradex_hw tdx_car_hw_tag;
@@ -117,7 +125,8 @@ extern u32 tdx_car_serial;
 
 int read_tdx_cfg_block(void);
 int read_tdx_cfg_block_carrier(void);
-
+const char * const get_toradex_carrier_boards(int pid4);
+const char * const get_toradex_display_adapters(int pid4);
 int try_migrate_tdx_cfg_block_carrier(void);
 
 void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr);
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
index 071961f3d9..d144914397 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -31,7 +31,7 @@ static char tdx_board_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1];
 #ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
 static char tdx_car_serial_str[SERIAL_STR_LEN + 1];
 static char tdx_car_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1];
-static char *tdx_carrier_board_name;
+static const char *tdx_carrier_board_name;
 #endif
 
 #if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
@@ -125,8 +125,8 @@ int show_board_info(void)
 			printf("MISSING TORADEX CARRIER CONFIG BLOCKS\n");
 			try_migrate_tdx_cfg_block_carrier();
 		} else {
-			tdx_carrier_board_name = (char *)
-				toradex_carrier_boards[tdx_car_hw_tag.prodid];
+			tdx_carrier_board_name =
+				get_toradex_carrier_boards(tdx_car_hw_tag.prodid);
 
 			snprintf(tdx_car_serial_str, sizeof(tdx_car_serial_str),
 				 "%08u", tdx_car_serial);
diff --git a/board/toradex/verdin-am62/Kconfig b/board/toradex/verdin-am62/Kconfig
new file mode 100644
index 0000000000..e752224407
--- /dev/null
+++ b/board/toradex/verdin-am62/Kconfig
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright 2023 Toradex
+#
+
+choice
+	prompt "Toradex Verdin AM62 based boards"
+	optional
+
+config TARGET_VERDIN_AM62_A53
+	bool "Toradex Verdin AM62 running on A53"
+	select ARM64
+	select BINMAN
+
+config TARGET_VERDIN_AM62_R5
+	bool "Toradex Verdin AM62 running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select K3_LOAD_SYSFW
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	select BINMAN
+	imply SYS_K3_SPL_ATF
+
+endchoice
+
+if TARGET_VERDIN_AM62_A53
+
+config SYS_BOARD
+	default "verdin-am62"
+
+config SYS_CONFIG_NAME
+	default "verdin-am62"
+
+config SYS_VENDOR
+	default "toradex"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_EXTRA
+	default y
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+config TDX_HAVE_EEPROM_EXTRA
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+source "board/toradex/common/Kconfig"
+
+endif
+
+if TARGET_VERDIN_AM62_R5
+
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+config SYS_BOARD
+	default "verdin-am62"
+
+config SYS_CONFIG_NAME
+	default "verdin-am62"
+
+config SYS_VENDOR
+	default "toradex"
+
+endif
diff --git a/board/toradex/verdin-am62/MAINTAINERS b/board/toradex/verdin-am62/MAINTAINERS
new file mode 100644
index 0000000000..4e75980dbd
--- /dev/null
+++ b/board/toradex/verdin-am62/MAINTAINERS
@@ -0,0 +1,17 @@
+Verdin AM62
+F:	arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
+F:	arch/arm/dts/k3-am625-verdin-r5.dts
+F:	arch/arm/dts/k3-am625-verdin-wifi-dev.dts
+F:	arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
+F:	arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
+F:	arch/arm/dts/k3-am62-verdin-dev.dtsi
+F:	arch/arm/dts/k3-am62-verdin.dtsi
+F:	arch/arm/dts/k3-am62-verdin-wifi.dtsi
+F:	board/toradex/verdin-am62/
+F:	configs/verdin-am62_a53_defconfig
+F:	configs/verdin-am62_r5_defconfig
+F:	doc/board/toradex/verdin-am62.rst
+F:	include/configs/verdin-am62.h
+M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
+S:	Maintained
+W:	https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am-62
diff --git a/board/toradex/verdin-am62/Makefile b/board/toradex/verdin-am62/Makefile
new file mode 100644
index 0000000000..af1a5508ed
--- /dev/null
+++ b/board/toradex/verdin-am62/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright 2023 Toradex
+#
+
+obj-y += verdin-am62.o
diff --git a/board/toradex/verdin-am62/board-cfg.yaml b/board/toradex/verdin-am62/board-cfg.yaml
new file mode 100644
index 0000000000..36cfb550ad
--- /dev/null
+++ b/board/toradex/verdin-am62/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62
+#
+
+---
+
+board-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
+    control:
+        subhdr:
+            magic: 0xC1D3
+            size: 7
+        main_isolation_enable : 0x5A
+        main_isolation_hostid : 0x2
+    secproxy:
+        subhdr:
+            magic: 0x1207
+            size: 7
+        scaling_factor : 0x1
+        scaling_profile : 0x1
+        disable_main_nav_secure_proxy : 0
+    msmc:
+        subhdr:
+            magic: 0xA5C3
+            size: 5
+        msmc_cache_size : 0x0
+    debug_cfg:
+        subhdr:
+            magic: 0x020C
+            size: 8
+        trace_dst_enables : 0x00
+        trace_src_enables : 0x00
diff --git a/board/toradex/verdin-am62/pm-cfg.yaml b/board/toradex/verdin-am62/pm-cfg.yaml
new file mode 100644
index 0000000000..5d04cf82ef
--- /dev/null
+++ b/board/toradex/verdin-am62/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62
+#
+
+---
+
+pm-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
diff --git a/board/toradex/verdin-am62/rm-cfg.yaml b/board/toradex/verdin-am62/rm-cfg.yaml
new file mode 100644
index 0000000000..c28707be8e
--- /dev/null
+++ b/board/toradex/verdin-am62/rm-cfg.yaml
@@ -0,0 +1,1088 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62
+#
+
+---
+
+rm-cfg:
+    rm_boardcfg:
+        rev:
+            boardcfg_abi_maj : 0x0
+            boardcfg_abi_min : 0x1
+        host_cfg:
+            subhdr:
+                magic: 0x4C41
+                size : 356
+            host_cfg_entries:
+                - #1
+                    host_id: 12
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #2
+                    host_id: 30
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #3
+                    host_id: 36
+                    allowed_atype : 0x2A
+                    allowed_qos : 0xAAAA
+                    allowed_orderid : 0xAAAAAAAA
+                    allowed_priority : 0xAAAA
+                    allowed_sched_priority : 0xAA
+                - #4
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #5
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #6
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #7
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #8
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #9
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #10
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #11
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #12
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #13
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #14
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #15
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #16
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #17
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #18
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #19
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #20
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #21
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #22
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #23
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #24
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #25
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #26
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #27
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #28
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #29
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #30
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #31
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+                - #32
+                    host_id: 0
+                    allowed_atype : 0
+                    allowed_qos : 0
+                    allowed_orderid : 0
+                    allowed_priority : 0
+                    allowed_sched_priority : 0
+        resasg:
+            subhdr:
+                magic: 0x7B25
+                size : 8
+            resasg_entries_size: 960
+            reserved : 0
+    resasg_entries:
+        -
+                start_resource: 0
+                num_resource: 16
+                type: 64
+                host_id: 12
+                reserved: 0
+
+        -
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+                host_id: 35
+                reserved: 0
+
+        -
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+                reserved: 0
+
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+
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+                num_resource: 22
+                type: 1818
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 10752
+                num_resource: 22
+                type: 1819
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 11264
+                num_resource: 28
+                type: 1820
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 11776
+                num_resource: 28
+                type: 1821
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 12288
+                num_resource: 28
+                type: 1822
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 1
+                type: 1923
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 10
+                type: 1936
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1936
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1936
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 13
+                num_resource: 3
+                type: 1936
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 16
+                num_resource: 3
+                type: 1936
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 64
+                type: 1937
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 64
+                type: 1937
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 83
+                num_resource: 8
+                type: 1938
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 91
+                num_resource: 8
+                type: 1939
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 99
+                num_resource: 10
+                type: 1942
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 109
+                num_resource: 3
+                type: 1942
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 109
+                num_resource: 3
+                type: 1942
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 112
+                num_resource: 3
+                type: 1942
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 115
+                num_resource: 3
+                type: 1942
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 118
+                num_resource: 16
+                type: 1943
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 118
+                num_resource: 16
+                type: 1943
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 134
+                num_resource: 8
+                type: 1944
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 134
+                num_resource: 8
+                type: 1945
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 142
+                num_resource: 8
+                type: 1946
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 142
+                num_resource: 8
+                type: 1947
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 10
+                type: 1955
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1955
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1955
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 13
+                num_resource: 3
+                type: 1955
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 16
+                num_resource: 3
+                type: 1955
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 8
+                type: 1956
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 8
+                type: 1956
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 27
+                num_resource: 1
+                type: 1957
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 28
+                num_resource: 1
+                type: 1958
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 10
+                type: 1961
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1961
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1961
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 13
+                num_resource: 3
+                type: 1961
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 16
+                num_resource: 3
+                type: 1961
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 10
+                type: 1962
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1962
+                host_id: 35
+                reserved: 0
+
+        -
+                start_resource: 10
+                num_resource: 3
+                type: 1962
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 13
+                num_resource: 3
+                type: 1962
+                host_id: 30
+                reserved: 0
+
+        -
+                start_resource: 16
+                num_resource: 3
+                type: 1962
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 1
+                type: 1963
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 1
+                type: 1963
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 16
+                type: 1964
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 19
+                num_resource: 16
+                type: 1964
+                host_id: 36
+                reserved: 0
+
+        -
+                start_resource: 20
+                num_resource: 1
+                type: 1965
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 35
+                num_resource: 8
+                type: 1966
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 21
+                num_resource: 1
+                type: 1967
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 35
+                num_resource: 8
+                type: 1968
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 22
+                num_resource: 1
+                type: 1969
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 43
+                num_resource: 8
+                type: 1970
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 23
+                num_resource: 1
+                type: 1971
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 43
+                num_resource: 8
+                type: 1972
+                host_id: 12
+                reserved: 0
+
+        -
+                start_resource: 0
+                num_resource: 1
+                type: 2112
+                host_id: 128
+                reserved: 0
+
+        -
+                start_resource: 2
+                num_resource: 2
+                type: 2122
+                host_id: 12
+                reserved: 0
diff --git a/board/toradex/verdin-am62/sec-cfg.yaml b/board/toradex/verdin-am62/sec-cfg.yaml
new file mode 100644
index 0000000000..07081ce06c
--- /dev/null
+++ b/board/toradex/verdin-am62/sec-cfg.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for AM62
+#
+
+---
+
+sec-cfg:
+    rev:
+        boardcfg_abi_maj : 0x0
+        boardcfg_abi_min : 0x1
+    processor_acl_list:
+        subhdr:
+            magic: 0xF1EA
+            size: 164
+        proc_acl_entries:
+            - #1
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #2
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #3
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #4
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #5
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #6
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #7
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #8
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #9
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #10
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #11
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #12
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #13
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #14
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #15
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #16
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #17
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #18
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #19
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #20
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #21
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #22
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #23
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #24
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #25
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #26
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #27
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #28
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #29
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #30
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #31
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            - #32
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+    host_hierarchy:
+        subhdr:
+            magic: 0x8D27
+            size: 68
+        host_hierarchy_entries:
+            - #1
+                host_id: 0
+                supervisor_host_id: 0
+            - #2
+                host_id: 0
+                supervisor_host_id: 0
+            - #3
+                host_id: 0
+                supervisor_host_id: 0
+            - #4
+                host_id: 0
+                supervisor_host_id: 0
+            - #5
+                host_id: 0
+                supervisor_host_id: 0
+            - #6
+                host_id: 0
+                supervisor_host_id: 0
+            - #7
+                host_id: 0
+                supervisor_host_id: 0
+            - #8
+                host_id: 0
+                supervisor_host_id: 0
+            - #9
+                host_id: 0
+                supervisor_host_id: 0
+            - #10
+                host_id: 0
+                supervisor_host_id: 0
+            - #11
+                host_id: 0
+                supervisor_host_id: 0
+            - #12
+                host_id: 0
+                supervisor_host_id: 0
+            - #13
+                host_id: 0
+                supervisor_host_id: 0
+            - #14
+                host_id: 0
+                supervisor_host_id: 0
+            - #15
+                host_id: 0
+                supervisor_host_id: 0
+            - #16
+                host_id: 0
+                supervisor_host_id: 0
+            - #17
+                host_id: 0
+                supervisor_host_id: 0
+            - #18
+                host_id: 0
+                supervisor_host_id: 0
+            - #19
+                host_id: 0
+                supervisor_host_id: 0
+            - #20
+                host_id: 0
+                supervisor_host_id: 0
+            - #21
+                host_id: 0
+                supervisor_host_id: 0
+            - #22
+                host_id: 0
+                supervisor_host_id: 0
+            - #23
+                host_id: 0
+                supervisor_host_id: 0
+            - #24
+                host_id: 0
+                supervisor_host_id: 0
+            - #25
+                host_id: 0
+                supervisor_host_id: 0
+            - #26
+                host_id: 0
+                supervisor_host_id: 0
+            - #27
+                host_id: 0
+                supervisor_host_id: 0
+            - #28
+                host_id: 0
+                supervisor_host_id: 0
+            - #29
+                host_id: 0
+                supervisor_host_id: 0
+            - #30
+                host_id: 0
+                supervisor_host_id: 0
+            - #31
+                host_id: 0
+                supervisor_host_id: 0
+            - #32
+                host_id: 0
+                supervisor_host_id: 0
+    otp_config:
+        subhdr:
+            magic: 0x4081
+            size: 69
+        write_host_id : 0
+        otp_entry:
+            - #1
+                host_id: 0
+                host_perms: 0
+            - #2
+                host_id: 0
+                host_perms: 0
+            - #3
+                host_id: 0
+                host_perms: 0
+            - #4
+                host_id: 0
+                host_perms: 0
+            - #5
+                host_id: 0
+                host_perms: 0
+            - #6
+                host_id: 0
+                host_perms: 0
+            - #7
+                host_id: 0
+                host_perms: 0
+            - #8
+                host_id: 0
+                host_perms: 0
+            - #9
+                host_id: 0
+                host_perms: 0
+            - #10
+                host_id: 0
+                host_perms: 0
+            - #11
+                host_id: 0
+                host_perms: 0
+            - #12
+                host_id: 0
+                host_perms: 0
+            - #13
+                host_id: 0
+                host_perms: 0
+            - #14
+                host_id: 0
+                host_perms: 0
+            - #15
+                host_id: 0
+                host_perms: 0
+            - #16
+                host_id: 0
+                host_perms: 0
+            - #17
+                host_id: 0
+                host_perms: 0
+            - #18
+                host_id: 0
+                host_perms: 0
+            - #19
+                host_id: 0
+                host_perms: 0
+            - #20
+                host_id: 0
+                host_perms: 0
+            - #21
+                host_id: 0
+                host_perms: 0
+            - #22
+                host_id: 0
+                host_perms: 0
+            - #23
+                host_id: 0
+                host_perms: 0
+            - #24
+                host_id: 0
+                host_perms: 0
+            - #25
+                host_id: 0
+                host_perms: 0
+            - #26
+                host_id: 0
+                host_perms: 0
+            - #27
+                host_id: 0
+                host_perms: 0
+            - #28
+                host_id: 0
+                host_perms: 0
+            - #29
+                host_id: 0
+                host_perms: 0
+            - #30
+                host_id: 0
+                host_perms: 0
+            - #31
+                host_id: 0
+                host_perms: 0
+            - #32
+                host_id: 0
+                host_perms: 0
+    dkek_config:
+        subhdr:
+            magic: 0x5170
+            size: 12
+        allowed_hosts: [128, 0, 0, 0]
+        allow_dkek_export_tisci : 0x5A
+        rsvd: [0, 0, 0]
+    sa2ul_cfg:
+        subhdr:
+            magic: 0x23BE
+            size : 0
+        auth_resource_owner: 0
+        enable_saul_psil_global_config_writes: 0x5A
+        rsvd: [0, 0]
+    sec_dbg_config:
+        subhdr:
+            magic: 0x42AF
+            size: 16
+        allow_jtag_unlock : 0x5A
+        allow_wildcard_unlock : 0x5A
+        allowed_debug_level_rsvd: 0
+        rsvd: 0
+        min_cert_rev : 0x0
+        jtag_unlock_hosts: [0, 0, 0, 0]
+    sec_handover_cfg:
+        subhdr:
+            magic: 0x608F
+            size: 10
+        handover_msg_sender : 0
+        handover_to_host_id : 0
+        rsvd: [0, 0, 0, 0]
diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c
new file mode 100644
index 0000000000..a3d1d07a0c
--- /dev/null
+++ b/board/toradex/verdin-am62/verdin-am62.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Board specific initialization for Verdin AM62 SoM
+ *
+ * Copyright 2023 Toradex - https://www.toradex.com/
+ *
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <k3-ddrss.h>
+#include <spl.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
+
+	if (gd->ram_size < SZ_64M)
+		puts("## WARNING: Less than 64MB RAM detected\n");
+
+	return 0;
+}
+
+/*
+ * Avoid relocated U-Boot clash with Linux reserved-memory on 512 MB SoM
+ */
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
+{
+	return 0x9C000000;
+}
+
+#if defined(CONFIG_SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+#endif
+
+#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+static void select_dt_from_module_version(void)
+{
+	char variant[32];
+	char *env_variant = env_get("variant");
+	int is_wifi = 0;
+
+	if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) {
+		/*
+		 * If we have a valid config block and it says we are a module with
+		 * Wi-Fi/Bluetooth make sure we use the -wifi device tree.
+		 */
+		is_wifi = (tdx_hw_tag.prodid == VERDIN_AM62Q_WIFI_BT_IT) ||
+			  (tdx_hw_tag.prodid == VERDIN_AM62S_512MB_WIFI_BT_IT) ||
+			  (tdx_hw_tag.prodid == VERDIN_AM62D_1G_WIFI_BT_IT) ||
+			  (tdx_hw_tag.prodid == VERDIN_AM62Q_2G_WIFI_BT_IT);
+	}
+
+	if (is_wifi)
+		strlcpy(&variant[0], "wifi", sizeof(variant));
+	else
+		strlcpy(&variant[0], "nonwifi", sizeof(variant));
+
+	if (strcmp(variant, env_variant)) {
+		printf("Setting variant to %s\n", variant);
+		env_set("variant", variant);
+	}
+}
+
+int board_late_init(void)
+{
+	select_dt_from_module_version();
+
+	return 0;
+}
+
+#define CTRLMMR_USB0_PHY_CTRL		0x43004008
+#define CTRLMMR_USB1_PHY_CTRL		0x43004018
+#define CORE_VOLTAGE			0x80000000
+#define MCU_CTRL_LFXOSC_32K_BYPASS_VAL	BIT(4)
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+	u32 val;
+
+	/* Set USB0 PHY core voltage to 0.85V */
+	val = readl(CTRLMMR_USB0_PHY_CTRL);
+	val &= ~(CORE_VOLTAGE);
+	writel(val, CTRLMMR_USB0_PHY_CTRL);
+
+	/* Set USB1 PHY core voltage to 0.85V */
+	val = readl(CTRLMMR_USB1_PHY_CTRL);
+	val &= ~(CORE_VOLTAGE);
+	writel(val, CTRLMMR_USB1_PHY_CTRL);
+
+	/* We use the 32k FOUT from the Epson RX8130CE RTC chip */
+	/* In WKUP_LFOSC0 clear the power down bit and set the bypass bit
+	 * The bypass bit is required as we provide a CMOS clock signal and
+	 * the power down seems to be required also in the bypass case
+	 * despite of the datasheet stating otherwise
+	 */
+	/* Compare with the AM62 datasheet,
+	 * Table 7-21. LFXOSC Modes of Operation
+	 */
+	val = readl(MCU_CTRL_LFXOSC_CTRL);
+	val &= ~MCU_CTRL_LFXOSC_32K_DISABLE_VAL;
+	val |= MCU_CTRL_LFXOSC_32K_BYPASS_VAL;
+	writel(val, MCU_CTRL_LFXOSC_CTRL);
+	/* Make sure to mux up to take the SoC 32k from the LFOSC input */
+	writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
+	       MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
+}
+#endif
diff --git a/board/toradex/verdin-imx8mm/MAINTAINERS b/board/toradex/verdin-imx8mm/MAINTAINERS
index 974b3a1032..8217bbcdc0 100644
--- a/board/toradex/verdin-imx8mm/MAINTAINERS
+++ b/board/toradex/verdin-imx8mm/MAINTAINERS
@@ -3,12 +3,12 @@ M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
 W:	https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini
 S:	Maintained
 F:	arch/arm/dts/imx8mm-verdin.dtsi
-F:	arch/arm/dts/imx8mm-verdin-dahlia.dtsi
 F:	arch/arm/dts/imx8mm-verdin-dev.dtsi
 F:	arch/arm/dts/imx8mm-verdin-wifi.dtsi
 F:	arch/arm/dts/imx8mm-verdin-wifi-dev.dts
 F:	arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
 F:	board/toradex/verdin-imx8mm/
+F:	board/toradex/common/
 F:	configs/verdin-imx8mm_defconfig
 F:	doc/board/toradex/verdin-imx8mm.rst
 F:	include/configs/verdin-imx8mm.h
diff --git a/board/toradex/verdin-imx8mp/MAINTAINERS b/board/toradex/verdin-imx8mp/MAINTAINERS
index cff3c50383..85d6be8816 100644
--- a/board/toradex/verdin-imx8mp/MAINTAINERS
+++ b/board/toradex/verdin-imx8mp/MAINTAINERS
@@ -1,11 +1,11 @@
 Verdin iMX8M Plus
 F:	arch/arm/dts/imx8mp-verdin.dtsi
-F:	arch/arm/dts/imx8mp-verdin-dahlia.dtsi
 F:	arch/arm/dts/imx8mp-verdin-dev.dtsi
 F:	arch/arm/dts/imx8mp-verdin-wifi.dtsi
 F:	arch/arm/dts/imx8mp-verdin-wifi-dev.dts
 F:	arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
 F:	board/toradex/verdin-imx8mp/
+F:	board/toradex/common/
 F:	configs/verdin-imx8mp_defconfig
 F:	doc/board/toradex/verdin-imx8mp.rst
 F:	include/configs/verdin-imx8mp.h
diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
index 5490d3ed44..e16a771e3e 100644
--- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c
+++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
@@ -81,7 +81,8 @@ static void select_dt_from_module_version(void)
 		 */
 		is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_WIFI_BT_IT) ||
 			  (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_2GB_WIFI_BT_IT) ||
-			  (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT);
+			  (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT) ||
+			  (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT_IT);
 	}
 
 	if (is_wifi)
diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c
index 5dfb7165c0..df9f0afe1a 100644
--- a/board/traverse/ten64/ten64.c
+++ b/board/traverse/ten64/ten64.c
@@ -31,6 +31,7 @@
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <nvme.h>
 
 #include <fsl_immap.h>
 
@@ -47,7 +48,9 @@ static void ten64_board_retimer_ds110df410_init(void);
 enum {
 	TEN64_BOARD_REV_A = 0xFF,
 	TEN64_BOARD_REV_B = 0xFE,
-	TEN64_BOARD_REV_C = 0xFD
+	TEN64_BOARD_REV_C = 0xFD,
+	TEN64_BOARD_REV_D = 0xFC,
+	TEN64_BOARD_MAX
 };
 
 #define RESV_MEM_IN_BANK(b)	(gd->arch.resv_ram >= base[b] && \
@@ -75,20 +78,24 @@ int checkboard(void)
 
 	switch (board_rev) {
 	case TEN64_BOARD_REV_A:
-		snprintf(boardmodel, 32, "1064-0201A (Alpha)");
+		snprintf(boardmodel, 32, "A (Alpha)");
 		break;
 	case TEN64_BOARD_REV_B:
-		snprintf(boardmodel, 32, "1064-0201B (Beta)");
+		snprintf(boardmodel, 32, "B (Beta)");
 		break;
 	case TEN64_BOARD_REV_C:
-		snprintf(boardmodel, 32, "1064-0201C");
+		snprintf(boardmodel, 32, "C");
+		break;
+	case TEN64_BOARD_REV_D:
+		snprintf(boardmodel, 32, "D");
 		break;
 	default:
-		snprintf(boardmodel, 32, "1064 Revision %X", (0xFF - board_rev));
+		snprintf(boardmodel, 32, " Revision %X", (0xFF - board_rev));
 		break;
 	}
 
-	printf("Board: %s, boot from ", boardmodel);
+	printf("Board: 1064-0201%s, boot from ", boardmodel);
+
 	if (src == BOOT_SOURCE_SD_MMC)
 		puts("SD card\n");
 	else if (src == BOOT_SOURCE_QSPI_NOR)
@@ -167,6 +174,12 @@ void fdt_fixup_board_enet(void *fdt)
 		return;
 	}
 
+	/* In the U-Boot FDT, a 'simple-mfd' compatible is added.
+	 * Remove this as FreeBSD will only match "fsl,qoriq-mc"
+	 * exactly on the DPAA2 bus/MC node.
+	 */
+	fdt_setprop(fdt, offset, "compatible", "fsl,qoriq-mc", 12);
+
 	if (get_mc_boot_status() == 0 &&
 	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 		fdt_status_okay(fdt, offset);
@@ -178,6 +191,11 @@ void fdt_fixup_board_enet(void *fdt)
 int fsl_board_late_init(void)
 {
 	ten64_board_retimer_ds110df410_init();
+
+	/* Ensure nvme storage devices are available to bootflow */
+	if (IS_ENABLED(CONFIG_NVME))
+		nvme_scan_namespace();
+
 	return 0;
 }
 
@@ -284,6 +302,7 @@ static void ten64_set_macaddrs_from_board_info(struct t64uc_board_info *boardinf
 {
 	char ethaddr[18];
 	char enetvar[10];
+	char serial[18];
 	u8 intfidx, this_dpmac_num;
 	u64 macaddr = 0;
 	/* We will copy the MAC address returned from the
@@ -304,6 +323,19 @@ static void ten64_set_macaddrs_from_board_info(struct t64uc_board_info *boardinf
 	 */
 	macaddr = __be64_to_cpu(macaddr);
 
+	/* Set serial# to GE0/DPMAC7 MAC address
+	 * (Matches the labels on the board and appliance)
+	 */
+	snprintf(serial, 18, "%02X%02X%02X%02X%02X%02X",
+		 MACADDRBITS(macaddr, 40),
+		 MACADDRBITS(macaddr, 32),
+		 MACADDRBITS(macaddr, 24),
+		 MACADDRBITS(macaddr, 16),
+		 MACADDRBITS(macaddr, 8),
+		 MACADDRBITS(macaddr, 0));
+	if (!env_get("serial#"))
+		env_set("serial#", serial);
+
 	for (intfidx = 0; intfidx < 10; intfidx++) {
 		snprintf(ethaddr, 18, "%02X:%02X:%02X:%02X:%02X:%02X",
 			 MACADDRBITS(macaddr, 40),
@@ -316,8 +348,8 @@ static void ten64_set_macaddrs_from_board_info(struct t64uc_board_info *boardinf
 		this_dpmac_num = allocation_order[intfidx];
 		printf("DPMAC%d: %s\n", this_dpmac_num, ethaddr);
 		snprintf(enetvar, 10,
-			 (this_dpmac_num != 1) ? "eth%daddr" : "ethaddr",
-			 this_dpmac_num - 1);
+			 (intfidx != 0) ? "eth%daddr" : "ethaddr",
+			 intfidx);
 		macaddr++;
 
 		if (!env_get(enetvar))
@@ -335,20 +367,32 @@ static int board_cycle_retimer(struct udevice **retim_dev)
 	u8 loop;
 	struct udevice *uc_dev;
 	struct udevice *i2cbus;
+	u32 board_rev = ten64_get_board_rev();
 
 	ret = ten64_get_micro_udevice(&uc_dev, &i2cbus);
 	if (ret)
 		return ret;
 
-	ret = dm_i2c_probe(i2cbus, I2C_RETIMER_ADDR, 0, retim_dev);
-	if (ret == 0) {
-		puts("(retimer on, resetting...) ");
+	/* Retimer power cycle not implemented on early board
+	 * revisions/controller firmwares
+	 */
+	if (IS_ENABLED(CONFIG_TEN64_CONTROLLER) &&
+	    board_rev <= TEN64_BOARD_REV_C) {
+		ret = dm_i2c_probe(i2cbus, I2C_RETIMER_ADDR, 0, retim_dev);
+		if (ret == 0) {
+			puts("(retimer on, resetting...) ");
 
-		ret = misc_call(uc_dev, TEN64_CNTRL_10G_OFF, NULL, 0, NULL, 0);
-		mdelay(1000);
-	}
+			ret = misc_call(uc_dev, TEN64_CNTRL_10G_OFF, NULL, 0, NULL, 0);
+			if (ret)
+				return ret;
+			mdelay(1000);
+		}
 
-	ret = misc_call(uc_dev, TEN64_CNTRL_10G_ON, NULL, 0, NULL, 0);
+		/* Turn on the retimer */
+		ret = misc_call(uc_dev, TEN64_CNTRL_10G_ON, NULL, 0, NULL, 0);
+		if (ret)
+			return ret;
+	}
 
 	// Wait for retimer to come back
 	for (loop = 0; loop < 5; loop++) {
@@ -369,19 +413,13 @@ static void ten64_board_retimer_ds110df410_init(void)
 	u8 reg;
 	int ret;
 	struct udevice *retim_dev;
-	u32 board_rev = ten64_get_board_rev();
 
 	puts("Retimer: ");
-	/* Retimer power cycle not implemented on early board
-	 * revisions/controller firmwares
-	 */
-	if (IS_ENABLED(CONFIG_TEN64_CONTROLLER) &&
-	    board_rev >= TEN64_BOARD_REV_C) {
-		ret = board_cycle_retimer(&retim_dev);
-		if (ret) {
-			puts("Retimer power on failed\n");
-			return;
-		}
+
+	ret = board_cycle_retimer(&retim_dev);
+	if (ret) {
+		puts("Retimer power on failed\n");
+		return;
 	}
 
 	/* Access to Control/Shared register */
@@ -437,3 +475,13 @@ static void ten64_board_retimer_ds110df410_init(void)
 
 	puts("OK\n");
 }
+
+/* Opt out of the fsl_setenv_bootcmd
+ * in arch/arm/cpu/armv8/fsl-layerscape/soc.c
+ * which is invoked by board_late_init.
+ */
+int fsl_setenv_bootcmd(void)
+{
+	return 0;
+}
+
diff --git a/board/vamrs/rock960_rk3399/MAINTAINERS b/board/vamrs/rock960_rk3399/MAINTAINERS
index 5ee5256495..8821672a3a 100644
--- a/board/vamrs/rock960_rk3399/MAINTAINERS
+++ b/board/vamrs/rock960_rk3399/MAINTAINERS
@@ -1,7 +1,7 @@
 ROCK960-RK3399
 M:      Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 S:      Maintained
-F:      board/rockchip/rock960_rk3399
+F:      board/vamrs/rock960_rk3399/
 F:      include/configs/rock960_rk3399.h
 F:      configs/rock960-rk3399_defconfig
 
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index d40f4d0176..61b9455a8f 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -1,11 +1,50 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2021 Collabora Ltd.
+ * Copyright 2018-2020 Variscite Ltd.
+ * Copyright 2023 DimOnOff Inc.
  */
 
 #include <common.h>
+#include <dm.h>
 #include <env.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <i2c_eeprom.h>
+#include <malloc.h>
 #include <asm/io.h>
+#include <asm/global_data.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <linux/libfdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Optional SOM features flags. */
+#define VAR_EEPROM_F_WIFI		BIT(0)
+#define VAR_EEPROM_F_ETH		BIT(1) /* Ethernet PHY on SOM. */
+#define VAR_EEPROM_F_AUDIO		BIT(2)
+#define VAR_EEPROM_F_MX8M_LVDS		BIT(3) /* i.MX8MM, i.MX8MN, i.MX8MQ only */
+#define VAR_EEPROM_F_MX8Q_SOC_ID	BIT(3) /* 0 = i.MX8QM, 1 = i.MX8QP */
+#define VAR_EEPROM_F_NAND		BIT(4)
+
+#define VAR_IMX8_EEPROM_MAGIC	0x384D /* "8M" */
+
+/* Number of DRAM adjustment tables. */
+#define DRAM_TABLES_NUM 7
+
+struct var_imx8_eeprom_info {
+	u16 magic;
+	u8 partnumber[3];         /* Part number */
+	u8 assembly[10];          /* Assembly number */
+	u8 date[9];               /* Build date */
+	u8 mac[6];                /* MAC address */
+	u8 somrev;
+	u8 eeprom_version;
+	u8 features;              /* SOM features */
+	u8 dramsize;              /* DRAM size */
+	u8 off[DRAM_TABLES_NUM + 1]; /* DRAM table offsets */
+	u8 partnumber2[5];        /* Part number 2 */
+} __packed;
 
 static void setup_fec(void)
 {
@@ -28,3 +67,178 @@ int board_mmc_get_env_dev(int devno)
 {
 	return devno;
 }
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+
+static void display_som_infos(struct var_imx8_eeprom_info *info)
+{
+	char partnumber[sizeof(info->partnumber) +
+			sizeof(info->partnumber2) + 1];
+	char assembly[sizeof(info->assembly) + 1];
+	char date[sizeof(info->date) + 1];
+
+	/* Read first part of P/N. */
+	memcpy(partnumber, info->partnumber, sizeof(info->partnumber));
+
+	/* Read second part of P/N. */
+	if (info->eeprom_version >= 3)
+		memcpy(partnumber + sizeof(info->partnumber), info->partnumber2,
+		       sizeof(info->partnumber2));
+
+	memcpy(assembly, info->assembly, sizeof(info->assembly));
+	memcpy(date, info->date, sizeof(info->date));
+
+	/* Make sure strings are null terminated. */
+	partnumber[sizeof(partnumber) - 1] = '\0';
+	assembly[sizeof(assembly) - 1] = '\0';
+	date[sizeof(date) - 1] = '\0';
+
+	printf("SOM board: P/N: %s, Assy: %s, Date: %s\n"
+	       "           Wifi: %s, EthPhy: %s, Rev: %d\n",
+	       partnumber, assembly, date,
+	       info->features & VAR_EEPROM_F_WIFI ? "yes" : "no",
+	       info->features & VAR_EEPROM_F_ETH ? "yes" : "no",
+	       info->somrev);
+}
+
+static int var_read_som_eeprom(struct var_imx8_eeprom_info *info)
+{
+	const char *path = "eeprom-som";
+	struct udevice *dev;
+	int ret, off;
+
+	off = fdt_path_offset(gd->fdt_blob, path);
+	if (off < 0) {
+		pr_err("%s: fdt_path_offset() failed: %d\n", __func__, off);
+		return off;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+	if (ret) {
+		pr_err("%s: uclass_get_device_by_of_offset() failed: %d\n",
+		       __func__, ret);
+		return ret;
+	}
+
+	ret = i2c_eeprom_read(dev, 0, (uint8_t *)info,
+			      sizeof(struct var_imx8_eeprom_info));
+	if (ret) {
+		pr_err("%s: i2c_eeprom_read() failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	if (htons(info->magic) != VAR_IMX8_EEPROM_MAGIC) {
+		/* Do not fail if the content is invalid */
+		pr_err("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n",
+		       htons(info->magic), VAR_IMX8_EEPROM_MAGIC);
+	}
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	int rc;
+	struct var_imx8_eeprom_info *info;
+
+	info = malloc(sizeof(struct var_imx8_eeprom_info));
+	if (!info)
+		return -ENOMEM;
+
+	rc = var_read_som_eeprom(info);
+	if (rc)
+		return rc;
+
+	display_som_infos(info);
+
+#if defined(CONFIG_BOARD_TYPES)
+	gd->board_type = info->features;
+#endif /* CONFIG_BOARD_TYPES */
+
+	return 0;
+}
+
+#endif /* CONFIG_DISPLAY_BOARDINFO */
+
+static int insert_gpios_prop(void *blob, int node, const char *prop,
+			     unsigned int phandle, u32 gpio, u32 flags)
+{
+	fdt32_t val[3] = { cpu_to_fdt32(phandle), cpu_to_fdt32(gpio),
+			   cpu_to_fdt32(flags) };
+	return fdt_setprop(blob, node, prop, &val, sizeof(val));
+}
+
+static int configure_phy_reset_gpios(void *blob)
+{
+	int node;
+	int phynode;
+	int ret;
+	u32 handle;
+	u32 gpio;
+	u32 flags;
+	char path[1024];
+	const char *eth_alias = "ethernet0";
+
+	snprintf(path, sizeof(path), "%s/mdio/ethernet-phy@4",
+		 fdt_get_alias(blob, eth_alias));
+
+	phynode = fdt_path_offset(blob, path);
+	if (phynode < 0) {
+		pr_err("%s(): unable to locate PHY node: %s\n", __func__, path);
+		return 0;
+	}
+
+	if (gd_board_type() & VAR_EEPROM_F_ETH) {
+		snprintf(path, sizeof(path), "%s",
+			 fdt_get_alias(blob, "gpio0")); /* Alias to gpio1 */
+		gpio = 9;
+		flags = GPIO_ACTIVE_LOW;
+	} else {
+		snprintf(path, sizeof(path), "%s/gpio@20",
+			 fdt_get_alias(blob, "i2c1")); /* Alias to i2c2 */
+		gpio = 5;
+		flags = GPIO_ACTIVE_HIGH;
+	}
+
+	node = fdt_path_offset(blob, path);
+	if (node < 0) {
+		pr_err("%s(): unable to locate GPIO node: %s\n", __func__,
+		       path);
+		return 0;
+	}
+
+	handle = fdt_get_phandle(blob, node);
+	if (handle < 0) {
+		pr_err("%s(): unable to locate GPIO controller handle: %s\n",
+		       __func__, path);
+	}
+
+	ret = insert_gpios_prop(blob, phynode, "reset-gpios",
+				handle, gpio, flags);
+	if (ret < 0) {
+		pr_err("%s(): failed to set reset-gpios property\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *blob)
+{
+	/* Fix U-Boot device tree: */
+	return configure_phy_reset_gpios(blob);
+}
+#endif /* CONFIG_OF_BOARD_FIXUP */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	/* Fix kernel device tree: */
+	return configure_phy_reset_gpios(blob);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index f335d5b4f4..8f23cda8e4 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -76,17 +76,23 @@ static int baltos_set_console(void)
 
 static int read_eeprom(BSP_VS_HWPARAM *header)
 {
-	i2c_set_bus_num(1);
+	int rc;
+	struct udevice *dev;
+	struct udevice *bus;
+
+	rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
+	if (rc)
+		return rc;
 
 	/* Check if baseboard eeprom is available */
-	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+	if (dm_i2c_probe(bus, CONFIG_SYS_I2C_EEPROM_ADDR, 0, &dev)) {
 		puts("Could not probe the EEPROM; something fundamentally "
 			"wrong on the I2C bus.\n");
 		return -ENODEV;
 	}
 
 	/* read the eeprom using i2c */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+	if (dm_i2c_read(dev, 0, (uchar *)header,
 		     sizeof(BSP_VS_HWPARAM))) {
 		puts("Could not read the EEPROM; something fundamentally"
 			" wrong on the I2C bus.\n");
@@ -173,34 +179,28 @@ const struct dpll_params dpll_ddr_baltos = {
 
 void am33xx_spl_board_init(void)
 {
-	int mpu_vdd;
-	int sil_rev;
+	int sil_rev, mpu_vdd;
+	int freq;
+
+	enable_i2c1_pin_mux();
+	i2c_set_bus_num(1);
 
-	/* Get the frequency */
-	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+	freq = am335x_get_efuse_mpu_max_freq(cdev);
 
 	/*
-	 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
+	 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
 	 * MPU frequencies we support we use a CORE voltage of
-	 * 1.1375V.  For MPU voltage we need to switch based on
+	 * 1.1375V. For MPU voltage we need to switch based on
 	 * the frequency we are running at.
 	 */
-	i2c_set_bus_num(1);
-
-	printf("I2C speed: %d Hz\n", CONFIG_SYS_I2C_SPEED);
-
-	if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
-		puts("i2c: cannot access TPS65910\n");
+	if (power_tps65910_init(1))
 		return;
-	}
-
 	/*
 	 * Depending on MPU clock and PG we will need a different
 	 * VDD to drive at that speed.
 	 */
 	sil_rev = readl(&cdev->deviceid) >> 28;
-	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
-					      dpll_mpu_opp100.m);
+	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
 
 	/* Tell the TPS65910 to use i2c */
 	tps65910_set_i2c_control();
@@ -213,12 +213,6 @@ void am33xx_spl_board_init(void)
 	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 		return;
 
-	/* Set CORE Frequencies to OPP100 */
-	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
-	/* Set MPU Frequency to what we detected now that voltages are set */
-	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-
 	writel(0x000010ff, PRM_DEVICE_INST + 4);
 }
 
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index da995dd0f5..48914450a2 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -352,9 +352,8 @@ static void setup_display(void)
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
-#ifdef CONFIG_SATA
-	setup_sata();
-#endif
+	if (CONFIG_IS_ENABLED(SATA))
+		setup_sata();
 
 	return 0;
 }
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
deleted file mode 100644
index b00accca1b..0000000000
--- a/board/xes/common/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
-obj-$(CONFIG_ARCH_P2020)		+= fsl_8xxx_clk.o
-obj-$(CONFIG_MPC85xx)		+= fsl_8xxx_misc.o board.o
-obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_misc.o board.o
diff --git a/board/xes/common/board.c b/board/xes/common/board.c
deleted file mode 100644
index 053b07a0b7..0000000000
--- a/board/xes/common/board.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009 Extreme Engineering Solutions, Inc.
- */
-
-#include <common.h>
-#include <env.h>
-#include "fsl_8xxx_misc.h"
-#include <init.h>
-
-int checkboard(void)
-{
-	char name[] = CONFIG_SYS_BOARD_NAME;
-	char buf[64];
-	char *s;
-	int i;
-
-#ifdef CONFIG_SYS_FORM_CUSTOM
-	s = "Custom";
-#elif CONFIG_SYS_FORM_6U_CPCI
-	s = "6U CompactPCI";
-#elif CONFIG_SYS_FORM_ATCA_PMC
-	s = "ATCA w/PMC";
-#elif CONFIG_SYS_FORM_ATCA_AMC
-	s = "ATCA w/AMC";
-#elif CONFIG_SYS_FORM_VME
-	s = "VME";
-#elif CONFIG_SYS_FORM_6U_VPX
-	s = "6U VPX";
-#elif CONFIG_SYS_FORM_PMC
-	s = "PMC";
-#elif CONFIG_SYS_FORM_PCI
-	s = "PCI";
-#elif CONFIG_SYS_FORM_3U_CPCI
-	s = "3U CompactPCI";
-#elif CONFIG_SYS_FORM_AMC
-	s = "AdvancedMC";
-#elif CONFIG_SYS_FORM_XMC
-	s = "XMC";
-#elif CONFIG_SYS_FORM_PMC_XMC
-	s = "PMC/XMC";
-#elif CONFIG_SYS_FORM_PCI_EXPRESS
-	s = "PCI Express";
-#elif CONFIG_SYS_FORM_3U_VPX
-	s = "3U VPX";
-#else
-#error "Form factor not defined"
-#endif
-
-	name[strlen(name) - 1] += get_board_derivative();
-	printf("Board: X-ES %s %s SBC\n", name, s);
-
-	/* Display board specific information */
-	puts("       ");
-	i = env_get_f("board_rev", buf, sizeof(buf));
-	if (i > 0)
-		printf("Rev %s, ", buf);
-	i = env_get_f("serial#", buf, sizeof(buf));
-	if (i > 0)
-		printf("Serial# %s, ", buf);
-	i = env_get_f("board_cfg", buf, sizeof(buf));
-	if (i > 0)
-		printf("Cfg %s", buf);
-	puts("\n");
-
-	return 0;
-}
diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c
deleted file mode 100644
index c36b2afd50..0000000000
--- a/board/xes/common/fsl_8xxx_clk.c
+++ /dev/null
@@ -1,54 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <asm/io.h>
-
-/*
- * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
- */
-unsigned long get_board_sys_clk(void)
-{
-#if defined(CONFIG_MPC85xx)
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-#elif defined(CONFIG_MPC86xx)
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-#endif
-
-	if (in_be32(&gur->gpporcr) & 0x10000)
-		return 66666666;
-	else
-#ifdef CONFIG_ARCH_P2020
-		return 100000000;
-#else
-		return 50000000;
-#endif
-}
-
-#ifdef CONFIG_MPC85xx
-/*
- * Return DDR input clock - synchronous with SYSCLK or 66 MHz
- * Note: 86xx doesn't support asynchronous DDR clk
- */
-unsigned long get_board_ddr_clk(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-	u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
-
-	if (ddr_ratio == 0x7)
-		return get_board_sys_clk();
-
-#ifdef CONFIG_ARCH_P2020
-	if (in_be32(&gur->gpporcr) & 0x20000)
-		return 66666666;
-	else
-		return 100000000;
-#else
-	return 66666666;
-#endif
-}
-#endif
diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c
deleted file mode 100644
index bc7e5c5764..0000000000
--- a/board/xes/common/fsl_8xxx_misc.c
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-#ifdef CONFIG_PCA953X
-#include <pca953x.h>
-
-/*
- * Determine if a board's flashes are write protected
- */
-int board_flash_wp_on(void)
-{
-	if (pca953x_get_val(CFG_SYS_I2C_PCA953X_ADDR0) &
-			CONFIG_SYS_PCA953X_NVM_WP)
-		return 1;
-
-	return 0;
-}
-#endif
-
-/*
- * Return a board's derivative model number.  For example:
- * return 2 for the XPedite5372 and return 1 for the XPedite5201.
- */
-uint get_board_derivative(void)
-{
-#if defined(CONFIG_MPC85xx)
-       volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
-#elif defined(CONFIG_MPC86xx)
-       volatile immap_t *immap = (immap_t *)CFG_SYS_CCSRBAR;
-       volatile ccsr_gur_t *gur = &immap->im_gur;
-#endif
-
-       /*
-	* The top 4 lines of the local bus address are pulled low/high and
-	* can be read to determine the least significant digit of a board's
-	* model number.
-	*/
-       return gur->gpporcr >> 28;
-}
diff --git a/board/xes/common/fsl_8xxx_misc.h b/board/xes/common/fsl_8xxx_misc.h
deleted file mode 100644
index 6e4858f15c..0000000000
--- a/board/xes/common/fsl_8xxx_misc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- */
-
-#ifndef __FSL_8XXX_MISC_H___
-#define __FSL_8XXX_MISC_H___
-
-uint get_board_derivative(void);
-
-#endif /* __FSL_8XXX_MISC_H__ */
diff --git a/board/xilinx/common/Makefile b/board/xilinx/common/Makefile
index cdc3c96774..d563290ab9 100644
--- a/board/xilinx/common/Makefile
+++ b/board/xilinx/common/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 # (C) Copyright 2020 Xilinx, Inc.
-# Michal Simek <michal.simek@xilinx.com>
+# Michal Simek <michal.simek@amd.com>
 #
 
 obj-y	+= board.o
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index d071ebfb9c..906d5e3c2d 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -52,10 +52,10 @@ struct efi_fw_image fw_images[] = {
 };
 
 struct efi_capsule_update_info update_info = {
+	.num_images = ARRAY_SIZE(fw_images),
 	.images = fw_images,
 };
 
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
 
 #define EEPROM_HEADER_MAGIC		0xdaaddeed
@@ -627,7 +627,7 @@ int embedded_dtb_select(void)
 #endif
 
 #if defined(CONFIG_LMB)
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	phys_size_t size;
 	phys_addr_t reg;
diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h
index 69e642429b..64d657673e 100644
--- a/board/xilinx/common/board.h
+++ b/board/xilinx/common/board.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * (C) Copyright 2020 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #ifndef _BOARD_XILINX_COMMON_BOARD_H
@@ -11,4 +11,11 @@ int board_late_init_xilinx(void);
 
 int xilinx_read_eeprom(void);
 
+char *board_name_decode(void);
+
+bool board_detection(void);
+
+char *soc_name_decode(void);
+
+bool soc_detection(void);
 #endif /* BOARD_XILINX_COMMON_BOARD_H */
diff --git a/board/xilinx/common/cpu-info.c b/board/xilinx/common/cpu-info.c
index 4eccc7abbe..bfe7f5b7e3 100644
--- a/board/xilinx/common/cpu-info.c
+++ b/board/xilinx/common/cpu-info.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2014 - 2020 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <common.h>
diff --git a/board/xilinx/common/fru.h b/board/xilinx/common/fru.h
index 586c41b66e..2b3fa05a61 100644
--- a/board/xilinx/common/fru.h
+++ b/board/xilinx/common/fru.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2019 Xilinx, Inc.
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 #ifndef __FRU_H
diff --git a/board/xilinx/versal-net/Kconfig b/board/xilinx/versal-net/Kconfig
index 8f94d2bb39..2484429d3c 100644
--- a/board/xilinx/versal-net/Kconfig
+++ b/board/xilinx/versal-net/Kconfig
@@ -6,4 +6,12 @@
 
 if ARCH_VERSAL_NET
 
+config CMD_VERSAL_NET
+	bool "Enable Versal NET specific commands"
+	default y
+	depends on ZYNQMP_FIRMWARE
+	help
+	  Select this to enable Versal NET specific commands.
+	  Commands like versalnet loadpdi are enabled by this.
+
 endif
diff --git a/board/xilinx/versal-net/Makefile b/board/xilinx/versal-net/Makefile
index 2008d4e231..f9ff07c11c 100644
--- a/board/xilinx/versal-net/Makefile
+++ b/board/xilinx/versal-net/Makefile
@@ -7,3 +7,4 @@
 #
 
 obj-y	:= board.o
+obj-$(CONFIG_CMD_VERSAL_NET)	+= cmds.o
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index 6724c7290f..f0d2224b33 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -10,6 +10,7 @@
 #include <cpu_func.h>
 #include <fdtdec.h>
 #include <init.h>
+#include <env_internal.h>
 #include <log.h>
 #include <malloc.h>
 #include <time.h>
@@ -74,32 +75,45 @@ char *soc_name_decode(void)
 
 bool soc_detection(void)
 {
-	u32 version;
+	u32 version, ps_version;
 
 	version = readl(PMC_TAP_VERSION);
 	platform_id = FIELD_GET(PLATFORM_MASK, version);
+	ps_version = FIELD_GET(PS_VERSION_MASK, version);
 
 	debug("idcode %x, version %x, usercode %x\n",
 	      readl(PMC_TAP_IDCODE), version,
 	      readl(PMC_TAP_USERCODE));
 
-	debug("pmc_ver %lx, ps version %lx, rtl version %lx\n",
+	debug("pmc_ver %lx, ps version %x, rtl version %lx\n",
 	      FIELD_GET(PMC_VERSION_MASK, version),
-	      FIELD_GET(PS_VERSION_MASK, version),
+	      ps_version,
 	      FIELD_GET(RTL_VERSION_MASK, version));
 
 	platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
 
 	if (platform_id == VERSAL_NET_SPP ||
 	    platform_id == VERSAL_NET_EMU) {
-		/*
-		 * 9 is diff for
-		 * 0 means 0.9 version
-		 * 1 means 1.0 version
-		 * 2 means 1.1 version
-		 * etc,
-		 */
-		platform_version += 9;
+		if (ps_version == PS_VERSION_PRODUCTION) {
+			/*
+			 * ES1 version ends at 1.9 version where there was +9
+			 * used because of IPP/SPP conversion. Production
+			 * version have platform_version started from 0 again
+			 * that's why adding +20 to continue with the same line.
+			 * It means the last ES1 version ends at 1.9 version and
+			 * new PRODUCTION line starts at 2.0.
+			 */
+			platform_version += 20;
+		} else {
+			/*
+			 * 9 is diff for
+			 * 0 means 0.9 version
+			 * 1 means 1.0 version
+			 * 2 means 1.1 version
+			 * etc,
+			 */
+			platform_version += 9;
+		}
 	}
 
 	debug("Platform id: %d version: %d.%d\n", platform_id,
@@ -165,8 +179,32 @@ int board_early_init_r(void)
 	return 0;
 }
 
+static u8 versal_net_get_bootmode(void)
+{
+	u8 bootmode;
+	u32 reg = 0;
+
+	reg = readl(&crp_base->boot_mode_usr);
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
 int board_late_init(void)
 {
+	u8 bootmode;
+	struct udevice *dev;
+	int bootseq = -1;
+	int bootseq_len = 0;
+	int env_targets_len = 0;
+	const char *mode;
+	char *new_targets;
+	char *env_targets;
+
 	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 		debug("Saved variables - Skipping\n");
 		return 0;
@@ -175,6 +213,113 @@ int board_late_init(void)
 	if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
 		return 0;
 
+	bootmode = versal_net_get_bootmode();
+
+	puts("Bootmode: ");
+	switch (bootmode) {
+	case USB_MODE:
+		puts("USB_MODE\n");
+		mode = "usb_dfu0 usb_dfu1";
+		break;
+	case JTAG_MODE:
+		puts("JTAG_MODE\n");
+		mode = "jtag pxe dhcp";
+		break;
+	case QSPI_MODE_24BIT:
+		puts("QSPI_MODE_24\n");
+		if (uclass_get_device_by_name(UCLASS_SPI,
+					      "spi@f1030000", &dev)) {
+			puts("Boot from QSPI but without QSPI enabled!\n");
+			return -1;
+		}
+		mode = "xspi";
+		bootseq = dev_seq(dev);
+		break;
+	case QSPI_MODE_32BIT:
+		puts("QSPI_MODE_32\n");
+		if (uclass_get_device_by_name(UCLASS_SPI,
+					      "spi@f1030000", &dev)) {
+			puts("Boot from QSPI but without QSPI enabled!\n");
+			return -1;
+		}
+		mode = "xspi";
+		bootseq = dev_seq(dev);
+		break;
+	case OSPI_MODE:
+		puts("OSPI_MODE\n");
+		if (uclass_get_device_by_name(UCLASS_SPI,
+					      "spi@f1010000", &dev)) {
+			puts("Boot from OSPI but without OSPI enabled!\n");
+			return -1;
+		}
+		mode = "xspi";
+		bootseq = dev_seq(dev);
+		break;
+	case EMMC_MODE:
+		puts("EMMC_MODE\n");
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		break;
+	case SD_MODE:
+		puts("SD_MODE\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "mmc@f1040000", &dev)) {
+			puts("Boot from SD0 but without SD0 enabled!\n");
+			return -1;
+		}
+		debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		break;
+	case SD1_LSHFT_MODE:
+		puts("LVL_SHFT_");
+		fallthrough;
+	case SD_MODE1:
+		puts("SD_MODE1\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "mmc@f1050000", &dev)) {
+			puts("Boot from SD1 but without SD1 enabled!\n");
+			return -1;
+		}
+		debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		break;
+	default:
+		mode = "";
+		printf("Invalid Boot Mode:0x%x\n", bootmode);
+		break;
+	}
+
+	if (bootseq >= 0) {
+		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
+		debug("Bootseq len: %x\n", bootseq_len);
+	}
+
+	/*
+	 * One terminating char + one byte for space between mode
+	 * and default boot_targets
+	 */
+	env_targets = env_get("boot_targets");
+	if (env_targets)
+		env_targets_len = strlen(env_targets);
+
+	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
+			     bootseq_len);
+	if (!new_targets)
+		return -ENOMEM;
+
+	if (bootseq >= 0)
+		sprintf(new_targets, "%s%x %s", mode, bootseq,
+			env_targets ? env_targets : "");
+	else
+		sprintf(new_targets, "%s %s", mode,
+			env_targets ? env_targets : "");
+
+	env_set("boot_targets", new_targets);
+
 	return board_late_init_xilinx();
 }
 
diff --git a/board/xilinx/versal-net/cmds.c b/board/xilinx/versal-net/cmds.c
new file mode 100644
index 0000000000..b18a71fe52
--- /dev/null
+++ b/board/xilinx/versal-net/cmds.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <cpu_func.h>
+#include <command.h>
+#include <common.h>
+#include <log.h>
+#include <memalign.h>
+#include <versalpl.h>
+#include <zynqmp_firmware.h>
+
+/**
+ * do_versalnet_load_pdi - Handle the "versalnet load pdi" command-line command
+ * @cmdtp:      Command data struct pointer
+ * @flag:       Command flag
+ * @argc:       Command-line argument count
+ * @argv:       Array of command-line arguments
+ *
+ * Processes the Versal NET load pdi command
+ *
+ * Return: return 0 on success, Error value if command fails.
+ * CMD_RET_USAGE incase of incorrect/missing parameters.
+ */
+static int do_versalnet_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
+				 char * const argv[])
+{
+	u32 buf_lo, buf_hi;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	ulong addr, *pdi_buf;
+	size_t len;
+	int ret;
+
+	if (argc != cmdtp->maxargs) {
+		debug("pdi_load: incorrect parameters passed\n");
+		return CMD_RET_USAGE;
+	}
+
+	addr = simple_strtol(argv[1], NULL, 16);
+	if (!addr) {
+		debug("pdi_load: zero pdi_data address\n");
+		return CMD_RET_USAGE;
+	}
+
+	len = hextoul(argv[2], NULL);
+	if (!len) {
+		debug("pdi_load: zero size\n");
+		return CMD_RET_USAGE;
+	}
+
+	pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
+	if ((ulong)addr != (ulong)pdi_buf) {
+		memcpy((void *)pdi_buf, (void *)addr, len);
+		debug("Pdi addr:0x%lx aligned to 0x%lx\n",
+		      addr, (ulong)pdi_buf);
+	}
+
+	flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
+
+	buf_lo = lower_32_bits((ulong)pdi_buf);
+	buf_hi = upper_32_bits((ulong)pdi_buf);
+
+	ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
+				buf_hi, 0, ret_payload);
+	if (ret)
+		printf("PDI load failed with err: 0x%08x\n", ret);
+
+	return cmd_process_error(cmdtp, ret);
+}
+
+static char versalnet_help_text[] =
+	"loadpdi addr len - Load pdi image\n"
+	"load pdi image at ddr address 'addr' with pdi image size 'len'\n"
+;
+
+U_BOOT_CMD_WITH_SUBCMDS(versalnet, "Versal NET sub-system", versalnet_help_text,
+			U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1,
+					    do_versalnet_load_pdi));
diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile
index 4a46ca02d7..d912f2e74f 100644
--- a/board/xilinx/versal/Makefile
+++ b/board/xilinx/versal/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2016 - 2018 Xilinx, Inc.
-# Michal Simek <michal.simek@xilinx.com>
+# Michal Simek <michal.simek@amd.com>
 #
 
 obj-y	:= board.o
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 81e1b69905..60bf37d3c9 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2014 - 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <command.h>
diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c
index 797c1a5d68..148fa51266 100644
--- a/board/xilinx/versal/cmds.c
+++ b/board/xilinx/versal/cmds.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * (C) Copyright 2020 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <cpu_func.h>
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 9a59445b44..3b6581e304 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -5,6 +5,8 @@
  */
 
 #include <common.h>
+#include <debug_uart.h>
+#include <dfu.h>
 #include <init.h>
 #include <log.h>
 #include <dm/uclass.h>
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
index c2a6f9199a..602a789e77 100644
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -12408,7 +12408,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
 unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
 
 int
-ps7_post_config()
+ps7_post_config(void)
 {
   // Get the PS_VERSION on run time
   unsigned long si_ver = ps7GetSiliconVersion ();
@@ -12427,7 +12427,7 @@ ps7_post_config()
 }
 
 int
-ps7_init()
+ps7_init(void)
 {
   // Get the PS_VERSION on run time
   unsigned long si_ver = ps7GetSiliconVersion ();
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
index fd102a3ce4..9343683f4d 100644
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
@@ -12741,7 +12741,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
 unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
 
 int
-ps7_post_config()
+ps7_post_config(void)
 {
   // Get the PS_VERSION on run time
   unsigned long si_ver = ps7GetSiliconVersion ();
@@ -12760,7 +12760,7 @@ ps7_post_config()
 }
 
 int
-ps7_init()
+ps7_init(void)
 {
   // Get the PS_VERSION on run time
   unsigned long si_ver = ps7GetSiliconVersion ();
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
index 796e5b0c5f..6b153aa379 100644
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
@@ -12648,7 +12648,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
 unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
 
 int
-ps7_post_config()
+ps7_post_config(void)
 {
   // Get the PS_VERSION on run time
   unsigned long si_ver = ps7GetSiliconVersion ();
@@ -12667,7 +12667,7 @@ ps7_post_config()
 }
 
 int
-ps7_init()
+ps7_init(void)
 {
   // Get the PS_VERSION on run time
   unsigned long si_ver = ps7GetSiliconVersion ();
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
index baf89a5800..6f2edf16c2 100644
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
@@ -12306,7 +12306,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
 unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
 
 int
-ps7_post_config()
+ps7_post_config(void)
 {
   // Get the PS_VERSION on run time
   unsigned long si_ver = ps7GetSiliconVersion ();
@@ -12325,7 +12325,7 @@ ps7_post_config()
 }
 
 int
-ps7_init()
+ps7_init(void)
 {
   // Get the PS_VERSION on run time
   unsigned long si_ver = ps7GetSiliconVersion ();
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 732f909fc2..204e4fadf0 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2014 - 2016 Xilinx, Inc.
-# Michal Simek <michal.simek@xilinx.com>
+# Michal Simek <michal.simek@amd.com>
 
 obj-y	:= zynqmp.o
 
diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c
index e20030ecda..ea404d547f 100644
--- a/board/xilinx/zynqmp/cmds.c
+++ b/board/xilinx/zynqmp/cmds.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * (C) Copyright 2018 Xilinx, Inc.
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 #include <common.h>
@@ -187,6 +187,11 @@ static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc,
 	if (argc != cmdtp->maxargs)
 		return CMD_RET_USAGE;
 
+	if (strcmp(argv[2], "lockstep") && strcmp(argv[2], "split")) {
+		printf("mode param should be lockstep or split\n");
+		return CMD_RET_FAILURE;
+	}
+
 	mode = hextoul(argv[2], NULL);
 	if (mode != TCM_LOCK && mode != TCM_SPLIT) {
 		printf("Mode should be either 0(lock)/1(split)\n");
@@ -211,15 +216,24 @@ static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc,
 
 	if (!strncmp(argv[2], "node", 4)) {
 		u32 id;
+		int ret;
 
 		if (!strncmp(argv[3], "close", 5))
 			return zynqmp_pmufw_config_close();
 
 		id = dectoul(argv[3], NULL);
+		if (!id) {
+			printf("Incorrect ID passed\n");
+			return CMD_RET_USAGE;
+		}
 
 		printf("Enable permission for node ID %d\n", id);
 
-		return zynqmp_pmufw_node(id);
+		ret = zynqmp_pmufw_node(id);
+		if (ret == -ENODEV)
+			ret = 0;
+
+		return ret;
 	}
 
 	addr = hextoul(argv[2], NULL);
@@ -390,17 +404,17 @@ static int do_zynqmp(struct cmd_tbl *cmdtp, int flag, int argc,
 		     char *const argv[])
 {
 	struct cmd_tbl *c;
+	int ret = CMD_RET_USAGE;
 
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
 	c = find_cmd_tbl(argv[1], &cmd_zynqmp_sub[0],
 			 ARRAY_SIZE(cmd_zynqmp_sub));
-
 	if (c)
-		return c->cmd(c, flag, argc, argv);
-	else
-		return CMD_RET_USAGE;
+		ret = c->cmd(c, flag, argc, argv);
+
+	return cmd_process_error(c, ret);
 }
 
 /***************************************************/
@@ -429,7 +443,7 @@ static char zynqmp_help_text[] =
 	"		       lock(0)/split(1)\n"
 #endif
 	"zynqmp pmufw address size - load PMU FW configuration object\n"
-	"zynqmp pmufw node <id> - load PMU FW configuration object\n"
+	"zynqmp pmufw node <id> - load PMU FW configuration object, <id> in dec\n"
 	"zynqmp pmufw node close - disable config object loading\n"
 	"	node: keyword, id: NODE_ID in decimal format\n"
 	"zynqmp rsa srcaddr srclen mod exp rsaop -\n"
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 39da96bcfb..309f24a5f4 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #include <common.h>
diff --git a/boot/Kconfig b/boot/Kconfig
index a643a3d128..e8fb03b801 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -125,8 +125,7 @@ config FIT_BEST_MATCH
 config FIT_IMAGE_POST_PROCESS
 	bool "Enable post-processing of FIT artifacts after loading by U-Boot"
 	depends on FIT
-	depends on TI_SECURE_DEVICE || SOCFPGA_SECURE_VAB_AUTH
-	default y if TI_SECURE_DEVICE
+	depends on SOCFPGA_SECURE_VAB_AUTH
 	help
 	  Allows doing any sort of manipulation to blobs after they got extracted
 	  from FIT images like stripping off headers or modifying the size of the
@@ -463,6 +462,17 @@ config BOOTMETH_GLOBAL
 	  EFI bootmgr, since they take full control over which bootdevs are
 	  selected to boot.
 
+config BOOTMETH_CROS
+	bool "Bootdev support for Chromium OS"
+	depends on X86 || SANDBOX
+	default y
+	help
+	  Enables support for booting Chromium OS using bootdevs. This uses the
+	  kernel A slot and obtains the kernel command line from the parameters
+	  provided there.
+
+	  Note that only x86 devices are supported at present.
+
 config BOOTMETH_EXTLINUX
 	bool "Bootdev support for extlinux boot"
 	select PXE_UTILS
@@ -1630,4 +1640,18 @@ config SAVE_PREV_BL_INITRAMFS_START_ADDR
 	  If no initramfs was provided by previous bootloader, no env variables
 	  will be created.
 
+menu "Configuration editor"
+
+config CEDIT
+	bool "Configuration editor"
+	depends on BOOTSTD
+	help
+	  Provides a way to deal with board configuration and present it to
+	  the user for adjustment.
+
+	  This is intended to provide both graphical and text-based user
+	  interfaces, but only graphical is support at present.
+
+endmenu		# Configuration editor
+
 endmenu		# Booting
diff --git a/boot/Makefile b/boot/Makefile
index f94c31d922..10f0157223 100644
--- a/boot/Makefile
+++ b/boot/Makefile
@@ -27,12 +27,14 @@ obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootstd-uclass.o
 obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EXTLINUX) += bootmeth_extlinux.o
 obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EXTLINUX_PXE) += bootmeth_pxe.o
 obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EFILOADER) += bootmeth_efi.o
+obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_CROS) += bootmeth_cros.o
 obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SANDBOX) += bootmeth_sandbox.o
 obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SCRIPT) += bootmeth_script.o
 ifdef CONFIG_$(SPL_TPL_)BOOTSTD_FULL
 obj-$(CONFIG_CMD_BOOTEFI_BOOTMGR) += bootmeth_efi_mgr.o
 obj-$(CONFIG_$(SPL_TPL_)EXPO) += bootflow_menu.o
 obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootflow_menu.o
+obj-$(CONFIG_$(SPL_TPL_)CEDIT) += cedit.o
 endif
 
 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
@@ -50,7 +52,7 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o
 endif
 
-obj-$(CONFIG_$(SPL_TPL_)EXPO) += expo.o scene.o scene_menu.o
+obj-$(CONFIG_$(SPL_TPL_)EXPO) += expo.o scene.o scene_menu.o expo_build.o
 
 obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE) += vbe.o
 obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE_REQUEST) += vbe_request.o
diff --git a/boot/android_ab.c b/boot/android_ab.c
index 2d7b392666..73b55c196c 100644
--- a/boot/android_ab.c
+++ b/boot/android_ab.c
@@ -85,11 +85,13 @@ static int ab_control_default(struct bootloader_control *abc)
  */
 static int ab_control_create_from_disk(struct blk_desc *dev_desc,
 				       const struct disk_partition *part_info,
-				       struct bootloader_control **abc)
+				       struct bootloader_control **abc,
+				       ulong offset)
 {
 	ulong abc_offset, abc_blocks, ret;
 
-	abc_offset = offsetof(struct bootloader_message_ab, slot_suffix);
+	abc_offset = offset +
+		     offsetof(struct bootloader_message_ab, slot_suffix);
 	if (abc_offset % part_info->blksz) {
 		log_err("ANDROID: Boot control block not block aligned.\n");
 		return -EINVAL;
@@ -135,11 +137,12 @@ static int ab_control_create_from_disk(struct blk_desc *dev_desc,
  */
 static int ab_control_store(struct blk_desc *dev_desc,
 			    const struct disk_partition *part_info,
-			    struct bootloader_control *abc)
+			    struct bootloader_control *abc, ulong offset)
 {
 	ulong abc_offset, abc_blocks, ret;
 
-	abc_offset = offsetof(struct bootloader_message_ab, slot_suffix) /
+	abc_offset = offset +
+		     offsetof(struct bootloader_message_ab, slot_suffix) /
 		     part_info->blksz;
 	abc_blocks = DIV_ROUND_UP(sizeof(struct bootloader_control),
 				  part_info->blksz);
@@ -181,15 +184,19 @@ static int ab_compare_slots(const struct slot_metadata *a,
 	return 0;
 }
 
-int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info)
+int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info,
+		   bool dec_tries)
 {
 	struct bootloader_control *abc = NULL;
 	u32 crc32_le;
 	int slot, i, ret;
 	bool store_needed = false;
 	char slot_suffix[4];
+#if ANDROID_AB_BACKUP_OFFSET
+	struct bootloader_control *backup_abc = NULL;
+#endif
 
-	ret = ab_control_create_from_disk(dev_desc, part_info, &abc);
+	ret = ab_control_create_from_disk(dev_desc, part_info, &abc, 0);
 	if (ret < 0) {
 		/*
 		 * This condition represents an actual problem with the code or
@@ -199,22 +206,53 @@ int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info)
 		return ret;
 	}
 
+#if ANDROID_AB_BACKUP_OFFSET
+	ret = ab_control_create_from_disk(dev_desc, part_info, &backup_abc,
+					  ANDROID_AB_BACKUP_OFFSET);
+	if (ret < 0) {
+		free(abc);
+		return ret;
+	}
+#endif
+
 	crc32_le = ab_control_compute_crc(abc);
 	if (abc->crc32_le != crc32_le) {
 		log_err("ANDROID: Invalid CRC-32 (expected %.8x, found %.8x),",
 			crc32_le, abc->crc32_le);
-		log_err("re-initializing A/B metadata.\n");
-
-		ret = ab_control_default(abc);
-		if (ret < 0) {
-			free(abc);
-			return -ENODATA;
+#if ANDROID_AB_BACKUP_OFFSET
+		crc32_le = ab_control_compute_crc(backup_abc);
+		if (backup_abc->crc32_le != crc32_le) {
+			log_err("ANDROID: Invalid backup CRC-32 ")
+			log_err("expected %.8x, found %.8x),",
+				crc32_le, backup_abc->crc32_le);
+#endif
+
+			log_err("re-initializing A/B metadata.\n");
+
+			ret = ab_control_default(abc);
+			if (ret < 0) {
+#if ANDROID_AB_BACKUP_OFFSET
+				free(backup_abc);
+#endif
+				free(abc);
+				return -ENODATA;
+			}
+#if ANDROID_AB_BACKUP_OFFSET
+		} else {
+			/*
+			 * Backup is valid. Copy it to the primary
+			 */
+			memcpy(abc, backup_abc, sizeof(*abc));
 		}
+#endif
 		store_needed = true;
 	}
 
 	if (abc->magic != BOOT_CTRL_MAGIC) {
 		log_err("ANDROID: Unknown A/B metadata: %.8x\n", abc->magic);
+#if ANDROID_AB_BACKUP_OFFSET
+		free(backup_abc);
+#endif
 		free(abc);
 		return -ENODATA;
 	}
@@ -222,6 +260,9 @@ int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info)
 	if (abc->version > BOOT_CTRL_VERSION) {
 		log_err("ANDROID: Unsupported A/B metadata version: %.8x\n",
 			abc->version);
+#if ANDROID_AB_BACKUP_OFFSET
+		free(backup_abc);
+#endif
 		free(abc);
 		return -ENODATA;
 	}
@@ -272,8 +313,10 @@ int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info)
 		log_err("ANDROID: Attempting slot %c, tries remaining %d\n",
 			BOOT_SLOT_NAME(slot),
 			abc->slot_info[slot].tries_remaining);
-		abc->slot_info[slot].tries_remaining--;
-		store_needed = true;
+		if (dec_tries) {
+			abc->slot_info[slot].tries_remaining--;
+			store_needed = true;
+		}
 	}
 
 	if (slot >= 0) {
@@ -294,8 +337,21 @@ int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info)
 
 	if (store_needed) {
 		abc->crc32_le = ab_control_compute_crc(abc);
-		ab_control_store(dev_desc, part_info, abc);
+		ab_control_store(dev_desc, part_info, abc, 0);
 	}
+
+#if ANDROID_AB_BACKUP_OFFSET
+	/*
+	 * If the backup doesn't match the primary, write the primary
+	 * to the backup offset
+	 */
+	if (memcmp(backup_abc, abc, sizeof(*abc)) != 0) {
+		ab_control_store(dev_desc, part_info, abc,
+				 ANDROID_AB_BACKUP_OFFSET);
+	}
+	free(backup_abc);
+#endif
+
 	free(abc);
 
 	if (slot < 0)
diff --git a/boot/boot_fit.c b/boot/boot_fit.c
index 4a493b3684..9d39412656 100644
--- a/boot/boot_fit.c
+++ b/boot/boot_fit.c
@@ -67,7 +67,7 @@ void *locate_dtb_in_fit(const void *fit)
 	header = (struct legacy_img_hdr *)fit;
 
 	if (image_get_magic(header) != FDT_MAGIC) {
-		debug("No FIT image appended to U-boot\n");
+		debug("No FIT image appended to U-Boot\n");
 		return NULL;
 	}
 
diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c
index 9660ff7567..fa52bc3a9c 100644
--- a/boot/bootdev-uclass.c
+++ b/boot/bootdev-uclass.c
@@ -216,7 +216,7 @@ void bootdev_list(bool probe)
 	for (i = 0; dev; i++) {
 		printf("%3x   [ %c ]  %6s  %-9.9s %s\n", dev_seq(dev),
 		       device_active(dev) ? '+' : ' ',
-		       ret ? simple_itoa(ret) : "OK",
+		       ret ? simple_itoa(-ret) : "OK",
 		       dev_get_uclass_name(dev_get_parent(dev)), dev->name);
 		if (probe)
 			ret = uclass_next_device_check(&dev);
@@ -262,7 +262,7 @@ static int bootdev_get_suffix_start(struct udevice *dev, const char *suffix)
 	return len;
 }
 
-int bootdev_setup_sibling_blk(struct udevice *blk, const char *drv_name)
+int bootdev_setup_for_sibling_blk(struct udevice *blk, const char *drv_name)
 {
 	struct udevice *parent, *dev;
 	char dev_name[50];
@@ -305,7 +305,9 @@ int bootdev_get_sibling_blk(struct udevice *dev, struct udevice **blkp)
 	if (device_get_uclass_id(dev) != UCLASS_BOOTDEV)
 		return -EINVAL;
 
-	/* This should always work if bootdev_setup_sibling_blk() was used */
+	/*
+	 * This should always work if bootdev_setup_for_sibling_blk() was used
+	 */
 	len = bootdev_get_suffix_start(dev, ".bootdev");
 	ret = device_find_child_by_namelen(parent, dev->name, len, &blk);
 	if (ret) {
@@ -335,7 +337,7 @@ static int bootdev_get_from_blk(struct udevice *blk, struct udevice **bootdevp)
 	if (device_get_uclass_id(blk) != UCLASS_BLK)
 		return -EINVAL;
 
-	/* This should always work if bootdev_setup_sibling_blk() was used */
+	/* This should always work if bootdev_setup_for_sibling_blk() was used */
 	len = bootdev_get_suffix_start(blk, ".blk");
 	snprintf(dev_name, sizeof(dev_name), "%.*s.%s", len, blk->name,
 		 "bootdev");
@@ -535,6 +537,8 @@ static int default_get_bootflow(struct udevice *dev, struct bootflow_iter *iter,
 	int ret;
 
 	ret = bootdev_get_sibling_blk(dev, &blk);
+	log_debug("sibling_blk ret=%d, blk=%s\n", ret,
+		  ret ? "(none)" : blk->name);
 	/*
 	 * If there is no media, indicate that no more partitions should be
 	 * checked
@@ -660,7 +664,8 @@ int bootdev_next_prio(struct bootflow_iter *iter, struct udevice **devp)
 				ret = bootdev_hunt_prio(iter->cur_prio,
 							iter->flags &
 							BOOTFLOWIF_SHOW);
-				log_debug("- hunt ret %d\n", ret);
+				log_debug("- bootdev_hunt_prio() ret %d\n",
+					  ret);
 				if (ret)
 					return log_msg_ret("hun", ret);
 			}
@@ -696,6 +701,7 @@ int bootdev_setup_iter(struct bootflow_iter *iter, const char *label,
 	/* hunt for any pre-scan devices */
 	if (iter->flags & BOOTFLOWIF_HUNT) {
 		ret = bootdev_hunt_prio(BOOTDEVP_1_PRE_SCAN, show);
+		log_debug("- bootdev_hunt_prio() ret %d\n", ret);
 		if (ret)
 			return log_msg_ret("pre", ret);
 	}
@@ -766,6 +772,7 @@ static int bootdev_hunt_drv(struct bootdev_hunter *info, uint seq, bool show)
 		log_debug("Hunting with: %s\n", name);
 		if (info->hunt) {
 			ret = info->hunt(info, show);
+			log_debug("  - hunt result %d\n", ret);
 			if (ret)
 				return ret;
 		}
@@ -831,9 +838,11 @@ int bootdev_hunt_prio(enum bootdev_prio_t prio, bool show)
 		if (prio != info->prio)
 			continue;
 		ret = bootdev_hunt_drv(info, i, show);
+		log_debug("bootdev_hunt_drv() return %d\n", ret);
 		if (ret && ret != -ENOENT)
 			result = ret;
 	}
+	log_debug("exit %d\n", result);
 
 	return result;
 }
diff --git a/boot/bootflow.c b/boot/bootflow.c
index 8f2cb876bb..81b5829d5b 100644
--- a/boot/bootflow.c
+++ b/boot/bootflow.c
@@ -12,7 +12,9 @@
 #include <bootmeth.h>
 #include <bootstd.h>
 #include <dm.h>
+#include <env_internal.h>
 #include <malloc.h>
+#include <serial.h>
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
 
@@ -315,14 +317,14 @@ static int bootflow_check(struct bootflow_iter *iter, struct bootflow *bflow)
 
 	/* If we got a valid bootflow, return it */
 	if (!ret) {
-		log_debug("Bootdevice '%s' part %d method '%s': Found bootflow\n",
+		log_debug("Bootdev '%s' part %d method '%s': Found bootflow\n",
 			  dev->name, iter->part, iter->method->name);
 		return 0;
 	}
 
 	/* Unless there is nothing more to try, move to the next device */
 	else if (ret != BF_NO_MORE_PARTS && ret != -ENOSYS) {
-		log_debug("Bootdevice '%s' part %d method '%s': Error %d\n",
+		log_debug("Bootdev '%s' part %d method '%s': Error %d\n",
 			  dev->name, iter->part, iter->method->name, ret);
 		/*
 		 * For 'all' we return all bootflows, even
@@ -552,3 +554,336 @@ int bootflow_iter_check_system(const struct bootflow_iter *iter)
 
 	return -ENOTSUPP;
 }
+
+/**
+ * bootflow_cmdline_set() - Set the command line for a bootflow
+ *
+ * @value: New command-line string
+ * Returns 0 if OK, -ENOENT if no current bootflow, -ENOMEM if out of memory
+ */
+int bootflow_cmdline_set(struct bootflow *bflow, const char *value)
+{
+	char *cmdline = NULL;
+
+	if (value) {
+		cmdline = strdup(value);
+		if (!cmdline)
+			return -ENOMEM;
+	}
+
+	free(bflow->cmdline);
+	bflow->cmdline = cmdline;
+
+	return 0;
+}
+
+#ifdef CONFIG_BOOTSTD_FULL
+/**
+ * on_bootargs() - Update the cmdline of a bootflow
+ */
+static int on_bootargs(const char *name, const char *value, enum env_op op,
+		       int flags)
+{
+	struct bootstd_priv *std;
+	struct bootflow *bflow;
+	int ret;
+
+	ret = bootstd_get_priv(&std);
+	if (ret)
+		return 0;
+	bflow = std->cur_bootflow;
+	if (!bflow)
+		return 0;
+
+	switch (op) {
+	case env_op_create:
+	case env_op_overwrite:
+		ret = bootflow_cmdline_set(bflow, value);
+		if (ret && ret != ENOENT)
+			return 1;
+		return 0;
+	case env_op_delete:
+		bootflow_cmdline_set(bflow, NULL);
+		fallthrough;
+	default:
+		return 0;
+	}
+}
+U_BOOT_ENV_CALLBACK(bootargs, on_bootargs);
+#endif
+
+/**
+ * copy_in() - Copy a string into a cmdline buffer
+ *
+ * @buf: Buffer to copy into
+ * @end: End of buffer (pointer to char after the end)
+ * @arg: String to copy from
+ * @len: Number of chars to copy from @arg (note that this is not usually the
+ * sane as strlen(arg) since the string may contain following arguments)
+ * @new_val: Value to put after arg, or BOOTFLOWCL_EMPTY to use an empty value
+ * with no '=' sign
+ * Returns: Number of chars written to @buf
+ */
+static int copy_in(char *buf, char *end, const char *arg, int len,
+		   const char *new_val)
+{
+	char *to = buf;
+
+	/* copy the arg name */
+	if (to + len >= end)
+		return -E2BIG;
+	memcpy(to, arg, len);
+	to += len;
+
+	if (new_val == BOOTFLOWCL_EMPTY) {
+		/* no value */
+	} else {
+		bool need_quote = strchr(new_val, ' ');
+		len = strlen(new_val);
+
+		/* need space for value, equals sign and maybe two quotes */
+		if (to + 1 + (need_quote ? 2 : 0) + len >= end)
+			return -E2BIG;
+		*to++ = '=';
+		if (need_quote)
+			*to++ = '"';
+		memcpy(to, new_val, len);
+		to += len;
+		if (need_quote)
+			*to++ = '"';
+	}
+
+	return to - buf;
+}
+
+int cmdline_set_arg(char *buf, int maxlen, const char *cmdline,
+		    const char *set_arg, const char *new_val, int *posp)
+{
+	bool found_arg = false;
+	const char *from;
+	char *to, *end;
+	int set_arg_len;
+	char empty = '\0';
+	int ret;
+
+	from = cmdline ?: &empty;
+
+	/* check if the value has quotes inside */
+	if (new_val && new_val != BOOTFLOWCL_EMPTY && strchr(new_val, '"'))
+		return -EBADF;
+
+	set_arg_len = strlen(set_arg);
+	for (to = buf, end = buf + maxlen; *from;) {
+		const char *val, *arg_end, *val_end, *p;
+		bool in_quote;
+
+		if (to >= end)
+			return -E2BIG;
+		while (*from == ' ')
+			from++;
+		if (!*from)
+			break;
+
+		/* find the end of this arg */
+		val = NULL;
+		arg_end = NULL;
+		val_end = NULL;
+		in_quote = false;
+		for (p = from;; p++) {
+			if (in_quote) {
+				if (!*p)
+					return -EINVAL;
+				if (*p == '"')
+					in_quote = false;
+				continue;
+			}
+			if (*p == '=') {
+				arg_end = p;
+				val = p + 1;
+			} else if (*p == '"') {
+				in_quote = true;
+			} else if (!*p || *p == ' ') {
+				val_end = p;
+				if (!arg_end)
+					arg_end = p;
+				break;
+			}
+		}
+		/*
+		 * At this point val_end points to the end of the value, or the
+		 * last char after the arg name, if there is no label.
+		 * arg_end is the char after the arg name
+		 * val points to the value, or NULL if there is none
+		 * char after the value.
+		 *
+		 *        fred=1234
+		 *        ^   ^^   ^
+		 *      from  ||   |
+		 *           / \    \
+		 *    arg_end  val   val_end
+		 */
+		log_debug("from %s arg_end %ld val %ld val_end %ld\n", from,
+			  (long)(arg_end - from), (long)(val - from),
+			  (long)(val_end - from));
+
+		if (to != buf) {
+			if (to >= end)
+				return -E2BIG;
+			*to++ = ' ';
+		}
+
+		/* if this is the target arg, update it */
+		if (!strncmp(from, set_arg, arg_end - from)) {
+			if (!buf) {
+				bool has_quote = val_end[-1] == '"';
+
+				/*
+				 * exclude any start/end quotes from
+				 * calculations
+				 */
+				if (!val)
+					val = val_end;
+				*posp = val - cmdline + has_quote;
+				return val_end - val - 2 * has_quote;
+			}
+			found_arg = true;
+			if (!new_val) {
+				/* delete this arg */
+				from = val_end + (*val_end == ' ');
+				log_debug("delete from: %s\n", from);
+				if (to != buf)
+					to--; /* drop the space we added */
+				continue;
+			}
+
+			ret = copy_in(to, end, from, arg_end - from, new_val);
+			if (ret < 0)
+				return ret;
+			to += ret;
+
+		/* if not the target arg, copy it unchanged */
+		} else if (to) {
+			int len;
+
+			len = val_end - from;
+			if (to + len >= end)
+				return -E2BIG;
+			memcpy(to, from, len);
+			to += len;
+		}
+		from = val_end;
+	}
+
+	/* If we didn't find the arg, add it */
+	if (!found_arg) {
+		/* trying to delete something that is not there */
+		if (!new_val || !buf)
+			return -ENOENT;
+		if (to >= end)
+			return -E2BIG;
+
+		/* add a space to separate it from the previous arg */
+		if (to != buf && to[-1] != ' ')
+			*to++ = ' ';
+		ret = copy_in(to, end, set_arg, set_arg_len, new_val);
+		log_debug("ret=%d, to: %s buf: %s\n", ret, to, buf);
+		if (ret < 0)
+			return ret;
+		to += ret;
+	}
+
+	/* delete any trailing space */
+	if (to > buf && to[-1] == ' ')
+		to--;
+
+	if (to >= end)
+		return -E2BIG;
+	*to++ = '\0';
+
+	return to - buf;
+}
+
+int bootflow_cmdline_set_arg(struct bootflow *bflow, const char *set_arg,
+			     const char *new_val, bool set_env)
+{
+	char buf[2048];
+	char *cmd = NULL;
+	int ret;
+
+	ret = cmdline_set_arg(buf, sizeof(buf), bflow->cmdline, set_arg,
+			      new_val, NULL);
+	if (ret < 0)
+		return ret;
+
+	ret = bootflow_cmdline_set(bflow, buf);
+	if (*buf) {
+		cmd = strdup(buf);
+		if (!cmd)
+			return -ENOMEM;
+	}
+	free(bflow->cmdline);
+	bflow->cmdline = cmd;
+
+	if (set_env) {
+		ret = env_set("bootargs", bflow->cmdline);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int cmdline_get_arg(const char *cmdline, const char *arg, int *posp)
+{
+	int ret;
+
+	ret = cmdline_set_arg(NULL, 1, cmdline, arg, NULL, posp);
+
+	return ret;
+}
+
+int bootflow_cmdline_get_arg(struct bootflow *bflow, const char *arg,
+			     const char **val)
+{
+	int ret;
+	int pos;
+
+	ret = cmdline_get_arg(bflow->cmdline, arg, &pos);
+	if (ret < 0)
+		return ret;
+	*val = bflow->cmdline + pos;
+
+	return ret;
+}
+
+int bootflow_cmdline_auto(struct bootflow *bflow, const char *arg)
+{
+	struct serial_device_info info;
+	char buf[50];
+	int ret;
+
+	ret = serial_getinfo(gd->cur_serial_dev, &info);
+	if (ret)
+		return ret;
+
+	*buf = '\0';
+	if (!strcmp("earlycon", arg)) {
+		snprintf(buf, sizeof(buf),
+			 "uart8250,mmio32,%#lx,%dn8", info.addr,
+			 info.baudrate);
+	} else if (!strcmp("console", arg)) {
+		snprintf(buf, sizeof(buf),
+			 "ttyS0,%dn8", info.baudrate);
+	}
+
+	if (!*buf) {
+		printf("Unknown param '%s\n", arg);
+		return -ENOENT;
+	}
+
+	ret = bootflow_cmdline_set_arg(bflow, arg, buf, true);
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c
index 7f06dac0af..7c1abe5772 100644
--- a/boot/bootflow_menu.c
+++ b/boot/bootflow_menu.c
@@ -124,6 +124,10 @@ int bootflow_menu_new(struct expo **expp)
 		priv->num_bootflows++;
 	}
 
+	ret = scene_arrange(scn);
+	if (ret)
+		return log_msg_ret("arr", ret);
+
 	*expp = exp;
 
 	return 0;
@@ -205,7 +209,7 @@ int bootflow_menu_run(struct bootstd_priv *std, bool text_mode,
 		return log_msg_ret("scn", ret);
 
 	if (text_mode)
-		exp_set_text_mode(exp, text_mode);
+		expo_set_text_mode(exp, text_mode);
 
 	done = false;
 	do {
diff --git a/boot/bootmeth-uclass.c b/boot/bootmeth-uclass.c
index 3b3e0614da..175eb1de5e 100644
--- a/boot/bootmeth-uclass.c
+++ b/boot/bootmeth-uclass.c
@@ -240,18 +240,7 @@ int bootmeth_set_order(const char *order_str)
 	return 0;
 }
 
-/**
- * setup_fs() - Set up read to read a file
- *
- * We must redo the setup before each filesystem operation. This function
- * handles that, including setting the filesystem type if a block device is not
- * being used
- *
- * @bflow: Information about file to try
- * @desc: Block descriptor to read from (NULL if not a block device)
- * Return: 0 if OK, -ve on error
- */
-static int setup_fs(struct bootflow *bflow, struct blk_desc *desc)
+int bootmeth_setup_fs(struct bootflow *bflow, struct blk_desc *desc)
 {
 	int ret;
 
@@ -288,7 +277,7 @@ int bootmeth_try_file(struct bootflow *bflow, struct blk_desc *desc,
 	log_debug("   %s - err=%d\n", path, ret);
 
 	/* Sadly FS closes the file after fs_size() so we must redo this */
-	ret2 = setup_fs(bflow, desc);
+	ret2 = bootmeth_setup_fs(bflow, desc);
 	if (ret2)
 		return log_msg_ret("fs", ret2);
 
@@ -301,32 +290,6 @@ int bootmeth_try_file(struct bootflow *bflow, struct blk_desc *desc,
 	return 0;
 }
 
-static int alloc_file(const char *fname, uint size, void **bufp)
-{
-	loff_t bytes_read;
-	ulong addr;
-	char *buf;
-	int ret;
-
-	buf = malloc(size + 1);
-	if (!buf)
-		return log_msg_ret("buf", -ENOMEM);
-	addr = map_to_sysmem(buf);
-
-	ret = fs_read(fname, addr, 0, size, &bytes_read);
-	if (ret) {
-		free(buf);
-		return log_msg_ret("read", ret);
-	}
-	if (size != bytes_read)
-		return log_msg_ret("bread", -EIO);
-	buf[size] = '\0';
-
-	*bufp = buf;
-
-	return 0;
-}
-
 int bootmeth_alloc_file(struct bootflow *bflow, uint size_limit, uint align)
 {
 	void *buf;
@@ -338,7 +301,7 @@ int bootmeth_alloc_file(struct bootflow *bflow, uint size_limit, uint align)
 	if (size > size_limit)
 		return log_msg_ret("chk", -E2BIG);
 
-	ret = alloc_file(bflow->fname, bflow->size, &buf);
+	ret = fs_read_alloc(bflow->fname, bflow->size, align, &buf);
 	if (ret)
 		return log_msg_ret("all", ret);
 
@@ -363,18 +326,18 @@ int bootmeth_alloc_other(struct bootflow *bflow, const char *fname,
 	if (bflow->blk)
 		desc = dev_get_uclass_plat(bflow->blk);
 
-	ret = setup_fs(bflow, desc);
+	ret = bootmeth_setup_fs(bflow, desc);
 	if (ret)
 		return log_msg_ret("fs", ret);
 
 	ret = fs_size(path, &size);
 	log_debug("   %s - err=%d\n", path, ret);
 
-	ret = setup_fs(bflow, desc);
+	ret = bootmeth_setup_fs(bflow, desc);
 	if (ret)
 		return log_msg_ret("fs", ret);
 
-	ret = alloc_file(path, size, &buf);
+	ret = fs_read_alloc(path, size, 0, &buf);
 	if (ret)
 		return log_msg_ret("all", ret);
 
@@ -395,7 +358,7 @@ int bootmeth_common_read_file(struct udevice *dev, struct bootflow *bflow,
 	if (bflow->blk)
 		desc = dev_get_uclass_plat(bflow->blk);
 
-	ret = setup_fs(bflow, desc);
+	ret = bootmeth_setup_fs(bflow, desc);
 	if (ret)
 		return log_msg_ret("fs", ret);
 
@@ -405,7 +368,7 @@ int bootmeth_common_read_file(struct udevice *dev, struct bootflow *bflow,
 	if (size > *sizep)
 		return log_msg_ret("spc", -ENOSPC);
 
-	ret = setup_fs(bflow, desc);
+	ret = bootmeth_setup_fs(bflow, desc);
 	if (ret)
 		return log_msg_ret("fs", ret);
 
@@ -421,7 +384,7 @@ int bootmeth_common_read_file(struct udevice *dev, struct bootflow *bflow,
 /**
  * on_bootmeths() - Update the bootmeth order
  *
- * This will check for a valid baudrate and only apply it if valid.
+ * This will check for a valid list of bootmeths and only apply it if valid.
  */
 static int on_bootmeths(const char *name, const char *value, enum env_op op,
 			int flags)
diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c
new file mode 100644
index 0000000000..aa19ae097f
--- /dev/null
+++ b/boot/bootmeth_cros.c
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Bootmethod for ChromiumOS
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_BOOTSTD
+
+#include <common.h>
+#include <blk.h>
+#include <bootdev.h>
+#include <bootflow.h>
+#include <bootmeth.h>
+#include <dm.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <part.h>
+#ifdef CONFIG_X86
+#include <asm/zimage.h>
+#endif
+#include <linux/sizes.h>
+
+enum {
+	/* Offsets in the kernel-partition header */
+	KERN_START	= 0x4f0,
+	KERN_SIZE	= 0x518,
+
+	SETUP_OFFSET	= 0x1000,	/* bytes before base */
+	CMDLINE_OFFSET	= 0x2000,	/* bytes before base */
+	OFFSET_BASE	= 0x100000,	/* assumed kernel load-address */
+};
+
+static int cros_check(struct udevice *dev, struct bootflow_iter *iter)
+{
+	/* This only works on block and network devices */
+	if (bootflow_iter_check_blk(iter))
+		return log_msg_ret("blk", -ENOTSUPP);
+
+	return 0;
+}
+
+static int copy_cmdline(const char *from, const char *uuid, char **bufp)
+{
+	const int maxlen = 2048;
+	char buf[maxlen];
+	char *cmd, *to, *end;
+	int len;
+
+	/* Allow space for cmdline + UUID */
+	len = strnlen(from, sizeof(buf));
+	if (len >= maxlen)
+		return -E2BIG;
+
+	log_debug("uuid %d %s\n", uuid ? (int)strlen(uuid) : 0, uuid);
+	for (to = buf, end = buf + maxlen - UUID_STR_LEN - 1; *from; from++) {
+		if (to >= end)
+			return -E2BIG;
+		if (from[0] == '%' && from[1] == 'U' && uuid &&
+		    strlen(uuid) == UUID_STR_LEN) {
+			strcpy(to, uuid);
+			to += UUID_STR_LEN;
+			from++;
+		} else {
+			*to++ = *from;
+		}
+	}
+	*to = '\0';
+	len = to - buf;
+	cmd = strdup(buf);
+	if (!cmd)
+		return -ENOMEM;
+	free(*bufp);
+	*bufp = cmd;
+
+	return 0;
+}
+
+static int cros_read_bootflow(struct udevice *dev, struct bootflow *bflow)
+{
+	struct blk_desc *desc = dev_get_uclass_plat(bflow->blk);
+	ulong base, start, size, setup, cmdline, num_blks, kern_base;
+	struct disk_partition info;
+	const char *uuid = NULL;
+	void *buf, *hdr;
+	int ret;
+
+	log_debug("starting, part=%d\n", bflow->part);
+
+	/* We consider the whole disk, not any one partition */
+	if (bflow->part)
+		return log_msg_ret("max", -ENOENT);
+
+	/* Check partition 2 */
+	ret = part_get_info(desc, 2, &info);
+	if (ret)
+		return log_msg_ret("part", ret);
+
+	/* Make a buffer for the header information */
+	num_blks = SZ_4K >> desc->log2blksz;
+	log_debug("Reading header, blk=%s, start=%lx, blocks=%lx\n",
+		  bflow->blk->name, (ulong)info.start, num_blks);
+	hdr = memalign(SZ_1K, SZ_4K);
+	if (!hdr)
+		return log_msg_ret("hdr", -ENOMEM);
+	ret = blk_read(bflow->blk, info.start, num_blks, hdr);
+	if (ret != num_blks)
+		return log_msg_ret("inf", ret);
+
+	if (memcmp("CHROMEOS", hdr, 8))
+		return -ENOENT;
+
+	log_info("Header at %lx\n", (ulong)map_to_sysmem(hdr));
+	start = *(u32 *)(hdr + KERN_START);
+	size = ALIGN(*(u32 *)(hdr + KERN_SIZE), desc->blksz);
+	log_debug("Reading start %lx size %lx\n", start, size);
+	bflow->size = size;
+
+	buf = memalign(SZ_1K, size);
+	if (!buf)
+		return log_msg_ret("buf", -ENOMEM);
+	num_blks = size >> desc->log2blksz;
+	log_debug("Reading data, blk=%s, start=%lx, blocks=%lx\n",
+		  bflow->blk->name, (ulong)info.start, num_blks);
+	ret = blk_read(bflow->blk, (ulong)info.start + 0x80, num_blks, buf);
+	if (ret != num_blks)
+		return log_msg_ret("inf", ret);
+	base = map_to_sysmem(buf);
+
+	setup = base + start - OFFSET_BASE - SETUP_OFFSET;
+	cmdline = base + start - OFFSET_BASE - CMDLINE_OFFSET;
+	kern_base = base + start - OFFSET_BASE + SZ_16K;
+	log_debug("base %lx setup %lx, cmdline %lx, kern_base %lx\n", base,
+		  setup, cmdline, kern_base);
+
+#ifdef CONFIG_X86
+	const char *version;
+
+	version = zimage_get_kernel_version(map_sysmem(setup, 0),
+					    map_sysmem(kern_base, 0));
+	log_debug("version %s\n", version);
+	if (version)
+		bflow->name = strdup(version);
+#endif
+	if (!bflow->name)
+		bflow->name = strdup("ChromeOS");
+	if (!bflow->name)
+		return log_msg_ret("nam", -ENOMEM);
+	bflow->os_name = strdup("ChromeOS");
+	if (!bflow->os_name)
+		return log_msg_ret("os", -ENOMEM);
+
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+	uuid = info.uuid;
+#endif
+	ret = copy_cmdline(map_sysmem(cmdline, 0), uuid, &bflow->cmdline);
+	if (ret)
+		return log_msg_ret("cmd", ret);
+
+	bflow->state = BOOTFLOWST_READY;
+	bflow->buf = buf;
+	bflow->x86_setup = map_sysmem(setup, 0);
+
+	return 0;
+}
+
+static int cros_read_file(struct udevice *dev, struct bootflow *bflow,
+			 const char *file_path, ulong addr, ulong *sizep)
+{
+	return -ENOSYS;
+}
+
+static int cros_boot(struct udevice *dev, struct bootflow *bflow)
+{
+#ifdef CONFIG_X86
+	zboot_start(map_to_sysmem(bflow->buf), bflow->size, 0, 0,
+		    map_to_sysmem(bflow->x86_setup),
+		    bflow->cmdline);
+#endif
+
+	return log_msg_ret("go", -EFAULT);
+}
+
+static int cros_bootmeth_bind(struct udevice *dev)
+{
+	struct bootmeth_uc_plat *plat = dev_get_uclass_plat(dev);
+
+	plat->desc = "ChromiumOS boot";
+
+	return 0;
+}
+
+static struct bootmeth_ops cros_bootmeth_ops = {
+	.check		= cros_check,
+	.read_bootflow	= cros_read_bootflow,
+	.read_file	= cros_read_file,
+	.boot		= cros_boot,
+};
+
+static const struct udevice_id cros_bootmeth_ids[] = {
+	{ .compatible = "u-boot,cros" },
+	{ }
+};
+
+U_BOOT_DRIVER(bootmeth_cros) = {
+	.name		= "bootmeth_cros",
+	.id		= UCLASS_BOOTMETH,
+	.of_match	= cros_bootmeth_ids,
+	.ops		= &cros_bootmeth_ops,
+	.bind		= cros_bootmeth_bind,
+};
diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
index af31fbfc85..ae936c8daa 100644
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -21,6 +21,7 @@
 #include <mmc.h>
 #include <net.h>
 #include <pxe_utils.h>
+#include <linux/sizes.h>
 
 #define EFI_DIRNAME	"efi/boot/"
 
@@ -94,6 +95,20 @@ static int get_efi_pxe_vci(char *str, int max_len)
 	return 0;
 }
 
+/**
+ * bootmeth_uses_network() - check if the media device is Ethernet
+ *
+ * @bflow: Bootflow to check
+ * Returns: true if the media device is Ethernet, else false
+ */
+static bool bootmeth_uses_network(struct bootflow *bflow)
+{
+	const struct udevice *media = dev_get_parent(bflow->dev);
+
+	return IS_ENABLED(CONFIG_CMD_DHCP) &&
+	    device_get_uclass_id(media) == UCLASS_ETH;
+}
+
 static void set_efi_bootdev(struct blk_desc *desc, struct bootflow *bflow)
 {
 	const struct udevice *media_dev;
@@ -129,13 +144,24 @@ static void set_efi_bootdev(struct blk_desc *desc, struct bootflow *bflow)
 	efi_set_bootdev(dev_name, devnum_str, bflow->fname, bflow->buf, size);
 }
 
-static int efiload_read_file(struct blk_desc *desc, struct bootflow *bflow)
+static int efiload_read_file(struct bootflow *bflow, ulong addr)
 {
+	struct blk_desc *desc = NULL;
+	loff_t bytes_read;
 	int ret;
 
-	ret = bootmeth_alloc_file(bflow, 0x2000000, 0x10000);
+	if (bflow->blk)
+		 desc = dev_get_uclass_plat(bflow->blk);
+	ret = bootmeth_setup_fs(bflow, desc);
+	if (ret)
+		return log_msg_ret("set", ret);
+
+	ret = fs_read(bflow->fname, addr, 0, bflow->size, &bytes_read);
 	if (ret)
 		return log_msg_ret("read", ret);
+	bflow->buf = map_sysmem(addr, bflow->size);
+
+	set_efi_bootdev(desc, bflow);
 
 	return 0;
 }
@@ -209,7 +235,18 @@ static int distro_efi_get_fdt_name(char *fname, int size, int seq)
 	return 0;
 }
 
-static int distro_efi_read_bootflow_file(struct udevice *dev,
+/*
+ * distro_efi_try_bootflow_files() - Check that files are present
+ *
+ * This reads any FDT file and checks whether the bootflow file is present, for
+ * later reading. We avoid reading the bootflow now, since it is likely large,
+ * it may take a long time and we want to avoid needing to allocate memory for
+ * it
+ *
+ * @dev: bootmeth device to use
+ * @bflow: bootflow to update
+ */
+static int distro_efi_try_bootflow_files(struct udevice *dev,
 					 struct bootflow *bflow)
 {
 	struct blk_desc *desc = NULL;
@@ -233,9 +270,8 @@ static int distro_efi_read_bootflow_file(struct udevice *dev,
 	if (ret)
 		return log_msg_ret("try", ret);
 
-	ret = efiload_read_file(desc, bflow);
-	if (ret)
-		return log_msg_ret("read", ret);
+	/* Since we can access the file, let's call it ready */
+	bflow->state = BOOTFLOWST_READY;
 
 	fdt_addr = env_get_hex("fdt_addr_r", 0);
 
@@ -246,9 +282,12 @@ static int distro_efi_read_bootflow_file(struct udevice *dev,
 		ret = distro_efi_get_fdt_name(fname, sizeof(fname), seq);
 		if (ret == -EALREADY)
 			bflow->flags = BOOTFLOWF_USE_PRIOR_FDT;
-		if (!ret)
+		if (!ret) {
+			/* Limit FDT files to 4MB */
+			size = SZ_4M;
 			ret = bootmeth_common_read_file(dev, bflow, fname,
 							fdt_addr, &size);
+		}
 	}
 
 	if (*fname) {
@@ -354,17 +393,15 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow)
 
 static int distro_efi_read_bootflow(struct udevice *dev, struct bootflow *bflow)
 {
-	const struct udevice *media = dev_get_parent(bflow->dev);
 	int ret;
 
-	if (IS_ENABLED(CONFIG_CMD_DHCP) &&
-	    device_get_uclass_id(media) == UCLASS_ETH) {
+	if (bootmeth_uses_network(bflow)) {
 		/* we only support reading from one device, so ignore 'dev' */
 		ret = distro_efi_read_bootflow_net(bflow);
 		if (ret)
 			return log_msg_ret("net", ret);
 	} else {
-		ret = distro_efi_read_bootflow_file(dev, bflow);
+		ret = distro_efi_try_bootflow_files(dev, bflow);
 		if (ret)
 			return log_msg_ret("blk", ret);
 	}
@@ -372,21 +409,17 @@ static int distro_efi_read_bootflow(struct udevice *dev, struct bootflow *bflow)
 	return 0;
 }
 
-int distro_efi_boot(struct udevice *dev, struct bootflow *bflow)
+static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow)
 {
 	ulong kernel, fdt;
 	char cmd[50];
+	int ret;
 
-	/* A non-zero buffer indicates the kernel is there */
-	if (bflow->buf) {
-		/* Set the EFI bootdev again, since reading an FDT loses it! */
-		if (bflow->blk) {
-			struct blk_desc *desc = dev_get_uclass_plat(bflow->blk);
-
-			set_efi_bootdev(desc, bflow);
-		}
-
-		kernel = (ulong)map_to_sysmem(bflow->buf);
+	kernel = env_get_hex("kernel_addr_r", 0);
+	if (!bootmeth_uses_network(bflow)) {
+		ret = efiload_read_file(bflow, kernel);
+		if (ret)
+			return log_msg_ret("read", ret);
 
 		/*
 		 * use the provided device tree if available, else fall back to
@@ -405,7 +438,6 @@ int distro_efi_boot(struct udevice *dev, struct bootflow *bflow)
 		 * But this is the same behaviour for distro boot, so it can be
 		 * fixed here.
 		 */
-		kernel = env_get_hex("kernel_addr_r", 0);
 		fdt = env_get_hex("fdt_addr_r", 0);
 	}
 
diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c
index ce986bd260..8d489a11aa 100644
--- a/boot/bootmeth_pxe.c
+++ b/boot/bootmeth_pxe.c
@@ -31,6 +31,9 @@ static int extlinux_pxe_getfile(struct pxe_context *ctx, const char *file_path,
 	int ret;
 
 	addr = simple_strtoul(file_addr, NULL, 16);
+
+	/* Allow up to 1GB */
+	*sizep = 1 << 30;
 	ret = bootmeth_read_file(info->dev, info->bflow, file_path, addr,
 				 sizep);
 	if (ret)
diff --git a/boot/bootmeth_qfw.c b/boot/bootmeth_qfw.c
index ecd4b082fd..8ebbc3ebcd 100644
--- a/boot/bootmeth_qfw.c
+++ b/boot/bootmeth_qfw.c
@@ -76,7 +76,7 @@ static int qfw_bootmeth_bind(struct udevice *dev)
 {
 	struct bootmeth_uc_plat *plat = dev_get_uclass_plat(dev);
 
-	plat->desc = "Sandbox boot for testing";
+	plat->desc = "QEMU boot using firmware interface";
 
 	return 0;
 }
diff --git a/boot/bootmeth_script.c b/boot/bootmeth_script.c
index 225eb18ee6..a4050c384d 100644
--- a/boot/bootmeth_script.c
+++ b/boot/bootmeth_script.c
@@ -190,7 +190,10 @@ static int script_boot(struct udevice *dev, struct bootflow *bflow)
 	ulong addr;
 	int ret;
 
-	ret = env_set("devtype", blk_get_devtype(bflow->blk));
+	if (desc->uclass_id == UCLASS_USB)
+		ret = env_set("devtype", "usb");
+	else
+		ret = env_set("devtype", blk_get_devtype(bflow->blk));
 	if (!ret)
 		ret = env_set_hex("devnum", desc->devnum);
 	if (!ret)
diff --git a/boot/cedit.c b/boot/cedit.c
new file mode 100644
index 0000000000..ee24658917
--- /dev/null
+++ b/boot/cedit.c
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Implementation of configuration editor
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <cli.h>
+#include <dm.h>
+#include <expo.h>
+#include <menu.h>
+#include <video.h>
+#include <linux/delay.h>
+#include "scene_internal.h"
+
+int cedit_arange(struct expo *exp, struct video_priv *vpriv, uint scene_id)
+{
+	struct scene_obj_txt *txt;
+	struct scene_obj *obj;
+	struct scene *scn;
+	int y;
+
+	scn = expo_lookup_scene_id(exp, scene_id);
+	if (!scn)
+		return log_msg_ret("scn", -ENOENT);
+
+	txt = scene_obj_find_by_name(scn, "prompt");
+	if (txt)
+		scene_obj_set_pos(scn, txt->obj.id, 0, vpriv->ysize - 50);
+
+	txt = scene_obj_find_by_name(scn, "title");
+	if (txt)
+		scene_obj_set_pos(scn, txt->obj.id, 200, 10);
+
+	y = 100;
+	list_for_each_entry(obj, &scn->obj_head, sibling) {
+		if (obj->type == SCENEOBJT_MENU) {
+			scene_obj_set_pos(scn, obj->id, 50, y);
+			scene_menu_arrange(scn, (struct scene_obj_menu *)obj);
+			y += 50;
+		}
+	}
+
+	return 0;
+}
+
+int cedit_run(struct expo *exp)
+{
+	struct cli_ch_state s_cch, *cch = &s_cch;
+	struct video_priv *vid_priv;
+	uint scene_id;
+	struct udevice *dev;
+	struct scene *scn;
+	bool done;
+	int ret;
+
+	cli_ch_init(cch);
+
+	/* For now we only support a video console */
+	ret = uclass_first_device_err(UCLASS_VIDEO, &dev);
+	if (ret)
+		return log_msg_ret("vid", ret);
+	ret = expo_set_display(exp, dev);
+	if (ret)
+		return log_msg_ret("dis", ret);
+
+	ret = expo_first_scene_id(exp);
+	if (ret < 0)
+		return log_msg_ret("scn", ret);
+	scene_id = ret;
+
+	ret = expo_set_scene_id(exp, scene_id);
+	if (ret)
+		return log_msg_ret("sid", ret);
+
+	exp->popup = true;
+
+	/* This is not supported for now */
+	if (0)
+		expo_set_text_mode(exp, true);
+
+	vid_priv = dev_get_uclass_priv(dev);
+
+	scn = expo_lookup_scene_id(exp, scene_id);
+	scene_highlight_first(scn);
+
+	cedit_arange(exp, vid_priv, scene_id);
+
+	ret = expo_calc_dims(exp);
+	if (ret)
+		return log_msg_ret("dim", ret);
+
+	done = false;
+	do {
+		struct expo_action act;
+		int ichar, key;
+
+		ret = expo_render(exp);
+		if (ret)
+			break;
+
+		ichar = cli_ch_process(cch, 0);
+		if (!ichar) {
+			while (!ichar && !tstc()) {
+				schedule();
+				mdelay(2);
+				ichar = cli_ch_process(cch, -ETIMEDOUT);
+			}
+			if (!ichar) {
+				ichar = getchar();
+				ichar = cli_ch_process(cch, ichar);
+			}
+		}
+
+		key = 0;
+		if (ichar) {
+			key = bootmenu_conv_key(ichar);
+			if (key == BKEY_NONE)
+				key = ichar;
+		}
+		if (!key)
+			continue;
+
+		ret = expo_send_key(exp, key);
+		if (ret)
+			break;
+
+		ret = expo_action_get(exp, &act);
+		if (!ret) {
+			switch (act.type) {
+			case EXPOACT_POINT_OBJ:
+				scene_set_highlight_id(scn, act.select.id);
+				cedit_arange(exp, vid_priv, scene_id);
+				break;
+			case EXPOACT_OPEN:
+				scene_set_open(scn, act.select.id, true);
+				cedit_arange(exp, vid_priv, scene_id);
+				break;
+			case EXPOACT_CLOSE:
+				scene_set_open(scn, act.select.id, false);
+				cedit_arange(exp, vid_priv, scene_id);
+				break;
+			case EXPOACT_SELECT:
+				scene_set_open(scn, scn->highlight_id, false);
+				cedit_arange(exp, vid_priv, scene_id);
+				break;
+			case EXPOACT_QUIT:
+				log_debug("quitting\n");
+				done = true;
+				break;
+			default:
+				break;
+			}
+		}
+	} while (!done);
+
+	if (ret)
+		return log_msg_ret("end", ret);
+
+	return 0;
+}
diff --git a/boot/expo.c b/boot/expo.c
index 05950a1760..db837f7b49 100644
--- a/boot/expo.c
+++ b/boot/expo.c
@@ -6,6 +6,8 @@
  * Written by Simon Glass <sjg@chromium.org>
  */
 
+#define LOG_CATEGORY	LOGC_EXPO
+
 #include <common.h>
 #include <dm.h>
 #include <expo.h>
@@ -54,6 +56,22 @@ void expo_destroy(struct expo *exp)
 	free(exp);
 }
 
+uint resolve_id(struct expo *exp, uint id)
+{
+	log_debug("resolve id %d\n", id);
+	if (!id)
+		id = exp->next_id++;
+	else if (id >= exp->next_id)
+		exp->next_id = id + 1;
+
+	return id;
+}
+
+void expo_set_dynamic_start(struct expo *exp, uint dyn_start)
+{
+	exp->next_id = dyn_start;
+}
+
 int expo_str(struct expo *exp, const char *name, uint id, const char *str)
 {
 	struct expo_string *estr;
@@ -83,12 +101,45 @@ const char *expo_get_str(struct expo *exp, uint id)
 
 int expo_set_display(struct expo *exp, struct udevice *dev)
 {
+	struct udevice *cons;
+	int ret;
+
+	ret = device_find_first_child_by_uclass(dev, UCLASS_VIDEO_CONSOLE,
+						&cons);
+	if (ret)
+		return log_msg_ret("con", ret);
+
 	exp->display = dev;
+	exp->cons = cons;
+
+	return 0;
+}
+
+int expo_calc_dims(struct expo *exp)
+{
+	struct scene *scn;
+	int ret;
+
+	if (!exp->cons)
+		return log_msg_ret("dim", -ENOTSUPP);
+
+	list_for_each_entry(scn, &exp->scene_head, sibling) {
+		/*
+		 * Do the menus last so that all the menus' text objects
+		 * are dimensioned
+		 */
+		ret = scene_calc_dims(scn, false);
+		if (ret)
+			return log_msg_ret("scn", ret);
+		ret = scene_calc_dims(scn, true);
+		if (ret)
+			return log_msg_ret("scn", ret);
+	}
 
 	return 0;
 }
 
-void exp_set_text_mode(struct expo *exp, bool text_mode)
+void expo_set_text_mode(struct expo *exp, bool text_mode)
 {
 	exp->text_mode = text_mode;
 }
@@ -107,13 +158,33 @@ struct scene *expo_lookup_scene_id(struct expo *exp, uint scene_id)
 
 int expo_set_scene_id(struct expo *exp, uint scene_id)
 {
-	if (!expo_lookup_scene_id(exp, scene_id))
+	struct scene *scn;
+	int ret;
+
+	scn = expo_lookup_scene_id(exp, scene_id);
+	if (!scn)
 		return log_msg_ret("id", -ENOENT);
+	ret = scene_arrange(scn);
+	if (ret)
+		return log_msg_ret("arr", ret);
+
 	exp->scene_id = scene_id;
 
 	return 0;
 }
 
+int expo_first_scene_id(struct expo *exp)
+{
+	struct scene *scn;
+
+	if (list_empty(&exp->scene_head))
+		return -ENOENT;
+
+	scn = list_first_entry(&exp->scene_head, struct scene, sibling);
+
+	return scn->id;
+}
+
 int expo_render(struct expo *exp)
 {
 	struct udevice *dev = exp->display;
@@ -156,6 +227,11 @@ int expo_send_key(struct expo *exp, int key)
 		ret = scene_send_key(scn, key, &exp->action);
 		if (ret)
 			return log_msg_ret("key", ret);
+
+		/* arrange it to get any changes */
+		ret = scene_arrange(scn);
+		if (ret)
+			return log_msg_ret("arr", ret);
 	}
 
 	return scn ? 0 : -ECHILD;
@@ -168,3 +244,25 @@ int expo_action_get(struct expo *exp, struct expo_action *act)
 
 	return act->type == EXPOACT_NONE ? -EAGAIN : 0;
 }
+
+int expo_apply_theme(struct expo *exp, ofnode node)
+{
+	struct scene *scn;
+	struct expo_theme *theme = &exp->theme;
+	int ret;
+
+	log_debug("Applying theme %s\n", ofnode_get_name(node));
+
+	memset(theme, '\0', sizeof(struct expo_theme));
+	ofnode_read_u32(node, "font-size", &theme->font_size);
+	ofnode_read_u32(node, "menu-inset", &theme->menu_inset);
+	ofnode_read_u32(node, "menuitem-gap-y", &theme->menuitem_gap_y);
+
+	list_for_each_entry(scn, &exp->scene_head, sibling) {
+		ret = scene_apply_theme(scn, theme);
+		if (ret)
+			return log_msg_ret("app", ret);
+	}
+
+	return 0;
+}
diff --git a/boot/expo_build.c b/boot/expo_build.c
new file mode 100644
index 0000000000..22f62eb54b
--- /dev/null
+++ b/boot/expo_build.c
@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Building an expo from an FDT description
+ *
+ * Copyright 2022 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY	LOGC_EXPO
+
+#include <common.h>
+#include <expo.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <malloc.h>
+#include <dm/ofnode.h>
+#include <linux/libfdt.h>
+
+/**
+ * struct build_info - Information to use when building
+ *
+ * @str_for_id: String for each ID in use, NULL if empty. The string is NULL
+ *	if there is nothing for this ID. Since ID 0 is never used, the first
+ *	element of this array is always NULL
+ * @str_count: Number of entries in @str_for_id
+ */
+struct build_info {
+	const char **str_for_id;
+	int str_count;
+};
+
+/**
+ * add_txt_str - Add a string or lookup its ID, then add to expo
+ *
+ * @info: Build information
+ * @node: Node describing scene
+ * @scn: Scene to add to
+ * @find_name: Name to look for (e.g. "title"). This will find a property called
+ * "title" if it exists, else will look up the string for "title-id"
+ * Return: ID of added string, or -ve on error
+ */
+int add_txt_str(struct build_info *info, ofnode node, struct scene *scn,
+		const char *find_name, uint obj_id)
+{
+	const char *text;
+	uint str_id;
+	int ret;
+
+	text = ofnode_read_string(node, find_name);
+	if (!text) {
+		char name[40];
+		u32 id;
+
+		snprintf(name, sizeof(name), "%s-id", find_name);
+		ret = ofnode_read_u32(node, name, &id);
+		if (ret)
+			return log_msg_ret("id", -EINVAL);
+
+		if (id >= info->str_count)
+			return log_msg_ret("id", -E2BIG);
+		text = info->str_for_id[id];
+		if (!text)
+			return log_msg_ret("id", -EINVAL);
+	}
+
+	ret = expo_str(scn->expo, find_name, 0, text);
+	if (ret < 0)
+		return log_msg_ret("add", ret);
+	str_id = ret;
+
+	ret = scene_txt_str(scn, find_name, obj_id, str_id, text, NULL);
+	if (ret < 0)
+		return log_msg_ret("add", ret);
+
+	return ret;
+}
+
+/**
+ * add_txt_str_list - Add a list string or lookup its ID, then add to expo
+ *
+ * @info: Build information
+ * @node: Node describing scene
+ * @scn: Scene to add to
+ * @find_name: Name to look for (e.g. "title"). This will find a string-list
+ * property called "title" if it exists, else will look up the string in the
+ * "title-id" string list.
+ * Return: ID of added string, or -ve on error
+ */
+int add_txt_str_list(struct build_info *info, ofnode node, struct scene *scn,
+		     const char *find_name, int index, uint obj_id)
+{
+	const char *text;
+	uint str_id;
+	int ret;
+
+	ret = ofnode_read_string_index(node, find_name, index, &text);
+	if (ret) {
+		char name[40];
+		u32 id;
+
+		snprintf(name, sizeof(name), "%s-id", find_name);
+		ret = ofnode_read_u32_index(node, name, index, &id);
+		if (ret)
+			return log_msg_ret("id", -ENOENT);
+
+		if (id >= info->str_count)
+			return log_msg_ret("id", -E2BIG);
+		text = info->str_for_id[id];
+		if (!text)
+			return log_msg_ret("id", -EINVAL);
+	}
+
+	ret = expo_str(scn->expo, find_name, 0, text);
+	if (ret < 0)
+		return log_msg_ret("add", ret);
+	str_id = ret;
+
+	ret = scene_txt_str(scn, find_name, obj_id, str_id, text, NULL);
+	if (ret < 0)
+		return log_msg_ret("add", ret);
+
+	return ret;
+}
+
+/*
+ * build_element() - Handle creating a text object from a label
+ *
+ * Look up a property called @label or @label-id and create a string for it
+ */
+int build_element(void *ldtb, int node, const char *label)
+{
+	return 0;
+}
+
+/**
+ * read_strings() - Read in the list of strings
+ *
+ * Read the strings into an ID-indexed list, so they can be used for building
+ * an expo. The strings are in a /strings node and each has its own subnode
+ * containing the ID and the string itself:
+ *
+ * example {
+ *    id = <123>;
+ *    value = "This is a test";
+ * };
+ *
+ * Future work may add support for unicode and multiple languages
+ *
+ * @info: Build information
+ * @root: Root node to read from
+ * Returns: 0 if OK, -ENOMEM if out of memory, -EINVAL if there is a format
+ * error
+ */
+static int read_strings(struct build_info *info, ofnode root)
+{
+	ofnode strings, node;
+
+	strings = ofnode_find_subnode(root, "strings");
+	if (!ofnode_valid(strings))
+		return log_msg_ret("str", -EINVAL);
+
+	ofnode_for_each_subnode(node, strings) {
+		const char *val;
+		int ret;
+		u32 id;
+
+		ret = ofnode_read_u32(node, "id", &id);
+		if (ret)
+			return log_msg_ret("id", -EINVAL);
+		val = ofnode_read_string(node, "value");
+		if (!val)
+			return log_msg_ret("val", -EINVAL);
+
+		if (id >= info->str_count) {
+			int new_count = info->str_count + 20;
+			void *new_arr;
+
+			new_arr = realloc(info->str_for_id,
+					  new_count * sizeof(char *));
+			if (!new_arr)
+				return log_msg_ret("id", -ENOMEM);
+			memset(new_arr + info->str_count, '\0',
+			       (new_count - info->str_count) * sizeof(char *));
+			info->str_for_id = new_arr;
+			info->str_count = new_count;
+		}
+
+		info->str_for_id[id] = val;
+	}
+
+	return 0;
+}
+
+/**
+ * list_strings() - List the available strings with their IDs
+ *
+ * @info: Build information
+ */
+static void list_strings(struct build_info *info)
+{
+	int i;
+
+	for (i = 0; i < info->str_count; i++) {
+		if (info->str_for_id[i])
+			printf("%3d %s\n", i, info->str_for_id[i]);
+	}
+}
+
+/**
+ * menu_build() - Build a menu and add it to a scene
+ *
+ * See doc/developer/expo.rst for a description of the format
+ *
+ * @info: Build information
+ * @node: Node containing the menu description
+ * @scn: Scene to add the menu to
+ * Returns: 0 if OK, -ENOMEM if out of memory, -EINVAL if there is a format
+ * error, -ENOENT if there is a references to a non-existent string
+ */
+static int menu_build(struct build_info *info, ofnode node, struct scene *scn)
+{
+	struct scene_obj_menu *menu;
+	uint title_id, menu_id;
+	const u32 *item_ids;
+	int ret, size, i;
+	const char *name;
+	u32 id;
+
+	name = ofnode_get_name(node);
+	ret = ofnode_read_u32(node, "id", &id);
+	if (ret)
+		return log_msg_ret("id", -EINVAL);
+
+	ret = scene_menu(scn, name, id, &menu);
+	if (ret < 0)
+		return log_msg_ret("men", ret);
+	menu_id = ret;
+
+	/* Set the title */
+	ret = add_txt_str(info, node, scn, "title", 0);
+	if (ret < 0)
+		return log_msg_ret("tit", ret);
+	title_id = ret;
+	ret = scene_menu_set_title(scn, menu_id, title_id);
+
+	item_ids = ofnode_read_prop(node, "item-id", &size);
+	if (!item_ids)
+		return log_msg_ret("itm", -EINVAL);
+	if (!size || size % sizeof(u32))
+		return log_msg_ret("isz", -EINVAL);
+	size /= sizeof(u32);
+
+	for (i = 0; i < size; i++) {
+		struct scene_menitem *item;
+		uint label, key, desc;
+
+		ret = add_txt_str_list(info, node, scn, "item-label", i, 0);
+		if (ret < 0 && ret != -ENOENT)
+			return log_msg_ret("lab", ret);
+		label = max(0, ret);
+
+		ret = add_txt_str_list(info, node, scn, "key-label", i, 0);
+		if (ret < 0 && ret != -ENOENT)
+			return log_msg_ret("key", ret);
+		key = max(0, ret);
+
+		ret = add_txt_str_list(info, node, scn, "desc-label", i, 0);
+		if (ret < 0  && ret != -ENOENT)
+			return log_msg_ret("lab", ret);
+		desc = max(0, ret);
+
+		ret = scene_menuitem(scn, menu_id, simple_xtoa(i),
+				     fdt32_to_cpu(item_ids[i]), key, label,
+				     desc, 0, 0, &item);
+		if (ret < 0)
+			return log_msg_ret("mi", ret);
+	}
+
+	return 0;
+}
+
+/**
+ * menu_build() - Build an expo object and add it to a scene
+ *
+ * See doc/developer/expo.rst for a description of the format
+ *
+ * @info: Build information
+ * @node: Node containing the object description
+ * @scn: Scene to add the object to
+ * Returns: 0 if OK, -ENOMEM if out of memory, -EINVAL if there is a format
+ * error, -ENOENT if there is a references to a non-existent string
+ */
+static int obj_build(struct build_info *info, ofnode node, struct scene *scn)
+{
+	const char *type;
+	u32 id;
+	int ret;
+
+	log_debug("- object %s\n", ofnode_get_name(node));
+	ret = ofnode_read_u32(node, "id", &id);
+	if (ret)
+		return log_msg_ret("id", -EINVAL);
+
+	type = ofnode_read_string(node, "type");
+	if (!type)
+		return log_msg_ret("typ", -EINVAL);
+
+	if (!strcmp("menu", type))
+		ret = menu_build(info, node, scn);
+	 else
+		ret = -EINVAL;
+	if (ret)
+		return log_msg_ret("bld", ret);
+
+	return 0;
+}
+
+/**
+ * scene_build() - Build a scene and all its objects
+ *
+ * See doc/developer/expo.rst for a description of the format
+ *
+ * @info: Build information
+ * @node: Node containing the scene description
+ * @scn: Scene to add the object to
+ * Returns: 0 if OK, -ENOMEM if out of memory, -EINVAL if there is a format
+ * error, -ENOENT if there is a references to a non-existent string
+ */
+static int scene_build(struct build_info *info, ofnode scn_node,
+		       struct expo *exp)
+{
+	const char *name;
+	struct scene *scn;
+	uint id, title_id;
+	ofnode node;
+	int ret;
+
+	name = ofnode_get_name(scn_node);
+	log_debug("Building scene %s\n", name);
+	ret = ofnode_read_u32(scn_node, "id", &id);
+	if (ret)
+		return log_msg_ret("id", -EINVAL);
+
+	ret = scene_new(exp, name, id, &scn);
+	if (ret < 0)
+		return log_msg_ret("scn", ret);
+
+	ret = add_txt_str(info, scn_node, scn, "title", 0);
+	if (ret < 0)
+		return log_msg_ret("tit", ret);
+	title_id = ret;
+	scene_title_set(scn, title_id);
+
+	ret = add_txt_str(info, scn_node, scn, "prompt", 0);
+	if (ret < 0)
+		return log_msg_ret("pr", ret);
+
+	ofnode_for_each_subnode(node, scn_node) {
+		ret = obj_build(info, node, scn);
+		if (ret < 0)
+			return log_msg_ret("mit", ret);
+	}
+
+	return 0;
+}
+
+int expo_build(ofnode root, struct expo **expp)
+{
+	struct build_info info;
+	ofnode scenes, node;
+	struct expo *exp;
+	u32 dyn_start;
+	int ret;
+
+	memset(&info, '\0', sizeof(info));
+	ret = read_strings(&info, root);
+	if (ret)
+		return log_msg_ret("str", ret);
+	if (_DEBUG)
+		list_strings(&info);
+
+	ret = expo_new("name", NULL, &exp);
+	if (ret)
+		return log_msg_ret("exp", ret);
+
+	if (!ofnode_read_u32(root, "dynamic-start", &dyn_start))
+		expo_set_dynamic_start(exp, dyn_start);
+
+	scenes = ofnode_find_subnode(root, "scenes");
+	if (!ofnode_valid(scenes))
+		return log_msg_ret("sno", -EINVAL);
+
+	ofnode_for_each_subnode(node, scenes) {
+		ret = scene_build(&info, node, exp);
+		if (ret < 0)
+			return log_msg_ret("scn", ret);
+	}
+	*expp = exp;
+
+	return 0;
+}
diff --git a/boot/scene.c b/boot/scene.c
index 030f6aa2a0..e52333371f 100644
--- a/boot/scene.c
+++ b/boot/scene.c
@@ -6,26 +6,19 @@
  * Written by Simon Glass <sjg@chromium.org>
  */
 
+#define LOG_CATEGORY	LOGC_EXPO
+
 #include <common.h>
 #include <dm.h>
 #include <expo.h>
 #include <malloc.h>
 #include <mapmem.h>
+#include <menu.h>
 #include <video.h>
 #include <video_console.h>
 #include <linux/input.h>
 #include "scene_internal.h"
 
-uint resolve_id(struct expo *exp, uint id)
-{
-	if (!id)
-		id = exp->next_id++;
-	else if (id >= exp->next_id)
-		exp->next_id = id + 1;
-
-	return id;
-}
-
 int scene_new(struct expo *exp, const char *name, uint id, struct scene **scnp)
 {
 	struct scene *scn;
@@ -65,16 +58,12 @@ void scene_destroy(struct scene *scn)
 		scene_obj_destroy(obj);
 
 	free(scn->name);
-	free(scn->title);
 	free(scn);
 }
 
-int scene_title_set(struct scene *scn, const char *title)
+int scene_title_set(struct scene *scn, uint id)
 {
-	free(scn->title);
-	scn->title = strdup(title);
-	if (!scn->title)
-		return log_msg_ret("tit", -ENOMEM);
+	scn->title_id = id;
 
 	return 0;
 }
@@ -103,6 +92,18 @@ void *scene_obj_find(struct scene *scn, uint id, enum scene_obj_t type)
 	return NULL;
 }
 
+void *scene_obj_find_by_name(struct scene *scn, const char *name)
+{
+	struct scene_obj *obj;
+
+	list_for_each_entry(obj, &scn->obj_head, sibling) {
+		if (!strcmp(name, obj->name))
+			return obj;
+	}
+
+	return NULL;
+}
+
 int scene_obj_add(struct scene *scn, const char *name, uint id,
 		  enum scene_obj_t type, uint size, struct scene_obj **objp)
 {
@@ -213,22 +214,46 @@ int scene_obj_set_pos(struct scene *scn, uint id, int x, int y)
 	obj = scene_obj_find(scn, id, SCENEOBJT_NONE);
 	if (!obj)
 		return log_msg_ret("find", -ENOENT);
-	obj->x = x;
-	obj->y = y;
-	if (obj->type == SCENEOBJT_MENU)
-		scene_menu_arrange(scn, (struct scene_obj_menu *)obj);
+	obj->dim.x = x;
+	obj->dim.y = y;
+
+	return 0;
+}
+
+int scene_obj_set_size(struct scene *scn, uint id, int w, int h)
+{
+	struct scene_obj *obj;
+
+	obj = scene_obj_find(scn, id, SCENEOBJT_NONE);
+	if (!obj)
+		return log_msg_ret("find", -ENOENT);
+	obj->dim.w = w;
+	obj->dim.h = h;
 
 	return 0;
 }
 
 int scene_obj_set_hide(struct scene *scn, uint id, bool hide)
 {
+	int ret;
+
+	ret = scene_obj_flag_clrset(scn, id, SCENEOF_HIDE,
+				    hide ? SCENEOF_HIDE : 0);
+	if (ret)
+		return log_msg_ret("flg", ret);
+
+	return 0;
+}
+
+int scene_obj_flag_clrset(struct scene *scn, uint id, uint clr, uint set)
+{
 	struct scene_obj *obj;
 
 	obj = scene_obj_find(scn, id, SCENEOBJT_NONE);
 	if (!obj)
 		return log_msg_ret("find", -ENOENT);
-	obj->hide = hide;
+	obj->flags &= ~clr;
+	obj->flags |= set;
 
 	return 0;
 }
@@ -258,16 +283,30 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp)
 	case SCENEOBJT_TEXT: {
 		struct scene_obj_txt *txt = (struct scene_obj_txt *)obj;
 		struct expo *exp = scn->expo;
+		struct vidconsole_bbox bbox;
+		const char *str;
+		int len, ret;
 
+		str = expo_get_str(exp, txt->str_id);
+		if (!str)
+			return log_msg_ret("str", -ENOENT);
+		len = strlen(str);
+
+		/* if there is no console, make it up */
+		if (!exp->cons) {
+			if (widthp)
+				*widthp = 8 * len;
+			return 16;
+		}
+
+		ret = vidconsole_measure(scn->expo->cons, txt->font_name,
+					 txt->font_size, str, &bbox);
+		if (ret)
+			return log_msg_ret("mea", ret);
 		if (widthp)
-			*widthp = 16; /* fake value for now */
-		if (txt->font_size)
-			return txt->font_size;
-		if (exp->display)
-			return video_default_font_height(exp->display);
-
-		/* use a sensible default */
-		return 16;
+			*widthp = bbox.x1;
+
+		return bbox.y1;
 	}
 	}
 
@@ -282,18 +321,13 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode)
 {
 	struct scene *scn = obj->scene;
 	struct expo *exp = scn->expo;
-	struct udevice *cons, *dev = exp->display;
+	const struct expo_theme *theme = &exp->theme;
+	struct udevice *dev = exp->display;
+	struct udevice *cons = text_mode ? NULL : exp->cons;
 	int x, y, ret;
 
-	cons = NULL;
-	if (!text_mode) {
-		ret = device_find_first_child_by_uclass(dev,
-							UCLASS_VIDEO_CONSOLE,
-							&cons);
-	}
-
-	x = obj->x;
-	y = obj->y;
+	x = obj->dim.x;
+	y = obj->dim.y;
 
 	switch (obj->type) {
 	case SCENEOBJT_NONE:
@@ -325,14 +359,45 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode)
 		}
 		if (ret && ret != -ENOSYS)
 			return log_msg_ret("font", ret);
-		vidconsole_set_cursor_pos(cons, x, y);
 		str = expo_get_str(exp, txt->str_id);
-		if (str)
+		if (str) {
+			struct video_priv *vid_priv;
+			struct vidconsole_colour old;
+			enum colour_idx fore, back;
+
+			if (CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK)) {
+				fore = VID_BLACK;
+				back = VID_WHITE;
+			} else {
+				fore = VID_LIGHT_GRAY;
+				back = VID_BLACK;
+			}
+
+			vid_priv = dev_get_uclass_priv(dev);
+			if (obj->flags & SCENEOF_POINT) {
+				vidconsole_push_colour(cons, fore, back, &old);
+				video_fill_part(dev, x - theme->menu_inset, y,
+						x + obj->dim.w,
+						y + obj->dim.h,
+						vid_priv->colour_bg);
+			}
+			vidconsole_set_cursor_pos(cons, x, y);
 			vidconsole_put_string(cons, str);
+			if (obj->flags & SCENEOF_POINT)
+				vidconsole_pop_colour(cons, &old);
+		}
 		break;
 	}
 	case SCENEOBJT_MENU: {
 		struct scene_obj_menu *menu = (struct scene_obj_menu *)obj;
+
+		if (exp->popup && (obj->flags & SCENEOF_OPEN)) {
+			if (!cons)
+				return -ENOTSUPP;
+
+			/* draw a background behind the menu items */
+			scene_menu_render(menu);
+		}
 		/*
 		 * With a vidconsole, the text and item pointer are rendered as
 		 * normal objects so we don't need to do anything here. The menu
@@ -371,6 +436,30 @@ int scene_arrange(struct scene *scn)
 	return 0;
 }
 
+int scene_render_deps(struct scene *scn, uint id)
+{
+	struct scene_obj *obj;
+	int ret;
+
+	if (!id)
+		return 0;
+	obj = scene_obj_find(scn, id, SCENEOBJT_NONE);
+	if (!obj)
+		return log_msg_ret("obj", -ENOENT);
+
+	if (!(obj->flags & SCENEOF_HIDE)) {
+		ret = scene_obj_render(obj, false);
+		if (ret && ret != -ENOTSUPP)
+			return log_msg_ret("ren", ret);
+
+		if (obj->type == SCENEOBJT_MENU)
+			scene_menu_render_deps(scn,
+					       (struct scene_obj_menu *)obj);
+	}
+
+	return 0;
+}
+
 int scene_render(struct scene *scn)
 {
 	struct expo *exp = scn->expo;
@@ -378,21 +467,107 @@ int scene_render(struct scene *scn)
 	int ret;
 
 	list_for_each_entry(obj, &scn->obj_head, sibling) {
-		if (!obj->hide) {
+		if (!(obj->flags & SCENEOF_HIDE)) {
 			ret = scene_obj_render(obj, exp->text_mode);
 			if (ret && ret != -ENOTSUPP)
 				return log_msg_ret("ren", ret);
 		}
 	}
 
+	/* render any highlighted object on top of the others */
+	if (scn->highlight_id && !exp->text_mode) {
+		ret = scene_render_deps(scn, scn->highlight_id);
+		if (ret && ret != -ENOTSUPP)
+			return log_msg_ret("dep", ret);
+	}
+
 	return 0;
 }
 
+/**
+ * send_key_obj() - Handle a keypress for moving between objects
+ *
+ * @scn: Scene to receive the key
+ * @key: Key to send (KEYCODE_UP)
+ * @event: Returns resulting event from this keypress
+ * Returns: 0 if OK, -ve on error
+ */
+static void send_key_obj(struct scene *scn, struct scene_obj *obj, int key,
+			 struct expo_action *event)
+{
+	switch (key) {
+	case BKEY_UP:
+		while (obj != list_first_entry(&scn->obj_head, struct scene_obj,
+					       sibling)) {
+			obj = list_entry(obj->sibling.prev,
+					 struct scene_obj, sibling);
+			if (obj->type == SCENEOBJT_MENU) {
+				event->type = EXPOACT_POINT_OBJ;
+				event->select.id = obj->id;
+				log_debug("up to obj %d\n", event->select.id);
+				break;
+			}
+		}
+		break;
+	case BKEY_DOWN:
+		while (!list_is_last(&obj->sibling, &scn->obj_head)) {
+			obj = list_entry(obj->sibling.next, struct scene_obj,
+					 sibling);
+			if (obj->type == SCENEOBJT_MENU) {
+				event->type = EXPOACT_POINT_OBJ;
+				event->select.id = obj->id;
+				log_debug("down to obj %d\n", event->select.id);
+				break;
+			}
+		}
+		break;
+	case BKEY_SELECT:
+		if (obj->type == SCENEOBJT_MENU) {
+			event->type = EXPOACT_OPEN;
+			event->select.id = obj->id;
+			log_debug("open obj %d\n", event->select.id);
+		}
+		break;
+	case BKEY_QUIT:
+		event->type = EXPOACT_QUIT;
+		log_debug("obj quit\n");
+		break;
+	}
+}
+
 int scene_send_key(struct scene *scn, int key, struct expo_action *event)
 {
+	struct scene_obj_menu *menu;
 	struct scene_obj *obj;
 	int ret;
 
+	event->type = EXPOACT_NONE;
+
+	/*
+	 * In 'popup' mode, arrow keys move betwen objects, unless a menu is
+	 * opened
+	 */
+	if (scn->expo->popup) {
+		obj = NULL;
+		if (scn->highlight_id) {
+			obj = scene_obj_find(scn, scn->highlight_id,
+					     SCENEOBJT_NONE);
+		}
+		if (!obj)
+			return 0;
+
+		if (!(obj->flags & SCENEOF_OPEN)) {
+			send_key_obj(scn, obj, key, event);
+			return 0;
+		}
+
+		menu = (struct scene_obj_menu *)obj,
+		ret = scene_menu_send_key(scn, menu, key, event);
+		if (ret)
+			return log_msg_ret("key", ret);
+		return 0;
+	}
+
 	list_for_each_entry(obj, &scn->obj_head, sibling) {
 		if (obj->type == SCENEOBJT_MENU) {
 			struct scene_obj_menu *menu;
@@ -401,14 +576,108 @@ int scene_send_key(struct scene *scn, int key, struct expo_action *event)
 			ret = scene_menu_send_key(scn, menu, key, event);
 			if (ret)
 				return log_msg_ret("key", ret);
+			break;
+		}
+	}
 
-			/* only allow one menu */
-			ret = scene_menu_arrange(scn, menu);
-			if (ret)
-				return log_msg_ret("arr", ret);
+	return 0;
+}
+
+int scene_calc_dims(struct scene *scn, bool do_menus)
+{
+	struct scene_obj *obj;
+	int ret;
+
+	list_for_each_entry(obj, &scn->obj_head, sibling) {
+		switch (obj->type) {
+		case SCENEOBJT_NONE:
+		case SCENEOBJT_TEXT:
+		case SCENEOBJT_IMAGE: {
+			int width;
+
+			if (!do_menus) {
+				ret = scene_obj_get_hw(scn, obj->id, &width);
+				if (ret < 0)
+					return log_msg_ret("get", ret);
+				obj->dim.w = width;
+				obj->dim.h = ret;
+			}
+			break;
+		}
+		case SCENEOBJT_MENU: {
+			struct scene_obj_menu *menu;
+
+			if (do_menus) {
+				menu = (struct scene_obj_menu *)obj;
+
+				ret = scene_menu_calc_dims(menu);
+				if (ret)
+					return log_msg_ret("men", ret);
+			}
+			break;
+		}
+		}
+	}
+
+	return 0;
+}
+
+int scene_apply_theme(struct scene *scn, struct expo_theme *theme)
+{
+	struct scene_obj *obj;
+	int ret;
+
+	/* Avoid error-checking optional items */
+	scene_txt_set_font(scn, scn->title_id, NULL, theme->font_size);
+
+	list_for_each_entry(obj, &scn->obj_head, sibling) {
+		switch (obj->type) {
+		case SCENEOBJT_NONE:
+		case SCENEOBJT_IMAGE:
+		case SCENEOBJT_MENU:
+			break;
+		case SCENEOBJT_TEXT:
+			scene_txt_set_font(scn, obj->id, NULL,
+					   theme->font_size);
+			break;
+		}
+	}
+
+	ret = scene_arrange(scn);
+	if (ret)
+		return log_msg_ret("arr", ret);
+
+	return 0;
+}
+
+void scene_set_highlight_id(struct scene *scn, uint id)
+{
+	scn->highlight_id = id;
+}
+
+void scene_highlight_first(struct scene *scn)
+{
+	struct scene_obj *obj;
+
+	list_for_each_entry(obj, &scn->obj_head, sibling) {
+		switch (obj->type) {
+		case SCENEOBJT_MENU:
+			scene_set_highlight_id(scn, obj->id);
+			return;
+		default:
 			break;
 		}
 	}
+}
+
+int scene_set_open(struct scene *scn, uint id, bool open)
+{
+	int ret;
+
+	ret = scene_obj_flag_clrset(scn, id, SCENEOF_OPEN,
+				    open ? SCENEOF_OPEN : 0);
+	if (ret)
+		return log_msg_ret("flg", ret);
 
 	return 0;
 }
diff --git a/boot/scene_internal.h b/boot/scene_internal.h
index e8fd765811..fb1ea5533b 100644
--- a/boot/scene_internal.h
+++ b/boot/scene_internal.h
@@ -23,7 +23,7 @@ struct scene *expo_lookup_scene_id(struct expo *exp, uint scene_id);
  *
  * @exp: Expo to use
  * @id: ID to use, or 0 to auto-allocate one
- * @return: Either @id, or the auto-allocated ID
+ * Returns: Either @id, or the auto-allocated ID
  */
 uint resolve_id(struct expo *exp, uint id);
 
@@ -36,10 +36,19 @@ uint resolve_id(struct expo *exp, uint id);
  * @scn: Scene to search
  * @id: ID of object to find
  * @type: Type of the object, or SCENEOBJT_NONE to match any type
+ * Returns: Object found, or NULL if not found
  */
 void *scene_obj_find(struct scene *scn, uint id, enum scene_obj_t type);
 
 /**
+ * scene_obj_find_by_name() - Find an object in a scene by name
+ *
+ * @scn: Scene to search
+ * @name: Name to search for
+ */
+void *scene_obj_find_by_name(struct scene *scn, const char *name);
+
+/**
  * scene_obj_add() - Add a new object to a scene
  *
  * @scn: Scene to update
@@ -54,6 +63,28 @@ int scene_obj_add(struct scene *scn, const char *name, uint id,
 		  enum scene_obj_t type, uint size, struct scene_obj **objp);
 
 /**
+ * scene_obj_flag_clrset() - Adjust object flags
+ *
+ * @scn: Scene to update
+ * @id: ID of object to update
+ * @clr: Bits to clear in the object's flags
+ * @set: Bits to set in the object's flags
+ * Returns 0 if OK, -ENOENT if the object was not found
+ */
+int scene_obj_flag_clrset(struct scene *scn, uint id, uint clr, uint set);
+
+/**
+ * scene_calc_dims() - Calculate the dimensions of the scene objects
+ *
+ * Updates the width and height of all objects based on their contents
+ *
+ * @scn: Scene to update
+ * @do_menus: true to calculate only menus, false to calculate everything else
+ * Returns 0 if OK, -ENOTSUPP if there is no graphical console
+ */
+int scene_calc_dims(struct scene *scn, bool do_menus);
+
+/**
  * scene_menu_arrange() - Set the position of things in the menu
  *
  * This updates any items associated with a menu to make sure they are
@@ -62,17 +93,27 @@ int scene_obj_add(struct scene *scn, const char *name, uint id,
  *
  * @scn: Scene to update
  * @menu: Menu to process
+ * Returns: 0 if OK, -ve on error
  */
 int scene_menu_arrange(struct scene *scn, struct scene_obj_menu *menu);
 
 /**
+ * scene_apply_theme() - Apply a theme to a scene
+ *
+ * @scn: Scene to update
+ * @theme: Theme to apply
+ * Returns: 0 if OK, -ve on error
+ */
+int scene_apply_theme(struct scene *scn, struct expo_theme *theme);
+
+/**
  * scene_menu_send_key() - Send a key to a menu for processing
  *
  * @scn: Scene to use
  * @menu: Menu to use
  * @key: Key code to send (KEY_...)
  * @event: Place to put any event which is generated by the key
- * @return 0 if OK, -ENOTTY if there is no current menu item, other -ve on other
+ * Returns: 0 if OK, -ENOTTY if there is no current menu item, other -ve on other
  *	error
  */
 int scene_menu_send_key(struct scene *scn, struct scene_obj_menu *menu, int key,
@@ -89,7 +130,7 @@ void scene_menu_destroy(struct scene_obj_menu *menu);
  * scene_menu_display() - Display a menu as text
  *
  * @menu: Menu to display
- * @return 0 if OK, -ENOENT if @id is invalid
+ * Returns: 0 if OK, -ENOENT if @id is invalid
  */
 int scene_menu_display(struct scene_obj_menu *menu);
 
@@ -120,4 +161,41 @@ int scene_render(struct scene *scn);
  */
 int scene_send_key(struct scene *scn, int key, struct expo_action *event);
 
+/**
+ * scene_menu_render() - Render the background behind a menu
+ *
+ * @menu: Menu to render
+ */
+void scene_menu_render(struct scene_obj_menu *menu);
+
+/**
+ * scene_render_deps() - Render an object and its dependencies
+ *
+ * @scn: Scene to render
+ * @id: Object ID to render (or 0 for none)
+ * Returns: 0 if OK, -ve on error
+ */
+int scene_render_deps(struct scene *scn, uint id);
+
+/**
+ * scene_menu_render_deps() - Render a menu and its dependencies
+ *
+ * Renders the menu and all of its attached objects
+ *
+ * @scn: Scene to render
+ * @menu: Menu render
+ * Returns: 0 if OK, -ve on error
+ */
+int scene_menu_render_deps(struct scene *scn, struct scene_obj_menu *menu);
+
+/**
+ * scene_menu_calc_dims() - Calculate the dimensions of a menu
+ *
+ * Updates the width and height of the menu based on its contents
+ *
+ * @menu: Menu to update
+ * Returns 0 if OK, -ENOTSUPP if there is no graphical console
+ */
+int scene_menu_calc_dims(struct scene_obj_menu *menu);
+
 #endif /* __SCENE_INTERNAL_H */
diff --git a/boot/scene_menu.c b/boot/scene_menu.c
index 18998e862a..8a355f838c 100644
--- a/boot/scene_menu.c
+++ b/boot/scene_menu.c
@@ -6,7 +6,7 @@
  * Written by Simon Glass <sjg@chromium.org>
  */
 
-#define LOG_CATEGORY	LOGC_BOOT
+#define LOG_CATEGORY	LOGC_EXPO
 
 #include <common.h>
 #include <dm.h>
@@ -33,6 +33,58 @@ void scene_menu_destroy(struct scene_obj_menu *menu)
 		scene_menuitem_destroy(item);
 }
 
+static struct scene_menitem *scene_menuitem_find(struct scene_obj_menu *menu,
+						 int id)
+{
+	struct scene_menitem *item;
+
+	list_for_each_entry(item, &menu->item_head, sibling) {
+		if (item->id == id)
+			return item;
+	}
+
+	return NULL;
+}
+
+/**
+ * update_pointers() - Update the pointer object and handle highlights
+ *
+ * @menu: Menu to update
+ * @id: ID of menu item to select/deselect
+ * @point: true if @id is being selected, false if it is being deselected
+ */
+static int update_pointers(struct scene_obj_menu *menu, uint id, bool point)
+{
+	struct scene *scn = menu->obj.scene;
+	const bool stack = scn->expo->popup;
+	const struct scene_menitem *item;
+	int ret;
+
+	item = scene_menuitem_find(menu, id);
+	if (!item)
+		return log_msg_ret("itm", -ENOENT);
+
+	/* adjust the pointer object to point to the selected item */
+	if (menu->pointer_id && item && point) {
+		struct scene_obj *label;
+
+		label = scene_obj_find(scn, item->label_id, SCENEOBJT_NONE);
+
+		ret = scene_obj_set_pos(scn, menu->pointer_id,
+					menu->obj.dim.x + 200, label->dim.y);
+		if (ret < 0)
+			return log_msg_ret("ptr", ret);
+	}
+
+	if (stack) {
+		point &= scn->highlight_id == menu->obj.id;
+		scene_obj_flag_clrset(scn, item->label_id, SCENEOF_POINT,
+				      point ? SCENEOF_POINT : 0);
+	}
+
+	return 0;
+}
+
 /**
  * menu_point_to_item() - Point to a particular menu item
  *
@@ -40,18 +92,115 @@ void scene_menu_destroy(struct scene_obj_menu *menu)
  */
 static void menu_point_to_item(struct scene_obj_menu *menu, uint item_id)
 {
+	if (menu->cur_item_id)
+		update_pointers(menu, menu->cur_item_id, false);
 	menu->cur_item_id = item_id;
+	update_pointers(menu, item_id, true);
+}
+
+static int scene_bbox_union(struct scene *scn, uint id, int inset,
+			    struct vidconsole_bbox *bbox)
+{
+	struct scene_obj *obj;
+
+	if (!id)
+		return 0;
+	obj = scene_obj_find(scn, id, SCENEOBJT_NONE);
+	if (!obj)
+		return log_msg_ret("obj", -ENOENT);
+	if (bbox->valid) {
+		bbox->x0 = min(bbox->x0, obj->dim.x - inset);
+		bbox->y0 = min(bbox->y0, obj->dim.y);
+		bbox->x1 = max(bbox->x1, obj->dim.x + obj->dim.w + inset);
+		bbox->y1 = max(bbox->y1, obj->dim.y + obj->dim.h);
+	} else {
+		bbox->x0 = obj->dim.x - inset;
+		bbox->y0 = obj->dim.y;
+		bbox->x1 = obj->dim.x + obj->dim.w + inset;
+		bbox->y1 = obj->dim.y + obj->dim.h;
+		bbox->valid = true;
+	}
+
+	return 0;
+}
+
+/**
+ * scene_menu_calc_bbox() - Calculate bounding boxes for the menu
+ *
+ * @menu: Menu to process
+ * @bbox: Returns bounding box of menu including prompts
+ * @label_bbox: Returns bounding box of labels
+ */
+static void scene_menu_calc_bbox(struct scene_obj_menu *menu,
+				 struct vidconsole_bbox *bbox,
+				 struct vidconsole_bbox *label_bbox)
+{
+	const struct expo_theme *theme = &menu->obj.scene->expo->theme;
+	const struct scene_menitem *item;
+
+	bbox->valid = false;
+	scene_bbox_union(menu->obj.scene, menu->title_id, 0, bbox);
+
+	label_bbox->valid = false;
+
+	list_for_each_entry(item, &menu->item_head, sibling) {
+		scene_bbox_union(menu->obj.scene, item->label_id,
+				 theme->menu_inset, bbox);
+		scene_bbox_union(menu->obj.scene, item->key_id, 0, bbox);
+		scene_bbox_union(menu->obj.scene, item->desc_id, 0, bbox);
+		scene_bbox_union(menu->obj.scene, item->preview_id, 0, bbox);
+
+		/* Get the bounding box of all labels */
+		scene_bbox_union(menu->obj.scene, item->label_id,
+				 theme->menu_inset, label_bbox);
+	}
+
+	/*
+	 * subtract the final menuitem's gap to keep the insert the same top
+	 * and bottom
+	 */
+	label_bbox->y1 -= theme->menuitem_gap_y;
+}
+
+int scene_menu_calc_dims(struct scene_obj_menu *menu)
+{
+	struct vidconsole_bbox bbox, label_bbox;
+	const struct scene_menitem *item;
+
+	scene_menu_calc_bbox(menu, &bbox, &label_bbox);
+
+	/* Make all labels the same size */
+	if (label_bbox.valid) {
+		list_for_each_entry(item, &menu->item_head, sibling) {
+			scene_obj_set_size(menu->obj.scene, item->label_id,
+					   label_bbox.x1 - label_bbox.x0,
+					   label_bbox.y1 - label_bbox.y0);
+		}
+	}
+
+	if (bbox.valid) {
+		menu->obj.dim.w = bbox.x1 - bbox.x0;
+		menu->obj.dim.h = bbox.y1 - bbox.y0;
+	}
+
+	return 0;
 }
 
 int scene_menu_arrange(struct scene *scn, struct scene_obj_menu *menu)
 {
+	const bool open = menu->obj.flags & SCENEOF_OPEN;
+	struct expo *exp = scn->expo;
+	const bool stack = exp->popup;
+	const struct expo_theme *theme = &exp->theme;
 	struct scene_menitem *item;
-	int y, cur_y;
+	uint sel_id;
+	int x, y;
 	int ret;
 
-	y = menu->obj.y;
+	x = menu->obj.dim.x;
+	y = menu->obj.dim.y;
 	if (menu->title_id) {
-		ret = scene_obj_set_pos(scn, menu->title_id, menu->obj.x, y);
+		ret = scene_obj_set_pos(scn, menu->title_id, menu->obj.dim.x, y);
 		if (ret < 0)
 			return log_msg_ret("tit", ret);
 
@@ -59,7 +208,10 @@ int scene_menu_arrange(struct scene *scn, struct scene_obj_menu *menu)
 		if (ret < 0)
 			return log_msg_ret("hei", ret);
 
-		y += ret * 2;
+		if (stack)
+			x += 200;
+		else
+			y += ret * 2;
 	}
 
 	/*
@@ -68,11 +220,12 @@ int scene_menu_arrange(struct scene *scn, struct scene_obj_menu *menu)
 	 * small. This can be updated once text measuring is supported in
 	 * vidconsole
 	 */
-	cur_y = -1;
+	sel_id = menu->cur_item_id;
 	list_for_each_entry(item, &menu->item_head, sibling) {
+		bool selected;
 		int height;
 
-		ret = scene_obj_get_hw(scn, item->desc_id, NULL);
+		ret = scene_obj_get_hw(scn, item->label_id, NULL);
 		if (ret < 0)
 			return log_msg_ret("get", ret);
 		height = ret;
@@ -81,32 +234,33 @@ int scene_menu_arrange(struct scene *scn, struct scene_obj_menu *menu)
 			y += height;
 
 		/* select an item if not done already */
-		if (!menu->cur_item_id)
-			menu_point_to_item(menu, item->id);
+		if (!sel_id)
+			sel_id = item->id;
+
+		selected = sel_id == item->id;
 
 		/*
 		 * Put the label on the left, then leave a space for the
 		 * pointer, then the key and the description
 		 */
-		if (item->label_id) {
-			ret = scene_obj_set_pos(scn, item->label_id, menu->obj.x,
-						y);
-			if (ret < 0)
-				return log_msg_ret("nam", ret);
-		}
-
-		ret = scene_obj_set_pos(scn, item->key_id, menu->obj.x + 230,
-					y);
+		ret = scene_obj_set_pos(scn, item->label_id,
+					x + theme->menu_inset, y);
 		if (ret < 0)
-			return log_msg_ret("key", ret);
+			return log_msg_ret("nam", ret);
+		scene_obj_set_hide(scn, item->label_id,
+				   stack && !open && !selected);
 
-		ret = scene_obj_set_pos(scn, item->desc_id, menu->obj.x + 280,
-					y);
-		if (ret < 0)
-			return log_msg_ret("des", ret);
+		if (item->key_id) {
+			ret = scene_obj_set_pos(scn, item->key_id, x + 230, y);
+			if (ret < 0)
+				return log_msg_ret("key", ret);
+		}
 
-		if (menu->cur_item_id == item->id)
-			cur_y = y;
+		if (item->desc_id) {
+			ret = scene_obj_set_pos(scn, item->desc_id, x + 280, y);
+			if (ret < 0)
+				return log_msg_ret("des", ret);
+		}
 
 		if (item->preview_id) {
 			bool hide;
@@ -125,19 +279,12 @@ int scene_menu_arrange(struct scene *scn, struct scene_obj_menu *menu)
 				return log_msg_ret("hid", ret);
 		}
 
-		y += height;
+		if (!stack || open)
+			y += height + theme->menuitem_gap_y;
 	}
 
-	if (menu->pointer_id && cur_y != -1) {
-		/*
-		 * put the pointer to the right of and level with the item it
-		 * points to
-		 */
-		ret = scene_obj_set_pos(scn, menu->pointer_id,
-					menu->obj.x + 200, cur_y);
-		if (ret < 0)
-			return log_msg_ret("ptr", ret);
-	}
+	if (sel_id)
+		menu_point_to_item(menu, sel_id);
 
 	return 0;
 }
@@ -158,10 +305,6 @@ int scene_menu(struct scene *scn, const char *name, uint id,
 		*menup = menu;
 	INIT_LIST_HEAD(&menu->item_head);
 
-	ret = scene_menu_arrange(scn, menu);
-	if (ret)
-		return log_msg_ret("pos", ret);
-
 	return menu->obj.id;
 }
 
@@ -191,6 +334,7 @@ static struct scene_menitem *scene_menu_find_key(struct scene *scn,
 int scene_menu_send_key(struct scene *scn, struct scene_obj_menu *menu, int key,
 			struct expo_action *event)
 {
+	const bool open = menu->obj.flags & SCENEOF_OPEN;
 	struct scene_menitem *item, *cur, *key_item;
 
 	cur = NULL;
@@ -215,7 +359,7 @@ int scene_menu_send_key(struct scene *scn, struct scene_obj_menu *menu, int key,
 					     struct scene_menitem, sibling)) {
 			item = list_entry(item->sibling.prev,
 					  struct scene_menitem, sibling);
-			event->type = EXPOACT_POINT;
+			event->type = EXPOACT_POINT_ITEM;
 			event->select.id = item->id;
 			log_debug("up to item %d\n", event->select.id);
 		}
@@ -224,7 +368,7 @@ int scene_menu_send_key(struct scene *scn, struct scene_obj_menu *menu, int key,
 		if (!list_is_last(&item->sibling, &menu->item_head)) {
 			item = list_entry(item->sibling.next,
 					  struct scene_menitem, sibling);
-			event->type = EXPOACT_POINT;
+			event->type = EXPOACT_POINT_ITEM;
 			event->select.id = item->id;
 			log_debug("down to item %d\n", event->select.id);
 		}
@@ -235,8 +379,13 @@ int scene_menu_send_key(struct scene *scn, struct scene_obj_menu *menu, int key,
 		log_debug("select item %d\n", event->select.id);
 		break;
 	case BKEY_QUIT:
-		event->type = EXPOACT_QUIT;
-		log_debug("quit\n");
+		if (scn->expo->popup && open) {
+			event->type = EXPOACT_CLOSE;
+			event->select.id = menu->obj.id;
+		} else {
+			event->type = EXPOACT_QUIT;
+			log_debug("menu quit\n");
+		}
 		break;
 	case '0'...'9':
 		key_item = scene_menu_find_key(scn, menu, key);
@@ -258,14 +407,13 @@ int scene_menuitem(struct scene *scn, uint menu_id, const char *name, uint id,
 {
 	struct scene_obj_menu *menu;
 	struct scene_menitem *item;
-	int ret;
 
 	menu = scene_obj_find(scn, menu_id, SCENEOBJT_MENU);
 	if (!menu)
 		return log_msg_ret("find", -ENOENT);
 
 	/* Check that the text ID is valid */
-	if (!scene_obj_find(scn, desc_id, SCENEOBJT_TEXT))
+	if (!scene_obj_find(scn, label_id, SCENEOBJT_TEXT))
 		return log_msg_ret("txt", -EINVAL);
 
 	item = calloc(1, sizeof(struct scene_obj_menu));
@@ -285,10 +433,6 @@ int scene_menuitem(struct scene *scn, uint menu_id, const char *name, uint id,
 	item->flags = flags;
 	list_add_tail(&item->sibling, &menu->item_head);
 
-	ret = scene_menu_arrange(scn, menu);
-	if (ret)
-		return log_msg_ret("pos", ret);
-
 	if (itemp)
 		*itemp = item;
 
@@ -388,3 +532,49 @@ int scene_menu_display(struct scene_obj_menu *menu)
 
 	return -ENOTSUPP;
 }
+
+void scene_menu_render(struct scene_obj_menu *menu)
+{
+	struct expo *exp = menu->obj.scene->expo;
+	const struct expo_theme *theme = &exp->theme;
+	struct vidconsole_bbox bbox, label_bbox;
+	struct udevice *dev = exp->display;
+	struct video_priv *vid_priv;
+	struct udevice *cons = exp->cons;
+	struct vidconsole_colour old;
+	enum colour_idx fore, back;
+
+	if (CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK)) {
+		fore = VID_BLACK;
+		back = VID_WHITE;
+	} else {
+		fore = VID_LIGHT_GRAY;
+		back = VID_BLACK;
+	}
+
+	scene_menu_calc_bbox(menu, &bbox, &label_bbox);
+	vidconsole_push_colour(cons, fore, back, &old);
+	vid_priv = dev_get_uclass_priv(dev);
+	video_fill_part(dev, label_bbox.x0 - theme->menu_inset,
+			label_bbox.y0 - theme->menu_inset,
+			label_bbox.x1, label_bbox.y1 + theme->menu_inset,
+			vid_priv->colour_fg);
+	vidconsole_pop_colour(cons, &old);
+}
+
+int scene_menu_render_deps(struct scene *scn, struct scene_obj_menu *menu)
+{
+	struct scene_menitem *item;
+
+	scene_render_deps(scn, menu->title_id);
+	scene_render_deps(scn, menu->cur_item_id);
+	scene_render_deps(scn, menu->pointer_id);
+
+	list_for_each_entry(item, &menu->item_head, sibling) {
+		scene_render_deps(scn, item->key_id);
+		scene_render_deps(scn, item->label_id);
+		scene_render_deps(scn, item->desc_id);
+	}
+
+	return 0;
+}
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 365371fb51..43ca10f69c 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -135,6 +135,14 @@ config CMD_BDI
 	help
 	  Print board info
 
+config CMD_BDINFO_EXTRA
+	bool "bdinfo extra features"
+	default y if SANDBOX || X86
+	help
+	  Show additional information about the board. This uses a little more
+	  code space but provides more options, particularly those useful for
+	  bringup, development and debugging.
+
 config CMD_CONFIG
 	bool "config"
 	default SANDBOX
@@ -362,7 +370,8 @@ config BOOTM_VXWORKS
 
 config SYS_BOOTM_LEN
 	hex "Maximum size of a decompresed OS image"
-	depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ
+	depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \
+		   LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT
 	default 0x4000000 if PPC || ARM64
 	default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7
 	default 0x800000
@@ -427,6 +436,15 @@ config CMD_ABOOTIMG
 
 	  See doc/android/boot-image.rst for details.
 
+config CMD_CEDIT
+	bool "cedit - Configuration editor"
+	depends on CEDIT
+	default y
+	help
+	  Provides a command to allow editing of board configuration and
+	  providing a UI for the user to adjust settings. Subcommands allow
+	  loading and saving of configuration as well as showing an editor.
+
 config CMD_ELF
 	bool "bootelf, bootvx"
 	default y
@@ -934,6 +952,16 @@ endmenu
 
 menu "Device access commands"
 
+config CMD_ARMFFA
+	bool "Arm FF-A test command"
+	depends on ARM_FFA_TRANSPORT
+	help
+	  Provides a test command for the FF-A support
+	  supported options:
+		- Listing the partition(s) info
+		- Sending a data pattern to the specified partition
+		- Displaying the arm_ffa device info
+
 config CMD_ARMFLASH
 	#depends on FLASH_CFI_DRIVER
 	bool "armflash"
@@ -968,6 +996,7 @@ config CMD_BCB
 config CMD_BIND
 	bool "bind/unbind - Bind or unbind a device to/from a driver"
 	depends on DM
+	default y if USB_ETHER
 	help
 	  Bind or unbind a device to/from a driver from the command line.
 	  This is useful in situations where a device may be handled by several
@@ -1227,6 +1256,7 @@ config LOADS_ECHO
 
 config CMD_SAVES
 	bool "saves - Save a file over serial in S-Record format"
+	depends on CMD_LOADS
 	help
 	  Provides a way to save a binary file using the Motorola S-Record
 	  format over the serial line.
@@ -1848,7 +1878,6 @@ config CMD_RARP
 
 config CMD_NFS
 	bool "nfs"
-	default y
 	help
 	  Boot image via network using NFS protocol.
 
@@ -1987,6 +2016,7 @@ config CMD_2048
 config CMD_BMP
 	bool "Enable 'bmp' command"
 	depends on VIDEO
+	select BMP
 	help
 	  This provides a way to obtain information about a BMP-format image
 	  and to display it. BMP (which presumably stands for BitMaP) is a
diff --git a/cmd/Makefile b/cmd/Makefile
index 6c37521b4e..9bebf321c3 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -12,6 +12,7 @@ obj-y += panic.o
 obj-y += version.o
 
 # command
+obj-$(CONFIG_CMD_ARMFFA) += armffa.o
 obj-$(CONFIG_CMD_2048) += 2048.o
 obj-$(CONFIG_CMD_ACPI) += acpi.o
 obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o
@@ -43,6 +44,7 @@ obj-$(CONFIG_CMD_BUTTON) += button.o
 obj-$(CONFIG_CMD_CAT) += cat.o
 obj-$(CONFIG_CMD_CACHE) += cache.o
 obj-$(CONFIG_CMD_CBFS) += cbfs.o
+obj-$(CONFIG_CMD_CEDIT) += cedit.o
 obj-$(CONFIG_CMD_CLK) += clk.o
 obj-$(CONFIG_CMD_CLS) += cls.o
 obj-$(CONFIG_CMD_CONFIG) += config.o
diff --git a/cmd/ab_select.c b/cmd/ab_select.c
index 3e46663d6e..bfb67b8236 100644
--- a/cmd/ab_select.c
+++ b/cmd/ab_select.c
@@ -16,10 +16,19 @@ static int do_ab_select(struct cmd_tbl *cmdtp, int flag, int argc,
 	struct blk_desc *dev_desc;
 	struct disk_partition part_info;
 	char slot[2];
+	bool dec_tries = true;
 
-	if (argc != 4)
+	if (argc < 4)
 		return CMD_RET_USAGE;
 
+	for (int i = 4; i < argc; i++) {
+		if (strcmp(argv[i], "--no-dec") == 0) {
+			dec_tries = false;
+		} else {
+			return CMD_RET_USAGE;
+		}
+	}
+
 	/* Lookup the "misc" partition from argv[2] and argv[3] */
 	if (part_get_info_by_dev_and_name_or_num(argv[2], argv[3],
 						 &dev_desc, &part_info,
@@ -27,7 +36,8 @@ static int do_ab_select(struct cmd_tbl *cmdtp, int flag, int argc,
 		return CMD_RET_FAILURE;
 	}
 
-	ret = ab_select_slot(dev_desc, &part_info);
+
+	ret = ab_select_slot(dev_desc, &part_info, dec_tries);
 	if (ret < 0) {
 		printf("Android boot failed, error %d.\n", ret);
 		return CMD_RET_FAILURE;
@@ -41,9 +51,9 @@ static int do_ab_select(struct cmd_tbl *cmdtp, int flag, int argc,
 	return CMD_RET_SUCCESS;
 }
 
-U_BOOT_CMD(ab_select, 4, 0, do_ab_select,
+U_BOOT_CMD(ab_select, 5, 0, do_ab_select,
 	   "Select the slot used to boot from and register the boot attempt.",
-	   "<slot_var_name> <interface> <dev[:part|#part_name]>\n"
+	   "<slot_var_name> <interface> <dev[:part|#part_name]> [--no-dec]\n"
 	   "    - Load the slot metadata from the partition 'part' on\n"
 	   "      device type 'interface' instance 'dev' and store the active\n"
 	   "      slot in the 'slot_var_name' variable. This also updates the\n"
@@ -53,4 +63,6 @@ U_BOOT_CMD(ab_select, 4, 0, do_ab_select,
 	   "    - If 'part_name' is passed, preceded with a # instead of :, the\n"
 	   "      partition name whose label is 'part_name' will be looked up in\n"
 	   "      the partition table. This is commonly the \"misc\" partition.\n"
+           "    - If '--no-dec' is set, the number of tries remaining will not\n"
+           "      decremented for the selected boot slot\n"
 );
diff --git a/cmd/acpi.c b/cmd/acpi.c
index e70913e40b..ede9c8c7dc 100644
--- a/cmd/acpi.c
+++ b/cmd/acpi.c
@@ -118,6 +118,22 @@ static int do_acpi_list(struct cmd_tbl *cmdtp, int flag, int argc,
 	return 0;
 }
 
+static int do_acpi_set(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	ulong val;
+
+	if (argc < 2) {
+		printf("ACPI pointer: %lx\n", gd_acpi_start());
+	} else {
+		val = hextoul(argv[1], NULL);
+		printf("Setting ACPI pointer to %lx\n", val);
+		gd_set_acpi_start(val);
+	}
+
+	return 0;
+}
+
 static int do_acpi_items(struct cmd_tbl *cmdtp, int flag, int argc,
 			 char *const argv[])
 {
@@ -157,12 +173,14 @@ static int do_acpi_dump(struct cmd_tbl *cmdtp, int flag, int argc,
 
 #ifdef CONFIG_SYS_LONGHELP
 static char acpi_help_text[] =
-	"list - list ACPI tables\n"
-	"acpi items [-d]  - List/dump each piece of ACPI data from devices\n"
-	"acpi dump <name> - Dump ACPI table";
+	"list  - list ACPI tables\n"
+	"acpi items [-d]   - List/dump each piece of ACPI data from devices\n"
+	"acpi set [<addr>] - Set or show address of ACPI tables\n"
+	"acpi dump <name>  - Dump ACPI table";
 #endif
 
 U_BOOT_CMD_WITH_SUBCMDS(acpi, "ACPI tables", acpi_help_text,
 	U_BOOT_SUBCMD_MKENT(list, 1, 1, do_acpi_list),
 	U_BOOT_SUBCMD_MKENT(items, 2, 1, do_acpi_items),
+	U_BOOT_SUBCMD_MKENT(set, 2, 1, do_acpi_set),
 	U_BOOT_SUBCMD_MKENT(dump, 2, 1, do_acpi_dump));
diff --git a/cmd/armffa.c b/cmd/armffa.c
new file mode 100644
index 0000000000..7e6eafc03a
--- /dev/null
+++ b/cmd/armffa.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+#include <common.h>
+#include <arm_ffa.h>
+#include <command.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <stdlib.h>
+#include <asm/io.h>
+
+/* Select the right physical address formatting according to the platform */
+#ifdef CONFIG_PHYS_64BIT
+#define PhysAddrLength "ll"
+#else
+#define PhysAddrLength ""
+#endif
+#define PHYS_ADDR_LN "%" PhysAddrLength "x"
+
+/**
+ * ffa_get_dev() - Return the FF-A device
+ * @devp:	pointer to the FF-A device
+ *
+ * Search for the FF-A device.
+ *
+ * Return:
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_get_dev(struct udevice **devp)
+{
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_FFA, devp);
+	if (ret) {
+		log_err("Cannot find FF-A bus device\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * do_ffa_getpart() - implementation of the getpart subcommand
+ * @cmdtp:		Command Table
+ * @flag:		flags
+ * @argc:		number of arguments
+ * @argv:		arguments
+ *
+ * Query a secure partition information. The secure partition UUID is provided
+ * as an argument. The function uses the arm_ffa driver
+ * partition_info_get operation which implements FFA_PARTITION_INFO_GET
+ * ABI to retrieve the data. The input UUID string is expected to be in big
+ * endian format.
+ *
+ * Return:
+ *
+ * CMD_RET_SUCCESS: on success, otherwise failure
+ */
+static int do_ffa_getpart(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	u32 count = 0;
+	int ret;
+	struct ffa_partition_desc *descs;
+	u32 i;
+	struct udevice *dev;
+
+	if (argc != 2) {
+		log_err("Missing argument\n");
+		return CMD_RET_USAGE;
+	}
+
+	ret = ffa_get_dev(&dev);
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	/* Ask the driver to fill the buffer with the SPs info */
+
+	ret = ffa_partition_info_get(dev, argv[1], &count, &descs);
+	if (ret) {
+		log_err("Failure in querying partition(s) info (error code: %d)\n", ret);
+		return CMD_RET_FAILURE;
+	}
+
+	/* SPs found , show the partition information */
+	for (i = 0; i < count ; i++) {
+		log_info("Partition: id = %x , exec_ctxt %x , properties %x\n",
+			 descs[i].info.id,
+			 descs[i].info.exec_ctxt,
+			 descs[i].info.properties);
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_ffa_ping() - implementation of the ping subcommand
+ * @cmdtp:		Command Table
+ * @flag:		flags
+ * @argc:		number of arguments
+ * @argv:		arguments
+ *
+ * Send data to a secure partition. The secure partition UUID is provided
+ * as an argument. Use the arm_ffa driver sync_send_receive operation
+ * which implements FFA_MSG_SEND_DIRECT_{REQ,RESP} ABIs to send/receive data.
+ *
+ * Return:
+ *
+ * CMD_RET_SUCCESS: on success, otherwise failure
+ */
+static int do_ffa_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	struct ffa_send_direct_data msg = {
+			.data0 = 0xaaaaaaaa,
+			.data1 = 0xbbbbbbbb,
+			.data2 = 0xcccccccc,
+			.data3 = 0xdddddddd,
+			.data4 = 0xeeeeeeee,
+	};
+	u16 part_id;
+	int ret;
+	struct udevice *dev;
+
+	if (argc != 2) {
+		log_err("Missing argument\n");
+		return CMD_RET_USAGE;
+	}
+
+	part_id = strtoul(argv[1], NULL, 16);
+	if (!part_id) {
+		log_err("Partition ID can not be 0\n");
+		return CMD_RET_USAGE;
+	}
+
+	ret = ffa_get_dev(&dev);
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	ret = ffa_sync_send_receive(dev, part_id, &msg, 1);
+	if (!ret) {
+		u8 cnt;
+
+		log_info("SP response:\n[LSB]\n");
+		for (cnt = 0;
+		     cnt < sizeof(struct ffa_send_direct_data) / sizeof(u64);
+		     cnt++)
+			log_info("%llx\n", ((u64 *)&msg)[cnt]);
+		return CMD_RET_SUCCESS;
+	}
+
+	log_err("Sending direct request error (%d)\n", ret);
+	return CMD_RET_FAILURE;
+}
+
+/**
+ *do_ffa_devlist() - implementation of the devlist subcommand
+ * @cmdtp: [in]		Command Table
+ * @flag:		flags
+ * @argc:		number of arguments
+ * @argv:		arguments
+ *
+ * Query the device belonging to the UCLASS_FFA
+ * class.
+ *
+ * Return:
+ *
+ * CMD_RET_SUCCESS: on success, otherwise failure
+ */
+static int do_ffa_devlist(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = ffa_get_dev(&dev);
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	log_info("device %s, addr " PHYS_ADDR_LN ", driver %s, ops " PHYS_ADDR_LN "\n",
+		 dev->name,
+		 map_to_sysmem(dev),
+		 dev->driver->name,
+		 map_to_sysmem(dev->driver->ops));
+
+	return CMD_RET_SUCCESS;
+}
+
+static char armffa_help_text[] =
+	"getpart <partition UUID>\n"
+	"       - lists the partition(s) info\n"
+	"ping <partition ID>\n"
+	"       - sends a data pattern to the specified partition\n"
+	"devlist\n"
+	"       - displays information about the FF-A device/driver\n";
+
+U_BOOT_CMD_WITH_SUBCMDS(armffa, "Arm FF-A test command", armffa_help_text,
+			U_BOOT_SUBCMD_MKENT(getpart, 2, 1, do_ffa_getpart),
+			U_BOOT_SUBCMD_MKENT(ping, 2, 1, do_ffa_ping),
+			U_BOOT_SUBCMD_MKENT(devlist, 1, 1, do_ffa_devlist));
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 365357ca54..1fe13ca13a 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -13,6 +13,7 @@
 #include <lmb.h>
 #include <mapmem.h>
 #include <net.h>
+#include <serial.h>
 #include <video.h>
 #include <vsprintf.h>
 #include <asm/cache.h>
@@ -113,6 +114,25 @@ static void show_video_info(void)
 	}
 }
 
+static void print_serial(struct udevice *dev)
+{
+	struct serial_device_info info;
+	int ret;
+
+	if (!dev || !IS_ENABLED(CONFIG_DM_SERIAL))
+		return;
+
+	ret = serial_getinfo(dev, &info);
+	if (ret)
+		return;
+
+	bdinfo_print_num_l("serial addr", info.addr);
+	bdinfo_print_num_l(" width", info.reg_width);
+	bdinfo_print_num_l(" shift", info.reg_shift);
+	bdinfo_print_num_l(" offset", info.reg_offset);
+	bdinfo_print_num_l(" clock", info.clock);
+}
+
 int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	struct bd_info *bd = gd->bd;
@@ -151,6 +171,13 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 		if (IS_ENABLED(CONFIG_OF_REAL))
 			printf("devicetree  = %s\n", fdtdec_get_srcname());
 	}
+	print_serial(gd->cur_serial_dev);
+
+	if (IS_ENABLED(CONFIG_CMD_BDINFO_EXTRA)) {
+		bdinfo_print_num_ll("stack ptr", (ulong)&bd);
+		bdinfo_print_num_ll("ram_top ptr", (ulong)gd->ram_top);
+		bdinfo_print_num_l("malloc base", gd_malloc_start());
+	}
 
 	arch_print_bdinfo();
 
diff --git a/cmd/bootdev.c b/cmd/bootdev.c
index 5b1efaaee8..a657de6bd0 100644
--- a/cmd/bootdev.c
+++ b/cmd/bootdev.c
@@ -99,7 +99,7 @@ static int do_bootdev_info(struct cmd_tbl *cmdtp, int flag, int argc,
 
 	printf("Name:      %s\n", dev->name);
 	printf("Sequence:  %d\n", dev_seq(dev));
-	printf("Status:    %s\n", ret ? simple_itoa(ret) : device_active(dev) ?
+	printf("Status:    %s\n", ret ? simple_itoa(-ret) : device_active(dev) ?
 		"Probed" : "OK");
 	printf("Uclass:    %s\n", dev_get_uclass_name(dev_get_parent(dev)));
 	printf("Bootflows: %d (%d valid)\n", i, num_valid);
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 5c0afec154..f73d6eb0e2 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -607,20 +607,6 @@ failure:
 }
 
 /**
- * bootefi_run_finish() - finish up after running an EFI test
- *
- * @loaded_image_info: Pointer to a struct which holds the loaded image info
- * @image_obj: Pointer to a struct which holds the loaded image object
- */
-static void bootefi_run_finish(struct efi_loaded_image_obj *image_obj,
-			       struct efi_loaded_image *loaded_image_info)
-{
-	efi_restore_gd();
-	free(loaded_image_info->load_options);
-	efi_delete_handle(&image_obj->header);
-}
-
-/**
  * do_efi_selftest() - execute EFI selftest
  *
  * Return:	status code
@@ -638,7 +624,12 @@ static int do_efi_selftest(void)
 
 	/* Execute the test */
 	ret = EFI_CALL(efi_selftest(&image_obj->header, &systab));
-	bootefi_run_finish(image_obj, loaded_image_info);
+	efi_restore_gd();
+	free(loaded_image_info->load_options);
+	if (ret != EFI_SUCCESS)
+		efi_delete_handle(&image_obj->header);
+	else
+		ret = efi_delete_handle(&image_obj->header);
 
 	return ret != EFI_SUCCESS;
 }
diff --git a/cmd/bootflow.c b/cmd/bootflow.c
index 5c61286a2a..c0aa4f84fe 100644
--- a/cmd/bootflow.c
+++ b/cmd/bootflow.c
@@ -288,6 +288,12 @@ static int do_bootflow_select(struct cmd_tbl *cmdtp, int flag, int argc,
 		return CMD_RET_FAILURE;
 	}
 	std->cur_bootflow = found;
+	if (IS_ENABLED(CONFIG_BOOTSTD_FULL)) {
+		if (env_set("bootargs", found->cmdline)) {
+			printf("Cannot set bootargs\n");
+			return CMD_RET_FAILURE;
+		}
+	}
 
 	return 0;
 }
@@ -324,6 +330,14 @@ static int do_bootflow_info(struct cmd_tbl *cmdtp, int flag, int argc,
 	printf("Buffer:    %lx\n", (ulong)map_to_sysmem(bflow->buf));
 	printf("Size:      %x (%d bytes)\n", bflow->size, bflow->size);
 	printf("OS:        %s\n", bflow->os_name ? bflow->os_name : "(none)");
+	printf("Cmdline:   ");
+	if (bflow->cmdline)
+		puts(bflow->cmdline);
+	else
+		puts("(none)");
+	putc('\n');
+	if (bflow->x86_setup)
+		printf("X86 setup: %p\n", bflow->x86_setup);
 	printf("Logo:      %s\n", bflow->logo ?
 	       simple_xtoa((ulong)map_to_sysmem(bflow->logo)) : "(none)");
 	if (bflow->logo) {
@@ -417,6 +431,75 @@ static int do_bootflow_menu(struct cmd_tbl *cmdtp, int flag, int argc,
 
 	return 0;
 }
+
+static int do_bootflow_cmdline(struct cmd_tbl *cmdtp, int flag, int argc,
+			       char *const argv[])
+{
+	struct bootstd_priv *std;
+	struct bootflow *bflow;
+	const char *op, *arg, *val = NULL;
+	int ret;
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	ret = bootstd_get_priv(&std);
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	bflow = std->cur_bootflow;
+	if (!bflow) {
+		printf("No bootflow selected\n");
+		return CMD_RET_FAILURE;
+	}
+
+	op = argv[1];
+	arg = argv[2];
+	if (*op == 's') {
+		if (argc < 4)
+			return CMD_RET_USAGE;
+		val = argv[3];
+	}
+
+	switch (*op) {
+	case 'c':	/* clear */
+		val = "";
+		fallthrough;
+	case 's':	/* set */
+	case 'd':	/* delete */
+		ret = bootflow_cmdline_set_arg(bflow, arg, val, true);
+		break;
+	case 'g':	/* get */
+		ret = bootflow_cmdline_get_arg(bflow, arg, &val);
+		if (ret >= 0)
+			printf("%.*s\n", ret, val);
+		break;
+	case 'a':	/* auto */
+		ret = bootflow_cmdline_auto(bflow, arg);
+		break;
+	}
+	switch (ret) {
+	case -E2BIG:
+		printf("Argument too long\n");
+		break;
+	case -ENOENT:
+		printf("Argument not found\n");
+		break;
+	case -EINVAL:
+		printf("Mismatched quotes\n");
+		break;
+	case -EBADF:
+		printf("Value must be quoted\n");
+		break;
+	default:
+		if (ret < 0)
+			printf("Unknown error: %dE\n", ret);
+	}
+	if (ret < 0)
+		return CMD_RET_FAILURE;
+
+	return 0;
+}
 #endif /* CONFIG_CMD_BOOTFLOW_FULL */
 
 #ifdef CONFIG_SYS_LONGHELP
@@ -427,7 +510,8 @@ static char bootflow_help_text[] =
 	"bootflow select [<num>|<name>] - select a bootflow\n"
 	"bootflow info [-d]             - show info on current bootflow (-d dump bootflow)\n"
 	"bootflow boot                  - boot current bootflow (or first available if none selected)\n"
-	"bootflow menu [-t]             - show a menu of available bootflows";
+	"bootflow menu [-t]             - show a menu of available bootflows\n"
+	"bootflow cmdline [set|get|clear|delete|auto] <param> [<value>] - update cmdline";
 #else
 	"scan - boot first available bootflow\n";
 #endif
@@ -441,5 +525,6 @@ U_BOOT_CMD_WITH_SUBCMDS(bootflow, "Boot flows", bootflow_help_text,
 	U_BOOT_SUBCMD_MKENT(info, 2, 1, do_bootflow_info),
 	U_BOOT_SUBCMD_MKENT(boot, 1, 1, do_bootflow_boot),
 	U_BOOT_SUBCMD_MKENT(menu, 2, 1, do_bootflow_menu),
+	U_BOOT_SUBCMD_MKENT(cmdline, 4, 1, do_bootflow_cmdline),
 #endif
 );
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index 6baeedc69f..987b16889f 100644
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -351,8 +351,8 @@ static struct bootmenu_data *bootmenu_create(int delay)
 		 * UEFI specification requires booting from removal media using
 		 * a architecture-specific default image name such as BOOTAA64.EFI.
 		 */
-		efi_ret = eficonfig_generate_media_device_boot_option();
-		if (efi_ret != EFI_SUCCESS && efi_ret != EFI_NOT_FOUND)
+		efi_ret = efi_bootmgr_update_media_device_boot_option();
+		if (efi_ret != EFI_SUCCESS)
 			goto cleanup;
 
 		ret = prepare_uefi_bootorder_entry(menu, &iter, &i);
diff --git a/cmd/cat.c b/cmd/cat.c
index 1273a26b14..b059080193 100644
--- a/cmd/cat.c
+++ b/cmd/cat.c
@@ -17,8 +17,8 @@ static int do_cat(struct cmd_tbl *cmdtp, int flag, int argc,
 	char *dev;
 	char *file;
 	char *buffer;
-	phys_addr_t addr;
-	loff_t file_size;
+	ulong file_size;
+	int ret;
 
 	if (argc < 4)
 		return CMD_RET_USAGE;
@@ -27,40 +27,27 @@ static int do_cat(struct cmd_tbl *cmdtp, int flag, int argc,
 	dev = argv[2];
 	file = argv[3];
 
+	ret = fs_load_alloc(ifname, dev, file, 0, 0, (void **)&buffer,
+			    &file_size);
+
 	// check file exists
-	if (fs_set_blk_dev(ifname, dev, FS_TYPE_ANY))
+	switch (ret) {
+	case 0:
+		break;
+	case -ENOMEDIUM:
 		return CMD_RET_FAILURE;
-
-	if (!fs_exists(file)) {
+	case -ENOENT:
 		log_err("File does not exist: ifname=%s dev=%s file=%s\n", ifname, dev, file);
 		return CMD_RET_FAILURE;
-	}
-
-	// get file size
-	if (fs_set_blk_dev(ifname, dev, FS_TYPE_ANY))
+	case -E2BIG:
+		log_err("File is too large: ifname=%s dev=%s file=%s\n", ifname, dev, file);
 		return CMD_RET_FAILURE;
-
-	if (fs_size(file, &file_size)) {
-		log_err("Cannot read file size: ifname=%s dev=%s file=%s\n", ifname, dev, file);
+	case -ENOMEM:
+		log_err("Not enough memory: ifname=%s dev=%s file=%s\n", ifname, dev, file);
 		return CMD_RET_FAILURE;
-	}
-
-	// allocate memory for file content
-	buffer = calloc(sizeof(char), file_size + 1);
-	if (!buffer) {
-		log_err("Out of memory\n");
-		return CMD_RET_FAILURE;
-	}
-
-	// map pointer to system memory
-	addr = map_to_sysmem(buffer);
-
-	// read file to memory
-	if (fs_set_blk_dev(ifname, dev, FS_TYPE_ANY))
-		return CMD_RET_FAILURE;
-
-	if (fs_read(file, addr, 0, 0, &file_size)) {
-		log_err("Cannot read file: ifname=%s dev=%s file=%s\n", ifname, dev, file);
+	default:
+	case -EIO:
+		log_err("File-read failed: ifname=%s dev=%s file=%s\n", ifname, dev, file);
 		return CMD_RET_FAILURE;
 	}
 
diff --git a/cmd/cedit.c b/cmd/cedit.c
new file mode 100644
index 0000000000..0cae304c4a
--- /dev/null
+++ b/cmd/cedit.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * 'cedit' command
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <expo.h>
+#include <fs.h>
+#include <dm/ofnode.h>
+#include <linux/sizes.h>
+
+struct expo *cur_exp;
+
+static int do_cedit_load(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	const char *fname;
+	struct expo *exp;
+	oftree tree;
+	ulong size;
+	void *buf;
+	int ret;
+
+	if (argc < 4)
+		return CMD_RET_USAGE;
+	fname = argv[3];
+
+	ret = fs_load_alloc(argv[1], argv[2], argv[3], SZ_1M, 0, &buf, &size);
+	if (ret) {
+		printf("File not found\n");
+		return CMD_RET_FAILURE;
+	}
+
+	tree = oftree_from_fdt(buf);
+	if (!oftree_valid(tree)) {
+		printf("Cannot create oftree\n");
+		return CMD_RET_FAILURE;
+	}
+
+	ret = expo_build(oftree_root(tree), &exp);
+	oftree_dispose(tree);
+	if (ret) {
+		printf("Failed to build expo: %dE\n", ret);
+		return CMD_RET_FAILURE;
+	}
+
+	cur_exp = exp;
+
+	return 0;
+}
+
+static int do_cedit_run(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	ofnode node;
+	int ret;
+
+	if (!cur_exp) {
+		printf("No expo loaded\n");
+		return CMD_RET_FAILURE;
+	}
+
+	node = ofnode_path("/cedit-theme");
+	if (ofnode_valid(node)) {
+		ret = expo_apply_theme(cur_exp, node);
+		if (ret)
+			return CMD_RET_FAILURE;
+	} else {
+		log_warning("No theme found\n");
+	}
+	ret = cedit_run(cur_exp);
+	if (ret) {
+		log_err("Failed (err=%dE)\n", ret);
+		return CMD_RET_FAILURE;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char cedit_help_text[] =
+	"load <interface> <dev[:part]> <filename>   - load config editor\n"
+	"cedit run                                        - run config editor";
+#endif /* CONFIG_SYS_LONGHELP */
+
+U_BOOT_CMD_WITH_SUBCMDS(cedit, "Configuration editor", cedit_help_text,
+	U_BOOT_SUBCMD_MKENT(load, 5, 1, do_cedit_load),
+	U_BOOT_SUBCMD_MKENT(run, 1, 1, do_cedit_run),
+);
diff --git a/cmd/cyclic.c b/cmd/cyclic.c
index 97324d8240..946f1d7818 100644
--- a/cmd/cyclic.c
+++ b/cmd/cyclic.c
@@ -77,7 +77,7 @@ static int do_cyclic_list(struct cmd_tbl *cmdtp, int flag, int argc,
 }
 
 static char cyclic_help_text[] =
-	"cyclic demo <cycletime_ms> <delay_us> - register cyclic demo function\n"
+	"demo <cycletime_ms> <delay_us> - register cyclic demo function\n"
 	"cyclic list - list cyclic functions\n";
 
 U_BOOT_CMD_WITH_SUBCMDS(cyclic, "Cyclic", cyclic_help_text,
diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
index 720f52b48b..e6e8a0a488 100644
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -1135,43 +1135,6 @@ out:
 }
 
 /**
- * eficonfig_get_unused_bootoption() - get unused "Boot####" index
- *
- * @buf:	pointer to the buffer to store boot option variable name
- * @buf_size:	buffer size
- * @index:	pointer to store the index in the BootOrder variable
- * Return:	status code
- */
-efi_status_t eficonfig_get_unused_bootoption(u16 *buf, efi_uintn_t buf_size,
-					     unsigned int *index)
-{
-	u32 i;
-	efi_status_t ret;
-	efi_uintn_t size;
-
-	if (buf_size < u16_strsize(u"Boot####"))
-		return EFI_BUFFER_TOO_SMALL;
-
-	for (i = 0; i <= 0xFFFF; i++) {
-		size = 0;
-		efi_create_indexed_name(buf, buf_size, "Boot", i);
-		ret = efi_get_variable_int(buf, &efi_global_variable_guid,
-					   NULL, &size, NULL, NULL);
-		if (ret == EFI_BUFFER_TOO_SMALL)
-			continue;
-		else
-			break;
-	}
-
-	if (i > 0xFFFF)
-		return EFI_OUT_OF_RESOURCES;
-
-	*index = i;
-
-	return EFI_SUCCESS;
-}
-
-/**
  * eficonfig_set_boot_option() - set boot option
  *
  * @varname:		pointer to variable name
@@ -1209,46 +1172,6 @@ static efi_status_t eficonfig_set_boot_option(u16 *varname, struct efi_device_pa
 }
 
 /**
- * eficonfig_append_bootorder() - append new boot option in BootOrder variable
- *
- * @index:	"Boot####" index to append to BootOrder variable
- * Return:	status code
- */
-efi_status_t eficonfig_append_bootorder(u16 index)
-{
-	u16 *bootorder;
-	efi_status_t ret;
-	u16 *new_bootorder = NULL;
-	efi_uintn_t last, size, new_size;
-
-	/* append new boot option */
-	bootorder = efi_get_var(u"BootOrder", &efi_global_variable_guid, &size);
-	last = size / sizeof(u16);
-	new_size = size + sizeof(u16);
-	new_bootorder = calloc(1, new_size);
-	if (!new_bootorder) {
-		ret = EFI_OUT_OF_RESOURCES;
-		goto out;
-	}
-	memcpy(new_bootorder, bootorder, size);
-	new_bootorder[last] = index;
-
-	ret = efi_set_variable_int(u"BootOrder", &efi_global_variable_guid,
-				   EFI_VARIABLE_NON_VOLATILE |
-				   EFI_VARIABLE_BOOTSERVICE_ACCESS |
-				   EFI_VARIABLE_RUNTIME_ACCESS,
-				   new_size, new_bootorder, false);
-	if (ret != EFI_SUCCESS)
-		goto out;
-
-out:
-	free(bootorder);
-	free(new_bootorder);
-
-	return ret;
-}
-
-/**
  * create_boot_option_entry() - create boot option entry
  *
  * @efi_menu:	pointer to the efimenu structure
@@ -1619,7 +1542,7 @@ static efi_status_t eficonfig_process_add_boot_option(void *data)
 	if (!bo)
 		return EFI_OUT_OF_RESOURCES;
 
-	ret = eficonfig_get_unused_bootoption(varname, sizeof(varname), &bo->boot_index);
+	ret = efi_bootmgr_get_unused_bootoption(varname, sizeof(varname), &bo->boot_index);
 	if (ret != EFI_SUCCESS)
 		return ret;
 
@@ -1627,7 +1550,7 @@ static efi_status_t eficonfig_process_add_boot_option(void *data)
 	if (ret != EFI_SUCCESS)
 		goto out;
 
-	ret = eficonfig_append_bootorder((u16)bo->boot_index);
+	ret = efi_bootmgr_append_bootorder((u16)bo->boot_index);
 	if (ret != EFI_SUCCESS)
 		goto out;
 
@@ -1657,31 +1580,6 @@ static efi_status_t eficonfig_process_boot_selected(void *data)
 }
 
 /**
- * search_bootorder() - search the boot option index in BootOrder
- *
- * @bootorder:	pointer to the BootOrder variable
- * @num:	number of BootOrder entry
- * @target:	target boot option index to search
- * @index:	pointer to store the index of BootOrder variable
- * Return:	true if exists, false otherwise
- */
-static bool search_bootorder(u16 *bootorder, efi_uintn_t num, u32 target, u32 *index)
-{
-	u32 i;
-
-	for (i = 0; i < num; i++) {
-		if (target == bootorder[i]) {
-			if (index)
-				*index = i;
-
-			return true;
-		}
-	}
-
-	return false;
-}
-
-/**
  * eficonfig_add_boot_selection_entry() - add boot option menu entry
  *
  * @efi_menu:	pointer to store the efimenu structure
@@ -1805,7 +1703,7 @@ static efi_status_t eficonfig_show_boot_selection(unsigned int *selected)
 
 		if (efi_varname_is_load_option(var_name16, &index)) {
 			/* If the index is included in the BootOrder, skip it */
-			if (search_bootorder(bootorder, num, index, NULL))
+			if (efi_search_bootorder(bootorder, num, index, NULL))
 				continue;
 
 			ret = eficonfig_add_boot_selection_entry(efi_menu, index, selected);
@@ -2202,7 +2100,7 @@ static efi_status_t eficonfig_create_change_boot_order_entry(struct efimenu *efi
 
 		if (efi_varname_is_load_option(var_name16, &index)) {
 			/* If the index is included in the BootOrder, skip it */
-			if (search_bootorder(bootorder, num, index, NULL))
+			if (efi_search_bootorder(bootorder, num, index, NULL))
 				continue;
 
 			ret = eficonfig_add_change_boot_order_entry(efi_menu, index, false);
@@ -2305,50 +2203,6 @@ out:
 }
 
 /**
- * delete_boot_option() - delete selected boot option
- *
- * @boot_index:	boot option index to delete
- * Return:	status code
- */
-static efi_status_t delete_boot_option(u16 boot_index)
-{
-	u16 *bootorder;
-	u16 varname[9];
-	efi_status_t ret;
-	unsigned int index;
-	efi_uintn_t num, size;
-
-	efi_create_indexed_name(varname, sizeof(varname),
-				"Boot", boot_index);
-	ret = efi_set_variable_int(varname, &efi_global_variable_guid,
-				   0, 0, NULL, false);
-	if (ret != EFI_SUCCESS) {
-		log_err("delete boot option(%ls) failed\n", varname);
-		return ret;
-	}
-
-	/* update BootOrder if necessary */
-	bootorder = efi_get_var(u"BootOrder", &efi_global_variable_guid, &size);
-	if (!bootorder)
-		return EFI_SUCCESS;
-
-	num = size / sizeof(u16);
-	if (!search_bootorder(bootorder, num, boot_index, &index))
-		return EFI_SUCCESS;
-
-	memmove(&bootorder[index], &bootorder[index + 1],
-		(num - index - 1) * sizeof(u16));
-	size -= sizeof(u16);
-	ret = efi_set_variable_int(u"BootOrder", &efi_global_variable_guid,
-				   EFI_VARIABLE_NON_VOLATILE |
-				   EFI_VARIABLE_BOOTSERVICE_ACCESS |
-				   EFI_VARIABLE_RUNTIME_ACCESS,
-				   size, bootorder, false);
-
-	return ret;
-}
-
-/**
  * eficonfig_process_delete_boot_option() - handler to delete boot option
  *
  * @data:	pointer to the data for each entry
@@ -2362,7 +2216,7 @@ static efi_status_t eficonfig_process_delete_boot_option(void *data)
 	while (1) {
 		ret = eficonfig_show_boot_selection(&selected);
 		if (ret == EFI_SUCCESS)
-			ret = delete_boot_option(selected);
+			ret = efi_bootmgr_delete_boot_option(selected);
 
 		if (ret != EFI_SUCCESS)
 			break;
@@ -2375,256 +2229,6 @@ static efi_status_t eficonfig_process_delete_boot_option(void *data)
 }
 
 /**
- * eficonfig_enumerate_boot_option() - enumerate the possible bootable media
- *
- * @opt:		pointer to the media boot option structure
- * @volume_handles:	pointer to the efi handles
- * @count:		number of efi handle
- * Return:		status code
- */
-efi_status_t eficonfig_enumerate_boot_option(struct eficonfig_media_boot_option *opt,
-					     efi_handle_t *volume_handles, efi_status_t count)
-{
-	u32 i;
-	struct efi_handler *handler;
-	efi_status_t ret = EFI_SUCCESS;
-
-	for (i = 0; i < count; i++) {
-		u16 *p;
-		u16 dev_name[BOOTMENU_DEVICE_NAME_MAX];
-		char *optional_data;
-		struct efi_load_option lo;
-		char buf[BOOTMENU_DEVICE_NAME_MAX];
-		struct efi_device_path *device_path;
-
-		ret = efi_search_protocol(volume_handles[i], &efi_guid_device_path, &handler);
-		if (ret != EFI_SUCCESS)
-			continue;
-		ret = efi_protocol_open(handler, (void **)&device_path,
-					efi_root, NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL);
-		if (ret != EFI_SUCCESS)
-			continue;
-
-		ret = efi_disk_get_device_name(volume_handles[i], buf, BOOTMENU_DEVICE_NAME_MAX);
-		if (ret != EFI_SUCCESS)
-			continue;
-
-		p = dev_name;
-		utf8_utf16_strncpy(&p, buf, strlen(buf));
-
-		lo.label = dev_name;
-		lo.attributes = LOAD_OPTION_ACTIVE;
-		lo.file_path = device_path;
-		lo.file_path_length = efi_dp_size(device_path) + sizeof(END);
-		/*
-		 * Set the dedicated guid to optional_data, it is used to identify
-		 * the boot option that automatically generated by the bootmenu.
-		 * efi_serialize_load_option() expects optional_data is null-terminated
-		 * utf8 string, so set the "1234567" string to allocate enough space
-		 * to store guid, instead of realloc the load_option.
-		 */
-		lo.optional_data = "1234567";
-		opt[i].size = efi_serialize_load_option(&lo, (u8 **)&opt[i].lo);
-		if (!opt[i].size) {
-			ret = EFI_OUT_OF_RESOURCES;
-			goto out;
-		}
-		/* set the guid */
-		optional_data = (char *)opt[i].lo + (opt[i].size - u16_strsize(u"1234567"));
-		memcpy(optional_data, &efi_guid_bootmenu_auto_generated, sizeof(efi_guid_t));
-	}
-
-out:
-	return ret;
-}
-
-/**
- * eficonfig_delete_invalid_boot_option() - delete non-existing boot option
- *
- * @opt:		pointer to the media boot option structure
- * @count:		number of media boot option structure
- * Return:		status code
- */
-efi_status_t eficonfig_delete_invalid_boot_option(struct eficonfig_media_boot_option *opt,
-						  efi_status_t count)
-{
-	efi_uintn_t size;
-	void *load_option;
-	u32 i, list_size = 0;
-	struct efi_load_option lo;
-	u16 *var_name16 = NULL;
-	u16 varname[] = u"Boot####";
-	efi_status_t ret = EFI_SUCCESS;
-	u16 *delete_index_list = NULL, *p;
-	efi_uintn_t buf_size;
-
-	buf_size = 128;
-	var_name16 = malloc(buf_size);
-	if (!var_name16)
-		return EFI_OUT_OF_RESOURCES;
-
-	var_name16[0] = 0;
-	for (;;) {
-		int index;
-		efi_guid_t guid;
-		efi_uintn_t tmp;
-
-		ret = efi_next_variable_name(&buf_size, &var_name16, &guid);
-		if (ret == EFI_NOT_FOUND) {
-			/*
-			 * EFI_NOT_FOUND indicates we retrieved all EFI variables.
-			 * This should be treated as success.
-			 */
-			ret = EFI_SUCCESS;
-			break;
-		}
-		if (ret != EFI_SUCCESS)
-			goto out;
-
-		if (!efi_varname_is_load_option(var_name16, &index))
-			continue;
-
-		efi_create_indexed_name(varname, sizeof(varname), "Boot", index);
-		load_option = efi_get_var(varname, &efi_global_variable_guid, &size);
-		if (!load_option)
-			continue;
-
-		tmp = size;
-		ret = efi_deserialize_load_option(&lo, load_option, &size);
-		if (ret != EFI_SUCCESS)
-			goto next;
-
-		if (size >= sizeof(efi_guid_bootmenu_auto_generated) &&
-		    !guidcmp(lo.optional_data, &efi_guid_bootmenu_auto_generated)) {
-			for (i = 0; i < count; i++) {
-				if (opt[i].size == tmp &&
-				    memcmp(opt[i].lo, load_option, tmp) == 0) {
-					opt[i].exist = true;
-					break;
-				}
-			}
-
-			/*
-			 * The entire list of variables must be retrieved by
-			 * efi_get_next_variable_name_int() before deleting the invalid
-			 * boot option, just save the index here.
-			 */
-			if (i == count) {
-				p = realloc(delete_index_list, sizeof(u32) *
-					    (list_size + 1));
-				if (!p) {
-					ret = EFI_OUT_OF_RESOURCES;
-					goto out;
-				}
-				delete_index_list = p;
-				delete_index_list[list_size++] = index;
-			}
-		}
-next:
-		free(load_option);
-	}
-
-	/* delete all invalid boot options */
-	for (i = 0; i < list_size; i++) {
-		ret = delete_boot_option(delete_index_list[i]);
-		if (ret != EFI_SUCCESS)
-			goto out;
-	}
-
-out:
-	free(var_name16);
-	free(delete_index_list);
-
-	return ret;
-}
-
-/**
- * eficonfig_generate_media_device_boot_option() - generate the media device boot option
- *
- * This function enumerates all devices supporting EFI_SIMPLE_FILE_SYSTEM_PROTOCOL
- * and generate the bootmenu entries.
- * This function also provide the BOOT#### variable maintenance for
- * the media device entries.
- *   - Automatically create the BOOT#### variable for the newly detected device,
- *     this BOOT#### variable is distinguished by the special GUID
- *     stored in the EFI_LOAD_OPTION.optional_data
- *   - If the device is not attached to the system, the associated BOOT#### variable
- *     is automatically deleted.
- *
- * Return:	status code
- */
-efi_status_t eficonfig_generate_media_device_boot_option(void)
-{
-	u32 i;
-	efi_status_t ret;
-	efi_uintn_t count;
-	efi_handle_t *volume_handles = NULL;
-	struct eficonfig_media_boot_option *opt = NULL;
-
-	ret = efi_locate_handle_buffer_int(BY_PROTOCOL, &efi_simple_file_system_protocol_guid,
-					   NULL, &count, (efi_handle_t **)&volume_handles);
-	if (ret != EFI_SUCCESS)
-		return ret;
-
-	opt = calloc(count, sizeof(struct eficonfig_media_boot_option));
-	if (!opt)
-		goto out;
-
-	/* enumerate all devices supporting EFI_SIMPLE_FILE_SYSTEM_PROTOCOL */
-	ret = eficonfig_enumerate_boot_option(opt, volume_handles, count);
-	if (ret != EFI_SUCCESS)
-		goto out;
-
-	/*
-	 * System hardware configuration may vary depending on the user setup.
-	 * The boot option is automatically added by the bootmenu.
-	 * If the device is not attached to the system, the boot option needs
-	 * to be deleted.
-	 */
-	ret = eficonfig_delete_invalid_boot_option(opt, count);
-	if (ret != EFI_SUCCESS)
-		goto out;
-
-	/* add non-existent boot option */
-	for (i = 0; i < count; i++) {
-		u32 boot_index;
-		u16 var_name[9];
-
-		if (!opt[i].exist) {
-			ret = eficonfig_get_unused_bootoption(var_name, sizeof(var_name),
-							      &boot_index);
-			if (ret != EFI_SUCCESS)
-				goto out;
-
-			ret = efi_set_variable_int(var_name, &efi_global_variable_guid,
-						   EFI_VARIABLE_NON_VOLATILE |
-						   EFI_VARIABLE_BOOTSERVICE_ACCESS |
-						   EFI_VARIABLE_RUNTIME_ACCESS,
-						   opt[i].size, opt[i].lo, false);
-			if (ret != EFI_SUCCESS)
-				goto out;
-
-			ret = eficonfig_append_bootorder(boot_index);
-			if (ret != EFI_SUCCESS) {
-				efi_set_variable_int(var_name, &efi_global_variable_guid,
-						     0, 0, NULL, false);
-				goto out;
-			}
-		}
-	}
-
-out:
-	if (opt) {
-		for (i = 0; i < count; i++)
-			free(opt[i].lo);
-	}
-	free(opt);
-	efi_free_pool(volume_handles);
-
-	return ret;
-}
-
-/**
  * eficonfig_init() - do required initialization for eficonfig command
  *
  * Return:	status code
@@ -2709,8 +2313,8 @@ static int do_eficonfig(struct cmd_tbl *cmdtp, int flag, int argc, char *const a
 	if (ret != EFI_SUCCESS)
 		return CMD_RET_FAILURE;
 
-	ret = eficonfig_generate_media_device_boot_option();
-	if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
+	ret = efi_bootmgr_update_media_device_boot_option();
+	if (ret != EFI_SUCCESS)
 		return ret;
 
 	while (1) {
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 9622430c47..0be3af3e76 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -486,6 +486,7 @@ static int do_efi_show_handles(struct cmd_tbl *cmdtp, int flag,
 			if (guidcmp(guid[j], &efi_guid_device_path))
 				printf("  %pUs\n", guid[j]);
 		}
+		efi_free_pool(guid);
 	}
 
 	efi_free_pool(handles);
diff --git a/cmd/fdt.c b/cmd/fdt.c
index aae3278526..2401ea8b44 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -733,7 +733,7 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 
 		gd->fdt_blob = blob;
 		cfg_noffset = fit_conf_get_node(working_fdt, NULL);
-		if (!cfg_noffset) {
+		if (cfg_noffset < 0) {
 			printf("Could not find configuration node: %s\n",
 			       fdt_strerror(cfg_noffset));
 			return CMD_RET_FAILURE;
diff --git a/cmd/fs.c b/cmd/fs.c
index 5ad11647c2..6044f73af5 100644
--- a/cmd/fs.c
+++ b/cmd/fs.c
@@ -20,7 +20,7 @@ U_BOOT_CMD(
 	"determine a file's size",
 	"<interface> <dev[:part]> <filename>\n"
 	"    - Find file 'filename' from 'dev' on 'interface'\n"
-	"      and determine its size."
+	"      determine its size, and store in the 'filesize' variable."
 );
 
 static int do_load_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/cmd/fwu_mdata.c b/cmd/fwu_mdata.c
index f04af27de6..5ecda455df 100644
--- a/cmd/fwu_mdata.c
+++ b/cmd/fwu_mdata.c
@@ -43,23 +43,10 @@ static void print_mdata(struct fwu_mdata *mdata)
 int do_fwu_mdata_read(struct cmd_tbl *cmdtp, int flag,
 		     int argc, char * const argv[])
 {
-	struct udevice *dev;
 	int ret = CMD_RET_SUCCESS, res;
-	struct fwu_mdata mdata = { 0 };
+	struct fwu_mdata mdata;
 
-	if (uclass_get_device(UCLASS_FWU_MDATA, 0, &dev) || !dev) {
-		log_err("Unable to get FWU metadata device\n");
-		return CMD_RET_FAILURE;
-	}
-
-	res = fwu_check_mdata_validity();
-	if (res < 0) {
-		log_err("FWU Metadata check failed\n");
-		ret = CMD_RET_FAILURE;
-		goto out;
-	}
-
-	res = fwu_get_mdata(dev, &mdata);
+	res = fwu_get_mdata(&mdata);
 	if (res < 0) {
 		log_err("Unable to get valid FWU metadata\n");
 		ret = CMD_RET_FAILURE;
diff --git a/cmd/ini.c b/cmd/ini.c
index 81dfc4c4e8..35de2373e6 100644
--- a/cmd/ini.c
+++ b/cmd/ini.c
@@ -89,7 +89,7 @@ static char *memgets(char *str, int num, char **mem, size_t *memsize)
 		end = *mem + *memsize;
 		newline = 0;
 	}
-	len = min((end - *mem) + newline, num);
+	len = min((int)(end - *mem) + newline, num);
 	memcpy(str, *mem, len);
 	if (len < num)
 		str[len] = '\0';
diff --git a/cmd/legacy-mtd-utils.c b/cmd/legacy-mtd-utils.c
index ac7139f84d..5903a90fe5 100644
--- a/cmd/legacy-mtd-utils.c
+++ b/cmd/legacy-mtd-utils.c
@@ -88,6 +88,11 @@ int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off,
 		return -1;
 	}
 
+	if (*size == 0) {
+		debug("ERROR: Invalid size 0\n");
+		return -1;
+	}
+
 print:
 	printf("device %d ", *idx);
 	if (*size == chipsize)
diff --git a/cmd/load.c b/cmd/load.c
index 5c4f34781d..2715cf5957 100644
--- a/cmd/load.c
+++ b/cmd/load.c
@@ -181,13 +181,17 @@ static ulong load_serial(long offset)
 		    } else
 #endif
 		    {
+			void *dst;
+
 			ret = lmb_reserve(&lmb, store_addr, binlen);
 			if (ret) {
 				printf("\nCannot overwrite reserved area (%08lx..%08lx)\n",
 					store_addr, store_addr + binlen);
 				return ret;
 			}
-			memcpy((char *)(store_addr), binbuf, binlen);
+			dst = map_sysmem(store_addr, binlen);
+			memcpy(dst, binbuf, binlen);
+			unmap_sysmem(dst);
 			lmb_free(&lmb, store_addr, binlen);
 		    }
 		    if ((store_addr) < start_addr)
@@ -350,15 +354,19 @@ static int save_serial(ulong address, ulong count)
 	if(write_record(SREC3_START))			/* write the header */
 		return (-1);
 	do {
-		if(count) {						/* collect hex data in the buffer  */
-			c = *(volatile uchar*)(address + reclen);	/* get one byte    */
-			checksum += c;							/* accumulate checksum */
+		volatile uchar *src;
+
+		src = map_sysmem(address, count);
+		if (count) {				/* collect hex data in the buffer */
+			c = src[reclen];		/* get one byte */
+			checksum += c;			/* accumulate checksum */
 			data[2*reclen]   = hex[(c>>4)&0x0f];
 			data[2*reclen+1] = hex[c & 0x0f];
 			data[2*reclen+2] = '\0';
 			++reclen;
 			--count;
 		}
+		unmap_sysmem((void *)src);
 		if(reclen == SREC_BYTES_PER_RECORD || count == 0) {
 			/* enough data collected for one record: dump it */
 			if(reclen) {	/* build & write a data record: */
diff --git a/cmd/mbr.c b/cmd/mbr.c
index c269833eb8..ec99b66283 100644
--- a/cmd/mbr.c
+++ b/cmd/mbr.c
@@ -244,7 +244,7 @@ static int do_verify_mbr(struct blk_desc *dev, const char *str)
 	for (i = 0; i < count; i++) {
 		struct disk_partition p;
 
-		if (part_get_info(dev, i + 1, &p))
+		if (part_get_info_by_type(dev, i + 1, PART_TYPE_DOS, &p))
 			goto fail;
 
 		if ((partitions[i].size && p.size != partitions[i].size) ||
diff --git a/cmd/net.c b/cmd/net.c
index 9e1f40a56e..d407d8320a 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -13,6 +13,7 @@
 #include <bootstage.h>
 #include <command.h>
 #include <dm.h>
+#include <dm/devres.h>
 #include <env.h>
 #include <image.h>
 #include <log.h>
@@ -691,8 +692,58 @@ static int do_net_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const ar
 	return CMD_RET_SUCCESS;
 }
 
+static int do_net_stats(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int nstats, err, i, off;
+	struct udevice *dev;
+	u64 *values;
+	u8 *strings;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	err = uclass_get_device_by_name(UCLASS_ETH, argv[1], &dev);
+	if (err) {
+		printf("Could not find device %s\n", argv[1]);
+		return CMD_RET_FAILURE;
+	}
+
+	if (!eth_get_ops(dev)->get_sset_count ||
+	    !eth_get_ops(dev)->get_strings ||
+	    !eth_get_ops(dev)->get_stats) {
+		printf("Driver does not implement stats dump!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	nstats = eth_get_ops(dev)->get_sset_count(dev);
+	strings = kcalloc(nstats, ETH_GSTRING_LEN, GFP_KERNEL);
+	if (!strings)
+		return CMD_RET_FAILURE;
+
+	values = kcalloc(nstats, sizeof(u64), GFP_KERNEL);
+	if (!values)
+		goto err_free_strings;
+
+	eth_get_ops(dev)->get_strings(dev, strings);
+	eth_get_ops(dev)->get_stats(dev, values);
+
+	off = 0;
+	for (i = 0; i < nstats; i++) {
+		printf("  %s: %llu\n", &strings[off], values[i]);
+		off += ETH_GSTRING_LEN;
+	};
+
+	return CMD_RET_SUCCESS;
+
+err_free_strings:
+	kfree(strings);
+
+	return CMD_RET_FAILURE;
+}
+
 static struct cmd_tbl cmd_net[] = {
 	U_BOOT_CMD_MKENT(list, 1, 0, do_net_list, "", ""),
+	U_BOOT_CMD_MKENT(stats, 2, 0, do_net_stats, "", ""),
 };
 
 static int do_net(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
@@ -714,9 +765,10 @@ static int do_net(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 }
 
 U_BOOT_CMD(
-	net, 2, 1, do_net,
+	net, 3, 1, do_net,
 	"NET sub-system",
 	"list - list available devices\n"
+	"stats <device> - dump statistics for specified device\n"
 );
 
 #if defined(CONFIG_CMD_NCSI)
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 12eae0627b..9e4ee4b017 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -43,28 +43,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if	defined(CONFIG_ENV_IS_IN_EEPROM)	|| \
-	defined(CONFIG_ENV_IS_IN_FLASH)		|| \
-	defined(CONFIG_ENV_IS_IN_MMC)		|| \
-	defined(CONFIG_ENV_IS_IN_FAT)		|| \
-	defined(CONFIG_ENV_IS_IN_EXT4)		|| \
-	defined(CONFIG_ENV_IS_IN_NAND)		|| \
-	defined(CONFIG_ENV_IS_IN_NVRAM)		|| \
-	defined(CONFIG_ENV_IS_IN_ONENAND)	|| \
-	defined(CONFIG_ENV_IS_IN_SPI_FLASH)	|| \
-	defined(CONFIG_ENV_IS_IN_REMOTE)	|| \
-	defined(CONFIG_ENV_IS_IN_UBI)
-
-#define ENV_IS_IN_DEVICE
-
-#endif
-
-#if	!defined(ENV_IS_IN_DEVICE)		&& \
-	!defined(CONFIG_ENV_IS_NOWHERE)
-# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|\
-NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
-#endif
-
 /*
  * Maximum expected input data size for import command
  */
@@ -596,7 +574,7 @@ static int do_env_edit(struct cmd_tbl *cmdtp, int flag, int argc,
 }
 #endif /* CONFIG_CMD_EDITENV */
 
-#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
+#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT)
 static int do_env_save(struct cmd_tbl *cmdtp, int flag, int argc,
 		       char *const argv[])
 {
@@ -1105,7 +1083,7 @@ static int do_env_info(struct cmd_tbl *cmdtp, int flag,
 	int eval_flags = 0;
 	int eval_results = 0;
 	bool quiet = false;
-#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
+#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT)
 	enum env_location loc;
 #endif
 
@@ -1148,7 +1126,7 @@ static int do_env_info(struct cmd_tbl *cmdtp, int flag,
 
 	/* evaluate whether environment can be persisted */
 	if (eval_flags & ENV_INFO_IS_PERSISTED) {
-#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
+#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT)
 		loc = env_get_location(ENVOP_SAVE, gd->env_load_prio);
 		if (ENVL_NOWHERE != loc && ENVL_UNKNOWN != loc) {
 			if (!quiet)
@@ -1229,7 +1207,7 @@ static struct cmd_tbl cmd_env_sub[] = {
 #if defined(CONFIG_CMD_RUN)
 	U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""),
 #endif
-#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
+#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT)
 	U_BOOT_CMD_MKENT(save, 1, 0, do_env_save, "", ""),
 #if defined(CONFIG_CMD_ERASEENV)
 	U_BOOT_CMD_MKENT(erase, 1, 0, do_env_erase, "", ""),
@@ -1320,7 +1298,7 @@ static char env_help_text[] =
 #if defined(CONFIG_CMD_RUN)
 	"env run var [...] - run commands in an environment variable\n"
 #endif
-#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
+#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT)
 	"env save - save environment\n"
 #if defined(CONFIG_CMD_ERASEENV)
 	"env erase - erase environment\n"
diff --git a/cmd/part.c b/cmd/part.c
index 28f2b7ff9b..0ce190005d 100644
--- a/cmd/part.c
+++ b/cmd/part.c
@@ -182,6 +182,36 @@ static int do_part_number(int argc, char *const argv[])
 	return do_part_info(argc, argv, CMD_PART_INFO_NUMBER);
 }
 
+static int do_part_set(int argc, char *const argv[])
+{
+	const char *devname, *partstr, *typestr;
+	struct blk_desc *desc;
+	int dev;
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	/* Look up the device */
+	devname = argv[0];
+	partstr = argv[1];
+	typestr = argv[2];
+	dev = blk_get_device_by_str(devname, partstr, &desc);
+	if (dev < 0) {
+		printf("** Bad device specification %s %s **\n", devname,
+		       partstr);
+		return CMD_RET_FAILURE;
+	}
+
+	desc->part_type = part_get_type_by_name(typestr);
+	if (!desc->part_type) {
+		printf("Unknown partition type '%s'\n", typestr);
+		return CMD_RET_FAILURE;
+	}
+	part_print(desc);
+
+	return 0;
+}
+
 #ifdef CONFIG_PARTITION_TYPE_GUID
 static int do_part_type(int argc, char *const argv[])
 {
@@ -245,6 +275,8 @@ static int do_part(struct cmd_tbl *cmdtp, int flag, int argc,
 		return do_part_number(argc - 2, argv + 2);
 	else if (!strcmp(argv[1], "types"))
 		return do_part_types(argc - 2, argv + 2);
+	else if (!strcmp(argv[1], "set"))
+		return do_part_set(argc - 2, argv + 2);
 #ifdef CONFIG_PARTITION_TYPE_GUID
 	else if (!strcmp(argv[1], "type"))
 		return do_part_type(argc - 2, argv + 2);
@@ -279,6 +311,8 @@ U_BOOT_CMD(
 #endif
 	"part type <interface> <dev>:<part> <varname>\n"
 	"    - set environment variable to partition type\n"
+	"part set <interface> <dev> type\n"
+	"    - set partition type for a device\n"
 	"part types\n"
 	"    - list supported partition table types"
 );
diff --git a/cmd/qfw.c b/cmd/qfw.c
index ae3c6a7a84..d6ecfa60d5 100644
--- a/cmd/qfw.c
+++ b/cmd/qfw.c
@@ -26,7 +26,7 @@ static int qemu_fwcfg_cmd_list_firmware(void)
 	for (file = qfw_file_iter_init(qfw_dev, &iter);
 	     !qfw_file_iter_end(&iter);
 	     file = qfw_file_iter_next(&iter)) {
-		printf("%-56s\n", file->cfg.name);
+		printf("%08lx %-56s\n", file->addr, file->cfg.name);
 	}
 
 	return 0;
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index 6f2cad4e7e..32761c595e 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -27,6 +27,8 @@ static struct sbi_imp implementations[] = {
 	{ 4, "RustSBI" },
 	{ 5, "Diosix" },
 	{ 6, "Coffer" },
+	{ 7, "Xen Project" },
+	{ 8, "PolarFire Hart Software Services" },
 };
 
 static struct sbi_ext extensions[] = {
@@ -46,6 +48,11 @@ static struct sbi_ext extensions[] = {
 	{ SBI_EXT_HSM,			      "Hart State Management Extension" },
 	{ SBI_EXT_SRST,			      "System Reset Extension" },
 	{ SBI_EXT_PMU,			      "Performance Monitoring Unit Extension" },
+	{ SBI_EXT_DBCN,			      "Debug Console Extension" },
+	{ SBI_EXT_SUSP,			      "System Suspend Extension" },
+	{ SBI_EXT_CPPC,			      "Collaborative Processor Performance Control Extension" },
+	{ SBI_EXT_NACL,			      "Nested Acceleration Extension" },
+	{ SBI_EXT_STA,			      "Steal-time Accounting Extension" },
 };
 
 static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/cmd/sf.c b/cmd/sf.c
index 11b9c25896..55bef2f769 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -353,6 +353,11 @@ static int do_spi_flash_erase(int argc, char *const argv[])
 	if (ret != 1)
 		return CMD_RET_USAGE;
 
+	if (size == 0) {
+		debug("ERROR: Invalid size 0\n");
+		return CMD_RET_FAILURE;
+	}
+
 	/* Consistency checking */
 	if (offset + size > flash->size) {
 		printf("ERROR: attempting %s past flash size (%#x)\n",
diff --git a/cmd/tpm-common.c b/cmd/tpm-common.c
index d0c63cadf4..a7dc23d85d 100644
--- a/cmd/tpm-common.c
+++ b/cmd/tpm-common.c
@@ -11,6 +11,7 @@
 #include <asm/unaligned.h>
 #include <linux/string.h>
 #include <tpm-common.h>
+#include <tpm_api.h>
 #include "tpm-user-utils.h"
 
 static struct udevice *tpm_dev;
@@ -367,6 +368,21 @@ int do_tpm_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 	return report_return_code(tpm_init(dev));
 }
 
+int do_tpm_autostart(struct cmd_tbl *cmdtp, int flag, int argc,
+		     char *const argv[])
+{
+	struct udevice *dev;
+	int rc;
+
+	if (argc != 1)
+		return CMD_RET_USAGE;
+	rc = get_tpm(&dev);
+	if (rc)
+		return rc;
+
+	return report_return_code(tpm_auto_start(dev));
+}
+
 int do_tpm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	struct cmd_tbl *tpm_commands, *cmd;
diff --git a/cmd/tpm-user-utils.h b/cmd/tpm-user-utils.h
index de4a934aab..dfa11353e1 100644
--- a/cmd/tpm-user-utils.h
+++ b/cmd/tpm-user-utils.h
@@ -20,6 +20,7 @@ int get_tpm(struct udevice **devp);
 int do_tpm_device(struct cmd_tbl *cmdtp, int flag, int argc,
 		  char *const argv[]);
 int do_tpm_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+int do_tpm_autostart(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
 int do_tpm_info(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
 int do_tpm_report_state(struct cmd_tbl *cmdtp, int flag, int argc,
 			char *const argv[]);
diff --git a/cmd/tpm-v1.c b/cmd/tpm-v1.c
index 0efb079b0a..3b95c950cc 100644
--- a/cmd/tpm-v1.c
+++ b/cmd/tpm-v1.c
@@ -655,6 +655,7 @@ TPM_COMMAND_NO_ARG(tpm_physical_disable)
 static struct cmd_tbl tpm1_commands[] = {
 	U_BOOT_CMD_MKENT(device, 0, 1, do_tpm_device, "", ""),
 	U_BOOT_CMD_MKENT(info, 0, 1, do_tpm_info, "", ""),
+	U_BOOT_CMD_MKENT(init, 0, 1, do_tpm_autostart, "", ""),
 	U_BOOT_CMD_MKENT(init, 0, 1, do_tpm_init, "", ""),
 	U_BOOT_CMD_MKENT(startup, 0, 1,
 			 do_tpm_startup, "", ""),
@@ -733,9 +734,12 @@ U_BOOT_CMD(tpm, CONFIG_SYS_MAXARGS, 1, do_tpm,
 "  device [num device]\n"
 "    - Show all devices or set the specified device\n"
 "  info - Show information about the TPM\n"
+"  autostart\n"
+"    - Initalize the tpm, perform a Startup(clear) and run a full selftest\n"
+"      sequence\n"
 "  init\n"
 "    - Put TPM into a state where it waits for 'startup' command.\n"
-"  startup mode\n"
+"      startup mode\n"
 "    - Issue TPM_Starup command.  <mode> is one of TPM_ST_CLEAR,\n"
 "      TPM_ST_STATE, and TPM_ST_DEACTIVATED.\n"
 "Admin Testing Commands:\n"
diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c
index d93b83ada9..7e479b9dfe 100644
--- a/cmd/tpm-v2.c
+++ b/cmd/tpm-v2.c
@@ -370,6 +370,7 @@ static struct cmd_tbl tpm2_commands[] = {
 	U_BOOT_CMD_MKENT(dam_reset, 0, 1, do_tpm_dam_reset, "", ""),
 	U_BOOT_CMD_MKENT(dam_parameters, 0, 1, do_tpm_dam_parameters, "", ""),
 	U_BOOT_CMD_MKENT(change_auth, 0, 1, do_tpm_change_auth, "", ""),
+	U_BOOT_CMD_MKENT(autostart, 0, 1, do_tpm_autostart, "", ""),
 	U_BOOT_CMD_MKENT(pcr_setauthpolicy, 0, 1,
 			 do_tpm_pcr_setauthpolicy, "", ""),
 	U_BOOT_CMD_MKENT(pcr_setauthvalue, 0, 1,
@@ -392,8 +393,13 @@ U_BOOT_CMD(tpm2, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command",
 "    Show information about the TPM.\n"
 "state\n"
 "    Show internal state from the TPM (if available)\n"
+"autostart\n"
+"    Initalize the tpm, perform a Startup(clear) and run a full selftest\n"
+"    sequence\n"
 "init\n"
 "    Initialize the software stack. Always the first command to issue.\n"
+"    'tpm startup' is the only acceptable command after a 'tpm init' has been\n"
+"    issued\n"
 "startup <mode>\n"
 "    Issue a TPM2_Startup command.\n"
 "    <mode> is one of:\n"
diff --git a/cmd/ubi.c b/cmd/ubi.c
index b61ae1efea..0a6a80bdd1 100644
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -653,7 +653,7 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 
 	if (strcmp(argv[1], "list") == 0) {
 		int numeric = 0;
-		if (argc >= 2 && argv[2][0] == '-') {
+		if (argc >= 3 && argv[2][0] == '-') {
 			if (strcmp(argv[2], "-numeric") == 0)
 				numeric = 1;
 			else
diff --git a/cmd/ufs.c b/cmd/ufs.c
index d4a1e66c1b..143e946370 100644
--- a/cmd/ufs.c
+++ b/cmd/ufs.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /**
- * ufs.c - UFS specific U-boot commands
+ * ufs.c - UFS specific U-Boot commands
  *
  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
  *
diff --git a/cmd/version.c b/cmd/version.c
index 190ef6a906..87e1fa4159 100644
--- a/cmd/version.c
+++ b/cmd/version.c
@@ -19,6 +19,8 @@
 	U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING
 
 const char version_string[] = U_BOOT_VERSION_STRING;
+const unsigned short version_num = U_BOOT_VERSION_NUM;
+const unsigned char version_num_patch = U_BOOT_VERSION_NUM_PATCH;
 
 static int do_version(struct cmd_tbl *cmdtp, int flag, int argc,
 		      char *const argv[])
diff --git a/cmd/x86/cbsysinfo.c b/cmd/x86/cbsysinfo.c
index 2b8d3b0a43..84822a3e32 100644
--- a/cmd/x86/cbsysinfo.c
+++ b/cmd/x86/cbsysinfo.c
@@ -190,8 +190,9 @@ static void show_table(struct sysinfo_t *info, bool verbose)
 	struct cb_serial *ser = info->serial;
 	int i;
 
-	printf("Coreboot table at %lx, decoded to %p",
-	       gd->arch.coreboot_table, info);
+	printf("Coreboot table at %lx, size %x, records %x (dec %d), decoded to %p",
+	       gd->arch.coreboot_table, info->table_size, info->rec_count,
+	       info->rec_count, info);
 	if (info->header)
 		printf(", forwarded to %p\n", info->header);
 	printf("\n");
diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c
index b1691d8b65..6ad7a123a4 100644
--- a/cmd/x86/mtrr.c
+++ b/cmd/x86/mtrr.c
@@ -10,71 +10,19 @@
 #include <asm/mp.h>
 #include <asm/mtrr.h>
 
-static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
-	"Uncacheable",
-	"Combine",
-	"2",
-	"3",
-	"Through",
-	"Protect",
-	"Back",
-};
-
-static void read_mtrrs(void *arg)
-{
-	struct mtrr_info *info = arg;
-
-	mtrr_read_all(info);
-}
-
-static int do_mtrr_list(int reg_count, int cpu_select)
-{
-	struct mtrr_info info;
-	int ret;
-	int i;
-
-	printf("Reg Valid Write-type   %-16s %-16s %-16s\n", "Base   ||",
-	       "Mask   ||", "Size   ||");
-	memset(&info, '\0', sizeof(info));
-	ret = mp_run_on_cpus(cpu_select, read_mtrrs, &info);
-	if (ret)
-		return log_msg_ret("run", ret);
-	for (i = 0; i < reg_count; i++) {
-		const char *type = "Invalid";
-		uint64_t base, mask, size;
-		bool valid;
-
-		base = info.mtrr[i].base;
-		mask = info.mtrr[i].mask;
-		size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
-		size |= (1 << 12) - 1;
-		size += 1;
-		valid = mask & MTRR_PHYS_MASK_VALID;
-		type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
-		printf("%d   %-5s %-12s %016llx %016llx %016llx\n", i,
-		       valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
-		       mask & ~MTRR_PHYS_MASK_VALID, size);
-	}
-
-	return 0;
-}
-
 static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[])
 {
 	const char *typename = argv[0];
 	uint32_t start, size;
 	uint64_t base, mask;
-	int i, type = -1;
+	int type = -1;
 	bool valid;
 	int ret;
 
 	if (argc < 3)
 		return CMD_RET_USAGE;
-	for (i = 0; i < MTRR_TYPE_COUNT; i++) {
-		if (*typename == *mtrr_type_name[i])
-			type = i;
-	}
-	if (type == -1) {
+	type = mtrr_get_type_by_name(typename);
+	if (type < 0) {
 		printf("Invalid type name %s\n", typename);
 		return CMD_RET_USAGE;
 	}
@@ -146,7 +94,7 @@ static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc,
 			if (!first)
 				printf("\n");
 			printf("CPU %d:\n", i);
-			ret = do_mtrr_list(reg_count, i);
+			ret = mtrr_list(reg_count, i);
 			if (ret) {
 				printf("Failed to read CPU %s (err=%d)\n",
 				       i < MP_SELECT_ALL ? simple_itoa(i) : "",
diff --git a/common/Kconfig b/common/Kconfig
index bbabadb35e..cdb77a6a7d 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -226,7 +226,7 @@ config CONSOLE_FLUSH_SUPPORT
 
 config CONSOLE_MUX
 	bool "Enable console multiplexing"
-	default y if VIDEO || VIDEO || LCD
+	default y if VIDEO || LCD
 	help
 	  This allows multiple devices to be used for each console 'file'.
 	  For example, stdout can be set to go to serial and video.
@@ -256,6 +256,7 @@ config SYS_CONSOLE_OVERWRITE_ROUTINE
 
 config SYS_CONSOLE_ENV_OVERWRITE
 	bool "Update environment variables during console init"
+	depends on SYS_CONSOLE_IS_IN_ENV
 	help
 	  The console environment variables (stdout, stdin, stderr) can be
 	  used to determine the correct console devices on start-up. This
@@ -935,12 +936,22 @@ config ANDROID_AB
 	  allows a bootloader to try a new version of the system but roll back
 	  to previous version if the new one didn't boot all the way.
 
+config ANDROID_AB_BACKUP_OFFSET
+	hex "Offset of backup bootloader control"
+	depends on ANDROID_AB
+	default 0x0
+	help
+	  If non-zero, a backup bootloader message starting at this offset in
+	  the partition will tried in the event that the primary one (starting
+	  at offset 0) fails its checksum.
+
 endmenu
 
 menu "Blob list"
 
 config BLOBLIST
 	bool "Support for a bloblist"
+	select CRC32
 	help
 	  This enables support for a bloblist in U-Boot, which can be passed
 	  from TPL to SPL to U-Boot proper (and potentially to Linux). The
@@ -951,6 +962,7 @@ config BLOBLIST
 config SPL_BLOBLIST
 	bool "Support for a bloblist in SPL"
 	depends on BLOBLIST && SPL_LIBGENERIC_SUPPORT && SPL_LIBCOMMON_SUPPORT
+	select SPL_CRC32
 	default y if SPL
 	help
 	  This enables a bloblist in SPL. If this is the first part of U-Boot
@@ -960,6 +972,7 @@ config SPL_BLOBLIST
 config TPL_BLOBLIST
 	bool "Support for a bloblist in TPL"
 	depends on BLOBLIST && TPL_LIBGENERIC_SUPPORT && TPL_LIBCOMMON_SUPPORT
+	select TPL_CRC32
 	default y if TPL
 	help
 	  This enables a bloblist in TPL. The bloblist is set up in TPL and
@@ -1157,12 +1170,11 @@ config IO_TRACE
 
 config BMP
 	bool "Enable bmp image display"
-	default y if CMD_BMP
 	help
 	  Enable bmp functions to display bmp image and get bmp info.
 
 config SPL_BMP
-	bool "Enable bmp image display at  SPL"
+	bool "Enable bmp image display at SPL"
 	depends on SPL_VIDEO
 	help
 	  Enable bmp functions to display bmp image and get bmp info at SPL.
diff --git a/common/Makefile b/common/Makefile
index c87bb2e78b..f5c3d90f06 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -79,7 +79,7 @@ endif # CONFIG_SPL_BUILD
 obj-$(CONFIG_CROS_EC) += cros_ec.o
 obj-y += dlmalloc.o
 ifdef CONFIG_SYS_MALLOC_F
-ifneq ($(CONFIG_$(SPL_TPL_)SYS_MALLOC_F_LEN),0)
+ifneq ($(CONFIG_$(SPL_TPL_)SYS_MALLOC_F_LEN),0x0)
 obj-y += malloc_simple.o
 endif
 endif
diff --git a/common/bloblist.c b/common/bloblist.c
index 0d63b6e881..2144b10e1d 100644
--- a/common/bloblist.c
+++ b/common/bloblist.c
@@ -51,6 +51,7 @@ static struct tag_name {
 
 	/* BLOBLISTT_PROJECT_AREA */
 	{ BLOBLISTT_U_BOOT_SPL_HANDOFF, "SPL hand-off" },
+	{ BLOBLISTT_U_BOOT_VIDEO, "SPL video handoff" },
 
 	/* BLOBLISTT_VENDOR_AREA */
 };
diff --git a/common/board_f.c b/common/board_f.c
index 1688e27071..e9f4edb93d 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -330,7 +330,7 @@ __weak int mach_cpu_init(void)
 }
 
 /* Get the top of usable RAM */
-__weak phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+__weak phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 #if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0
 	/*
@@ -411,7 +411,15 @@ __weak int arch_reserve_mmu(void)
 
 static int reserve_video(void)
 {
-	if (IS_ENABLED(CONFIG_VIDEO)) {
+	if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() > PHASE_SPL) {
+		struct video_handoff *ho;
+
+		ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho));
+		if (!ho)
+			return log_msg_ret("blf", -ENOENT);
+		video_reserve_from_bloblist(ho);
+		gd->relocaddr = ho->fb;
+	} else if (CONFIG_IS_ENABLED(VIDEO)) {
 		ulong addr;
 		int ret;
 
@@ -633,8 +641,6 @@ static int init_post(void)
 static int reloc_fdt(void)
 {
 	if (!IS_ENABLED(CONFIG_OF_EMBED)) {
-		if (gd->flags & GD_FLG_SKIP_RELOC)
-			return 0;
 		if (gd->new_fdt) {
 			memcpy(gd->new_fdt, gd->fdt_blob,
 			       fdt_totalsize(gd->fdt_blob));
@@ -731,8 +737,7 @@ static int fix_fdt(void)
 #endif
 
 /* ARM calls relocate_code from its crt0.S */
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
-		!CONFIG_IS_ENABLED(X86_64)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
 
 static int jump_to_copy(void)
 {
@@ -754,7 +759,11 @@ static int jump_to_copy(void)
 	 * (CPU cache)
 	 */
 	arch_setup_gd(gd->new_gd);
-	board_init_f_r_trampoline(gd->start_addr_sp);
+# if CONFIG_IS_ENABLED(X86_64)
+		board_init_f_r_trampoline64(gd->new_gd, gd->start_addr_sp);
+# else
+		board_init_f_r_trampoline(gd->start_addr_sp);
+# endif
 #else
 	relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
 #endif
@@ -969,8 +978,7 @@ static const init_fnc_t init_sequence_f[] = {
 	 * watchdog device is not serviced is as small as possible.
 	 */
 	cyclic_unregister_all,
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
-		!CONFIG_IS_ENABLED(X86_64)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
 	jump_to_copy,
 #endif
 	NULL,
diff --git a/common/board_r.c b/common/board_r.c
index d798c00a80..4aaa894031 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -196,7 +196,7 @@ static int initr_barrier(void)
 
 static int initr_malloc(void)
 {
-	ulong malloc_start;
+	ulong start;
 
 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
 	debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
@@ -207,8 +207,9 @@ static int initr_malloc(void)
 	 * This value MUST match the value of gd->start_addr_sp in board_f.c:
 	 * reserve_noncached().
 	 */
-	malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN;
-	mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN),
+	start = gd->relocaddr - TOTAL_MALLOC_LEN;
+	gd_set_malloc_start(start);
+	mem_malloc_init((ulong)map_sysmem(start, TOTAL_MALLOC_LEN),
 			TOTAL_MALLOC_LEN);
 	return 0;
 }
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 171069f5f4..cee87249bc 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -324,7 +324,7 @@ typedef struct {
 /* I can almost use ordinary FILE *.  Is open_memstream() universally
  * available?  Where is it documented? */
 struct in_str {
-	const char *p;
+	const unsigned char *p;
 #ifndef __U_BOOT__
 	char peek_buf[2];
 #endif
diff --git a/common/console.c b/common/console.c
index 71ad8efd6f..98c3ee6ca6 100644
--- a/common/console.c
+++ b/common/console.c
@@ -1010,29 +1010,41 @@ int console_init_f(void)
 	return 0;
 }
 
-void stdio_print_current_devices(void)
+static void stdio_print_current_devices(void)
 {
-	/* Print information */
-	puts("In:    ");
-	if (stdio_devices[stdin] == NULL) {
-		puts("No input devices available!\n");
+	char *stdinname, *stdoutname, *stderrname;
+
+	if (CONFIG_IS_ENABLED(CONSOLE_MUX) &&
+	    CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV)) {
+		/* stdin stdout and stderr are in environment */
+		stdinname  = env_get("stdin");
+		stdoutname = env_get("stdout");
+		stderrname = env_get("stderr");
+
+		stdinname = stdinname ? : "No input devices available!";
+		stdoutname = stdoutname ? : "No output devices available!";
+		stderrname = stderrname ? : "No error devices available!";
 	} else {
-		printf ("%s\n", stdio_devices[stdin]->name);
+		stdinname = stdio_devices[stdin] ?
+			stdio_devices[stdin]->name :
+			"No input devices available!";
+		stdoutname = stdio_devices[stdout] ?
+			stdio_devices[stdout]->name :
+			"No output devices available!";
+		stderrname = stdio_devices[stderr] ?
+			stdio_devices[stderr]->name :
+			"No error devices available!";
 	}
 
+	/* Print information */
+	puts("In:    ");
+	printf("%s\n", stdinname);
+
 	puts("Out:   ");
-	if (stdio_devices[stdout] == NULL) {
-		puts("No output devices available!\n");
-	} else {
-		printf ("%s\n", stdio_devices[stdout]->name);
-	}
+	printf("%s\n", stdoutname);
 
 	puts("Err:   ");
-	if (stdio_devices[stderr] == NULL) {
-		puts("No error devices available!\n");
-	} else {
-		printf ("%s\n", stdio_devices[stderr]->name);
-	}
+	printf("%s\n", stderrname);
 }
 
 #if CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV)
diff --git a/common/event.c b/common/event.c
index 164c95f8f5..3224e28122 100644
--- a/common/event.c
+++ b/common/event.c
@@ -27,7 +27,7 @@ const char *const type_name[] = {
 	"test",
 
 	/* Events related to driver model */
-	"dm_post_init",
+	"dm_post_init_f",
 	"dm_pre_probe",
 	"dm_post_probe",
 	"dm_pre_remove",
@@ -36,6 +36,9 @@ const char *const type_name[] = {
 	/* init hooks */
 	"misc_init_f",
 
+	/* Fpga load hook */
+	"fpga_load",
+
 	/* fdt hooks */
 	"ft_fixup",
 
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 2053fe3bad..5e49078f8c 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -13,6 +13,7 @@
 #include <mapmem.h>
 #include <net.h>
 #include <stdio_dev.h>
+#include <dm/ofnode.h>
 #include <linux/ctype.h>
 #include <linux/types.h>
 #include <asm/global_data.h>
@@ -1050,6 +1051,79 @@ void fdt_fixup_mtdparts(void *blob, const struct node_info *node_info,
 }
 #endif
 
+int fdt_copy_fixed_partitions(void *blob)
+{
+	ofnode node, subnode;
+	int off, suboff, res;
+	char path[256];
+	int address_cells, size_cells;
+	u8 i, j, child_count;
+
+	node = ofnode_by_compatible(ofnode_null(), "fixed-partitions");
+	while (ofnode_valid(node)) {
+		/* copy the U-Boot fixed partition */
+		address_cells = ofnode_read_simple_addr_cells(node);
+		size_cells = ofnode_read_simple_size_cells(node);
+
+		res = ofnode_get_path(ofnode_get_parent(node), path, sizeof(path));
+		if (res)
+			return res;
+
+		off = fdt_path_offset(blob, path);
+		if (off < 0)
+			return -ENODEV;
+
+		off = fdt_find_or_add_subnode(blob, off, "partitions");
+		res = fdt_setprop_string(blob, off, "compatible", "fixed-partitions");
+		if (res)
+			return res;
+
+		res = fdt_setprop_u32(blob, off, "#address-cells", address_cells);
+		if (res)
+			return res;
+
+		res = fdt_setprop_u32(blob, off, "#size-cells", size_cells);
+		if (res)
+			return res;
+
+		/*
+		 * parse partition in reverse order as fdt_find_or_add_subnode() only
+		 * insert the new node after the parent's properties
+		 */
+		child_count = ofnode_get_child_count(node);
+		for (i = child_count; i > 0 ; i--) {
+			subnode = ofnode_first_subnode(node);
+			if (!ofnode_valid(subnode))
+				break;
+
+			for (j = 0; (j < i - 1); j++)
+				subnode = ofnode_next_subnode(subnode);
+
+			if (!ofnode_valid(subnode))
+				break;
+
+			const u32 *reg;
+			int len;
+
+			suboff = fdt_find_or_add_subnode(blob, off, ofnode_get_name(subnode));
+			res = fdt_setprop_string(blob, suboff, "label",
+						 ofnode_read_string(subnode, "label"));
+			if (res)
+				return res;
+
+			reg = ofnode_get_property(subnode, "reg", &len);
+			res = fdt_setprop(blob, suboff, "reg", reg, len);
+			if (res)
+				return res;
+		}
+
+		/* go to next fixed-partitions node */
+		node = ofnode_by_compatible(node, "fixed-partitions");
+	}
+
+	return 0;
+}
+
 void fdt_del_node_and_alias(void *blob, const char *alias)
 {
 	int off = fdt_path_offset(blob, alias);
@@ -1065,7 +1139,6 @@ void fdt_del_node_and_alias(void *blob, const char *alias)
 
 /* Max address size we deal with */
 #define OF_MAX_ADDR_CELLS	4
-#define OF_BAD_ADDR	FDT_ADDR_T_NONE
 #define OF_CHECK_COUNTS(na, ns)	((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
 			(ns) > 0)
 
diff --git a/common/hash.c b/common/hash.c
index 9a52d6073c..cbffdfd6db 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -586,6 +586,8 @@ int hash_command(const char *algo_name, int flags, struct cmd_tbl *cmdtp,
 
 		output = memalign(ARCH_DMA_MINALIGN,
 				  sizeof(uint32_t) * HASH_MAX_DIGEST_SIZE);
+		if (!output)
+			return CMD_RET_FAILURE;
 
 		buf = map_sysmem(addr, len);
 		algo->hash_func_ws(buf, len, output, algo->chunk_size);
@@ -602,6 +604,7 @@ int hash_command(const char *algo_name, int flags, struct cmd_tbl *cmdtp,
 					flags & HASH_FLAG_ENV)) {
 				printf("ERROR: %s does not contain a valid "
 					"%s sum\n", *argv, algo->name);
+				free(output);
 				return 1;
 			}
 			if (memcmp(output, vsum, algo->digest_size) != 0) {
@@ -612,6 +615,7 @@ int hash_command(const char *algo_name, int flags, struct cmd_tbl *cmdtp,
 				for (i = 0; i < algo->digest_size; i++)
 					printf("%02x", vsum[i]);
 				puts(" ** ERROR **\n");
+				free(output);
 				return 1;
 			}
 		} else {
@@ -622,10 +626,10 @@ int hash_command(const char *algo_name, int flags, struct cmd_tbl *cmdtp,
 				store_result(algo, output, *argv,
 					flags & HASH_FLAG_ENV);
 			}
-		unmap_sysmem(output);
-
 		}
 
+		free(output);
+
 	/* Horrible code size hack for boards that just want crc32 */
 	} else {
 		ulong crc;
diff --git a/common/init/board_init.c b/common/init/board_init.c
index 96ffb79a98..ab8c508ad8 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -162,6 +162,9 @@ void board_init_f_init_reserve(ulong base)
 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
 	/* go down one 'early malloc arena' */
 	gd->malloc_base = base;
+#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
+	memset((void *)base, '\0', CONFIG_VAL(SYS_MALLOC_F_LEN));
+#endif
 #endif
 
 	if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
diff --git a/common/log.c b/common/log.c
index 7cfc49bc28..b2de57fcb3 100644
--- a/common/log.c
+++ b/common/log.c
@@ -31,6 +31,7 @@ static const char *const log_cat_name[] = {
 	"boot",
 	"event",
 	"fs",
+	"expo",
 };
 
 _Static_assert(ARRAY_SIZE(log_cat_name) == LOGC_COUNT - LOGC_NONE,
@@ -436,7 +437,7 @@ int log_init(void)
 	/*
 	 * We cannot add runtime data to the driver since it is likely stored
 	 * in rodata. Instead, set up a 'device' corresponding to each driver.
-	 * We only support having a single device.
+	 * We only support having a single device for each driver.
 	 */
 	INIT_LIST_HEAD((struct list_head *)&gd->log_head);
 	while (drv < end) {
diff --git a/common/log_console.c b/common/log_console.c
index f1dcc04b97..bb091ce21a 100644
--- a/common/log_console.c
+++ b/common/log_console.c
@@ -37,8 +37,14 @@ static int log_console_emit(struct log_device *ldev, struct log_rec *rec)
 			printf("%s:", rec->file);
 		if (fmt & BIT(LOGF_LINE))
 			printf("%d-", rec->line);
-		if (fmt & BIT(LOGF_FUNC))
-			printf("%*s()", CONFIG_LOGF_FUNC_PAD, rec->func);
+		if (fmt & BIT(LOGF_FUNC)) {
+			if (CONFIG_IS_ENABLED(USE_TINY_PRINTF)) {
+				printf("%s()", rec->func);
+			} else {
+				printf("%*s()", CONFIG_LOGF_FUNC_PAD,
+				       rec->func);
+			}
+		}
 	}
 	if (fmt & BIT(LOGF_MSG))
 		printf("%s%s", add_space ? " " : "", rec->msg);
diff --git a/common/memsize.c b/common/memsize.c
index 66d5be6a1f..d646df8b04 100644
--- a/common/memsize.c
+++ b/common/memsize.c
@@ -7,9 +7,18 @@
 #include <common.h>
 #include <init.h>
 #include <asm/global_data.h>
+#include <cpu_func.h>
+#include <stdint.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+# define MEMSIZE_CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
+#else
+/* Just use the greatest cache flush alignment requirement I'm aware of */
+# define MEMSIZE_CACHELINE_SIZE 128
+#endif
+
 #ifdef __PPC__
 /*
  * At least on G2 PowerPC cores, sequential accesses to non-existent
@@ -20,6 +29,15 @@ DECLARE_GLOBAL_DATA_PTR;
 # define sync()		/* nothing */
 #endif
 
+static void dcache_flush_invalidate(volatile long *p)
+{
+	uintptr_t start, stop;
+	start = ALIGN_DOWN((uintptr_t)p, MEMSIZE_CACHELINE_SIZE);
+	stop = start + MEMSIZE_CACHELINE_SIZE;
+	flush_dcache_range(start, stop);
+	invalidate_dcache_range(start, stop);
+}
+
 /*
  * Check memory range for valid RAM. A simple memory test determines
  * the actually available RAM size between addresses `base' and
@@ -34,6 +52,7 @@ long get_ram_size(long *base, long maxsize)
 	long           val;
 	long           size;
 	int            i = 0;
+	int            dcache_en = dcache_status();
 
 	for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
 		addr = base + cnt;	/* pointer arith! */
@@ -41,6 +60,8 @@ long get_ram_size(long *base, long maxsize)
 		save[i++] = *addr;
 		sync();
 		*addr = ~cnt;
+		if (dcache_en)
+			dcache_flush_invalidate(addr);
 	}
 
 	addr = base;
@@ -50,6 +71,9 @@ long get_ram_size(long *base, long maxsize)
 	*addr = 0;
 
 	sync();
+	if (dcache_en)
+		dcache_flush_invalidate(addr);
+
 	if ((val = *addr) != 0) {
 		/* Restore the original data before leaving the function. */
 		sync();
diff --git a/common/menu.c b/common/menu.c
index 94514177e4..b55cf7b999 100644
--- a/common/menu.c
+++ b/common/menu.c
@@ -15,7 +15,7 @@
 
 #include "menu.h"
 
-#define ansi 0
+#define ansi 1
 
 /*
  * Internally, each item in a menu is represented by a struct menu_item.
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 2c042ad306..c5dd476db5 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -550,29 +550,6 @@ config SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION
 	  the eMMC EXT_CSC_PART_CONFIG selection should be overridden in SPL
 	  by user defined partition number.
 
-config SPL_CRC32
-	bool "Support CRC32"
-	default y if SPL_LEGACY_IMAGE_FORMAT || SPL_EFI_PARTITION
-	default y if SPL_ENV_SUPPORT || TPL_BLOBLIST
-	help
-	  Enable this to support CRC32 in uImages or FIT images within SPL.
-	  This is a 32-bit checksum value that can be used to verify images.
-	  For FIT images, this is the least secure type of checksum, suitable
-	  for detected accidental image corruption. For secure applications you
-	  should consider SHA1 or SHA256.
-
-config SPL_MD5
-	bool "Support MD5"
-	depends on SPL_FIT
-	help
-	  Enable this to support MD5 in FIT images within SPL. An MD5
-	  checksum is a 128-bit hash value used to check that the image
-	  contents have not been corrupted. Note that MD5 is not considered
-	  secure as it is possible (with a brute-force attack) to adjust the
-	  image while still retaining the same MD5 hash value. For secure
-	  applications where images may be changed maliciously, you should
-	  consider SHA256 or SHA384.
-
 config SPL_FIT_IMAGE_TINY
 	bool "Remove functionality from SPL FIT loading to reduce size"
 	depends on SPL_FIT
@@ -1263,6 +1240,33 @@ config SPL_SATA_RAW_U_BOOT_SECTOR
 	  Sector on the SATA disk to load U-Boot from, when the SATA disk is being
 	  used in raw mode. Units: SATA disk sectors (1 sector = 512 bytes).
 
+config SPL_NVME
+	bool "NVM Express device support"
+	depends on BLK
+	select HAVE_BLOCK_DEVICE
+	select FS_LOADER
+	select SPL_BLK_FS
+	help
+	  This option enables support for NVM Express devices.
+	  It supports basic functions of NVMe (read/write).
+
+config SPL_NVME_PCI
+	bool "NVM Express PCI device support for SPL"
+	depends on SPL_PCI && SPL_NVME
+	help
+	  This option enables support for NVM Express PCI devices.
+	  This allows use of NVMe devices for loading u-boot.
+
+config SPL_NVME_BOOT_DEVICE
+	hex "NVMe boot device number"
+	depends on SPL_NVME
+	default 0x0
+
+config SYS_NVME_BOOT_PARTITION
+	hex "NVMe boot partition number"
+	depends on SPL_NVME
+	default	0x1
+
 config SPL_SERIAL
 	bool "Support serial"
 	select SPL_PRINTF
@@ -1345,96 +1349,6 @@ config SPL_THERMAL
 	  automatic power-off when the temperature gets too high or low. Other
 	  devices may be discrete but connected on a suitable bus.
 
-config SPL_USB_HOST
-	bool "Support USB host drivers"
-	help
-	  Enable access to USB (Universal Serial Bus) host devices so that
-	  SPL can load U-Boot from a connected USB peripheral, such as a USB
-	  flash stick. While USB takes a little longer to start up than most
-	  buses, it is very flexible since many different types of storage
-	  device can be attached. This option enables the drivers in
-	  drivers/usb/host as part of an SPL build.
-
-config SPL_USB_STORAGE
-	bool "Support loading from USB"
-	depends on SPL_USB_HOST
-	help
-	  Enable support for USB devices in SPL. This allows use of USB
-	  devices such as hard drives and flash drivers for loading U-Boot.
-	  The actual drivers are enabled separately using the normal U-Boot
-	  config options. This enables loading from USB using a configured
-	  device.
-
-config SYS_USB_FAT_BOOT_PARTITION
-	int "Partition on USB to use to load U-Boot from"
-	depends on SPL_USB_STORAGE
-	default 1
-	help
-	  Partition on the USB storage device to load U-Boot from
-
-config SPL_USB_GADGET
-	bool "Suppport USB Gadget drivers"
-	help
-	  Enable USB Gadget API which allows to enable USB device functions
-	  in SPL.
-
-if SPL_USB_GADGET
-
-config SPL_USB_ETHER
-	bool "Support USB Ethernet drivers"
-	depends on SPL_NET
-	help
-	  Enable access to the USB network subsystem and associated
-	  drivers in SPL. This permits SPL to load U-Boot over a
-	  USB-connected Ethernet link (such as a USB Ethernet dongle) rather
-	  than from an onboard peripheral. Environment support is required
-	  since the network stack uses a number of environment variables.
-	  See also SPL_NET and SPL_ETH.
-
-config SPL_DFU
-	bool "Support DFU (Device Firmware Upgrade)"
-	select SPL_HASH
-	select SPL_DFU_NO_RESET
-	depends on SPL_RAM_SUPPORT
-	help
-	  This feature enables the DFU (Device Firmware Upgrade) in SPL with
-	  RAM memory device support. The ROM code will load and execute
-	  the SPL built with dfu. The user can load binaries (u-boot/kernel) to
-	  selected device partition from host-pc using dfu-utils.
-	  This feature is useful to flash the binaries to factory or bare-metal
-	  boards using USB interface.
-
-choice
-	bool "DFU device selection"
-	depends on SPL_DFU
-
-config SPL_DFU_RAM
-	bool "RAM device"
-	depends on SPL_DFU && SPL_RAM_SUPPORT
-	help
-	 select RAM/DDR memory device for loading binary images
-	 (u-boot/kernel) to the selected device partition using
-	 DFU and execute the u-boot/kernel from RAM.
-
-endchoice
-
-config SPL_USB_SDP_SUPPORT
-	bool "Support SDP (Serial Download Protocol)"
-	depends on SPL_SERIAL
-	help
-	  Enable Serial Download Protocol (SDP) device support in SPL. This
-	  allows to download images into memory and execute (jump to) them
-	  using the same protocol as implemented by the i.MX family's boot ROM.
-
-config SPL_SDP_USB_DEV
-	int "SDP USB controller index"
-	default 0
-	depends on SPL_USB_SDP_SUPPORT
-	help
-	  Some boards have USB controller other than 0. Define this option
-	  so it can be used in compiled environment.
-endif
-
 config SPL_WATCHDOG
 	bool "Support watchdog drivers"
 	imply SPL_WDT if !HW_WATCHDOG
@@ -1524,8 +1438,10 @@ config SPL_OPENSBI_SCRATCH_OPTIONS
 	default 0x1
 	depends on SPL_OPENSBI
 	help
-	  Options passed to fw_dynamic, for example SBI_SCRATCH_NO_BOOT_PRINTS or
-	  SBI_SCRATCH_DEBUG_PRINTS.
+	  This bitmap of options is passed from U-Boot SPL to OpenSBI.
+	  As of OpenSBI 1.3 the following bits are defined:
+	  - SBI_SCRATCH_NO_BOOT_PRINTS = 0x1 (Disable prints during boot)
+	  - SBI_SCRATCH_DEBUG_PRINTS   = 0x2 (Enable runtime debug prints)
 
 config SPL_TARGET
 	string "Addtional build targets for 'make'"
diff --git a/common/spl/Kconfig.tpl b/common/spl/Kconfig.tpl
index 1874f9db4f..3d6cf1e59f 100644
--- a/common/spl/Kconfig.tpl
+++ b/common/spl/Kconfig.tpl
@@ -43,6 +43,7 @@ config TPL_FRAMEWORK
 
 config TPL_BANNER_PRINT
 	bool "Enable output of the TPL banner 'U-Boot TPL ...'"
+	depends on DEBUG_UART && TPL_SERIAL
 	default y
 	help
 	  If this option is enabled, TPL will print the banner with version
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 13db3df993..bad2bbf6cf 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -10,6 +10,7 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o
 obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o
 obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit.o
+obj-$(CONFIG_$(SPL_TPL_)BLK_FS) += spl_blk_fs.o
 obj-$(CONFIG_$(SPL_TPL_)LEGACY_IMAGE_FORMAT) += spl_legacy.o
 obj-$(CONFIG_$(SPL_TPL_)NOR_SUPPORT) += spl_nor.o
 obj-$(CONFIG_$(SPL_TPL_)XIP_SUPPORT) += spl_xip.o
@@ -28,6 +29,7 @@ obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
 obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
 obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
 obj-$(CONFIG_$(SPL_TPL_)SATA) += spl_sata.o
+obj-$(CONFIG_$(SPL_TPL_)NVME) += spl_nvme.o
 obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += spl_semihosting.o
 obj-$(CONFIG_$(SPL_TPL_)DFU) += spl_dfu.o
 obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 72078a8ebc..0062f3f45d 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -321,7 +321,7 @@ static int spl_load_fit_image(struct spl_image_info *spl_image,
 		spl_image->fdt_addr = (void *)dt_data;
 
 		if (spl_image->os == IH_OS_U_BOOT) {
-			/* HACK: U-boot expects FDT at a specific address */
+			/* HACK: U-Boot expects FDT at a specific address */
 			fdt_hack = spl_image->load_addr + spl_image->size;
 			fdt_hack = (fdt_hack + 3) & ~3;
 			debug("Relocating FDT to %p\n", spl_image->fdt_addr);
@@ -331,7 +331,7 @@ static int spl_load_fit_image(struct spl_image_info *spl_image,
 
 	conf_noffset = fit_conf_get_node((const void *)header,
 					 fit_uname_config);
-	if (conf_noffset <= 0)
+	if (conf_noffset < 0)
 		return 0;
 
 	for (idx = 0;
@@ -800,6 +800,13 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	    IS_ENABLED(CONFIG_SPL_ATF))
 		dram_init_banksize();
 
+	if (CONFIG_IS_ENABLED(PCI)) {
+		ret = pci_init();
+		if (ret)
+			puts(SPL_TPL_PROMPT "Cannot initialize PCI\n");
+		/* Don't fail. We still can try other boot methods. */
+	}
+
 	bootcount_inc();
 
 	/* Dump driver model states to aid analysis */
@@ -891,18 +898,18 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 		debug("Failed to stash bootstage: err=%d\n", ret);
 #endif
 
-#if defined(CONFIG_SPL_VIDEO)
-	struct udevice *dev;
-	int rc;
+	if (IS_ENABLED(CONFIG_SPL_VIDEO_REMOVE)) {
+		struct udevice *dev;
+		int rc;
 
-	rc = uclass_find_device(UCLASS_VIDEO, 0, &dev);
-	if (!rc && dev) {
-		rc = device_remove(dev, DM_REMOVE_NORMAL);
-		if (rc)
-			printf("Cannot remove video device '%s' (err=%d)\n",
-			       dev->name, rc);
+		rc = uclass_find_device(UCLASS_VIDEO, 0, &dev);
+		if (!rc && dev) {
+			rc = device_remove(dev, DM_REMOVE_NORMAL);
+			if (rc)
+				printf("Cannot remove video device '%s' (err=%d)\n",
+				       dev->name, rc);
+		}
 	}
-#endif
 
 	spl_board_prepare_for_boot();
 	jump_to_image_no_args(&spl_image);
@@ -992,6 +999,7 @@ ulong spl_relocate_stack_gd(void)
 #endif
 	/* Get stack position: use 8-byte alignment for ABI compliance */
 	ptr = CONFIG_SPL_STACK_R_ADDR - roundup(sizeof(gd_t),16);
+	gd->start_addr_sp = ptr;
 	new_gd = (gd_t *)ptr;
 	memcpy(new_gd, (void *)gd, sizeof(gd_t));
 #if CONFIG_IS_ENABLED(DM)
diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c
new file mode 100644
index 0000000000..16ecece702
--- /dev/null
+++ b/common/spl/spl_blk_fs.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023
+ * Ventana Micro Systems Inc.
+ *
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <image.h>
+#include <fs.h>
+
+struct blk_dev {
+	const char *ifname;
+	char dev_part_str[8];
+};
+
+static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
+			  ulong size, void *buf)
+{
+	loff_t actlen;
+	int ret;
+	struct blk_dev *dev = (struct blk_dev *)load->priv;
+
+	ret = fs_set_blk_dev(dev->ifname, dev->dev_part_str, FS_TYPE_ANY);
+	if (ret) {
+		printf("spl: unable to set blk_dev %s %s. Err - %d\n",
+		       dev->ifname, dev->dev_part_str, ret);
+		return ret;
+	}
+
+	ret = fs_read(load->filename, (ulong)buf, file_offset, size, &actlen);
+	if (ret < 0) {
+		printf("spl: error reading image %s. Err - %d\n",
+		       load->filename, ret);
+		return ret;
+	}
+
+	return actlen;
+}
+
+int spl_blk_load_image(struct spl_image_info *spl_image,
+		       struct spl_boot_device *bootdev,
+		       enum uclass_id uclass_id, int devnum, int partnum)
+{
+	const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
+	struct disk_partition part_info = {};
+	struct legacy_img_hdr *header;
+	struct blk_desc *blk_desc;
+	loff_t actlen, filesize;
+	struct blk_dev dev;
+	int ret;
+
+	blk_desc = blk_get_devnum_by_uclass_id(uclass_id, devnum);
+	if (!blk_desc) {
+		printf("blk desc for %d %d not found\n", uclass_id, devnum);
+		goto out;
+	}
+
+	blk_show_device(uclass_id, devnum);
+	header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+	ret = part_get_info(blk_desc, 1, &part_info);
+	if (ret) {
+		printf("spl: no partition table found. Err - %d\n", ret);
+		goto out;
+	}
+
+	dev.ifname = blk_get_uclass_name(uclass_id);
+	snprintf(dev.dev_part_str, sizeof(dev.dev_part_str) - 1, "%x:%x",
+		 devnum, partnum);
+	ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY);
+	if (ret) {
+		printf("spl: unable to set blk_dev %s %s. Err - %d\n",
+		       dev.ifname, dev.dev_part_str, ret);
+		goto out;
+	}
+
+	ret = fs_read(filename, (ulong)header, 0,
+		      sizeof(struct legacy_img_hdr), &actlen);
+	if (ret) {
+		printf("spl: unable to read file %s. Err - %d\n", filename,
+		       ret);
+		goto out;
+	}
+
+	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	    image_get_magic(header) == FDT_MAGIC) {
+		struct spl_load_info load;
+
+		debug("Found FIT\n");
+		load.read = spl_fit_read;
+		load.bl_len = 1;
+		load.filename = (void *)filename;
+		load.priv = &dev;
+
+		return spl_load_simple_fit(spl_image, &load, 0, header);
+	}
+
+	ret = spl_parse_image_header(spl_image, bootdev, header);
+	if (ret) {
+		printf("spl: unable to parse image header. Err - %d\n",
+		       ret);
+		goto out;
+	}
+
+	ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY);
+	if (ret) {
+		printf("spl: unable to set blk_dev %s %s. Err - %d\n",
+		       dev.ifname, dev.dev_part_str, ret);
+		goto out;
+	}
+
+	ret = fs_size(filename, &filesize);
+	if (ret) {
+		printf("spl: unable to get file size: %s. Err - %d\n",
+		       filename, ret);
+		goto out;
+	}
+
+	ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY);
+	if (ret) {
+		printf("spl: unable to set blk_dev %s %s. Err - %d\n",
+		       dev.ifname, dev.dev_part_str, ret);
+		goto out;
+	}
+
+	ret = fs_read(filename, (ulong)spl_image->load_addr, 0, filesize,
+		      &actlen);
+	if (ret)
+		printf("spl: unable to read file %s. Err - %d\n",
+		       filename, ret);
+out:
+	return ret;
+}
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index c51482b3b6..730639f756 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -27,10 +27,6 @@ struct spl_fit_info {
 	int conf_node;		/* FDT offset to selected configuration node */
 };
 
-__weak void board_spl_fit_post_load(const void *fit)
-{
-}
-
 __weak ulong board_spl_fit_size_align(ulong size)
 {
 	return size;
@@ -829,8 +825,5 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 
 	spl_image->flags |= SPL_FIT_FOUND;
 
-	if (IS_ENABLED(CONFIG_IMX_HAB))
-		board_spl_fit_post_load(ctx.fit);
-
 	return 0;
 }
diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c
index 16851c55eb..095443c63d 100644
--- a/common/spl/spl_legacy.c
+++ b/common/spl/spl_legacy.c
@@ -7,6 +7,7 @@
 #include <image.h>
 #include <log.h>
 #include <malloc.h>
+#include <asm/sections.h>
 #include <spl.h>
 
 #include <lzma/LzmaTypes.h>
@@ -15,6 +16,22 @@
 
 #define LZMA_LEN	(1 << 20)
 
+static void spl_parse_legacy_validate(uintptr_t start, uintptr_t size)
+{
+	uintptr_t spl_start = (uintptr_t)_start;
+	uintptr_t spl_end = (uintptr_t)_image_binary_end;
+	uintptr_t end = start + size;
+
+	if ((start >= spl_start && start < spl_end) ||
+	    (end > spl_start && end <= spl_end) ||
+	    (start < spl_start && end >= spl_end) ||
+	    (start > end && end > spl_start))
+		panic("SPL: Image overlaps SPL\n");
+
+	if (size > CONFIG_SYS_BOOTM_LEN)
+		panic("SPL: Image too large\n");
+}
+
 int spl_parse_legacy_header(struct spl_image_info *spl_image,
 			    const struct legacy_img_hdr *header)
 {
@@ -58,6 +75,9 @@ int spl_parse_legacy_header(struct spl_image_info *spl_image,
 	      "payload image: %32s load addr: 0x%lx size: %d\n",
 	      spl_image->name, spl_image->load_addr, spl_image->size);
 
+	spl_parse_legacy_validate(spl_image->load_addr, spl_image->size);
+	spl_parse_legacy_validate(spl_image->entry_point, 0);
+
 	return 0;
 }
 
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index a072216704..a665091b00 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -250,7 +250,7 @@ static int mmc_load_image_raw_os(struct spl_image_info *spl_image,
 		return ret;
 
 	if (spl_image->os != IH_OS_LINUX && spl_image->os != IH_OS_TEE) {
-		puts("Expected image is not found. Trying to start U-boot\n");
+		puts("Expected image is not found. Trying to start U-Boot\n");
 		return -ENOENT;
 	}
 
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index 1ef5e41262..5b65b96a77 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -121,6 +121,6 @@ static int spl_nor_load_image(struct spl_image_info *spl_image,
 					   &hdr);
 	}
 
-	return 0;
+	return -EINVAL;
 }
 SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image);
diff --git a/common/spl/spl_nvme.c b/common/spl/spl_nvme.c
new file mode 100644
index 0000000000..c8774d67ec
--- /dev/null
+++ b/common/spl/spl_nvme.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023
+ * Ventana Micro Systems Inc.
+ *
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <nvme.h>
+
+static int spl_nvme_load_image(struct spl_image_info *spl_image,
+			       struct spl_boot_device *bootdev)
+{
+	int ret;
+
+	ret = nvme_scan_namespace();
+	if (ret < 0)
+		return ret;
+
+	ret = spl_blk_load_image(spl_image, bootdev, UCLASS_NVME,
+				 CONFIG_SPL_NVME_BOOT_DEVICE,
+				 CONFIG_SYS_NVME_BOOT_PARTITION);
+	return ret;
+}
+
+SPL_LOAD_IMAGE_METHOD("NVME", 0, BOOT_DEVICE_NVME, spl_nvme_load_image);
diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c
index 8139a20327..93cf420d81 100644
--- a/common/spl/spl_ram.c
+++ b/common/spl/spl_ram.c
@@ -6,7 +6,7 @@
  * (C) Copyright 2016
  * Toradex AG
  *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  * Stefan Agner <stefan.agner@toradex.com>
  */
 #include <common.h>
diff --git a/common/splash_source.c b/common/splash_source.c
index a260137619..7223a1aae7 100644
--- a/common/splash_source.c
+++ b/common/splash_source.c
@@ -363,7 +363,7 @@ static int splash_load_fit(struct splash_location *location, u32 bmp_load_addr)
 	if (res < 0)
 		return res;
 
-	img_header = (struct legacy_img_hdr *)bmp_load_addr;
+	img_header = (struct legacy_img_hdr *)(uintptr_t)bmp_load_addr;
 	if (image_get_magic(img_header) != FDT_MAGIC) {
 		printf("Could not find FDT magic\n");
 		return -EINVAL;
@@ -373,7 +373,7 @@ static int splash_load_fit(struct splash_location *location, u32 bmp_load_addr)
 
 	/* Read in entire FIT */
 	fit_header = (const u32 *)(bmp_load_addr + header_size);
-	res = splash_storage_read_raw(location, (u32)fit_header, fit_size);
+	res = splash_storage_read_raw(location, (uintptr_t)fit_header, fit_size);
 	if (res < 0)
 		return res;
 
@@ -398,7 +398,7 @@ static int splash_load_fit(struct splash_location *location, u32 bmp_load_addr)
 	/* Extract the splash data from FIT */
 	/* 1. Test if splash is in FIT internal data. */
 	if (!fit_image_get_data(fit_header, node_offset, &internal_splash_data, &internal_splash_size))
-		memmove((void *)bmp_load_addr, internal_splash_data, internal_splash_size);
+		memmove((void *)(uintptr_t)bmp_load_addr, internal_splash_data, internal_splash_size);
 	/* 2. Test if splash is in FIT external data with fixed position. */
 	else if (!fit_image_get_data_position(fit_header, node_offset, &external_splash_addr))
 		is_splash_external = true;
diff --git a/common/stdio.c b/common/stdio.c
index cbedfdda53..894cbd3fb4 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -386,11 +386,3 @@ int stdio_add_devices(void)
 
 	return 0;
 }
-
-int stdio_init(void)
-{
-	stdio_init_tables();
-	stdio_add_devices();
-
-	return 0;
-}
diff --git a/common/usb_storage.c b/common/usb_storage.c
index ac64275773..85774220ef 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -246,7 +246,7 @@ static int usb_stor_probe_device(struct usb_device *udev)
 		if (ret)
 			return ret;
 
-		ret = bootdev_setup_sibling_blk(dev, "usb_bootdev");
+		ret = bootdev_setup_for_sibling_blk(dev, "usb_bootdev");
 		if (ret) {
 			int ret2;
 
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index 54a67c5aa9..b76f31b009 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig
index fc73c0613d..13da353d7e 100644
--- a/configs/3c120_defconfig
+++ b/configs/3c120_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/configs/CMPC885_defconfig b/configs/CMPC885_defconfig
index f5bc6d6c00..54873daa15 100644
--- a/configs/CMPC885_defconfig
+++ b/configs/CMPC885_defconfig
@@ -51,7 +51,6 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_MII_INIT=y
 CONFIG_CMD_PING=y
diff --git a/configs/CMPCPRO_defconfig b/configs/CMPCPRO_defconfig
index 80913e653b..d817274a93 100644
--- a/configs/CMPCPRO_defconfig
+++ b/configs/CMPCPRO_defconfig
@@ -136,7 +136,6 @@ CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_SLEEP is not set
diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig
index 0c5afe869b..aa054f753f 100644
--- a/configs/M5208EVBE_defconfig
+++ b/configs/M5208EVBE_defconfig
@@ -50,3 +50,5 @@ CONFIG_MCFFEC=y
 CONFIG_MII=y
 CONFIG_MCFUART=y
 CONFIG_WATCHDOG_TIMEOUT_MSECS=5000
+CONFIG_WDT=y
+CONFIG_WDT_MCF=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 5e8dfbfcdd..0d0707e026 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -101,7 +101,9 @@ CONFIG_SYS_QE_FW_ADDR=0xEFE00000
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1337=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 06eb06dfa8..fe84f36ace 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -101,7 +101,9 @@ CONFIG_SYS_QE_FW_ADDR=0xEFF10000
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1337=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 8a85d4999d..e1e963037d 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -106,7 +106,9 @@ CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index f5383cc6cb..d9116df624 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -108,7 +108,9 @@ CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index eddd6fb6ff..4b63ef413a 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -96,7 +96,9 @@ CONFIG_MII=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/ad401_defconfig b/configs/ad401_defconfig
new file mode 100644
index 0000000000..529e553bac
--- /dev/null
+++ b/configs/ad401_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x00000000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00200000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-a1-ad401"
+CONFIG_SYS_PROMPT="ad401 # "
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_MESON_A1=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_DEBUG_UART=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_LED=y
+CONFIG_MISC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_WDT=y
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index 090b902be3..6ef3c78390 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -18,7 +18,6 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
 CONFIG_SPL_FS_EXT4=y
@@ -57,10 +56,10 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_NET_RETRY_COUNT=10
 CONFIG_BOOTP_SEND_HOSTNAME=y
+# CONFIG_TI_SYSC is not set
 CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_SPEED=1000
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MMC_OMAP_HS_ADMA=y
@@ -79,6 +78,8 @@ CONFIG_PHY_SMSC=y
 CONFIG_DM_MDIO=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
+CONFIG_DM_PMIC=y
+# CONFIG_PMIC_CHILDREN is not set
 CONFIG_SPL_POWER_TPS65910=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
@@ -94,5 +95,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_USB_ETHER=y
-CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
 CONFIG_WDT=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index c42d2a0006..e581accc21 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -34,8 +34,6 @@ CONFIG_SPL_FALCON_BOOT_MMCSD=y
 CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_BOOTM_LEN=0x1000000
 CONFIG_CMD_SPL=y
@@ -89,8 +87,10 @@ CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_MUSB_TI=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
 CONFIG_USB_ETHER=y
+CONFIG_SPL_USB_ETHER=y
 CONFIG_LZO=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index ffeeb8573d..a179f1ed5f 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -39,8 +39,6 @@ CONFIG_SPL_FALCON_BOOT_MMCSD=y
 CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_BOOTM_LEN=0x1000000
 CONFIG_CMD_EXTENSION=y
@@ -115,10 +113,12 @@ CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_MUSB_TI=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
 CONFIG_USB_ETHER=y
+CONFIG_SPL_USB_ETHER=y
 CONFIG_WDT=y
 # CONFIG_SPL_WDT is not set
 CONFIG_DYNAMIC_CRC_TABLE=y
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index ad0fa46cb8..a485cc65ea 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -45,8 +45,6 @@ CONFIG_SPL_NAND_BASE=y
 CONFIG_SPL_NET=y
 CONFIG_SPL_NET_VCI_STRING="Guardian U-Boot SPL"
 CONFIG_SPL_POWER=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_BOOTM_LEN=0x1000000
 CONFIG_CMD_ASKENV=y
@@ -127,10 +125,12 @@ CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_MUSB_TI=y
 # CONFIG_USB_STORAGE is not set
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
 CONFIG_USB_ETHER=y
+CONFIG_SPL_USB_ETHER=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_BMP_16BPP=y
 CONFIG_SPL_WDT=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 1e93439f94..a3a4ab361c 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -37,7 +37,6 @@ CONFIG_SYS_BOOTM_LEN=0x1000000
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_DNS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 34525d686f..323862009f 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -34,9 +34,6 @@ CONFIG_SPL_FALCON_BOOT_MMCSD=y
 CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_CMD_SPL=y
 CONFIG_CMD_SPL_NAND_OFS=0x00100000
@@ -97,6 +94,7 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
 CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_XHCI_OMAP=y
@@ -106,8 +104,10 @@ CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0403
 CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_ETHER=y
+CONFIG_SPL_USB_ETHER=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 64ecd92fbb..406c0fc2d7 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -30,9 +30,6 @@ CONFIG_SPL_FALCON_BOOT_MMCSD=y
 CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_STORAGE=y
-CONFIG_SPL_USB_GADGET=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_CMD_SPL=y
 CONFIG_CMD_SPL_NAND_OFS=0x00100000
@@ -98,6 +95,7 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_XHCI_OMAP=y
@@ -106,7 +104,9 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y
 CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_SPL_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0403
 CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 6715a254c4..01428ac7aa 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -34,15 +34,10 @@ CONFIG_SPL_NAND_ECC=y
 CONFIG_SPL_NAND_BASE=y
 CONFIG_SPL_NET=y
 CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_STORAGE=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_DNS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
@@ -95,6 +90,7 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
 CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_XHCI_OMAP=y
@@ -103,9 +99,12 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y
 CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_SPL_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0403
 CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_ETHER=y
+CONFIG_SPL_USB_ETHER=y
diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig
index ad6ce2b7d6..54051ca047 100644
--- a/configs/am43xx_hs_evm_qspi_defconfig
+++ b/configs/am43xx_hs_evm_qspi_defconfig
@@ -31,7 +31,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_DNS2=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 1b038488b3..94ffce1a99 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -49,7 +49,6 @@ CONFIG_CMD_ABOOTIMG=y
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_CMD_BCB=y
 # CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_AB_SELECT=y
 CONFIG_BOOTP_DNS2=y
 # CONFIG_CMD_PMIC is not set
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index fe7173811e..404e714d4f 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -44,8 +44,6 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -54,7 +52,6 @@ CONFIG_CMD_ABOOTIMG=y
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_CMD_BCB=y
 # CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_AB_SELECT=y
 CONFIG_BOOTP_DNS2=y
 # CONFIG_CMD_PMIC is not set
@@ -120,7 +117,9 @@ CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_SPL_DFU=y
 CONFIG_LIBAVB=y
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 41fa6f38aa..773cf3a591 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -23,6 +23,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
 CONFIG_SPL_MAX_SIZE=0x58000
 CONFIG_SPL_PAD_TO=0x0
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -35,6 +36,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_MMC=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index 7c3bc184cf..d55caabe22 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -29,7 +29,7 @@ CONFIG_SPL_SPI=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; setenv fdtfile ti/${name_fdt}; run distro_bootcmd"
+CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
 CONFIG_SPL_MAX_SIZE=0x58000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80c80000
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 4589624e96..718ad176cb 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_SPL_GPIO=y
@@ -13,7 +14,6 @@ CONFIG_TARGET_AM642_A53_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
 CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x680000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
@@ -32,7 +32,7 @@ CONFIG_SPL_SPI=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_MAX_SIZE=0x180000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -59,13 +59,8 @@ CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_STORAGE=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x800000
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_DM=y
@@ -82,14 +77,11 @@ CONFIG_OF_LIST="k3-am642-evm k3-am642-sk"
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
@@ -153,16 +145,20 @@ CONFIG_SYSRESET_TI_SCI=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
 CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_CDNS3=y
 CONFIG_USB_CDNS3_GADGET=y
 CONFIG_USB_CDNS3_HOST=y
 CONFIG_SPL_USB_CDNS3_GADGET=y
 CONFIG_SPL_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
+CONFIG_SPL_DFU=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index 023ee638a0..b501c17b87 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x80000
 CONFIG_SPL_GPIO=y
@@ -65,10 +66,6 @@ CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_REMOTEPROC=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_STORAGE=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=64
@@ -95,7 +92,6 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
@@ -159,6 +155,7 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
 CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_CDNS3=y
 CONFIG_USB_CDNS3_GADGET=y
@@ -166,9 +163,12 @@ CONFIG_USB_CDNS3_HOST=y
 CONFIG_SPL_USB_CDNS3_GADGET=y
 CONFIG_SPL_USB_CDNS3_HOST=y
 CONFIG_USB_STORAGE=y
+CONFIG_SPL_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index f294a4595f..4301553af8 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -61,10 +61,6 @@ CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_STORAGE=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_CMD_ASKENV=y
@@ -75,7 +71,6 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs)"
@@ -167,15 +162,19 @@ CONFIG_SYSRESET_TI_SCI=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
 CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y
 CONFIG_USB_KEYBOARD=y
+CONFIG_SPL_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
 CONFIG_PHANDLE_CHECK_SEQ=y
diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig
index 8b0192579c..88f68aa70e 100644
--- a/configs/am65x_evm_r5_usbdfu_defconfig
+++ b/configs/am65x_evm_r5_usbdfu_defconfig
@@ -51,8 +51,6 @@ CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_REMOTEPROC=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=64
@@ -130,8 +128,10 @@ CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig
index 01e46e6a62..8da49c78c8 100644
--- a/configs/am65x_evm_r5_usbmsc_defconfig
+++ b/configs/am65x_evm_r5_usbmsc_defconfig
@@ -50,9 +50,6 @@ CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_REMOTEPROC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_STORAGE=y
-CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=64
@@ -120,12 +117,15 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
 CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_STORAGE=y
+CONFIG_SPL_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig
index e0277d4787..3f9626e455 100644
--- a/configs/am65x_hs_evm_a53_defconfig
+++ b/configs/am65x_hs_evm_a53_defconfig
@@ -69,7 +69,6 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs)"
diff --git a/configs/anbernic-rgxx3_defconfig b/configs/anbernic-rgxx3_defconfig
index b17e917914..ed6643d9d4 100644
--- a/configs/anbernic-rgxx3_defconfig
+++ b/configs/anbernic-rgxx3_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x600000
@@ -24,9 +25,13 @@ CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
+# CONFIG_CONSOLE_MUX is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_RNG_SEED=y
 CONFIG_SPL_MAX_SIZE=0x20000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -41,6 +46,7 @@ CONFIG_CMD_PWM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_CLS is not set
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
@@ -60,6 +66,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_PMIC_FAN53555=y
 CONFIG_PMIC_RK8XX=y
@@ -69,10 +76,18 @@ CONFIG_REGULATOR_RK8XX=y
 CONFIG_DM_REGULATOR_SCMI=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
+# CONFIG_RAM_ROCKCHIP_DEBUG is not set
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+# CONFIG_RNG_SMCCC_TRNG is not set
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_DW_MIPI=y
+CONFIG_VIDEO_BRIDGE=y
 CONFIG_REGEX=y
 CONFIG_ERRNO_STR=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index 36d28a249c..fda85c2d6a 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -43,7 +43,6 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index d7342c4968..5f0f78191c 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -43,9 +43,6 @@ CONFIG_MISC_INIT_R=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_DMA=y
 CONFIG_SPL_I2C=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_MAXARGS=48
 CONFIG_SYS_CBSIZE=1024
 CONFIG_SYS_PBSIZE=1055
@@ -65,7 +62,6 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_BOOTCOUNT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -113,12 +109,15 @@ CONFIG_DM_SCSI=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Toradex"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 516552584c..83aab2450b 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -38,7 +38,6 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig
index 29c4c187b5..ce7f2355e1 100644
--- a/configs/arbel_evb_defconfig
+++ b/configs/arbel_evb_defconfig
@@ -1,8 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_NPCM=y
+CONFIG_TEXT_BASE=0x06208000
 CONFIG_SYS_MALLOC_LEN=0x240000
 CONFIG_SYS_MALLOC_F_LEN=0x1000
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x3C0000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -13,7 +14,7 @@ CONFIG_DM_RESET=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_ARCH_NPCM8XX=y
 CONFIG_TARGET_ARBEL_EVB=y
-CONFIG_SYS_LOAD_ADDR=0x10000000
+CONFIG_SYS_LOAD_ADDR=0x06208000
 CONFIG_ENV_ADDR=0x803C0000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -24,8 +25,10 @@ CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_BOOTM_LEN=0x1400000
 CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
@@ -35,7 +38,9 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_RNG=y
 CONFIG_CMD_UUID=y
 CONFIG_CMD_HASH=y
+CONFIG_CMD_TPM=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
@@ -47,6 +52,7 @@ CONFIG_DM_I2C=y
 # CONFIG_INPUT is not set
 CONFIG_MISC=y
 CONFIG_NPCM_HOST=y
+CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_NPCM=y
 CONFIG_DM_SPI_FLASH=y
@@ -65,7 +71,6 @@ CONFIG_PINCTRL_NPCM8XX=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_NPCM8XX=y
 CONFIG_RESET_SYSCON=y
-CONFIG_DM_RNG=y
 CONFIG_RNG_NPCM=y
 CONFIG_DM_SERIAL=y
 CONFIG_NPCM_SERIAL=y
@@ -73,8 +78,11 @@ CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_NPCM_FIU_SPI=y
 CONFIG_NPCM_PSPI=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
 CONFIG_TIMER=y
 CONFIG_NPCM_TIMER=y
+CONFIG_TPM2_FTPM_TEE=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_NPCM=y
@@ -84,5 +92,6 @@ CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_OHCI_NPCM=y
 CONFIG_USB_STORAGE=y
 CONFIG_LIB_HW_RAND=y
+CONFIG_TPM=y
 CONFIG_SHA_HW_ACCEL=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig
index db68b21c03..d1eb2abfae 100644
--- a/configs/aristainetos2c_defconfig
+++ b/configs/aristainetos2c_defconfig
@@ -59,7 +59,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DTB_RESELECT=y
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_SPI_EARLY=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig
index d369505e8b..638976df95 100644
--- a/configs/aristainetos2ccslb_defconfig
+++ b/configs/aristainetos2ccslb_defconfig
@@ -59,7 +59,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DTB_RESELECT=y
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_SPI_EARLY=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index aade1f98be..f4dad3bcc8 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -46,5 +46,5 @@ CONFIG_DM_RTC=y
 CONFIG_MCFRTC=y
 CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
 CONFIG_MCFUART=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_TIMEOUT_MSECS=3355
+CONFIG_WDT=y
+CONFIG_WDT_MCF=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index 5eeeb0828b..5d6dd2ae91 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -49,7 +49,6 @@ CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20ba0000
 CONFIG_SYS_SPL_MALLOC_SIZE=0x460000
-CONFIG_SPL_CRC32=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_NAND_RAW_ONLY=y
 CONFIG_SPL_NAND_DRIVERS=y
@@ -102,4 +101,5 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_ATMEL_USART=y
 CONFIG_WDT=y
 CONFIG_WDT_AT91=y
+CONFIG_SPL_CRC32=y
 CONFIG_HEXDUMP=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 4e59d513cd..a44c9b714b 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -37,7 +37,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 3820a333ec..0d8a74be7a 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -38,7 +38,6 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig
index c38ba15cd0..3995d41ce1 100644
--- a/configs/bitmain_antminer_s9_defconfig
+++ b/configs/bitmain_antminer_s9_defconfig
@@ -55,7 +55,6 @@ CONFIG_CMD_PART=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_MAY_FAIL=y
-# CONFIG_CMD_NFS is not set
 CONFIG_SYS_DISABLE_AUTOLOAD=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 2c9b066215..653620263c 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -64,7 +64,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_MAY_FAIL=y
-# CONFIG_CMD_NFS is not set
 CONFIG_SYS_DISABLE_AUTOLOAD=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig
index 00ef3d9908..05ee4c5797 100644
--- a/configs/brppt2_defconfig
+++ b/configs/brppt2_defconfig
@@ -56,7 +56,6 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_MAY_FAIL=y
-# CONFIG_CMD_NFS is not set
 CONFIG_SYS_DISABLE_AUTOLOAD=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig
index 1e55ed7c60..94943fccf1 100644
--- a/configs/brsmarc1_defconfig
+++ b/configs/brsmarc1_defconfig
@@ -73,7 +73,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_MAY_FAIL=y
-# CONFIG_CMD_NFS is not set
 CONFIG_SYS_DISABLE_AUTOLOAD=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index 1c437e9743..b50aef0aad 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -63,7 +63,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_MAY_FAIL=y
-# CONFIG_CMD_NFS is not set
 CONFIG_SYS_DISABLE_AUTOLOAD=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index 00fea793f9..4fe4621f03 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -35,7 +35,6 @@ CONFIG_CMD_PCI=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
index c00e6bec5a..b920ac2ae4 100644
--- a/configs/cei-tk1-som_defconfig
+++ b/configs/cei-tk1-som_defconfig
@@ -41,7 +41,6 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig
index 4137b1c77e..00799715e8 100644
--- a/configs/cherryhill_defconfig
+++ b/configs/cherryhill_defconfig
@@ -28,7 +28,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index d4302353c5..6a9b509d0e 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
 CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC is not set
@@ -25,6 +26,8 @@ CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_DEBUG_UART=y
 CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
+CONFIG_SILENT_CONSOLE=y
+CONFIG_LOG=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
@@ -35,7 +38,6 @@ CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SPL_CRC32 is not set
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -81,6 +83,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
 CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
@@ -95,6 +98,7 @@ CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
@@ -103,9 +107,11 @@ CONFIG_USB_DWC2=y
 CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
+CONFIG_CONSOLE_TRUETYPE=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+# CONFIG_USE_PRIVATE_LIBGCC is not set
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index dd6d4069a6..1807e83822 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -43,6 +43,7 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig
index f5995f2200..152f297c35 100644
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig
@@ -1,5 +1,6 @@
 CONFIG_X86=y
 CONFIG_TEXT_BASE=0x1110000
+CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x3d00
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_MAX_CPUS=8
@@ -22,6 +23,7 @@ CONFIG_X86_OFFSET_U_BOOT=0xffd00000
 CONFIG_X86_OFFSET_SPL=0xffe80000
 CONFIG_INTEL_ACPIGEN=y
 CONFIG_INTEL_GENERIC_WIFI=y
+CONFIG_BOOTSTD_FULL=y
 CONFIG_SYS_MONITOR_BASE=0x01110000
 CONFIG_CHROMEOS=y
 CONFIG_BOOTSTAGE=y
@@ -33,8 +35,10 @@ CONFIG_BOOTSTAGE_STASH=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS_SUBST=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="tpm init; tpm startup TPM2_SU_CLEAR; read mmc 0:2 100000 0 80; setexpr loader *001004f0; setexpr size *00100518; setexpr blocks $size / 200; read mmc 0:2 100000 80 $blocks; setexpr setup $loader - 1000; setexpr cmdline_ptr $loader - 2000; setexpr.s cmdline *$cmdline_ptr; setexpr cmdline gsub %U \\\\${uuid}; if part uuid mmc 0:2 uuid; then zboot start 100000 0 0 0 $setup cmdline; zboot load; zboot setup; zboot dump; zboot go;fi"
+CONFIG_BOOTCOMMAND="tpm init; tpm startup TPM2_SU_CLEAR; bootflow scan -lb"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_LOG=y
+CONFIG_LOGF_FUNC=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_BLOBLIST=y
@@ -51,10 +55,11 @@ CONFIG_SPL_POWER=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 CONFIG_TPL_POWER=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1024
 CONFIG_CMD_CPU=y
 CONFIG_CMD_PMC=y
+CONFIG_CMD_MEM_SEARCH=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PART=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 1a54986d08..9fdad32553 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -37,7 +37,6 @@ CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SPL_CRC32 is not set
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -84,6 +83,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
 CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
@@ -102,6 +102,7 @@ CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_SOUND=y
 CONFIG_I2S=y
 CONFIG_I2S_ROCKCHIP=y
+CONFIG_SOUND_MAX98090=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig
index 3d2642f0d0..638beee2c6 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -44,6 +44,7 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 8c75d65429..558609e13d 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -50,7 +50,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 3098857d6e..96c26f1c37 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -37,7 +37,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 73ab2f62af..811d666b75 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
 CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC is not set
@@ -26,6 +27,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
 CONFIG_SILENT_CONSOLE=y
+CONFIG_LOG=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
@@ -36,7 +38,6 @@ CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SPL_CRC32 is not set
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -83,6 +84,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
 CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
@@ -97,6 +99,7 @@ CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_SOUND=y
 CONFIG_I2S=y
 CONFIG_I2S_ROCKCHIP=y
@@ -109,11 +112,12 @@ CONFIG_USB_DWC2=y
 CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
+CONFIG_CONSOLE_TRUETYPE=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_EDP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_CONSOLE_SCROLL_LINES=10
+# CONFIG_USE_PRIVATE_LIBGCC is not set
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index 0d20891d2b..4019c169a4 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -39,7 +39,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 06437aae18..8b6d995d92 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
 CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC is not set
@@ -26,6 +27,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
 CONFIG_SILENT_CONSOLE=y
+CONFIG_LOG=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
@@ -36,7 +38,6 @@ CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SPL_CRC32 is not set
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -50,6 +51,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
@@ -82,6 +84,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
 CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
@@ -97,6 +100,10 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SERIAL=y
+CONFIG_SOUND=y
+CONFIG_I2S=y
+CONFIG_I2S_ROCKCHIP=y
+CONFIG_SOUND_MAX98090=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index 96c739cbfb..f050d066be 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -32,7 +32,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index a307e83d1d..12d010ab64 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -62,7 +62,6 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_NFS is not set
 CONFIG_SYS_DISABLE_AUTOLOAD=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index e25cde9e5f..be1037b6cb 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -42,9 +42,6 @@ CONFIG_MISC_INIT_R=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_DMA=y
 CONFIG_SPL_I2C=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_MAXARGS=48
 CONFIG_SYS_CBSIZE=1024
 CONFIG_SYS_PBSIZE=1056
@@ -64,7 +61,6 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_BOOTCOUNT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -110,12 +106,15 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Toradex"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index cdf9e8b1d0..eb2e202f6f 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -36,7 +36,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index fed867a8eb..8098ff7abc 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -36,7 +36,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index c47bfc801a..4d4d0e4aaf 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -51,7 +51,6 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT4=y
diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
index 14f00b6212..656d575998 100644
--- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
@@ -44,7 +44,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 613dcd3ca5..54dc59e8a1 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -40,7 +40,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
index 60a1924e9e..8aadaa68c2 100644
--- a/configs/coreboot64_defconfig
+++ b/configs/coreboot64_defconfig
@@ -30,7 +30,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig
index 058caf008f..8e11de6638 100644
--- a/configs/coreboot_defconfig
+++ b/configs/coreboot_defconfig
@@ -1,5 +1,6 @@
 CONFIG_X86=y
 CONFIG_TEXT_BASE=0x1110000
+CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_ENV_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="coreboot"
@@ -8,12 +9,11 @@ CONFIG_VENDOR_COREBOOT=y
 CONFIG_TARGET_COREBOOT=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTD_FULL=y
 CONFIG_SYS_MONITOR_BASE=0x01110000
 CONFIG_SHOW_BOOT_PROGRESS=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
 CONFIG_PRE_CONSOLE_BUFFER=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_LOG=y
@@ -22,17 +22,12 @@ CONFIG_LOGF_FUNC=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_PCI_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_MEM_SEARCH=y
-CONFIG_CMD_IDE=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
@@ -53,13 +48,6 @@ CONFIG_USE_ROOTPATH=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 # CONFIG_ACPIGEN is not set
-CONFIG_SYS_IDE_MAXDEVICE=4
-CONFIG_SYS_ATA_DATA_OFFSET=0
-CONFIG_SYS_ATA_REG_OFFSET=0
-CONFIG_SYS_ATA_ALT_OFFSET=0
-CONFIG_ATAPI=y
-CONFIG_LBA48=y
-CONFIG_SYS_64BIT_LBA=y
 CONFIG_NVME_PCI=y
 # CONFIG_PCI_PNP is not set
 CONFIG_SOUND=y
diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
index 2d391048cd..3b5733b777 100644
--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
@@ -15,22 +15,25 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk"
-CONFIG_BOOTCOMMAND="run retrieve_kernel_load_addr; echo Loading kernel from $kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
+CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
 CONFIG_CONSOLE_RECORD=y
 CONFIG_LOGLEVEL=7
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_LATE_INIT=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_CBSIZE=512
 # CONFIG_CMD_CONSOLE is not set
+CONFIG_CMD_FWU_METADATA=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_SYS_BOOTM_LEN=0x800000
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
 CONFIG_CMD_LOADM=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_RTC=y
 CONFIG_CMD_TIME=y
@@ -39,6 +42,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
+CONFIG_ARM_FFA_TRANSPORT=y
 CONFIG_MISC=y
 # CONFIG_MMC is not set
 CONFIG_NVMXIP_QSPI=y
@@ -50,6 +54,16 @@ CONFIG_RAM=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_EMULATION=y
 CONFIG_DM_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
 CONFIG_USB=y
 CONFIG_USB_ISP1760=y
 CONFIG_ERRNO_STR=y
+CONFIG_EFI_MM_COMM_TEE=y
+CONFIG_FFA_SHARED_MM_BUF_SIZE=4096
+CONFIG_FFA_SHARED_MM_BUF_OFFSET=0
+CONFIG_FFA_SHARED_MM_BUF_ADDR=0x02000000
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_FWU_MULTI_BANK_UPDATE=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 47834bb6fe..da5ff5573d 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -31,7 +31,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 69ad017f98..70e1a50a24 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -33,7 +33,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 936787bb39..92f4436eeb 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -36,7 +36,6 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig
index 14e6e6c2d8..9313e7fbd1 100644
--- a/configs/dfi-bt700-q7x-151_defconfig
+++ b/configs/dfi-bt700-q7x-151_defconfig
@@ -38,7 +38,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index a45d3cb05f..c1094b4eda 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -42,9 +42,6 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
@@ -112,15 +109,18 @@ CONFIG_MXC_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="dh"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_SDP_LOADADDR=0x17ffffc0
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
 CONFIG_IMX_WATCHDOG=y
 CONFIG_BZIP2=y
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 4b3a4bfc82..a5396f7e54 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -48,9 +48,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x3F00
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_CBSIZE=2048
@@ -129,12 +126,15 @@ CONFIG_MXC_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Liebherr"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_WATCHDOG_TIMEOUT_MSECS=15000
 CONFIG_IMX_WATCHDOG=y
 CONFIG_PANIC_HANG=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 371c888c24..14dff63221 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -47,8 +47,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_CMD_SPL=y
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
@@ -148,6 +146,8 @@ CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_SPL_DFU=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 3165b9b506..0d6d9efd4e 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -44,8 +44,6 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 # CONFIG_CMD_FLASH is not set
@@ -141,6 +139,8 @@ CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_SPL_DFU=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 6ed98cf0c1..506a65aac3 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -43,8 +43,6 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
@@ -128,6 +126,8 @@ CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_SPL_DFU=y
diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig
index b4112a1471..77edbdbf95 100644
--- a/configs/eaidk-610-rk3399_defconfig
+++ b/configs/eaidk-610-rk3399_defconfig
@@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index 24edecb510..2873322598 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -52,3 +52,4 @@ CONFIG_MII=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1338=y
 CONFIG_MCFUART=y
+CONFIG_WDT=y
diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index 44e22eb01d..bd780034ba 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -50,3 +50,4 @@ CONFIG_MII=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1338=y
 CONFIG_MCFUART=y
+CONFIG_WDT=y
diff --git a/configs/edison_defconfig b/configs/edison_defconfig
index 00342aace9..8692a8a999 100644
--- a/configs/edison_defconfig
+++ b/configs/edison_defconfig
@@ -28,7 +28,6 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_HASH=y
 CONFIG_CMD_EXT4=y
diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig
index a5c629b46f..4149eea6cf 100644
--- a/configs/efi-x86_payload32_defconfig
+++ b/configs/efi-x86_payload32_defconfig
@@ -25,7 +25,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig
index 5cde04a5ac..d41f73cccf 100644
--- a/configs/efi-x86_payload64_defconfig
+++ b/configs/efi-x86_payload64_defconfig
@@ -25,7 +25,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index c3d0bc2455..f03b59e106 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -31,7 +31,6 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_UNZIP=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SAVES=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_SPI=y
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 32e022fb8a..9244654c82 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -45,7 +45,6 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000000
 CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_CRC32=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_RAM_SUPPORT=y
@@ -121,6 +120,7 @@ CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_WDT=y
 CONFIG_SHA384=y
+CONFIG_SPL_CRC32=y
 CONFIG_HEXDUMP=y
 # CONFIG_EFI_LOADER is not set
 CONFIG_PHANDLE_CHECK_SEQ=y
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 4ac161683c..d75329d385 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -100,7 +100,6 @@ CONFIG_DM_RNG=y
 CONFIG_RNG_ROCKCHIP=y
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index 29f7516e75..5f32c92674 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -76,7 +76,6 @@ CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_TPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_PANIC_HANG=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 9dcd113a95..02254ef708 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -15,7 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
 CONFIG_SPL_TEXT_BASE=0x10081000
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
 CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x60800800
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index cf73afeded..c1e7f390ad 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -31,8 +31,6 @@ CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
-CONFIG_SPL_OPTEE_IMAGE=y
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index 6950b5ba06..a13a809c1e 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -73,7 +73,6 @@ CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 580ee502dc..b9c541a92a 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -69,10 +69,12 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -87,13 +89,11 @@ CONFIG_TPL_RAM=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
@@ -101,6 +101,7 @@ CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_DWC3=y
 # CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index f594f15b3f..5740ffc38f 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -28,6 +28,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index 07819d1054..5f3fab7304 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -22,6 +22,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index d5f1c4b9eb..f49c2ca686 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -23,6 +23,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index 94b8f88a96..90b07d847c 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x10000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index 47c924c3df..11a3baa7a3 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -99,7 +99,6 @@ CONFIG_TPL_RAM=y
 CONFIG_ROCKCHIP_SDRAM_COMMON=y
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index 0ece93b71d..b4660a051d 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -30,6 +30,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 0d2ebdab92..c6d989ea6e 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -29,7 +29,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
index c8c8469d8a..7901a195aa 100644
--- a/configs/gazerbeam_defconfig
+++ b/configs/gazerbeam_defconfig
@@ -123,7 +123,6 @@ CONFIG_SYS_LOADS_BAUD_CHANGE=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_AXI=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig
index 07e357e26c..b3b69a642a 100644
--- a/configs/ge_b1x5v2_defconfig
+++ b/configs/ge_b1x5v2_defconfig
@@ -14,6 +14,7 @@ CONFIG_ENV_SECT_SIZE=0x10000
 # CONFIG_GE_RTC is not set
 CONFIG_MX6QDL=y
 CONFIG_TARGET_GE_B1X5V2=y
+CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6dl-b1x5v2"
 CONFIG_SPL_TEXT_BASE=0x00908000
 CONFIG_SPL_SERIAL=y
@@ -41,9 +42,6 @@ CONFIG_MISC_INIT_R=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
@@ -121,15 +119,18 @@ CONFIG_POWEROFF_GPIO=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Congatec"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
 CONFIG_IMX_VIDEO_SKIP=y
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index f005e91e0b..2ef560ccaa 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -34,7 +34,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_BMP=y
 CONFIG_CMD_BOOTCOUNT=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
index fdd01b6494..8f4be79831 100644
--- a/configs/geekbox_defconfig
+++ b/configs/geekbox_defconfig
@@ -26,7 +26,6 @@ CONFIG_PINCTRL=y
 CONFIG_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig
index 15dc16b00f..ed38d6ee69 100644
--- a/configs/grpeach_defconfig
+++ b/configs/grpeach_defconfig
@@ -52,6 +52,8 @@ CONFIG_SPI_FLASH_MACRONIX=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_BITBANGMII=y
 CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_SH_ETHER=y
 CONFIG_PINCTRL=y
 CONFIG_DM_REGULATOR=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index b1d9399b86..8b49505a65 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -31,7 +31,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index 06dd6b1f0e..96d15e89af 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -14,6 +14,9 @@ CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="imx28-xea"
 CONFIG_SPL_TEXT_BASE=0x1000
 CONFIG_TARGET_XEA=y
+CONFIG_SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT=y
+CONFIG_SPL_MXS_PMU_DISABLE_BATT_CHARGE=y
+# CONFIG_SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR is not set
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x20000
@@ -26,6 +29,8 @@ CONFIG_SYS_LOAD_ADDR=0x42000000
 CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_FIT=y
 CONFIG_TIMESTAMP=y
+# CONFIG_BOOTMETH_EXTLINUX is not set
+# CONFIG_BOOTMETH_VBE is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyAMA0,115200n8"
@@ -95,7 +100,7 @@ CONFIG_MMC_MXS=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=3
+CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -113,9 +118,9 @@ CONFIG_PINCTRL_MXS=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_CONS_INDEX=0
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_MXS_SPI=y
-CONFIG_FS_FAT=y
 # CONFIG_SPL_OF_LIBFDT is not set
diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig
index bb7bf5d9da..a43183444d 100644
--- a/configs/imx28_xea_sb_defconfig
+++ b/configs/imx28_xea_sb_defconfig
@@ -94,7 +94,9 @@ CONFIG_PINCTRL_MXS=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_MXS_SPI=y
diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig
index ccccb95c83..c44d43aaca 100644
--- a/configs/imx6q_bosch_acc_defconfig
+++ b/configs/imx6q_bosch_acc_defconfig
@@ -37,7 +37,6 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_RAW_IMAGE_SUPPORT=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xaa
-# CONFIG_SPL_CRC32 is not set
 # CONFIG_SPL_CRYPTO is not set
 CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
@@ -77,7 +76,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent"
 CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_MMC_ENV_PART=1
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 2bc4679451..2814e2c814 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -42,9 +42,6 @@ CONFIG_SPL_FALCON_BOOT_MMCSD=y
 CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x800
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=543
@@ -116,9 +113,12 @@ CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_USB=y
 # CONFIG_SPL_DM_USB is not set
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig
index b3220833e4..f3da19deb0 100644
--- a/configs/imx6ulz_smm_m2_defconfig
+++ b/configs/imx6ulz_smm_m2_defconfig
@@ -27,9 +27,6 @@ CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_DMA=y
 CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_CMD_DM=y
 CONFIG_CMD_GPIO=y
@@ -71,9 +68,12 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="BSH"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_SDP_LOADADDR=0x877fffc0
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig
index e18fcf9307..c43aed4a94 100644
--- a/configs/imx7_cm_defconfig
+++ b/configs/imx7_cm_defconfig
@@ -30,9 +30,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_I2C=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CMD_BOOTD is not set
@@ -102,13 +99,16 @@ CONFIG_FSL_QSPI=y
 # CONFIG_FSL_QSPI_AHB_FULL_MAP is not set
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_SPLASH_SCREEN=y
diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig
index 00f7c5434f..13bd195151 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -51,9 +51,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_CBSIZE=2048
@@ -133,14 +130,17 @@ CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 # CONFIG_USB_STORAGE is not set
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Menlo"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_SDP_LOADADDR=0x40400000
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index 4a96bd2556..52edb2ed19 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SOURCE_FILE="imx8mm_beacon"
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
@@ -40,9 +41,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=64
@@ -134,13 +132,16 @@ CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_SDP_LOADADDR=0x40400000
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig
new file mode 100644
index 0000000000..e1b75d6416
--- /dev/null
+++ b/configs/imx8mm_beacon_fspi_defconfig
@@ -0,0 +1,154 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit"
+CONFIG_SPL_TEXT_BASE=0x7E2000
+CONFIG_TARGET_IMX8MM_BEACON=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x920000
+CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_LTO=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi;"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
+CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x910000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_SYS_BOOTM_LEN=0x800000
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="FEC"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_SPL_PHY=y
+CONFIG_SPL_NOP_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_BD71837=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_SPL_CRC32=y
+CONFIG_FSPI_CONF_HEADER=y
+CONFIG_FSPI_CONF_FILE="fspi_header.bin"
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index dacd473035..ac9810fe1b 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -39,9 +39,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_CBSIZE=2048
@@ -108,14 +105,17 @@ CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 # CONFIG_USB_STORAGE is not set
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_SDP_LOADADDR=0x40400000
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig
index 4f988f5db0..9fdce5c8b5 100644
--- a/configs/imx8mm_phg_defconfig
+++ b/configs/imx8mm_phg_defconfig
@@ -39,9 +39,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_CBSIZE=2048
@@ -106,14 +103,17 @@ CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 # CONFIG_USB_STORAGE is not set
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_SDP_LOADADDR=0x40400000
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index 9d0d0ee315..a485910a52 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x8000
-CONFIG_ENV_OFFSET=0xff0000
+CONFIG_ENV_OFFSET=0x3f0000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice"
 CONFIG_SPL_TEXT_BASE=0x7E1000
@@ -19,7 +19,7 @@ CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
 CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0xff8000
+CONFIG_ENV_OFFSET_REDUND=0x3f8000
 CONFIG_SYS_LOAD_ADDR=0x48200000
 CONFIG_SYS_MEMTEST_START=0x40000000
 CONFIG_SYS_MEMTEST_END=0x80000000
@@ -36,6 +36,7 @@ CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
@@ -51,6 +52,7 @@ CONFIG_SYS_PBSIZE=2074
 CONFIG_SYS_BOOTM_LEN=0x10000000
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
 CONFIG_CRC32_VERIFY=y
 CONFIG_CMD_MD5SUM=y
 CONFIG_MD5SUM_VERIFY=y
@@ -89,6 +91,7 @@ CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_IMX8MM=y
 CONFIG_CLK_IMX8MM=y
 CONFIG_GPIO_HOG=y
+CONFIG_DM_GPIO_LOOKUP_LABEL=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_LED=y
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index 494085b373..fab3ab154b 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="imx8mn_beacon"
 CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index 629025a7eb..f810d4be61 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="imx8mn_beacon"
 CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig
index dade877a14..8705d9bccc 100644
--- a/configs/imx8mn_beacon_fspi_defconfig
+++ b/configs/imx8mn_beacon_fspi_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="imx8mn_beacon"
 CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index 350c0225a6..b346b14ebd 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -23,12 +23,15 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
 CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_OF_BOARD_FIXUP=y
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb"
+CONFIG_BOARD_TYPES=y
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -76,6 +79,7 @@ CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_UUU_SUPPORT=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=2
 CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index 3974a384d1..39f930ae2c 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x8000
-CONFIG_ENV_OFFSET=0xff0000
+CONFIG_ENV_OFFSET=0x3f0000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mn-venice"
 CONFIG_SPL_TEXT_BASE=0x912000
@@ -19,7 +19,7 @@ CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x980000
 CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0xff8000
+CONFIG_ENV_OFFSET_REDUND=0x3f8000
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
 CONFIG_SYS_LOAD_ADDR=0x48200000
 CONFIG_SYS_MEMTEST_START=0x40000000
@@ -38,6 +38,7 @@ CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SYS_SPL_MALLOC=y
@@ -54,6 +55,7 @@ CONFIG_SYS_PBSIZE=2074
 CONFIG_SYS_BOOTM_LEN=0x10000000
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
 CONFIG_CRC32_VERIFY=y
 CONFIG_CMD_MD5SUM=y
 CONFIG_MD5SUM_VERIFY=y
@@ -90,6 +92,7 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_CLK_IMX8MN=y
 CONFIG_CLK_IMX8MN=y
 CONFIG_GPIO_HOG=y
+CONFIG_DM_GPIO_LOOKUP_LABEL=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_LED=y
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index 99c4043ace..2570eb6a88 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -34,6 +34,7 @@ CONFIG_ARMV8_SECURE_BASE=0x970000
 CONFIG_ARMV8_EA_EL3_FIRST=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
 CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_LTO=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
index 34a7f179d1..2ff577f2d8 100644
--- a/configs/imx8mp_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -95,7 +95,6 @@ CONFIG_MD5SUM_VERIFY=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_SHA1SUM=y
 CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_BIND=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_FUSE=y
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index 60ab31b6e8..14ac499e58 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -90,7 +90,6 @@ CONFIG_MD5SUM_VERIFY=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_SHA1SUM=y
 CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_BIND=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_FUSE=y
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig
index 6a98a90605..3b26f315bb 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -91,7 +91,6 @@ CONFIG_MD5SUM_VERIFY=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_SHA1SUM=y
 CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_BIND=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_FUSE=y
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index a6f6ec67c5..294206ba8b 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x8000
-CONFIG_ENV_OFFSET=0xff0000
+CONFIG_ENV_OFFSET=0x3f0000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mp-venice"
 CONFIG_SPL_TEXT_BASE=0x920000
@@ -19,7 +19,7 @@ CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
 CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0xff8000
+CONFIG_ENV_OFFSET_REDUND=0x3f8000
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
 CONFIG_SYS_LOAD_ADDR=0x40480000
 CONFIG_SYS_MEMTEST_START=0x40000000
@@ -38,6 +38,7 @@ CONFIG_SPL_MAX_SIZE=0x26000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x98fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SYS_SPL_MALLOC=y
@@ -54,6 +55,7 @@ CONFIG_SYS_PBSIZE=2074
 CONFIG_SYS_BOOTM_LEN=0x10000000
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
 CONFIG_CRC32_VERIFY=y
 CONFIG_CMD_MD5SUM=y
 CONFIG_MD5SUM_VERIFY=y
@@ -75,7 +77,7 @@ CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw74xx"
+CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw74xx imx8mp-venice-gw7905-2x"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_MMC_ENV_DEV=2
@@ -87,6 +89,7 @@ CONFIG_SPL_DM=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_IMX8MP=y
 CONFIG_GPIO_HOG=y
+CONFIG_DM_GPIO_LOOKUP_LABEL=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_LED=y
diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig
index 89edebc4c6..65f473885c 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -7,7 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_OFFSET=0x700000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk"
 CONFIG_SPL_TEXT_BASE=0x2049A000
@@ -81,6 +81,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_ADC_IMX93=y
 CONFIG_CPU=y
 CONFIG_CPU_IMX=y
 CONFIG_IMX_RGPIO2P=y
diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
index a71de4960a..40210a5f0b 100644
--- a/configs/imxrt1020-evk_defconfig
+++ b/configs/imxrt1020-evk_defconfig
@@ -29,7 +29,6 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
-# CONFIG_SPL_CRC32 is not set
 CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 # CONFIG_BOOTM_NETBSD is not set
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index f451a0d0d6..8f7a36fea7 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -32,7 +32,6 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
-# CONFIG_SPL_CRC32 is not set
 CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 # CONFIG_BOOTM_NETBSD is not set
diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig
index 0030733e09..8320c091d2 100644
--- a/configs/imxrt1170-evk_defconfig
+++ b/configs/imxrt1170-evk_defconfig
@@ -24,7 +24,6 @@ CONFIG_SYS_LOAD_ADDR=0x202C0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SD_BOOT=y
 # CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_BOARD_INIT=y
@@ -32,7 +31,6 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
-# CONFIG_SPL_CRC32 is not set
 # CONFIG_BOOTM_NETBSD is not set
 # CONFIG_BOOTM_PLAN9 is not set
 # CONFIG_BOOTM_RTEMS is not set
diff --git a/configs/iot2050_pg1_defconfig b/configs/iot2050_defconfig
index cc1b9673d7..bcbaa92ee8 100644
--- a/configs/iot2050_pg1_defconfig
+++ b/configs/iot2050_defconfig
@@ -8,7 +8,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SOC_K3_AM654=y
-CONFIG_TARGET_IOT2050_A53_PG1=y
+CONFIG_TARGET_IOT2050_A53=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80100000
 CONFIG_ENV_SIZE=0x20000
@@ -29,12 +29,17 @@ CONFIG_SPL_SPI=y
 CONFIG_PCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTSTAGE=y
 CONFIG_SHOW_BOOT_PROGRESS=y
 CONFIG_SPL_SHOW_BOOT_PROGRESS=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_FLUSH_STDIN=y
+CONFIG_AUTOBOOT_PROMPT="Hit SPACE to stop autoboot in %d seconds...\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_BOOTCOMMAND="run start_watchdog; run distro_bootcmd"
 CONFIG_CONSOLE_MUX=y
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -73,7 +78,6 @@ CONFIG_CMD_TIME=y
 # CONFIG_ISO_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="k3-am6528-iot2050-basic k3-am6548-iot2050-advanced"
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_OF_LIST="k3-am65-iot2050-spl"
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
diff --git a/configs/iot2050_pg2_defconfig b/configs/iot2050_pg2_defconfig
deleted file mode 100644
index c5741a4dae..0000000000
--- a/configs/iot2050_pg2_defconfig
+++ /dev/null
@@ -1,150 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_ARCH_K3=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_AM654=y
-CONFIG_TARGET_IOT2050_A53_PG2=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80100000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x680000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic-pg2"
-CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_SYS_PROMPT="IOT2050> "
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_DM_RESET=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_ENV_OFFSET_REDUND=0x6a0000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-CONFIG_PCI=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTSTAGE=y
-CONFIG_SHOW_BOOT_PROGRESS=y
-CONFIG_SPL_SHOW_BOOT_PROGRESS=y
-CONFIG_BOOTCOMMAND="run start_watchdog; run distro_bootcmd"
-CONFIG_CONSOLE_MUX=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_MAX_SIZE=0x58000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80a00000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x380000
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1050
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_WDT=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="k3-am6528-iot2050-basic-pg2 k3-am6548-iot2050-advanced-pg2 k3-am6548-iot2050-advanced-m2"
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_OF_LIST="k3-am65-iot2050-spl"
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_DMA_CHANNELS=y
-CONFIG_TI_K3_NAVSS_UDMA=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_LED=y
-CONFIG_SPL_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_SPL_LED_GPIO=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_AM654=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PCI_KEYSTONE=y
-CONFIG_PHY=y
-CONFIG_AM654_PHY=y
-CONFIG_OMAP_USB2_PHY=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SOC_DEVICE=y
-CONFIG_SOC_DEVICE_TI_K3=y
-CONFIG_SOC_TI=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_KEYBOARD=y
-# CONFIG_WATCHDOG is not set
-# CONFIG_WATCHDOG_AUTOSTART is not set
-CONFIG_WATCHDOG_TIMEOUT_MSECS=0
-CONFIG_WDT=y
-CONFIG_WDT_K3_RTI=y
-CONFIG_WDT_K3_RTI_LOAD_FW=y
-CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index e40900fffa..ad8492a17e 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -12,7 +12,6 @@ CONFIG_TARGET_J7200_A72_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
 CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x680000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board"
@@ -23,7 +22,6 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_ENV_OFFSET_REDUND=0x6A0000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -35,7 +33,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
+CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
 CONFIG_LOGLEVEL=7
 CONFIG_SPL_MAX_SIZE=0xc0000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -47,7 +45,7 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
 CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
@@ -64,8 +62,6 @@ CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_CMD_ASKENV=y
@@ -80,7 +76,6 @@ CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
@@ -92,8 +87,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
@@ -101,7 +94,6 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
@@ -197,9 +189,11 @@ CONFIG_USB_CDNS3_GADGET=y
 CONFIG_USB_CDNS3_HOST=y
 CONFIG_SPL_USB_CDNS3_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
+CONFIG_SPL_DFU=y
 CONFIG_UFS=y
 CONFIG_CADENCE_UFS=y
 CONFIG_TI_J721E_UFS=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 94a6523f06..c4dd33627b 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -43,7 +43,7 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
 CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
 CONFIG_SPL_EARLY_BSS=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
 CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FS_EXT4=y
@@ -61,8 +61,6 @@ CONFIG_SPL_REMOTEPROC=y
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=64
@@ -160,10 +158,12 @@ CONFIG_USB_CDNS3=y
 CONFIG_USB_CDNS3_GADGET=y
 CONFIG_SPL_USB_CDNS3_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
 CONFIG_LIB_RATIONAL=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index eaf83e0a01..214fa8b2f3 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -33,7 +33,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
+CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
 CONFIG_LOGLEVEL=7
 CONFIG_SPL_MAX_SIZE=0xc0000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -62,8 +62,6 @@ CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_CMD_ASKENV=y
@@ -78,7 +76,6 @@ CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
@@ -93,18 +90,13 @@ CONFIG_OF_LIST="k3-j721e-common-proc-board k3-j721e-sk"
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
-CONFIG_ENV_IS_IN_FAT=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
@@ -201,9 +193,11 @@ CONFIG_USB_CDNS3_GADGET=y
 CONFIG_USB_CDNS3_HOST=y
 CONFIG_SPL_USB_CDNS3_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
+CONFIG_SPL_DFU=y
 CONFIG_UFS=y
 CONFIG_CADENCE_UFS=y
 CONFIG_TI_J721E_UFS=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index afe1f3a313..cf7bc872b5 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -10,7 +10,7 @@ CONFIG_SOC_K3_J721E=y
 CONFIG_K3_EARLY_CONS=y
 CONFIG_TARGET_J721E_R5_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
@@ -22,22 +22,19 @@ CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL_SIZE_LIMIT=0xf59f0
-CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
-CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
-CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_USE_BOOTCOMMAND=y
 # CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
 CONFIG_SPL_MAX_SIZE=0xf59f0
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x41cf59f0
@@ -69,8 +66,6 @@ CONFIG_SPL_REMOTEPROC=y
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=64
@@ -173,10 +168,12 @@ CONFIG_USB_CDNS3=y
 CONFIG_USB_CDNS3_GADGET=y
 CONFIG_SPL_USB_CDNS3_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
 CONFIG_LIB_RATIONAL=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 594c8dad2c..09addcbb25 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -32,7 +32,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
+CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
 CONFIG_LOGLEVEL=7
 CONFIG_SPL_MAX_SIZE=0xc0000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -62,8 +62,6 @@ CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
 CONFIG_SPL_THERMAL=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_CMD_ASKENV=y
@@ -78,7 +76,6 @@ CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
@@ -91,17 +88,13 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="k3-j721s2-common-proc-board k3-am68-sk-base-board"
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FAT=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
@@ -205,9 +198,11 @@ CONFIG_USB_CDNS3_GADGET=y
 CONFIG_USB_CDNS3_HOST=y
 CONFIG_SPL_USB_CDNS3_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
+CONFIG_SPL_DFU=y
 CONFIG_UFS=y
 CONFIG_CADENCE_UFS=y
 CONFIG_TI_J721E_UFS=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 4ddbe8faef..1e66ac23d0 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -68,8 +68,6 @@ CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_SPL_THERMAL=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=64
@@ -169,10 +167,12 @@ CONFIG_USB_CDNS3=y
 CONFIG_USB_CDNS3_GADGET=y
 CONFIG_SPL_USB_CDNS3_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
 CONFIG_PANIC_HANG=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index b2a39e0c84..d808628158 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -40,7 +40,6 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 6d9d82594e..44bed00ec9 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -58,7 +58,6 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_DNS2=y
 CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index c782bf1183..55c0182f87 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -34,7 +34,6 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_DNS2=y
 CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 756e7502a1..45c7fade32 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -56,7 +56,6 @@ CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_DNS2=y
 CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index f0de3232e9..54a980cab5 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -33,7 +33,6 @@ CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_DNS2=y
 CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice"
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 74ef0668d8..a265178048 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -58,7 +58,6 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_DNS2=y
 CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index 5bd8c28f54..8c0472dcc2 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -34,7 +34,6 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_DNS2=y
 CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 378a71f94e..55ddd3cce9 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -58,7 +58,6 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_DNS2=y
 CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index 31ec3029d7..ce7aa3a39e 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -35,7 +35,6 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_DNS2=y
 CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
 CONFIG_CMD_UBI=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig
index 0651b982f5..2800c47361 100644
--- a/configs/khadas-edge-captain-rk3399_defconfig
+++ b/configs/khadas-edge-captain-rk3399_defconfig
@@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_SYS_PBSIZE=1048
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
index 85e18aaa1a..33b2afd869 100644
--- a/configs/khadas-edge-rk3399_defconfig
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_SYS_PBSIZE=1048
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig
index 7fe559b49e..f7a6445b3c 100644
--- a/configs/khadas-edge-v-rk3399_defconfig
+++ b/configs/khadas-edge-v-rk3399_defconfig
@@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_SYS_PBSIZE=1048
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig
index 0dbf7eacdb..d54e60395d 100644
--- a/configs/kontron-sl-mx6ul_defconfig
+++ b/configs/kontron-sl-mx6ul_defconfig
@@ -36,9 +36,6 @@ CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
@@ -100,11 +97,14 @@ CONFIG_FSL_QSPI=y
 CONFIG_MXC_SPI=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index d232f5cfe2..1aab157591 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -17,7 +17,6 @@ CONFIG_SPL_TEXT_BASE=0x10081000
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_KYLIN_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
 CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x60800800
diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig
index c118459688..fa936609e9 100644
--- a/configs/leez-rk3399_defconfig
+++ b/configs/leez-rk3399_defconfig
@@ -25,6 +25,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig
index b846a8320c..973b2ea20c 100644
--- a/configs/librem5_defconfig
+++ b/configs/librem5_defconfig
@@ -50,8 +50,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_PBSIZE=1050
@@ -144,8 +142,10 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Purism"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_SDP_LOADADDR=0x40400000
 CONFIG_USB_FUNCTION_ACM=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 2a180609b2..7c55b3be0d 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -95,7 +95,6 @@ CONFIG_SPL_RAM=y
 CONFIG_TPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSINFO=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 069a8dc0c3..ea195d7c50 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -86,7 +86,9 @@ CONFIG_NVME_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index e796c0a9a2..ae8600ffd9 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -89,7 +89,9 @@ CONFIG_NVME_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index f5faa02e59..d9ff0fd16a 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -110,7 +110,9 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index b75550b2d3..ad11818743 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -117,7 +117,8 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPL_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 3e0d16430e..fe0dd04f1f 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -110,7 +110,9 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 04e66f1e6c..aa5404cbb5 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -115,7 +115,8 @@ CONFIG_NVME_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPL_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index cf4623eb63..480e928936 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -84,7 +84,9 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 15e2916538..e259041708 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -90,7 +90,9 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
index 8d6a1371ac..d280cf8e6b 100644
--- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
@@ -30,6 +30,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_PBSIZE=532
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -61,13 +62,16 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index e5d2b556f7..207f411397 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -34,6 +34,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_PBSIZE=532
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -67,6 +68,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
@@ -76,7 +78,9 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index 7be98df566..924ff78b45 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -111,7 +111,8 @@ CONFIG_POWER_LEGACY=y
 CONFIG_POWER_I2C=y
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPL_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index 3cefae092f..bb278845e0 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -86,7 +86,9 @@ CONFIG_POWER_LEGACY=y
 CONFIG_POWER_I2C=y
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 02979dd2ff..0fb1a6c281 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -90,7 +90,9 @@ CONFIG_POWER_LEGACY=y
 CONFIG_POWER_I2C=y
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index 8f7d05fab9..eb0184c592 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -118,7 +118,8 @@ CONFIG_POWER_LEGACY=y
 CONFIG_POWER_I2C=y
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPL_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 900e26be3b..2813c79f59 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -109,7 +109,9 @@ CONFIG_POWER_LEGACY=y
 CONFIG_POWER_I2C=y
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SCSI_AHCI_PLAT=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index ded6be50a3..a621859aa7 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -111,7 +111,8 @@ CONFIG_POWER_LEGACY=y
 CONFIG_POWER_I2C=y
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPL_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index 3eaa985ec7..fbcf294eb5 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -79,7 +79,9 @@ CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_POWER_LEGACY=y
 CONFIG_POWER_I2C=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 7e8d86d03c..24a54230f8 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -85,7 +85,9 @@ CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_POWER_LEGACY=y
 CONFIG_POWER_I2C=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig
new file mode 100644
index 0000000000..b01d3bd2a1
--- /dev/null
+++ b/configs/lubancat-2-rk3568_defconfig
@@ -0,0 +1,85 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+# CONFIG_SPI_FLASH is not set
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
+CONFIG_EFI_VAR_BUF_SIZE=16384
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
index 03de161684..a69e1934fe 100644
--- a/configs/malta64_defconfig
+++ b/configs/malta64_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_IDE=y
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 # CONFIG_ISO_PARTITION is not set
diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
index 3ea9fa9857..21a291d341 100644
--- a/configs/malta64el_defconfig
+++ b/configs/malta64el_defconfig
@@ -28,7 +28,6 @@ CONFIG_CMD_IDE=y
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 # CONFIG_ISO_PARTITION is not set
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index 317b422a6b..8c76ebbb15 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -25,7 +25,6 @@ CONFIG_CMD_IDE=y
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 # CONFIG_ISO_PARTITION is not set
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index 3e4d2beda2..4abd3b1558 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -27,7 +27,6 @@ CONFIG_CMD_IDE=y
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 # CONFIG_ISO_PARTITION is not set
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index 47fcf1574e..e99bb8f5b5 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -31,7 +31,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 6aa1d03e5b..589da3226d 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0xc0000
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
 CONFIG_SYS_PROMPT="U-Boot-mONStR> "
 CONFIG_SPL_SERIAL=y
diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig
index c03c8ec6ec..fa49d3865f 100644
--- a/configs/microchip_mpfs_icicle_defconfig
+++ b/configs/microchip_mpfs_icicle_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
+CONFIG_DEFAULT_DEVICE_TREE="mpfs-icicle-kit"
 CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_SYS_MEM_TOP_HIDE=0x400000
 CONFIG_SYS_LOAD_ADDR=0x80200000
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 6082b8d70d..8347a9dcec 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -43,7 +43,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig
index b30b804dbf..e3ff906098 100644
--- a/configs/mscc_jr2_defconfig
+++ b/configs/mscc_jr2_defconfig
@@ -44,7 +44,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_DHCP=y
 # CONFIG_NET_TFTP_VARS is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
index 9a1e0c3e06..e811bc97e1 100644
--- a/configs/mscc_luton_defconfig
+++ b/configs/mscc_luton_defconfig
@@ -46,7 +46,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_DHCP=y
 # CONFIG_NET_TFTP_VARS is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
index a372b21f66..f3246f2219 100644
--- a/configs/mscc_ocelot_defconfig
+++ b/configs/mscc_ocelot_defconfig
@@ -44,7 +44,6 @@ CONFIG_CMD_MTD=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_DHCP=y
 # CONFIG_NET_TFTP_VARS is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig
index 055ed68305..4ff7933717 100644
--- a/configs/mscc_serval_defconfig
+++ b/configs/mscc_serval_defconfig
@@ -41,7 +41,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_DHCP=y
 # CONFIG_NET_TFTP_VARS is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
diff --git a/configs/mscc_servalt_defconfig b/configs/mscc_servalt_defconfig
index 6e225a6938..5f6ed73c2e 100644
--- a/configs/mscc_servalt_defconfig
+++ b/configs/mscc_servalt_defconfig
@@ -40,7 +40,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_DHCP=y
 # CONFIG_NET_TFTP_VARS is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
diff --git a/configs/mt7620_mt7530_rfb_defconfig b/configs/mt7620_mt7530_rfb_defconfig
index 96f10926b1..af9df547d5 100644
--- a/configs/mt7620_mt7530_rfb_defconfig
+++ b/configs/mt7620_mt7530_rfb_defconfig
@@ -38,7 +38,6 @@ CONFIG_SYS_BOOTM_LEN=0x1000000
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SPI=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 # CONFIG_CMD_MDIO is not set
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupts resets reset-names"
diff --git a/configs/mt7620_rfb_defconfig b/configs/mt7620_rfb_defconfig
index d96da91df3..fe57fd1892 100644
--- a/configs/mt7620_rfb_defconfig
+++ b/configs/mt7620_rfb_defconfig
@@ -39,7 +39,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 # CONFIG_CMD_MDIO is not set
 CONFIG_CMD_FAT=y
diff --git a/configs/mt7621_nand_rfb_defconfig b/configs/mt7621_nand_rfb_defconfig
index 5291bb300e..368bf80096 100644
--- a/configs/mt7621_nand_rfb_defconfig
+++ b/configs/mt7621_nand_rfb_defconfig
@@ -49,7 +49,6 @@ CONFIG_CMD_MTD=y
 CONFIG_CMD_PART=y
 # CONFIG_CMD_PINMUX is not set
 CONFIG_CMD_USB=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 # CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/mt7621_rfb_defconfig b/configs/mt7621_rfb_defconfig
index b50fbec92d..49c9e7411d 100644
--- a/configs/mt7621_rfb_defconfig
+++ b/configs/mt7621_rfb_defconfig
@@ -47,7 +47,6 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 # CONFIG_CMD_PINMUX is not set
 CONFIG_CMD_SPI=y
-# CONFIG_CMD_NFS is not set
 CONFIG_DOS_PARTITION=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig
index a7687b54f0..20c84d65df 100644
--- a/configs/mt7623a_unielec_u7623_02_defconfig
+++ b/configs/mt7623a_unielec_u7623_02_defconfig
@@ -31,7 +31,6 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_READ=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig
index 62a17f2cbc..5e7c1fefad 100644
--- a/configs/mt7623n_bpir2_defconfig
+++ b/configs/mt7623n_bpir2_defconfig
@@ -31,7 +31,6 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_READ=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/mt7628_rfb_defconfig b/configs/mt7628_rfb_defconfig
index 0e100fca49..7e5b76c590 100644
--- a/configs/mt7628_rfb_defconfig
+++ b/configs/mt7628_rfb_defconfig
@@ -37,7 +37,6 @@ CONFIG_SYS_BOOTM_LEN=0x1000000
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SPI=y
-# CONFIG_CMD_NFS is not set
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig
index ea8d77c0a2..0e3bd4ffa7 100644
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -48,7 +48,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/mt7988_rfb_defconfig b/configs/mt7988_rfb_defconfig
new file mode 100644
index 0000000000..dc97bb36ea
--- /dev/null
+++ b/configs/mt7988_rfb_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
+CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_TARGET_MT7988=y
+CONFIG_DEBUG_UART_BASE=0x11000000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_DEBUG_UART=y
+# CONFIG_AUTOBOOT is not set
+CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
+CONFIG_LOGLEVEL=7
+CONFIG_LOG=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SMC=y
+CONFIG_DOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_NETMASK=y
+CONFIG_NETMASK="255.255.255.0"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.2"
+CONFIG_PROT_TCP=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_FIXED=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPIM=y
+CONFIG_LZO=y
+CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/mt7988_sd_rfb_defconfig b/configs/mt7988_sd_rfb_defconfig
new file mode 100644
index 0000000000..421999da86
--- /dev/null
+++ b/configs/mt7988_sd_rfb_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb"
+CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_TARGET_MT7988=y
+CONFIG_DEBUG_UART_BASE=0x11000000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_DEBUG_UART=y
+# CONFIG_AUTOBOOT is not set
+CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
+CONFIG_LOGLEVEL=7
+CONFIG_LOG=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SMC=y
+CONFIG_DOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_NETMASK=y
+CONFIG_NETMASK="255.255.255.0"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.2"
+CONFIG_PROT_TCP=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_PHY_FIXED=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPIM=y
+CONFIG_LZO=y
+CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig
index 0a4c2189f3..dbf1e3136c 100644
--- a/configs/mvebu_ac5_rd_defconfig
+++ b/configs/mvebu_ac5_rd_defconfig
@@ -18,7 +18,6 @@ CONFIG_SYS_MEMTEST_END=0x200ffffff
 CONFIG_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=-1
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index 89b69fb323..335de62e84 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -14,7 +14,6 @@ CONFIG_TARGET_MX23_OLINUXINO=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x42000000
-# CONFIG_SYS_MALLOC_F is not set
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loaduimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
@@ -50,6 +49,7 @@ CONFIG_LED_STATUS_BOOT=0
 CONFIG_LED_STATUS_CMD=y
 CONFIG_MMC_MXS=y
 CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_HOST_ETHER=y
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index 3602ead863..7d0e7cc1e0 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -49,6 +49,7 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index dad8839a6c..df0cceaea7 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -62,6 +62,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_RTC_MXS=y
-CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
 CONFIG_SPI=y
 CONFIG_USB=y
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 503a733fc2..ee518cab6d 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -35,9 +35,6 @@ CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
@@ -101,16 +98,19 @@ CONFIG_DM_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 # CONFIG_VIDEO_BPP8 is not set
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index a0befcc6ce..0a8b0477b4 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -33,9 +33,6 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
@@ -109,13 +106,16 @@ CONFIG_DM_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 # CONFIG_VIDEO_BPP8 is not set
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 1572afb2b5..0e036606c1 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -33,9 +33,6 @@ CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
 CONFIG_SPL_I2C=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
@@ -94,13 +91,16 @@ CONFIG_FSL_QSPI=y
 CONFIG_SOFT_SPI=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig
index 637860c281..8e3938dcaa 100644
--- a/configs/myir_mys_6ulx_defconfig
+++ b/configs/myir_mys_6ulx_defconfig
@@ -23,8 +23,6 @@ CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_DMA=y
 CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
@@ -70,4 +68,6 @@ CONFIG_SYSINFO=y
 CONFIG_SYSINFO_SMBIOS=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index 75589bb519..82e86ca070 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -28,6 +28,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig
index 04ce5438f4..dd715517d5 100644
--- a/configs/nanopi-m4-2gb-rk3399_defconfig
+++ b/configs/nanopi-m4-2gb-rk3399_defconfig
@@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
index 6745934d98..3da93db06d 100644
--- a/configs/nanopi-m4-rk3399_defconfig
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig
index 1a9839b4d1..701dde15f3 100644
--- a/configs/nanopi-m4b-rk3399_defconfig
+++ b/configs/nanopi-m4b-rk3399_defconfig
@@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig
index ad0627fe65..3f9d0340c8 100644
--- a/configs/nanopi-neo4-rk3399_defconfig
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig
index 84710c185b..583179d7c5 100644
--- a/configs/nanopi-r2c-rk3328_defconfig
+++ b/configs/nanopi-r2c-rk3328_defconfig
@@ -71,10 +71,12 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -97,7 +99,6 @@ CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
@@ -105,6 +106,7 @@ CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_DWC3=y
 # CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
index 21d7a073e2..f7ed71e412 100644
--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig
@@ -71,10 +71,12 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -97,7 +99,6 @@ CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
@@ -105,6 +106,7 @@ CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_DWC3=y
 # CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig
index a41e774b0c..4f4363cb0f 100644
--- a/configs/nanopi-r4s-rk3399_defconfig
+++ b/configs/nanopi-r4s-rk3399_defconfig
@@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig
new file mode 100644
index 0000000000..201b21ad77
--- /dev/null
+++ b/configs/nanopi-r5c-rk3568_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig
new file mode 100644
index 0000000000..67b2843070
--- /dev/null
+++ b/configs/nanopi-r5s-rk3568_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig
new file mode 100644
index 0000000000..c7bc3b1965
--- /dev/null
+++ b/configs/neu6b-io-rk3588_defconfig
@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_RK3588_NEU6=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6b-io.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index a9c10cdbb0..cc64facd5f 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -45,7 +45,6 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 459ae3d59c..eb759e0073 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -35,6 +35,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3326-odroid-go2.dtb"
 # CONFIG_CONSOLE_MUX is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_LATE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x20000
 CONFIG_SPL_PAD_TO=0x7f8000
@@ -103,7 +104,6 @@ CONFIG_TPL_RAM=y
 CONFIG_ROCKCHIP_SDRAM_COMMON=y
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig
new file mode 100644
index 0000000000..3dda5c1f91
--- /dev/null
+++ b/configs/odroid-m1-rk3568_defconfig
@@ -0,0 +1,111 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_ODROID_M1_RK3568=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-odroid-m1.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_INI=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_CRAMFS=y
+CONFIG_MTDPARTS_DEFAULT="nor0:0x100000(reserved),0x200000(uboot),0x100000(splash),0xc00000(Firmware)"
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_FS_CRAMFS=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index ce0c47e505..b1943cfd39 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -41,7 +41,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 # CONFIG_CMD_SLEEP is not set
 CONFIG_CMD_PMIC=y
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index e27e27d014..5571722ea6 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -33,7 +33,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 909f10ee79..0a8a1c77ea 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -29,7 +29,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_EFI_PARTITION is not set
 CONFIG_SPL_PARTITION_UUIDS=y
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig
new file mode 100644
index 0000000000..0ea45df333
--- /dev/null
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -0,0 +1,114 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL_STACK=0x400000
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x2000000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSINFO=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig
new file mode 100644
index 0000000000..e3d7f0b8ae
--- /dev/null
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -0,0 +1,114 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL_STACK=0x400000
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x2000000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSINFO=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig
index 0f814b1b28..ba6d91e877 100644
--- a/configs/orangepi-rk3399_defconfig
+++ b/configs/orangepi-rk3399_defconfig
@@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig
index 6cb942f511..f13735e91c 100644
--- a/configs/orangepi_zero2_defconfig
+++ b/configs/orangepi_zero2_defconfig
@@ -7,6 +7,7 @@ CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
 CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e
 CONFIG_DRAM_SUN50I_H616_TPR10=0xf83438
 CONFIG_MACH_SUN50I_H616=y
+CONFIG_SUNXI_DRAM_H616_DDR3_1333=y
 CONFIG_R_I2C_ENABLE=y
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -19,3 +20,6 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_PHY_REALTEK=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SPI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index 7e75f44c74..dcfd3eb99a 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -28,7 +28,6 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index dd773266d6..7716655278 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -35,7 +35,6 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_OF_LIVE=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index 47a0a62d25..7e2829e3a0 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -29,7 +29,6 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
index 125134db59..3cdb1a7271 100644
--- a/configs/p2771-0000-000_defconfig
+++ b/configs/p2771-0000-000_defconfig
@@ -28,7 +28,6 @@ CONFIG_CMD_POWEROFF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig
index 5ffff2c99f..41a108d3ff 100644
--- a/configs/p2771-0000-500_defconfig
+++ b/configs/p2771-0000-500_defconfig
@@ -28,7 +28,6 @@ CONFIG_CMD_POWEROFF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
index f8dbedf7f5..febd82e230 100644
--- a/configs/p3450-0000_defconfig
+++ b/configs/p3450-0000_defconfig
@@ -36,7 +36,6 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_OF_LIVE=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index fadf7fdeb0..8c125c39b2 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -28,7 +28,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index ffdb5cce8e..4a27d15cb1 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -21,6 +21,7 @@ CONFIG_SPL_STACK=0x920000
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x3E0000
 CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_LTO=y
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 3d076204ad..7bf404be86 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -21,6 +21,7 @@ CONFIG_SPL_STACK=0x960000
 CONFIG_SPL=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
 CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_LTO=y
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index 9386d6f9e9..2d06621963 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -20,7 +20,6 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
@@ -63,6 +62,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Phytec"
 CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig
index 64ebc9f57d..327ea56cb8 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -20,7 +20,6 @@ CONFIG_BOOTDELAY=3
 CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
@@ -54,6 +53,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Phytec"
 CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig
index ff5090998a..4fd588051c 100644
--- a/configs/pico-dwarf-imx6ul_defconfig
+++ b/configs/pico-dwarf-imx6ul_defconfig
@@ -27,9 +27,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb"
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 CONFIG_CMD_BOOTMENU=y
@@ -72,9 +69,12 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig
index 8a5ed1efbe..2cd906a63d 100644
--- a/configs/pico-dwarf-imx7d_defconfig
+++ b/configs/pico-dwarf-imx7d_defconfig
@@ -26,9 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CMD_BOOTD is not set
@@ -80,14 +77,17 @@ CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig
index 58d6d144af..c430b4d622 100644
--- a/configs/pico-hobbit-imx6ul_defconfig
+++ b/configs/pico-hobbit-imx6ul_defconfig
@@ -28,9 +28,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 CONFIG_CMD_BOOTMENU=y
@@ -75,9 +72,12 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
index 3cdb4d3e07..b63281e533 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -26,9 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CMD_BOOTD is not set
@@ -79,14 +76,17 @@ CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig
index 821cb970fd..be7b119ba7 100644
--- a/configs/pico-imx6_defconfig
+++ b/configs/pico-imx6_defconfig
@@ -31,9 +31,6 @@ CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
@@ -85,11 +82,14 @@ CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 # CONFIG_BACKLIGHT is not set
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index 78cd63c219..a6cbc51331 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -28,9 +28,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="ask"
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 CONFIG_CMD_BOOTMENU=y
@@ -79,12 +76,15 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 CONFIG_VIDEO_MXS=y
diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig
index 74aab863f4..546e1e6545 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -28,9 +28,6 @@ CONFIG_SPL_MAX_SIZE=0xe000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
@@ -77,15 +74,18 @@ CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index 447342f5e9..f11e1f4ef4 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -26,9 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CMD_BOOTD is not set
@@ -80,14 +77,17 @@ CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig
index 8a5ed1efbe..2cd906a63d 100644
--- a/configs/pico-nymph-imx7d_defconfig
+++ b/configs/pico-nymph-imx7d_defconfig
@@ -26,9 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CMD_BOOTD is not set
@@ -80,14 +77,17 @@ CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig
index b7d1ccd81a..3c822d10a4 100644
--- a/configs/pico-pi-imx6ul_defconfig
+++ b/configs/pico-pi-imx6ul_defconfig
@@ -28,9 +28,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb"
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 CONFIG_CMD_BOOTMENU=y
@@ -75,9 +72,12 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index 2f028c24bf..3e26aae400 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -26,9 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CMD_BOOTD is not set
@@ -80,14 +77,17 @@ CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig
index 58a8b91aa6..ae3211bbe9 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -12,6 +12,7 @@ CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_TARGET_PINEBOOK_PRO_RK3399=y
 CONFIG_SPL_STACK=0x400000
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
@@ -26,7 +27,7 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400000
@@ -36,6 +37,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig
index e4a8beeb1a..11243bc5c1 100644
--- a/configs/pinephone-pro-rk3399_defconfig
+++ b/configs/pinephone-pro-rk3399_defconfig
@@ -12,6 +12,7 @@ CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro"
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_TARGET_PINEPHONE_PRO_RK3399=y
 CONFIG_SPL_STACK=0x400000
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
@@ -25,7 +26,7 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400000
@@ -35,6 +36,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 4fee9df94f..ab9aef5e47 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -32,7 +32,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig
index b00fb48a5a..1eb339610d 100644
--- a/configs/poleg_evb_defconfig
+++ b/configs/poleg_evb_defconfig
@@ -18,6 +18,7 @@ CONFIG_DM_RESET=y
 CONFIG_TARGET_POLEG=y
 CONFIG_SYS_LOAD_ADDR=0x10000000
 CONFIG_ENV_ADDR=0x80100000
+CONFIG_FIT=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run common_bootargs; run romboot"
 CONFIG_SYS_MAXARGS=32
@@ -101,4 +102,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 # CONFIG_WATCHDOG is not set
 CONFIG_WDT_NPCM=y
 CONFIG_LIB_HW_RAND=y
+CONFIG_SHA512=y
 CONFIG_SHA_HW_ACCEL=y
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig
index abe6cfbd57..d96fd14b36 100644
--- a/configs/px30-core-ctouch2-of10-px30_defconfig
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -99,7 +99,6 @@ CONFIG_DM_RNG=y
 CONFIG_RNG_ROCKCHIP=y
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig
index e839dcb5f6..ac2af6d8cb 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -99,7 +99,6 @@ CONFIG_DM_RNG=y
 CONFIG_RNG_ROCKCHIP=y
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
index 92540e73be..a49bb4072d 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -99,7 +99,6 @@ CONFIG_DM_RNG=y
 CONFIG_RNG_ROCKCHIP=y
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index 105b937efa..5f0746e4e2 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xf00000
 CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="qemu-ppce500"
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SYS_CLK_FREQ=33000000
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index f29a5aa0f8..c6f30674a8 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -6,30 +6,39 @@ CONFIG_ENV_SIZE=0x40000
 CONFIG_MAX_CPUS=2
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
-CONFIG_SPL_TEXT_BASE=0xfffd0000
+CONFIG_SPL_TEXT_BASE=0xfffd8000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_X86_RUN_64BIT=y
 CONFIG_TARGET_QEMU_X86_64=y
 CONFIG_DEBUG_UART=y
+# CONFIG_HAVE_MICROCODE is not set
 CONFIG_SMP=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_X86_OFFSET_U_BOOT=0xfff00000
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_SYS_MONITOR_BASE=0x01110000
-CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SHOW_BOOT_PROGRESS=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_LOG=y
+CONFIG_LOGF_FUNC=y
+CONFIG_SPL_LOG=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_PCI_INIT_R=y
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_ADDR=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
+CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_CPU=y
 CONFIG_SPL_ENV_SUPPORT=y
@@ -42,12 +51,13 @@ CONFIG_SYS_PBSIZE=532
 CONFIG_CMD_CPU=y
 CONFIG_CMD_BOOTEFI_SELFTEST=y
 CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_MEM_SEARCH=y
 CONFIG_CMD_IDE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
+CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
@@ -69,13 +79,16 @@ CONFIG_LBA48=y
 CONFIG_SYS_64BIT_LBA=y
 CONFIG_CPU=y
 CONFIG_NVME_PCI=y
+CONFIG_SPL_PCI_PNP=y
 CONFIG_SPL_DM_RTC=y
 CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_KEYBOARD=y
+CONFIG_SPL_VIDEO=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
 CONFIG_FRAMEBUFFER_VESA_MODE=0x144
 CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_GENERATE_ACPI_TABLE=y
 # CONFIG_GZIP is not set
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 9bf29647fe..24682a5387 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -5,17 +5,23 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_ENV_SIZE=0x40000
 CONFIG_MAX_CPUS=2
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_DEBUG_UART=y
 CONFIG_SMP=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_FIT=y
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SHOW_BOOT_PROGRESS=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_LOG=y
+CONFIG_LOGF_FUNC=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_PCI_INIT_R=y
@@ -23,12 +29,13 @@ CONFIG_SYS_PBSIZE=532
 CONFIG_CMD_CPU=y
 CONFIG_CMD_BOOTEFI_SELFTEST=y
 CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_MEM_SEARCH=y
 CONFIG_CMD_IDE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
+CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig
new file mode 100644
index 0000000000..d55b224fea
--- /dev/null
+++ b/configs/quartz64-a-rk3566_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_QUARTZ64_RK3566=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig
new file mode 100644
index 0000000000..b98c81f9dc
--- /dev/null
+++ b/configs/quartz64-b-rk3566_defconfig
@@ -0,0 +1,106 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-b"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_QUARTZ64_RK3566=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-b.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig
new file mode 100644
index 0000000000..e26607a897
--- /dev/null
+++ b/configs/r8a77970_v3msk_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=16666666
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a77970-v3msk-u-boot"
+CONFIG_SPL_TEXT_BASE=0xe6318000
+CONFIG_RCAR_GEN3=y
+CONFIG_R8A77970=y
+CONFIG_TARGET_V3MSK=y
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_SPL_STACK=0xe6304000
+CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_LTO=y
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTARGS=y
+CONFIG_DEFAULT_FDT_FILE="r8a77970-v3msk.dtb"
+CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0xe631f000
+CONFIG_SPL_BSS_MAX_SIZE=0x1000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=2068
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_DTB_PROPS_REMOVE=y
+CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_BITBANGMII=y
+CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
+CONFIG_SYSRESET=y
diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig
new file mode 100644
index 0000000000..0025c044c0
--- /dev/null
+++ b/configs/r8a77980_v3hsk_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=16666666
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a77980-v3hsk-u-boot"
+CONFIG_SPL_TEXT_BASE=0xe6318000
+CONFIG_RCAR_GEN3=y
+CONFIG_R8A77980=y
+CONFIG_TARGET_V3HSK=y
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_SPL_STACK=0xe6304000
+CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_LTO=y
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_DEFAULT_FDT_FILE="r8a77980-v3hsk.dtb"
+# CONFIG_BOARD_EARLY_INIT_F is not set
+CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0xe631f000
+CONFIG_SPL_BSS_MAX_SIZE=0x1000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=2068
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_DTB_PROPS_REMOVE=y
+CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_BITBANGMII=y
+CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_SH_ETHER=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
+CONFIG_SYSRESET=y
diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig
index 56802d85cc..f89777184c 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -22,6 +22,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -74,8 +75,8 @@ CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig
new file mode 100644
index 0000000000..a905100a79
--- /dev/null
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index e9234efc2a..cdec0c52e6 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -111,7 +111,6 @@ CONFIG_DM_RNG=y
 CONFIG_RNG_ROCKCHIP=y
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 8eafd52a6b..9a789b212f 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -73,7 +73,6 @@ CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
index 6b3bc75ae9..4ac3c9403b 100644
--- a/configs/roc-cc-rk3328_defconfig
+++ b/configs/roc-cc-rk3328_defconfig
@@ -72,12 +72,14 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -102,7 +104,6 @@ CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
@@ -110,6 +111,7 @@ CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_DWC3=y
 # CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig
index 9321292ca5..06d97c3e1a 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -13,6 +13,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine"
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_TARGET_ROC_PC_RK3399=y
 CONFIG_SPL_STACK=0x400000
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
@@ -26,7 +27,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400000
@@ -37,6 +38,8 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index 824b4041c2..c53e862243 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -14,6 +14,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc"
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_TARGET_ROC_PC_RK3399=y
 CONFIG_SPL_STACK=0x400000
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
@@ -27,7 +28,7 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400000
@@ -38,6 +39,8 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 616499f2f8..44ff054df6 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -22,11 +22,14 @@ CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -45,6 +48,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PMIC=y
@@ -53,8 +57,11 @@ CONFIG_CMD_REGULATOR=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
@@ -65,10 +72,14 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_XTX=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_SPL_PINCTRL=y
@@ -77,6 +88,8 @@ CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
@@ -84,10 +97,10 @@ CONFIG_ROCKCHIP_SFC=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig
index 3c79d2ac3d..3028a86705 100644
--- a/configs/rock-4c-plus-rk3399_defconfig
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -31,6 +31,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_NVEDIT_EFI=y
diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig
new file mode 100644
index 0000000000..9abe8bf853
--- /dev/null
+++ b/configs/rock-4se-rk3399_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00200000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x400000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DFU_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_ROCKCHIP_LPDDR4=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index 4b984adc6e..84e0dcf028 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -20,6 +20,7 @@ CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
@@ -32,6 +33,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_NVEDIT_EFI=y
diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig
index 1c7648c1f0..5c9fb14787 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -31,6 +31,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_NVEDIT_EFI=y
diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig
index 9c67d0c5fe..c0375beffe 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -73,11 +73,12 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PHY=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -95,7 +96,6 @@ CONFIG_TPL_RAM=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSINFO=y
 CONFIG_SYSINFO_SMBIOS=y
@@ -103,7 +103,6 @@ CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
@@ -111,6 +110,7 @@ CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_DWC3=y
 # CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig
index 8eb17d8fec..1978fd525b 100644
--- a/configs/rock-pi-n10-rk3399pro_defconfig
+++ b/configs/rock-pi-n10-rk3399pro_defconfig
@@ -32,6 +32,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig
index c6fae07913..cc3274a98b 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -18,6 +18,7 @@ CONFIG_SPL_STACK_R_ADDR=0xc00000
 CONFIG_SPL_STACK=0x400000
 CONFIG_DEBUG_UART_BASE=0xFF0A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
+# CONFIG_DEBUG_UART_BOARD_INIT is not set
 CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_ANDROID_BOOT_IMAGE=y
@@ -73,7 +74,6 @@ CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
new file mode 100644
index 0000000000..39e352509a
--- /dev/null
+++ b/configs/rock5a-rk3588s_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x1000000
+CONFIG_TARGET_ROCK5A_RK3588=y
+CONFIG_SPL_STACK=0x1000000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index c1155c20ef..3fa65cbf9b 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_COUNTER_FREQUENCY=24000000
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
@@ -29,10 +30,12 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_PCI_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -46,18 +49,22 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MISC=y
@@ -67,13 +74,17 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_XTX=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_RTL8169=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_PWM_ROCKCHIP=y
@@ -84,10 +95,16 @@ CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SFC=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
@@ -96,4 +113,8 @@ CONFIG_USB_ETHER_LAN78XX=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350b
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index 74a9cc0a7d..c2641f65b5 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -71,11 +71,16 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -100,7 +105,6 @@ CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
@@ -108,6 +112,7 @@ CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_DWC3=y
 # CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index 3d6aeaa5ef..4e048b6ba1 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -30,6 +30,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_SYS_PBSIZE=1052
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
index f41c030679..4cd6b76665 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -21,15 +21,15 @@ CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
-CONFIG_LTO=y
 CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400000
@@ -39,7 +39,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index 6b7e308680..9456b9e1e1 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -27,6 +27,7 @@ CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SYS_LOAD_ADDR=0x22000000
 CONFIG_DEBUG_UART=y
+CONFIG_LTO=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SD_BOOT=y
@@ -41,6 +42,7 @@ CONFIG_SPL_MAX_SIZE=0x10000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index e33dcb8fb8..9ef0ff4aa9 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -28,6 +28,7 @@ CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SYS_LOAD_ADDR=0x22000000
 CONFIG_DEBUG_UART=y
+CONFIG_LTO=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SD_BOOT=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index acd75174f7..aed9edafdf 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -29,6 +29,7 @@ CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SYS_LOAD_ADDR=0x22000000
 CONFIG_DEBUG_UART=y
+CONFIG_LTO=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SD_BOOT=y
diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig
index 6346e5315b..c9a20723f5 100644
--- a/configs/sama5d2_xplained_qspiflash_defconfig
+++ b/configs/sama5d2_xplained_qspiflash_defconfig
@@ -29,6 +29,7 @@ CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SYS_LOAD_ADDR=0x22000000
 CONFIG_DEBUG_UART=y
+CONFIG_LTO=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_QSPI_BOOT=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index 76fa56ebeb..c01a0c4cc7 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -31,6 +31,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x22000000
 CONFIG_DEBUG_UART=y
+CONFIG_LTO=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SPI_BOOT=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 98b3e0cda4..69e5efe874 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -51,6 +51,7 @@ CONFIG_CMD_GPT_RENAME=y
 CONFIG_CMD_IDE=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_LOADM=y
+CONFIG_CMD_MBR=y
 CONFIG_CMD_OSD=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_READ=y
@@ -134,7 +135,6 @@ CONFIG_DM_DEMO_SHAPE=y
 CONFIG_DFU_SF=y
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FWU_MDATA_GPT_BLK=y
 CONFIG_GPIO_HOG=y
 CONFIG_DM_GPIO_LOOKUP_LABEL=y
 CONFIG_QCOM_PMIC_GPIO=y
@@ -260,3 +260,4 @@ CONFIG_FWU_MULTI_BANK_UPDATE=y
 CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
+CONFIG_ARM_FFA_TRANSPORT=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 1ec44d5b33..1cd1c2ed7c 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -30,6 +30,7 @@ CONFIG_AUTOBOOT_STOP_STR_ENABLE=y
 CONFIG_AUTOBOOT_STOP_STR_CRYPT="$5$rounds=640000$HrpE65IkB8CM5nCL$BKT3QdF98Bo8fJpTr9tjZLZQyzqPASBY20xuK5Rent9"
 CONFIG_IMAGE_PRE_LOAD=y
 CONFIG_IMAGE_PRE_LOAD_SIG=y
+CONFIG_CEDIT=y
 CONFIG_CONSOLE_RECORD=y
 CONFIG_CONSOLE_RECORD_OUT_SIZE=0x6000
 CONFIG_PRE_CONSOLE_BUFFER=y
@@ -64,7 +65,6 @@ CONFIG_CMD_MEM_SEARCH=y
 CONFIG_CMD_MX_CYCLIC=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_UNZIP=y
-CONFIG_CMD_BIND=y
 CONFIG_CMD_DEMO=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPIO_READ=y
@@ -75,6 +75,7 @@ CONFIG_CMD_IDE=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_LOADM=y
 CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MUX=y
 CONFIG_CMD_OSD=y
@@ -344,3 +345,4 @@ CONFIG_TEST_FDTDEC=y
 CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
+CONFIG_ARM_FFA_TRANSPORT=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index e7657d40dc..8aa295686d 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -44,6 +44,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_IDE=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MBR=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_OSD=y
 CONFIG_CMD_PCI=y
diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig
index fc20317ac8..2c6aab6c85 100644
--- a/configs/sandbox_noinst_defconfig
+++ b/configs/sandbox_noinst_defconfig
@@ -59,6 +59,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_IDE=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MBR=y
 CONFIG_CMD_OSD=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_REMOTEPROC=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index dd848c57c6..8d50162b27 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -60,6 +60,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_IDE=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MBR=y
 CONFIG_CMD_OSD=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_REMOTEPROC=y
diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig
index 27971c018a..f3a0fd19a9 100644
--- a/configs/sandbox_vpl_defconfig
+++ b/configs/sandbox_vpl_defconfig
@@ -75,6 +75,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_IDE=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MBR=y
 CONFIG_CMD_OSD=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_REMOTEPROC=y
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 00cca91171..f8759f2554 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -31,7 +31,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig
index 93031c750e..9dec10ef39 100644
--- a/configs/seeed_npi_imx6ull_defconfig
+++ b/configs/seeed_npi_imx6ull_defconfig
@@ -24,8 +24,6 @@ CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_DMA=y
 CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
@@ -75,4 +73,6 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig
index 044e1060a5..a591b2741d 100644
--- a/configs/sheep-rk3368_defconfig
+++ b/configs/sheep-rk3368_defconfig
@@ -28,7 +28,6 @@ CONFIG_PINCTRL=y
 CONFIG_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index ffae8655c9..867611b6b4 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -31,6 +31,7 @@ CONFIG_DISPLAY_CPUINFO=y
 CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_ID_EEPROM=y
+CONFIG_PCI_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x100000
 CONFIG_SPL_BSS_START_ADDR=0x85000000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index cc0ecad11b..2f466d23a5 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -27,7 +27,6 @@ CONFIG_SYS_PBSIZE=1024
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 # CONFIG_CMD_SLEEP is not set
 CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 3d43c9b996..7f1b2bee8e 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -21,8 +21,6 @@ CONFIG_FIT_VERBOSE=y
 # CONFIG_BOOTSTD is not set
 CONFIG_AUTOBOOT_MENU_SHOW=y
 CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if test \"${bootcount}\" -gt \"${bootlimit}\"; then run altbootcmd; else if test \"${ustate}\" = 1; then setenv upgrade_available 1; saveenv; fi; run mmcboot; fi;"
 CONFIG_USE_PREBOOT=y
 CONFIG_PREBOOT="run setup_boot_menu;"
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index f6b59a6e9b..c762d75aec 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -32,7 +32,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_I2C_LEGACY=y
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
index 0785157544..ba0dbb8496 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -39,7 +39,6 @@ CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
 CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
-CONFIG_SPL_CRC32=y
 CONFIG_SPL_CACHE=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
@@ -92,3 +91,4 @@ CONFIG_DESIGNWARE_WATCHDOG=y
 CONFIG_WDT=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_PANIC_HANG=y
+CONFIG_SPL_CRC32=y
diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig
index 037597f95c..7c83ec971a 100644
--- a/configs/socfpga_agilex_vab_defconfig
+++ b/configs/socfpga_agilex_vab_defconfig
@@ -40,7 +40,6 @@ CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
 CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
-CONFIG_SPL_CRC32=y
 CONFIG_SPL_CACHE=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
@@ -93,3 +92,4 @@ CONFIG_DESIGNWARE_WATCHDOG=y
 CONFIG_WDT=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_PANIC_HANG=y
+CONFIG_SPL_CRC32=y
diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig
index f308239b3f..78595c5d9e 100644
--- a/configs/socfpga_n5x_atf_defconfig
+++ b/configs/socfpga_n5x_atf_defconfig
@@ -38,7 +38,6 @@ CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
 CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
-CONFIG_SPL_CRC32=y
 CONFIG_SPL_CACHE=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
@@ -91,3 +90,4 @@ CONFIG_DESIGNWARE_WATCHDOG=y
 CONFIG_WDT=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_PANIC_HANG=y
+CONFIG_SPL_CRC32=y
diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig
index e82f6cd8ae..e8c62d0575 100644
--- a/configs/socfpga_n5x_vab_defconfig
+++ b/configs/socfpga_n5x_vab_defconfig
@@ -39,7 +39,6 @@ CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
 CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
-CONFIG_SPL_CRC32=y
 CONFIG_SPL_CACHE=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
@@ -92,3 +91,4 @@ CONFIG_DESIGNWARE_WATCHDOG=y
 CONFIG_WDT=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_PANIC_HANG=y
+CONFIG_SPL_CRC32=y
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
index e3e8a6345b..2d4f70592d 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -39,7 +39,6 @@ CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
 CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
-CONFIG_SPL_CRC32=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
 CONFIG_SPL_ATF=y
@@ -93,3 +92,4 @@ CONFIG_DESIGNWARE_WATCHDOG=y
 CONFIG_WDT=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_PANIC_HANG=y
+CONFIG_SPL_CRC32=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index 6b67021064..33092c7461 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -57,7 +57,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
@@ -68,7 +67,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=fe000000.nor_flash,nand0=socrates_nand"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe000000.nor_flash:13312k(system1),13312k(system2),5120k(data),128k(env),128k(env-red),768k(u-boot);socrates_nand:256M(ubi-data1),-(ubi-data2)"
 # CONFIG_CMD_IRQ is not set
 CONFIG_OF_CONTROL=y
-CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR_REDUND=0xFFF00000
diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig
index ad95274879..4a149133db 100644
--- a/configs/som-db5800-som-6867_defconfig
+++ b/configs/som-db5800-som-6867_defconfig
@@ -38,7 +38,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig
new file mode 100644
index 0000000000..181c284e73
--- /dev/null
+++ b/configs/soquartz-blade-rk3566_defconfig
@@ -0,0 +1,90 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_QUARTZ64_RK3566=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-blade.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SPL_CLK=y
+CONFIG_GPIO_HOG=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig
new file mode 100644
index 0000000000..7e29035147
--- /dev/null
+++ b/configs/soquartz-cm4-rk3566_defconfig
@@ -0,0 +1,90 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-cm4"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_QUARTZ64_RK3566=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-cm4.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SPL_CLK=y
+CONFIG_GPIO_HOG=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig
new file mode 100644
index 0000000000..c3958579db
--- /dev/null
+++ b/configs/soquartz-model-a-rk3566_defconfig
@@ -0,0 +1,90 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-model-a"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_QUARTZ64_RK3566=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-model-a.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SPL_CLK=y
+CONFIG_GPIO_HOG=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index ffbc4b9476..e9b63e5b84 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -6,23 +6,36 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000
 CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_ENV_SUPPORT=y
+CONFIG_SAVEENV=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE_AUTO=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xf0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
 CONFIG_SPL_TEXT_BASE=0x8000000
-CONFIG_SYS_PROMPT="StarFive #"
+CONFIG_SYS_PROMPT="StarFive # "
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
+CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x8180000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_SYS_PCI_64BIT=y
+CONFIG_PCI=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000
 CONFIG_ARCH_RV64I=y
 CONFIG_CMODEL_MEDANY=y
 CONFIG_RISCV_SMODE=y
+# CONFIG_OF_BOARD_FIXUP is not set
 CONFIG_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_QSPI_BOOT=y
@@ -31,9 +44,11 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
 CONFIG_USE_PREBOOT=y
 CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
-CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=5
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x0
 CONFIG_SPL_BSS_START_ADDR=0x8040000
@@ -45,19 +60,36 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000
 CONFIG_SYS_SPL_MALLOC_SIZE=0x400000
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_I2C=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_SIZE=512
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_OF_BOARD=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_JH7110=y
-# CONFIG_I2C is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0X50
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_SPL_MMC_HS400_SUPPORT=y
 CONFIG_MMC_DW=y
@@ -66,6 +98,18 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_STARFIVE=y
+CONFIG_RGMII=y
+CONFIG_RMII=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_STARFIVE_JH7110=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
@@ -77,3 +121,7 @@ CONFIG_PINCTRL_STARFIVE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER_EARLY=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_KEYBOARD=y
diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig
index b076573c45..82b62744f6 100644
--- a/configs/stm32mp13_defconfig
+++ b/configs/stm32mp13_defconfig
@@ -7,7 +7,7 @@ CONFIG_ENV_OFFSET=0x900000
 CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dk"
 CONFIG_SYS_PROMPT="STM32MP> "
 CONFIG_STM32MP13x=y
-CONFIG_DDR_CACHEABLE_SIZE=0x10000000
+CONFIG_DDR_CACHEABLE_SIZE=0x8000000
 CONFIG_CMD_STM32KEY=y
 CONFIG_TARGET_ST_STM32MP13x=y
 CONFIG_ENV_OFFSET_REDUND=0x940000
@@ -39,7 +39,6 @@ CONFIG_CMD_RNG=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_LOG=y
 CONFIG_CMD_UBI=y
 CONFIG_OF_LIVE=y
@@ -59,7 +58,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_STM32_SDMMC2=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-CONFIG_SYS_MTDPARTS_RUNTIME=y
 CONFIG_PINCONF=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
@@ -75,7 +73,6 @@ CONFIG_TEE=y
 CONFIG_OPTEE=y
 # CONFIG_OPTEE_TA_AVB is not set
 CONFIG_ERRNO_STR=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
 # CONFIG_LMB_USE_MAX_REGIONS is not set
 CONFIG_LMB_MEMORY_REGIONS=2
 CONFIG_LMB_RESERVED_REGIONS=16
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index 13355ebb46..9ea5aaa714 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -75,7 +75,6 @@ CONFIG_CMD_TIMER=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_LOG=y
 CONFIG_CMD_UBI=y
 # CONFIG_SPL_DOS_PARTITION is not set
@@ -102,7 +101,6 @@ CONFIG_SET_DFU_ALT_INFO=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
 CONFIG_FASTBOOT_BUF_SIZE=0x02000000
-CONFIG_FASTBOOT_USB_DEV=1
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
@@ -110,7 +108,6 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0"
 CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1"
 CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
 CONFIG_FASTBOOT_MMC_USER_NAME="mmc1"
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
 CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
 CONFIG_GPIO_HOG=y
@@ -125,7 +122,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_STM32_SDMMC2=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-CONFIG_SYS_MTDPARTS_RUNTIME=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_STM32_FMC2=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
@@ -175,6 +171,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483
 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
 CONFIG_BACKLIGHT_GPIO=y
 CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
 CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
@@ -182,6 +179,8 @@ CONFIG_VIDEO_STM32=y
 CONFIG_VIDEO_STM32_DSI=y
 CONFIG_VIDEO_STM32_MAX_XRES=1280
 CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
@@ -189,7 +188,6 @@ CONFIG_WDT=y
 CONFIG_WDT_STM32MP=y
 # CONFIG_BINMAN_FDT is not set
 CONFIG_ERRNO_STR=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
 # CONFIG_LMB_USE_MAX_REGIONS is not set
 CONFIG_LMB_MEMORY_REGIONS=2
 CONFIG_LMB_RESERVED_REGIONS=16
diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig
index 2669aae0f2..4d0a81f8a8 100644
--- a/configs/stm32mp15_defconfig
+++ b/configs/stm32mp15_defconfig
@@ -3,15 +3,15 @@ CONFIG_ARCH_STM32MP=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_MALLOC_F_LEN=0x80000
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
-CONFIG_ENV_OFFSET=0x480000
+CONFIG_ENV_OFFSET=0x900000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
 CONFIG_SYS_PROMPT="STM32MP> "
-CONFIG_DDR_CACHEABLE_SIZE=0x10000000
+CONFIG_DDR_CACHEABLE_SIZE=0x8000000
 CONFIG_CMD_STM32KEY=y
 CONFIG_TYPEC_STUSB160X=y
 CONFIG_TARGET_ST_STM32MP15x=y
-CONFIG_ENV_OFFSET_REDUND=0x4C0000
+CONFIG_ENV_OFFSET_REDUND=0x940000
 CONFIG_CMD_STM32PROG=y
 # CONFIG_ARMV7_NONSEC is not set
 CONFIG_SYS_LOAD_ADDR=0xc2000000
@@ -51,7 +51,6 @@ CONFIG_CMD_TIMER=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_LOG=y
 CONFIG_CMD_UBI=y
 CONFIG_OF_LIVE=y
@@ -75,7 +74,6 @@ CONFIG_SET_DFU_ALT_INFO=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
 CONFIG_FASTBOOT_BUF_SIZE=0x02000000
-CONFIG_FASTBOOT_USB_DEV=1
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
@@ -83,7 +81,6 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0"
 CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1"
 CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
 CONFIG_FASTBOOT_MMC_USER_NAME="mmc1"
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
 CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
 CONFIG_GPIO_HOG=y
@@ -98,7 +95,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_STM32_SDMMC2=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-CONFIG_SYS_MTDPARTS_RUNTIME=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_STM32_FMC2=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
@@ -151,6 +147,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483
 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
 CONFIG_BACKLIGHT_GPIO=y
 CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
 CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
@@ -158,6 +155,8 @@ CONFIG_VIDEO_STM32=y
 CONFIG_VIDEO_STM32_DSI=y
 CONFIG_VIDEO_STM32_MAX_XRES=1280
 CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
@@ -165,7 +164,6 @@ CONFIG_WDT=y
 CONFIG_WDT_STM32MP=y
 # CONFIG_BINMAN_FDT is not set
 CONFIG_ERRNO_STR=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
 # CONFIG_LMB_USE_MAX_REGIONS is not set
 CONFIG_LMB_MEMORY_REGIONS=2
 CONFIG_LMB_RESERVED_REGIONS=16
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index 93494f83a8..af7416659c 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -55,8 +55,6 @@ CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_FLASH_MTD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_TARGET="u-boot.itb"
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x2000000
@@ -87,9 +85,6 @@ CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_BTRFS=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=nor0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k(env1),64k(env2)"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
@@ -166,14 +161,15 @@ CONFIG_USB_DWC2=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="dh"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0483
 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
 CONFIG_WDT=y
 CONFIG_WDT_STM32MP=y
 CONFIG_FAT_WRITE=y
 # CONFIG_BINMAN_FDT is not set
-CONFIG_FDT_FIXUP_PARTITIONS=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index b54ff93014..b7f372f9e4 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -53,8 +53,6 @@ CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_FLASH_MTD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
 CONFIG_SPL_TARGET="u-boot.itb"
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x2000000
@@ -85,13 +83,11 @@ CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_BTRFS=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=nor0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k(env1),64k(env2)"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_OF_LIVE=y
+CONFIG_OF_LIST="stm32mp15xx-dhcor-avenger96 stm32mp15xx-dhcor-testbench stm32mp15xx-dhcor-drc-compact"
 CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
@@ -165,14 +161,15 @@ CONFIG_USB_DWC2=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="dh"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0483
 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
 CONFIG_WDT=y
 CONFIG_WDT_STM32MP=y
 CONFIG_FAT_WRITE=y
 # CONFIG_BINMAN_FDT is not set
-CONFIG_FDT_FIXUP_PARTITIONS=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 5f0fb45651..0a7d862485 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -52,7 +52,6 @@ CONFIG_CMD_TIMER=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_LOG=y
 CONFIG_CMD_UBI=y
 CONFIG_OF_LIVE=y
@@ -76,7 +75,6 @@ CONFIG_SET_DFU_ALT_INFO=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
 CONFIG_FASTBOOT_BUF_SIZE=0x02000000
-CONFIG_FASTBOOT_USB_DEV=1
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
@@ -84,7 +82,6 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0"
 CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1"
 CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
 CONFIG_FASTBOOT_MMC_USER_NAME="mmc1"
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
 CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
 CONFIG_GPIO_HOG=y
@@ -99,7 +96,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_STM32_SDMMC2=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-CONFIG_SYS_MTDPARTS_RUNTIME=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_STM32_FMC2=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
@@ -151,6 +147,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483
 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
 CONFIG_BACKLIGHT_GPIO=y
 CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
 CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
@@ -158,6 +155,8 @@ CONFIG_VIDEO_STM32=y
 CONFIG_VIDEO_STM32_DSI=y
 CONFIG_VIDEO_STM32_MAX_XRES=1280
 CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
@@ -165,7 +164,6 @@ CONFIG_WDT=y
 CONFIG_WDT_STM32MP=y
 # CONFIG_BINMAN_FDT is not set
 CONFIG_ERRNO_STR=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
 # CONFIG_LMB_USE_MAX_REGIONS is not set
 CONFIG_LMB_MEMORY_REGIONS=2
 CONFIG_LMB_RESERVED_REGIONS=16
diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig
index 68f7bacf02..b0b6868b22 100644
--- a/configs/synquacer_developerbox_defconfig
+++ b/configs/synquacer_developerbox_defconfig
@@ -1,23 +1,23 @@
 CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
 CONFIG_ARCH_SYNQUACER=y
-CONFIG_TEXT_BASE=0x08200000
 CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xe0000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_SF_DEFAULT_SPEED=31250000
 CONFIG_ENV_SIZE=0x30000
-CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_OFFSET=0x580000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox"
 CONFIG_SYS_LOAD_ADDR=0x80000000
 CONFIG_TARGET_DEVELOPERBOX=y
+CONFIG_FWU_NUM_IMAGES_PER_BANK=1
 CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE_STASH_SIZE=4096
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=128
+CONFIG_CMD_FWU_METADATA=y
 CONFIG_SYS_BOOTM_LEN=0x800000
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_ERASEENV=y
@@ -44,7 +44,6 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_LOG=y
 CONFIG_ISO_PARTITION=y
-CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_PROT_UDP=y
@@ -54,6 +53,7 @@ CONFIG_DFU_TFTP=y
 CONFIG_DFU_MTD=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
+CONFIG_FWU_MDATA_MTD=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_SYNQUACER=y
 CONFIG_MMC_SDHCI=y
@@ -97,3 +97,4 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
 CONFIG_EFI_IGNORE_OSINDICATIONS=y
 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_FWU_MULTI_BANK_UPDATE=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 2a85c0d190..81a83771cd 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -53,7 +53,6 @@ CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20ba0000
 CONFIG_SYS_SPL_MALLOC_SIZE=0x460000
-CONFIG_SPL_CRC32=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_NAND_RAW_ONLY=y
 CONFIG_SPL_NAND_DRIVERS=y
@@ -119,4 +118,5 @@ CONFIG_USB_GADGET_AT91=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_WDT=y
 CONFIG_WDT_AT91=y
+CONFIG_SPL_CRC32=y
 CONFIG_HEXDUMP=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 442cee33a9..4776e92683 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -34,7 +34,6 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 461c46c725..8a5d959a5c 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -31,7 +31,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/ten64_tfa_defconfig b/configs/ten64_tfa_defconfig
index 9797a343e5..24282a6a9c 100644
--- a/configs/ten64_tfa_defconfig
+++ b/configs/ten64_tfa_defconfig
@@ -17,12 +17,14 @@ CONFIG_AHCI=y
 CONFIG_SYS_FSL_NUM_CC_PLLS=3
 CONFIG_MP=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTSTD_BOOTCOMMAND=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_LOGLEVEL=7
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -75,7 +77,7 @@ CONFIG_PHY_VITESSE=y
 CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
@@ -94,6 +96,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
 CONFIG_WDT=y
 CONFIG_WDT_SP805=y
 CONFIG_TPM=y
diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
new file mode 100644
index 0000000000..710ec6abf5
--- /dev/null
+++ b/configs/th1520_lpi4a_defconfig
@@ -0,0 +1,82 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
+CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a"
+CONFIG_SYS_PROMPT="LPI4A=> "
+CONFIG_SYS_LOAD_ADDR=0x80200000
+# CONFIG_SMP is not set
+CONFIG_TARGET_TH1520_LPI4A=y
+CONFIG_ARCH_RV64I=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_SYS_BOOT_GET_CMDLINE=y
+CONFIG_SYS_BOOT_GET_KBD=y
+CONFIG_FIT=y
+# CONFIG_FIT_FULL_CHECK is not set
+# CONFIG_FIT_PRINT is not set
+# CONFIG_BOOTSTD is not set
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTARGS_SUBST=y
+CONFIG_BOOTCOMMAND=""
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-lichee-pi-4a.dtb"
+CONFIG_LOG=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
+CONFIG_CMD_CONFIG=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_MEMORY is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNLZ4 is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_SLEEP is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_NET is not set
+# CONFIG_BLOCK_CACHE is not set
+# CONFIG_GPIO is not set
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+# CONFIG_DM_MMC is not set
+# CONFIG_MTD is not set
+# CONFIG_POWER is not set
+CONFIG_SYS_NS16550=y
+CONFIG_RISCV_TIMER=y
+CONFIG_AES=y
+CONFIG_BLAKE2=y
+CONFIG_SHA512=y
+CONFIG_LZ4=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
+CONFIG_ZLIB_UNCOMPRESS=y
+CONFIG_BZIP2=y
+CONFIG_ZSTD=y
+CONFIG_LIB_RATIONAL=y
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LMB_USE_MAX_REGIONS is not set
diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
index 43dab09316..69499e17f4 100644
--- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
@@ -38,7 +38,6 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_TIME=y
diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig
index 5aec52733e..e2e64b7434 100644
--- a/configs/theadorable-x86-conga-qa3-e3845_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig
@@ -37,7 +37,6 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_TIME=y
diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig
index d5a28a2df4..751ae3497e 100644
--- a/configs/theadorable-x86-dfi-bt700_defconfig
+++ b/configs/theadorable-x86-dfi-bt700_defconfig
@@ -35,7 +35,6 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_TIME=y
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
deleted file mode 100644
index a4bc993297..0000000000
--- a/configs/ti816x_evm_defconfig
+++ /dev/null
@@ -1,82 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4031ff00
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x1C0000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="dm8168-evm"
-CONFIG_SPL_TEXT_BASE=0x40400000
-CONFIG_TI816X=y
-CONFIG_TARGET_TI816X_EVM=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x1E0000
-CONFIG_SYS_CLK_FREQ=27000000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyO2,115200n8 noinitrd earlyprintk"
-CONFIG_BOOTCOMMAND="mmc rescan;fatload mmc 0 ${loadaddr} uImage;bootm ${loadaddr}"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_SPL_MAX_SIZE=0xfff1b400
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_NAND_DRIVERS=y
-CONFIG_SPL_NAND_ECC=y
-CONFIG_SPL_NAND_BASE=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_BOOTP_DNS2=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RETRY_COUNT=10
-CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
-CONFIG_SYS_NAND_PAGE_SIZE=0x800
-CONFIG_SYS_NAND_OOBSIZE=0x40
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
-CONFIG_MII=y
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-# CONFIG_USE_PRIVATE_LIBGCC is not set
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index 2bc3bd9e91..3f588ea69b 100644
--- a/configs/tools-only_defconfig
+++ b/configs/tools-only_defconfig
@@ -10,6 +10,7 @@ CONFIG_FIT=y
 CONFIG_TIMESTAMP=y
 CONFIG_FIT_SIGNATURE=y
 # CONFIG_BOOTSTD_FULL is not set
+# CONFIG_BOOTMETH_CROS is not set
 # CONFIG_BOOTMETH_VBE is not set
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run distro_bootcmd"
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index d94a0b408b..9ec08bda88 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -35,7 +35,6 @@ CONFIG_CMD_PCI=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig
index 698a41d6eb..1cfa3421fd 100644
--- a/configs/variscite_dart6ul_defconfig
+++ b/configs/variscite_dart6ul_defconfig
@@ -20,7 +20,6 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=3
 CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
 CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
@@ -59,6 +58,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Variscite"
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index fd538da3ac..ebd1754fc8 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -36,7 +36,6 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index 5e2ff877ca..2da8ba94d6 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -29,7 +29,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig
new file mode 100644
index 0000000000..889b7e9936
--- /dev/null
+++ b/configs/verdin-am62_a53_defconfig
@@ -0,0 +1,185 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM625=y
+CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
+CONFIG_TARGET_VERDIN_AM62_A53=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-verdin-wifi-dev"
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_SYS_PROMPT="Verdin AM62 # "
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x88200000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile k3-am625-verdin-${variant}-${fdt_board}.dtb"
+CONFIG_LOG=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x58000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80c80000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x40000000
+CONFIG_CMD_ADTIMG=y
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_BCB=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth0"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_GPIO_HOG=y
+CONFIG_SPL_GPIO_HOG=y
+CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_ETHERNET_ID=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65219=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_TPS65219=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_HEXDUMP=y
diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig
new file mode 100644
index 0000000000..878195a61a
--- /dev/null
+++ b/configs/verdin-am62_r5_defconfig
@@ -0,0 +1,111 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_LEN=0x08000000
+CONFIG_SYS_MALLOC_F_LEN=0x9000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_VERDIN_AM62_R5=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-verdin-r5"
+CONFIG_SPL_TEXT_BASE=0x43c00000
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000
+CONFIG_SPL_SIZE_LIMIT=0x3A7F0
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0x3B000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x43c3b000
+CONFIG_SPL_BSS_MAX_SIZE=0x3000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_SPL_MISC=y
+CONFIG_ESM_K3=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index 0eb1891515..09e14c6f8c 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -98,6 +98,7 @@ CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_IMX8MM=y
 CONFIG_CLK_IMX8MM=y
 CONFIG_GPIO_HOG=y
+CONFIG_SPL_GPIO_HOG=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig
index f1fa2b8f49..2df0f4f344 100644
--- a/configs/verdin-imx8mp_defconfig
+++ b/configs/verdin-imx8mp_defconfig
@@ -42,6 +42,7 @@ CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx8mp-verdin-${variant}-${
 CONFIG_LOG=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_MAX_SIZE=0x26000
@@ -108,6 +109,7 @@ CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_IMX8MP=y
 CONFIG_FSL_CAAM=y
 CONFIG_GPIO_HOG=y
+CONFIG_SPL_GPIO_HOG=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index 4ee64c332b..5cacecc7cb 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -30,7 +30,6 @@ CONFIG_CMD_MMC=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_BOOTFILESIZE=y
-# CONFIG_CMD_NFS is not set
 # CONFIG_CMD_SLEEP is not set
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/videostrong-kii-pro_defconfig b/configs/videostrong-kii-pro_defconfig
new file mode 100644
index 0000000000..4a2ff34385
--- /dev/null
+++ b/configs/videostrong-kii-pro_defconfig
@@ -0,0 +1,67 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-kii-pro"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" kii-pro"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_PHY=y
+CONFIG_MESON_GXBB_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index 2aa272f02d..cbb82593d0 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -37,9 +37,6 @@ CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
 CONFIG_SPL_I2C=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
@@ -96,13 +93,16 @@ CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_USB_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Softing"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/x240_defconfig b/configs/x240_defconfig
new file mode 100644
index 0000000000..7d2b8603e6
--- /dev/null
+++ b/configs/x240_defconfig
@@ -0,0 +1,86 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_TEXT_BASE=0x200000000
+CONFIG_SYS_MALLOC_LEN=0x900000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
+CONFIG_TARGET_X240=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x00f80000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="ac5-98dx35xx-atl-x240"
+CONFIG_SYS_LOAD_ADDR=0x220000000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_MVEBU=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_PXA3XX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MAX313XX=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_MVEBU_A3700_SPI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+# CONFIG_FAT_WRITE is not set
diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig
index 122c1a99e3..318951e19c 100644
--- a/configs/x96_mate_defconfig
+++ b/configs/x96_mate_defconfig
@@ -10,6 +10,7 @@ CONFIG_DRAM_SUN50I_H616_TPR10=0x2f0007
 CONFIG_DRAM_SUN50I_H616_TPR11=0xffffdddd
 CONFIG_DRAM_SUN50I_H616_TPR12=0xfedf7557
 CONFIG_MACH_SUN50I_H616=y
+CONFIG_SUNXI_DRAM_H616_DDR3_1333=y
 CONFIG_R_I2C_ENABLE=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
@@ -18,3 +19,5 @@ CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig
new file mode 100644
index 0000000000..6d5affcd52
--- /dev/null
+++ b/configs/xilinx_versal_net_mini_emmc_defconfig
@@ -0,0 +1,63 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_versal_net_mini"
+CONFIG_COUNTER_FREQUENCY=100000000
+CONFIG_ARCH_VERSAL_NET=y
+CONFIG_TEXT_BASE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x80000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000
+CONFIG_ENV_SIZE=0x80
+CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-emmc"
+CONFIG_SYS_PROMPT="Versal NET> "
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
+# CONFIG_EXPERT is not set
+CONFIG_REMAKE_ELF=y
+# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_BOARD_LATE_INIT is not set
+# CONFIG_CMDLINE_EDITING is not set
+# CONFIG_AUTO_COMPLETE is not set
+# CONFIG_SYS_LONGHELP is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ARM_DCC=y
+CONFIG_FAT_WRITE=y
+# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig
new file mode 100644
index 0000000000..d11e180780
--- /dev/null
+++ b/configs/xilinx_versal_net_mini_ospi_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_versal_net_mini"
+CONFIG_COUNTER_FREQUENCY=100000000
+CONFIG_ARCH_VERSAL_NET=y
+CONFIG_TEXT_BASE=0xBBF00000
+CONFIG_SYS_MALLOC_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x500
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000
+CONFIG_SF_DEFAULT_SPEED=30000000
+CONFIG_ENV_SIZE=0x80
+# CONFIG_DM_GPIO is not set
+CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-ospi-single"
+CONFIG_SYS_PROMPT="Versal NET> "
+CONFIG_SYS_MEM_RSVD_FOR_MMU=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0xBBF80000
+# CONFIG_EXPERT is not set
+CONFIG_REMAKE_ELF=y
+# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_BOARD_LATE_INIT is not set
+# CONFIG_CMDLINE_EDITING is not set
+# CONFIG_AUTO_COMPLETE is not set
+# CONFIG_SYS_LONGHELP is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_NET is not set
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_ARM_DCC=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=200000000
+CONFIG_CADENCE_OSPI_VERSAL=y
+# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig
new file mode 100644
index 0000000000..a7ebc38cda
--- /dev/null
+++ b/configs/xilinx_versal_net_mini_qspi_defconfig
@@ -0,0 +1,75 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_versal_net_mini"
+CONFIG_COUNTER_FREQUENCY=100000000
+CONFIG_ARCH_VERSAL_NET=y
+CONFIG_TEXT_BASE=0xBBF00000
+CONFIG_SYS_MALLOC_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000
+CONFIG_SF_DEFAULT_SPEED=30000000
+CONFIG_ENV_SIZE=0x80
+CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-qspi-single"
+CONFIG_SYS_PROMPT="Versal NET> "
+CONFIG_SYS_MEM_RSVD_FOR_MMU=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0xBBF80000
+# CONFIG_EXPERT is not set
+CONFIG_REMAKE_ELF=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+# CONFIG_AUTOBOOT is not set
+CONFIG_LOGLEVEL=0
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_BOARD_LATE_INIT is not set
+# CONFIG_CMDLINE_EDITING is not set
+# CONFIG_AUTO_COMPLETE is not set
+# CONFIG_SYS_LONGHELP is not set
+# CONFIG_SYS_XTRACE is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
+# CONFIG_NET is not set
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_GPIO is not set
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+# CONFIG_POWER is not set
+CONFIG_ARM_DCC=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 474abc7f6b..9900577345 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -7,6 +7,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_OFFSET=0xE00000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL_STACK=0xfffffe00
 CONFIG_SPL=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index c4bbde2206..acab38fefe 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -63,7 +63,6 @@ CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
 CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_BIND=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_FPGA_LOADBP=y
diff --git a/disk/Kconfig b/disk/Kconfig
index 817b7c8c76..8549695807 100644
--- a/disk/Kconfig
+++ b/disk/Kconfig
@@ -51,7 +51,7 @@ config SPL_MAC_PARTITION
 
 config DOS_PARTITION
 	bool "Enable MS Dos partition table"
-	default y if DISTRO_DEFAULTS
+	default y if BOOT_DEFAULTS
 	default y if x86 || CMD_FAT || USB_STORAGE
 	select PARTITIONS
 	help
@@ -67,7 +67,7 @@ config SPL_DOS_PARTITION
 
 config ISO_PARTITION
 	bool "Enable ISO partition table"
-	default y if DISTRO_DEFAULTS
+	default y if BOOT_DEFAULTS
 	default y if MIPS || ARCH_TEGRA
 	select PARTITIONS
 
@@ -91,7 +91,7 @@ config SPL_AMIGA_PARTITION
 
 config EFI_PARTITION
 	bool "Enable EFI GPT partition table"
-	default y if DISTRO_DEFAULTS
+	default y if BOOT_DEFAULTS
 	default y if ARCH_TEGRA
 	select PARTITIONS
 	select LIB_UUID
@@ -139,7 +139,7 @@ config SPL_EFI_PARTITION
 config PARTITION_UUIDS
 	bool "Enable support of UUID for partition"
 	depends on PARTITIONS
-	default y if DISTRO_DEFAULTS
+	default y if BOOT_DEFAULTS
 	default y if EFI_PARTITION
 	select LIB_UUID
 	help
diff --git a/disk/part.c b/disk/part.c
index 35300df590..eec02f5898 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -26,6 +26,22 @@
 /* Check all partition types */
 #define PART_TYPE_ALL		-1
 
+static struct part_driver *part_driver_get_type(int part_type)
+{
+	struct part_driver *drv =
+		ll_entry_start(struct part_driver, part_driver);
+	const int n_ents = ll_entry_count(struct part_driver, part_driver);
+	struct part_driver *entry;
+
+	for (entry = drv; entry != drv + n_ents; entry++) {
+		if (part_type == entry->part_type)
+			return entry;
+	}
+
+	/* Not found */
+	return NULL;
+}
+
 static struct part_driver *part_driver_lookup_type(struct blk_desc *dev_desc)
 {
 	struct part_driver *drv =
@@ -44,16 +60,29 @@ static struct part_driver *part_driver_lookup_type(struct blk_desc *dev_desc)
 			}
 		}
 	} else {
-		for (entry = drv; entry != drv + n_ents; entry++) {
-			if (dev_desc->part_type == entry->part_type)
-				return entry;
-		}
+		return part_driver_get_type(dev_desc->part_type);
 	}
 
 	/* Not found */
 	return NULL;
 }
 
+int part_get_type_by_name(const char *name)
+{
+	struct part_driver *drv =
+		ll_entry_start(struct part_driver, part_driver);
+	const int n_ents = ll_entry_count(struct part_driver, part_driver);
+	struct part_driver *entry;
+
+	for (entry = drv; entry != drv + n_ents; entry++) {
+		if (!strcasecmp(name, entry->name))
+			return entry->part_type;
+	}
+
+	/* Not found */
+	return PART_TYPE_UNKNOWN;
+}
+
 static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
 {
 	struct blk_desc *dev_desc;
@@ -306,8 +335,8 @@ void part_print(struct blk_desc *dev_desc)
 		drv->print(dev_desc);
 }
 
-int part_get_info(struct blk_desc *dev_desc, int part,
-		       struct disk_partition *info)
+int part_get_info_by_type(struct blk_desc *dev_desc, int part, int part_type,
+			  struct disk_partition *info)
 {
 	struct part_driver *drv;
 
@@ -320,7 +349,12 @@ int part_get_info(struct blk_desc *dev_desc, int part,
 		info->type_guid[0] = 0;
 #endif
 
-		drv = part_driver_lookup_type(dev_desc);
+		if (part_type == PART_TYPE_UNKNOWN) {
+			drv = part_driver_lookup_type(dev_desc);
+		} else {
+			drv = part_driver_get_type(part_type);
+		}
+
 		if (!drv) {
 			debug("## Unknown partition table type %x\n",
 			      dev_desc->part_type);
@@ -340,6 +374,12 @@ int part_get_info(struct blk_desc *dev_desc, int part,
 	return -ENOENT;
 }
 
+int part_get_info(struct blk_desc *dev_desc, int part,
+		  struct disk_partition *info)
+{
+	return part_get_info_by_type(dev_desc, part, PART_TYPE_UNKNOWN, info);
+}
+
 int part_get_info_whole_disk(struct blk_desc *dev_desc,
 			     struct disk_partition *info)
 {
@@ -468,9 +508,11 @@ int blk_get_device_part_str(const char *ifname, const char *dev_part_str,
 #endif
 
 	/* If no dev_part_str, use bootdevice environment variable */
-	if (!dev_part_str || !strlen(dev_part_str) ||
-	    !strcmp(dev_part_str, "-"))
-		dev_part_str = env_get("bootdevice");
+	if (CONFIG_IS_ENABLED(ENV_SUPPORT)) {
+		if (!dev_part_str || !strlen(dev_part_str) ||
+		    !strcmp(dev_part_str, "-"))
+			dev_part_str = env_get("bootdevice");
+	}
 
 	/* If still no dev_part_str, it's an error */
 	if (!dev_part_str) {
@@ -630,8 +672,8 @@ cleanup:
 	return ret;
 }
 
-int part_get_info_by_name_type(struct blk_desc *dev_desc, const char *name,
-			       struct disk_partition *info, int part_type)
+int part_get_info_by_name(struct blk_desc *dev_desc, const char *name,
+			  struct disk_partition *info)
 {
 	struct part_driver *part_drv;
 	int ret;
@@ -662,12 +704,6 @@ int part_get_info_by_name_type(struct blk_desc *dev_desc, const char *name,
 	return -ENOENT;
 }
 
-int part_get_info_by_name(struct blk_desc *dev_desc, const char *name,
-			  struct disk_partition *info)
-{
-	return part_get_info_by_name_type(dev_desc, name, info, PART_TYPE_ALL);
-}
-
 /**
  * Get partition info from device number and partition name.
  *
diff --git a/doc/README.falcon b/doc/README.falcon
deleted file mode 100644
index 88218d35b9..0000000000
--- a/doc/README.falcon
+++ /dev/null
@@ -1,232 +0,0 @@
-U-Boot Falcon Mode
-====================
-
-Introduction
-------------
-
-This document provides an overview of how to add support for Falcon Mode
-to a board.
-
-Falcon Mode is introduced to speed up the booting process, allowing
-to boot a Linux kernel (or whatever image) without a full blown U-Boot.
-
-Falcon Mode relies on the SPL framework. In fact, to make booting faster,
-U-Boot is split into two parts: the SPL (Secondary Program Loader) and U-Boot
-image. In most implementations, SPL is used to start U-Boot when booting from
-a mass storage, such as NAND or SD-Card. SPL has now support for other media,
-and can generally be seen as a way to start an image performing the minimum
-required initialization. SPL mainly initializes the RAM controller, and then
-copies U-Boot image into the memory.
-
-The Falcon Mode extends this way allowing to start the Linux kernel directly
-from SPL. A new command is added to U-Boot to prepare the parameters that SPL
-must pass to the kernel, using ATAGS or Device Tree.
-
-In normal mode, these parameters are generated each time before
-loading the kernel, passing to Linux the address in memory where
-the parameters can be read.
-With Falcon Mode, this snapshot can be saved into persistent storage and SPL is
-informed to load it before running the kernel.
-
-To boot the kernel, these steps under a Falcon-aware U-Boot are required:
-
-1. Boot the board into U-Boot.
-After loading the desired legacy-format kernel image into memory (and DT as
-well, if used), use the "spl export" command to generate the kernel parameters
-area or the DT.  U-Boot runs as when it boots the kernel, but stops before
-passing the control to the kernel.
-
-2. Save the prepared snapshot into persistent media.
-The address where to save it must be configured into board configuration
-file (CONFIG_CMD_SPL_NAND_OFS for NAND).
-
-3. Boot the board into Falcon Mode. SPL will load the kernel and copy
-the parameters which are saved in the persistent area to the required address.
-If a valid uImage is not found at the defined location, U-Boot will be
-booted instead.
-
-It is required to implement a custom mechanism to select if SPL loads U-Boot
-or another image.
-
-The value of a GPIO is a simple way to operate the selection, as well as
-reading a character from the SPL console if CONFIG_SPL_CONSOLE is set.
-
-Falcon Mode is generally activated by setting CONFIG_SPL_OS_BOOT. This tells
-SPL that U-Boot is not the only available image that SPL is able to start.
-
-Configuration
-----------------------------
-CONFIG_CMD_SPL		Enable the "spl export" command.
-			The command "spl export" is then available in U-Boot
-			mode
-CONFIG_SYS_SPL_ARGS_ADDR	Address in RAM where the parameters must be
-				copied by SPL.
-				In most cases, it is <start_of_ram> + 0x100
-
-CONFIG_SYS_NAND_SPL_KERNEL_OFFS	Offset in NAND where the kernel is stored
-
-CONFIG_CMD_SPL_NAND_OFS	Offset in NAND where the parameters area was saved.
-
-CONFIG_CMD_SPL_NOR_OFS	Offset in NOR where the parameters area was saved.
-
-CONFIG_CMD_SPL_WRITE_SIZE	Size of the parameters area to be copied
-
-CONFIG_SPL_OS_BOOT	Activate Falcon Mode.
-
-Function that a board must implement
-------------------------------------
-
-void spl_board_prepare_for_linux(void) : optional
-	Called from SPL before starting the kernel
-
-spl_start_uboot() : required
-		Returns "0" if SPL should start the kernel, "1" if U-Boot
-		must be started.
-
-Environment variables
----------------------
-
-A board may chose to look at the environment for decisions about falcon
-mode.  In this case the following variables may be supported:
-
-boot_os :		Set to yes/Yes/true/True/1 to enable booting to OS,
-			any other value to fall back to U-Boot (including
-			unset)
-falcon_args_file :	Filename to load as the 'args' portion of falcon mode
-			rather than the hard-coded value.
-falcon_image_file :	Filename to load as the OS image portion of falcon
-			mode rather than the hard-coded value.
-
-Using spl command
------------------
-
-spl - SPL configuration
-
-Usage:
-
-spl export <img=atags|fdt> [kernel_addr] [initrd_addr] [fdt_addr ]
-
-img		: "atags" or "fdt"
-kernel_addr	: kernel is loaded as part of the boot process, but it is not started.
-		  This is the address where a kernel image is stored.
-initrd_addr	: Address of initial ramdisk
-		  can be set to "-" if fdt_addr without initrd_addr is used
-fdt_addr	: in case of fdt, the address of the device tree.
-
-The spl export command does not write to a storage media. The user is
-responsible to transfer the gathered information (assembled ATAGS list
-or prepared FDT) from temporary storage in RAM into persistant storage
-after each run of 'spl export'. Unfortunately the position of temporary
-storage can not be predicted nor provided at commandline, it depends
-highly on your system setup and your provided data (ATAGS or FDT).
-However at the end of an succesful 'spl export' run it will print the
-RAM address of temporary storage. The RAM address of FDT will also be
-set in the environment variable 'fdtargsaddr', the new length of the
-prepared FDT will be set in the environment variable 'fdtargslen'.
-These environment variables can be used in scripts for writing updated
-FDT to persistent storage.
-
-Now the user have to save the generated BLOB from that printed address
-to the pre-defined address in persistent storage
-(CONFIG_CMD_SPL_NAND_OFS in case of NAND).
-The following example shows how to prepare the data for Falcon Mode on
-twister board with ATAGS BLOB.
-
-The "spl export" command is prepared to work with ATAGS and FDT. However,
-using FDT is at the moment untested. The ppc port (see a3m071 example
-later) prepares the fdt blob with the fdt command instead.
-
-
-Usage on the twister board:
---------------------------------
-
-Using mtd names with the following (default) configuration
-for mtdparts:
-
-device nand0 <omap2-nand.0>, # parts = 9
- #: name		size		offset		mask_flags
- 0: MLO                 0x00080000      0x00000000      0
- 1: u-boot              0x00100000      0x00080000      0
- 2: env1                0x00040000      0x00180000      0
- 3: env2                0x00040000      0x001c0000      0
- 4: kernel              0x00600000      0x00200000      0
- 5: bootparms           0x00040000      0x00800000      0
- 6: splashimg           0x00200000      0x00840000      0
- 7: mini                0x02800000      0x00a40000      0
- 8: rootfs              0x1cdc0000      0x03240000      0
-
-
-twister => nand read 82000000 kernel
-
-NAND read: device 0 offset 0x200000, size 0x600000
- 6291456 bytes read: OK
-
-Now the kernel is in RAM at address 0x82000000
-
-twister => spl export atags 0x82000000
-## Booting kernel from Legacy Image at 82000000 ...
-   Image Name:   Linux-3.5.0-rc4-14089-gda0b7f4
-   Image Type:   ARM Linux Kernel Image (uncompressed)
-   Data Size:    3654808 Bytes = 3.5 MiB
-   Load Address: 80008000
-   Entry Point:  80008000
-   Verifying Checksum ... OK
-   Loading Kernel Image ... OK
-OK
-cmdline subcommand not supported
-bdt subcommand not supported
-Argument image is now in RAM at: 0x80000100
-
-The result can be checked at address 0x80000100:
-
-twister => md 0x80000100
-80000100: 00000005 54410001 00000000 00000000    ......AT........
-80000110: 00000000 00000067 54410009 746f6f72    ....g.....ATroot
-80000120: 65642f3d 666e2f76 77722073 73666e20    =/dev/nfs rw nfs
-
-The parameters generated with this step can be saved into NAND at the offset
-0x800000 (value for twister for CONFIG_CMD_SPL_NAND_OFS)
-
-nand erase.part bootparms
-nand write 0x80000100 bootparms 0x4000
-
-Now the parameters are stored into the NAND flash at the address
-CONFIG_CMD_SPL_NAND_OFS (=0x800000).
-
-Next time, the board can be started into Falcon Mode moving the
-setting the gpio (on twister gpio 55 is used) to kernel mode.
-
-The kernel is loaded directly by the SPL without passing through U-Boot.
-
-Example with FDT: a3m071 board
--------------------------------
-
-To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
-prepard/patched first. U-Boot usually inserts some dynamic values into
-the DT binary (blob), e.g. autodetected memory size, MAC addresses,
-clocks speeds etc. To generate this patched DT blob, you can use
-the following command:
-
-1. Load fdt blob to SDRAM:
-=> tftp 1800000 a3m071/a3m071.dtb
-
-2. Set bootargs as desired for Linux booting (e.g. flash_mtd):
-=> run mtdargs addip2 addtty
-
-3. Use "fdt" commands to patch the DT blob:
-=> fdt addr 1800000
-=> fdt boardsetup
-=> fdt chosen
-
-4. Display patched DT blob (optional):
-=> fdt print
-
-5. Save fdt to NOR flash:
-=> erase fc060000 fc07ffff
-=> cp.b 1800000 fc060000 10000
-...
-
-
-Falcon Mode was presented at the RMLL 2012. Slides are available at:
-
-http://schedule2012.rmll.info/IMG/pdf/LSM2012_UbootFalconMode_Babic.pdf
diff --git a/doc/README.pcap b/doc/README.pcap
index 8e30b93c66..10318ef0a9 100644
--- a/doc/README.pcap
+++ b/doc/README.pcap
@@ -1,6 +1,6 @@
 PCAP:
 
-U-boot supports live Ethernet packet capture in PCAP(2.4) format.
+U-Boot supports live Ethernet packet capture in PCAP(2.4) format.
 This is enabled by CONFIG_CMD_PCAP.
 
 The capture is stored on physical memory, and should be copied to
diff --git a/doc/README.rmobile b/doc/README.rmobile
index ea170a25a6..524d839558 100644
--- a/doc/README.rmobile
+++ b/doc/README.rmobile
@@ -35,6 +35,7 @@ Currently the following boards are supported:
 | R8A77965 M3-N | Renesas Electronics ULCB               | r8a77965_ulcb
 |---------------+----------------------------------------+-------------------
 | R8A77970 V3M  | Renesas Electronics Eagle              | r8a77970_eagle_defconfig
+| R8A77970 V3M  | Renesas Electronics V3MSK              | r8a77970_v3msk_defconfig
 |---------------+----------------------------------------+-------------------
 | R8A77995 D3   | Renesas Electronics Draak              | r8a77995_draak_defconfig
 '===============+========================================+===================
diff --git a/doc/README.s5p4418 b/doc/README.s5p4418
index ac724d08a0..8ec7b05fd2 100644
--- a/doc/README.s5p4418
+++ b/doc/README.s5p4418
@@ -38,7 +38,7 @@ The source code for (the used?) LUbuntu 16.04 can be found at [5].
 Links
 =====
 
-[1] FriendlyArm U-boot v2016.01:
+[1] FriendlyArm U-Boot v2016.01:
 
 https://github.com/friendlyarm/u-boot/tree/nanopi2-v2016.01
 
diff --git a/doc/SPL/README.spl-secure-boot b/doc/SPL/README.spl-secure-boot
index f2f8d78883..982fbec654 100644
--- a/doc/SPL/README.spl-secure-boot
+++ b/doc/SPL/README.spl-secure-boot
@@ -12,7 +12,7 @@ Methodology
 
 The SPL image is responsible for loading the next stage boot loader, which is
 the main u-boot image. For secure boot process on these platforms ROM verifies
-SPL image, so to continue chain of trust SPL image verifies U-boot image using
+SPL image, so to continue chain of trust SPL image verifies U-Boot image using
 spl_validate_uboot(). This function uses QorIQ Trust Architecture header
-(appended to U-boot image) to validate the U-boot binary just before passing
+(appended to U-Boot image) to validate the U-Boot binary just before passing
 control to it.
diff --git a/doc/android/ab.rst b/doc/android/ab.rst
index 961895c32e..2adf88781d 100644
--- a/doc/android/ab.rst
+++ b/doc/android/ab.rst
@@ -31,6 +31,12 @@ boot script. This command analyzes and processes A/B metadata stored on a
 special partition (e.g. ``misc``) and determines which slot should be used for
 booting up.
 
+If the A/B metadata partition has a backup bootloader_message block that is used
+to ensure one is always valid even in the event of interruption when writing, it
+can be enabled in your board configuration file::
+
+    CONFIG_ANDROID_AB_BACKUP_OFFSET=0x1000
+
 Command usage
 -------------
 
diff --git a/doc/api/index.rst b/doc/api/index.rst
index a9338cfef9..3a80ae0635 100644
--- a/doc/api/index.rst
+++ b/doc/api/index.rst
@@ -15,6 +15,7 @@ U-Boot API documentation
    lmb
    logging
    nvmem
+   part
    pinctrl
    rng
    sandbox
diff --git a/doc/api/part.rst b/doc/api/part.rst
new file mode 100644
index 0000000000..d1df1d8494
--- /dev/null
+++ b/doc/api/part.rst
@@ -0,0 +1,6 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Partition API
+=============
+
+.. kernel-doc:: include/part.h
diff --git a/doc/arch/arm64.ffa.rst b/doc/arch/arm64.ffa.rst
new file mode 100644
index 0000000000..4ecdc31716
--- /dev/null
+++ b/doc/arch/arm64.ffa.rst
@@ -0,0 +1,261 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Arm FF-A Support
+================
+
+Summary
+-------
+
+FF-A stands for Firmware Framework for Arm A-profile processors.
+
+FF-A specifies interfaces that enable a pair of software execution environments aka partitions to
+communicate with each other. A partition could be a VM in the Normal or Secure world, an
+application in S-EL0, or a Trusted OS in S-EL1.
+
+The U-Boot FF-A support (the bus) implements the interfaces to communicate
+with partitions in the Secure world aka Secure partitions (SPs).
+
+The FF-A support specifically focuses on communicating with SPs that
+isolate portions of EFI runtime services that must run in a protected
+environment which is inaccessible by the Host OS or Hypervisor.
+Examples of such services are set/get variables.
+
+The FF-A support uses the SMC ABIs defined by the FF-A specification to:
+
+- Discover the presence of SPs of interest
+- Access an SP's service through communication protocols
+  e.g. EFI MM communication protocol
+
+At this stage of development only EFI boot-time services are supported.
+Runtime support will be added in future developments.
+
+The U-Boot FF-A support provides the following parts:
+
+- A Uclass driver providing generic FF-A methods.
+- An Arm FF-A device driver providing Arm-specific methods and reusing the Uclass methods.
+- A sandbox emulator for Arm FF-A, emulates the FF-A side of the Secure World and provides
+  FF-A ABIs inspection methods.
+- An FF-A sandbox device driver for FF-A communication with the emulated Secure World.
+  The driver leverages the FF-A Uclass to establish FF-A communication.
+- Sandbox FF-A test cases.
+
+FF-A and SMC specifications
+-------------------------------------------
+
+The current implementation of the U-Boot FF-A support relies on
+`FF-A v1.0 specification`_ and uses SMC32 calling convention which
+means using the first 32-bit data of the Xn registers.
+
+At this stage we only need the FF-A v1.0 features.
+
+The FF-A support has been tested with OP-TEE which supports SMC32 calling
+convention.
+
+Hypervisors are supported if they are configured to trap SMC calls.
+
+The FF-A support uses 64-bit registers as per `SMC Calling Convention v1.2 specification`_.
+
+Supported hardware
+--------------------------------
+
+Aarch64 plaforms
+
+Configuration
+----------------------
+
+CONFIG_ARM_FFA_TRANSPORT
+    Enables the FF-A support. Turn this on if you want to use FF-A
+    communication.
+    When using an Arm 64-bit platform, the Arm FF-A driver will be used.
+    When using sandbox, the sandbox FF-A emulator and FF-A sandbox driver will be used.
+
+FF-A ABIs under the hood
+---------------------------------------
+
+Invoking an FF-A ABI involves providing to the secure world/hypervisor the
+expected arguments from the ABI.
+
+On an Arm 64-bit platform, the ABI arguments are stored in x0 to x7 registers.
+Then, an SMC instruction is executed.
+
+At the secure side level or hypervisor the ABI is handled at a higher exception
+level and the arguments are read and processed.
+
+The response is put back through x0 to x7 registers and control is given back
+to the U-Boot Arm FF-A driver (non-secure world).
+
+The driver reads the response and processes it accordingly.
+
+This methodology applies to all the FF-A ABIs.
+
+FF-A bus discovery on Arm 64-bit platforms
+---------------------------------------------
+
+When CONFIG_ARM_FFA_TRANSPORT is enabled, the FF-A bus is considered as
+an architecture feature and discovered using ARM_SMCCC_FEATURES mechanism.
+This discovery mechanism is performed by the PSCI driver.
+
+The PSCI driver comes with a PSCI device tree node which is the root node for all
+architecture features including FF-A bus.
+
+::
+
+   => dm tree
+
+    Class     Index  Probed  Driver                Name
+   -----------------------------------------------------------
+    firmware      0  [ + ]   psci                      |-- psci
+    ffa                   0  [   ]   arm_ffa               |   `-- arm_ffa
+
+The PSCI driver is bound to the PSCI device and when probed it tries to discover
+the architecture features by calling a callback the features drivers provide.
+
+In case of FF-A, the callback is arm_ffa_is_supported() which tries to discover the
+FF-A framework by querying the FF-A framework version from secure world using
+FFA_VERSION ABI. When discovery is successful, the ARM_SMCCC_FEATURES
+mechanism creates a U-Boot device for the FF-A bus and binds the Arm FF-A driver
+with the device using device_bind_driver().
+
+At this stage the FF-A bus is registered with the DM and can be interacted with using
+the DM APIs.
+
+Clients are able to probe then use the FF-A bus by calling uclass_first_device().
+Please refer to the armffa command implementation as an example of how to probe
+and interact with the FF-A bus.
+
+When calling uclass_first_device(), the FF-A driver is probed and ends up calling
+ffa_do_probe() provided by the Uclass which does the following:
+
+    - saving the FF-A framework version in uc_priv
+    - querying from secure world the u-boot endpoint ID
+    - querying from secure world the supported features of FFA_RXTX_MAP
+    - mapping the RX/TX buffers
+    - querying from secure world all the partitions information
+
+When one of the above actions fails, probing fails and the driver stays not active
+and can be probed again if needed.
+
+Requirements for clients
+-------------------------------------
+
+When using the FF-A bus with EFI, clients must query the SPs they are looking for
+during EFI boot-time mode using the service UUID.
+
+The RX/TX buffers are only available at EFI boot-time. Querying partitions is
+done at boot time and data is cached for future use.
+
+RX/TX buffers should be unmapped before EFI runtime mode starts.
+The driver provides a bus operation for that called ffa_rxtx_unmap().
+
+The user should call ffa_rxtx_unmap() to unmap the RX/TX buffers when required
+(e.g: at efi_exit_boot_services()).
+
+The Linux kernel allocates its own RX/TX buffers. To be able to register these kernel buffers
+with secure world, the U-Boot's RX/TX buffers should be unmapped before EFI runtime starts.
+
+When invoking FF-A direct messaging, clients should specify which ABI protocol
+they want to use (32-bit vs 64-bit). Selecting the protocol means using
+the 32-bit or 64-bit version of FFA_MSG_SEND_DIRECT_{REQ, RESP}.
+The calling convention between U-Boot and the secure world stays the same: SMC32.
+
+Requirements for user drivers
+-------------------------------------
+
+Users who want to implement their custom FF-A device driver while reusing the FF-A Uclass can do so
+by implementing their own invoke_ffa_fn() in the user driver.
+
+The bus driver layer
+------------------------------
+
+FF-A support comes on top of the SMCCC layer and is implemented by the FF-A Uclass drivers/firmware/arm-ffa/arm-ffa-uclass.c
+
+The following features are provided:
+
+- Support for the 32-bit version of the following ABIs:
+
+    - FFA_VERSION
+    - FFA_ID_GET
+    - FFA_FEATURES
+    - FFA_PARTITION_INFO_GET
+    - FFA_RXTX_UNMAP
+    - FFA_RX_RELEASE
+    - FFA_RUN
+    - FFA_ERROR
+    - FFA_SUCCESS
+    - FFA_INTERRUPT
+    - FFA_MSG_SEND_DIRECT_REQ
+    - FFA_MSG_SEND_DIRECT_RESP
+
+- Support for the 64-bit version of the following ABIs:
+
+    - FFA_RXTX_MAP
+    - FFA_MSG_SEND_DIRECT_REQ
+    - FFA_MSG_SEND_DIRECT_RESP
+
+- Processing the received data from the secure world/hypervisor and caching it
+
+- Hiding from upper layers the FF-A protocol and registers details. Upper
+  layers focus on exchanged data, FF-A support takes care of how to transport
+  that to the secure world/hypervisor using FF-A
+
+- FF-A support provides driver operations to be used by upper layers:
+
+    - ffa_partition_info_get
+    - ffa_sync_send_receive
+    - ffa_rxtx_unmap
+
+- FF-A bus discovery makes sure FF-A framework is responsive and compatible
+  with the driver
+
+- FF-A bus can be compiled and used without EFI
+
+Relationship between the sandbox emulator and the FF-A device
+---------------------------------------------------------------
+
+::
+
+   => dm tree
+
+    Class     Index  Probed  Driver                Name
+   -----------------------------------------------------------
+   ffa_emul      0  [ + ]   sandbox_ffa_emul      `-- arm-ffa-emul
+    ffa                  0  [    ]   sandbox_arm_ffa               `-- sandbox-arm-ffa
+
+The armffa command
+-----------------------------------
+
+armffa is a command showcasing how to use the FF-A bus and how to invoke the driver operations.
+
+Please refer the command documentation at :doc:`../usage/cmd/armffa`
+
+Example of boot logs with FF-A enabled
+--------------------------------------
+
+For example, when using FF-A with Corstone-1000, debug logs enabled, the output is as follows:
+
+::
+
+   U-Boot 2023.01 (May 10 2023 - 11:08:07 +0000) corstone1000 aarch64
+
+   DRAM:  2 GiB
+   Arm FF-A framework discovery
+   FF-A driver 1.0
+   FF-A framework 1.0
+   FF-A versions are compatible
+   ...
+   FF-A driver 1.0
+   FF-A framework 1.0
+   FF-A versions are compatible
+   EFI: MM partition ID 0x8003
+   ...
+   EFI stub: Booting Linux Kernel...
+   ...
+   Linux version 6.1.9-yocto-standard (oe-user@oe-host) (aarch64-poky-linux-musl-gcc (GCC) 12.2.0, GNU ld (GNU Binutils) 2.40.202301193
+   Machine model: ARM Corstone1000 FPGA MPS3 board
+
+Contributors
+------------
+   * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+.. _`FF-A v1.0 specification`: https://documentation-service.arm.com/static/5fb7e8a6ca04df4095c1d65e
+.. _`SMC Calling Convention v1.2 specification`: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6
diff --git a/doc/arch/index.rst b/doc/arch/index.rst
index b8da4b8c8e..2f916f4026 100644
--- a/doc/arch/index.rst
+++ b/doc/arch/index.rst
@@ -8,6 +8,7 @@ Architecture-specific doc
 
    arc
    arm64
+   arm64.ffa
    m68k
    mips
    nios2
diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
index 77ca6bc4cc..a3631de749 100644
--- a/doc/arch/sandbox/sandbox.rst
+++ b/doc/arch/sandbox/sandbox.rst
@@ -200,6 +200,7 @@ Supported Drivers
 
 U-Boot sandbox supports these emulations:
 
+- Arm FF-A
 - Block devices
 - Chrome OS EC
 - GPIO
diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst
index 66b581c837..46f44bf34e 100644
--- a/doc/board/amlogic/index.rst
+++ b/doc/board/amlogic/index.rst
@@ -118,6 +118,7 @@ Board Documentation
    sei610
    s400
    u200
+   videostrong-kii-pro
    wetek-core2
    wetek-hub
    wetek-play2
diff --git a/doc/board/amlogic/p201.rst b/doc/board/amlogic/p201.rst
index 28aae98d99..13b732fc7e 100644
--- a/doc/board/amlogic/p201.rst
+++ b/doc/board/amlogic/p201.rst
@@ -56,7 +56,7 @@ image but sources have been shared by Linux development contractor, Baylibre:
     $ make
     $ export FIPDIR=$PWD/fip
 
-Go back to mainline U-boot source tree then :
+Go back to mainline U-Boot source tree then :
 
 .. code-block:: bash
 
diff --git a/doc/board/amlogic/p212.rst b/doc/board/amlogic/p212.rst
index c1b73e83b1..a872f32f0f 100644
--- a/doc/board/amlogic/p212.rst
+++ b/doc/board/amlogic/p212.rst
@@ -50,7 +50,7 @@ the git tree published by the board vendor:
     $ make
     $ export FIPDIR=$PWD/fip
 
-Go back to mainline U-boot source tree then :
+Go back to mainline U-Boot source tree then :
 
 .. code-block:: bash
 
diff --git a/doc/board/amlogic/s400.rst b/doc/board/amlogic/s400.rst
index 59dda82375..205e7c38fa 100644
--- a/doc/board/amlogic/s400.rst
+++ b/doc/board/amlogic/s400.rst
@@ -56,7 +56,7 @@ image but sources have been shared by Linux development contractor, Baylibre:
     $ make
     $ export FIPDIR=$PWD/fip
 
-Go back to mainline U-boot source tree then :
+Go back to mainline U-Boot source tree then :
 
 .. code-block:: bash
 
diff --git a/doc/board/amlogic/videostrong-kii-pro.rst b/doc/board/amlogic/videostrong-kii-pro.rst
new file mode 100644
index 0000000000..1c6adac996
--- /dev/null
+++ b/doc/board/amlogic/videostrong-kii-pro.rst
@@ -0,0 +1,112 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Videostrong KII Pro (S905)
+=====================================
+
+Videostrong KII Pro is an Android STB manufactured by Videostrong and 
+based on the Amlogic p201 reference board, with the following specification:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - 16GB eMMC
+ - Gigabit Ethernet
+ - Boardcom BCM4335 WiFi and BT 4.0
+ - HDMI 2.0 4K/60Hz display
+ - 3x USB 2.0 host
+ - 1x USB 2.0 otg
+ - microSD
+ - Infrared receiver
+ - Blue LED
+ - Red LED
+ - Power button (case, front)
+ - Reset button (underside)
+ - DVB Card: DVB-S and DVB-T/C
+
+Schematics are not publicly available.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make videostrong-kii-pro_defconfig
+    $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh wetek-play2 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create 
+a bootloader image and Videostrong has not publicly shared the U-Boot sources 
+needed to build FIP binaries for signing. However you can use the WeTek 
+Play2 binaries from the amlogic-boot-fip repo as the WeTek Play2 and the 
+Videostrong KII Pro share the same RAM chips.
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip/wetek-play2
+    $ export FIPDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+    $ cp $FIPDIR/bl2.bin fip/
+    $ cp $FIPDIR/acs.bin fip/
+    $ cp $FIPDIR/bl21.bin fip/
+    $ cp $FIPDIR/bl30.bin fip/
+    $ cp $FIPDIR/bl301.bin fip/
+    $ cp $FIPDIR/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+    $ $FIPDIR/blx_fix.sh \
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
+    $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+                         --bl31 fip/bl31.img \
+                         --bl33 fip/bl33.bin \
+                         fip/fip.bin
+    $ sed -i 's/\x73\x02\x08\x91/\x1F\x20\x03\xD5/' fip/bl2.bin
+    $ python3 $FIPDIR/acs_tool.py fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+    $ $FIPDIR/blx_fix.sh \
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
+    $ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin
+    $ $FIPDIR/aml_encrypt_gxb --bootsig \
+                              --input fip/boot_new.bin
+                              --output fip/u-boot.bin
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+    $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+    $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+    $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+    $ ./aml_chksum fip/u-boot.bin.gxbb
+    $ dd if=fip/u-boot.bin.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440
diff --git a/doc/board/anbernic/rgxx3.rst b/doc/board/anbernic/rgxx3.rst
index afa7538282..7d1beb423c 100644
--- a/doc/board/anbernic/rgxx3.rst
+++ b/doc/board/anbernic/rgxx3.rst
@@ -7,27 +7,36 @@ This allows U-Boot to boot the following Anbernic devices:
 
  - Anbernic RG353M
  - Anbernic RG353P
+ - Anbernic RG353PS
  - Anbernic RG353V
  - Anbernic RG353VS
  - Anbernic RG503
 
 The correct device is detected automatically by comparing ADC values
-from ADC channel 1. In the event of an RG353V, an attempt is then made
-to probe for an eMMC and if it fails the device is assumed to be an
-RG353VS. Based on the detected device, the environment variables
-"board", "board_name", and "fdtfile" are set to the correct values
-corresponding to the board which can be read by a boot script to boot
-with the correct device tree.
-
-Please note that there are some versions of the RG353 devices with
-different panels. Panel auto-detection is planned for a later date.
+from ADC channel 1. In the event of an RG353V or RG353P, an attempt
+is then made to probe for an eMMC and if it fails the device is assumed
+to be an RG353VS or RG353PS. Based on the detected device, the
+environment variables "board", "board_name", and "fdtfile" are set to
+the correct values corresponding to the board which can be read by a
+boot script to boot with the correct device tree. If the board detected
+is not of type RG503 (which currently has only 1 panel revision) a
+panel detect is then performed by probing a "dummy" display on the DSI
+bus and then querying the display ID. The display ID is then compared
+to a table to get the known compatible string for use in Linux, and
+this string is saved as an environment variable of "panel".
+
+FDT fixups are performed in the event of an RG353M to change the device
+name, or in the event the panel detected does not match the devicetree.
+This allows Linux to load the correct panel driver without having to
+know exactly which panel is used (as there is no user distingushable
+way to tell).
 
 Building U-Boot
 ---------------
 
 .. code-block:: bash
 
-    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ export CROSS_COMPILE=aarch64-linux-gnu-
     $ export BL31=../rkbin/bin/rk35/rk3568_bl31_v1.34.elf
     $ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3568_ddr_1056MHz_v1.13.bin
     $ make anbernic-rgxx3_defconfig
@@ -40,7 +49,7 @@ Image installation
 ------------------
 
 Write the ``u-boot-rockchip.bin`` to an SD card offset 32kb from the
-start.
+start. Please note that eMMC booting has not been tested at this time.
 
 .. code-block:: bash
 
diff --git a/doc/board/beacon/beacon-imx8mm.rst b/doc/board/beacon/beacon-imx8mm.rst
new file mode 100644
index 0000000000..8bf983bff7
--- /dev/null
+++ b/doc/board/beacon/beacon-imx8mm.rst
@@ -0,0 +1,55 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Beacon EmbeddedWorks i.MX8M Mini Devkit
+======================================================
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get DDR firmware
+- Build U-Boot
+- Burn U-Boot to microSD Card
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/nxp-imx/imx-atf.git -b v2.6
+    $ make PLAT=imx8mm bl31 CROSS_COMPILE=aarch64-linux-gnu-
+    $ cp build/imx8mm/release/bl31.bin ../
+
+Get the DDR firmware
+--------------------
+
+.. code-block:: bash
+
+    $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.15.bin
+    $ chmod +x firmware-imx-8.15.bin
+    $ ./firmware-imx-8.15
+    $ cp firmware-imx-8.15/firmware/ddr/synopsys/lpddr4*.bin .
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+    $ make imx8mm_beacon_defconfig
+    $ make CROSS_COMPILE=aarch64-linux-gnu-
+
+Burn U-Boot to microSD Card
+---------------------------
+
+.. code-block:: bash
+
+    $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
+
+Boot
+----
+
+Set baseboard DIP switches for micoSD Card:
+- S11 (1:8) 01101000
+- S10 (1:8) 11001000
+- S17 (1:8) 0110xxxx
diff --git a/doc/board/beacon/beacon-imx8mn.rst b/doc/board/beacon/beacon-imx8mn.rst
new file mode 100644
index 0000000000..bb4a86369b
--- /dev/null
+++ b/doc/board/beacon/beacon-imx8mn.rst
@@ -0,0 +1,53 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Beacon EmbeddedWorks i.MX8M Nano Devkit
+======================================================
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get DDR firmware
+- Build U-Boot
+- Burn U-Boot to microSD Card
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/nxp-imx/imx-atf.git -b v2.6
+    $ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu-
+    $ cp build/imx8mn/release/bl31.bin ../
+
+Get the DDR firmware
+--------------------
+
+.. code-block:: bash
+
+    $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.15.bin
+    $ chmod +x firmware-imx-8.15.bin
+    $ ./firmware-imx-8.15
+    $ cp firmware-imx-8.15/firmware/ddr/synopsys/lpddr4*.bin .
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+    $ make imx8mn_beacon_defconfig
+    $ make CROSS_COMPILE=aarch64-linux-gnu-
+
+Burn U-Boot to microSD Card
+---------------------------
+
+.. code-block:: bash
+
+    $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
+
+Boot
+----
+
+Set baseboard DIP switches for micoSD Card:
+S17 (1:8): 1100xxxx
diff --git a/doc/board/beacon/index.rst b/doc/board/beacon/index.rst
index 1fe1046a4c..bf62b09fba 100644
--- a/doc/board/beacon/index.rst
+++ b/doc/board/beacon/index.rst
@@ -7,3 +7,5 @@ Beacon
    :maxdepth: 2
 
    beacon-imx8mp
+   beacon-imx8mm
+   beacon-imx8mn
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
index 0fe95af56d..d660a223d9 100644
--- a/doc/board/coreboot/coreboot.rst
+++ b/doc/board/coreboot/coreboot.rst
@@ -51,6 +51,40 @@ can be useful for running UEFI applications, for example.
 
 This has only been lightly tested.
 
+CBFS access
+-----------
+
+You can use the 'cbfs' commands to access the Coreboot filesystem::
+
+   => cbfsinit
+   => cbfsinfo
+
+   CBFS version: 0x31313132
+   ROM size: 0x100000
+   Boot block size: 0x4
+   CBFS size: 0xffdfc
+   Alignment: 64
+   Offset: 0x200
+
+   => cbfsls
+        size              type  name
+   ------------------------------------------
+          32       cbfs header  cbfs master header
+       16720                17  fallback/romstage
+       53052                17  fallback/ramstage
+         398               raw  config
+         715               raw  revision
+         117               raw  build_info
+        4044               raw  fallback/dsdt.aml
+         640       cmos layout  cmos_layout.bin
+       17804                17  fallback/postcar
+      335797           payload  fallback/payload
+      607000              null  (empty)
+       10752         bootblock  bootblock
+
+   12 file(s)
+
+   =>
 
 Memory map
 ----------
@@ -100,3 +134,23 @@ input clock is 1843200. So you can add the following CONFIG options::
    CONFIG_DEBUG_UART_CLOCK=1843200
    CONFIG_DEBUG_UART_SHIFT=2
    CONFIG_DEBUG_UART_ANNOUNCE=y
+
+coreboot in CI
+--------------
+
+CI runs tests using a pre-built coreboot image. This ensures that U-Boot can
+boot as a coreboot payload, based on a known-good build of coreboot.
+
+To update the `coreboot.rom` file which is used:
+
+#. Build coreboot with `CONFIG_LINEAR_FRAMEBUFFER=y`. If using `make menuconfig`
+   this is under
+   `Devices ->Display->Framebuffer mode->Linear "high resolution" framebuffer`.
+
+#. Compress the resulting `coreboot.rom`::
+
+      xz -c /path/to/coreboot/build/coreboot.rom >coreboot.rom.xz
+
+#. Upload the file to Google drive
+
+#. Send a patch to change the file ID used by wget in the CI yaml files.
diff --git a/doc/board/emulation/blkdev.rst b/doc/board/emulation/blkdev.rst
new file mode 100644
index 0000000000..f187ff22a8
--- /dev/null
+++ b/doc/board/emulation/blkdev.rst
@@ -0,0 +1,48 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Emulation of block devices
+--------------------------
+
+QEMU can emulate common block devices by adding the following parameters to
+the qemu-system-<arch> command line:
+
+* MMC
+
+  .. code-block:: bash
+
+      -device sdhci-pci,sd-spec-version=3 \
+      -drive if=none,file=disk.img,format=raw,id=MMC1 \
+      -device sd-card,drive=MMC1
+
+* NVMe
+
+  .. code-block:: bash
+
+      -drive if=none,file=disk.img,format=raw,id=NVME1 \
+      -device nvme,drive=NVME1,serial=nvme-1
+
+* SATA
+
+  .. code-block:: bash
+
+      -device ahci,id=ahci0 \
+      -drive if=none,file=disk.img,format=raw,id=SATA1 \
+      -device ide-hd,bus=ahci0.0,drive=SATA1
+
+* USB
+
+  .. code-block:: bash
+
+      -device qemu-xhci \
+      -drive if=none,file=disk.img,format=raw,id=USB1 \
+      -device usb-storage,drive=USB1
+
+* Virtio
+
+  .. code-block:: bash
+
+      -drive if=none,file=disk.img,format=raw,id=VIRTIO1 \
+      -device virtio-blk,drive=VIRTIO1
+
+  .. note::
+     As of v2023.07 U-Boot does not have a driver for virtio-scsi-pci.
diff --git a/doc/board/emulation/index.rst b/doc/board/emulation/index.rst
index b5b6c3fa0d..932c65adeb 100644
--- a/doc/board/emulation/index.rst
+++ b/doc/board/emulation/index.rst
@@ -4,8 +4,10 @@ Emulation
 =========
 
 .. toctree::
-   :maxdepth: 2
+   :maxdepth: 1
 
+   blkdev
+   ../../usage/semihosting
    qemu-arm
    qemu-mips
    qemu-ppce500
diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst
index 16f66388eb..b42d924cc6 100644
--- a/doc/board/emulation/qemu-arm.rst
+++ b/doc/board/emulation/qemu-arm.rst
@@ -54,7 +54,7 @@ Note that for some odd reason qemu-system-aarch64 needs to be explicitly
 told to use a 64-bit CPU or it will boot in 32-bit mode. The -nographic argument
 ensures that output appears on the terminal. Use Ctrl-A X to quit.
 
-Additional persistent U-boot environment support can be added as follows:
+Additional persistent U-Boot environment support can be added as follows:
 
 - Create envstore.img using qemu-img::
 
diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst
index 509bf7c4a6..61137bcbf1 100644
--- a/doc/board/emulation/qemu-riscv.rst
+++ b/doc/board/emulation/qemu-riscv.rst
@@ -133,6 +133,16 @@ An attached disk can be emulated in RISC-V virt machine by adding::
 
 You will have to run 'scsi scan' to use it.
 
+A video console can be emulated in RISC-V virt machine by removing "-nographic"
+and adding::
+
+    -serial stdio -device VGA
+
+In addition, a usb keyboard can be attached to an emulated xHCI controller in
+RISC-V virt machine as an option of input devices by adding::
+
+    -device qemu-xhci,id=xhci -device usb-kbd,bus=xhci.0
+
 Running with KVM
 ----------------
 
diff --git a/doc/board/emulation/qemu-x86.rst b/doc/board/emulation/qemu-x86.rst
index e7dd4e994d..15f56b6bc7 100644
--- a/doc/board/emulation/qemu-x86.rst
+++ b/doc/board/emulation/qemu-x86.rst
@@ -113,7 +113,87 @@ sure the specified CPU supports 64-bit like '-cpu core2duo'. Conversely
 '-cpu pentium' won't work for obvious reasons that the processor only
 supports 32-bit.
 
-Note 64-bit support is very preliminary at this point. Lots of features
-are missing in the 64-bit world. One notable feature is the VGA console
-support which is currently missing, so that you must specify '-nographic'
-to get 64-bit U-Boot up and running.
+Booting distros
+---------------
+
+It is possible to install and boot a standard Linux distribution using
+qemu-x86_64 by setting up a root disk::
+
+   qemu-img create root.img 10G
+
+then using the installer to install. For example, with Ubuntu 2023.04::
+
+   qemu-system-x86_64 -m 8G -smp 4 -bios /tmp/b/qemu-x86_64/u-boot.rom \
+     -drive file=root.img,if=virtio,driver=raw \
+     -drive file=ubuntu-23.04-desktop-amd64.iso,if=virtio,driver=raw
+
+You can also add `-serial mon:stdio` if you want the serial console to show as
+well as the video.
+
+The output will be something like this::
+
+   U-Boot SPL 2023.07 (Jul 23 2023 - 08:00:12 -0600)
+   Trying to boot from SPI
+   Jumping to 64-bit U-Boot: Note many features are missing
+
+
+   U-Boot 2023.07 (Jul 23 2023 - 08:00:12 -0600)
+
+   CPU:   QEMU Virtual CPU version 2.5+
+   DRAM:  8 GiB
+   Core:  20 devices, 13 uclasses, devicetree: separate
+   Loading Environment from nowhere... OK
+   Model: QEMU x86 (I440FX)
+   Net:   e1000: 52:54:00:12:34:56
+          eth0: e1000#0
+   Hit any key to stop autoboot:  0
+   Scanning for bootflows in all bootdevs
+   Seq  Method       State   Uclass    Part  Name                      Filename
+   ---  -----------  ------  --------  ----  ------------------------  ----------------
+   Scanning global bootmeth 'efi_mgr':
+   Hunting with: nvme
+   Hunting with: qfw
+   Hunting with: scsi
+   scanning bus for devices...
+   Hunting with: virtio
+   Scanning bootdev 'qfw_pio.bootdev':
+   fatal: no kernel available
+   Scanning bootdev 'virtio-blk#0.bootdev':
+   Scanning bootdev 'virtio-blk#1.bootdev':
+     0  efi          ready   virtio       2  virtio-blk#1.bootdev.part efi/boot/bootx64.efi
+   ** Booting bootflow 'virtio-blk#1.bootdev.part_2' with efi
+   EFI using ACPI tables at f0060
+        efi_install_fdt() WARNING: Can't have ACPI table and device tree - ignoring DT.
+          efi_run_image() Booting /efi\boot\bootx64.efi
+   error: file `/boot/' not found.
+
+Standard boot looks through various available devices and finds the virtio
+disks, then boots from the first one. After a second or so the grub menu appears
+and you can work through the installer flow normally.
+
+Note that standard boot will not find 32-bit distros, since it looks for a
+different filename.
+
+Current limitations
+-------------------
+
+Only qemu-x86-64 can be used for booting distros, since qemu-x86 (the 32-bit
+version of U-Boot) seems to have an EFI bug leading to the boot handing after
+Linux is selected from grub, e.g. with `debian-12.1.0-i386-netinst.iso`::
+
+   ** Booting bootflow 'virtio-blk#1.bootdev.part_2' with efi
+   EFI using ACPI tables at f0180
+        efi_install_fdt() WARNING: Can't have ACPI table and device tree - ignoring DT.
+          efi_run_image() Booting /efi\boot\bootia32.efi
+   Failed to open efi\boot\root=/dev/sdb3 - Not Found
+   Failed to load image 큀緃: Not Found
+   start_image() returned Not Found, falling back to default loader
+   Welcome to GRUB!
+
+The bochs video driver also seems to cause problems before the OS is able to
+show a display.
+
+Finally, the use of `-M accel=kvm` is intended to use the native CPU's
+virtual-machine features to accelerate operation, but this causes U-Boot to hang
+when jumping 64-bit mode, at least on AMD machines. This may be a bug in U-Boot
+or something else.
diff --git a/doc/board/gateworks/imx8mm_venice.rst b/doc/board/gateworks/imx8mm_venice.rst
index f1e7e49944..ea78dfd7ae 100644
--- a/doc/board/gateworks/imx8mm_venice.rst
+++ b/doc/board/gateworks/imx8mm_venice.rst
@@ -47,4 +47,6 @@ Update eMMC
 
    => tftpboot $loadaddr flash.bin
    => setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200
-   => mmc dev 2 && mmc write $loadaddr 0x42 $blkcnt
+   => mmc dev 2 0 && mmc write $loadaddr 0x42 $blkcnt # emmc user hw part
+   => mmc dev 2 1 && mmc write $loadaddr 0x42 $blkcnt # or emmc boot0 hw part
+   => mmc dev 2 2 && mmc write $loadaddr 0x42 $blkcnt # or emmc boot1 hw part
diff --git a/doc/board/gateworks/imx8mn_venice.rst b/doc/board/gateworks/imx8mn_venice.rst
index 7ba953a4a8..7015f4ef31 100644
--- a/doc/board/gateworks/imx8mn_venice.rst
+++ b/doc/board/gateworks/imx8mn_venice.rst
@@ -47,4 +47,6 @@ Update eMMC
 
    => tftpboot $loadaddr flash.bin
    => setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200
-   => mmc dev 2 && mmc write $loadaddr 0x40 $blkcnt
+   => mmc dev 2 0 && mmc write $loadaddr 0x40 $blkcnt # emmc user hw part
+   => mmc dev 2 1 && mmc write $loadaddr 0 $blkcnt # or emmc boot0 hw part
+   => mmc dev 2 2 && mmc write $loadaddr 0 $blkcnt # or emmc boot1 hw part
diff --git a/doc/board/gateworks/imx8mp_venice.rst b/doc/board/gateworks/imx8mp_venice.rst
index 632cd742d1..a219caadff 100644
--- a/doc/board/gateworks/imx8mp_venice.rst
+++ b/doc/board/gateworks/imx8mp_venice.rst
@@ -47,4 +47,6 @@ Update eMMC
 
    => tftpboot $loadaddr flash.bin
    => setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200
-   => mmc dev 2 && mmc write $loadaddr 0x40 $blkcnt
+   => mmc dev 2 0 && mmc write $loadaddr 0x40 $blkcnt # emmc user hw part
+   => mmc dev 2 1 && mmc write $loadaddr 0 $blkcnt # or emmc boot0 hw part
+   => mmc dev 2 2 && mmc write $loadaddr 0 $blkcnt # or emmc boot1 hw part
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 2e11dbb06f..0194f0aaa3 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -35,6 +35,7 @@ Board-specific doc
    nokia/index
    nxp/index
    openpiton/index
+   phytec/index
    purism/index
    qualcomm/index
    renesas/index
@@ -48,6 +49,7 @@ Board-specific doc
    starfive/index
    ste/index
    tbs/index
+   thead/index
    ti/index
    toradex/index
    variscite/index
diff --git a/doc/board/microchip/mpfs_icicle.rst b/doc/board/microchip/mpfs_icicle.rst
index 09c2c6a9c1..1464e536e9 100644
--- a/doc/board/microchip/mpfs_icicle.rst
+++ b/doc/board/microchip/mpfs_icicle.rst
@@ -134,7 +134,7 @@ Build OpenSBI
 .. code-block:: none
 
    make PLATFORM=generic FW_PAYLOAD_PATH=<u-boot-directory>/u-boot.bin
-   FW_FDT_PATH=<u-boot-directory>/arch/riscv/dts/microchip-mpfs-icicle-kit-.dtb
+   FW_FDT_PATH=<u-boot-directory>/arch/riscv/dts/mpfs-icicle-kit-.dtb
 
 3. Output "fw_payload.bin" file available at
    "<opensbi-directory>/build/platform/generic/firmware/fw_payload.bin"
@@ -277,14 +277,14 @@ load uImage (with initramfs).
    done
    Bytes transferred = 14482480 (dcfc30 hex)
 
-   RISC-V # tftpboot ${fdt_addr_r} microchip-mpfs-icicle-kit.dtb
+   RISC-V # tftpboot ${fdt_addr_r} mpfs-icicle-kit.dtb
    ethernet@20112000: PHY present at 9
    ethernet@20112000: Starting autonegotiation...
    ethernet@20112000: Autonegotiation complete
    ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800)
    Using ethernet@20112000 device
    TFTP from server 192.168.1.3; our IP address is 192.168.1.5
-   Filename 'microchip-mpfs-icicle-kit.dtb'.
+   Filename 'mpfs-icicle-kit.dtb'.
    Load address: 0x82200000
    Loading: #
 			2.5 MiB/s
diff --git a/doc/board/nxp/imx8mp_evk.rst b/doc/board/nxp/imx8mp_evk.rst
index e7cc7b396b..72175dbe78 100644
--- a/doc/board/nxp/imx8mp_evk.rst
+++ b/doc/board/nxp/imx8mp_evk.rst
@@ -37,21 +37,22 @@ Build U-Boot
 
 .. code-block:: bash
 
+Note: builddir is U-Boot build directory (source directory for in-tree builds).
+
    $ export CROSS_COMPILE=aarch64-poky-linux-
    $ make O=build imx8mp_evk_defconfig
-   $ cp ../imx-atf/build/imx8mp/release/bl31.bin ./build/bl31.bin
-   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_202006.bin ./build/
-   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_202006.bin ./build/
-   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_202006.bin ./build/
-   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_202006.bin ./build/
-   $ export ATF_LOAD_ADDR=0x970000
-   $ make O=build
+   $ cp ../imx-atf/build/imx8mp/release/bl31.bin $(builddir)
+   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_202006.bin $(builddir)
+   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_202006.bin $(builddir)
+   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_202006.bin $(builddir)
+   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_202006.bin $(builddir)
+   $ make
 
 Burn the flash.bin to the MicroSD card at offset 32KB:
 
 .. code-block:: bash
 
-   $sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
+   $ sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
 
 Boot
 ----
diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst
index 35465d0061..49b4842b30 100644
--- a/doc/board/nxp/ls1046ardb.rst
+++ b/doc/board/nxp/ls1046ardb.rst
@@ -150,7 +150,7 @@ Then, launch openocd like::
 
     openocd -f u-boot.tcl
 
-You should see the U-boot SPL banner followed by the banner for U-Boot proper
+You should see the U-Boot SPL banner followed by the banner for U-Boot proper
 in the output of openocd. The CMSIS-DAP adapter is slow, so this can take a
 long time. If you don't see it, something has gone wrong. After a while, you
 should see the prompt. You can load an image using semihosting by running::
diff --git a/doc/board/nxp/mx6sabresd.rst b/doc/board/nxp/mx6sabresd.rst
index fe15ba7b79..c9869f4a73 100644
--- a/doc/board/nxp/mx6sabresd.rst
+++ b/doc/board/nxp/mx6sabresd.rst
@@ -53,7 +53,7 @@ This will generate the SPL and u-boot-dtb.img binaries.
 
 - Boot first from SD card as shown in the previous section
 
-In U-boot change the eMMC partition config::
+In U-Boot change the eMMC partition config::
 
    => mmc partconf 2 1 0 0
 
diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst
new file mode 100644
index 0000000000..a5b442045e
--- /dev/null
+++ b/doc/board/phytec/index.rst
@@ -0,0 +1,10 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+PHYTEC
+======
+
+.. toctree::
+   :maxdepth: 2
+
+   phycore-imx8mm
+   phycore-imx8mp
diff --git a/doc/board/phytec/phycore-imx8mm.rst b/doc/board/phytec/phycore-imx8mm.rst
new file mode 100644
index 0000000000..e9dc225990
--- /dev/null
+++ b/doc/board/phytec/phycore-imx8mm.rst
@@ -0,0 +1,60 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+phyCORE-i.MX 8M Mini
+====================
+
+The phyCORE-i.MX 8M Mini with 2GB of main memory is supported.
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Boot
+
+Build the ARM Trusted firmware binary
+-------------------------------------
+
+.. code-block:: bash
+
+   $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+   $ cd trusted-firmware-a
+   $ export CROSS_COMPILE=aarch64-linux-gnu
+   $ export IMX_BOOT_UART_BASE=0x30880000
+   $ make PLAT=imx8mm bl31
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.19.bin
+   $ chmod +x firmware-imx-8.19.bin
+   $ ./firmware-imx-8.19.bin
+
+Build U-Boot for SD card
+------------------------
+
+Copy binaries
+^^^^^^^^^^^^^
+
+.. code-block:: bash
+
+   $ cp <TF-A dir>/build/imx8mm/release/bl31.bin .
+   $ cp firmware-imx-8.19/firmware/ddr/synopsys/lpddr4*.bin .
+
+Build U-Boot
+^^^^^^^^^^^^
+
+.. code-block:: bash
+
+   $ make phycore-imx8mm_defconfig
+   $ make flash.bin
+
+Flash SD card
+^^^^^^^^^^^^^
+
+.. code-block:: bash
+
+   $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=sync
diff --git a/doc/board/phytec/phycore-imx8mp.rst b/doc/board/phytec/phycore-imx8mp.rst
new file mode 100644
index 0000000000..fda751aeff
--- /dev/null
+++ b/doc/board/phytec/phycore-imx8mp.rst
@@ -0,0 +1,60 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+phyCORE-i.MX 8M Plus
+====================
+
+The phyCORE-i.MX 8M Plus with 2GB of main memory is supported.
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Boot
+
+Build the ARM Trusted firmware binary
+-------------------------------------
+
+.. code-block:: bash
+
+   $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+   $ cd trusted-firmware-a
+   $ export CROSS_COMPILE=aarch64-linux-gnu
+   $ export IMX_BOOT_UART_BASE=0x30860000
+   $ make PLAT=imx8mp bl31
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.19.bin
+   $ chmod +x firmware-imx-8.19.bin
+   $ ./firmware-imx-8.19.bin
+
+Build U-Boot for SD card
+------------------------
+
+Copy binaries
+^^^^^^^^^^^^^
+
+.. code-block:: bash
+
+   $ cp <TF-A dir>/build/imx8mp/release/bl31.bin .
+   $ cp firmware-imx-8.19/firmware/ddr/synopsys/lpddr4*.bin .
+
+Build U-Boot
+^^^^^^^^^^^^
+
+.. code-block:: bash
+
+   $ make phycore-imx8mp_defconfig
+   $ make flash.bin
+
+Flash SD card
+^^^^^^^^^^^^^
+
+.. code-block:: bash
+
+   $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=sync
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 99376fb54c..4668e59851 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -84,21 +84,35 @@ List of mainline supported Rockchip boards:
      - Orange Pi RK3399 (orangepi-rk3399)
      - Pine64 RockPro64 (rockpro64-rk3399)
      - Radxa ROCK 4C+ (rock-4c-plus-rk3399)
-     - Radxa ROCK 4SE (rock-pi-4-rk3399)
+     - Radxa ROCK 4SE (rock-4se-rk3399)
      - Radxa ROCK Pi 4A/B/A+/B+ (rock-pi-4-rk3399)
      - Radxa ROCK Pi 4C (rock-pi-4c-rk3399)
      - Rockchip Evb-RK3399 (evb_rk3399)
      - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
 
 * rk3566
-     - Anbernic RGxx3 (rgxx3-rk3566)
+     - Anbernic RGxx3 (anbernic-rgxx3)
+     - Pine64 Quartz64-A Board (quartz64-a-rk3566)
+     - Pine64 Quartz64-B Board (quartz64-b-rk3566)
+     - Pine64 SOQuartz on Blade (soquartz-blade-rk3566)
+     - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566)
+     - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566)
+     - Radxa CM3 IO Board (radxa-cm3-io-rk3566)
 
 * rk3568
      - Rockchip Evb-RK3568 (evb-rk3568)
+     - EmbedFire LubanCat 2 (lubancat-2-rk3568)
+     - FriendlyElec NanoPi R5C (nanopi-r5c-rk3568)
+     - FriendlyElec NanoPi R5S (nanopi-r5s-rk3568)
+     - Hardkernel ODROID-M1 (odroid-m1-rk3568)
+     - Radxa E25 Carrier Board (radxa-e25-rk3568)
+     - Radxa ROCK 3 Model A (rock-3a-rk3568)
 
 * rk3588
      - Rockchip EVB (evb-rk3588)
-     - Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-rk3588)
+     - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588)
+     - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
+     - Radxa ROCK 5A (rock5a-rk3588s)
      - Radxa ROCK 5B (rock5b-rk3588)
 
 * rv1108
@@ -211,7 +225,7 @@ SD Card
 ^^^^^^^
 
 All Rockchip platforms (except rk3128 which doesn't use SPL) are now
-supporting a single boot image using binman and pad_cat.
+supporting a single boot image using binman.
 
 To write an image that boots from a SD card (assumed to be /dev/sda):
 
@@ -262,31 +276,15 @@ is u-boot-dtb.img
 SPI
 ^^^
 
-The SPI boot method requires the generation of idbloader.img with help of the mkimage tool.
+Write u-boot-rockchip-spi.bin to offset 0 of SPI flash.
 
-SPL-alone SPI boot image:
-
-.. code-block:: bash
-
-        ./tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin idbloader.img
-
-TPL+SPL SPI boot image:
-
-.. code-block:: bash
-
-        ./tools/mkimage -n rk3399 -T rkspi -d tpl/u-boot-tpl.bin:spl/u-boot-spl.bin idbloader.img
-
-Copy SPI boot images into SD card and boot from SD:
+Copy u-boot-rockchip-spi.bin into SD card and boot from SD:
 
 .. code-block:: bash
 
         sf probe
-        load mmc 1:1 $kernel_addr_r idbloader.img
-        sf erase 0 +$filesize
-        sf write $kernel_addr_r 0 ${filesize}
-        load mmc 1:1 ${kernel_addr_r} u-boot.itb
-        sf erase 0x60000 +$filesize
-        sf write $kernel_addr_r 0x60000 ${filesize}
+        load mmc 1:1 $kernel_addr_r u-boot-rockchip-spi.bin
+        sf update $fileaddr 0 $filesize
 
 2. Package the image with Rockchip miniloader
 ---------------------------------------------
@@ -333,12 +331,12 @@ Note:
 
 Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support.
 If all other boot options fail then it enters into a BootROM mode on the USB OTG port.
-This method loads TPL/SPL on NAND with U-boot and kernel on SD card.
+This method loads TPL/SPL on NAND with U-Boot and kernel on SD card.
 
 SD Card
 ^^^^^^^
 
-U-boot expects a GPT partition map and a boot directory structure with files on the SD card.
+U-Boot expects a GPT partition map and a boot directory structure with files on the SD card.
 
 .. code-block:: none
 
@@ -363,7 +361,7 @@ Boot partition:
         zImage
         rk3066a-mk808.dtb
 
-To write a U-boot image to the SD card (assumed to be /dev/sda):
+To write a U-Boot image to the SD card (assumed to be /dev/sda):
 
 .. code-block:: bash
 
diff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst
index 074d6aa15a..ee3c5c9584 100644
--- a/doc/board/siemens/iot2050.rst
+++ b/doc/board/siemens/iot2050.rst
@@ -66,17 +66,16 @@ U-Boot:
 
 .. code-block:: text
 
- $ export ATF=/path/to/bl31.bin
- $ export TEE=/path/to/tee-pager_v2.bin
-
- # configure for PG1
- $ make iot2050_pg1_defconfig
-
- # or configure for PG2 or the M.2 variant
- $ make iot2050_pg2_defconfig
+ $ export BL31=/path/to/bl31.bin
+ $ export TEE=/path/to/tee-raw.bin
+ $ make iot2050_defconfig
 
  $ make
 
+This will generate two different flash images: flash-p1.bin that targets the
+first generation of IOT2050 devices and flash-pg2.bin that runs on PG2
+including M.2 devices.
+
 Flashing
 --------
 
@@ -85,20 +84,20 @@ Via U-Boot:
 .. code-block:: text
 
  IOT2050> sf probe
- IOT2050> load mmc 0:1 $loadaddr /path/to/flash.bin
+ IOT2050> load mmc 0:1 $loadaddr /path/to/flash-pgX.bin
  IOT2050> sf update $loadaddr 0x0 $filesize
 
 Via external programmer Dediprog SF100 or SF600:
 
 .. code-block:: text
 
- $ dpcmd --vcc 2 -v -u flash.bin
+ $ dpcmd --vcc 2 -v -u flash-pgX.bin
 
 Signing (optional)
 ------------------
 
 To enable verified boot for the firmware artifacts after the Siemens-managed
-first-stage loader (seboot_pg*.bin), the following steps need to be taken
+first-stage loader (seboot_pgX.bin), the following steps need to be taken
 before and after the build:
 
 Generate dtsi holding the public key
@@ -131,8 +130,8 @@ Build U-Boot
 
 See related section above.
 
-Sign flash.bin
-^^^^^^^^^^^^^^
+Sign flash-pgX.bin
+^^^^^^^^^^^^^^^^^^
 
 In the build folder still containing artifacts from step 3, invoke:
 
@@ -140,10 +139,10 @@ In the build folder still containing artifacts from step 3, invoke:
 
  tools/iot2050-sign-fw.sh /path/to/key.pem
 
-Flash signed flash.bin
-^^^^^^^^^^^^^^^^^^^^^^
+Flash signed flash-pgX.bin
+^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-The signing has happen in-place in flash.bin, thus the flashing procedure
+The signing has happen in-place in flash-pgX.bin, thus the flashing procedure
 described above.
 
 M.2 slot configuration
diff --git a/doc/board/sifive/unmatched.rst b/doc/board/sifive/unmatched.rst
index de2aab59bb..c515949066 100644
--- a/doc/board/sifive/unmatched.rst
+++ b/doc/board/sifive/unmatched.rst
@@ -558,7 +558,7 @@ for partitions one through three respectively.
 	    --new=3:10280:10535 --change-name=3:env   --typecode=3:3DE21764-95BD-54BD-A5C3-4ABE786F38A8 \
 	    /dev/mtdblock0
 
-Write U-boot SPL and U-boot to their partitions.
+Write U-Boot SPL and U-Boot to their partitions.
 
 .. code-block:: none
 
diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst
index 2d943c23be..aa7080e26c 100644
--- a/doc/board/socionext/developerbox.rst
+++ b/doc/board/socionext/developerbox.rst
@@ -57,14 +57,20 @@ Installation
 
 You can install the SNI_NOR_UBOOT.fd via NOR flash writer.
 
-Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port.
-Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing.
+Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine
+or other mezzanine which can connect to the LS-UART0 port.
+Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the
+board on again. The flash writer program will be started automatically;
+don't forget to turn the DSW2-7 off again after flashing.
 
-*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail*
+*!!CAUTION!! If you write the U-Boot image on wrong address, the board can
+be bricked. See below page if you need to recover the bricked board. See
+the following page for more details*
 
 https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html
 
-When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0::
+When the serial flasher is running correctly it will show the following boot
+messages printed to the LS-UART0 console::
 
 
   /*------------------------------------------*/
@@ -81,7 +87,143 @@ Once the flasher tool is running we are ready flash the UEFI image::
   flash rawwrite 200000 100000
   >> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) <<
 
-*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).*
+*!!NOTE!! The flasher command parameter is different from the command for
+board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the
+size 100000 (1-five-0, 1M in hex).*
 
-After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board.
+After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and
+reset the board.
 
+
+Enable FWU Multi Bank Update
+============================
+
+DeveloperBox supports the FWU Multi Bank Update. You *MUST* update both
+*SCP firmware* and *TF-A* for this feature. This will change the layout and
+the boot process but you can switch back to the normal one by changing
+the DSW 1-4 off.
+
+Configure U-Boot
+----------------
+
+To enable the FWU Multi Bank Update on the DeveloperBox board the
+configs/synquacer_developerbox_defconfig enables default FWU configuration ::
+
+ CONFIG_FWU_MULTI_BANK_UPDATE=y
+ CONFIG_FWU_MDATA=y
+ CONFIG_FWU_MDATA_MTD=y
+ CONFIG_FWU_NUM_BANKS=2
+ CONFIG_FWU_NUM_IMAGES_PER_BANK=1
+ CONFIG_CMD_FWU_METADATA=y
+
+And build it::
+
+  cd u-boot/
+  export ARCH=arm64
+  export CROSS_COMPILE=aarch64-linux-gnu-
+  make synquacer_developerbox_defconfig
+  make -j `noproc`
+  cd ../
+
+By default, the CONFIG_FWU_NUM_BANKS and CONFIG_FWU_NUM_IMAGES_PER_BANKS are
+set to 2 and 1 respectively. This uses FIP (Firmware Image Package) type image
+which contains TF-A, U-Boot and OP-TEE (the OP-TEE is optional).
+You can use fiptool to compose the FIP image from those firmware images.
+
+Rebuild SCP firmware
+--------------------
+
+Rebuild SCP firmware which supports FWU Multi Bank Update as below::
+
+  cd SCP-firmware/
+  OUT=./build/product/synquacer
+  ROMFW_FILE=$OUT/scp_romfw/$SCP_BUILD_MODE/bin/scp_romfw.bin
+  RAMFW_FILE=$OUT/scp_ramfw/$SCP_BUILD_MODE/bin/scp_ramfw.bin
+  ROMRAMFW_FILE=scp_romramfw_release.bin
+
+  make CC=arm-none-eabi-gcc PRODUCT=synquacer MODE=release
+  tr "\000" "\377" < /dev/zero | dd of=${ROMRAMFW_FILE} bs=1 count=196608
+  dd if=${ROMFW_FILE} of=${ROMRAMFW_FILE} bs=1 conv=notrunc seek=0
+  dd if=${RAMFW_FILE} of=${ROMRAMFW_FILE} bs=1 seek=65536
+  cd ../
+
+And you can get the `scp_romramfw_release.bin` file.
+
+Rebuild OPTEE firmware
+----------------------
+
+Rebuild OPTEE to use in new-layout FIP as below::
+
+  cd optee_os/
+  make -j`nproc` PLATFORM=synquacer ARCH=arm \
+    CROSS_COMPILE64=aarch64-linux-gnu- CFG_ARM64_core=y \
+    CFG_CRYPTO_WITH_CE=y CFG_CORE_HEAP_SIZE=524288 CFG_CORE_DYN_SHM=y \
+    CFG_CORE_ARM64_PA_BITS=48 CFG_TEE_CORE_LOG_LEVEL=1 CFG_TEE_TA_LOG_LEVEL=1
+  cp out/arm-plat-synquacer/core/tee-pager_v2.bin ../arm-trusted-firmware/
+
+The produced `tee-pager_v2.bin` is to be used while building TF-A next.
+
+
+Rebuild TF-A and FIP
+--------------------
+
+Rebuild TF-A which supports FWU Multi Bank Update as below::
+
+  cd arm-trusted-firmware/
+  make CROSS_COMPILE=aarch64-linux-gnu- -j`nproc` PLAT=synquacer \
+     TRUSTED_BOARD_BOOT=1 SPD=opteed SQ_RESET_TO_BL2=1 GENERATE_COT=1 \
+     MBEDTLS_DIR=../mbedtls BL32=tee-pager_v2.bin \
+     BL33=../u-boot/u-boot.bin all fip fiptool
+
+And make a FIP image.::
+
+  cp build/synquacer/release/fip.bin SPI_NOR_NEWFIP.fd
+  tools/fiptool/fiptool update --tb-fw build/synquacer/release/bl2.bin SPI_NOR_NEWFIP.fd
+
+UUIDs for the FWU Multi Bank Update
+-----------------------------------
+
+FWU multi-bank update requires some UUIDs. The DeveloperBox platform uses
+following UUIDs.
+
+ - Location UUID for the FIP image: 17e86d77-41f9-4fd7-87ec-a55df9842de5
+ - Image type UUID for the FIP image: 10c36d7d-ca52-b843-b7b9-f9d6c501d108
+ - Image UUID for Bank0 : 5a66a702-99fd-4fef-a392-c26e261a2828
+ - Image UUID for Bank1 : a8f868a1-6e5c-4757-878d-ce63375ef2c0
+
+These UUIDs are used for making a FWU metadata image.
+
+u-boot$ ./tools/mkfwumdata -i 1 -b 2 \
+	17e86d77-41f9-4fd7-87ec-a55df9842de5,10c36d7d-ca52-b843-b7b9-f9d6c501d108,5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0 \
+	../devbox-fwu-mdata.img
+
+Create Accept & Revert capsules
+
+u-boot$ ./tools/mkeficapsule -A -g 7d6dc310-52ca-43b8-b7b9-f9d6c501d108 NEWFIP_accept.Cap
+u-boot$ ./tools/mkeficapsule -R NEWFIP_revert.Cap
+
+Install via flash writer
+------------------------
+
+As explained in above section, the new FIP image and the FWU metadata image
+can be installed via NOR flash writer.
+
+Once the flasher tool is running we are ready to flash the images.::
+Write the FIP image to the Bank-0 & 1 at 6MB and 10MB offset.::
+
+  flash rawwrite 600000 180000
+  flash rawwrite a00000 180000
+  >> Send SPI_NOR_NEWFIP.fd via XMODEM (Control-A S in minicom) <<
+
+  flash rawwrite 500000 1000
+  flash rawwrite 530000 1000
+  >> Send devbox-fwu-mdata.img via XMODEM (Control-A S in minicom) <<
+
+And write the new SCP firmware.::
+
+  flash write cm3
+  >> Send scp_romramfw_release.bin via XMODEM (Control-A S in minicom) <<
+
+At last, turn on the DSW 3-4 on the board, and reboot.
+Note that if DSW 3-4 is turned off, the DeveloperBox will boot from
+the original EDK2 firmware (or non-FWU U-Boot if you already installed).
diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst
index c0b1daa041..63b44776ff 100644
--- a/doc/board/st/stm32mp1.rst
+++ b/doc/board/st/stm32mp1.rst
@@ -345,7 +345,7 @@ Build Procedure
         - BL33=u-boot-nodtb.bin
         - BL33_CFG=u-boot.dtb
 
-     You can also update a existing FIP after U-boot compilation with fiptool,
+     You can also update a existing FIP after U-Boot compilation with fiptool,
      a tool provided by TF-A_::
 
      # fiptool update --nt-fw u-boot-nodtb.bin --hw-config u-boot.dtb fip-stm32mp157c-ev1.bin
diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst
index 4d43ac9729..941899a0a4 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -62,7 +62,7 @@ Now build the U-Boot SPL and U-Boot proper
 .. code-block:: console
 
 	cd <U-Boot-dir>
-	make starfive_visionfive2_13b_defconfig
+	make starfive_visionfive2_defconfig
 	make OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
 
 This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
@@ -118,7 +118,7 @@ Program the SD card
 	sudo cp u-boot.itb /mnt/
 	sudo cp Image.gz /mnt/
 	sudo cp initramfs.cpio.gz /mnt/
-	sudo cp jh7110-starfive-visionfive-2-v1.3b.dtb /mnt/
+	sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
 	sudo umount /mnt
 
 Booting
@@ -206,16 +206,16 @@ Sample boot log from StarFive VisionFive2 board
 	Working FDT set to ff74a340
 	Hit any key to stop autoboot:  0
 	StarFive #
-	StarFive #version
+	StarFive # version
 	U-Boot 2023.04-rc2-00055-gfc43b9c51a-dirty (Mar 02 2023 - 10:51:39 +0800)
 
 	riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot VF2_515_v1.0.0_rc4) 10.3.0
 	GNU ld (GNU Binutils) 2.36.1
 	StarFive #
-	StarFive #mmc dev 1
+	StarFive # mmc dev 1
 	switch to partitions #0, OK
 	mmc1 is current device
-	StarFive #mmc info
+	StarFive # mmc info
 	Device: mmc@16020000
 	Manufacturer ID: 9f
 	OEM: 5449
@@ -229,7 +229,7 @@ Sample boot log from StarFive VisionFive2 board
 	Bus Width: 4-bit
 	Erase Group Size: 512 Bytes
 	StarFive #
-	StarFive #mmc part
+	StarFive # mmc part
 
 	Partition Map for MMC device 1  --   Partition Type: EFI
 
@@ -253,7 +253,7 @@ Sample boot log from StarFive VisionFive2 board
 					(data)
 			guid:   539a6df9-4655-4953-8541-733ca36eb1db
 	StarFive #
-	StarFive #fatls mmc 1:3
+	StarFive # fatls mmc 1:3
 	6429424   Image.gz
 	717705   u-boot.itb
 	125437   u-boot-spl.bin.normal.out
@@ -262,13 +262,13 @@ Sample boot log from StarFive VisionFive2 board
 
 	5 file(s), 0 dir(s)
 
-	StarFive #fatload mmc 1:3 ${kernel_addr_r} Image.gz
+	StarFive # fatload mmc 1:3 ${kernel_addr_r} Image.gz
 	6429424 bytes read in 394 ms (15.6 MiB/s)
-	StarFive #fatload mmc 1:3 ${fdt_addr_r} jh7110-starfive-visionfive-2-v1.3b.dtb
+	StarFive # fatload mmc 1:3 ${fdt_addr_r} jh7110-starfive-visionfive-2.dtb
 	11285 bytes read in 5 ms (2.2 MiB/s)
-	StarFive #fatload mmc 1:3 ${ramdisk_addr_r} initramfs.cpio.gz
+	StarFive # fatload mmc 1:3 ${ramdisk_addr_r} initramfs.cpio.gz
 	152848495 bytes read in 9271 ms (15.7 MiB/s)
-	StarFive #booti ${kernel_addr_r} ${ramdisk_addr_r}:${filesize} ${fdt_addr_r}
+	StarFive # booti ${kernel_addr_r} ${ramdisk_addr_r}:${filesize} ${fdt_addr_r}
 	Uncompressing Kernel Image
 	## Flattened Device Tree blob at 46000000
 	Booting using the fdt blob at 0x46000000
diff --git a/doc/board/thead/index.rst b/doc/board/thead/index.rst
new file mode 100644
index 0000000000..41566d3a36
--- /dev/null
+++ b/doc/board/thead/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+T-HEAD
+========
+
+.. toctree::
+   :maxdepth: 1
+
+   lpi4a
diff --git a/doc/board/thead/lpi4a.rst b/doc/board/thead/lpi4a.rst
new file mode 100644
index 0000000000..e395c6ae12
--- /dev/null
+++ b/doc/board/thead/lpi4a.rst
@@ -0,0 +1,129 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Sipeed's Lichee PI 4A based on T-HEAD TH1520 SoC
+================================================
+
+The LicheePi4A is a high-performance RISC-V SBC based on TH1520(4xC910@1.85GHz),
+comes with 4/8/16 GB RAM, and up to 128GB eMMC, and rich peripherals.
+
+ - SoC            T-HEAD TH1520 SoC
+ - System Memory  4GB, 8GB, or 16GB LPDDR4X
+ - Storage        eMMC flash with 8/32/128 GB
+ -                external microSD slot
+ - Networking     2x Gigabit Ethernet
+ -                WiFi+BT
+ - Display        HDMI2.0, 4-lane MIPI DSI
+ - Camera         4-lane MIPI CSI + 2x2-lane MIPI CSI
+ - Audio          Onboard Speaker, 2xMEMS MIC, 3.5mm headphone jack
+ - USB            4xUSB3.0 Type-A, 1xUSB2.0 Type-C
+ - GPIO           2x10Pin breakout, UART/IIC/SPI
+ - Power          DC 12V/2A, POE 5V/2.4A, USB Type-C 5V/2A
+
+TH1520 RISC-V SoC
+-----------------
+
+The TH1520 SoC consist of quad-core RISC-V Xuantie C910 (RV64GCV) processor,
+Xuantie C906 audio DSP, low power Xuantie E902 core, it also integrate
+Imagination GPU for graphics, and 4 TOPS NPU for AI acceleration.
+
+Mainline support
+----------------
+
+The support for following drivers are already enabled:
+
+1. ns16550 UART Driver.
+
+Building
+~~~~~~~~
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+   export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+The U-Boot is capable of running in M-Mode, so we can directly build it.
+
+.. code-block:: console
+
+	cd <U-Boot-dir>
+	make th1520_lpi4a_defconfig
+	make
+
+This will generate u-boot-dtb.bin
+
+Booting
+~~~~~~~
+
+Currently, we rely on vendor u-boot to initialize the clock, pinctrl subsystem,
+and chain load the mainline u-boot image either via tftp or emmc storage,
+then bootup from it.
+
+Sample boot log from Lichee PI 4A board via tftp
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: none
+
+	brom_ver 8
+	[APP][E] protocol_connect failed, exit.
+
+	U-Boot SPL 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000)
+	FM[1] lpddr4x dualrank freq=3733 64bit dbi_off=n sdram init
+	ddr initialized, jump to uboot
+	image has no header
+
+
+	U-Boot 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000)
+
+	CPU:   rv64imafdcvsu
+	Model: T-HEAD c910 light
+	DRAM:  8 GiB
+	C910 CPU FREQ: 750MHz
+	AHB2_CPUSYS_HCLK FREQ: 250MHz
+	AHB3_CPUSYS_PCLK FREQ: 125MHz
+	PERISYS_AHB_HCLK FREQ: 250MHz
+	PERISYS_APB_PCLK FREQ: 62MHz
+	GMAC PLL POSTDIV FREQ: 1000MHZ
+	DPU0 PLL POSTDIV FREQ: 1188MHZ
+	DPU1 PLL POSTDIV FREQ: 1188MHZ
+	MMC:   sdhci@ffe7080000: 0, sd@ffe7090000: 1
+	Loading Environment from MMC... OK
+	Error reading output register
+	Warning: cannot get lcd-en GPIO
+	LCD panel cannot be found : -121
+	splash screen startup cost 16 ms
+	In:    serial
+	Out:   serial
+	Err:   serial
+	Net:
+	Warning: ethernet@ffe7070000 using MAC address from ROM
+	eth0: ethernet@ffe7070000ethernet@ffe7070000:0 is connected to ethernet@ffe7070000.  Reconnecting to ethernet@ffe7060000
+
+	Warning: ethernet@ffe7060000 (eth1) using random MAC address - 42:25:d4:16:5f:fc
+	, eth1: ethernet@ffe7060000
+	Hit any key to stop autoboot:  2
+	ethernet@ffe7060000 Waiting for PHY auto negotiation to complete.. done
+	Speed: 1000, full duplex
+	Using ethernet@ffe7070000 device
+	TFTP from server 192.168.8.50; our IP address is 192.168.8.45
+	Filename 'u-boot-dtb.bin'.
+	Load address: 0x1c00000
+	Loading: * #########################
+		 8 MiB/s
+	done
+	Bytes transferred = 376686 (5bf6e hex)
+	## Starting application at 0x01C00000 ...
+
+        U-Boot 2023.07-rc2-00004-g1befbe31c1 (May 23 2023 - 18:40:01 +0800)
+
+        CPU:   rv64imafdc
+        Model: Sipeed Lichee Pi 4A
+        DRAM:  8 GiB
+        Core:  13 devices, 6 uclasses, devicetree: separate
+        Loading Environment from <NULL>... OK
+        In:    serial@ffe7014000
+        Out:   serial@ffe7014000
+        Err:   serial@ffe7014000
+        Model: Sipeed Lichee Pi 4A
+        LPI4A=>
diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst
index ee4faec37c..3332d51b36 100644
--- a/doc/board/ti/am335x_evm.rst
+++ b/doc/board/ti/am335x_evm.rst
@@ -201,3 +201,65 @@ booting and mtdparts have been configured correctly for the board:
 	U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
 	U-Boot # nand erase.part u-boot-spl-os
 	U-Boot # nand write ${fdtaddr} u-boot-spl-os
+
+USB device
+----------
+
+The platform code for am33xx based designs is legacy in the sense that
+it is not fully compliant with the driver model in its management of the
+various resources. This is particularly true for the USB Ethernet gadget
+which will automatically be bound to the first USB Device Controller
+(UDC). This make the USB Ethernet gadget work out of the box on common
+boards like the Beagle Bone Blacks and by default will prevents other
+gadgets to be used.
+
+The output of the 'dm tree' command shows which driver is bound to which
+device, so the user can easily configure their platform differently from
+the command line:
+
+.. code-block:: text
+
+	=> dm tree
+	 Class     Index  Probed  Driver                Name
+	-----------------------------------------------------------
+	[...]
+	misc          0  [ + ]   ti-musb-wrapper       |   |-- usb@47400000
+	usb           0  [ + ]   ti-musb-peripheral    |   |   |-- usb@47401000
+	ethernet      1  [ + ]   usb_ether             |   |   |   `-- usb_ether
+	bootdev       3  [   ]   eth_bootdev           |   |   |       `-- usb_ether.bootdev
+	usb           0  [   ]   ti-musb-host          |   |   `-- usb@47401800
+
+Typically here any network command performed using the usb_ether
+interface would work, while using other gadgets would fail:
+
+.. code-block:: text
+
+	=> fastboot usb 0
+	All UDC in use (1 available), use the unbind command
+	g_dnl_register: failed!, error: -19
+	exit not allowed from main input shell.
+
+As hinted by the primary error message, the only controller available
+(usb@47401000) is currently bound to the usb_ether driver, which makes
+it impossible for the fastboot command to bind with this device (at
+least from a bootloader point of view). The solution here would be to
+use the unbind command specifying the class and index parameters (as
+shown above in the 'dm tree' output) to target the driver to unbind:
+
+.. code-block:: text
+
+	=> unbind ethernet 1
+
+The output of the 'dm tree' command now shows the availability of the
+first USB device controller, the fastboot gadget will now be able to
+bind with it:
+
+.. code-block:: text
+
+	=> dm tree
+	 Class     Index  Probed  Driver                Name
+	-----------------------------------------------------------
+	[...]
+	misc          0  [ + ]   ti-musb-wrapper       |   |-- usb@47400000
+	usb           0  [   ]   ti-musb-peripheral    |   |   |-- usb@47401000
+	usb           0  [   ]   ti-musb-host          |   |   `-- usb@47401800
diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index 27d7b527c6..5ed17c0a3a 100644
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -38,197 +38,173 @@ Some highlights of this SoC are:
 More details can be found in the Technical Reference Manual:
 https://www.ti.com/lit/pdf/spruiv7
 
+Platform information:
+
+* https://www.ti.com/tool/SK-AM62B
+
 Boot Flow:
 ----------
 Below is the pictorial representation of boot flow:
 
-.. code-block:: text
-
- +------------------------------------------------------------------------+
- |        TIFS            |      Main R5          |        A53            |
- +------------------------------------------------------------------------+
- |    +--------+          |                       |                       |
- |    |  Reset |          |                       |                       |
- |    +--------+          |                       |                       |
- |         :              |                       |                       |
- |    +--------+          |   +-----------+       |                       |
- |    | *ROM*  |----------|-->| Reset rls |       |                       |
- |    +--------+          |   +-----------+       |                       |
- |    |        |          |         :             |                       |
- |    |  ROM   |          |         :             |                       |
- |    |services|          |         :             |                       |
- |    |        |          |   +-------------+     |                       |
- |    |        |          |   |  *R5 ROM*   |     |                       |
- |    |        |          |   +-------------+     |                       |
- |    |        |<---------|---|Load and auth|     |                       |
- |    |        |          |   | tiboot3.bin |     |                       |
- |    +--------+          |   +-------------+     |                       |
- |    |        |<---------|---| Load sysfw  |     |                       |
- |    |        |          |   | part to TIFS|     |                       |
- |    |        |          |   | core        |     |                       |
- |    |        |          |   +-------------+     |                       |
- |    |        |          |         :             |                       |
- |    |        |          |         :             |                       |
- |    |        |          |         :             |                       |
- |    |        |          |   +-------------+     |                       |
- |    |        |          |   |  *R5 SPL*   |     |                       |
- |    |        |          |   +-------------+     |                       |
- |    |        |          |   |    DDR      |     |                       |
- |    |        |          |   |   config    |     |                       |
- |    |        |          |   +-------------+     |                       |
- |    |        |          |   |    Load     |     |                       |
- |    |        |          |   |  tispl.bin  |     |                       |
- |    |        |          |   +-------------+     |                       |
- |    |        |          |   |   Load R5   |     |                       |
- |    |        |          |   |   firmware  |     |                       |
- |    |        |          |   +-------------+     |                       |
- |    |        |<---------|---| Start A53   |     |                       |
- |    |        |          |   | and jump to |     |                       |
- |    |        |          |   | DM fw image |     |                       |
- |    |        |          |   +-------------+     |                       |
- |    |        |          |                       |     +-----------+     |
- |    |        |----------|-----------------------|---->| Reset rls |     |
- |    |        |          |                       |     +-----------+     |
- |    |  TIFS  |          |                       |          :            |
- |    |Services|          |                       |     +-----------+     |
- |    |        |<---------|-----------------------|---->|*ATF/OPTEE*|     |
- |    |        |          |                       |     +-----------+     |
- |    |        |          |                       |          :            |
- |    |        |          |                       |     +-----------+     |
- |    |        |<---------|-----------------------|---->| *A53 SPL* |     |
- |    |        |          |                       |     +-----------+     |
- |    |        |          |                       |     |   Load    |     |
- |    |        |          |                       |     | u-boot.img|     |
- |    |        |          |                       |     +-----------+     |
- |    |        |          |                       |          :            |
- |    |        |          |                       |     +-----------+     |
- |    |        |<---------|-----------------------|---->| *U-Boot*  |     |
- |    |        |          |                       |     +-----------+     |
- |    |        |          |                       |     |  prompt   |     |
- |    |        |----------|-----------------------|-----+-----------+-----|
- |    +--------+          |                       |                       |
- |                        |                       |                       |
- +------------------------------------------------------------------------+
+.. image:: img/boot_diagram_k3_current.svg
 
 - Here TIFS acts as master and provides all the critical services. R5/A53
   requests TIFS to get these services done as shown in the above diagram.
 
 Sources:
 --------
-1. SYSFW:
-	Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git
-	Branch: master
 
-2. ATF:
-	Tree: https://github.com/ARM-software/arm-trusted-firmware.git
-	Branch: master
+.. include::  ../ti/k3.rst
+    :start-after: .. k3_rst_include_start_boot_sources
+    :end-before: .. k3_rst_include_end_boot_sources
 
-3. OPTEE:
-	Tree: https://github.com/OP-TEE/optee_os.git
-	Branch: master
+Build procedure:
+----------------
+0. Setup the environment variables:
 
-4. U-Boot:
-	Tree: https://source.denx.de/u-boot/u-boot
-	Branch: master
+.. include::  ../ti/k3.rst
+    :start-after: .. k3_rst_include_start_common_env_vars_desc
+    :end-before: .. k3_rst_include_end_common_env_vars_desc
 
-5. TI Linux Firmware:
-	Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git
-	Branch: ti-linux-firmware
+.. include::  ../ti/k3.rst
+    :start-after: .. k3_rst_include_start_board_env_vars_desc
+    :end-before: .. k3_rst_include_end_board_env_vars_desc
 
-Build procedure:
-----------------
-1. ATF:
+Set the variables corresponding to this platform:
 
-.. code-block:: text
+.. include::  ../ti/k3.rst
+    :start-after: .. k3_rst_include_start_common_env_vars_defn
+    :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
 
- $ make CROSS_COMPILE=aarch64-none-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=lite SPD=opteed
+ $ export UBOOT_CFG_CORTEXR=am62x_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=am62x_evm_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am62x
+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
 
-2. OPTEE:
+.. am62x_evm_rst_include_start_build_steps
 
-.. code-block:: text
+1. Trusted Firmware-A:
 
- $ make PLATFORM=k3 CFG_ARM64_core=y CROSS_COMPILE=arm-none-linux-gnueabihf- CROSS_COMPILE64=aarch64-none-linux-gnu-
+.. include::  ../ti/k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_tfa
+    :end-before: .. k3_rst_include_end_build_steps_tfa
 
-3. U-Boot:
 
-* 3.1 R5:
+2. OP-TEE:
 
-.. code-block:: text
+.. include::  ../ti/k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_optee
+    :end-before: .. k3_rst_include_end_build_steps_optee
 
- $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- am62x_evm_r5_defconfig O=/tmp/r5
- $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- O=/tmp/r5
- $ cd <k3-image-gen>
- $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=am62x SBL=/tmp/r5/spl/u-boot-spl.bin SYSFW_PATH=<path to ti-linux-firmware>/ti-sysfw/ti-fs-firmware-am62x-gp.bin
+3. U-Boot:
 
-Use the tiboot3.bin generated from last command
+* 4.1 R5:
 
-* 3.2 A53:
+.. include::  ../ti/k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_spl_r5
+    :end-before: .. k3_rst_include_end_build_steps_spl_r5
 
-.. code-block:: text
+* 4.2 A53:
 
- $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- am62x_evm_a53_defconfig O=/tmp/a53
- $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- ATF=<path to ATF dir>/build/k3/lite/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=<path to ti-linux-firmware>/ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f O=/tmp/a53
+.. include::  ../ti/k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_uboot
+    :end-before: .. k3_rst_include_end_build_steps_uboot
+.. am62x_evm_rst_include_end_build_steps
 
 Target Images
 --------------
-Copy the below images to an SD card and boot:
- - tiboot3.bin from step 3.1
- - tispl.bin, u-boot.img from 3.2
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img.  Each SoC
+variant (GP, HS-FS, HS-SE) requires a different source for these files.
+
+ - GP
+
+        * tiboot3-am62x-gp-evm.bin from step 3.1
+        * tispl.bin_unsigned, u-boot.img_unsigned from step 3.2
+
+ - HS-FS
+
+        * tiboot3-am62x-hs-fs-evm.bin from step 3.1
+        * tispl.bin, u-boot.img from step 3.2
+
+ - HS-SE
+
+        * tiboot3-am62x-hs-evm.bin from step 3.1
+        * tispl.bin, u-boot.img from step 3.2
 
 Image formats:
 --------------
 
-- tiboot3.bin:
-
-.. code-block:: text
-
-                +-----------------------+
-                |        X.509          |
-                |      Certificate      |
-                | +-------------------+ |
-                | |                   | |
-                | |        R5         | |
-                | |   u-boot-spl.bin  | |
-                | |                   | |
-                | +-------------------+ |
-                | |                   | |
-                | |TIFS with board cfg| |
-                | |                   | |
-                | +-------------------+ |
-                | |                   | |
-                | |                   | |
-                | |     FIT header    | |
-                | | +---------------+ | |
-                | | |               | | |
-                | | |   DTB 1...N   | | |
-                | | +---------------+ | |
-                | +-------------------+ |
-                +-----------------------+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
 
 - tispl.bin
 
-.. code-block:: text
-
-                +-----------------------+
-                |                       |
-                |       FIT HEADER      |
-                | +-------------------+ |
-                | |                   | |
-                | |      A53 ATF      | |
-                | +-------------------+ |
-                | |                   | |
-                | |     A53 OPTEE     | |
-                | +-------------------+ |
-                | |                   | |
-                | |      R5 DM FW     | |
-                | +-------------------+ |
-                | |                   | |
-                | |      A53 SPL      | |
-                | +-------------------+ |
-                | |                   | |
-                | |   SPL DTB 1...N   | |
-                | +-------------------+ |
-                +-----------------------+
+.. image:: img/dm_tispl.bin.svg
+
+A53 SPL DDR Memory Layout
+-------------------------
+
+.. am62x_evm_rst_include_start_ddr_mem_layout
+
+This provides an overview memory usage in A53 SPL stage.
+
+.. list-table::
+   :widths: 16 16 16
+   :header-rows: 1
+
+   * - Region
+     - Start Address
+     - End Address
+
+   * - EMPTY
+     - 0x80000000
+     - 0x80080000
+
+   * - TEXT BASE
+     - 0x80080000
+     - 0x800d8000
+
+   * - EMPTY
+     - 0x800d8000
+     - 0x80200000
+
+   * - BMP IMAGE
+     - 0x80200000
+     - 0x80b77660
+
+   * - STACK
+     - 0x80b77660
+     - 0x80b77e60
+
+   * - GD
+     - 0x80b77e60
+     - 0x80b78000
+
+   * - MALLOC
+     - 0x80b78000
+     - 0x80b80000
+
+   * - EMPTY
+     - 0x80b80000
+     - 0x80c80000
+
+   * - BSS
+     - 0x80c80000
+     - 0x80d00000
+
+   * - BLOBS
+     - 0x80d00000
+     - 0x80d00400
+
+   * - EMPTY
+     - 0x80d00400
+     - 0x81000000
+.. am62x_evm_rst_include_end_ddr_mem_layout
 
 Switch Setting for Boot Mode
 ----------------------------
@@ -241,16 +217,56 @@ The following table shows some common boot modes used on AM62 platform. More
 details can be found in the Technical Reference Manual:
 https://www.ti.com/lit/pdf/spruiv7 under the `Boot Mode Pins` section.
 
-*Boot Modes*
+.. list-table:: Boot Modes
+   :widths: 16 16 16
+   :header-rows: 1
+
+   * - Switch Label
+     - SW2: 12345678
+     - SW3: 12345678
+
+   * - SD
+     - 01000000
+     - 11000010
+
+   * - OSPI
+     - 00000000
+     - 11001110
+
+   * - EMMC
+     - 00000000
+     - 11010010
 
-============ ============= =============
-Switch Label SW2: 12345678 SW3: 12345678
-============ ============= =============
-SD           01000000      11000010
-OSPI         00000000      11001110
-EMMC         00000000      11010010
-UART         00000000      11011100
-USB DFU      00000000      11001010
-============ ============= =============
+   * - UART
+     - 00000000
+     - 11011100
+
+   * - USB DFU
+     - 00000000
+     - 11001010
 
 For SW2 and SW1, the switch state in the "ON" position = 1.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+  **OpenOCD support since**: v0.12.0
+
+  If the default package version of OpenOCD in your development
+  environment's distribution needs to be updated, it might be necessary to
+  build OpenOCD from the source.
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+    :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. code-block:: bash
+
+  openocd -f board/ti_am625evm.cfg
diff --git a/doc/board/ti/am65x_evm.rst b/doc/board/ti/am65x_evm.rst
new file mode 100644
index 0000000000..5f3c46cf9f
--- /dev/null
+++ b/doc/board/ti/am65x_evm.rst
@@ -0,0 +1,313 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Neha Francis <n-francis@ti.com>
+
+AM65x Platforms
+===============
+
+Introduction:
+-------------
+The AM65x family of SoCs is the first device family from K3 Multicore
+SoC architecture, targeted for broad market and industrial control with
+aim to meet the complex processing needs of modern embedded products.
+
+The device is built over three domains, each containing specific processing
+cores, voltage domains and peripherals:
+
+1. Wake-up (WKUP) domain:
+        * Device Management and Security Controller (DMSC)
+
+2. Microcontroller (MCU) domain:
+        * Dual Core ARM Cortex-R5F processor
+
+3. MAIN domain:
+        * Quad core 64-bit ARM Cortex-A53
+
+More info can be found in TRM: http://www.ti.com/lit/pdf/spruid7
+
+Platform information:
+
+* https://www.ti.com/tool/TMDX654GPEVM
+
+Boot Flow:
+----------
+On AM65x family devices, ROM supports boot only via MCU(R5). This means that
+bootloader has to run on R5 core. In order to meet this constraint, and for
+the following reasons the boot flow is designed as mentioned:
+
+1. Need to move away from R5 asap, so that we want to start *any*
+firmware on the R5 cores for example autosar can be loaded to receive CAN
+response and other safety operations to be started. This operation is
+very time critical and is applicable for all automotive use cases.
+
+2. U-Boot on A53 should start other remotecores for various
+applications. This should happen before running Linux.
+
+3. In production boot flow, we might not like to use full U-Boot,
+instead use Falcon boot flow to reduce boot time.
+
+.. image:: img/boot_diagram_am65.svg
+
+- Here DMSC acts as master and provides all the critical services. R5/A53
+  requests DMSC to get these services done as shown in the above diagram.
+
+Sources:
+--------
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_boot_sources
+    :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_common_env_vars_desc
+    :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_board_env_vars_desc
+    :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_common_env_vars_defn
+    :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=am65x_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=am65x_evm_a53_defconfig
+ $ export TFA_BOARD=generic
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am65x
+ $ # we dont use any extra OP-TEE parameters
+ $ unset OPTEE_EXTRA_ARGS
+
+.. am65x_evm_rst_include_start_build_steps
+
+1. Trusted Firmware-A:
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_tfa
+    :end-before: .. k3_rst_include_end_build_steps_tfa
+
+
+2. OP-TEE:
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_optee
+    :end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+* 4.1 R5:
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_spl_r5
+    :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* 4.2 A53:
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_uboot
+    :end-before: .. k3_rst_include_end_build_steps_uboot
+.. am65x_evm_rst_include_end_build_steps
+
+Target Images
+--------------
+In order to boot we need tiboot3.bin, sysfw.itb, tispl.bin and u-boot.img.
+Each SoC variant (GP and HS) requires a different source for these files.
+
+- GP
+
+        * tiboot3-am65x_sr2-gp-evm.bin, sysfw-am65x_sr2-gp-evm.itb from step 4.1
+        * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2
+
+- HS
+
+        * tiboot3-am65x_sr2-hs-evm.bin, sysfw-am65x_sr2-hs-evm.itb from step 4.1
+        * tispl.bin, u-boot.img from step 4.2
+
+Image formats:
+--------------
+
+- tiboot3.bin
+
+.. image:: img/no_multi_cert_tiboot3.bin.svg
+
+- tispl.bin
+
+.. image:: img/nodm_tispl.bin.svg
+
+- sysfw.itb
+
+.. image:: img/sysfw.itb.svg
+
+eMMC:
+-----
+ROM supports booting from eMMC from boot0 partition offset 0x0
+
+Flashing images to eMMC:
+
+The following commands can be used to download tiboot3.bin, tispl.bin,
+u-boot.img, and sysfw.itb from an SD card and write them to the eMMC boot0
+partition at respective addresses.
+
+.. code-block:: text
+
+ => mmc dev 0 1
+ => fatload mmc 1 ${loadaddr} tiboot3.bin
+ => mmc write ${loadaddr} 0x0 0x400
+ => fatload mmc 1 ${loadaddr} tispl.bin
+ => mmc write ${loadaddr} 0x400 0x1000
+ => fatload mmc 1 ${loadaddr} u-boot.img
+ => mmc write ${loadaddr} 0x1400 0x2000
+ => fatload mmc 1 ${loadaddr} sysfw.itb
+ => mmc write ${loadaddr} 0x3600 0x800
+
+To give the ROM access to the boot partition, the following commands must be
+used for the first time:
+
+.. code-block:: text
+
+ => mmc partconf 0 1 1 1
+ => mmc bootbus 0 1 0 0
+
+To create a software partition for the rootfs, the following command can be
+used:
+
+.. code-block:: text
+
+ => gpt write mmc 0 ${partitions}
+
+eMMC layout:
+
+.. image:: img/emmc_am65x_evm_boot0.svg
+
+Kernel image and DT are expected to be present in the /boot folder of rootfs.
+To boot kernel from eMMC, use the following commands:
+
+.. code-block:: text
+
+ => setenv mmcdev 0
+ => setenv bootpart 0
+ => boot
+
+OSPI:
+-----
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
+and sysfw.itb over tftp and then flash those to OSPI at their respective
+addresses.
+
+.. code-block:: text
+
+ => sf probe
+ => tftp ${loadaddr} tiboot3.bin
+ => sf update $loadaddr 0x0 $filesize
+ => tftp ${loadaddr} tispl.bin
+ => sf update $loadaddr 0x80000 $filesize
+ => tftp ${loadaddr} u-boot.img
+ => sf update $loadaddr 0x280000 $filesize
+ => tftp ${loadaddr} sysfw.itb
+ => sf update $loadaddr 0x6C0000 $filesize
+
+Flash layout for OSPI:
+
+.. image:: img/ospi_sysfw.svg
+
+Kernel Image and DT are expected to be present in the /boot folder of UBIFS
+ospi.rootfs just like in SD card case. U-Boot looks for UBI volume named
+"rootfs" for rootfs.
+
+To boot kernel from OSPI, at the U-Boot prompt:
+
+.. code-block:: text
+
+ => setenv boot ubi
+ => boot
+
+UART:
+-----
+ROM supports booting from MCU_UART0 via X-Modem protocol. The entire UART-based
+boot process up to U-Boot (proper) prompt goes through different stages and uses
+different UART peripherals as follows:
+
+.. list-table:: ROM UART Boot Responsibilities
+   :widths: 16 16 16 16
+   :header-rows: 1
+
+   * - Who
+     - Loading What
+     - Hardware Module
+     - Protocol
+
+   * - Boot ROM
+     - tiboot3.bin
+     - MCU_UART0
+     - X-Modem(*)
+
+   * - R5 SPL
+     - sysfw.itb
+     - MCU_UART0
+     - Y-Modem(*)
+
+   * - R5 SPL
+     - tispl.bin
+     - MAIN_UART0
+     - Y-Modem
+
+   * - A53 SPL
+     - u-boot.img
+     - MAIN_UART0
+     - Y-Modem
+
+Note that in addition to X/Y-Modem related protocol timeouts the DMSC
+watchdog timeout of 3min (typ.) needs to be observed until System Firmware
+is fully loaded (from sysfw.itb) and started.
+
+Example bash script sequence for running on a Linux host PC feeding all boot
+artifacts needed to the device:
+
+.. code-block:: text
+
+ MCU_DEV=/dev/ttyUSB1
+ MAIN_DEV=/dev/ttyUSB0
+
+ stty -F $MCU_DEV 115200 cs8 -cstopb -parenb
+ stty -F $MAIN_DEV 115200 cs8 -cstopb -parenb
+
+ sb --xmodem tiboot3.bin > $MCU_DEV < $MCU_DEV
+ sb --ymodem sysfw.itb > $MCU_DEV < $MCU_DEV
+ sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV
+ sleep 1
+ sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+  **OpenOCD support since**: v0.12.0
+
+  If the default package version of OpenOCD in your development
+  environment's distribution needs to be updated, it might be necessary to
+  build OpenOCD from the source.
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+    :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. code-block:: bash
+
+  openocd -f board/ti_am654evm.cfg
diff --git a/doc/board/ti/img/boot_diagram_am65.svg b/doc/board/ti/img/boot_diagram_am65.svg
new file mode 100644
index 0000000000..79c65e115f
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+             style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 153px; height: 1px; padding-top: 90px; margin-left: 41px;">
+            <xhtml:div
+               data-drawio-colors="color: rgb(0, 0, 0); "
+               style="box-sizing: border-box; font-size: 0px; text-align: center;">
+              <xhtml:div
+                 style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">sysfw.bin</xhtml:div>
+            </xhtml:div>
+          </xhtml:div>
+        </foreignObject>
+        <text
+           x="118"
+           y="94"
+           fill="rgb(0, 0, 0)"
+           font-family="Helvetica"
+           font-size="12px"
+           text-anchor="middle"
+           id="text885">sysfw.bin</text>
+      </switch>
+    </g>
+    <rect
+       x="40"
+       y="110"
+       width="155"
+       height="40"
+       fill="none"
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+       transform="translate(-0.5 -0.5)"
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+           width="100%"
+           height="100%"
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+               data-drawio-colors="color: rgb(0, 0, 0); "
+               style="box-sizing: border-box; font-size: 0px; text-align: center;">
+              <xhtml:div
+                 style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">board config</xhtml:div>
+            </xhtml:div>
+          </xhtml:div>
+        </foreignObject>
+        <text
+           x="118"
+           y="134"
+           fill="rgb(0, 0, 0)"
+           font-family="Helvetica"
+           font-size="12px"
+           text-anchor="middle"
+           id="text893">board config</text>
+      </switch>
+    </g>
+    <rect
+       x="40"
+       y="150"
+       width="155"
+       height="40"
+       fill="none"
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+       id="rect899" />
+    <g
+       transform="translate(-0.5 -0.5)"
+       id="g905">
+      <switch
+         id="switch903">
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+           pointer-events="none"
+           width="100%"
+           height="100%"
+           requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
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+          <xhtml:div
+             style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 153px; height: 1px; padding-top: 170px; margin-left: 41px;">
+            <xhtml:div
+               data-drawio-colors="color: rgb(0, 0, 0); "
+               style="box-sizing: border-box; font-size: 0px; text-align: center;">
+              <xhtml:div
+                 style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">PM config</xhtml:div>
+            </xhtml:div>
+          </xhtml:div>
+        </foreignObject>
+        <text
+           x="118"
+           y="174"
+           fill="rgb(0, 0, 0)"
+           font-family="Helvetica"
+           font-size="12px"
+           text-anchor="middle"
+           id="text901">PM config</text>
+      </switch>
+    </g>
+    <rect
+       x="40"
+       y="190"
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+    <g
+       transform="translate(-0.5 -0.5)"
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+           height="100%"
+           requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
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+          <xhtml:div
+             style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 153px; height: 1px; padding-top: 210px; margin-left: 41px;">
+            <xhtml:div
+               data-drawio-colors="color: rgb(0, 0, 0); "
+               style="box-sizing: border-box; font-size: 0px; text-align: center;">
+              <xhtml:div
+                 style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">RM config</xhtml:div>
+            </xhtml:div>
+          </xhtml:div>
+        </foreignObject>
+        <text
+           x="118"
+           y="214"
+           fill="rgb(0, 0, 0)"
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+    <g
+       transform="translate(-0.5 -0.5)"
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+      <switch
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+        <foreignObject
+           pointer-events="none"
+           width="100%"
+           height="100%"
+           requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+           style="overflow: visible; text-align: left;">
+          <xhtml:div
+             style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 153px; height: 1px; padding-top: 250px; margin-left: 41px;">
+            <xhtml:div
+               data-drawio-colors="color: rgb(0, 0, 0); "
+               style="box-sizing: border-box; font-size: 0px; text-align: center;">
+              <xhtml:div
+                 style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Secure config</xhtml:div>
+            </xhtml:div>
+          </xhtml:div>
+        </foreignObject>
+        <text
+           x="118"
+           y="254"
+           fill="rgb(0, 0, 0)"
+           font-family="Helvetica"
+           font-size="12px"
+           text-anchor="middle"
+           id="text917">Secure config</text>
+      </switch>
+    </g>
+  </g>
+  <switch
+     id="switch931">
+    <g
+       requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+       id="g925" />
+    <a
+       transform="translate(0,-5)"
+       xlink:href="https://www.diagrams.net/doc/faq/svg-export-text-problems"
+       target="_blank"
+       id="a929">
+      <text
+         text-anchor="middle"
+         font-size="10px"
+         x="50%"
+         y="100%"
+         id="text927">Text is not SVG - cannot display</text>
+    </a>
+  </switch>
+</svg>
diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst
new file mode 100644
index 0000000000..2e60e22ba1
--- /dev/null
+++ b/doc/board/ti/j7200_evm.rst
@@ -0,0 +1,227 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Udit Kumar <u-kumar1@ti.com>
+
+J7200 Platforms
+===============
+
+Introduction:
+-------------
+The J7200 family of SoCs are part of K3 Multicore SoC architecture platform
+targeting automotive applications. They are designed as a low power, high
+performance and highly integrated device architecture, adding significant
+enhancement on processing power, graphics capability, video and imaging
+processing, virtualization and coherent memory support.
+
+The device is partitioned into three functional domains, each containing
+specific processing cores and peripherals:
+
+1. Wake-up (WKUP) domain:
+        * Device Management and Security Controller (DMSC)
+
+2. Microcontroller (MCU) domain:
+        * Dual Core ARM Cortex-R5F processor
+
+3. MAIN domain:
+        * Dual core 64-bit ARM Cortex-A72
+
+More info can be found in TRM: https://www.ti.com/lit/pdf/spruiu1
+
+Platform information:
+
+* https://www.ti.com/tool/J7200XSOMXEVM
+
+Boot Flow:
+----------
+Below is the pictorial representation of boot flow:
+
+.. image:: img/boot_diagram_k3_current.svg
+
+- Here DMSC acts as master and provides all the critical services. R5/A72
+  requests DMSC to get these services done as shown in the above diagram.
+
+Sources:
+--------
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_boot_sources
+    :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_common_env_vars_desc
+    :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_board_env_vars_desc
+    :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_common_env_vars_defn
+    :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=j7200_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=j7200_evm_a72_defconfig
+ $ export TFA_BOARD=generic
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-j7200
+ $ # we dont use any extra OP-TEE parameters
+ $ unset OPTEE_EXTRA_ARGS
+
+.. j7200_evm_rst_include_start_build_steps
+
+1. Trusted Firmware-A:
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_tfa
+    :end-before: .. k3_rst_include_end_build_steps_tfa
+
+
+2. OP-TEE:
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_optee
+    :end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+* 4.1 R5:
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_spl_r5
+    :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* 4.2 A72:
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_uboot
+    :end-before: .. k3_rst_include_end_build_steps_uboot
+.. j7200_evm_rst_include_end_build_steps
+
+Target Images
+--------------
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
+variant (GP, HS-FS, HS-SE) requires a different source for these files.
+
+ - GP
+
+        * tiboot3-j7200-gp-evm.bin from step 4.1
+        * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2
+
+ - HS-FS
+
+        * tiboot3-j7200_sr2-hs-fs-evm.bin from step 4.1
+        * tispl.bin, u-boot.img from step 4.2
+
+ - HS-SE
+
+        * tiboot3-j7200_sr2-hs-evm.bin from step 4.1
+        * tispl.bin, u-boot.img from step 4.2
+
+Image formats:
+--------------
+
+- tiboot3.bin
+
+.. image:: img/j7200_tiboot3.bin.svg
+
+- tispl.bin
+
+.. image:: img/dm_tispl.bin.svg
+
+
+
+Switch Setting for Boot Mode
+----------------------------
+
+Boot Mode pins provide means to select the boot mode and options before the
+device is powered up. After every POR, they are the main source to populate
+the Boot Parameter Tables.
+
+The following table shows some common boot modes used on J7200 platform. More
+details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruiu1 under the `Boot Mode Pins` section.
+
+.. list-table:: Boot Modes
+   :widths: 16 16 16
+   :header-rows: 1
+
+   * - Switch Label
+     - SW9: 12345678
+     - SW8: 12345678
+
+   * - SD
+     - 00000000
+     - 10000010
+
+   * - EMMC
+     - 01000000
+     - 10000000
+
+   * - OSPI
+     - 01000000
+     - 00000110
+
+   * - UART
+     - 01110000
+     - 00000000
+
+   * - USB DFU
+     - 00100000
+     - 10000000
+
+For SW8 and SW9, the switch state in the "ON" position = 1.
+
+eMMC:
+-----
+ROM supports booting from eMMC raw read or UDA FS mode.
+
+Below is memory layout in case of booting from
+boot 0/1  partition in raw mode.
+
+Current allocated size for tiboot3 size is 1MB, tispl is 2MB.
+
+Size of u-boot.img is taken 4MB for refernece,
+But this is subject to change depending upon atf, optee size
+
+.. image:: img/emmc_j7200_evm_boot01.svg
+
+In case of UDA FS mode booting, following is layout.
+
+All boot images tiboot3.bin, tispl and u-boot should be written to
+fat formatted UDA FS as file.
+
+.. image:: img/emmc_j7200_evm_udafs.svg
+
+In case of booting from eMMC, write above images into raw or UDA FS.
+and set mmc partconf accordingly.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+  **OpenOCD support since**: v0.12.0
+
+  If the default package version of OpenOCD in your development
+  environment's distribution needs to be updated, it might be necessary to
+  build OpenOCD from the source.
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+    :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. code-block:: bash
+
+  openocd -f board/ti_j7200evm.cfg
diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst
index feaa2da5e9..d2a214fb33 100644
--- a/doc/board/ti/j721e_evm.rst
+++ b/doc/board/ti/j721e_evm.rst
@@ -29,244 +29,121 @@ specific processing cores and peripherals:
 
 More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1
 
+Platform information:
+
+* https://www.ti.com/tool/J721EXSOMXEVM
+* https://www.ti.com/tool/SK-TDA4VM
+
 Boot Flow:
 ----------
 Boot flow is similar to that of AM65x SoC and extending it with remoteproc
 support. Below is the pictorial representation of boot flow:
 
-.. code-block:: text
-
- +------------------------------------------------------------------------+-----------------------+
- |        DMSC            |      MCU R5           |        A72            |  MAIN R5/C66x/C7x     |
- +------------------------------------------------------------------------+-----------------------+
- |    +--------+          |                       |                       |                       |
- |    |  Reset |          |                       |                       |                       |
- |    +--------+          |                       |                       |                       |
- |         :              |                       |                       |                       |
- |    +--------+          |   +-----------+       |                       |                       |
- |    | *ROM*  |----------|-->| Reset rls |       |                       |                       |
- |    +--------+          |   +-----------+       |                       |                       |
- |    |        |          |         :             |                       |                       |
- |    |  ROM   |          |         :             |                       |                       |
- |    |services|          |         :             |                       |                       |
- |    |        |          |   +-------------+     |                       |                       |
- |    |        |          |   |  *R5 ROM*   |     |                       |                       |
- |    |        |          |   +-------------+     |                       |                       |
- |    |        |<---------|---|Load and auth|     |                       |                       |
- |    |        |          |   | tiboot3.bin |     |                       |                       |
- |    |        |          |   +-------------+     |                       |                       |
- |    |        |          |         :             |                       |                       |
- |    |        |          |         :             |                       |                       |
- |    |        |          |         :             |                       |                       |
- |    |        |          |   +-------------+     |                       |                       |
- |    |        |          |   |  *R5 SPL*   |     |                       |                       |
- |    |        |          |   +-------------+     |                       |                       |
- |    |        |          |   |    Load     |     |                       |                       |
- |    |        |          |   |  sysfw.itb  |     |                       |                       |
- |    | Start  |          |   +-------------+     |                       |                       |
- |    | System |<---------|---|    Start    |     |                       |                       |
- |    |Firmware|          |   |    SYSFW    |     |                       |                       |
- |    +--------+          |   +-------------+     |                       |                       |
- |        :               |   |             |     |                       |                       |
- |    +---------+         |   |   Load      |     |                       |                       |
- |    | *SYSFW* |         |   |   system    |     |                       |                       |
- |    +---------+         |   | Config data |     |                       |                       |
- |    |         |<--------|---|             |     |                       |                       |
- |    |         |         |   +-------------+     |                       |                       |
- |    |         |         |   |    DDR      |     |                       |                       |
- |    |         |         |   |   config    |     |                       |                       |
- |    |         |         |   +-------------+     |                       |                       |
- |    |         |         |   |    Load     |     |                       |                       |
- |    |         |         |   |  tispl.bin  |     |                       |                       |
- |    |         |         |   +-------------+     |                       |                       |
- |    |         |         |   |   Load R5   |     |                       |                       |
- |    |         |         |   |   firmware  |     |                       |                       |
- |    |         |         |   +-------------+     |                       |                       |
- |    |         |<--------|---| Start A72   |     |                       |                       |
- |    |         |         |   | and jump to |     |                       |                       |
- |    |         |         |   | DM fw image |     |                       |                       |
- |    |         |         |   +-------------+     |                       |                       |
- |    |         |         |                       |     +-----------+     |                       |
- |    |         |---------|-----------------------|---->| Reset rls |     |                       |
- |    |         |         |                       |     +-----------+     |                       |
- |    |  TIFS   |         |                       |          :            |                       |
- |    |Services |         |                       |     +-----------+     |                       |
- |    |         |<--------|-----------------------|---->|*ATF/OPTEE*|     |                       |
- |    |         |         |                       |     +-----------+     |                       |
- |    |         |         |                       |          :            |                       |
- |    |         |         |                       |     +-----------+     |                       |
- |    |         |<--------|-----------------------|---->| *A72 SPL* |     |                       |
- |    |         |         |                       |     +-----------+     |                       |
- |    |         |         |                       |     |   Load    |     |                       |
- |    |         |         |                       |     | u-boot.img|     |                       |
- |    |         |         |                       |     +-----------+     |                       |
- |    |         |         |                       |          :            |                       |
- |    |         |         |                       |     +-----------+     |                       |
- |    |         |<--------|-----------------------|---->| *U-Boot*  |     |                       |
- |    |         |         |                       |     +-----------+     |                       |
- |    |         |         |                       |     |  prompt   |     |                       |
- |    |         |         |                       |     +-----------+     |                       |
- |    |         |         |                       |     |  Load R5  |     |                       |
- |    |         |         |                       |     |  Firmware |     |                       |
- |    |         |         |                       |     +-----------+     |                       |
- |    |         |<--------|-----------------------|-----|  Start R5 |     |      +-----------+    |
- |    |         |---------|-----------------------|-----+-----------+-----|----->| R5 starts |    |
- |    |         |         |                       |     |  Load C6  |     |      +-----------+    |
- |    |         |         |                       |     |  Firmware |     |                       |
- |    |         |         |                       |     +-----------+     |                       |
- |    |         |<--------|-----------------------|-----|  Start C6 |     |      +-----------+    |
- |    |         |---------|-----------------------|-----+-----------+-----|----->| C6 starts |    |
- |    |         |         |                       |     |  Load C7  |     |      +-----------+    |
- |    |         |         |                       |     |  Firmware |     |                       |
- |    |         |         |                       |     +-----------+     |                       |
- |    |         |<--------|-----------------------|-----|  Start C7 |     |      +-----------+    |
- |    |         |---------|-----------------------|-----+-----------+-----|----->| C7 starts |    |
- |    +---------+         |                       |                       |      +-----------+    |
- |                        |                       |                       |                       |
- +------------------------------------------------------------------------+-----------------------+
+.. image:: img/boot_diagram_j721e.svg
 
 - Here DMSC acts as master and provides all the critical services. R5/A72
   requests DMSC to get these services done as shown in the above diagram.
 
 Sources:
 --------
-1. SYSFW:
-	Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git
-	Branch: master
 
-2. ATF:
-	Tree: https://github.com/ARM-software/arm-trusted-firmware.git
-	Branch: master
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_boot_sources
+    :end-before: .. k3_rst_include_end_boot_sources
 
-3. OPTEE:
-	Tree: https://github.com/OP-TEE/optee_os.git
-	Branch: master
+Build procedure:
+----------------
+0. Setup the environment variables:
 
-4. DM Firmware:
-	Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git
-	Branch: ti-linux-firmware
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_common_env_vars_desc
+    :end-before: .. k3_rst_include_end_common_env_vars_desc
 
-5. U-Boot:
-	Tree: https://source.denx.de/u-boot/u-boot
-	Branch: master
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_board_env_vars_desc
+    :end-before: .. k3_rst_include_end_board_env_vars_desc
 
-Build procedure:
-----------------
-1. SYSFW:
+Set the variables corresponding to this platform:
 
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_common_env_vars_defn
+    :end-before: .. k3_rst_include_end_common_env_vars_defn
 .. code-block:: bash
 
-    make CROSS_COMPILE=arm-linux-gnueabihf- SOC=j721e
+ $ export UBOOT_CFG_CORTEXR=j721e_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=j721e_evm_a72_defconfig
+ $ export TFA_BOARD=generic
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-j721e
+ $ # we dont use any extra OP-TEE parameters
+ $ unset OPTEE_EXTRA_ARGS
 
-2. ATF:
+.. j721e_evm_rst_include_start_build_steps
 
-.. code-block:: bash
+1. Trusted Firmware-A:
 
-    make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_tfa
+    :end-before: .. k3_rst_include_end_build_steps_tfa
 
-3. OPTEE:
 
-.. code-block:: bash
+2. OP-TEE:
 
-    make PLATFORM=k3-j721e CFG_ARM64_core=y
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_optee
+    :end-before: .. k3_rst_include_end_build_steps_optee
 
-4. U-Boot:
+3. U-Boot:
 
 * 4.1 R5:
 
-.. code-block:: bash
-
-    make CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=build/r5
-    make CROSS_COMPILE=arm-linux-gnueabihf- O=build/r5
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_spl_r5
+    :end-before: .. k3_rst_include_end_build_steps_spl_r5
 
 * 4.2 A72:
 
-.. code-block:: bash
-
-    make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=build/a72
-    make CROSS_COMPILE=aarch64-linux-gnu- ATF=<ATF dir>/build/k3/generic/release/bl31.bin TEE=<OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=<DM firmware>/ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f O=build/a72
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_uboot
+    :end-before: .. k3_rst_include_end_build_steps_uboot
+.. j721e_evm_rst_include_end_build_steps
 
 Target Images
 --------------
-Copy the below images to an SD card and boot:
- - sysfw.itb from step 1
- - tiboot3.bin from step 4.1
- - tispl.bin, u-boot.img from 4.2
+In order to boot we need tiboot3.bin, sysfw.itb, tispl.bin and u-boot.img.
+Each SoC variant (GP, HS-FS and HS-SE) requires a different source for these
+files.
+
+ - GP
+
+        * tiboot3-j721e-gp-evm.bin, sysfw-j721e-gp-evm.itb from step 4.1
+        * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2
+
+ - HS-FS
+
+        * tiboot3-j721e_sr2-hs-fs-evm.bin, sysfw-j721e_sr2-hs-fs-evm.itb from step 4.1
+        * tispl.bin, u-boot.img from step 4.2
+
+ - HS-SE
+
+        * tiboot3-j721e_sr2-hs-evm.bin, sysfw-j721e_sr2-hs-evm.itb from step 4.1
+        * tispl.bin, u-boot.img from step 4.2
 
 Image formats:
 --------------
 
-- tiboot3.bin:
+- tiboot3.bin
 
-.. code-block:: text
-
-                +-----------------------+
-                |        X.509          |
-                |      Certificate      |
-                | +-------------------+ |
-                | |                   | |
-                | |        R5         | |
-                | |   u-boot-spl.bin  | |
-                | |                   | |
-                | +-------------------+ |
-                | |                   | |
-                | |     FIT header    | |
-                | | +---------------+ | |
-                | | |               | | |
-                | | |   DTB 1...N   | | |
-                | | +---------------+ | |
-                | +-------------------+ |
-                +-----------------------+
+.. image:: img/no_multi_cert_tiboot3.bin.svg
 
 - tispl.bin
 
-.. code-block:: text
-
-                +-----------------------+
-                |                       |
-                |       FIT HEADER      |
-                | +-------------------+ |
-                | |                   | |
-                | |      A72 ATF      | |
-                | +-------------------+ |
-                | |                   | |
-                | |     A72 OPTEE     | |
-                | +-------------------+ |
-                | |                   | |
-                | |      R5 DM FW     | |
-                | +-------------------+ |
-                | |                   | |
-                | |      A72 SPL      | |
-                | +-------------------+ |
-                | |                   | |
-                | |   SPL DTB 1...N   | |
-                | +-------------------+ |
-                +-----------------------+
+.. image:: img/dm_tispl.bin.svg
 
 - sysfw.itb
 
-.. code-block:: text
-
-                +-----------------------+
-                |                       |
-                |       FIT HEADER      |
-                | +-------------------+ |
-                | |                   | |
-                | |     sysfw.bin     | |
-                | +-------------------+ |
-                | |                   | |
-                | |    board config   | |
-                | +-------------------+ |
-                | |                   | |
-                | |     PM config     | |
-                | +-------------------+ |
-                | |                   | |
-                | |     RM config     | |
-                | +-------------------+ |
-                | |                   | |
-                | |    Secure config  | |
-                | +-------------------+ |
-                +-----------------------+
+.. image:: img/sysfw.itb.svg
 
 R5 Memory Map:
 --------------
@@ -335,32 +212,7 @@ addresses.
 
 Flash layout for OSPI:
 
-.. code-block:: text
-
-         0x0 +----------------------------+
-             |     ospi.tiboot3(512K)     |
-             |                            |
-     0x80000 +----------------------------+
-             |     ospi.tispl(2M)         |
-             |                            |
-    0x280000 +----------------------------+
-             |     ospi.u-boot(4M)        |
-             |                            |
-    0x680000 +----------------------------+
-             |     ospi.env(128K)         |
-             |                            |
-    0x6A0000 +----------------------------+
-	     |	 ospi.env.backup (128K)   |
-	     |                            |
-    0x6C0000 +----------------------------+
-             |      ospi.sysfw(1M)        |
-             |                            |
-    0x7C0000 +----------------------------+
-	     |      padding (256k)        |
-    0x800000 +----------------------------+
-             |     ospi.rootfs(UBIFS)     |
-             |                            |
-             +----------------------------+
+.. image:: img/ospi_sysfw.svg
 
 Firmwares:
 ----------
@@ -376,3 +228,27 @@ J721E common processor board can be attached to a Ethernet QSGMII card and the
 PHY in the card has to be reset before it can be used for data transfer.
 "do_main_cpsw0_qsgmii_phyinit" env variable has to be set for the U-BOOT to
 configure this PHY.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+  **OpenOCD support since**: v0.12.0
+
+  If the default package version of OpenOCD in your development
+  environment's distribution needs to be updated, it might be necessary to
+  build OpenOCD from the source.
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+    :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. code-block:: bash
+
+  openocd -f board/ti_j721eevm.cfg
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index b49a60caf1..f4576c54cb 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -30,8 +30,11 @@ K3 Based SoCs
 .. toctree::
    :maxdepth: 1
 
-   j721e_evm
    am62x_sk
+   ../toradex/verdin-am62
+   am65x_evm
+   j7200_evm
+   j721e_evm
 
 Boot Flow Overview
 ------------------
@@ -43,22 +46,16 @@ boot media needed to load the binaries packaged inside `tiboot3.bin`,
 including a 32bit U-Boot SPL, (called the wakup SPL) that ROM will jump
 to after it has finished loading everything into internal SRAM.
 
-.. code-block:: text
-
-   |  WKUP Domain
-    ROM -> WKUP SPL ->
+.. image:: img/boot_flow_01.svg
 
 The wakeup SPL, running on a wakeup domain core, will initialize DDR and
 any peripherals needed load the larger binaries inside the `tispl.bin`
 into DDR.  Once loaded the wakeup SPL will start one of the 'big'
 application cores inside the main domain to initialize the main domain,
-starting with ARM Trusted Firmware (ATF), before moving on to start
-OPTEE and the main domain's U-Boot SPL.
+starting with Trusted Firmware-A (TF-A), before moving on to start
+OP-TEE and the main domain's U-Boot SPL.
 
-.. code-block:: text
-
-   |  WKUP Domain   | Main Domain ->
-    ROM -> WKUP SPL -> ATF -> OPTEE -> Main SPL
+.. image:: img/boot_flow_02.svg
 
 The main domain's SPL, running on a 64bit application core, has
 virtually unlimited space (billions of bytes now that DDR is working) to
@@ -66,10 +63,7 @@ initialize even more peripherals needed to load in the `u-boot.img`
 which loads more firmware into the micro-controller & wakeup domains and
 finally prepare the main domain to run Linux.
 
-.. code-block:: text
-
-   |  WKUP Domain   | Main Domain ->
-    ROM -> WKUP SPL -> ATF -> OPTEE -> Main SPL -> UBoot -> Linux
+.. image:: img/boot_flow_03.svg
 
 This is the typical boot flow for all K3 based SoCs, however this flow
 offers quite a lot in the terms of flexibility, especially on High
@@ -109,22 +103,19 @@ All scripts and code needed to build the `tiboot3.bin`, `tispl.bin` and
 `u-boot.img` for all K3 SoCs can be located at the following places
 online
 
+.. k3_rst_include_start_boot_sources
+
 * **Das U-Boot**
 
   | **source:** https://source.denx.de/u-boot/u-boot.git
   | **branch:** master
 
-* **K3 Image Gen**
+* **Trusted Firmware-A (TF-A)**
 
-  | **source:** https://git.ti.com/git/k3-image-gen/k3-image-gen.git
+  | **source:** https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/
   | **branch:** master
 
-* **ARM Trusted Firmware (ATF)**
-
-  | **source:** https://github.com/ARM-software/arm-trusted-firmware.git
-  | **branch:** master
-
-* **Open Portable Trusted Execution Environment (OPTEE)**
+* **Open Portable Trusted Execution Environment (OP-TEE)**
 
   | **source:** https://github.com/OP-TEE/optee_os.git
   | **branch:** master
@@ -134,10 +125,7 @@ online
   | **source:** https://git.ti.com/git/processor-firmware/ti-linux-firmware.git
   | **branch:** ti-linux-firmware
 
-* **TI's Security Development Tools**
-
-  | **source:** https://git.ti.com/git/security-development-tools/core-secdev-k3.git
-  | **branch:** master
+.. k3_rst_include_end_boot_sources
 
 Build Procedure
 ---------------
@@ -158,56 +146,100 @@ compiled for 64bit main domain CPU cores.
 All of that to say you will need both a 32bit and 64bit cross compiler
 (assuming you're using an x86 desktop)
 
+.. k3_rst_include_start_common_env_vars_desc
+.. list-table:: Generic environment variables
+   :widths: 25 25 50
+   :header-rows: 1
+
+   * - S/w Component
+     - Env Variable
+     - Description
+   * - All Software
+     - CC32
+     - Cross compiler for ARMv7 (ARM 32bit), typically arm-linux-gnueabihf-
+   * - All Software
+     - CC64
+     - Cross compiler for ARMv8 (ARM 64bit), typically aarch64-linux-gnu-
+   * - All Software
+     - LNX_FW_PATH
+     - Path to TI Linux firmware repository
+   * - All Software
+     - TFA_PATH
+     - Path to source of Trusted Firmware-A
+   * - All Software
+     - OPTEE_PATH
+     - Path to source of OP-TEE
+.. k3_rst_include_end_common_env_vars_desc
+
+.. k3_rst_include_start_common_env_vars_defn
 .. code-block:: bash
 
-   export CC32=arm-linux-gnueabihf-
-   export CC64=aarch64-linux-gnu-
+ $ export CC32=arm-linux-gnueabihf-
+ $ export CC64=aarch64-linux-gnu-
+ $ export LNX_FW_PATH=path/to/ti-linux-firmware
+ $ export TFA_PATH=path/to/trusted-firmware-a
+ $ export OPTEE_PATH=path/to/optee_os
+.. k3_rst_include_end_common_env_vars_defn
+
+We will also need some common environment variables set up for the various
+other build sources. we shall use the following, in the build descriptions below:
+
+.. k3_rst_include_start_board_env_vars_desc
+.. list-table:: Board specific environment variables
+   :widths: 25 25 50
+   :header-rows: 1
+
+   * - S/w Component
+     - Env Variable
+     - Description
+   * - U-Boot
+     - UBOOT_CFG_CORTEXR
+     - Defconfig for Cortex-R (Boot processor).
+   * - U-Boot
+     - UBOOT_CFG_CORTEXA
+     - Defconfig for Cortex-A (MPU processor).
+   * - Trusted Firmware-A
+     - TFA_BOARD
+     - Platform name used for building TF-A for Cortex-A Processor.
+   * - Trusted Firmware-A
+     - TFA_EXTRA_ARGS
+     - Any extra arguments used for building TF-A.
+   * - OP-TEE
+     - OPTEE_PLATFORM
+     - Platform name used for building OP-TEE for Cortex-A Processor.
+   * - OP-TEE
+     - OPTEE_EXTRA_ARGS
+     - Any extra arguments used for building OP-TEE.
+.. k3_rst_include_end_board_env_vars_desc
 
 Building tiboot3.bin
 ^^^^^^^^^^^^^^^^^^^^^
 
 1. To generate the U-Boot SPL for the wakeup domain, use the following
    commands, substituting :code:`{SOC}` for the name of your device (eg:
-   am62x)
-
-.. code-block:: bash
-
-   # inside u-boot source
-   make ARCH=arm O=build/wkup CROSS_COMPILE=$CC32 {SOC}_evm_r5_defconfig
-   make ARCH=arm O=build/wkup CROSS_COMPILE=$CC32
-
-2. Next we will use the K3 Image Gen scripts to package the various
-   firmware and the wakeup UBoot SPL into the final `tiboot3.bin`
-   binary. (or the `sysfw.itb` if your device uses the split binary
-   flow)
+   am62x) to package the various firmware and the wakeup UBoot SPL into
+   the final `tiboot3.bin` binary. (or the `sysfw.itb` if your device
+   uses the split binary flow)
 
+.. k3_rst_include_start_build_steps_spl_r5
 .. code-block:: bash
 
-   # inside k3-image-gen source
-   make CROSS_COMPILE=$CC32 SOC={SOC} SOC_TYPE={hs,gp} \
-        TI_SECURE_DEV_PKG=<path/to/securit-development-tools> \
-        SYSFW_PATH=<path/to/ti-sysfw/ti-fs-firmware-{SOC}-{hs|gp}.bin> \
-        SYSFW_HS_INNER_CERT_PATH=<path/to/ti-sysfw/ti-fs-firmware-{SOC}-hs-cert.bin
-
-For devices that use the *combined binary flow*, you will also need to
-supply the location of the SPL we created in step 1 above, so it can be
-packaged into the final `tiboot3.bin`.
-
-.. code-block:: bash
-
-   SBL=<path/to/wakeup/u-boot-spl.bin>
+ $ # inside u-boot source
+ $ make $UBOOT_CFG_CORTEXR
+ $ make CROSS_COMPILE=$CC32 BINMAN_INDIRS=$LNX_FW_PATH
+.. k3_rst_include_end_build_steps_spl_r5
 
 At this point you should have all the needed binaries to boot the wakeup
 domain of your K3 SoC.
 
 **Combined Binary Boot Flow** (eg: am62x, am64x, ... )
 
-   `k3-image-gen/tiboot3-{SOC}-{hs,gp}-evm.bin`
+   `tiboot3-{SOC}-{gp/hs-fs/hs}.bin`
 
 **Split Binary Boot Flow** (eg: j721e, am65x)
 
-   | `u-boot/build/wkup/tiboot3.bin`
-   | `k3-image-gen/sysfw-{SOC}-evm.bin`
+   | `tiboot3-{SOC}-{gp/hs-fs/hs}.bin`
+   | `sysfw-{SOC}-{gp/hs-fs/hs}-evm.itb`
 
 .. note ::
 
@@ -222,53 +254,731 @@ The `tispl.bin` is a standard fitImage combining the firmware need for
 the main domain to function properly as well as Device Management (DM)
 firmware if your device using a split firmware.
 
-3. We will first need ATF, as it's the first thing to run on the 'big'
+2. We will first need TF-A, as it's the first thing to run on the 'big'
    application cores on the main domain.
 
+.. k3_rst_include_start_build_steps_tfa
 .. code-block:: bash
 
-   # inside arm-trusted-firmware source
-   make CROSS_COMPILE=$CC64 ARCH=aarch64 PLAT=k3 \
-        TARGET_BOARD={lite|generic} \
-        SPD=opteed \
+ $ # inside trusted-firmware-a source
+ $ make CROSS_COMPILE=$CC64 ARCH=aarch64 PLAT=k3 SPD=opteed $TFA_EXTRA_ARGS \
+        TARGET_BOARD=$TFA_BOARD
+.. k3_rst_include_end_build_steps_tfa
 
-Typically all `j7*` devices will use `TARGET_BOARD=generic` while all
-Sitara (`am6*`) devices use the `lite` option.
+Typically all `j7*` devices will use `TARGET_BOARD=generic` or `TARGET_BOARD
+=j784s4` (if it is a J784S4 device), while typical Sitara (`am6*`) devices
+use the `lite` option.
 
-4. The Open Portable Trusted Execution Environment (OPTEE) is designed
+3. The Open Portable Trusted Execution Environment (OP-TEE) is designed
    to run as a companion to a non-secure Linux kernel for Cortex-A cores
    using the TrustZone technology built into the core.
 
+.. k3_rst_include_start_build_steps_optee
 .. code-block:: bash
 
-   # inside optee_os source
-   make CROSS_COMPILE=$CC32 CROSS_COMPILE64=$CC64 \
-        PLATFORM=k3 CFG_ARM64_core=y
+ $ # inside optee_os source
+ $ make CROSS_COMPILE=$CC32 CROSS_COMPILE64=$CC64 CFG_ARM64_core=y $OPTEE_EXTRA_ARGS \
+         PLATFORM=$OPTEE_PLATFORM
+.. k3_rst_include_end_build_steps_optee
 
-5. Finally, after ATF has initialized the main domain and OPTEE has
+4. Finally, after TF-A has initialized the main domain and OP-TEE has
    finished, we can jump back into U-Boot again, this time running on a
    64bit core in the main domain.
 
+.. k3_rst_include_start_build_steps_uboot
 .. code-block:: bash
 
-   # inside u-boot source
-   make ARCH=arm O=build/main CROSS_COMPILE=$CC64 {SOC}_evm_a{53,72}_defconfig
-   make ARCH=arm O=build/main CROSS_COMPILE=$CC64 \
-        ATF=<path/to/atf/bl31.bin \
-        TEE=<path/to/optee/tee-pager_v2.bin
+ $ # inside u-boot source
+ $ make $UBOOT_CFG_CORTEXA
+ $ make CROSS_COMPILE=$CC64 BINMAN_INDIRS=$LNX_FW_PATH \
+        BL31=$TFA_PATH/build/k3/$TFA_BOARD/release/bl31.bin \
+        TEE=$OPTEE_PATH/out/arm-plat-k3/core/tee-raw.bin
+.. k3_rst_include_end_build_steps_uboot
+
+At this point you should have every binary needed initialize both the
+wakeup and main domain and to boot to the U-Boot prompt
+
+**Main Domain Bootloader**
+
+   | `tispl.bin` for HS devices or `tispl.bin_unsigned` for GP devices
+   | `u-boot.img` for HS devices or `u-boot.img_unsigned` for GP devices
+
+Fit Signature Signing
+---------------------
+
+K3 Platforms have fit signature signing enabled by default on their primary
+platforms. Here we'll take an example for creating fit image for J721e platform
+and the same can be extended to other platforms
+
+1. Describing FIT source
+
+  .. code-block:: bash
+
+    /dts-v1/;
+
+    / {
+            description = "Kernel fitImage for j721e-hs-evm";
+            #address-cells = <1>;
+
+            images {
+                    kernel-1 {
+                            description = "Linux kernel";
+                            data = /incbin/("Image");
+                            type = "kernel";
+                            arch = "arm64";
+                            os = "linux";
+                            compression = "none";
+                            load = <0x80080000>;
+                            entry = <0x80080000>;
+                            hash-1 {
+                                    algo = "sha512";
+                            };
+
+                    };
+                    fdt-ti_k3-j721e-common-proc-board.dtb {
+                            description = "Flattened Device Tree blob";
+                            data = /incbin/("k3-j721e-common-proc-board.dtb");
+                            type = "flat_dt";
+                            arch = "arm64";
+                            compression = "none";
+                            load = <0x83000000>;
+                            hash-1 {
+                                    algo = "sha512";
+                            };
+
+                    };
+            };
+
+            configurations {
+                    default = "conf-ti_k3-j721e-common-proc-board.dtb";
+                    conf-ti_k3-j721e-common-proc-board.dtb {
+                            description = "Linux kernel, FDT blob";
+                            fdt = "fdt-ti_k3-j721e-common-proc-board.dtb";
+                            kernel = "kernel-1";
+                            signature-1 {
+                                    algo = "sha512,rsa4096";
+                                    key-name-hint = "custMpk";
+                                    sign-images = "kernel", "fdt";
+                            };
+                    };
+            };
+    };
+
+  You would require to change the '/incbin/' lines to point to the respective
+  files in your local machine and the key-name-hint also needs to be changed
+  if you are using some other key other than the TI dummy key that we are
+  using for this example.
+
+2. Compile U-boot for the respective board
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_uboot
+    :end-before: .. k3_rst_include_end_build_steps_uboot
+
+.. note::
+
+    The changes only affect a72 binaries so the example just builds that
+
+3. Sign the fit image and embed the dtb in uboot
+
+  Now once the build is done, you'll have a dtb for your board that you'll
+  be passing to mkimage for signing the fitImage and embedding the key in
+  the u-boot dtb.
+
+  .. code-block:: bash
+
+    mkimage -r -f fitImage.its -k $UBOOT_PATH/board/ti/keys -K
+    $UBOOT_PATH/build/a72/dts/dt.dtb
+
+  For signing a secondary platform, pass the -K parameter to that DTB
+
+  .. code-block:: bash
+
+    mkimage -f fitImage.its -k $UBOOT_PATH/board/ti/keys -K
+    $UBOOT_PATH/build/a72/arch/arm/dts/k3-j721e-sk.dtb
+
+  .. note::
+
+    If changing `CONFIG_DEFAULT_DEVICE_TREE` to the secondary platform,
+    binman changes would also be required so that correct dtb gets packaged.
+
+    .. code-block:: bash
+
+      diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi
+      index 673be646b1e3..752fa805fe8d 100644
+      --- a/arch/arm/dts/k3-j721e-binman.dtsi
+      +++ b/arch/arm/dts/k3-j721e-binman.dtsi
+      @@ -299,8 +299,8 @@
+       #define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb"
+
+       #define UBOOT_NODTB "u-boot-nodtb.bin"
+      -#define J721E_EVM_DTB "u-boot.dtb"
+      -#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb"
+      +#define J721E_EVM_DTB "arch/arm/dts/k3-j721e-common-proc-board.dtb"
+      +#define J721E_SK_DTB "u-boot.dtb"
+
+5. Rebuilt u-boot
+
+   This is required so that the modified dtb gets updated in u-boot.img
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_uboot
+    :end-before: .. k3_rst_include_end_build_steps_uboot
+
+6. (Optional) Enabled FIT_SIGNATURE_ENFORCED
+
+   By default u-boot will boot up the fit image without any authentication as
+   such if the public key is not embedded properly, to check if the public key
+   nodes are proper you can enable FIT_SIGNATURE_ENFORCED that would not rely
+   on the dtb for anything else then the signature node for checking the fit
+   image, rest other things will be enforced such as the property of
+   required-keys. This is not an extensive check so do manual checks also
+
+   This is by default enabled for devices with TI_SECURE_DEVICE enabled.
+
+.. note::
+
+   The devices now also have distroboot enabled so if the fit image doesn't
+   work then the fallback to normal distroboot will be there on hs devices,
+   this will need to be explicitly disabled by changing the boot_targets.
+
+Saving environment
+------------------
+
+SAVEENV is disabled by default and for the new flow uses Uenv.txt as the default
+way for saving the environments. This has been done as Uenv.txt is more granular
+then the saveenv command and can be used across various bootmodes too.
+
+**Writing to MMC/EMMC**
+
+.. code-block::
+
+  => env export -t $loadaddr <list of variables>
+  => fatwrite mmc ${mmcdev} ${loadaddr} ${bootenvfile} ${filesize}
+
+**Reading from MMC/EMMC**
+
+By default run envboot will read it from the MMC/EMMC partition ( based on
+mmcdev) and set the environments.
+
+If manually needs to be done then the environment can be read from the
+filesystem and then imported
+
+.. code-block::
+
+  => fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
+  => env import -t ${loadaddr} ${filesize}
+
+.. _k3_rst_refer_openocd:
+
+Common Debugging environment - OpenOCD
+--------------------------------------
+
+This section will show you how to connect a board to `OpenOCD
+<https://openocd.org/>`_ and load the SPL symbols for debugging with
+a K3 generation device. To follow this guide, you must build custom
+u-boot binaries, start your board from a boot media such as an SD
+card, and use an OpenOCD environment. This section uses generic
+examples, though you can apply these instructions to any supported K3
+generation device.
+
+The overall structure of this setup is in the following figure.
+
+.. image:: img/openocd-overview.svg
+
+.. note::
+
+  If you find these instructions useful, please consider `donating
+  <https://openocd.org/pages/donations.html>`_ to OpenOCD.
+
+Step 1: Download and install OpenOCD
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+To get started, it is more convenient if the distribution you
+use supports OpenOCD by default. Follow the instructions in the
+`getting OpenOCD <https://openocd.org/pages/getting-openocd.html>`_
+documentation to pick the installation steps appropriate to your
+environment. Some references to OpenOCD documentation:
+
+* `OpenOCD User Guide <https://openocd.org/doc/html/index.html>`_
+* `OpenOCD Developer's Guide <https://openocd.org/doc/doxygen/html/index.html>`_
 
-If your device uses a split firmware, you will also need to supply the
-path to the Device Management (DM) Firmware to be included in the final
-`tispl.bin` binary
+Refer to the release notes corresponding to the `OpenOCD version
+<https://github.com/openocd-org/openocd/releases>`_ to ensure
+
+* Processor support: In general, processor support shouldn't present
+  any difficulties since OpenOCD provides solid support for both ARMv8
+  and ARMv7.
+* SoC support: When working with System-on-a-Chip (SoC), the support
+  usually comes as a TCL config file. It is vital to ensure the correct
+  version of OpenOCD or to use the TCL files from the latest release or
+  the one mentioned.
+* Board or the JTAG adapter support: In most cases, board support is
+  a relatively easy problem if the board has a JTAG pin header. All
+  you need to do is ensure that the adapter you select is compatible
+  with OpenOCD. Some boards come with an onboard JTAG adapter that
+  requires a USB cable to be plugged into the board, in which case, it
+  is vital to ensure that the JTAG adapter is supported. Fortunately,
+  almost all TI K3 SK/EVMs come with TI's XDS110, which has out of the
+  box support by OpenOCD. The board-specific documentation will
+  cover the details and any adapter/dongle recommendations.
 
 .. code-block:: bash
 
-   DM=<path/to/ti-linux-firmware/ti-dm/ipc_echo_testb_mcu1_0_release_strip.xer5f>
+ openocd -v
 
-At this point you should have every binary needed initialize both the
-wakeup and main domain and to boot to the U-Boot prompt
+.. note::
 
-**Main Domain Bootloader**
+ OpenOCD version 0.12.0 is usually required to connect to most K3
+ devices. If your device is only supported by a newer version than the
+ one provided by your distribution, you may need to build it from the source.
+
+Building OpenOCD from source
+""""""""""""""""""""""""""""
+
+The dependency package installation instructions below are for Debian
+systems, but equivalent instructions should exist for systems with
+other package managers. Please refer to the `OpenOCD Documentation
+<https://openocd.org/>`_ for more recent installation steps.
+
+.. code-block:: bash
+
+  $ # Check the packages to be installed: needs deb-src in sources.list
+  $ sudo apt build-dep openocd
+  $ # The following list is NOT complete - please check the latest
+  $ sudo apt-get install libtool pkg-config texinfo libusb-dev \
+    libusb-1.0.0-dev libftdi-dev libhidapi-dev autoconf automake
+  $ git clone https://github.com/openocd-org/openocd.git openocd
+  $ cd openocd
+  $ git submodule init
+  $ git submodule update
+  $ ./bootstrap
+  $ ./configure --prefix=/usr/local/
+  $ make -j`nproc`
+  $ sudo make install
+
+.. note::
+
+  The example above uses the GitHub mirror site. See
+  `git repo information <https://openocd.org/doc/html/Developers.html#OpenOCD-Git-Repository>`_
+  information to pick the official git repo.
+  If a specific version is desired, select the version using `git checkout tag`.
+
+Installing OpenOCD udev rules
+"""""""""""""""""""""""""""""
+
+The step is not necessary if the distribution supports the OpenOCD, but
+if building from a source, ensure that the udev rules are installed
+correctly to ensure a sane system.
+
+.. code-block:: bash
+
+  # Go to the OpenOCD source directory
+  $ cd openocd
+  # Copy the udev rules to the correct system location
+  $ sudo cp ./contrib/60-openocd.rules \
+      ./src/JTAG/drivers/libjaylink/contrib/99-libjaylink.rules \
+      /etc/udev/rules.d/
+  # Get Udev to load the new rules up
+  $ sudo udevadm control --reload-rules
+  # Use the new rules on existing connected devices
+  $ sudo udevadm trigger
+
+Step 2: Setup GDB
+^^^^^^^^^^^^^^^^^
+
+Most systems come with gdb-multiarch package.
+
+.. code-block:: bash
+
+  # Install gdb-multiarch package
+  $ sudo apt-get install gdb-multiarch
+
+Though using GDB natively is normal, developers with interest in using IDE
+may find a few of these interesting:
+
+* `gdb-dashboard <https://github.com/cyrus-and/gdb-dashboard>`_
+* `gef <https://github.com/hugsy/gef>`_
+* `peda <https://github.com/longld/peda>`_
+* `pwndbg <https://github.com/pwndbg/pwndbg>`_
+* `voltron <https://github.com/snare/voltron>`_
+* `ddd <https://www.gnu.org/software/ddd/>`_
+* `vscode <https://www.justinmklam.com/posts/2017/10/vscode-debugger-setup/>`_
+* `vim conque-gdb <https://github.com/vim-scripts/Conque-GDB>`_
+* `emacs realgud <https://github.com/realgud/realgud/wiki/gdb-notes>`_
+* `Lauterbach IDE <https://www2.lauterbach.com/pdf/backend_gdb.pdf>`_
+
+.. warning::
+  LLDB support for OpenOCD is still a work in progress as of this writing.
+  Using GDB is probably the safest option at this point in time.
+
+Step 3: Connect board to PC
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+There are few patterns of boards in the ecosystem
+
+.. k3_rst_include_start_openocd_connect_XDS110
+
+**Integrated JTAG adapter/dongle**: The board has a micro-USB connector labelled
+XDS110 USB or JTAG. Connect a USB cable to the board to the mentioned port.
+
+.. note::
+
+  There are multiple USB ports on a typical board, So, ensure you have read
+  the user guide for the board and confirmed the silk screen label to ensure
+  connecting to the correct port.
+
+.. k3_rst_include_end_openocd_connect_XDS110
+
+.. k3_rst_include_start_openocd_connect_cti20
+
+**cTI20 connector**: The TI's `cTI20
+<https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_JTAG_connectors.html#cti-20-pin-header-information>`_ connector
+is probably the most prevelant on TI platforms. Though many
+TI boards have an onboard XDS110, cTI20 connector is usually
+provided as an alternate scheme to connect alternatives such
+as `Lauterbach <https://www.lauterbach.com/>`_ or `XDS560
+<https://www.ti.com/tool/TMDSEMU560V2STM-U>`_.
+
+To debug on these boards, the following combinations is suggested:
+
+* `TUMPA <https://www.diygadget.com/JTAG-cables-and-microcontroller-programmers/tiao-usb-multi-protocol-adapter-JTAG-spi-i2c-serial>`_
+  or `equivalent dongles supported by OpenOCD. <https://openocd.org/doc/html/Debug-Adapter-Hardware.html#Debug-Adapter-Hardware>`_
+* Cable such as `Tag-connect ribbon cable <https://www.tag-connect.com/product/20-pin-cortex-ribbon-cable-4-length-with-50-mil-connectors>`_
+* Adapter to convert cTI20 to ARM20 such as those from
+  `Segger <https://www.segger.com/products/debug-probes/j-link/accessories/adapters/ti-cti-20-adapter/>`_
+  or `Lauterbach LA-3780 <https://www.lauterbach.com/ad3780.html>`_
+  Or optionally, if you have manufacturing capability then you could try
+  `BeagleBone JTAG Adapter <https://github.com/mmorawiec/BeagleBone-Black-JTAG-Adapters>`_
+
+.. warning::
+  XDS560 and Lauterbach are proprietary solutions and is not supported by
+  OpenOCD.
+  When purchasing an off the shelf adapter/dongle, you do want to be careful
+  about the signalling though. Please
+  `read for additional info <https://software-dl.ti.com/ccs/esd/xdsdebugprobes/emu_JTAG_connectors.html>`_.
+
+.. k3_rst_include_end_openocd_connect_cti20
+
+.. k3_rst_include_start_openocd_connect_tag_connect
+
+**Tag-Connect**: `Tag-Connect <https://www.tag-connect.com/>`_
+pads on the boards which require special cable. Please check the documentation
+to `identify <https://www.tag-connect.com/info/legs-or-no-legs>`_ if "legged"
+or "no-leg" version of the cable is appropriate for the board.
+
+To debug on these boards, you will need:
+
+* `TUMPA <https://www.diygadget.com/JTAG-cables-and-microcontroller-programmers/tiao-usb-multi-protocol-adapter-JTAG-spi-i2c-serial>`_
+  or `equivalent dongles supported by OpenOCD <https://openocd.org/doc/html/Debug-Adapter-Hardware.html#Debug-Adapter-Hardware>`_.
+* Tag-Connect cable appropriate to the board such as
+  `TC2050-IDC-NL <https://www.tag-connect.com/product/TC2050-IDC-NL-10-pin-no-legs-cable-with-ribbon-connector>`_
+* In case of no-leg, version, a
+  `retaining clip <https://www.tag-connect.com/product/tc2050-clip-3pack-retaining-clip>`_
+* Tag-Connect to ARM20
+  `adapter <https://www.tag-connect.com/product/tc2050-arm2010-arm-20-pin-to-tc2050-adapter>`_
+
+.. note::
+  You can optionally use a 3d printed solution such as
+  `Protective cap <https://www.thingiverse.com/thing:3025584>`_ or
+  `clip <https://www.thingiverse.com/thing:3035278>`_ to replace
+  the retaining clip.
+
+.. warning::
+  With the Tag-Connect to ARM20 adapter, Please solder the "Trst" signal for
+  connection to work.
+
+.. k3_rst_include_end_openocd_connect_tag_connect
+
+Debugging with OpenOCD
+^^^^^^^^^^^^^^^^^^^^^^
+
+Debugging U-Boot is different from debugging regular user space
+applications. The bootloader initialization process involves many boot
+media and hardware configuration operations. For K3 devices, there
+are also interactions with security firmware. While reloading the
+"elf" file works through GDB, developers must be mindful of cascading
+initialization's potential consequences.
+
+Consider the following code change:
+
+.. code-block:: diff
+
+  --- a/file.c	2023-07-29 10:55:29.647928811 -0500
+  +++ b/file.c	2023-07-29 10:55:46.091856816 -0500
+  @@ -1,3 +1,3 @@
+   val = readl(reg);
+  -val |= 0x2;
+  +val |= 0x1;
+   writel(val, reg);
+
+Re-running the elf file with the above change will result in the
+register setting 0x3 instead of the intended 0x1. There are other
+hardware blocks which may not behave very well with a re-initialization
+without proper shutdown.
+
+To help narrow the debug down, it is usually simpler to use the
+standard boot media to get to the bootloader and debug only in the area
+of interest.
+
+In general, to debug u-boot spl/u-boot with OpenOCD there are three steps:
+
+* Modify the code adding a loop to allow the debugger to attach
+  near the point of interest. Boot up normally to stop at the loop.
+* Connect with OpenOCD and step out of the loop.
+* Step through the code to find the root of issue.
+
+Typical debugging involves a few iterations of the above sequence.
+Though most bootloader developers like to use printf to debug,
+debug with JTAG tends to be most efficient since it is possible to
+investigate the code flow and inspect hardware registers without
+repeated iterations.
+
+Code modification
+"""""""""""""""""
+
+* **start.S**: Adding an infinite while loop at the very entry of
+  U-Boot. For this, look for the corresponding start.S entry file.
+  This is usually only required when debugging some core SoC or
+  processor related function. For example: arch/arm/cpu/armv8/start.S or
+  arch/arm/cpu/armv7/start.S
+
+.. code-block:: diff
+
+  diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
+  index 69e281b086..744929e825 100644
+  --- a/arch/arm/cpu/armv7/start.S
+  +++ b/arch/arm/cpu/armv7/start.S
+  @@ -37,6 +37,8 @@
+   #endif
+
+   reset:
+  +dead_loop:
+  +    b dead_loop
+       /* Allow the board to save important registers */
+       b    save_boot_params
+   save_boot_params_ret:
+
+* **board_init_f**: Adding an infinite while loop at the board entry
+  function. In many cases, it is important to debug the boot process if
+  any changes are made for board-specific applications. Below is a step
+  by step process for debugging the boot SPL or Armv8 SPL:
+
+  To debug the boot process in either domain, we will first
+  add a modification to the code we would like to debug.
+  In this example, we will debug ``board_init_f`` inside
+  ``arch/arm/mach-k3/{soc}_init.c``. Since some sections of U-Boot
+  will be executed multiple times during the bootup process of K3
+  devices, we will need to include either ``CONFIG_CPU_ARM64`` or
+  ``CONFIG_CPU_V7R`` to catch the CPU at the desired place during the
+  bootup process (Main or Wakeup domains). For example, modify the
+  file as follows (depending on need):
+
+.. code-block:: c
+
+  void board_init_f(ulong dummy)
+  {
+      .
+      .
+      /* Code to run on the R5F (Wakeup/Boot Domain) */
+      if (IS_ENABLED(CONFIG_CPU_V7R)) {
+          volatile int x = 1;
+          while(x) {};
+      }
+      ...
+      /* Code to run on the ARMV8 (Main Domain) */
+      if (IS_ENABLED(CONFIG_CPU_ARM64)) {
+          volatile int x = 1;
+          while(x) {};
+      }
+      .
+      .
+  }
+
+Connecting with OpenOCD for a debug session
+"""""""""""""""""""""""""""""""""""""""""""
+
+Startup OpenOCD to debug the platform as follows:
+
+* **Integrated JTAG interface**: If the evm has a debugger such as
+  XDS110 inbuilt, there is typically an evm board support added and a
+  cfg file will be available.
+
+.. k3_rst_include_start_openocd_cfg_XDS110
+
+.. code-block:: bash
+
+  openocd -f board/{board_of_choice}.cfg
+
+.. k3_rst_include_end_openocd_cfg_XDS110
+
+.. k3_rst_include_start_openocd_cfg_external_intro
+
+* **External JTAG adapter/interface**: In other cases, where an
+  adapter/dongle is used, a simple cfg file can be created to integrate the
+  SoC and adapter information. See `supported TI K3 SoCs
+  <https://github.com/openocd-org/openocd/blob/master/tcl/target/ti_k3.cfg#L59>`_
+  to decide if the SoC is supported or not.
+
+.. code-block:: bash
+
+  openocd -f openocd_connect.cfg
+
+.. k3_rst_include_end_openocd_cfg_external_intro
+
+  For example, with BeaglePlay (AM62X platform), the openocd_connect.cfg:
+
+.. code-block:: tcl
+
+  # TUMPA example:
+  # http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual
+  source [find interface/ftdi/tumpa.cfg]
+
+  transport select jtag
+
+  # default JTAG configuration has only SRST and no TRST
+  reset_config srst_only srst_push_pull
+
+  # delay after SRST goes inactive
+  adapter srst delay 20
+
+  if { ![info exists SOC] } {
+    # Set the SoC of interest
+    set SOC am625
+  }
+
+  source [find target/ti_k3.cfg]
+
+  ftdi tdo_sample_edge falling
+
+  # Speeds for FT2232H are in multiples of 2, and 32MHz is tops
+  # max speed we seem to achieve is ~20MHz.. so we pick 16MHz
+  adapter speed 16000
+
+Below is an example of the output of this command:
+
+.. code-block:: console
+
+  Info : Listening on port 6666 for tcl connections
+  Info : Listening on port 4444 for telnet connections
+  Info : XDS110: connected
+  Info : XDS110: vid/pid = 0451/bef3
+  Info : XDS110: firmware version = 3.0.0.20
+  Info : XDS110: hardware version = 0x002f
+  Info : XDS110: connected to target via JTAG
+  Info : XDS110: TCK set to 2500 kHz
+  Info : clock speed 2500 kHz
+  Info : JTAG tap: am625.cpu tap/device found: 0x0bb7e02f (mfg: 0x017 (Texas Instruments), part: 0xbb7e, ver: 0x0)
+  Info : starting gdb server for am625.cpu.sysctrl on 3333
+  Info : Listening on port 3333 for gdb connections
+  Info : starting gdb server for am625.cpu.a53.0 on 3334
+  Info : Listening on port 3334 for gdb connections
+  Info : starting gdb server for am625.cpu.a53.1 on 3335
+  Info : Listening on port 3335 for gdb connections
+  Info : starting gdb server for am625.cpu.a53.2 on 3336
+  Info : Listening on port 3336 for gdb connections
+  Info : starting gdb server for am625.cpu.a53.3 on 3337
+  Info : Listening on port 3337 for gdb connections
+  Info : starting gdb server for am625.cpu.main0_r5.0 on 3338
+  Info : Listening on port 3338 for gdb connections
+  Info : starting gdb server for am625.cpu.gp_mcu on 3339
+  Info : Listening on port 3339 for gdb connections
+
+.. note::
+  Notice the default configuration is non-SMP configuration allowing
+  for each of the core to be attached and debugged simultaneously.
+  ARMv8 SPL/U-Boot starts up on cpu0 of a53/a72.
+
+.. k3_rst_include_start_openocd_cfg_external_gdb
+
+To debug using this server, use GDB directly or your preferred
+GDB-based IDE. To start up GDB in the terminal, run the following
+command.
+
+.. code-block:: bash
+
+  gdb-multiarch
+
+To connect to your desired core, run the following command within GDB:
+
+.. code-block:: bash
+
+  target extended-remote localhost:{port for desired core}
+
+To load symbols:
+
+.. warning::
+
+  SPL and U-Boot does a re-location of address compared to where it
+  is loaded originally. This step takes place after the DDR size is
+  determined from dt parsing. So, debugging can be split into either
+  "before re-location" or "after re-location". Please refer to the
+  file ''doc/README.arm-relocation'' to see how to grab the relocation
+  address.
+
+* Prior to relocation:
+
+.. code-block:: bash
+
+  symbol-file {path to elf file}
+
+* After relocation:
+
+.. code-block:: bash
+
+  # Drop old symbol file
+  symbol-file
+  # Pick up new relocaddr
+  add-symbol-file {path to elf file} {relocaddr}
+
+.. k3_rst_include_end_openocd_cfg_external_gdb
+
+In the above example of AM625,
+
+.. code-block:: bash
+
+  target extended-remote localhost:3338     <- R5F (Wakeup Domain)
+  target extended-remote localhost:3334     <- A53 (Main Domain)
+
+The core can now be debugged directly within GDB using GDB commands or
+if using IDE, as appropriate to the IDE.
+
+Stepping through the code
+"""""""""""""""""""""""""
+
+`GDB TUI Commands
+<https://sourceware.org/gdb/onlinedocs/gdb/TUI-Commands.html>`_ can
+help set up the display more sensible for debug. Provide the name
+of the layout that can be used to debug. For example, use the GDB
+command ``layout src`` after loading the symbols to see the code and
+breakpoints. To exit the debug loop added above, add any breakpoints
+needed and run the following GDB commands to step out of the debug
+loop set in the ``board_init_f`` function.
+
+.. code-block:: bash
+
+  set x = 0
+  continue
+
+The platform has now been successfully setup to debug with OpenOCD
+using GDB commands or a GDB-based IDE. See `OpenOCD documentation for
+GDB <https://openocd.org/doc/html/GDB-and-OpenOCD.html>`_ for further
+information.
+
+.. warning::
+
+  On the K3 family of devices, a watchdog timer within the DMSC is
+  enabled by default by the ROM bootcode with a timeout of 3 minutes.
+  The watchdog timer is serviced by System Firmware (SYSFW) or TI
+  Foundational Security (TIFS) during normal operation. If debugging
+  the SPL before the SYSFW is loaded, the watchdog timer will not get
+  serviced automatically and the debug session will reset after 3
+  minutes. It is recommended to start debugging SPL code only after
+  the startup of SYSFW to avoid running into the watchdog timer reset.
+
+Miscellaneous notes with OpenOCD
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-   | `u-boot/build/main/tispl.bin`
-   | `u-boot/build/main/u-boot.img`
+Currently, OpenOCD does not support tracing for K3 platforms. Tracing
+function could be beneficial if the bug in code occurs deep within
+nested function and can optionally save developers major trouble of
+stepping through a large quantity of code.
diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst
index ead5efbb95..89fbdcbb9e 100644
--- a/doc/board/toradex/index.rst
+++ b/doc/board/toradex/index.rst
@@ -9,5 +9,6 @@ Toradex
    apalis-imx8
    colibri_imx7
    colibri-imx8x
+   verdin-am62
    verdin-imx8mm
    verdin-imx8mp
diff --git a/doc/board/toradex/verdin-am62.rst b/doc/board/toradex/verdin-am62.rst
new file mode 100644
index 0000000000..36db149cda
--- /dev/null
+++ b/doc/board/toradex/verdin-am62.rst
@@ -0,0 +1,133 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+.. sectionauthor:: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+
+Verdin AM62 Module
+==================
+
+- SoM: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+- Carrier board: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+
+Quick Start
+-----------
+
+- Get the binary-only SYSFW
+- Get binary-only TI Linux firmware
+- Build the ARM trusted firmware binary
+- Build the OPTEE binary
+- Build U-Boot for the R5
+- Build U-Boot for the A53
+- Flash to eMMC
+- Boot
+
+For an overview of the TI AM62 SoC boot flow please head over to:
+:doc:`../ti/am62x_sk`
+
+Sources:
+--------
+.. include::  ../ti/k3.rst
+    :start-after: .. k3_rst_include_start_boot_sources
+    :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include::  ../ti/k3.rst
+    :start-after: .. k3_rst_include_start_common_env_vars_desc
+    :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include::  ../ti/k3.rst
+    :start-after: .. k3_rst_include_start_board_env_vars_desc
+    :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include::  ../ti/k3.rst
+    :start-after: .. k3_rst_include_start_common_env_vars_defn
+    :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=verdin-am62_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=verdin-am62_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am62x
+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+
+.. include::  ../ti/am62x_sk.rst
+    :start-after: .. am62x_evm_rst_include_start_build_steps
+    :end-before: .. am62x_evm_rst_include_end_build_steps
+
+Flash to eMMC
+-------------
+
+.. code-block:: bash
+
+    => mmc dev 0 1
+    => fatload mmc 1 ${loadaddr} tiboot3.bin
+    => mmc write ${loadaddr} 0x0 0x400
+    => fatload mmc 1 ${loadaddr} tispl.bin
+    => mmc write ${loadaddr} 0x400 0x1000
+    => fatload mmc 1 ${loadaddr} u-boot.img
+    => mmc write ${loadaddr} 0x1400 0x2000
+
+Boot
+----
+
+Output:
+
+.. code-block:: none
+
+  U-Boot SPL 2023.10-rc1-00210-gb678170a34c (Aug 03 2023 - 00:09:14 +0200)
+  SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.1--v09.00.01 (Kool Koala)')
+  SPL initial stack usage: 13368 bytes
+  Trying to boot from MMC1
+  Authentication passed
+  Authentication passed
+  Authentication passed
+  Authentication passed
+  Authentication passed
+  Starting ATF on ARM64 core...
+
+  NOTICE:  BL31: v2.9(release):v2.9.0-73-g463655cc8
+  NOTICE:  BL31: Built : 14:51:42, Jun  5 2023
+  I/TC:
+  I/TC: OP-TEE version: 3.21.0-168-g322cf9e33 (gcc version 12.2.1 20221205 (Arm GNU Toolchain 12.2.Rel1 (Build arm-12.24))) #2 Mon Jun  5 13:04:15 UTC 2023 aarch64
+  I/TC: WARNING: This OP-TEE configuration might be insecure!
+  I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
+  I/TC: Primary CPU initializing
+  I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.1--v09.00.01 (Kool Koala)')
+  I/TC: HUK Initialized
+  I/TC: Primary CPU switching to normal world boot
+
+  U-Boot SPL 2023.10-rc1-00210-gb678170a34c (Aug 03 2023 - 00:09:41 +0200)
+  SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.1--v09.00.01 (Kool Koala)')
+  SPL initial stack usage: 1840 bytes
+  Trying to boot from MMC1
+  Authentication passed
+  Authentication passed
+
+
+  U-Boot 2023.10-rc1-00210-gb678170a34c (Aug 03 2023 - 00:09:41 +0200)
+
+  SoC:   AM62X SR1.0 HS-FS
+  DRAM:  2 GiB
+  Core:  136 devices, 28 uclasses, devicetree: separate
+  MMC:   mmc@fa10000: 0, mmc@fa00000: 1
+  Loading Environment from MMC... OK
+  In:    serial@2800000
+  Out:   serial@2800000
+  Err:   serial@2800000
+  Model: Toradex 0076 Verdin AM62 Quad 2GB WB IT V1.0A
+  Serial#: 15037380
+  Carrier: Toradex Verdin Development Board V1.1A, Serial# 10754333
+  am65_cpsw_nuss ethernet@8000000: K3 CPSW: nuss_ver: 0x6BA01103 cpsw_ver: 0x6BA81103 ale_ver: 0x00290105 Ports:2 mdio_freq:1000000
+  Setting variant to wifi
+  Net:
+  Warning: ethernet@8000000port@1 MAC addresses don't match:
+  Address in ROM is		1c:63:49:22:5f:f9
+  Address in environment is	00:14:2d:e5:73:c4
+  eth0: ethernet@8000000port@1 [PRIME], eth1: ethernet@8000000port@2
+  Hit any key to stop autoboot:  0
+  Verdin AM62 #
diff --git a/doc/board/toradex/verdin-imx8mm.rst b/doc/board/toradex/verdin-imx8mm.rst
index 439128adce..cc39030450 100644
--- a/doc/board/toradex/verdin-imx8mm.rst
+++ b/doc/board/toradex/verdin-imx8mm.rst
@@ -1,8 +1,12 @@
-.. SPDX-License-Identifier: GPL-2.0+
+.. SPDX-License-Identifier: GPL-2.0-or-later
+.. sectionauthor:: Marcel Ziswiler <marcel.ziswiler@toradex.com>
 
 Verdin iMX8M Mini Module
 ========================
 
+- SoM: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano
+- Carrier board: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+
 Quick Start
 -----------
 
@@ -25,6 +29,7 @@ Then build ATF (TF-A):
 
 .. code-block:: bash
 
+    $ export CROSS_COMPILE=aarch64-linux-gnu-
     $ make PLAT=imx8mm IMX_BOOT_UART_BASE=0x30860000 bl31
     $ cp build/imx8mm/release/bl31.bin ../
 
@@ -75,30 +80,30 @@ Boot sequence is:
 
 Output:
 
-.. code-block:: bash
-
-U-Boot SPL 2021.10-rc2-00028-gee010ba1129 (Aug 23 2021 - 16:56:02 +0200)
-Normal Boot
-WDT:   Started with servicing (60s timeout)
-Trying to boot from MMC1
-NOTICE:  BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
-NOTICE:  BL31: Built : 18:02:12, Aug 16 2021
-
-
-U-Boot 2021.10-rc2-00028-gee010ba1129 (Aug 23 2021 - 16:56:02 +0200)
-
-CPU:   Freescale i.MX8MMQ rev1.0 at 1200 MHz
-Reset cause: POR
-DRAM:  2 GiB
-WDT:   Started with servicing (60s timeout)
-MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
-Loading Environment from MMC... OK
-In:    serial
-Out:   serial
-Err:   serial
-Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.1A, Serial# 06760554
-Carrier: Toradex Verdin Development Board V1.1A, Serial# 10754333
-Setting variant to wifi
-Net:   eth0: ethernet@30be0000
-Hit any key to stop autoboot:  0
-Verdin iMX8MM #
+.. code-block:: none
+
+  U-Boot SPL 2021.10-rc2-00028-gee010ba1129 (Aug 23 2021 - 16:56:02 +0200)
+  Normal Boot
+  WDT:   Started with servicing (60s timeout)
+  Trying to boot from MMC1
+  NOTICE:  BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
+  NOTICE:  BL31: Built : 18:02:12, Aug 16 2021
+
+
+  U-Boot 2021.10-rc2-00028-gee010ba1129 (Aug 23 2021 - 16:56:02 +0200)
+
+  CPU:   Freescale i.MX8MMQ rev1.0 at 1200 MHz
+  Reset cause: POR
+  DRAM:  2 GiB
+  WDT:   Started with servicing (60s timeout)
+  MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
+  Loading Environment from MMC... OK
+  In:    serial
+  Out:   serial
+  Err:   serial
+  Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.1A, Serial# 06760554
+  Carrier: Toradex Verdin Development Board V1.1A, Serial# 10754333
+  Setting variant to wifi
+  Net:   eth0: ethernet@30be0000
+  Hit any key to stop autoboot:  0
+  Verdin iMX8MM #
diff --git a/doc/board/toradex/verdin-imx8mp.rst b/doc/board/toradex/verdin-imx8mp.rst
index 482f693577..bdc4d0c2cb 100644
--- a/doc/board/toradex/verdin-imx8mp.rst
+++ b/doc/board/toradex/verdin-imx8mp.rst
@@ -1,8 +1,12 @@
 .. SPDX-License-Identifier: GPL-2.0-or-later
+.. sectionauthor:: Marcel Ziswiler <marcel.ziswiler@toradex.com>
 
 Verdin iMX8M Plus Module
 ========================
 
+- SoM: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus
+- Carrier board: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+
 Quick Start
 -----------
 
@@ -76,36 +80,36 @@ Boot sequence is:
 
 Output:
 
-.. code-block:: bash
-
-U-Boot SPL 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
-Quad die, dual rank failed, attempting dual die, single rank configuration.
-Normal Boot
-WDT:   Started watchdog@30280000 with servicing (60s timeout)
-Trying to boot from BOOTROM
-Find img info 0x&48025a00, size 872
-Need continue download 1024
-Download 779264, Total size 780424
-NOTICE:  BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
-NOTICE:  BL31: Built : 16:52:37, Aug 26 2021
-
-
-U-Boot 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
-
-CPU:   Freescale i.MX8MP[8] rev1.1 at 1200 MHz
-Reset cause: POR
-DRAM:  8 GiB
-Core:  78 devices, 18 uclasses, devicetree: separate
-WDT:   Started watchdog@30280000 with servicing (60s timeout)
-MMC:   FSL_SDHC: 1, FSL_SDHC: 2
-Loading Environment from MMC... OK
-In:    serial
-Out:   serial
-Err:   serial
-Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0B, Serial# 06817281
-Carrier: Toradex Verdin Development Board V1.1A, Serial# 10807609
-Setting variant to wifi
-Net:   Hard-coding pdata->enetaddr
-eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
-Hit any key to stop autoboot:  0
-Verdin iMX8MP #
+.. code-block:: none
+
+  U-Boot SPL 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
+  Quad die, dual rank failed, attempting dual die, single rank configuration.
+  Normal Boot
+  WDT:   Started watchdog@30280000 with servicing (60s timeout)
+  Trying to boot from BOOTROM
+  Find img info 0x&48025a00, size 872
+  Need continue download 1024
+  Download 779264, Total size 780424
+  NOTICE:  BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
+  NOTICE:  BL31: Built : 16:52:37, Aug 26 2021
+
+
+  U-Boot 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
+
+  CPU:   Freescale i.MX8MP[8] rev1.1 at 1200 MHz
+  Reset cause: POR
+  DRAM:  8 GiB
+  Core:  78 devices, 18 uclasses, devicetree: separate
+  WDT:   Started watchdog@30280000 with servicing (60s timeout)
+  MMC:   FSL_SDHC: 1, FSL_SDHC: 2
+  Loading Environment from MMC... OK
+  In:    serial
+  Out:   serial
+  Err:   serial
+  Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0B, Serial# 06817281
+  Carrier: Toradex Verdin Development Board V1.1A, Serial# 10807609
+  Setting variant to wifi
+  Net:   Hard-coding pdata->enetaddr
+  eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
+  Hit any key to stop autoboot:  0
+  Verdin iMX8MP #
diff --git a/doc/board/xen/xenguest_arm64.rst b/doc/board/xen/xenguest_arm64.rst
index 1327f88f99..e9bdaf7ffb 100644
--- a/doc/board/xen/xenguest_arm64.rst
+++ b/doc/board/xen/xenguest_arm64.rst
@@ -6,7 +6,7 @@ Xen guest ARM64 board
 This board specification
 ------------------------
 
-This board is to be run as a virtual Xen [1] guest with U-boot as its primary
+This board is to be run as a virtual Xen [1] guest with U-Boot as its primary
 bootloader. Xen is a type 1 hypervisor that allows multiple operating systems
 to run simultaneously on a single physical server. Xen is capable of running
 virtual machines in both full virtualization and para-virtualization (PV)
@@ -16,7 +16,7 @@ Paravirtualized drivers are a special type of device drivers that are used in
 a guest system in the Xen domain and perform I/O operations using a special
 interface provided by the virtualization system and the host system.
 
-Xen support for U-boot is implemented by introducing a new Xen guest ARM64
+Xen support for U-Boot is implemented by introducing a new Xen guest ARM64
 board and porting essential drivers from MiniOS [3] as well as some of the work
 previously done by NXP [4]:
 
@@ -39,7 +39,7 @@ previously done by NXP [4]:
 Board limitations
 -----------------
 
-1. U-boot runs without MMU enabled at the early stages.
+1. U-Boot runs without MMU enabled at the early stages.
    According to Xen on ARM ABI (xen/include/public/arch-arm.h): all memory
    which is shared with other entities in the system (including the hypervisor
    and other guests) must reside in memory which is mapped as Normal Inner
@@ -54,14 +54,14 @@ Board limitations
 2. No serial console until MMU is up.
    Because data cache maintenance is required until the MMU setup the
    early/debug serial console is not implemented. Therefore, we do not have
-   usual prints like U-boot’s banner etc. until the serial driver is
+   usual prints like U-Boot’s banner etc. until the serial driver is
    initialized.
 
 3. Single RAM bank supported.
    If a Xen guest is given much memory it is possible that Xen allocates two
    memory banks for it. The first one is allocated under 4GB address space and
    in some cases may represent the whole guest’s memory. It is assumed that
-   U-boot most likely won’t require high memory bank for its work andlaunching
+   U-Boot most likely won’t require high memory bank for its work andlaunching
    OS, so it is enough to take the first one.
 
 
diff --git a/doc/build/clang.rst b/doc/build/clang.rst
index 1d35616eb5..cc265506c2 100644
--- a/doc/build/clang.rst
+++ b/doc/build/clang.rst
@@ -74,3 +74,39 @@ simplified with a simple wrapper script - saved as
 
     #!/bin/sh
     exec clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd "$@"
+
+
+Known Issues
+------------
+
+When build U-boot for `xenguest_arm64_defconfig` target, it reports linkage
+error:
+
+.. code-block:: bash
+
+    aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `do_hypervisor_callback':
+    /home/leoy/Dev2/u-boot/drivers/xen/hypervisor.c:188: undefined reference to `__aarch64_swp8_acq_rel'
+    aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_set_bit':
+    /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel'
+    aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_clear_bit':
+    /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel'
+    aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_set_bit':
+    /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel'
+    aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_clear_bit':
+    /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel'
+    aarch64-linux-gnu-ld.bfd: drivers/xen/events.o: in function `synch_test_and_clear_bit':
+    /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel'
+    aarch64-linux-gnu-ld.bfd: drivers/xen/events.o: in function `synch_test_and_set_bit':
+    /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel'
+    aarch64-linux-gnu-ld.bfd: drivers/xen/gnttab.o: in function `gnttab_end_access':
+    /home/leoy/Dev2/u-boot/drivers/xen/gnttab.c:109: undefined reference to `__aarch64_cas2_acq_rel'
+    Segmentation fault
+
+To fix the failure, we need to append option `-mno-outline-atomics` in Clang
+command to not generate local calls to out-of-line atomic operations:
+
+.. code-block:: bash
+
+    make HOSTCC=clang xenguest_arm64_defconfig
+    make HOSTCC=clang CROSS_COMPILE=aarch64-linux-gnu- \
+         CC="clang -target aarch64-linux-gnueabi -mno-outline-atomics" -j8
diff --git a/doc/develop/board_best_practices.rst b/doc/develop/board_best_practices.rst
new file mode 100644
index 0000000000..f44401eab7
--- /dev/null
+++ b/doc/develop/board_best_practices.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+Best Practices for Board Ports
+==============================
+
+In addition to the regular best practices such as using :doc:`checkpatch` and
+following the :doc:`docstyle` and the :doc:`codingstyle` there are some things
+which are specific to creating a new board port.
+
+* Implement :doc:`bootstd` to ensure that most operating systems will be
+  supported by the platform.
+
+* The platform defconfig file must be generated via `make savedefconfig`.
+
+* The Kconfig and Kbuild infrastructure supports using "fragments" that can be
+  used to apply changes on top of a defconfig file. These can be useful for
+  many things such as:
+
+  * Supporting different firmware locations (e.g. eMMC, SD, QSPI).
+
+  * Multiple board variants when runtime detection is not desired.
+
+  * Supporting different build types such as production and development.
+
+  Kconfig fragments should reside in the board directory itself rather than in
+  the top-level `configs/` directory.
diff --git a/doc/develop/bootstd.rst b/doc/develop/bootstd.rst
index 7a2a69fdfc..ec31365357 100644
--- a/doc/develop/bootstd.rst
+++ b/doc/develop/bootstd.rst
@@ -306,7 +306,7 @@ media device::
 
 The bootdev device is typically created automatically in the media uclass'
 `post_bind()` method by calling `bootdev_setup_for_dev()` or
-`bootdev_setup_sibling_blk()`. The code typically something like this::
+`bootdev_setup_for_sibling_blk()`. The code typically something like this::
 
     /* dev is the Ethernet device */
     ret = bootdev_setup_for_dev(dev, "eth_bootdev");
@@ -316,7 +316,7 @@ The bootdev device is typically created automatically in the media uclass'
 or::
 
     /* blk is the block device (child of MMC device)
-    ret = bootdev_setup_sibling_blk(blk, "mmc_bootdev");
+    ret = bootdev_setup_for_sibling_blk(blk, "mmc_bootdev");
     if (ret)
         return log_msg_ret("bootdev", ret);
 
diff --git a/doc/develop/codingstyle.rst b/doc/develop/codingstyle.rst
index 3d05a6b988..b25bfbd271 100644
--- a/doc/develop/codingstyle.rst
+++ b/doc/develop/codingstyle.rst
@@ -120,7 +120,7 @@ then headers with directories, then local files:
    #include <others.h>
    #include <asm/...>
    #include <arm/arch/...>
-   #include <dm/device_compat/.h>
+   #include <dm/device_compat.h>
    #include <linux/...>
    #include "local.h"
 
diff --git a/doc/develop/docstyle.rst b/doc/develop/docstyle.rst
index f9ba83a559..50506d6857 100644
--- a/doc/develop/docstyle.rst
+++ b/doc/develop/docstyle.rst
@@ -20,7 +20,7 @@ We apply the following rules:
 * For documentation we use reStructured text conforming to the requirements
   of `Sphinx <https://www.sphinx-doc.org>`_.
 * For documentation within code we follow the Linux kernel guide
-  `Writing kernel-doc comments <https://docs.kernel.org/doc-guide/kernel-doc.html>`_.
+  `Writing kernel-doc comments <https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html>`_.
 * We try to stick to 80 columns per line in documents.
 * For tables we prefer simple tables over grid tables. We avoid list tables
   as they make the reStructured text documents hard to read.
diff --git a/doc/develop/driver-model/bind.rst b/doc/develop/driver-model/bind.rst
index b19661b5fe..0d0d40734c 100644
--- a/doc/develop/driver-model/bind.rst
+++ b/doc/develop/driver-model/bind.rst
@@ -7,7 +7,7 @@ Binding/unbinding a driver
 This document aims to describe the bind and unbind commands.
 
 For debugging purpose, it should be useful to bind or unbind a driver from
-the U-boot command line.
+the U-Boot command line.
 
 The unbind command calls the remove device driver callback and unbind the
 device from its driver.
diff --git a/doc/develop/driver-model/fs_firmware_loader.rst b/doc/develop/driver-model/fs_firmware_loader.rst
index b0823700a9..149b8b436e 100644
--- a/doc/develop/driver-model/fs_firmware_loader.rst
+++ b/doc/develop/driver-model/fs_firmware_loader.rst
@@ -92,9 +92,9 @@ For example of getting DT phandle from /chosen and creating instance:
 	if (ret)
 		return ret;
 
-Firmware loader driver is also designed to support U-boot environment
+Firmware loader driver is also designed to support U-Boot environment
 variables, so all these data from FDT can be overwritten
-through the U-boot environment variable during run time.
+through the U-Boot environment variable during run time.
 
 For examples:
 
@@ -110,7 +110,7 @@ fw_ubi_volume:
 When above environment variables are set, environment values would be
 used instead of data from FDT.
 The benefit of this design allows user to change storage attribute data
-at run time through U-boot console and saving the setting as default
+at run time through U-Boot console and saving the setting as default
 environment values in the storage for the next power cycle, so no
 compilation is required for both driver and FDT.
 
diff --git a/doc/develop/expo.rst b/doc/develop/expo.rst
index 32dd7f0903..2ac4af232d 100644
--- a/doc/develop/expo.rst
+++ b/doc/develop/expo.rst
@@ -85,6 +85,9 @@ or even the IDs of objects. Programmatic creation of many items in a loop can be
 handled by allocating space in the enum for a maximum number of items, then
 adding the loop count to the enum values to obtain unique IDs.
 
+Where dynamic IDs are need, use expo_set_dynamic_start() to set the start value,
+so that they are allocated above the starting (enum) IDs.
+
 All text strings are stored in a structure attached to the expo, referenced by
 a text ID. This makes it easier at some point to implement multiple languages or
 to support Unicode strings.
@@ -97,10 +100,13 @@ objects first, then create the menu item, passing in the relevant IDs.
 Creating an expo
 ----------------
 
-To create an expo, use `expo_new()` followed by `scene_new()` to create a scene.
-Then add objects to the scene, using functions like `scene_txt_str()` and
-`scene_menu()`. For every menu item, add text and image objects, then create
-the menu item with `scene_menuitem()`, referring to those objects.
+To create an expo programmatically, use `expo_new()` followed by `scene_new()`
+to create a scene. Then add objects to the scene, using functions like
+`scene_txt_str()` and `scene_menu()`. For every menu item, add text and image
+objects, then create the menu item with `scene_menuitem()`, referring to those
+objects.
+
+To create an expo using a description file, see :ref:`expo_format` below.
 
 Layout
 ------
@@ -152,8 +158,287 @@ such as scanning devices for more bootflows.
 Themes
 ------
 
-Expo does not itself support themes. The bootflow_menu implement supposed a
-basic theme, applying font sizes to the various text objects in the expo.
+Expo supports simple themes, for setting the font size, for example. Use the
+expo_apply_theme() function to load a theme, passing a node with the required
+properties:
+
+font-size
+    Font size to use for all text (type: u32)
+
+menu-inset
+    Number of pixels to inset the menu on the sides and top (type: u32)
+
+menuitem-gap-y
+    Number of pixels between menu items
+
+Pop-up mode
+-----------
+
+Expos support two modes. The simple mode is used for selecting from a single
+menu, e.g. when choosing with OS to boot. In this mode the menu items are shown
+in a list (label, > pointer, key and description) and can be chosen using arrow
+keys and enter::
+
+   U-Boot Boot Menu
+
+   UP and DOWN to choose, ENTER to select
+
+   mmc1           > 0  Fedora-Workstation-armhfp-31-1.9
+   mmc3             1  Armbian
+
+The popup mode allows multiple menus to be present in a scene. Each is shown
+just as its title and label, as with the `CPU Speed` and `AC Power` menus here::
+
+              Test Configuration
+
+
+   CPU Speed        <2 GHz>  (highlighted)
+
+   AC Power         Always Off
+
+
+     UP and DOWN to choose, ENTER to select
+
+
+.. _expo_format:
+
+Expo Format
+-----------
+
+It can be tedious to create a complex expo using code. Expo supports a
+data-driven approach, where the expo description is in a devicetree file. This
+makes it easier and faster to create and edit the description. An expo builder
+is provided to convert this format into an expo structure.
+
+Layout of the expo scenes is handled automatically, based on a set of simple
+rules. The :doc:`../usage/cmd/cedit` can be used to load a configuration
+and create an expo from it.
+
+Top-level node
+~~~~~~~~~~~~~~
+
+The top-level node has the following properties:
+
+dynamic-start
+    type: u32, optional
+
+    Specifies the start of the dynamically allocated objects. This results in
+    a call to expo_set_dynamic_start().
+
+The top-level node has the following subnodes:
+
+scenes
+    Specifies the scenes in the expo, each one being a subnode
+
+strings
+    Specifies the strings in the expo, each one being a subnode
+
+`scenes` node
+~~~~~~~~~~~~~
+
+Contains a list of scene subnodes. The name of each subnode is passed as the
+name to `scene_new()`.
+
+`strings` node
+~~~~~~~~~~~~~~
+
+Contains a list of string subnodes. The name of each subnode is ignored.
+
+`strings` subnodes
+~~~~~~~~~~~~~~~~~~
+
+Each subnode defines a string which can be used by scenes and objects. Each
+string has an ID number which is used to refer to it.
+
+The `strings` subnodes have the following properties:
+
+id
+    type: u32, required
+
+    Specifies the ID number for the string.
+
+value:
+    type: string, required
+
+    Specifies the string text. For now only a single value is supported. Future
+    work may add support for multiple languages by using a value for each
+    language.
+
+Scene nodes (`scenes` subnodes)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Each subnode of the `scenes` node contains a scene description.
+
+Most properties can use either a string or a string ID. For example, a `title`
+property can be used to provide the title for a menu; alternatively a `title-id`
+property can provide the string ID of the title. If both are present, the
+ID takes preference, except that if a string with that ID does not exist, it
+falls back to using the string from the property (`title` in this example). The
+description below shows these are alternative properties with the same
+description.
+
+The scene nodes have the following properties:
+
+id
+    type: u32, required
+
+    Specifies the ID number for the string.
+
+title / title-id
+    type: string / u32, required
+
+    Specifies the title of the scene. This is shown at the top of the scene.
+
+prompt / prompt-id
+    type: string / u32, required
+
+    Specifies a prompt for the scene. This is shown at the bottom of the scene.
+
+The scene nodes have a subnode for each object in the scene.
+
+Object nodes
+~~~~~~~~~~~~
+
+The object-node name is used as the name of the object, e.g. when calling
+`scene_menu()` to create a menu.
+
+Object nodes have the following common properties:
+
+type
+    type: string, required
+
+    Specifies the type of the object. Valid types are:
+
+    "menu"
+        Menu containing items which can be selected by the user
+
+id
+    type: u32, required
+
+    Specifies the ID of the object. This is used when referring to the object.
+
+
+Menu nodes have the following additional properties:
+
+title / title-id
+    type: string / u32, required
+
+    Specifies the title of the menu. This is shown to the left of the area for
+    this menu.
+
+item-id
+    type: u32 list, required
+
+    Specifies the ID for each menu item. These are used for checking which item
+    has been selected.
+
+item-label / item-label-id
+    type: string list / u32 list, required
+
+    Specifies the label for each item in the menu. These are shown to the user.
+    In 'popup' mode these form the items in the menu.
+
+key-label / key-label-id
+    type: string list / u32 list, optional
+
+    Specifies the key for each item in the menu. These are currently only
+    intended for use in simple mode.
+
+desc-label / desc-label-id
+    type: string list / u32 list, optional
+
+    Specifies the description for each item in the menu. These are currently
+    only intended for use in simple mode.
+
+
+Expo layout
+~~~~~~~~~~~
+
+The `expo_arrange()` function can be called to arrange the expo objects in a
+suitable manner. For each scene it puts the title at the top, the prompt at the
+bottom and the objects in order from top to bottom.
+
+Expo format example
+~~~~~~~~~~~~~~~~~~~
+
+This example shows an expo with a single scene consisting of two menus. The
+scene title is specified using a string from the strings table, but all other
+strings are provided inline in the nodes where they are used.
+
+::
+
+    #define ID_PROMPT           1
+    #define ID_SCENE1           2
+    #define ID_SCENE1_TITLE     3
+
+    #define ID_CPU_SPEED        4
+    #define ID_CPU_SPEED_TITLE  5
+    #define ID_CPU_SPEED_1      6
+    #define ID_CPU_SPEED_2      7
+    #define ID_CPU_SPEED_3      8
+
+    #define ID_POWER_LOSS       9
+    #define ID_AC_OFF           10
+    #define ID_AC_ON            11
+    #define ID_AC_MEMORY        12
+
+    #define ID_DYNAMIC_START    13
+
+    &cedit {
+        dynamic-start = <ID_DYNAMIC_START>;
+
+        scenes {
+            main {
+                id = <ID_SCENE1>;
+
+                /* value refers to the matching id in /strings */
+                title-id = <ID_SCENE1_TITLE>;
+
+                /* simple string is used as it is */
+                prompt = "UP and DOWN to choose, ENTER to select";
+
+                /* defines a menu within the scene */
+                cpu-speed {
+                    type = "menu";
+                    id = <ID_CPU_SPEED>;
+
+                    /*
+                     * has both string and ID. The string is ignored
+                     * if the ID is present and points to a string
+                     */
+                    title = "CPU speed";
+                    title-id = <ID_CPU_SPEED_TITLE>;
+
+                    /* menu items as simple strings */
+                    item-label = "2 GHz", "2.5 GHz", "3 GHz";
+
+                    /* IDs for the menu items */
+                    item-id = <ID_CPU_SPEED_1 ID_CPU_SPEED_2
+                        ID_CPU_SPEED_3>;
+                };
+
+                power-loss {
+                    type = "menu";
+                    id = <ID_POWER_LOSS>;
+
+                    title = "AC Power";
+                    item-label = "Always Off", "Always On",
+                        "Memory";
+
+                    item-id = <ID_AC_OFF ID_AC_ON ID_AC_MEMORY>;
+                };
+            };
+        };
+
+        strings {
+            title {
+                id = <ID_SCENE1_TITLE>;
+                value = "Test Configuration";
+                value-es = "configuración de prueba";
+            };
+        };
+    };
+
 
 API documentation
 -----------------
@@ -166,12 +451,10 @@ Future ideas
 Some ideas for future work:
 
 - Default menu item and a timeout
-- Higher-level / automatic / more flexible layout of objects
 - Image formats other than BMP
 - Use of ANSI sequences to control a serial terminal
 - Colour selection
-- Better support for handling lots of settings, e.g. with multiple menus and
-  radio/option widgets
+- Support for more widgets, e.g. text, numeric, radio/option
 - Mouse support
 - Integrate Nuklear, NxWidgets or some other library for a richer UI
 - Optimise rendering by only updating the display with changes since last render
@@ -179,10 +462,10 @@ Some ideas for future work:
 - Add a Kconfig option to drop the names to save code / data space
 - Add a Kconfig option to disable vidconsole support to save code / data space
 - Support both graphical and text menus at the same time on different devices
-- Implement proper measurement of object bounding boxes, to permit more exact
-  layout. This would tidy up the layout when Truetype is not used
 - Support unicode
 - Support curses for proper serial-terminal menus
+- Add support for large menus which need to scroll
+- Add support for reading and writing configuration settings with cedit
 
 .. Simon Glass <sjg@chromium.org>
 .. 7-Oct-22
diff --git a/doc/develop/falcon.rst b/doc/develop/falcon.rst
new file mode 100644
index 0000000000..a569d1a295
--- /dev/null
+++ b/doc/develop/falcon.rst
@@ -0,0 +1,258 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Falcon Mode
+===========
+
+Introduction
+------------
+
+This document provides an overview of how to add support for Falcon Mode
+to a board.
+
+Falcon Mode is introduced to speed up the booting process, allowing
+to boot a Linux kernel (or whatever image) without a full blown U-Boot.
+
+Falcon Mode relies on the SPL framework. In fact, to make booting faster,
+U-Boot is split into two parts: the SPL (Secondary Program Loader) and U-Boot
+image. In most implementations, SPL is used to start U-Boot when booting from
+a mass storage, such as NAND or SD-Card. SPL has now support for other media,
+and can generally be seen as a way to start an image performing the minimum
+required initialization. SPL mainly initializes the RAM controller, and then
+copies U-Boot image into the memory.
+
+The Falcon Mode extends this way allowing to start the Linux kernel directly
+from SPL. A new command is added to U-Boot to prepare the parameters that SPL
+must pass to the kernel, using ATAGS or Device Tree.
+
+In normal mode, these parameters are generated each time before
+loading the kernel, passing to Linux the address in memory where
+the parameters can be read.
+With Falcon Mode, this snapshot can be saved into persistent storage and SPL is
+informed to load it before running the kernel.
+
+To boot the kernel, these steps under a Falcon-aware U-Boot are required:
+
+1. Boot the board into U-Boot.
+    After loading the desired legacy-format kernel image into memory (and DT as
+    well, if used), use the "spl export" command to generate the kernel
+    parameters area or the DT.  U-Boot runs as when it boots the kernel, but
+    stops before passing the control to the kernel.
+
+2. Save the prepared snapshot into persistent media.
+    The address where to save it must be configured into board configuration
+    file (CONFIG_CMD_SPL_NAND_OFS for NAND).
+
+3. Boot the board into Falcon Mode. SPL will load the kernel and copy
+    the parameters which are saved in the persistent area to the required
+    address. If a valid uImage is not found at the defined location, U-Boot
+    will be booted instead.
+
+It is required to implement a custom mechanism to select if SPL loads U-Boot
+or another image.
+
+The value of a GPIO is a simple way to operate the selection, as well as
+reading a character from the SPL console if CONFIG_SPL_CONSOLE is set.
+
+Falcon Mode is generally activated by setting CONFIG_SPL_OS_BOOT. This tells
+SPL that U-Boot is not the only available image that SPL is able to start.
+
+Configuration
+-------------
+
+CONFIG_CMD_SPL
+    Enable the "spl export" command.
+    The command "spl export" is then available in U-Boot mode.
+
+CONFIG_SYS_SPL_ARGS_ADDR
+    Address in RAM where the parameters must be copied by SPL.
+    In most cases, it is <start_of_ram> + 0x100.
+
+CONFIG_SYS_NAND_SPL_KERNEL_OFFS
+    Offset in NAND where the kernel is stored
+
+CONFIG_CMD_SPL_NAND_OFS
+    Offset in NAND where the parameters area was saved.
+
+CONFIG_CMD_SPL_NOR_OFS
+    Offset in NOR where the parameters area was saved.
+
+CONFIG_CMD_SPL_WRITE_SIZE
+    Size of the parameters area to be copied
+
+CONFIG_SPL_OS_BOOT
+    Activate Falcon Mode.
+
+Function that a board must implement
+------------------------------------
+
+void spl_board_prepare_for_linux(void)
+    optional, called from SPL before starting the kernel
+
+spl_start_uboot()
+    required, returns "0" if SPL should start the kernel, "1" if U-Boot
+    must be started.
+
+Environment variables
+---------------------
+
+A board may chose to look at the environment for decisions about falcon
+mode.  In this case the following variables may be supported:
+
+boot_os
+    Set to yes/Yes/true/True/1 to enable booting to OS,
+    any other value to fall back to U-Boot (including unset)
+
+falcon_args_file
+    Filename to load as the 'args' portion of falcon mode rather than the
+    hard-coded value.
+
+falcon_image_file
+    Filename to load as the OS image portion of falcon mode rather than the
+    hard-coded value.
+
+Using spl command
+-----------------
+
+spl - SPL configuration
+
+Usage::
+
+    spl export <img=atags|fdt> [kernel_addr] [initrd_addr] [fdt_addr ]
+
+img
+    "atags" or "fdt"
+
+kernel_addr
+    kernel is loaded as part of the boot process, but it is not started.
+    This is the address where a kernel image is stored.
+
+initrd_addr
+    Address of initial ramdisk
+    can be set to "-" if fdt_addr without initrd_addr is used
+
+fdt_addr
+    in case of fdt, the address of the device tree.
+
+The *spl export* command does not write to a storage media. The user is
+responsible to transfer the gathered information (assembled ATAGS list
+or prepared FDT) from temporary storage in RAM into persistent storage
+after each run of *spl export*. Unfortunately the position of temporary
+storage can not be predicted nor provided at command line, it depends
+highly on your system setup and your provided data (ATAGS or FDT).
+However at the end of an successful *spl export* run it will print the
+RAM address of temporary storage. The RAM address of FDT will also be
+set in the environment variable *fdtargsaddr*, the new length of the
+prepared FDT will be set in the environment variable *fdtargslen*.
+These environment variables can be used in scripts for writing updated
+FDT to persistent storage.
+
+Now the user have to save the generated BLOB from that printed address
+to the pre-defined address in persistent storage
+(CONFIG_CMD_SPL_NAND_OFS in case of NAND).
+The following example shows how to prepare the data for Falcon Mode on
+twister board with ATAGS BLOB.
+
+The *spl export* command is prepared to work with ATAGS and FDT. However,
+using FDT is at the moment untested. The ppc port (see a3m071 example
+later) prepares the fdt blob with the fdt command instead.
+
+
+Usage on the twister board
+--------------------------
+
+Using mtd names with the following (default) configuration
+for mtdparts::
+
+    device nand0 <omap2-nand.0>, # parts = 9
+     #: name        size        offset      mask_flags
+     0: MLO                 0x00080000      0x00000000      0
+     1: u-boot              0x00100000      0x00080000      0
+     2: env1                0x00040000      0x00180000      0
+     3: env2                0x00040000      0x001c0000      0
+     4: kernel              0x00600000      0x00200000      0
+     5: bootparms           0x00040000      0x00800000      0
+     6: splashimg           0x00200000      0x00840000      0
+     7: mini                0x02800000      0x00a40000      0
+     8: rootfs              0x1cdc0000      0x03240000      0
+
+::
+
+    twister => nand read 82000000 kernel
+
+    NAND read: device 0 offset 0x200000, size 0x600000
+    6291456 bytes read: OK
+
+Now the kernel is in RAM at address 0x82000000::
+
+    twister => spl export atags 0x82000000
+    ## Booting kernel from Legacy Image at 82000000 ...
+       Image Name:   Linux-3.5.0-rc4-14089-gda0b7f4
+       Image Type:   ARM Linux Kernel Image (uncompressed)
+       Data Size:    3654808 Bytes = 3.5 MiB
+       Load Address: 80008000
+       Entry Point:  80008000
+       Verifying Checksum ... OK
+       Loading Kernel Image ... OK
+    OK
+    cmdline subcommand not supported
+    bdt subcommand not supported
+    Argument image is now in RAM at: 0x80000100
+
+The result can be checked at address 0x80000100::
+
+    twister => md 0x80000100
+    80000100: 00000005 54410001 00000000 00000000    ......AT........
+    80000110: 00000000 00000067 54410009 746f6f72    ....g.....ATroot
+    80000120: 65642f3d 666e2f76 77722073 73666e20    =/dev/nfs rw nfs
+
+The parameters generated with this step can be saved into NAND at the offset
+0x800000 (value for twister for CONFIG_CMD_SPL_NAND_OFS)::
+
+    nand erase.part bootparms
+    nand write 0x80000100 bootparms 0x4000
+
+Now the parameters are stored into the NAND flash at the address
+CONFIG_CMD_SPL_NAND_OFS (=0x800000).
+
+Next time, the board can be started into Falcon Mode moving the
+setting the GPIO (on twister GPIO 55 is used) to kernel mode.
+
+The kernel is loaded directly by the SPL without passing through U-Boot.
+
+Example with FDT: a3m071 board
+-------------------------------
+
+To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
+prepared/patched first. U-Boot usually inserts some dynamic values into
+the DT binary (blob), e.g. autodetected memory size, MAC addresses,
+clocks speeds etc. To generate this patched DT blob, you can use
+the following command:
+
+1. Load fdt blob to SDRAM::
+
+        => tftp 1800000 a3m071/a3m071.dtb
+
+2. Set bootargs as desired for Linux booting (e.g. flash_mtd)::
+
+        => run mtdargs addip2 addtty
+
+3. Use "fdt" commands to patch the DT blob::
+
+        => fdt addr 1800000
+        => fdt boardsetup
+        => fdt chosen
+
+4. Display patched DT blob (optional)::
+
+        => fdt print
+
+5. Save fdt to NOR flash::
+
+        => erase fc060000 fc07ffff
+        => cp.b 1800000 fc060000 10000
+        ...
+
+
+Falcon Mode was presented at the RMLL 2012. Slides are available at:
+
+http://schedule2012.rmll.info/IMG/pdf/LSM2012_UbootFalconMode_Babic.pdf
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index ddbf8dad4a..5b230d0321 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -9,6 +9,7 @@ General
 .. toctree::
    :maxdepth: 1
 
+   board_best_practices
    codingstyle
    designprinciples
    docstyle
@@ -45,6 +46,7 @@ Implementation
    printf
    smbios
    spl
+   falcon
    uefi/index
    vbe
    version
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 2c82783a89..752e1304d3 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -48,13 +48,13 @@ Examples::
 Current Status
 --------------
 
-* U-Boot v2023.04 was released on Mon 03 April 2023.
+* U-Boot v2023.07 was released on Mon 10 July 2023.
 
-* The Merge Window for the next release (v2023.07) is **closed**.
+* The Merge Window for the next release (v2023.10) is **closed**.
 
 * The next branch is now **open**.
 
-* Release "v2023.07" is scheduled for 03 July 2023.
+* Release "v2023.10" is scheduled for 02 October 2023.
 
 Future Releases
 ---------------
@@ -64,27 +64,27 @@ Future Releases
 
 For the next scheduled release, release candidates were made on::
 
-* U-Boot v2023.07-rc1 was released on Mon 01 May 2023.
+* U-Boot v2023.10-rc1 was released on Tue 25 July 2023.
 
-* U-Boot v2023.07-rc2 was released on Mon 08 May 2023.
+* U-Boot v2023.10-rc2 was released on Mon 07 August 2023.
 
-* U-Boot v2023.07-rc3 was released on Mon 29 May 2023.
+.. * U-Boot v2023.10-rc3 was released on Mon 21 August 2023.
 
-* U-Boot v2023.07-rc4 was released on Mon 12 June 2023.
+.. * U-Boot v2023.10-rc4 was released on Mon 04 September 2023.
 
-.. * U-Boot v2023.07-rc5 was released on Mon 19 June 2023.
+.. * U-Boot v2023.10-rc5 was released on Mon 18 September 2023.
 
 Please note that the following dates are planned only and may be deviated from
 as needed.
 
-* "v2023.07": end of MW = Mon, Apr 24, 2023; release = Mon, Jul 03, 2023 
-
 * "v2023.10": end of MW = Mon, Jul 24, 2023; release = Mon, Oct 02, 2023
 
 * "v2024.01": end of MW = Mon, Oct 23, 2023; release = Mon, Jan 08, 2024
 
 * "v2024.04": end of MW = Mon, Jan 29, 2024; release = Tue, Apr 02, 2024
 
+* "v2024.07": end of MW = Mon, Apr 22, 2024; release = Mon, Jul 01, 2024
+
 Previous Releases
 -----------------
 
@@ -92,6 +92,8 @@ Note: these statistics are generated by our fork of `gitdm
 <https://source.denx.de/u-boot/gitdm>`_, which was originally created by
 Jonathan Corbet.
 
+* :doc:`statistics/u-boot-stats-v2023.07` which was released on 10 July 2023.
+
 * :doc:`statistics/u-boot-stats-v2023.04` which was released on 03 April 2023.
 
 * :doc:`statistics/u-boot-stats-v2023.01` which was released on 09 January 2023.
diff --git a/doc/develop/spl.rst b/doc/develop/spl.rst
index a1515a7b43..76e87f07c7 100644
--- a/doc/develop/spl.rst
+++ b/doc/develop/spl.rst
@@ -77,10 +77,11 @@ To check whether a feature is enabled, use CONFIG_IS_ENABLED()::
 This checks CONFIG_CLK for the main build, CONFIG_SPL_CLK for the SPL build,
 CONFIG_TPL_CLK for the TPL build, etc.
 
-U-Boot Phases
--------------
+U-Boot Boot Phases
+------------------
 
-U-Boot boots through the following phases:
+U-Boot goes through the following boot phases where TPL, VPL, SPL are optional.
+While many boards use SPL, less use TPL.
 
 TPL
    Very early init, as tiny as possible. This loads SPL (or VPL if enabled).
@@ -97,6 +98,12 @@ SPL
 U-Boot
    U-Boot proper, containing the command line and boot logic.
 
+Further usages of U-Boot SPL comprise:
+
+* Launching BL31 of ARM Trusted Firmware which invokes main U-Boot as BL33
+* launching EDK II
+* launching Linux kernel
+* launching RISC-V OpenSBI which invokes main U-Boot
 
 Checking the boot phase
 -----------------------
diff --git a/doc/develop/statistics/u-boot-stats-v2022.10.rst b/doc/develop/statistics/u-boot-stats-v2022.10.rst
index 6fb71d4753..7a5fc2edc7 100644
--- a/doc/develop/statistics/u-boot-stats-v2022.10.rst
+++ b/doc/develop/statistics/u-boot-stats-v2022.10.rst
@@ -607,20 +607,21 @@ Release Statistics for U-Boot v2022.10
    ====================================  =====
    Name                                  Count
    ====================================  =====
-   (Unknown)                             590 (38.8%)
+   (Unknown)                             584 (38.4%)
    Konsulko Group                        265 (17.4%)
    Google, Inc.                          141 (9.3%)
    NXP                                   77 (5.1%)
+   AMD                                   70 (4.6%)
    ST Microelectronics                   67 (4.4%)
    Linaro                                60 (3.9%)
    Texas Instruments                     56 (3.7%)
-   AMD                                   53 (3.5%)
    DENX Software Engineering             45 (3.0%)
    Toradex                               45 (3.0%)
    Weidmüller Interface GmbH & Co. KG    41 (2.7%)
-   Xilinx                                29 (1.9%)
    Amarula Solutions                     18 (1.2%)
+   Xilinx                                12 (0.8%)
    ARM                                   11 (0.7%)
+   Collabora Ltd.                        7 (0.5%)
    BayLibre SAS                          5 (0.3%)
    SUSE                                  4 (0.3%)
    Socionext Inc.                        3 (0.2%)
@@ -628,7 +629,6 @@ Release Statistics for U-Boot v2022.10
    IBM                                   2 (0.1%)
    Siemens                               2 (0.1%)
    Broadcom                              1 (0.1%)
-   Collabora Ltd.                        1 (0.1%)
    Debian.org                            1 (0.1%)
    Marvell                               1 (0.1%)
    Samsung                               1 (0.1%)
@@ -642,7 +642,7 @@ Release Statistics for U-Boot v2022.10
    Name                                  Count
    ====================================  =====
    Konsulko Group                        98915 (47.3%)
-   (Unknown)                             36773 (17.6%)
+   (Unknown)                             36630 (17.5%)
    Toradex                               20197 (9.7%)
    NXP                                   11759 (5.6%)
    Google, Inc.                          8739 (4.2%)
@@ -651,12 +651,13 @@ Release Statistics for U-Boot v2022.10
    Texas Instruments                     5930 (2.8%)
    ST Microelectronics                   3803 (1.8%)
    DENX Software Engineering             3551 (1.7%)
-   AMD                                   2343 (1.1%)
+   AMD                                   2591 (1.2%)
    Amarula Solutions                     1360 (0.7%)
-   Xilinx                                1016 (0.5%)
+   Xilinx                                768 (0.4%)
    Broadcom                              315 (0.2%)
    ARM                                   298 (0.1%)
    BayLibre SAS                          197 (0.1%)
+   Collabora Ltd.                        144 (0.1%)
    SUSE                                  79 (0.0%)
    IBM                                   34 (0.0%)
    Bootlin                               32 (0.0%)
@@ -665,7 +666,6 @@ Release Statistics for U-Boot v2022.10
    Debian.org                            4 (0.0%)
    Marvell                               3 (0.0%)
    Samsung                               2 (0.0%)
-   Collabora Ltd.                        1 (0.0%)
    ====================================  =====
 
 
@@ -677,13 +677,14 @@ Release Statistics for U-Boot v2022.10
    ====================================  =====
    AMD                                   81 (30.5%)
    NXP                                   51 (19.2%)
-   (Unknown)                             33 (12.4%)
+   (Unknown)                             28 (10.5%)
    Texas Instruments                     19 (7.1%)
    Linaro                                16 (6.0%)
    ARM                                   16 (6.0%)
    Amarula Solutions                     14 (5.3%)
    Xilinx                                13 (4.9%)
    Konsulko Group                        6 (2.3%)
+   Canonical                             5 (1.9%)
    Toradex                               4 (1.5%)
    Google, Inc.                          4 (1.5%)
    Socionext Inc.                        4 (1.5%)
@@ -699,19 +700,20 @@ Release Statistics for U-Boot v2022.10
    ====================================  =====
    Name                                  Count
    ====================================  =====
-   (Unknown)                             78 (51.0%)
+   (Unknown)                             77 (50.3%)
    Linaro                                12 (7.8%)
    Texas Instruments                     11 (7.2%)
    NXP                                   7 (4.6%)
+   AMD                                   6 (3.9%)
    Google, Inc.                          5 (3.3%)
    DENX Software Engineering             5 (3.3%)
-   Xilinx                                4 (2.6%)
    Toradex                               4 (2.6%)
    ST Microelectronics                   4 (2.6%)
-   AMD                                   3 (2.0%)
    ARM                                   3 (2.0%)
    BayLibre SAS                          3 (2.0%)
    Amarula Solutions                     2 (1.3%)
+   Collabora Ltd.                        2 (1.3%)
+   Xilinx                                1 (0.7%)
    Konsulko Group                        1 (0.7%)
    Socionext Inc.                        1 (0.7%)
    Broadcom                              1 (0.7%)
@@ -723,5 +725,4 @@ Release Statistics for U-Boot v2022.10
    Debian.org                            1 (0.7%)
    Marvell                               1 (0.7%)
    Samsung                               1 (0.7%)
-   Collabora Ltd.                        1 (0.7%)
    ====================================  =====
diff --git a/doc/develop/statistics/u-boot-stats-v2023.01.rst b/doc/develop/statistics/u-boot-stats-v2023.01.rst
index 2fd34bb5ee..793aaa5bbb 100644
--- a/doc/develop/statistics/u-boot-stats-v2023.01.rst
+++ b/doc/develop/statistics/u-boot-stats-v2023.01.rst
@@ -5,7 +5,7 @@ Release Statistics for U-Boot v2023.01
 
 * Processed 1396 changesets from 152 developers
 
-* 23 employers found
+* 24 employers found
 
 * A total of 91252 lines added, 42422 removed (delta 48830)
 
@@ -603,11 +603,11 @@ Release Statistics for U-Boot v2023.01
    ====================================  =====
    Name                                  Count
    ====================================  =====
-   (Unknown)                             557 (39.9%)
+   (Unknown)                             556 (39.8%)
    Google, Inc.                          270 (19.3%)
+   AMD                                   90 (6.4%)
    DENX Software Engineering             86 (6.2%)
    Linaro                                85 (6.1%)
-   AMD                                   80 (5.7%)
    Konsulko Group                        48 (3.4%)
    ST Microelectronics                   47 (3.4%)
    SUSE                                  36 (2.6%)
@@ -616,16 +616,17 @@ Release Statistics for U-Boot v2023.01
    Broadcom                              27 (1.9%)
    Texas Instruments                     26 (1.9%)
    Amarula Solutions                     24 (1.7%)
-   Xilinx                                13 (0.9%)
    NXP                                   8 (0.6%)
    BayLibre SAS                          6 (0.4%)
    Collabora Ltd.                        6 (0.4%)
    Weidmüller Interface GmbH & Co. KG    6 (0.4%)
    Socionext Inc.                        4 (0.3%)
+   Xilinx                                3 (0.2%)
    Edgeble AI Technologies Pvt. Ltd.     1 (0.1%)
    Marvell                               1 (0.1%)
    Rockchip                              1 (0.1%)
    Siemens                               1 (0.1%)
+   Canonical                             1 (0.1%)
    ====================================  =====
 
 
@@ -635,7 +636,7 @@ Release Statistics for U-Boot v2023.01
    ====================================  =====
    Name                                  Count
    ====================================  =====
-   (Unknown)                             41561 (37.8%)
+   (Unknown)                             41551 (37.8%)
    Google, Inc.                          19204 (17.5%)
    Linaro                                11194 (10.2%)
    Toradex                               6724 (6.1%)
@@ -644,18 +645,19 @@ Release Statistics for U-Boot v2023.01
    Collabora Ltd.                        3312 (3.0%)
    Amarula Solutions                     3308 (3.0%)
    ST Microelectronics                   3303 (3.0%)
+   AMD                                   2379 (2.2%)
    Texas Instruments                     2174 (2.0%)
    DENX Software Engineering             2105 (1.9%)
-   AMD                                   2105 (1.9%)
    ARM                                   1569 (1.4%)
    SUSE                                  478 (0.4%)
    Weidmüller Interface GmbH & Co. KG    448 (0.4%)
    NXP                                   446 (0.4%)
-   Xilinx                                280 (0.3%)
    Marvell                               200 (0.2%)
    Socionext Inc.                        76 (0.1%)
    BayLibre SAS                          65 (0.1%)
+   Canonical                             10 (0.0%)
    Siemens                               9 (0.0%)
+   Xilinx                                6 (0.0%)
    Edgeble AI Technologies Pvt. Ltd.     1 (0.0%)
    Rockchip                              1 (0.0%)
    ====================================  =====
@@ -669,47 +671,49 @@ Release Statistics for U-Boot v2023.01
    ====================================  =====
    AMD                                   79 (46.7%)
    Amarula Solutions                     27 (16.0%)
-   (Unknown)                             22 (13.0%)
+   (Unknown)                             18 (10.7%)
    DENX Software Engineering             10 (5.9%)
    NXP                                   7 (4.1%)
    Linaro                                5 (3.0%)
    Google, Inc.                          4 (2.4%)
    ST Microelectronics                   4 (2.4%)
    ARM                                   4 (2.4%)
+   Canonical                             4 (2.4%)
    Texas Instruments                     3 (1.8%)
    Konsulko Group                        2 (1.2%)
    BayLibre SAS                          2 (1.2%)
    ====================================  =====
 
 
-.. table:: Employers with the most hackers (total 154)
+.. table:: Employers with the most hackers (total 153)
    :widths: auto
 
    ====================================  =====
    Name                                  Count
    ====================================  =====
-   (Unknown)                             81 (52.6%)
-   Linaro                                9 (5.8%)
+   (Unknown)                             80 (52.3%)
+   AMD                                   9 (5.9%)
+   Linaro                                9 (5.9%)
    Texas Instruments                     8 (5.2%)
-   AMD                                   7 (4.5%)
    ST Microelectronics                   6 (3.9%)
-   DENX Software Engineering             5 (3.2%)
+   DENX Software Engineering             5 (3.3%)
    Amarula Solutions                     4 (2.6%)
    Toradex                               4 (2.6%)
-   Xilinx                                4 (2.6%)
-   NXP                                   3 (1.9%)
-   Google, Inc.                          3 (1.9%)
-   ARM                                   3 (1.9%)
-   BayLibre SAS                          3 (1.9%)
+   NXP                                   3 (2.0%)
+   Google, Inc.                          3 (2.0%)
+   ARM                                   3 (2.0%)
+   BayLibre SAS                          3 (2.0%)
    Collabora Ltd.                        2 (1.3%)
    SUSE                                  2 (1.3%)
    Weidmüller Interface GmbH & Co. KG    2 (1.3%)
    Socionext Inc.                        2 (1.3%)
-   Konsulko Group                        1 (0.6%)
-   Broadcom                              1 (0.6%)
-   Marvell                               1 (0.6%)
-   Siemens                               1 (0.6%)
-   Edgeble AI Technologies Pvt. Ltd.     1 (0.6%)
-   Rockchip                              1 (0.6%)
+   Canonical                             1 (0.7%)
+   Konsulko Group                        1 (0.7%)
+   Broadcom                              1 (0.7%)
+   Marvell                               1 (0.7%)
+   Siemens                               1 (0.7%)
+   Xilinx                                1 (0.7%)
+   Edgeble AI Technologies Pvt. Ltd.     1 (0.7%)
+   Rockchip                              1 (0.7%)
    ====================================  =====
 
diff --git a/doc/develop/statistics/u-boot-stats-v2023.04.rst b/doc/develop/statistics/u-boot-stats-v2023.04.rst
index 57f2efc30e..73a3583e9f 100644
--- a/doc/develop/statistics/u-boot-stats-v2023.04.rst
+++ b/doc/develop/statistics/u-boot-stats-v2023.04.rst
@@ -5,7 +5,7 @@ Release Statistics for U-Boot v2023.04
 
 * Processed 1691 changesets from 157 developers
 
-* 29 employers found
+* 28 employers found
 
 * A total of 174471 lines added, 78380 removed (delta 96091)
 
@@ -631,17 +631,17 @@ Release Statistics for U-Boot v2023.04
    ====================================  =====
    Name                                  Count
    ====================================  =====
-   (Unknown)                             524 (31.0%)
+   (Unknown)                             464 (27.4%)
    Google, Inc.                          381 (22.5%)
    Konsulko Group                        333 (19.7%)
+   Renesas Electronics                   84 (5.0%)
    DENX Software Engineering             72 (4.3%)
    Texas Instruments                     49 (2.9%)
    Linaro                                47 (2.8%)
    Edgeble AI Technologies Pvt. Ltd.     46 (2.7%)
    ST Microelectronics                   40 (2.4%)
-   AMD                                   34 (2.0%)
+   AMD                                   35 (2.1%)
    NXP                                   25 (1.5%)
-   Renesas Electronics                   24 (1.4%)
    Toradex                               24 (1.4%)
    Amarula Solutions                     20 (1.2%)
    Collabora Ltd.                        20 (1.2%)
@@ -659,7 +659,6 @@ Release Statistics for U-Boot v2023.04
    Intel                                 1 (0.1%)
    linutronix                            1 (0.1%)
    Samsung                               1 (0.1%)
-   Xilinx                                1 (0.1%)
    ====================================  =====
 
 
@@ -669,18 +668,18 @@ Release Statistics for U-Boot v2023.04
    ====================================  =====
    Name                                  Count
    ====================================  =====
-   (Unknown)                             64681 (30.1%)
+   (Unknown)                             51007 (23.8%)
    Texas Instruments                     42105 (19.6%)
    Konsulko Group                        36464 (17.0%)
    Google, Inc.                          30090 (14.0%)
    Edgeble AI Technologies Pvt. Ltd.     23070 (10.7%)
+   Renesas Electronics                   14449 (6.7%)
    Linaro                                4601 (2.1%)
    DENX Software Engineering             4582 (2.1%)
-   AMD                                   1741 (0.8%)
+   AMD                                   1744 (0.8%)
    Amarula Solutions                     1649 (0.8%)
    ST Microelectronics                   882 (0.4%)
    Bootlin                               860 (0.4%)
-   Renesas Electronics                   775 (0.4%)
    Socionext Inc.                        760 (0.4%)
    ARM                                   724 (0.3%)
    Collabora Ltd.                        413 (0.2%)
@@ -695,7 +694,6 @@ Release Statistics for U-Boot v2023.04
    Pengutronix                           13 (0.0%)
    Samsung                               9 (0.0%)
    Ronetix                               4 (0.0%)
-   Xilinx                                3 (0.0%)
    Intel                                 1 (0.0%)
    linutronix                            1 (0.0%)
    ====================================  =====
@@ -707,14 +705,14 @@ Release Statistics for U-Boot v2023.04
    ====================================  =====
    Name                                  Count
    ====================================  =====
-   (Unknown)                             48 (22.3%)
+   Renesas Electronics                   30 (14.0%)
    Rockchip                              29 (13.5%)
    Toradex                               28 (13.0%)
+   (Unknown)                             27 (12.6%)
    Amarula Solutions                     24 (11.2%)
    AMD                                   23 (10.7%)
    NVidia                                19 (8.8%)
    Linaro                                9 (4.2%)
-   Renesas Electronics                   9 (4.2%)
    Texas Instruments                     5 (2.3%)
    Konsulko Group                        5 (2.3%)
    NXP                                   4 (1.9%)
@@ -734,18 +732,18 @@ Release Statistics for U-Boot v2023.04
    ====================================  =====
    Name                                  Count
    ====================================  =====
-   (Unknown)                             86 (53.8%)
+   (Unknown)                             85 (53.1%)
    Linaro                                9 (5.6%)
    Texas Instruments                     8 (5.0%)
-   AMD                                   6 (3.8%)
+   AMD                                   7 (4.4%)
    Collabora Ltd.                        6 (3.8%)
    Toradex                               5 (3.1%)
    DENX Software Engineering             5 (3.1%)
    Amarula Solutions                     4 (2.5%)
    NXP                                   4 (2.5%)
+   Renesas Electronics                   3 (1.9%)
    ARM                                   3 (1.9%)
    ST Microelectronics                   3 (1.9%)
-   Renesas Electronics                   2 (1.2%)
    SUSE                                  2 (1.2%)
    Socionext Inc.                        2 (1.2%)
    Konsulko Group                        1 (0.6%)
@@ -761,7 +759,6 @@ Release Statistics for U-Boot v2023.04
    Pengutronix                           1 (0.6%)
    Samsung                               1 (0.6%)
    Ronetix                               1 (0.6%)
-   Xilinx                                1 (0.6%)
    linutronix                            1 (0.6%)
    ====================================  =====
 
diff --git a/doc/develop/statistics/u-boot-stats-v2023.07.rst b/doc/develop/statistics/u-boot-stats-v2023.07.rst
new file mode 100644
index 0000000000..4c8b47161c
--- /dev/null
+++ b/doc/develop/statistics/u-boot-stats-v2023.07.rst
@@ -0,0 +1,844 @@
+:orphan:
+
+Release Statistics for U-Boot v2023.07
+======================================
+
+* Processed 1668 changesets from 187 developers
+
+* 27 employers found
+
+* A total of 120881 lines added, 46887 removed (delta 73994)
+
+.. table:: Developers with the most changesets
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Simon Glass                           224 (13.4%)
+   Marek Vasut                           173 (10.4%)
+   Pali Rohár                            92 (5.5%)
+   Heinrich Schuchardt                   79 (4.7%)
+   Tom Rini                              60 (3.6%)
+   Jonas Karlman                         51 (3.1%)
+   Christian Hewitt                      47 (2.8%)
+   Peng Fan                              39 (2.3%)
+   Johan Jonker                          39 (2.3%)
+   Andrew Davis                          32 (1.9%)
+   Ye Li                                 32 (1.9%)
+   Christophe Leroy                      31 (1.9%)
+   Hai Pham                              25 (1.5%)
+   Bin Meng                              23 (1.4%)
+   Ioana Ciornei                         23 (1.4%)
+   Nikhil M Jain                         22 (1.3%)
+   Fabio Estevam                         21 (1.3%)
+   Manorit Chawdhry                      21 (1.3%)
+   Samuel Holland                        21 (1.3%)
+   Svyatoslav Ryhel                      21 (1.3%)
+   Eugen Hristev                         20 (1.2%)
+   Mathew McBride                        19 (1.1%)
+   Safae Ouajih                          19 (1.1%)
+   Rasmus Villemoes                      18 (1.1%)
+   Yanhong Wang                          16 (1.0%)
+   Eduard Strehlau                       14 (0.8%)
+   Michal Simek                          13 (0.8%)
+   Jan Kiszka                            13 (0.8%)
+   Dzmitry Sankouski                     13 (0.8%)
+   Kunihiko Hayashi                      12 (0.7%)
+   Ilias Apalodimas                      11 (0.7%)
+   FUKAUMI Naoki                         11 (0.7%)
+   Ralph Siemsen                         10 (0.6%)
+   Jernej Skrabec                        10 (0.6%)
+   Tobias Waldekranz                     9 (0.5%)
+   Tim Harvey                            8 (0.5%)
+   Neha Francis                          8 (0.5%)
+   John Keeping                          8 (0.5%)
+   Ashok Reddy Soma                      8 (0.5%)
+   Andre Przywara                        7 (0.4%)
+   Andrejs Cainikovs                     7 (0.4%)
+   Stefan Herbrechtsmeier                7 (0.4%)
+   Vladimir Zapolskiy                    7 (0.4%)
+   Abdellatif El Khlifi                  7 (0.4%)
+   Angelo Dureghello                     7 (0.4%)
+   Marcel Ziswiler                       7 (0.4%)
+   Sean Edmond                           6 (0.4%)
+   Jacky Bai                             6 (0.4%)
+   Patrick Delaunay                      6 (0.4%)
+   Linus Walleij                         6 (0.4%)
+   Peter Hoyes                           6 (0.4%)
+   Will Deacon                           6 (0.4%)
+   Patrice Chotard                       6 (0.4%)
+   Emanuele Ghidoli                      6 (0.4%)
+   Álvaro Fernández Rojas                6 (0.4%)
+   Algapally Santosh Sagar               5 (0.3%)
+   Baruch Siach                          5 (0.3%)
+   Chris Morgan                          5 (0.3%)
+   Hugo Villeneuve                       5 (0.3%)
+   Marc Zyngier                          5 (0.3%)
+   Tho Vu                                5 (0.3%)
+   Ovidiu Panait                         5 (0.3%)
+   Chunfeng Yun                          5 (0.3%)
+   Josua Mayer                           4 (0.2%)
+   Thomas RIENOESSL                      4 (0.2%)
+   Yang Xiwen                            4 (0.2%)
+   Dario Binacchi                        4 (0.2%)
+   Tony Dinh                             4 (0.2%)
+   Evgeny Bachinin                       4 (0.2%)
+   Sergiu Moga                           4 (0.2%)
+   Xavier Drudis Ferran                  3 (0.2%)
+   Sam Edwards                           3 (0.2%)
+   Dhruva Gole                           3 (0.2%)
+   Stefan Roese                          3 (0.2%)
+   Jon Lin                               3 (0.2%)
+   Christian Gmeiner                     3 (0.2%)
+   Ehsan Mohandesi                       3 (0.2%)
+   Nishanth Menon                        3 (0.2%)
+   Dmitrii Merkurev                      3 (0.2%)
+   Pavel Skripkin                        3 (0.2%)
+   Karl Chan                             3 (0.2%)
+   Frieder Schrempf                      3 (0.2%)
+   Martin Rowe                           3 (0.2%)
+   Loic Poulain                          3 (0.2%)
+   Corentin Guillevic                    3 (0.2%)
+   Markus Niebel                         3 (0.2%)
+   Ivan Mikhaylov                        3 (0.2%)
+   Stephen Carlson                       3 (0.2%)
+   Krzysztof Kozlowski                   3 (0.2%)
+   Kamal Dasu                            3 (0.2%)
+   Francesco Dolcini                     2 (0.1%)
+   Ondrej Jirman                         2 (0.1%)
+   Mark Kettenis                         2 (0.1%)
+   Neil Armstrong                        2 (0.1%)
+   Quentin Schulz                        2 (0.1%)
+   Henrik Grimler                        2 (0.1%)
+   Neal Frager                           2 (0.1%)
+   Judith Mendez                         2 (0.1%)
+   Sergei Antonov                        2 (0.1%)
+   Kishon Vijay Abraham I                2 (0.1%)
+   Daniel Golle                          2 (0.1%)
+   Bhupesh Sharma                        2 (0.1%)
+   Konrad Dybcio                         2 (0.1%)
+   Apurva Nandan                         2 (0.1%)
+   Christophe Kerello                    2 (0.1%)
+   Phong Hoang                           2 (0.1%)
+   Roman Kopytin                         2 (0.1%)
+   Chris Packham                         2 (0.1%)
+   Philippe Schenker                     2 (0.1%)
+   Janne Grunau                          2 (0.1%)
+   Sinthu Raja                           2 (0.1%)
+   chao zeng                             2 (0.1%)
+   Su Baocheng                           2 (0.1%)
+   Dylan Hung                            2 (0.1%)
+   Heiko Schocher                        1 (0.1%)
+   Ken Sloat                             1 (0.1%)
+   Kever Yang                            1 (0.1%)
+   Peter Robinson                        1 (0.1%)
+   Mingli Yu                             1 (0.1%)
+   Frank Wunderlich                      1 (0.1%)
+   Teik Heng Chong                       1 (0.1%)
+   Clément Léger                         1 (0.1%)
+   Thomas Perrot                         1 (0.1%)
+   Ilko Iliev                            1 (0.1%)
+   Mayuresh Chitale                      1 (0.1%)
+   Detlev Casanova                       1 (0.1%)
+   Adam Ford                             1 (0.1%)
+   LUU HOAI                              1 (0.1%)
+   Hiroyuki Yokoyama                     1 (0.1%)
+   Mattijs Korpershoek                   1 (0.1%)
+   Ben Dooks                             1 (0.1%)
+   Andrea Merello                        1 (0.1%)
+   Dave Gerlach                          1 (0.1%)
+   Bryan Brattlof                        1 (0.1%)
+   Fedor Ross                            1 (0.1%)
+   Wadim Egorov                          1 (0.1%)
+   Wolfgang Zarre                        1 (0.1%)
+   Christopher Obbard                    1 (0.1%)
+   Joseph Chen                           1 (0.1%)
+   Raphael Gallais-Pou                   1 (0.1%)
+   Nuno Sá                               1 (0.1%)
+   Tianling Shen                         1 (0.1%)
+   Vignesh Raghavendra                   1 (0.1%)
+   Dominique Martinet                    1 (0.1%)
+   Christian Kohlschütter                1 (0.1%)
+   Michael Trimarchi                     1 (0.1%)
+   Ying-Chun Liu (PaulLiu)               1 (0.1%)
+   Elmar Psilog                          1 (0.1%)
+   Praneeth Bajjuri                      1 (0.1%)
+   Alexander Shirokov                    1 (0.1%)
+   Nitin Yadav                           1 (0.1%)
+   Aradhya Bhatia                        1 (0.1%)
+   Oliver Graute                         1 (0.1%)
+   Patrick Wildt                         1 (0.1%)
+   Jorge Ramirez-Ortiz                   1 (0.1%)
+   Takahiro Kuwano                       1 (0.1%)
+   Sinan Akman                           1 (0.1%)
+   Devarsh Thakkar                       1 (0.1%)
+   Jayesh Choudhary                      1 (0.1%)
+   meitao                                1 (0.1%)
+   Jim Liu                               1 (0.1%)
+   Peter Geis                            1 (0.1%)
+   Jonathan Liu                          1 (0.1%)
+   Jianqun Xu                            1 (0.1%)
+   Vasily Khoruzhick                     1 (0.1%)
+   Kuan Lim Lee                          1 (0.1%)
+   Jianlong Huang                        1 (0.1%)
+   Lionel Debieve                        1 (0.1%)
+   ETIENNE DUBLE                         1 (0.1%)
+   Haibo Chen                            1 (0.1%)
+   Francis Laniel                        1 (0.1%)
+   Tim Lee                               1 (0.1%)
+   Vladimir Oltean                       1 (0.1%)
+   Luca Ceresoli                         1 (0.1%)
+   Quanyang Wang                         1 (0.1%)
+   Tommaso Merciai                       1 (0.1%)
+   Igor Opaniuk                          1 (0.1%)
+   Max Krummenacher                      1 (0.1%)
+   Jean-Marie Lemetayer                  1 (0.1%)
+   Stefan Eichenberger                   1 (0.1%)
+   Claudiu Beznea                        1 (0.1%)
+   Mikhail Lappo                         1 (0.1%)
+   Jiajie Chen                           1 (0.1%)
+   Michael Grzeschik                     1 (0.1%)
+   Pierre-Clément Tosi                   1 (0.1%)
+   Ryan Chen                             1 (0.1%)
+   Claire Lin                            1 (0.1%)
+   ====================================  =====
+
+
+.. table:: Developers with the most changed lines
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Simon Glass                           14640 (10.3%)
+   Marek Vasut                           11805 (8.3%)
+   Dzmitry Sankouski                     9062 (6.4%)
+   Tom Rini                              8562 (6.0%)
+   Hai Pham                              7139 (5.0%)
+   Yanhong Wang                          7001 (4.9%)
+   Christophe Leroy                      6098 (4.3%)
+   Peng Fan                              5493 (3.9%)
+   Ralph Siemsen                         5477 (3.8%)
+   Christian Hewitt                      5207 (3.7%)
+   Ioana Ciornei                         4038 (2.8%)
+   Adam Ford                             3578 (2.5%)
+   Svyatoslav Ryhel                      3377 (2.4%)
+   Chris Morgan                          3010 (2.1%)
+   Andrew Davis                          2844 (2.0%)
+   Phong Hoang                           2503 (1.8%)
+   LUU HOAI                              2126 (1.5%)
+   Manorit Chawdhry                      2116 (1.5%)
+   Patrick Wildt                         1766 (1.2%)
+   Ye Li                                 1710 (1.2%)
+   Pali Rohár                            1592 (1.1%)
+   Eugen Hristev                         1463 (1.0%)
+   Heinrich Schuchardt                   1353 (0.9%)
+   Kunihiko Hayashi                      1335 (0.9%)
+   Tobias Waldekranz                     1242 (0.9%)
+   Sean Edmond                           1182 (0.8%)
+   Oliver Graute                         1155 (0.8%)
+   FUKAUMI Naoki                         1140 (0.8%)
+   Mathew McBride                        1129 (0.8%)
+   Linus Walleij                         1117 (0.8%)
+   Safae Ouajih                          1098 (0.8%)
+   Jonas Karlman                         1005 (0.7%)
+   Kuan Lim Lee                          1001 (0.7%)
+   Johan Jonker                          872 (0.6%)
+   Nikhil M Jain                         801 (0.6%)
+   Jan Kiszka                            718 (0.5%)
+   Abdellatif El Khlifi                  677 (0.5%)
+   Tho Vu                                661 (0.5%)
+   Neil Armstrong                        646 (0.5%)
+   Neha Francis                          588 (0.4%)
+   Yang Xiwen                            588 (0.4%)
+   Fabio Estevam                         575 (0.4%)
+   Jianqun Xu                            541 (0.4%)
+   Jernej Skrabec                        525 (0.4%)
+   Chris Packham                         498 (0.3%)
+   Ehsan Mohandesi                       459 (0.3%)
+   Samuel Holland                        441 (0.3%)
+   Jianlong Huang                        427 (0.3%)
+   Jacky Bai                             402 (0.3%)
+   Andre Przywara                        388 (0.3%)
+   Emanuele Ghidoli                      375 (0.3%)
+   Dmitrii Merkurev                      366 (0.3%)
+   Rasmus Villemoes                      341 (0.2%)
+   Ivan Mikhaylov                        336 (0.2%)
+   Angelo Dureghello                     335 (0.2%)
+   Kever Yang                            319 (0.2%)
+   Marc Zyngier                          315 (0.2%)
+   Daniel Golle                          304 (0.2%)
+   Karl Chan                             290 (0.2%)
+   Roman Kopytin                         290 (0.2%)
+   Su Baocheng                           249 (0.2%)
+   Stephen Carlson                       245 (0.2%)
+   Sergiu Moga                           244 (0.2%)
+   Sergei Antonov                        242 (0.2%)
+   Tim Harvey                            227 (0.2%)
+   Chunfeng Yun                          208 (0.1%)
+   Ilias Apalodimas                      192 (0.1%)
+   Aradhya Bhatia                        187 (0.1%)
+   Mark Kettenis                         177 (0.1%)
+   Kamal Dasu                            165 (0.1%)
+   Eduard Strehlau                       162 (0.1%)
+   Tianling Shen                         162 (0.1%)
+   Thomas RIENOESSL                      145 (0.1%)
+   ETIENNE DUBLE                         142 (0.1%)
+   Lionel Debieve                        132 (0.1%)
+   Kishon Vijay Abraham I                131 (0.1%)
+   chao zeng                             129 (0.1%)
+   Will Deacon                           126 (0.1%)
+   Vladimir Zapolskiy                    118 (0.1%)
+   Martin Rowe                           118 (0.1%)
+   Xavier Drudis Ferran                  114 (0.1%)
+   Ashok Reddy Soma                      105 (0.1%)
+   Álvaro Fernández Rojas                102 (0.1%)
+   Jon Lin                               101 (0.1%)
+   Bin Meng                              93 (0.1%)
+   Algapally Santosh Sagar               85 (0.1%)
+   Ovidiu Panait                         85 (0.1%)
+   Takahiro Kuwano                       85 (0.1%)
+   Michal Simek                          83 (0.1%)
+   Evgeny Bachinin                       83 (0.1%)
+   Marcel Ziswiler                       82 (0.1%)
+   Stefan Herbrechtsmeier                80 (0.1%)
+   Joseph Chen                           77 (0.1%)
+   Dario Binacchi                        76 (0.1%)
+   Josua Mayer                           70 (0.0%)
+   Andrejs Cainikovs                     67 (0.0%)
+   Claudiu Beznea                        64 (0.0%)
+   Patrice Chotard                       59 (0.0%)
+   Jim Liu                               59 (0.0%)
+   Jayesh Choudhary                      53 (0.0%)
+   Sinthu Raja                           51 (0.0%)
+   Stefan Roese                          48 (0.0%)
+   Pavel Skripkin                        43 (0.0%)
+   Apurva Nandan                         43 (0.0%)
+   Patrick Delaunay                      42 (0.0%)
+   Hugo Villeneuve                       39 (0.0%)
+   Loic Poulain                          37 (0.0%)
+   Markus Niebel                         36 (0.0%)
+   Christophe Kerello                    36 (0.0%)
+   Nitin Yadav                           36 (0.0%)
+   Sinan Akman                           35 (0.0%)
+   Peter Hoyes                           34 (0.0%)
+   John Keeping                          31 (0.0%)
+   Judith Mendez                         28 (0.0%)
+   Teik Heng Chong                       26 (0.0%)
+   Francesco Dolcini                     25 (0.0%)
+   Tony Dinh                             24 (0.0%)
+   Quanyang Wang                         24 (0.0%)
+   Tommaso Merciai                       24 (0.0%)
+   Nishanth Menon                        22 (0.0%)
+   Christopher Obbard                    22 (0.0%)
+   Christian Gmeiner                     18 (0.0%)
+   Francis Laniel                        17 (0.0%)
+   Frieder Schrempf                      16 (0.0%)
+   Elmar Psilog                          15 (0.0%)
+   meitao                                13 (0.0%)
+   Max Krummenacher                      13 (0.0%)
+   Thomas Perrot                         12 (0.0%)
+   Peter Geis                            12 (0.0%)
+   Neal Frager                           11 (0.0%)
+   Jorge Ramirez-Ortiz                   11 (0.0%)
+   Quentin Schulz                        10 (0.0%)
+   Nuno Sá                               10 (0.0%)
+   Dhruva Gole                           9 (0.0%)
+   Luca Ceresoli                         9 (0.0%)
+   Pierre-Clément Tosi                   9 (0.0%)
+   Baruch Siach                          8 (0.0%)
+   Ondrej Jirman                         8 (0.0%)
+   Detlev Casanova                       8 (0.0%)
+   Wolfgang Zarre                        8 (0.0%)
+   Vladimir Oltean                       8 (0.0%)
+   Konrad Dybcio                         7 (0.0%)
+   Hiroyuki Yokoyama                     7 (0.0%)
+   Krzysztof Kozlowski                   6 (0.0%)
+   Bhupesh Sharma                        6 (0.0%)
+   Frank Wunderlich                      6 (0.0%)
+   Devarsh Thakkar                       6 (0.0%)
+   Dylan Hung                            5 (0.0%)
+   Ben Dooks                             5 (0.0%)
+   Sam Edwards                           4 (0.0%)
+   Philippe Schenker                     4 (0.0%)
+   Mattijs Korpershoek                   4 (0.0%)
+   Christian Kohlschütter                4 (0.0%)
+   Mikhail Lappo                         4 (0.0%)
+   Ryan Chen                             4 (0.0%)
+   Claire Lin                            4 (0.0%)
+   Corentin Guillevic                    3 (0.0%)
+   Janne Grunau                          3 (0.0%)
+   Andrea Merello                        3 (0.0%)
+   Bryan Brattlof                        3 (0.0%)
+   Dominique Martinet                    3 (0.0%)
+   Vasily Khoruzhick                     3 (0.0%)
+   Tim Lee                               3 (0.0%)
+   Jiajie Chen                           3 (0.0%)
+   Henrik Grimler                        2 (0.0%)
+   Mingli Yu                             2 (0.0%)
+   Ilko Iliev                            2 (0.0%)
+   Mayuresh Chitale                      2 (0.0%)
+   Dave Gerlach                          2 (0.0%)
+   Raphael Gallais-Pou                   2 (0.0%)
+   Vignesh Raghavendra                   2 (0.0%)
+   Michael Trimarchi                     2 (0.0%)
+   Ying-Chun Liu (PaulLiu)               2 (0.0%)
+   Praneeth Bajjuri                      2 (0.0%)
+   Alexander Shirokov                    2 (0.0%)
+   Jonathan Liu                          2 (0.0%)
+   Haibo Chen                            2 (0.0%)
+   Michael Grzeschik                     2 (0.0%)
+   Heiko Schocher                        1 (0.0%)
+   Ken Sloat                             1 (0.0%)
+   Peter Robinson                        1 (0.0%)
+   Clément Léger                         1 (0.0%)
+   Fedor Ross                            1 (0.0%)
+   Wadim Egorov                          1 (0.0%)
+   Igor Opaniuk                          1 (0.0%)
+   Jean-Marie Lemetayer                  1 (0.0%)
+   Stefan Eichenberger                   1 (0.0%)
+   ====================================  =====
+
+
+.. table:: Developers with the most lines removed
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Tom Rini                              5481 (11.7%)
+   Ioana Ciornei                         3633 (7.7%)
+   Christophe Leroy                      2651 (5.7%)
+   Manorit Chawdhry                      1764 (3.8%)
+   Andrew Davis                          443 (0.9%)
+   Emanuele Ghidoli                      240 (0.5%)
+   Fabio Estevam                         235 (0.5%)
+   Tim Harvey                            197 (0.4%)
+   Stefan Roese                          36 (0.1%)
+   Hugo Villeneuve                       34 (0.1%)
+   Bin Meng                              33 (0.1%)
+   Ovidiu Panait                         24 (0.1%)
+   Francesco Dolcini                     23 (0.0%)
+   Andrejs Cainikovs                     22 (0.0%)
+   Teik Heng Chong                       14 (0.0%)
+   Quentin Schulz                        8 (0.0%)
+   Nishanth Menon                        5 (0.0%)
+   Krzysztof Kozlowski                   2 (0.0%)
+   Sam Edwards                           2 (0.0%)
+   Mikhail Lappo                         2 (0.0%)
+   Quanyang Wang                         1 (0.0%)
+   Dylan Hung                            1 (0.0%)
+   Jiajie Chen                           1 (0.0%)
+   Dave Gerlach                          1 (0.0%)
+   Heiko Schocher                        1 (0.0%)
+   ====================================  =====
+
+
+.. table:: Developers with the most signoffs (total 389)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Neil Armstrong                        51 (13.1%)
+   Peng Fan                              49 (12.6%)
+   Marek Vasut                           33 (8.5%)
+   Andre Przywara                        30 (7.7%)
+   Michal Simek                          25 (6.4%)
+   Dario Binacchi                        21 (5.4%)
+   Fabio Estevam                         14 (3.6%)
+   Ying-Chun Liu (PaulLiu)               13 (3.3%)
+   Hai Pham                              12 (3.1%)
+   Andrejs Cainikovs                     10 (2.6%)
+   Miquel Raynal                         10 (2.6%)
+   Linus Walleij                         10 (2.6%)
+   Simon Glass                           7 (1.8%)
+   Ashok Reddy Soma                      5 (1.3%)
+   Marcel Ziswiler                       5 (1.3%)
+   Jonas Karlman                         5 (1.3%)
+   Eugen Hristev                         5 (1.3%)
+   Tom Rini                              4 (1.0%)
+   Claudiu Beznea                        4 (1.0%)
+   Ilias Apalodimas                      4 (1.0%)
+   Jan Kiszka                            4 (1.0%)
+   Heinrich Schuchardt                   4 (1.0%)
+   Pierre-Clément Tosi                   3 (0.8%)
+   Christian Hewitt                      3 (0.8%)
+   Manorit Chawdhry                      2 (0.5%)
+   Francesco Dolcini                     2 (0.5%)
+   Vignesh Raghavendra                   2 (0.5%)
+   Stefano Babic                         2 (0.5%)
+   Siddharth Vadapalli                   2 (0.5%)
+   Yifeng Zhao                           2 (0.5%)
+   Emil Renner Berthing                  2 (0.5%)
+   Takeshi Kihara                        2 (0.5%)
+   Anatolij Gustschin                    2 (0.5%)
+   Dhruva Gole                           2 (0.5%)
+   Vladimir Zapolskiy                    2 (0.5%)
+   Ivan Mikhaylov                        2 (0.5%)
+   Ye Li                                 2 (0.5%)
+   LUU HOAI                              2 (0.5%)
+   Yanhong Wang                          2 (0.5%)
+   Bin Meng                              1 (0.3%)
+   Frank Wunderlich                      1 (0.3%)
+   Geert Uytterhoeven                    1 (0.3%)
+   Jagan Teki                            1 (0.3%)
+   Tero Kristo                           1 (0.3%)
+   Kamlesh Gurudasani                    1 (0.3%)
+   Ren Jianing                           1 (0.3%)
+   Frank Wang                            1 (0.3%)
+   William Wu                            1 (0.3%)
+   Stephen Chen                          1 (0.3%)
+   Manoj Sai                             1 (0.3%)
+   Paweł Jarosz                          1 (0.3%)
+   Cong Dang                             1 (0.3%)
+   Lin Jinhan                            1 (0.3%)
+   Nam Nguyen                            1 (0.3%)
+   Bryan Brattlof                        1 (0.3%)
+   Patrick Delaunay                      1 (0.3%)
+   Thomas Perrot                         1 (0.3%)
+   Apurva Nandan                         1 (0.3%)
+   Neha Francis                          1 (0.3%)
+   Will Deacon                           1 (0.3%)
+   Kamal Dasu                            1 (0.3%)
+   Samuel Holland                        1 (0.3%)
+   Kever Yang                            1 (0.3%)
+   Jianlong Huang                        1 (0.3%)
+   Kuan Lim Lee                          1 (0.3%)
+   Phong Hoang                           1 (0.3%)
+   Svyatoslav Ryhel                      1 (0.3%)
+   ====================================  =====
+
+
+.. table:: Developers with the most reviews (total 991)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Simon Glass                           291 (29.4%)
+   Kever Yang                            117 (11.8%)
+   Marek Vasut                           69 (7.0%)
+   Peng Fan                              54 (5.4%)
+   Ramon Fried                           49 (4.9%)
+   Bin Meng                              34 (3.4%)
+   Stefan Roese                          29 (2.9%)
+   Tom Rini                              23 (2.3%)
+   Andre Przywara                        21 (2.1%)
+   Ioana Ciornei                         20 (2.0%)
+   Mattijs Korpershoek                   20 (2.0%)
+   Michael Trimarchi                     19 (1.9%)
+   Jagan Teki                            15 (1.5%)
+   Neil Armstrong                        13 (1.3%)
+   Devarsh Thakkar                       13 (1.3%)
+   Fabio Estevam                         12 (1.2%)
+   Ilias Apalodimas                      12 (1.2%)
+   Heiko Schocher                        12 (1.2%)
+   Christian Gmeiner                     12 (1.2%)
+   Heinrich Schuchardt                   11 (1.1%)
+   Ye Li                                 10 (1.0%)
+   Patrick Delaunay                      8 (0.8%)
+   Rick Chen                             8 (0.8%)
+   Patrice Chotard                       8 (0.8%)
+   Michal Simek                          7 (0.7%)
+   Kamlesh Gurudasani                    7 (0.7%)
+   Leo Yu-Chi Liang                      7 (0.7%)
+   Jaehoon Chung                         7 (0.7%)
+   Bryan Brattlof                        6 (0.6%)
+   Konrad Dybcio                         5 (0.5%)
+   Jacky Bai                             5 (0.5%)
+   Jernej Skrabec                        5 (0.5%)
+   Claudiu Beznea                        4 (0.4%)
+   Sean Anderson                         4 (0.4%)
+   Douglas Anderson                      4 (0.4%)
+   Vladimir Oltean                       4 (0.4%)
+   Jonas Karlman                         3 (0.3%)
+   Viacheslav Mitrofanov                 3 (0.3%)
+   Mark Kettenis                         3 (0.3%)
+   Andrejs Cainikovs                     2 (0.2%)
+   Minkyu Kang                           2 (0.2%)
+   Sumit Garg                            2 (0.2%)
+   Joel Stanley                          2 (0.2%)
+   Ying-Chun Liu (PaulLiu)               1 (0.1%)
+   Miquel Raynal                         1 (0.1%)
+   Marcel Ziswiler                       1 (0.1%)
+   Eugen Hristev                         1 (0.1%)
+   Manorit Chawdhry                      1 (0.1%)
+   Francesco Dolcini                     1 (0.1%)
+   Dhruva Gole                           1 (0.1%)
+   Geert Uytterhoeven                    1 (0.1%)
+   Neha Francis                          1 (0.1%)
+   Andrew Davis                          1 (0.1%)
+   Tim Harvey                            1 (0.1%)
+   Quentin Schulz                        1 (0.1%)
+   Krzysztof Kozlowski                   1 (0.1%)
+   Qu Wenruo                             1 (0.1%)
+   Marek Behún                           1 (0.1%)
+   Pratyush Yadav                        1 (0.1%)
+   Shawn Lin                             1 (0.1%)
+   Alexander Kochetkov                   1 (0.1%)
+   Andrew Pinski                         1 (0.1%)
+   Alice Guo                             1 (0.1%)
+   Chia-Wei Wang                         1 (0.1%)
+   Ray Jui                               1 (0.1%)
+   Peter Robinson                        1 (0.1%)
+   Frieder Schrempf                      1 (0.1%)
+   John Keeping                          1 (0.1%)
+   Sergei Antonov                        1 (0.1%)
+   Chris Packham                         1 (0.1%)
+   Pali Rohár                            1 (0.1%)
+   Adam Ford                             1 (0.1%)
+   ====================================  =====
+
+
+.. table:: Developers with the most test credits (total 210)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Michal Simek                          41 (19.5%)
+   Mattijs Korpershoek                   19 (9.0%)
+   Ioana Ciornei                         18 (8.6%)
+   Svyatoslav Ryhel                      17 (8.1%)
+   Conor Dooley                          17 (8.1%)
+   Andreas Westman Dorcsak               15 (7.1%)
+   Simon Glass                           12 (5.7%)
+   Tony Dinh                             8 (3.8%)
+   Robert Eckelmann                      7 (3.3%)
+   Nicolas Chauvet                       7 (3.3%)
+   Martin Rowe                           7 (3.3%)
+   Bin Meng                              6 (2.9%)
+   Tom Rini                              4 (1.9%)
+   Heiko Schocher                        4 (1.9%)
+   Jonas Karlman                         4 (1.9%)
+   Marek Vasut                           2 (1.0%)
+   Jagan Teki                            2 (1.0%)
+   Viacheslav Mitrofanov                 2 (1.0%)
+   Quentin Schulz                        2 (1.0%)
+   Vagrant Cascadian                     2 (1.0%)
+   Nikhil M Jain                         2 (1.0%)
+   Fabio Estevam                         1 (0.5%)
+   Christian Gmeiner                     1 (0.5%)
+   Patrick Delaunay                      1 (0.5%)
+   Mark Kettenis                         1 (0.5%)
+   Eugen Hristev                         1 (0.5%)
+   Francesco Dolcini                     1 (0.5%)
+   Peter Robinson                        1 (0.5%)
+   Sergei Antonov                        1 (0.5%)
+   Frank Wunderlich                      1 (0.5%)
+   Ion Agorria                           1 (0.5%)
+   Jonas Schwöbel                        1 (0.5%)
+   Alexandre Ghiti                       1 (0.5%)
+   ====================================  =====
+
+
+.. table:: Developers who gave the most tested-by credits (total 210)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Svyatoslav Ryhel                      45 (21.4%)
+   Marek Vasut                           41 (19.5%)
+   Safae Ouajih                          19 (9.0%)
+   Pali Rohár                            18 (8.6%)
+   Mathew McBride                        18 (8.6%)
+   Yanhong Wang                          15 (7.1%)
+   Simon Glass                           13 (6.2%)
+   Johan Jonker                          7 (3.3%)
+   Nikhil M Jain                         5 (2.4%)
+   Jonas Karlman                         3 (1.4%)
+   Fabio Estevam                         3 (1.4%)
+   Marcel Ziswiler                       3 (1.4%)
+   Xavier Drudis Ferran                  3 (1.4%)
+   Ehsan Mohandesi                       3 (1.4%)
+   Dhruva Gole                           2 (1.0%)
+   Patrick Wildt                         2 (1.0%)
+   Heinrich Schuchardt                   1 (0.5%)
+   Tim Harvey                            1 (0.5%)
+   Linus Walleij                         1 (0.5%)
+   Jianlong Huang                        1 (0.5%)
+   Kuan Lim Lee                          1 (0.5%)
+   Ondrej Jirman                         1 (0.5%)
+   Francis Laniel                        1 (0.5%)
+   Lionel Debieve                        1 (0.5%)
+   Daniel Golle                          1 (0.5%)
+   Jianqun Xu                            1 (0.5%)
+   ====================================  =====
+
+
+.. table:: Developers with the most report credits (total 20)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Tom Rini                              7 (35.0%)
+   Francesco Dolcini                     2 (10.0%)
+   Mark Millard                          2 (10.0%)
+   Pali Rohár                            1 (5.0%)
+   Heinrich Schuchardt                   1 (5.0%)
+   Patrick Delaunay                      1 (5.0%)
+   Mark Kettenis                         1 (5.0%)
+   Frank Wunderlich                      1 (5.0%)
+   Alexandre Ghiti                       1 (5.0%)
+   Andre Przywara                        1 (5.0%)
+   AdityaK                               1 (5.0%)
+   Rob Herring                           1 (5.0%)
+   ====================================  =====
+
+
+.. table:: Developers who gave the most report credits (total 20)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Heinrich Schuchardt                   5 (25.0%)
+   Simon Glass                           3 (15.0%)
+   Nishanth Menon                        3 (15.0%)
+   Tom Rini                              2 (10.0%)
+   Patrick Delaunay                      2 (10.0%)
+   Fabio Estevam                         2 (10.0%)
+   Ilias Apalodimas                      1 (5.0%)
+   Ying-Chun Liu (PaulLiu)               1 (5.0%)
+   Krzysztof Kozlowski                   1 (5.0%)
+   ====================================  =====
+
+
+.. table:: Top changeset contributors by employer
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   (Unknown)                             704 (42.2%)
+   Google, Inc.                          234 (14.0%)
+   Renesas Electronics                   163 (9.8%)
+   Texas Instruments                     105 (6.3%)
+   NXP                                   102 (6.1%)
+   DENX Software Engineering             69 (4.1%)
+   Konsulko Group                        60 (3.6%)
+   Linaro                                47 (2.8%)
+   AMD                                   28 (1.7%)
+   Collabora Ltd.                        22 (1.3%)
+   ARM                                   20 (1.2%)
+   BayLibre SAS                          20 (1.2%)
+   Toradex                               19 (1.1%)
+   Siemens                               17 (1.0%)
+   ST Microelectronics                   16 (1.0%)
+   Socionext Inc.                        12 (0.7%)
+   Weidmüller Interface GmbH & Co. KG    7 (0.4%)
+   Amarula Solutions                     6 (0.4%)
+   Rockchip                              6 (0.4%)
+   Bootlin                               3 (0.2%)
+   Wind River                            2 (0.1%)
+   Analog Devices                        1 (0.1%)
+   Broadcom                              1 (0.1%)
+   Intel                                 1 (0.1%)
+   Pengutronix                           1 (0.1%)
+   Phytec                                1 (0.1%)
+   Ronetix                               1 (0.1%)
+   ====================================  =====
+
+
+.. table:: Top lines changed by employer
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   (Unknown)                             59395 (41.6%)
+   Renesas Electronics                   16879 (11.8%)
+   Google, Inc.                          15141 (10.6%)
+   NXP                                   11653 (8.2%)
+   Konsulko Group                        8562 (6.0%)
+   DENX Software Engineering             7986 (5.6%)
+   Linaro                                7608 (5.3%)
+   Texas Instruments                     6924 (4.9%)
+   Collabora Ltd.                        1493 (1.0%)
+   Socionext Inc.                        1335 (0.9%)
+   BayLibre SAS                          1102 (0.8%)
+   ARM                                   1099 (0.8%)
+   Siemens                               1096 (0.8%)
+   Rockchip                              1038 (0.7%)
+   Toradex                               500 (0.4%)
+   AMD                                   284 (0.2%)
+   ST Microelectronics                   271 (0.2%)
+   Amarula Solutions                     95 (0.1%)
+   Weidmüller Interface GmbH & Co. KG    80 (0.1%)
+   Wind River                            26 (0.0%)
+   Intel                                 26 (0.0%)
+   Bootlin                               22 (0.0%)
+   Analog Devices                        10 (0.0%)
+   Broadcom                              4 (0.0%)
+   Pengutronix                           2 (0.0%)
+   Ronetix                               2 (0.0%)
+   Phytec                                1 (0.0%)
+   ====================================  =====
+
+
+.. table:: Employers with the most signoffs (total 389)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Linaro                                80 (20.6%)
+   Renesas Electronics                   52 (13.4%)
+   NXP                                   51 (13.1%)
+   ARM                                   30 (7.7%)
+   AMD                                   30 (7.7%)
+   (Unknown)                             29 (7.5%)
+   Amarula Solutions                     23 (5.9%)
+   DENX Software Engineering             18 (4.6%)
+   Toradex                               17 (4.4%)
+   Texas Instruments                     12 (3.1%)
+   Google, Inc.                          11 (2.8%)
+   Bootlin                               11 (2.8%)
+   Rockchip                              7 (1.8%)
+   Collabora Ltd.                        5 (1.3%)
+   Konsulko Group                        4 (1.0%)
+   Siemens                               4 (1.0%)
+   Canonical                             4 (1.0%)
+   ST Microelectronics                   1 (0.3%)
+   ====================================  =====
+
+
+.. table:: Employers with the most hackers (total 188)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   (Unknown)                             93 (49.5%)
+   Texas Instruments                     18 (9.6%)
+   Linaro                                10 (5.3%)
+   Renesas Electronics                   6 (3.2%)
+   NXP                                   6 (3.2%)
+   Toradex                               6 (3.2%)
+   ST Microelectronics                   5 (2.7%)
+   AMD                                   4 (2.1%)
+   DENX Software Engineering             4 (2.1%)
+   Google, Inc.                          4 (2.1%)
+   Rockchip                              4 (2.1%)
+   ARM                                   3 (1.6%)
+   Amarula Solutions                     3 (1.6%)
+   Bootlin                               3 (1.6%)
+   Collabora Ltd.                        3 (1.6%)
+   Siemens                               3 (1.6%)
+   BayLibre SAS                          2 (1.1%)
+   Wind River                            2 (1.1%)
+   Konsulko Group                        1 (0.5%)
+   Socionext Inc.                        1 (0.5%)
+   Weidmüller Interface GmbH & Co. KG    1 (0.5%)
+   Intel                                 1 (0.5%)
+   Analog Devices                        1 (0.5%)
+   Broadcom                              1 (0.5%)
+   Pengutronix                           1 (0.5%)
+   Ronetix                               1 (0.5%)
+   Phytec                                1 (0.5%)
+   ====================================  =====
+
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index ffe25ca231..a7a41f2fac 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -318,6 +318,33 @@ Run the following command
       --guid <image GUID> \
       <capsule_file_name>
 
+The UEFI specification does not define the firmware versioning mechanism.
+EDK II reference implementation inserts the FMP Payload Header right before
+the payload. It coutains the fw_version and lowest supported version,
+EDK II reference implementation uses these information to implement the
+firmware versioning and anti-rollback protection, the firmware version and
+lowest supported version is stored into EFI non-volatile variable.
+
+In U-Boot, the firmware versioning is implemented utilizing
+the FMP Payload Header same as EDK II reference implementation,
+reads the FMP Payload Header and stores the firmware version into
+"FmpStateXXXX" EFI non-volatile variable. XXXX indicates the image index,
+since FMP protocol handles multiple image indexes.
+
+To add the fw_version into the FMP Payload Header,
+add --fw-version option in mkeficapsule tool.
+
+.. code-block:: console
+
+    $ mkeficapsule \
+      --index <index> --instance 0 \
+      --guid <image GUID> \
+      --fw-version 5 \
+      <capsule_file_name>
+
+If the --fw-version option is not set, FMP Payload Header is not inserted
+and fw_version is set as 0.
+
 Performing the update
 *********************
 
@@ -330,7 +357,7 @@ bit in OsIndications variable with
 
     => setenv -e -nv -bs -rt -v OsIndications =0x0000000000000004
 
-Since U-boot doesn't currently support SetVariable at runtime, its value
+Since U-Boot doesn't currently support SetVariable at runtime, its value
 won't be taken over across the reboot. If this is the case, you can skip
 this feature check with the Kconfig option (CONFIG_EFI_IGNORE_OSINDICATIONS)
 set.
@@ -510,6 +537,52 @@ where signature.dts looks like::
             };
     };
 
+Anti-rollback Protection
+************************
+
+Anti-rollback prevents unintentional installation of outdated firmware.
+To enable anti-rollback, you must add the lowest-supported-version property
+to dtb and specify --fw-version when creating a capsule file with the
+mkeficapsule tool.
+When executing capsule update, U-Boot checks if fw_version is greater than
+or equal to lowest-supported-version. If fw_version is less than
+lowest-supported-version, the update will fail.
+For example, if lowest-supported-version is set to 7 and you run capsule
+update using a capsule file with --fw-version of 5, the update will fail.
+When the --fw-version in the capsule file is updated, lowest-supported-version
+in the dtb might be updated accordingly.
+
+If user needs to enforce anti-rollback to any older version,
+the lowest-supported-version property in dtb must be always updated manually.
+
+Note that the lowest-supported-version property specified in U-Boot's control
+device tree can be changed by U-Boot fdt command.
+Secure systems should not enable this command.
+
+To insert the lowest supported version into a dtb
+
+.. code-block:: console
+
+    $ dtc -@ -I dts -O dtb -o version.dtbo version.dts
+    $ fdtoverlay -i orig.dtb -o new.dtb -v version.dtbo
+
+where version.dts looks like::
+
+    /dts-v1/;
+    /plugin/;
+    &{/} {
+            firmware-version {
+                    image1 {
+                            image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8";
+                            image-index = <1>;
+                            lowest-supported-version = <3>;
+                    };
+            };
+    };
+
+The properties of image-type-id and image-index must match the value
+defined in the efi_fw_image array as image_type_id and image_index.
+
 Executing the boot manager
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
 
diff --git a/doc/device-tree-bindings/config.txt b/doc/device-tree-bindings/config.txt
index 3151778b2c..f50c68bbdc 100644
--- a/doc/device-tree-bindings/config.txt
+++ b/doc/device-tree-bindings/config.txt
@@ -76,6 +76,8 @@ u-boot,mmc-env-partition (int)
 	precedence. In that case, only if the partition is not found,
 	mmc-env-offset* will be tried.
 
+	Note that CONFIG_ENV_MMC_PARTITION overrides this device-tree setting.
+
 u-boot,no-apm-finalize (bool)
 	For x86 devices running on coreboot, this tells U-Boot not to lock
 	down the Intel Management Engine (ME) registers. This allows U-Boot to
diff --git a/doc/device-tree-bindings/firmware/firmware-version.txt b/doc/device-tree-bindings/firmware/firmware-version.txt
new file mode 100644
index 0000000000..ee90ce3117
--- /dev/null
+++ b/doc/device-tree-bindings/firmware/firmware-version.txt
@@ -0,0 +1,22 @@
+firmware-version bindings
+-------------------------------
+
+Required properties:
+- image-type-id			: guid for image blob type
+- image-index			: image index
+- lowest-supported-version	: lowest supported version
+
+Example:
+
+	firmware-version {
+		image1 {
+			image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8";
+			image-index = <1>;
+			lowest-supported-version = <3>;
+		};
+		image2 {
+			image-type-id = "5A7021F5-FEF2-48B4-AABA-832E777418C0";
+			image-index = <2>;
+			lowest-supported-version = <7>;
+		};
+	};
diff --git a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
index 4f5404f999..6a22aeea30 100644
--- a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
+++ b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
@@ -1,13 +1,13 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-sf.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
+$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-mtd.yaml#
+$schema: http://devicetree.org/meta-schemas/base.yaml#
 
 title: FWU metadata on MTD device without GPT
 
 maintainers:
- - Masami Hiramatsu <masami.hiramatsu@linaro.org>
+ - Jassi Brar <jaswinder.singh@linaro.org>
 
 properties:
   compatible:
@@ -15,24 +15,101 @@ properties:
       - const: u-boot,fwu-mdata-mtd
 
   fwu-mdata-store:
-    maxItems: 1
-    description: Phandle of the MTD device which contains the FWU medatata.
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: Phandle of the MTD device which contains the FWU MetaData and Banks.
 
-  mdata-offsets:
+  mdata-parts:
+    $ref: /schemas/types.yaml#/definitions/non-unique-string-array
     minItems: 2
-    description: Offsets of the primary and secondary FWU metadata in the NOR flash.
+    maxItems: 2
+    description: labels of the primary and secondary FWU metadata partitions in the 'fixed-partitions' subnode of the 'jedec,spi-nor' flash device node.
+
+  patternProperties:
+    "fwu-bank[0-9]":
+    type: object
+    description: List of FWU mtd-backed banks. Typically two banks.
+
+    properties:
+      id:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: Index of the bank.
+
+      label:
+        $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+        minItems: 1
+        maxItems: 1
+        description: label of the partition, in the 'fixed-partitions' subnode of the 'jedec,spi-nor' flash device node, that holds this bank.
+
+      patternProperties:
+        "fwu-image[0-9]":
+        type: object
+        description: List of images in the FWU mtd-backed bank.
+
+        properties:
+          id:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Index of the bank.
+
+          offset:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Offset, from start of the bank, where the image is located.
+
+          size:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Size reserved for the image.
+
+          uuid:
+            $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+            minItems: 1
+            maxItems: 1
+            description: UUID of the image.
+
+        required:
+          - id
+          - offset
+          - size
+          - uuid
+        additionalProperties: false
+
+    required:
+      - id
+      - label
+      - fwu-images
+    additionalProperties: false
 
 required:
   - compatible
   - fwu-mdata-store
-  - mdata-offsets
-
+  - mdata-parts
+  - fwu-banks
 additionalProperties: false
 
 examples:
   - |
-    fwu-mdata {
-        compatible = "u-boot,fwu-mdata-mtd";
-        fwu-mdata-store = <&spi-flash>;
-        mdata-offsets = <0x500000 0x530000>;
-    };
+	fwu-mdata {
+		compatible = "u-boot,fwu-mdata-mtd";
+		fwu-mdata-store = <&flash0>;
+		mdata-parts = "MDATA-Pri", "MDATA-Sec";
+
+		fwu-bank0 {
+			id = <0>;
+			label = "FIP-Bank0";
+			fwu-image0 {
+				id = <0>;
+				offset = <0x0>;
+				size = <0x400000>;
+				uuid = "5a66a702-99fd-4fef-a392-c26e261a2828";
+			};
+		};
+		fwu-bank1 {
+			id = <1>;
+			label = "FIP-Bank1";
+			fwu-image0 {
+				id = <0>;
+				offset = <0x0>;
+				size = <0x400000>;
+				uuid = "a8f868a1-6e5c-4757-878d-ce63375ef2c0";
+			};
+		};
+	};
+...
diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
index da210bfc86..1381bdcd16 100644
--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -41,3 +41,6 @@ Example: Bundles both peripheral bitstream and core bitstream into FIT image
 		resets = <&rst FPGAMGR_RESET>;
 		altr,bitstream = "fit_spl_fpga.itb";
 	};
+
+- The .its related documentations can be found here
+	- Appendix - Reducing Arria 10 Fabric Configuration Time - https://rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10
diff --git a/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml b/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
new file mode 100644
index 0000000000..6554978583
--- /dev/null
+++ b/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Broadband SoC High Speed SPI controller
+
+maintainers:
+  - William Zhang <william.zhang@broadcom.com>
+  - Kursad Oney <kursad.oney@broadcom.com>
+  - Jonas Gorski <jonas.gorski@gmail.com>
+
+description: |
+  Broadcom Broadband SoC supports High Speed SPI master controller since the
+  early MIPS based chips such as BCM6328 and BCM63268.  This initial rev 1.0
+  controller was carried over to recent ARM based chips, such as BCM63138,
+  BCM4908 and BCM6858. The old MIPS based chip should continue to use the
+  brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to
+  use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as
+  defined below to match the specific chip along with ip revision info.
+
+  This rev 1.0 controller has a limitation that can not keep the chip select line
+  active between the SPI transfers within the same SPI message. This can
+  terminate the transaction to some SPI devices prematurely. The issue can be
+  worked around by either the controller's prepend mode or using the dummy chip
+  select workaround. Driver automatically picks the suitable mode based on
+  transfer type so it is transparent to the user.
+
+  The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI
+  controller rev 1.1 that add the capability to allow the driver to control chip
+  select explicitly. This solves the issue in the old controller.
+
+properties:
+  compatible:
+    oneOf:
+      - const: brcm,bcm6328-hsspi
+      - items:
+          - enum:
+              - brcm,bcm47622-hsspi
+              - brcm,bcm4908-hsspi
+              - brcm,bcm63138-hsspi
+              - brcm,bcm63146-hsspi
+              - brcm,bcm63148-hsspi
+              - brcm,bcm63158-hsspi
+              - brcm,bcm63178-hsspi
+              - brcm,bcm6846-hsspi
+              - brcm,bcm6856-hsspi
+              - brcm,bcm6858-hsspi
+              - brcm,bcm6878-hsspi
+          - const: brcm,bcmbca-hsspi-v1.0
+      - items:
+          - enum:
+              - brcm,bcm4912-hsspi
+              - brcm,bcm6756-hsspi
+              - brcm,bcm6813-hsspi
+              - brcm,bcm6855-hsspi
+          - const: brcm,bcmbca-hsspi-v1.1
+
+  reg:
+    items:
+      - description: main registers
+      - description: miscellaneous control registers
+    minItems: 1
+
+  reg-names:
+    items:
+      - const: hsspi
+      - const: spim-ctrl
+    minItems: 1
+
+  clocks:
+    items:
+      - description: SPI master reference clock
+      - description: SPI master pll clock
+
+  clock-names:
+    items:
+      - const: hsspi
+      - const: pll
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+
+allOf:
+  - $ref: spi-controller.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - brcm,bcm6328-hsspi
+              - brcm,bcmbca-hsspi-v1.0
+    then:
+      properties:
+        reg:
+          maxItems: 1
+        reg-names:
+          maxItems: 1
+    else:
+      properties:
+        reg:
+          minItems: 2
+          maxItems: 2
+        reg-names:
+          minItems: 2
+          maxItems: 2
+      required:
+        - reg-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    spi@ff801000 {
+        compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1";
+        reg = <0xff801000 0x1000>,
+              <0xff802610 0x4>;
+        reg-names = "hsspi", "spim-ctrl";
+        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&hsspi>, <&hsspi_pll>;
+        clock-names = "hsspi", "pll";
+        num-cs = <8>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+    };
diff --git a/doc/device-tree-bindings/spi/soft-spi.txt b/doc/device-tree-bindings/spi/soft-spi.txt
index dfb5066473..bdf7e86bef 100644
--- a/doc/device-tree-bindings/spi/soft-spi.txt
+++ b/doc/device-tree-bindings/spi/soft-spi.txt
@@ -9,10 +9,10 @@ The soft SPI node requires the following properties:
 Mandatory properties:
 compatible: "spi-gpio"
 cs-gpios: GPIOs to use for SPI chip select (output)
-gpio-sck: GPIO to use for SPI clock (output)
+sck-gpios: GPIO to use for SPI clock (output)
 And at least one of:
-gpio-mosi: GPIO to use for SPI MOSI line (output)
-gpio-miso: GPIO to use for SPI MISO line (input)
+mosi-gpios: GPIO to use for SPI MOSI line (output)
+miso-gpios: GPIO to use for SPI MISO line (input)
 
 Optional propertie:
 spi-delay-us: Number of microseconds of delay between each CS transition
@@ -27,9 +27,9 @@ Example:
 	soft-spi {
 		compatible = "spi-gpio";
 		cs-gpios = <&gpio 235 0>;	/* Y43 */
-		gpio-sck = <&gpio 225 0>;	/* Y31 */
-		gpio-mosi = <&gpio 227 0>;	/* Y33 */
-		gpio-miso = <&gpio 224 0>;	/* Y30 */
+		sck-gpios = <&gpio 225 0>;	/* Y31 */
+		mosi-gpios = <&gpio 227 0>;	/* Y33 */
+		miso-gpios = <&gpio 224 0>;	/* Y30 */
 		spi-delay-us = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 96623c3b4e..0ceb9eb88b 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -22,6 +22,7 @@ alias apritzel       Andre Przywara <andre.przywara@arm.com>
 alias bmeng          Bin Meng <bmeng.cn@gmail.com>
 alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 alias dinh           Dinh Nguyen <dinguyen@kernel.org>
+alias ehristev       Eugen Hristev <eugen.hristev@collabora.com>
 alias hs             Heiko Schocher <hs@denx.de>
 alias freenix        Peng Fan <peng.fan@nxp.com>
 alias iwamatsu       Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh
index 7a9a05e633..d87015f6c4 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf.sh
+++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh
@@ -22,6 +22,27 @@
 cp doc/imx/habv4/csf_examples/mx8m/csf_spl.txt csf_spl.tmp
 cp doc/imx/habv4/csf_examples/mx8m/csf_fit.txt csf_fit.tmp
 
+# update File Paths from env vars
+if ! [ -r $CSF_KEY ]; then
+	echo "Error: \$CSF_KEY not found"
+	exit 1
+fi
+if ! [ -r $IMG_KEY ]; then
+	echo "Error: \$IMG_KEY not found"
+	exit 1
+fi
+if ! [ -r $SRK_TABLE ]; then
+	echo "Error: \$SRK_TABLE not found"
+	exit 1
+fi
+sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_spl.tmp
+sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_spl.tmp
+sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_spl.tmp
+sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_fit.tmp
+sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_fit.tmp
+sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_fit.tmp
+
+# update SPL Blocks
 spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p" .config) - 0x40)) )
 spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin))
 sed -i "/Blocks = / s@.*@  Blocks = $spl_block_base 0x0 $spl_block_size \"flash.bin\"@" csf_spl.tmp
@@ -37,29 +58,11 @@ dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc
 
 # 3) Sign u-boot.itb
 
-# fitImage tree
-fit_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_TEXT_BASE=/ s@.*=@@p" .config) - $(sed -n "/CONFIG_FIT_EXTERNAL_OFFSET=/ s@.*=@@p" .config) - 0x200 - 0x40)) )
+# fitImage
+fit_block_base=$(printf "0x%x" $(sed -n "/CONFIG_SPL_LOAD_FIT_ADDRESS=/ s@.*=@@p" .config) )
 fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset))
-fit_block_size=$(printf "0x%x" $(( ( ($(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) )
-sed -i "/Blocks = / s@.*@  Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\", \\\\@" csf_fit.tmp
-
-# U-Boot
-uboot_block_base=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/uboot load))
-uboot_block_offset=$(printf "0x%x" $(( $(printf "0x%s" $(fdtget -t x u-boot.itb /images/uboot data-position)) + ${fit_block_offset} )))
-uboot_block_size=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/uboot data-size))
-sed -i "/0xuuuu/ s@.*@           $uboot_block_base $uboot_block_offset $uboot_block_size \"flash.bin\", \\\\@" csf_fit.tmp
-
-# ATF
-atf_block_base=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/atf load))
-atf_block_offset=$(printf "0x%x" $(( $(printf "0x%s" $(fdtget -t x u-boot.itb /images/atf data-position)) + ${fit_block_offset} )))
-atf_block_size=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/atf data-size))
-sed -i "/0xaaaa/ s@.*@           $atf_block_base $atf_block_offset $atf_block_size \"flash.bin\", \\\\@" csf_fit.tmp
-
-# DTB
-dtb_block_base=$(printf "0x%x" $(( ${uboot_block_base} + ${uboot_block_size} )))
-dtb_block_offset=$(printf "0x%x" $(( $(printf "0x%s" $(fdtget -t x u-boot.itb /images/fdt-1 data-position)) + ${fit_block_offset} )))
-dtb_block_size=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/fdt-1 data-size))
-sed -i "/0xdddd/ s@.*@           $dtb_block_base $dtb_block_offset $dtb_block_size \"flash.bin\"@" csf_fit.tmp
+fit_block_size=$(printf "0x%x" $(( ( ( $(stat -tc %s u-boot.itb) + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) )
+sed -i "/Blocks = / s@.*@  Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\"@" csf_fit.tmp
 
 # IVT
 ivt_ptr_base=$(printf "%08x" ${fit_block_base} | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
@@ -68,7 +71,7 @@ csf_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} )) | se
 ivt_block_offset=$((${fit_block_offset} + ${fit_block_size} - 0x20))
 csf_block_offset=$((${ivt_block_offset} + 0x20))
 
-echo "0xd1002041 ${ivt_ptr_base} 0x00000000 0x00000000 0x00000000 ${ivt_block_base} ${csf_block_base} 0x00000000" | xxd -r -p > ivt.bin
+echo "0xd1002041 ${ivt_block_base} 0x00000000 0x00000000 0x00000000 ${ivt_block_base} ${csf_block_base} 0x00000000" | xxd -r -p > ivt.bin
 dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc
 
 # Generate CSF blob
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
index cd1d4070a5..3d79edf281 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
@@ -7,30 +7,24 @@
   Signature Format = CMS
 
 [Install SRK]
-  # FIXME: Adjust path here
-  File = "/path/to/cst-3.3.1/crts/SRK_1_2_3_4_table.bin"
+  # SRK_TABLE is full path to SRK_1_2_3_4_table.bin
+  File = "$SRK_TABLE"
   Source index = 0
 
 [Install CSFK]
-  # FIXME: Adjust path here
-  File = "/path/to/cst-3.3.1/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem"
+  # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem
+  File = "$CSF_KEY"
 
 [Authenticate CSF]
 
 [Install Key]
   Verification index = 0
   Target Index = 2
-  # FIXME: Adjust path here
-  File = "/path/to/cst-3.3.1/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem"
+  # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem
+  File = "$IMG_KEY"
 
 [Authenticate Data]
   Verification index = 2
   # FIXME:
-  # Line 1 -- fitImage tree
-  # Line 2 -- U-Boot u-boot-nodtb.bin blob
-  # Line 3 -- ATF BL31 blob
-  # Line 4 -- DT blob
-  Blocks = 0x401fcdc0 0x57c00 0xffff "flash.bin", \
-           0x40200000 0x62c00 0xuuuu "flash.bin", \
-	   0x920000   0x00000 0xaaaa "flash.bin", \
-	   0x40200000 0x00000 0xdddd "flash.bin"
+  # Line 1 -- fitImage
+  Blocks = 0x401fcdc0 0x57c00 0xffff "flash.bin"
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
index 00e34f6b1b..88fa420a5f 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
@@ -7,13 +7,13 @@
   Signature Format = CMS
 
 [Install SRK]
-  # FIXME: Adjust path here
-  File = "/path/to/cst-3.3.1/crts/SRK_1_2_3_4_table.bin"
+  # SRK_TABLE is full path to SRK_1_2_3_4_table.bin
+  File = "$SRK_TABLE"
   Source index = 0
 
 [Install CSFK]
-  # FIXME: Adjust path here
-  File = "/path/to/cst-3.3.1/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem"
+  # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem
+  File = "$CSF_KEY"
 
 [Authenticate CSF]
 
@@ -24,8 +24,8 @@
 [Install Key]
   Verification index = 0
   Target Index = 2
-  # FIXME: Adjust path here
-  File = "/path/to/cst-3.3.1/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem"
+  # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem
+  File = "$IMG_KEY"
 
 [Authenticate Data]
   Verification index = 2
diff --git a/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt b/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt
index 53f71fbc3e..7fba84a394 100644
--- a/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt
+++ b/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt
@@ -113,7 +113,7 @@ the U-Boot build, the example below is a log for mx7dsabresd_defconfig target:
 1.4 Signing the U-Boot binary
 ------------------------------
 
-The CST tool is used for singing the U-Boot binary and generating a CSF binary,
+The CST tool is used for signing the U-Boot binary and generating a CSF binary,
 users should input the CSF description file created in the step above and
 should receive a CSF binary, which contains the CSF commands, SRK table,
 signatures and certificates.
diff --git a/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt b/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt
index fde0f27efd..56b8cd62cb 100644
--- a/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt
+++ b/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt
@@ -145,7 +145,7 @@ addresses, the csf_uboot.txt can be used as example:
 1.4 Signing the images
 -----------------------
 
-The CST tool is used for singing the U-Boot binary and generating a CSF binary,
+The CST tool is used for signing the U-Boot binary and generating a CSF binary,
 users should input the CSF description file created in the step above and
 receive a CSF binary, which contains the CSF commands, SRK table, signatures
 and certificates.
diff --git a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
index 3e3d38440f..e16e5410bd 100644
--- a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
+++ b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
@@ -79,18 +79,16 @@ code within it:
 
 The diagram below illustrate a signed U-Boot binary, DT blob and external
 ATF BL31 blob combined to form fitImage part of flash.bin container layout.
-The *load_address is derived from CONFIG_TEXT_BASE such that the U-Boot
-binary *start is placed exactly at CONFIG_SPL_TEXT_BASE in DRAM, however the
-SPL moves the fitImage tree further to location:
- *load_address = CONFIG_SPL_TEXT_BASE - CONFIG_FIT_EXTERNAL_OFFSET (=12kiB) -
-                 512 Byte sector - sizeof(mkimage header)
+The *load_address is CONFIG_SPL_LOAD_FIT_ADDRESS, the fitImage is loaded
+including all of its embedded data, authenticated using IVT+CSF concatenated
+at the end of the fitImage at offset aligned to 4 kiB. The fitImage with
+external data is not supported.
 
             ------- +-----------------------------+ <-- *load_address
                 ^   |                             |
                 |   |        fitImage tree        |
-                |   |    with external data at    |
-                |   |   offset 12 kiB from tree   |
-                |   |        (cca. 1 kiB)         |
+                |   |      with embedded data     |
+                |   |        (cca. 1 MiB)         |
          Signed |   |                             |
   .-----  Tree  |   +-----------------------------+
   |       Data  |   | Padding to next 4k aligned  |
@@ -101,34 +99,9 @@ SPL moves the fitImage tree further to location:
   |         ------- +-----------------------------+ <-- *csf
   |                 | Command Sequence File (CSF) |
   |                 |  for all signed entries in  |
-   >--------------->| the fitImage, tree and data |
-  |                 |        (cca 6-7 kiB)        |
-  |                 +-----------------------------+
-  |                 |  Padding to 12 kiB offset   |
-  |                 |     from *load_address      |
-  |         ------- +-----------------------------+ <-- *start
-  |             ^   |                             |
-  |      Signed |   |                             |
-  |---- Payload |   |  U-Boot external data blob  |
-  |       Data  |   |                             |
-  |             v   |                             |
-  |         ------- +-----------------------------+
-  |                 |     Padding to 4 Bytes      |
-  |         ------- +-----------------------------+
-  |             ^   |                             |
-  |      Signed |   |                             |
-  |---- Payload |   |    ATF external data blob   |
-  |       Data  |   |                             |
-  |             v   |                             |
-  |         ------- +-----------------------------+
-  |                 |     Padding to 4 Bytes      |
-  |         ------- +-----------------------------+
-  |             ^   |                             |
-  |      Signed |   |                             |
-  '---- Payload |   |    DTB external data blob   |
-          Data  |   |                             |
-                v   |                             |
-            ------- +-----------------------------+
+  '---------------->| the fitImage, tree and data |
+                    |        (cca 6-7 kiB)        |
+                    +-----------------------------+
 
 The diagram below illustrate a combined flash.bin container layout:
 
@@ -202,29 +175,11 @@ dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc
 
 CSF "Blocks" line for csf_fit.txt can be generated as follows:
 ```
-# fitImage tree
-fit_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_TEXT_BASE=/ s@.*=@@p" .config) - $(sed -n "/CONFIG_FIT_EXTERNAL_OFFSET=/ s@.*=@@p" .config) - 0x200 - 0x40)) )
+# fitImage
+fit_block_base=$(printf "0x%x" $(sed -n "/CONFIG_SPL_LOAD_FIT_ADDRESS=/ s@.*=@@p" .config) )
 fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset))
-fit_block_size=$(printf "0x%x" $(( ( $(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1) + 0x20 )) )
-sed -i "/Blocks = / s@.*@  Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\", \\\\@" csf_fit.tmp
-
-# U-Boot
-uboot_block_base=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/uboot load))
-uboot_block_offset=$(printf "0x%x" $(( $(printf "0x%s" $(fdtget -t x u-boot.itb /images/uboot data-position)) + ${fit_block_offset} )))
-uboot_block_size=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/uboot data-size))
-sed -i "/0xuuuu/ s@.*@           $uboot_block_base $uboot_block_offset $uboot_block_size \"flash.bin\", \\\\@" csf_fit.tmp
-
-# ATF
-atf_block_base=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/atf load))
-atf_block_offset=$(printf "0x%x" $(( $(printf "0x%s" $(fdtget -t x u-boot.itb /images/atf data-position)) + ${fit_block_offset} )))
-atf_block_size=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/atf data-size))
-sed -i "/0xaaaa/ s@.*@           $atf_block_base $atf_block_offset $atf_block_size \"flash.bin\", \\\\@" csf_fit.tmp
-
-# DTB
-dtb_block_base=$(printf "0x%x" $(( ${uboot_block_base} + ${uboot_block_size} )))
-dtb_block_offset=$(printf "0x%x" $(( $(printf "0x%s" $(fdtget -t x u-boot.itb /images/fdt-1 data-position)) + ${fit_block_offset} )))
-dtb_block_size=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/fdt-1 data-size))
-sed -i "/0xdddd/ s@.*@           $dtb_block_base $dtb_block_offset $dtb_block_size \"flash.bin\"@" csf_fit.tmp
+fit_block_size=$(printf "0x%x" $(( ( ( $(stat -tc %s u-boot.itb) + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) )
+sed -i "/Blocks = / s@.*@  Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\"@" csf_fit.tmp
 ```
 
 The fitImage part of flash.bin requires separate IVT. Generate the IVT and
@@ -237,8 +192,9 @@ csf_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} )) | se
 ivt_block_offset=$((${fit_block_offset} + ${fit_block_size} - 0x20))
 csf_block_offset=$((${ivt_block_offset} + 0x20))
 
-echo "0xd1002041 ${ivt_ptr_base} 0x00000000 0x00000000 0x00000000 ${ivt_block_base} ${csf_block_base} 0x00000000" | xxd -r -p > ivt.bin
+echo "0xd1002041 ${ivt_block_base} 0x00000000 0x00000000 0x00000000 ${ivt_block_base} ${csf_block_base} 0x00000000" | xxd -r -p > ivt.bin
 dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc
+```
 
 To generate CSF signature for the fitImage part of flash.bin container, use CST:
 ```
@@ -251,6 +207,16 @@ dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc
 ```
 
 The entire script is available in doc/imx/habv4/csf_examples/mx8m/csf.sh
+and can be used as follows to modify flash.bin to be signed
+(adjust paths as needed):
+```
+export CST_DIR=/usr/src/cst-3.3.1/
+export CSF_KEY=$CST_DIR/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem
+export IMG_KEY=$CST_DIR/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem
+export SRK_TABLE=$CST_DIR/crts/SRK_1_2_3_4_table.bin
+export PATH=$CST_DIR/linux64/bin:$PATH
+/bin/sh doc/imx/habv4/csf_examples/mx8m/csf.sh
+```
 
 1.4 Closing the device
 -----------------------
diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1
index 1ca245a10f..c4c2057d5c 100644
--- a/doc/mkeficapsule.1
+++ b/doc/mkeficapsule.1
@@ -62,6 +62,16 @@ Specify an image index
 Specify a hardware instance
 
 .PP
+FMP Payload Header is inserted right before the payload if
+.BR --fw-version
+is specified
+
+
+.TP
+.BI "-v\fR,\fB --fw-version " firmware-version
+Specify a firmware version, 0 if omitted
+
+.PP
 For generation of firmware accept empty capsule
 .BR --guid
 is mandatory
diff --git a/doc/mkfwumdata.1 b/doc/mkfwumdata.1
new file mode 100644
index 0000000000..7dd718b26e
--- /dev/null
+++ b/doc/mkfwumdata.1
@@ -0,0 +1,89 @@
+.\" SPDX-License-Identifier: GPL-2.0-or-later
+.\" Copyright (C) 2023 Jassi Brar <jaswinder.singh@linaro.org>
+.TH MKFWUMDATA 1 2023-04-10 U-Boot
+.SH NAME
+mkfwumdata \- create FWU metadata image
+.
+.SH SYNOPSIS
+.SY mkfwumdata
+.OP \-a activeidx
+.OP \-p previousidx
+.OP \-g
+.BI \-i\~ imagecount
+.BI \-b\~ bankcount
+.I UUIDs
+.I outputimage
+.YS
+.SY mkfwumdata
+.B \-h
+.YS
+.
+.SH DESCRIPTION
+.B mkfwumdata
+creates metadata info to be used with FWU.
+.
+.SH OPTIONS
+.TP
+.B \-h
+Print usage information and exit.
+.
+.TP
+.B \-a
+Set 
+.IR activeidx
+as the currently active Bank. Default is 0.
+.
+.TP
+.B \-p
+Set 
+.IR previousidx
+as the previous active Bank. Default is
+.IR activeidx "-1"
+or
+.IR bankcount "-1,"
+whichever is non-negative.
+.
+.TP
+.B \-g
+Convert the
+.IR UUIDs
+as GUIDs before use.
+.
+.TP
+.B \-i
+Specify there are
+.IR imagecount
+images in each bank.
+.
+.TP
+.B \-b
+Specify there are a total of
+.IR bankcount
+banks.
+.
+.TP
+.IR UUIDs
+Comma-separated list of UUIDs required to create the metadata :-
+location_uuid,image_type_uuid,<images per bank uuid list of all banks>
+.
+.TP
+.IR outputimage
+Specify the name of the metadata image file to be created.
+.
+.SH BUGS
+Please report bugs to the
+.UR https://\:source\:.denx\:.de/\:u-boot/\:u-boot/\:issues
+U-Boot bug tracker
+.UE .
+.SH EXAMPLES
+Create a metadata image with 2 banks and 1 image/bank, BankAct=0, BankPrev=1:
+.PP
+.EX
+.in +4
+$ \c
+.B mkfwumdata \-a 0 \-p 1 \-b 2 \-i 1 \\\\\&
+.in +6
+.B 17e86d77-41f9-4fd7-87ec-a55df9842de5,\\\\\&
+.B 10c36d7d-ca52-b843-b7b9-f9d6c501d108,\\\\\&
+.B 5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0 \\\\\&
+.B fwu-mdata.img
diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt
index f9f6cc6e92..4f411f78d0 100644
--- a/doc/sphinx/requirements.txt
+++ b/doc/sphinx/requirements.txt
@@ -1,6 +1,6 @@
 alabaster==0.7.12
 Babel==2.9.1
-certifi==2022.12.7
+certifi==2023.07.22
 charset-normalizer==2.0.12
 docutils==0.16
 idna==3.3
@@ -8,10 +8,10 @@ imagesize==1.3.0
 Jinja2==3.0.3
 MarkupSafe==2.1.1
 packaging==21.3
-Pygments==2.11.2
+Pygments==2.15.1
 pyparsing==3.0.7
-pytz==2022.1
-requests==2.27.1
+pytz==2023.3
+requests==2.31.0
 six==1.16.0
 snowballstemmer==2.2.0
 Sphinx==3.4.3
diff --git a/doc/uImage.FIT/beaglebone_vboot.txt b/doc/uImage.FIT/beaglebone_vboot.txt
deleted file mode 100644
index ebd2068ed3..0000000000
--- a/doc/uImage.FIT/beaglebone_vboot.txt
+++ /dev/null
@@ -1,607 +0,0 @@
-Verified Boot on the Beaglebone Black
-=====================================
-
-Introduction
-------------
-
-Before reading this, please read verified-boot.txt and signature.txt. These
-instructions are for mainline U-Boot from v2014.07 onwards.
-
-There is quite a bit of documentation in this directory describing how
-verified boot works in U-Boot. There is also a test which runs through the
-entire process of signing an image and running U-Boot (sandbox) to check it.
-However, it might be useful to also have an example on a real board.
-
-Beaglebone Black is a fairly common board so seems to be a reasonable choice
-for an example of how to enable verified boot using U-Boot.
-
-First a note that may to help avoid confusion. U-Boot and Linux both use
-device tree. They may use the same device tree source, but it is seldom useful
-for them to use the exact same binary from the same place. More typically,
-U-Boot has its device tree packaged wtih it, and the kernel's device tree is
-packaged with the kernel. In particular this is important with verified boot,
-since U-Boot's device tree must be immutable. If it can be changed then the
-public keys can be changed and verified boot is useless. An attacker can
-simply generate a new key and put his public key into U-Boot so that
-everything verifies. On the other hand the kernel's device tree typically
-changes when the kernel changes, so it is useful to package an updated device
-tree with the kernel binary. U-Boot supports the latter with its flexible FIT
-format (Flat Image Tree).
-
-
-Overview
---------
-
-The steps are roughly as follows:
-
-1. Build U-Boot for the board, with the verified boot options enabled.
-
-2. Obtain a suitable Linux kernel
-
-3. Create a Image Tree Source file (ITS) file describing how you want the
-kernel to be packaged, compressed and signed.
-
-4. Create a key pair
-
-5. Sign the kernel
-
-6. Put the public key into U-Boot's image
-
-7. Put U-Boot and the kernel onto the board
-
-8. Try it
-
-
-Step 1: Build U-Boot
---------------------
-
-a. Set up the environment variable to point to your toolchain. You will need
-this for U-Boot and also for the kernel if you build it. For example if you
-installed a Linaro version manually it might be something like:
-
-   export CROSS_COMPILE=/opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.08_linux/bin/arm-linux-gnueabihf-
-
-or if you just installed gcc-arm-linux-gnueabi then it might be
-
-   export CROSS_COMPILE=arm-linux-gnueabi-
-
-b. Configure and build U-Boot with verified boot enabled:
-
-   export UBOOT=/path/to/u-boot
-   cd $UBOOT
-   # You can add -j10 if you have 10 CPUs to make it faster
-   make O=b/am335x_boneblack_vboot am335x_boneblack_vboot_config all
-   export UOUT=$UBOOT/b/am335x_boneblack_vboot
-
-c. You will now have a U-Boot image:
-
-   file b/am335x_boneblack_vboot/u-boot-dtb.img
-b/am335x_boneblack_vboot/u-boot-dtb.img: u-boot legacy uImage, U-Boot 2014.07-rc2-00065-g2f69f8, Firmware/ARM, Firmware Image (Not compressed), 395375 bytes, Sat May 31 16:19:04 2014, Load Address: 0x80800000, Entry Point: 0x00000000, Header CRC: 0x0ABD6ACA, Data CRC: 0x36DEF7E4
-
-
-Step 2: Build Linux
---------------------
-
-a. Find the kernel image ('Image') and device tree (.dtb) file you plan to
-use. In our case it is am335x-boneblack.dtb and it is built with the kernel.
-At the time of writing an SD Boot image can be obtained from here:
-
-   http://www.elinux.org/Beagleboard:Updating_The_Software#Image_For_Booting_From_microSD
-
-You can write this to an SD card and then mount it to extract the kernel and
-device tree files.
-
-You can also build a kernel. Instructions for this are are here:
-
-   http://elinux.org/Building_BBB_Kernel
-
-or you can use your favourite search engine. Following these instructions
-produces a kernel Image and device tree files. For the record the steps were:
-
-   export KERNEL=/path/to/kernel
-   cd $KERNEL
-   git clone git://github.com/beagleboard/kernel.git .
-   git checkout v3.14
-   ./patch.sh
-   cp configs/beaglebone kernel/arch/arm/configs/beaglebone_defconfig
-   cd kernel
-   make beaglebone_defconfig
-   make uImage dtbs   # -j10 if you have 10 CPUs
-   export OKERNEL=$KERNEL/kernel/arch/arm/boot
-
-c. You now have the 'Image' and 'am335x-boneblack.dtb' files needed to boot.
-
-
-Step 3: Create the ITS
-----------------------
-
-Set up a directory for your work.
-
-   export WORK=/path/to/dir
-   cd $WORK
-
-Put this into a file in that directory called sign.its:
-
-/dts-v1/;
-
-/ {
-	description = "Beaglebone black";
-	#address-cells = <1>;
-
-	images {
-		kernel {
-			data = /incbin/("Image.lzo");
-			type = "kernel";
-			arch = "arm";
-			os = "linux";
-			compression = "lzo";
-			load = <0x80008000>;
-			entry = <0x80008000>;
-			hash-1 {
-				algo = "sha1";
-			};
-		};
-		fdt-1 {
-			description = "beaglebone-black";
-			data = /incbin/("am335x-boneblack.dtb");
-			type = "flat_dt";
-			arch = "arm";
-			compression = "none";
-			hash-1 {
-				algo = "sha1";
-			};
-		};
-	};
-	configurations {
-		default = "conf-1";
-		conf-1 {
-			kernel = "kernel";
-			fdt = "fdt-1";
-			signature-1 {
-				algo = "sha1,rsa2048";
-				key-name-hint = "dev";
-				sign-images = "fdt", "kernel";
-			};
-		};
-	};
-};
-
-
-The explanation for this is all in the documentation you have already read.
-But briefly it packages a kernel and device tree, and provides a single
-configuration to be signed with a key named 'dev'. The kernel is compressed
-with LZO to make it smaller.
-
-
-Step 4: Create a key pair
--------------------------
-
-See signature.txt for details on this step.
-
-   cd $WORK
-   mkdir keys
-   openssl genrsa -F4 -out keys/dev.key 2048
-   openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt
-
-Note: keys/dev.key contains your private key and is very secret. If anyone
-gets access to that file they can sign kernels with it. Keep it secure.
-
-
-Step 5: Sign the kernel
------------------------
-
-We need to use mkimage (which was built when you built U-Boot) to package the
-Linux kernel into a FIT (Flat Image Tree, a flexible file format that U-Boot
-can load) using the ITS file you just created.
-
-At the same time we must put the public key into U-Boot device tree, with the
-'required' property, which tells U-Boot that this key must be verified for the
-image to be valid. You will make this key available to U-Boot for booting in
-step 6.
-
-   ln -s $OKERNEL/dts/am335x-boneblack.dtb
-   ln -s $OKERNEL/Image
-   ln -s $UOUT/u-boot-dtb.img
-   cp $UOUT/arch/arm/dts/am335x-boneblack.dtb am335x-boneblack-pubkey.dtb
-   lzop Image
-   $UOUT/tools/mkimage -f sign.its -K am335x-boneblack-pubkey.dtb -k keys -r image.fit
-
-You should see something like this:
-
-FIT description: Beaglebone black
-Created:         Sun Jun  1 12:50:30 2014
- Image 0 (kernel)
-  Description:  unavailable
-  Created:      Sun Jun  1 12:50:30 2014
-  Type:         Kernel Image
-  Compression:  lzo compressed
-  Data Size:    7790938 Bytes = 7608.34 kB = 7.43 MB
-  Architecture: ARM
-  OS:           Linux
-  Load Address: 0x80008000
-  Entry Point:  0x80008000
-  Hash algo:    sha1
-  Hash value:   c94364646427e10f423837e559898ef02c97b988
- Image 1 (fdt-1)
-  Description:  beaglebone-black
-  Created:      Sun Jun  1 12:50:30 2014
-  Type:         Flat Device Tree
-  Compression:  uncompressed
-  Data Size:    31547 Bytes = 30.81 kB = 0.03 MB
-  Architecture: ARM
-  Hash algo:    sha1
-  Hash value:   cb09202f889d824f23b8e4404b781be5ad38a68d
- Default Configuration: 'conf-1'
- Configuration 0 (conf-1)
-  Description:  unavailable
-  Kernel:       kernel
-  FDT:          fdt-1
-
-
-Now am335x-boneblack-pubkey.dtb contains the public key and image.fit contains
-the signed kernel. Jump to step 6 if you like, or continue reading to increase
-your understanding.
-
-You can also run fit_check_sign to check it:
-
-   $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb
-
-which results in:
-
-Verifying Hash Integrity ... sha1,rsa2048:dev+
-## Loading kernel from FIT Image at 7fc6ee469000 ...
-   Using 'conf-1' configuration
-   Verifying Hash Integrity ...
-sha1,rsa2048:dev+
-OK
-
-   Trying 'kernel' kernel subimage
-     Description:  unavailable
-     Created:      Sun Jun  1 12:50:30 2014
-     Type:         Kernel Image
-     Compression:  lzo compressed
-     Data Size:    7790938 Bytes = 7608.34 kB = 7.43 MB
-     Architecture: ARM
-     OS:           Linux
-     Load Address: 0x80008000
-     Entry Point:  0x80008000
-     Hash algo:    sha1
-     Hash value:   c94364646427e10f423837e559898ef02c97b988
-   Verifying Hash Integrity ...
-sha1+
-OK
-
-Unimplemented compression type 4
-## Loading fdt from FIT Image at 7fc6ee469000 ...
-   Using 'conf-1' configuration
-   Trying 'fdt-1' fdt subimage
-     Description:  beaglebone-black
-     Created:      Sun Jun  1 12:50:30 2014
-     Type:         Flat Device Tree
-     Compression:  uncompressed
-     Data Size:    31547 Bytes = 30.81 kB = 0.03 MB
-     Architecture: ARM
-     Hash algo:    sha1
-     Hash value:   cb09202f889d824f23b8e4404b781be5ad38a68d
-   Verifying Hash Integrity ...
-sha1+
-OK
-
-   Loading Flat Device Tree ... OK
-
-## Loading ramdisk from FIT Image at 7fc6ee469000 ...
-   Using 'conf-1' configuration
-Could not find subimage node
-
-Signature check OK
-
-
-At the top, you see "sha1,rsa2048:dev+". This means that it checked an RSA key
-of size 2048 bits using SHA1 as the hash algorithm. The key name checked was
-'dev' and the '+' means that it verified. If it showed '-' that would be bad.
-
-Once the configuration is verified it is then possible to rely on the hashes
-in each image referenced by that configuration. So fit_check_sign goes on to
-load each of the images. We have a kernel and an FDT but no ramkdisk. In each
-case fit_check_sign checks the hash and prints sha1+ meaning that the SHA1
-hash verified. This means that none of the images has been tampered with.
-
-There is a test in test/vboot which uses U-Boot's sandbox build to verify that
-the above flow works.
-
-But it is fun to do this by hand, so you can load image.fit into a hex editor
-like ghex, and change a byte in the kernel:
-
-   $UOUT/tools/fit_info -f image.fit -n /images/kernel -p data
-NAME: kernel
-LEN: 7790938
-OFF: 168
-
-This tells us that the kernel starts at byte offset 168 (decimal) in image.fit
-and extends for about 7MB. Try changing a byte at 0x2000 (say) and run
-fit_check_sign again. You should see something like:
-
-Verifying Hash Integrity ... sha1,rsa2048:dev+
-## Loading kernel from FIT Image at 7f5a39571000 ...
-   Using 'conf-1' configuration
-   Verifying Hash Integrity ...
-sha1,rsa2048:dev+
-OK
-
-   Trying 'kernel' kernel subimage
-     Description:  unavailable
-     Created:      Sun Jun  1 13:09:21 2014
-     Type:         Kernel Image
-     Compression:  lzo compressed
-     Data Size:    7790938 Bytes = 7608.34 kB = 7.43 MB
-     Architecture: ARM
-     OS:           Linux
-     Load Address: 0x80008000
-     Entry Point:  0x80008000
-     Hash algo:    sha1
-     Hash value:   c94364646427e10f423837e559898ef02c97b988
-   Verifying Hash Integrity ...
-sha1 error
-Bad hash value for 'hash-1' hash node in 'kernel' image node
-Bad Data Hash
-
-## Loading fdt from FIT Image at 7f5a39571000 ...
-   Using 'conf-1' configuration
-   Trying 'fdt-1' fdt subimage
-     Description:  beaglebone-black
-     Created:      Sun Jun  1 13:09:21 2014
-     Type:         Flat Device Tree
-     Compression:  uncompressed
-     Data Size:    31547 Bytes = 30.81 kB = 0.03 MB
-     Architecture: ARM
-     Hash algo:    sha1
-     Hash value:   cb09202f889d824f23b8e4404b781be5ad38a68d
-   Verifying Hash Integrity ...
-sha1+
-OK
-
-   Loading Flat Device Tree ... OK
-
-## Loading ramdisk from FIT Image at 7f5a39571000 ...
-   Using 'conf-1' configuration
-Could not find subimage node
-
-Signature check Bad (error 1)
-
-
-It has detected the change in the kernel.
-
-You can also be sneaky and try to switch images, using the libfdt utilities
-that come with dtc (package name is device-tree-compiler but you will need a
-recent version like 1.4:
-
-   dtc -v
-Version: DTC 1.4.0
-
-First we can check which nodes are actually hashed by the configuration:
-
-   fdtget -l image.fit /
-images
-configurations
-
-   fdtget -l image.fit /configurations
-conf-1
-fdtget -l image.fit /configurations/conf-1
-signature-1
-
-   fdtget -p image.fit /configurations/conf-1/signature-1
-hashed-strings
-hashed-nodes
-timestamp
-signer-version
-signer-name
-value
-algo
-key-name-hint
-sign-images
-
-   fdtget image.fit /configurations/conf-1/signature-1 hashed-nodes
-/ /configurations/conf-1 /images/fdt-1 /images/fdt-1/hash /images/kernel /images/kernel/hash-1
-
-This gives us a bit of a look into the signature that mkimage added. Note you
-can also use fdtdump to list the entire device tree.
-
-Say we want to change the kernel that this configuration uses
-(/images/kernel). We could just put a new kernel in the image, but we will
-need to change the hash to match. Let's simulate that by changing a byte of
-the hash:
-
-    fdtget -tx image.fit /images/kernel/hash-1 value
-c9436464 6427e10f 423837e5 59898ef0 2c97b988
-    fdtput -tx image.fit /images/kernel/hash-1 value c9436464 6427e10f 423837e5 59898ef0 2c97b981
-
-Now check it again:
-
-   $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb
-Verifying Hash Integrity ... sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13
-rsa_verify_with_keynode: RSA failed to verify: -13
--
-Failed to verify required signature 'key-dev'
-Signature check Bad (error 1)
-
-This time we don't even get as far as checking the images, since the
-configuration signature doesn't match. We can't change any hashes without the
-signature check noticing. The configuration is essentially locked. U-Boot has
-a public key for which it requires a match, and will not permit the use of any
-configuration that does not match that public key. The only way the
-configuration will match is if it was signed by the matching private key.
-
-It would also be possible to add a new signature node that does match your new
-configuration. But that won't work since you are not allowed to change the
-configuration in any way. Try it with a fresh (valid) image if you like by
-running the mkimage link again. Then:
-
-   fdtput -p image.fit /configurations/conf-1/signature-1 value fred
-   $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb
-Verifying Hash Integrity ... -
-sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13
-rsa_verify_with_keynode: RSA failed to verify: -13
--
-Failed to verify required signature 'key-dev'
-Signature check Bad (error 1)
-
-
-Of course it would be possible to add an entirely new configuration and boot
-with that, but it still needs to be signed, so it won't help.
-
-
-6. Put the public key into U-Boot's image
------------------------------------------
-
-Having confirmed that the signature is doing its job, let's try it out in
-U-Boot on the board. U-Boot needs access to the public key corresponding to
-the private key that you signed with so that it can verify any kernels that
-you sign.
-
-   cd $UBOOT
-   make O=b/am335x_boneblack_vboot EXT_DTB=${WORK}/am335x-boneblack-pubkey.dtb
-
-Here we are overriding the normal device tree file with our one, which
-contains the public key.
-
-Now you have a special U-Boot image with the public key. It can verify can
-kernel that you sign with the private key as in step 5.
-
-If you like you can take a look at the public key information that mkimage
-added to U-Boot's device tree:
-
-   fdtget -p am335x-boneblack-pubkey.dtb /signature/key-dev
-required
-algo
-rsa,r-squared
-rsa,modulus
-rsa,n0-inverse
-rsa,num-bits
-key-name-hint
-
-This has information about the key and some pre-processed values which U-Boot
-can use to verify against it. These values are obtained from the public key
-certificate by mkimage, but require quite a bit of code to generate. To save
-code space in U-Boot, the information is extracted and written in raw form for
-U-Boot to easily use. The same mechanism is used in Google's Chrome OS.
-
-Notice the 'required' property. This marks the key as required - U-Boot will
-not boot any image that does not verify against this key.
-
-
-7. Put U-Boot and the kernel onto the board
--------------------------------------------
-
-The method here varies depending on how you are booting. For this example we
-are booting from an micro-SD card with two partitions, one for U-Boot and one
-for Linux. Put it into your machine and write U-Boot and the kernel to it.
-Here the card is /dev/sde:
-
-   cd $WORK
-   export UDEV=/dev/sde1   # Change thes two lines to the correct device
-   export KDEV=/dev/sde2
-   sudo mount $UDEV /mnt/tmp && sudo cp $UOUT/u-boot-dtb.img /mnt/tmp/u-boot.img  && sleep 1 && sudo umount $UDEV
-   sudo mount $KDEV /mnt/tmp && sudo cp $WORK/image.fit /mnt/tmp/boot/image.fit && sleep 1 && sudo umount $KDEV
-
-
-8. Try it
----------
-
-Boot the board using the commands below:
-
-   setenv bootargs console=ttyO0,115200n8 quiet root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait
-   ext2load mmc 0:2 82000000 /boot/image.fit
-   bootm 82000000
-
-You should then see something like this:
-
-U-Boot# setenv bootargs console=ttyO0,115200n8 quiet root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait
-U-Boot# ext2load mmc 0:2 82000000 /boot/image.fit
-7824930 bytes read in 589 ms (12.7 MiB/s)
-U-Boot# bootm 82000000
-## Loading kernel from FIT Image at 82000000 ...
-   Using 'conf-1' configuration
-   Verifying Hash Integrity ... sha1,rsa2048:dev+ OK
-   Trying 'kernel' kernel subimage
-     Description:  unavailable
-     Created:      2014-06-01  19:32:54 UTC
-     Type:         Kernel Image
-     Compression:  lzo compressed
-     Data Start:   0x820000a8
-     Data Size:    7790938 Bytes = 7.4 MiB
-     Architecture: ARM
-     OS:           Linux
-     Load Address: 0x80008000
-     Entry Point:  0x80008000
-     Hash algo:    sha1
-     Hash value:   c94364646427e10f423837e559898ef02c97b988
-   Verifying Hash Integrity ... sha1+ OK
-## Loading fdt from FIT Image at 82000000 ...
-   Using 'conf-1' configuration
-   Trying 'fdt-1' fdt subimage
-     Description:  beaglebone-black
-     Created:      2014-06-01  19:32:54 UTC
-     Type:         Flat Device Tree
-     Compression:  uncompressed
-     Data Start:   0x8276e2ec
-     Data Size:    31547 Bytes = 30.8 KiB
-     Architecture: ARM
-     Hash algo:    sha1
-     Hash value:   cb09202f889d824f23b8e4404b781be5ad38a68d
-   Verifying Hash Integrity ... sha1+ OK
-   Booting using the fdt blob at 0x8276e2ec
-   Uncompressing Kernel Image ... OK
-   Loading Device Tree to 8fff5000, end 8ffffb3a ... OK
-
-Starting kernel ...
-
-[    0.582377] omap_init_mbox: hwmod doesn't have valid attrs
-[    2.589651] musb-hdrc musb-hdrc.0.auto: Failed to request rx1.
-[    2.595830] musb-hdrc musb-hdrc.0.auto: musb_init_controller failed with status -517
-[    2.606470] musb-hdrc musb-hdrc.1.auto: Failed to request rx1.
-[    2.612723] musb-hdrc musb-hdrc.1.auto: musb_init_controller failed with status -517
-[    2.940808] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
-[    7.248889] libphy: PHY 4a101000.mdio:01 not found
-[    7.253995] net eth0: phy 4a101000.mdio:01 not found on slave 1
-systemd-fsck[83]: Angstrom: clean, 50607/218160 files, 306348/872448 blocks
-
-.---O---.
-|       |                  .-.           o o
-|   |   |-----.-----.-----.| |   .----..-----.-----.
-|       |     | __  |  ---'| '--.|  .-'|     |     |
-|   |   |  |  |     |---  ||  --'|  |  |  '  | | | |
-'---'---'--'--'--.  |-----''----''--'  '-----'-'-'-'
-                -'  |
-                '---'
-
-The Angstrom Distribution beaglebone ttyO0
-
-Angstrom v2012.12 - Kernel 3.14.1+
-
-beaglebone login:
-
-At this point your kernel has been verified and you can be sure that it is one
-that you signed. As an exercise, try changing image.fit as in step 5 and see
-what happens.
-
-
-Further Improvements
---------------------
-
-Several of the steps here can be easily automated. In particular it would be
-capital if signing and packaging a kernel were easy, perhaps a simple make
-target in the kernel.
-
-Some mention of how to use multiple .dtb files in a FIT might be useful.
-
-U-Boot's verified boot mechanism has not had a robust and independent security
-review. Such a review should look at the implementation and its resistance to
-attacks.
-
-Perhaps the verified boot feature could could be integrated into the Amstrom
-distribution.
-
-
-Simon Glass
-sjg@chromium.org
-2-June-14
diff --git a/doc/uImage.FIT/command_syntax_extensions.txt b/doc/uImage.FIT/command_syntax_extensions.txt
deleted file mode 100644
index 6a99089ab5..0000000000
--- a/doc/uImage.FIT/command_syntax_extensions.txt
+++ /dev/null
@@ -1,201 +0,0 @@
-Command syntax extensions for the new uImage format
-===================================================
-
-Author: Bartlomiej Sieka <tur@semihalf.com>
-
-With the introduction of the new uImage format, bootm command (and other
-commands as well) have to understand new syntax of the arguments. This is
-necessary in order to specify objects contained in the new uImage, on which
-bootm has to operate. This note attempts to first summarize bootm usage
-scenarios, and then introduces new argument syntax.
-
-
-bootm usage scenarios
----------------------
-
-Below is a summary of bootm usage scenarios, focused on booting a PowerPC
-Linux kernel. The purpose of the following list is to document a complete list
-of supported bootm usages.
-
-Note: U-Boot supports two methods of booting a PowerPC Linux kernel: old way,
-i.e., without passing the Flattened Device Tree (FDT), and new way, where the
-kernel is passed a pointer to the FDT. The boot method is indicated for each
-scenario.
-
-
-1.  bootm		boot image at the current address, equivalent to 2,3,8
-
-Old uImage:
-2.  bootm <addr1>		    /* single image at <addr1> */
-3.  bootm <addr1>		    /* multi-image at <addr1>  */
-4.  bootm <addr1> -		    /* multi-image at <addr1>  */
-5.  bootm <addr1> <addr2>	    /* single image at <addr1> */
-6.  bootm <addr1> <addr2> <addr3>   /* single image at <addr1> */
-7.  bootm <addr1> -	  <addr3>   /* single image at <addr1> */
-
-New uImage:
-8.  bootm <addr1>
-9.  bootm [<addr1>]:<subimg1>
-10. bootm [<addr1>]#<conf>[#<extra-conf[#...]]
-11. bootm [<addr1>]:<subimg1> [<addr2>]:<subimg2>
-12. bootm [<addr1>]:<subimg1> [<addr2>]:<subimg2> [<addr3>]:<subimg3>
-13. bootm [<addr1>]:<subimg1> [<addr2>]:<subimg2> <addr3>
-14. bootm [<addr1>]:<subimg1> -			  [<addr3>]:<subimg3>
-15. bootm [<addr1>]:<subimg1> -			  <addr3>
-
-
-Ad. 1. This is equivalent to cases 2,3,8, depending on the type of image at
-the current image address.
-- boot method: see cases 2,3,8
-
-Ad. 2. Boot kernel image located at <addr1>.
-- boot method: non-FDT
-
-Ad. 3. First and second components of the image at <addr1> are assumed to be a
-kernel and a ramdisk, respectively. The kernel is booted with initrd loaded
-with the ramdisk from the image.
-- boot method: depends on the number of components at <addr1>, and on whether
-  U-Boot is compiled with OF support:
-
-		    |	       2 components |	       3 components |
-		    |	   (kernel, initrd) | (kernel, initrd, fdt) |
----------------------------------------------------------------------
-#ifdef CONFIG_OF_*  |		    non-FDT |			FDT |
-#ifndef CONFIG_OF_* |		    non-FDT |		    non-FDT |
-
-Ad. 4. Similar to case 3, but the kernel is booted without initrd.  Second
-component of the multi-image is irrelevant (it can be a dummy, 1-byte file).
-- boot method: see case 3
-
-Ad. 5. Boot kernel image located at <addr1> with initrd loaded with ramdisk
-from the image at <addr2>.
-- boot method: non-FDT
-
-Ad. 6. <addr1> is the address of a kernel image, <addr2> is the address of a
-ramdisk image, and <addr3> is the address of a FDT binary blob.  Kernel is
-booted with initrd loaded with ramdisk from the image at <addr2>.
-- boot method: FDT
-
-Ad. 7. <addr1> is the address of a kernel image and <addr3> is the address of
-a FDT binary blob. Kernel is booted without initrd.
-- boot method: FDT
-
-Ad. 8. Image at <addr1> is assumed to contain a default configuration, which
-is booted.
-- boot method: FDT or non-FDT, depending on whether the default configuration
-  defines FDT
-
-Ad. 9. Similar to case 2: boot kernel stored in <subimg1> from the image at
-address <addr1>.
-- boot method: non-FDT
-
-Ad. 10. Boot configuration <conf> from the image at <addr1>.
-- boot method: FDT or non-FDT, depending on whether the configuration given
-  defines FDT
-
-Ad. 11. Equivalent to case 5: boot kernel stored in <subimg1> from the image
-at <addr1> with initrd loaded with ramdisk <subimg2> from the image at
-<addr2>.
-- boot method: non-FDT
-
-Ad. 12. Equivalent to case 6: boot kernel stored in <subimg1> from the image
-at <addr1> with initrd loaded with ramdisk <subimg2> from the image at
-<addr2>, and pass FDT blob <subimg3> from the image at <addr3>.
-- boot method: FDT
-
-Ad. 13. Similar to case 12, the difference being that <addr3> is the address
-of FDT binary blob that is to be passed to the kernel.
-- boot method: FDT
-
-Ad. 14. Equivalent to case 7: boot kernel stored in <subimg1> from the image
-at <addr1>, without initrd, and pass FDT blob <subimg3> from the image at
-<addr3>.
-- boot method: FDT
-
-Ad. 15. Similar to case 14, the difference being that <addr3> is the address
-of the FDT binary blob that is to be passed to the kernel.
-- boot method: FDT
-
-
-New uImage argument syntax
---------------------------
-
-New uImage support introduces two new forms for bootm arguments, with the
-following syntax:
-
-- new uImage sub-image specification
-<addr>:<sub-image unit_name>
-
-- new uImage configuration specification
-<addr>#<configuration unit_name>
-
-- new uImage configuration specification with extra configuration components
-<addr>#<configuration unit_name>[#<extra configuration unit_name>[#..]]
-
-The extra configuration currently is supported only for additional device tree
-overlays to apply on the base device tree supplied by the first configuration
-unit.
-
-Examples:
-
-- boot kernel "kernel-1" stored in a new uImage located at 200000:
-bootm 200000:kernel-1
-
-- boot configuration "cfg-1" from a new uImage located at 200000:
-bootm 200000#cfg-1
-
-- boot configuration "cfg-1" with extra "cfg-2" from a new uImage located
-  at 200000:
-bootm 200000#cfg-1#cfg-2
-
-- boot "kernel-1" from a new uImage at 200000 with initrd "ramdisk-2" found in
-  some other new uImage stored at address 800000:
-bootm 200000:kernel-1 800000:ramdisk-2
-
-- boot "kernel-2" from a new uImage at 200000, with initrd "ramdisk-1" and FDT
-  "fdt-1", both stored in some other new uImage located at 800000:
-bootm 200000:kernel-1 800000:ramdisk-1 800000:fdt-1
-
-- boot kernel "kernel-2" with initrd "ramdisk-2", both stored in a new uImage
-  at address 200000, with a raw FDT blob stored at address 600000:
-bootm 200000:kernel-2 200000:ramdisk-2 600000
-
-- boot kernel "kernel-2" from new uImage at 200000 with FDT "fdt-1" from the
-  same new uImage:
-bootm 200000:kernel-2 - 200000:fdt-1
-
-
-Note on current image address
------------------------------
-
-When bootm is called without arguments, the image at current image address is
-booted. The current image address is the address set most recently by a load
-command, etc, and is by default equal to CONFIG_SYS_LOAD_ADDR. For example, consider
-the following commands:
-
-tftp 200000 /tftpboot/kernel
-bootm
-Last command is equivalent to:
-bootm 200000
-
-In case of the new uImage argument syntax, the address portion of any argument
-can be omitted. If <addr3> is omitted, then it is assumed that image at
-<addr2> should be used. Similarly, when <addr2> is omitted, it is assumed that
-image at <addr1> should be used. If <addr1> is omitted, it is assumed that the
-current image address is to be used. For example, consider the following
-commands:
-
-tftp 200000 /tftpboot/uImage
-bootm :kernel-1
-Last command is equivalent to:
-bootm 200000:kernel-1
-
-tftp 200000 /tftpboot/uImage
-bootm 400000:kernel-1 :ramdisk-1
-Last command is equivalent to:
-bootm 400000:kernel-1 400000:ramdisk-1
-
-tftp 200000 /tftpboot/uImage
-bootm :kernel-1 400000:ramdisk-1 :fdt-1
-Last command is equivalent to:
-bootm 200000:kernel-1 400000:ramdisk-1 400000:fdt-1
diff --git a/doc/uImage.FIT/howto.txt b/doc/uImage.FIT/howto.txt
deleted file mode 100644
index 6dbd17dc8c..0000000000
--- a/doc/uImage.FIT/howto.txt
+++ /dev/null
@@ -1,411 +0,0 @@
-How to use images in the new image format
-=========================================
-
-Author: Bartlomiej Sieka <tur@semihalf.com>
-
-
-Overview
---------
-
-The new uImage format allows more flexibility in handling images of various
-types (kernel, ramdisk, etc.), it also enhances integrity protection of images
-with sha1 and md5 checksums.
-
-Two auxiliary tools are needed on the development host system in order to
-create an uImage in the new format: mkimage and dtc, although only one
-(mkimage) is invoked directly. dtc is called from within mkimage and operates
-behind the scenes, but needs to be present in the $PATH nevertheless. It is
-important that the dtc used has support for binary includes -- refer to
-
-	git://git.kernel.org/pub/scm/utils/dtc/dtc.git
-
-for its latest version. mkimage (together with dtc) takes as input
-an image source file, which describes the contents of the image and defines
-its various properties used during booting. By convention, image source file
-has the ".its" extension, also, the details of its format are given in
-doc/uImage.FIT/source_file_format.txt. The actual data that is to be included in
-the uImage (kernel, ramdisk, etc.) is specified in the image source file in the
-form of paths to appropriate data files. The outcome of the image creation
-process is a binary file (by convention with the ".itb" extension) that
-contains all the referenced data (kernel, ramdisk, etc.) and other information
-needed by U-Boot to handle the uImage properly. The uImage file is then
-transferred to the target (e.g., via tftp) and booted using the bootm command.
-
-To summarize the prerequisites needed for new uImage creation:
-- mkimage
-- dtc (with support for binary includes)
-- image source file (*.its)
-- image data file(s)
-
-
-Here's a graphical overview of the image creation and booting process:
-
-image source file     mkimage + dtc		  transfer to target
-	+	     ---------------> image file --------------------> bootm
-image data file(s)
-
-SPL usage
----------
-
-The SPL can make use of the new image format as well, this traditionally
-is used to ship multiple device tree files within one image. Code in the SPL
-will choose the one matching the current board and append this to the
-U-Boot proper binary to be automatically used up by it.
-Aside from U-Boot proper and one device tree blob the SPL can load multiple,
-arbitrary image files as well. These binaries should be specified in their
-own subnode under the /images node, which should then be referenced from one or
-multiple /configurations subnodes. The required images must be enumerated in
-the "loadables" property as a list of strings.
-
-If a platform specific image source file (.its) is shipped with the U-Boot
-source, it can be specified using the CONFIG_SPL_FIT_SOURCE Kconfig symbol.
-In this case it will be automatically used by U-Boot's Makefile to generate
-the image.
-If a static source file is not flexible enough, CONFIG_SPL_FIT_GENERATOR
-can point to a script which generates this image source file during
-the build process. It gets passed a list of device tree files (taken from the
-CONFIG_OF_LIST symbol).
-
-The SPL also records to a DT all additional images (called loadables) which are
-loaded. The information about loadables locations is passed via the DT node with
-fit-images name.
-
-Finally, if there are multiple xPL phases (e.g. SPL, VPL), images can be marked
-as intended for a particular phase using the 'phase' property. For example, if
-fit_image_load() is called with image_ph(IH_PHASE_SPL, IH_TYPE_FIRMWARE), then
-only the image listed into the "firmware" property where phase is set to "spl"
-will be loaded.
-
-Loadables Example
------------------
-Consider the following case for an ARM64 platform where U-Boot runs in EL2
-started by ATF where SPL is loading U-Boot (as loadables) and ATF (as firmware).
-
-/dts-v1/;
-
-/ {
-	description = "Configuration to load ATF before U-Boot";
-
-	images {
-		uboot {
-			description = "U-Boot (64-bit)";
-			data = /incbin/("u-boot-nodtb.bin");
-			type = "firmware";
-			os = "u-boot";
-			arch = "arm64";
-			compression = "none";
-			load = <0x8 0x8000000>;
-			entry = <0x8 0x8000000>;
-			hash {
-				algo = "md5";
-			};
-		};
-		atf {
-			description = "ARM Trusted Firmware";
-			data = /incbin/("bl31.bin");
-			type = "firmware";
-			os = "arm-trusted-firmware";
-			arch = "arm64";
-			compression = "none";
-			load = <0xfffea000>;
-			entry = <0xfffea000>;
-			hash {
-				algo = "md5";
-			};
-		};
-		fdt_1 {
-			description = "zynqmp-zcu102-revA";
-			data = /incbin/("arch/arm/dts/zynqmp-zcu102-revA.dtb");
-			type = "flat_dt";
-			arch = "arm64";
-			compression = "none";
-			load = <0x100000>;
-			hash {
-				algo = "md5";
-			};
-		};
-	};
-	configurations {
-		default = "config_1";
-
-		config_1 {
-			description = "zynqmp-zcu102-revA";
-			firmware = "atf";
-			loadables = "uboot";
-			fdt = "fdt_1";
-		};
-	};
-};
-
-In this case the SPL records via fit-images DT node the information about
-loadables U-Boot image.
-
-ZynqMP> fdt addr $fdtcontroladdr
-ZynqMP> fdt print /fit-images
-fit-images {
-	uboot {
-		os = "u-boot";
-		type = "firmware";
-		size = <0x001017c8>;
-		entry = <0x00000008 0x08000000>;
-		load = <0x00000008 0x08000000>;
-	};
-};
-
-As you can see entry and load properties are 64bit wide to support loading
-images above 4GB (in past entry and load properties where just 32bit).
-
-
-Example 1 -- old-style (non-FDT) kernel booting
------------------------------------------------
-
-Consider a simple scenario, where a PPC Linux kernel built from sources on the
-development host is to be booted old-style (non-FDT) by U-Boot on an embedded
-target. Assume that the outcome of the build is vmlinux.bin.gz, a file which
-contains a gzip-compressed PPC Linux kernel (the only data file in this case).
-The uImage can be produced using the image source file
-doc/uImage.FIT/kernel.its (note that kernel.its assumes that vmlinux.bin.gz is
-in the current working directory; if desired, an alternative path can be
-specified in the kernel.its file). Here's how to create the image and inspect
-its contents:
-
-[on the host system]
-$ mkimage -f kernel.its kernel.itb
-DTC: dts->dtb  on file "kernel.its"
-$
-$ mkimage -l kernel.itb
-FIT description: Simple image with single Linux kernel
-Created:	 Tue Mar 11 17:26:15 2008
- Image 0 (kernel)
-  Description:	Vanilla Linux kernel
-  Type:		Kernel Image
-  Compression:	gzip compressed
-  Data Size:	943347 Bytes = 921.24 kB = 0.90 MB
-  Architecture: PowerPC
-  OS:		Linux
-  Load Address: 0x00000000
-  Entry Point:	0x00000000
-  Hash algo:	crc32
-  Hash value:	2ae2bb40
-  Hash algo:	sha1
-  Hash value:	3c200f34e2c226ddc789240cca0c59fc54a67cf4
- Default Configuration: 'config-1'
- Configuration 0 (config-1)
-  Description:	Boot Linux kernel
-  Kernel:	kernel
-
-
-The resulting image file kernel.itb can be now transferred to the target,
-inspected and booted (note that first three U-Boot commands below are shown
-for completeness -- they are part of the standard booting procedure and not
-specific to the new image format).
-
-[on the target system]
-=> print nfsargs
-nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
-=> print addip
-addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off panic=1
-=> run nfsargs addip
-=> tftp 900000 /path/to/tftp/location/kernel.itb
-Using FEC device
-TFTP from server 192.168.1.1; our IP address is 192.168.160.5
-Filename '/path/to/tftp/location/kernel.itb'.
-Load address: 0x900000
-Loading: #################################################################
-done
-Bytes transferred = 944464 (e6950 hex)
-=> iminfo
-
-## Checking Image at 00900000 ...
-   FIT image found
-   FIT description: Simple image with single Linux kernel
-   Created:	    2008-03-11	16:26:15 UTC
-    Image 0 (kernel)
-     Description:  Vanilla Linux kernel
-     Type:	   Kernel Image
-     Compression:  gzip compressed
-     Data Start:   0x009000e0
-     Data Size:    943347 Bytes = 921.2 kB
-     Architecture: PowerPC
-     OS:	   Linux
-     Load Address: 0x00000000
-     Entry Point:  0x00000000
-     Hash algo:    crc32
-     Hash value:   2ae2bb40
-     Hash algo:    sha1
-     Hash value:   3c200f34e2c226ddc789240cca0c59fc54a67cf4
-    Default Configuration: 'config-1'
-    Configuration 0 (config-1)
-     Description:  Boot Linux kernel
-     Kernel:	   kernel
-
-=> bootm
-## Booting kernel from FIT Image at 00900000 ...
-   Using 'config-1' configuration
-   Trying 'kernel' kernel subimage
-     Description:  Vanilla Linux kernel
-     Type:	   Kernel Image
-     Compression:  gzip compressed
-     Data Start:   0x009000e0
-     Data Size:    943347 Bytes = 921.2 kB
-     Architecture: PowerPC
-     OS:	   Linux
-     Load Address: 0x00000000
-     Entry Point:  0x00000000
-     Hash algo:    crc32
-     Hash value:   2ae2bb40
-     Hash algo:    sha1
-     Hash value:   3c200f34e2c226ddc789240cca0c59fc54a67cf4
-   Verifying Hash Integrity ... crc32+ sha1+ OK
-   Uncompressing Kernel Image ... OK
-Memory BAT mapping: BAT2=256Mb, BAT3=0Mb, residual: 0Mb
-Linux version 2.4.25 (m8@hekate) (gcc version 4.0.0 (DENX ELDK 4.0 4.0.0)) #2 czw lip 5 17:56:18 CEST 2007
-On node 0 totalpages: 65536
-zone(0): 65536 pages.
-zone(1): 0 pages.
-zone(2): 0 pages.
-Kernel command line: root=/dev/nfs rw nfsroot=192.168.1.1:/opt/eldk-4.1/ppc_6xx ip=192.168.160.5:192.168.1.1::255.255.0.0:lite5200b:eth0:off panic=1
-Calibrating delay loop... 307.20 BogoMIPS
-
-
-Example 2 -- new-style (FDT) kernel booting
--------------------------------------------
-
-Consider another simple scenario, where a PPC Linux kernel is to be booted
-new-style, i.e., with a FDT blob. In this case there are two prerequisite data
-files: vmlinux.bin.gz (Linux kernel) and target.dtb (FDT blob). The uImage can
-be produced using image source file doc/uImage.FIT/kernel_fdt.its like this
-(note again, that both prerequisite data files are assumed to be present in
-the current working directory -- image source file kernel_fdt.its can be
-modified to take the files from some other location if needed):
-
-[on the host system]
-$ mkimage -f kernel_fdt.its kernel_fdt.itb
-DTC: dts->dtb  on file "kernel_fdt.its"
-$
-$ mkimage -l kernel_fdt.itb
-FIT description: Simple image with single Linux kernel and FDT blob
-Created:	 Tue Mar 11 16:29:22 2008
- Image 0 (kernel)
-  Description:	Vanilla Linux kernel
-  Type:		Kernel Image
-  Compression:	gzip compressed
-  Data Size:	1092037 Bytes = 1066.44 kB = 1.04 MB
-  Architecture: PowerPC
-  OS:		Linux
-  Load Address: 0x00000000
-  Entry Point:	0x00000000
-  Hash algo:	crc32
-  Hash value:	2c0cc807
-  Hash algo:	sha1
-  Hash value:	264b59935470e42c418744f83935d44cdf59a3bb
- Image 1 (fdt-1)
-  Description:	Flattened Device Tree blob
-  Type:		Flat Device Tree
-  Compression:	uncompressed
-  Data Size:	16384 Bytes = 16.00 kB = 0.02 MB
-  Architecture: PowerPC
-  Hash algo:	crc32
-  Hash value:	0d655d71
-  Hash algo:	sha1
-  Hash value:	25ab4e15cd4b8a5144610394560d9c318ce52def
- Default Configuration: 'conf-1'
- Configuration 0 (conf-1)
-  Description:	Boot Linux kernel with FDT blob
-  Kernel:	kernel
-  FDT:		fdt-1
-
-
-The resulting image file kernel_fdt.itb can be now transferred to the target,
-inspected and booted:
-
-[on the target system]
-=> tftp 900000 /path/to/tftp/location/kernel_fdt.itb
-Using FEC device
-TFTP from server 192.168.1.1; our IP address is 192.168.160.5
-Filename '/path/to/tftp/location/kernel_fdt.itb'.
-Load address: 0x900000
-Loading: #################################################################
-	 ###########
-done
-Bytes transferred = 1109776 (10ef10 hex)
-=> iminfo
-
-## Checking Image at 00900000 ...
-   FIT image found
-   FIT description: Simple image with single Linux kernel and FDT blob
-   Created:	    2008-03-11	15:29:22 UTC
-    Image 0 (kernel)
-     Description:  Vanilla Linux kernel
-     Type:	   Kernel Image
-     Compression:  gzip compressed
-     Data Start:   0x009000ec
-     Data Size:    1092037 Bytes =  1 MB
-     Architecture: PowerPC
-     OS:	   Linux
-     Load Address: 0x00000000
-     Entry Point:  0x00000000
-     Hash algo:    crc32
-     Hash value:   2c0cc807
-     Hash algo:    sha1
-     Hash value:   264b59935470e42c418744f83935d44cdf59a3bb
-    Image 1 (fdt-1)
-     Description:  Flattened Device Tree blob
-     Type:	   Flat Device Tree
-     Compression:  uncompressed
-     Data Start:   0x00a0abdc
-     Data Size:    16384 Bytes = 16 kB
-     Architecture: PowerPC
-     Hash algo:    crc32
-     Hash value:   0d655d71
-     Hash algo:    sha1
-     Hash value:   25ab4e15cd4b8a5144610394560d9c318ce52def
-    Default Configuration: 'conf-1'
-    Configuration 0 (conf-1)
-     Description:  Boot Linux kernel with FDT blob
-     Kernel:	   kernel
-     FDT:	   fdt-1
-=> bootm
-## Booting kernel from FIT Image at 00900000 ...
-   Using 'conf-1' configuration
-   Trying 'kernel' kernel subimage
-     Description:  Vanilla Linux kernel
-     Type:	   Kernel Image
-     Compression:  gzip compressed
-     Data Start:   0x009000ec
-     Data Size:    1092037 Bytes =  1 MB
-     Architecture: PowerPC
-     OS:	   Linux
-     Load Address: 0x00000000
-     Entry Point:  0x00000000
-     Hash algo:    crc32
-     Hash value:   2c0cc807
-     Hash algo:    sha1
-     Hash value:   264b59935470e42c418744f83935d44cdf59a3bb
-   Verifying Hash Integrity ... crc32+ sha1+ OK
-   Uncompressing Kernel Image ... OK
-## Flattened Device Tree from FIT Image at 00900000
-   Using 'conf-1' configuration
-   Trying 'fdt-1' FDT blob subimage
-     Description:  Flattened Device Tree blob
-     Type:	   Flat Device Tree
-     Compression:  uncompressed
-     Data Start:   0x00a0abdc
-     Data Size:    16384 Bytes = 16 kB
-     Architecture: PowerPC
-     Hash algo:    crc32
-     Hash value:   0d655d71
-     Hash algo:    sha1
-     Hash value:   25ab4e15cd4b8a5144610394560d9c318ce52def
-   Verifying Hash Integrity ... crc32+ sha1+ OK
-   Booting using the fdt blob at 0xa0abdc
-   Loading Device Tree to 007fc000, end 007fffff ... OK
-[    0.000000] Using lite5200 machine description
-[    0.000000] Linux version 2.6.24-rc6-gaebecdfc (m8@hekate) (gcc version 4.0.0 (DENX ELDK 4.1 4.0.0)) #1 Sat Jan 12 15:38:48 CET 2008
-
-
-Example 3 -- advanced booting
------------------------------
-
-Refer to doc/uImage.FIT/multi.its for an image source file that allows more
-sophisticated booting scenarios (multiple kernels, ramdisks and fdt blobs).
diff --git a/doc/uImage.FIT/kernel.its b/doc/uImage.FIT/kernel.its
deleted file mode 100644
index 77ddf622de..0000000000
--- a/doc/uImage.FIT/kernel.its
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Simple U-Boot uImage source file containing a single kernel
- */
-
-/dts-v1/;
-
-/ {
-	description = "Simple image with single Linux kernel";
-	#address-cells = <1>;
-
-	images {
-		kernel {
-			description = "Vanilla Linux kernel";
-			data = /incbin/("./vmlinux.bin.gz");
-			type = "kernel";
-			arch = "ppc";
-			os = "linux";
-			compression = "gzip";
-			load = <00000000>;
-			entry = <00000000>;
-			hash-1 {
-				algo = "crc32";
-			};
-			hash-2 {
-				algo = "sha1";
-			};
-		};
-	};
-
-	configurations {
-		default = "config-1";
-		config-1 {
-			description = "Boot Linux kernel";
-			kernel = "kernel";
-		};
-	};
-};
-
-
-
-For x86 a setup node is also required: see x86-fit-boot.txt.
-
-/dts-v1/;
-
-/ {
-	description = "Simple image with single Linux kernel on x86";
-	#address-cells = <1>;
-
-	images {
-		kernel {
-			description = "Vanilla Linux kernel";
-			data = /incbin/("./image.bin.lzo");
-			type = "kernel";
-			arch = "x86";
-			os = "linux";
-			compression = "lzo";
-			load = <0x01000000>;
-			entry = <0x00000000>;
-			hash-2 {
-				algo = "sha1";
-			};
-		};
-
-		setup {
-			description = "Linux setup.bin";
-			data = /incbin/("./setup.bin");
-			type = "x86_setup";
-			arch = "x86";
-			os = "linux";
-			compression = "none";
-			load = <0x00090000>;
-			entry = <0x00090000>;
-			hash-2 {
-				algo = "sha1";
-			};
-		};
-	};
-
-	configurations {
-		default = "config-1";
-		config-1 {
-			description = "Boot Linux kernel";
-			kernel = "kernel";
-			setup = "setup";
-		};
-	};
-};
-
-Note: the above assumes a 32-bit kernel. To directly boot a 64-bit kernel,
-change both arch values to "x86_64". U-Boot will then change to 64-bit mode
-before booting the kernel (see boot_linux_kernel()).
diff --git a/doc/uImage.FIT/kernel_fdt.its b/doc/uImage.FIT/kernel_fdt.its
deleted file mode 100644
index 000d85b8e0..0000000000
--- a/doc/uImage.FIT/kernel_fdt.its
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Simple U-Boot uImage source file containing a single kernel and FDT blob
- */
-
-/dts-v1/;
-
-/ {
-	description = "Simple image with single Linux kernel and FDT blob";
-	#address-cells = <1>;
-
-	images {
-		kernel {
-			description = "Vanilla Linux kernel";
-			data = /incbin/("./vmlinux.bin.gz");
-			type = "kernel";
-			arch = "ppc";
-			os = "linux";
-			compression = "gzip";
-			load = <00000000>;
-			entry = <00000000>;
-			hash-1 {
-				algo = "crc32";
-			};
-			hash-2 {
-				algo = "sha1";
-			};
-		};
-		fdt-1 {
-			description = "Flattened Device Tree blob";
-			data = /incbin/("./target.dtb");
-			type = "flat_dt";
-			arch = "ppc";
-			compression = "none";
-			hash-1 {
-				algo = "crc32";
-			};
-			hash-2 {
-				algo = "sha1";
-			};
-		};
-	};
-
-	configurations {
-		default = "conf-1";
-		conf-1 {
-			description = "Boot Linux kernel with FDT blob";
-			kernel = "kernel";
-			fdt = "fdt-1";
-		};
-	};
-};
diff --git a/doc/uImage.FIT/kernel_fdts_compressed.its b/doc/uImage.FIT/kernel_fdts_compressed.its
deleted file mode 100644
index 8f81106efc..0000000000
--- a/doc/uImage.FIT/kernel_fdts_compressed.its
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * U-Boot uImage source file with a kernel and multiple compressed FDT blobs.
- * Since the FDTs are compressed, configurations must provide a compatible
- * string to match directly.
- */
-
-/dts-v1/;
-
-/ {
-	description = "Image with single Linux kernel and compressed FDT blobs";
-	#address-cells = <1>;
-
-	images {
-		kernel {
-			description = "Vanilla Linux kernel";
-			data = /incbin/("./vmlinux.bin.gz");
-			type = "kernel";
-			arch = "ppc";
-			os = "linux";
-			compression = "gzip";
-			load = <00000000>;
-			entry = <00000000>;
-			hash-1 {
-				algo = "crc32";
-			};
-			hash-2 {
-				algo = "sha1";
-			};
-		};
-		fdt@1 {
-			description = "Flattened Device Tree blob 1";
-			data = /incbin/("./myboard-var1.dtb");
-			type = "flat_dt";
-			arch = "ppc";
-			compression = "gzip";
-			hash-1 {
-				algo = "crc32";
-			};
-			hash-2 {
-				algo = "sha1";
-			};
-		};
-		fdt@2 {
-			description = "Flattened Device Tree blob 2";
-			data = /incbin/("./myboard-var2.dtb");
-			type = "flat_dt";
-			arch = "ppc";
-			compression = "lzma";
-			hash-1 {
-				algo = "crc32";
-			};
-			hash-2 {
-				algo = "sha1";
-			};
-		};
-	};
-
-	configurations {
-		default = "conf@1";
-		conf@1 {
-			description = "Boot Linux kernel with FDT blob 1";
-			kernel = "kernel";
-			fdt = "fdt@1";
-			compatible = "myvendor,myboard-variant1";
-		};
-		conf@2 {
-			description = "Boot Linux kernel with FDT blob 2";
-			kernel = "kernel";
-			fdt = "fdt@2";
-			compatible = "myvendor,myboard-variant2";
-		};
-	};
-};
diff --git a/doc/uImage.FIT/multi-with-fpga.its b/doc/uImage.FIT/multi-with-fpga.its
deleted file mode 100644
index 021cbc7cf4..0000000000
--- a/doc/uImage.FIT/multi-with-fpga.its
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
- * This example makes use of the 'loadables' field
- */
-
-/dts-v1/;
-
-/ {
-	description = "Configuration to load fpga before Kernel";
-	#address-cells = <1>;
-
-	images {
-		fdt-1 {
-			description = "zc706";
-			data = /incbin/("/tftpboot/devicetree.dtb");
-			type = "flat_dt";
-			arch = "arm";
-			compression = "none";
-			load = <0x10000000>;
-			hash-1 {
-				algo = "md5";
-			};
-		};
-
-		fpga {
-			description = "FPGA";
-			data = /incbin/("/tftpboot/download.bit");
-			type = "fpga";
-			arch = "arm";
-			compression = "none";
-			load = <0x30000000>;
-			compatible = "u-boot,fpga-legacy"
-			hash-1 {
-				algo = "md5";
-			};
-		};
-
-		linux_kernel {
-			description = "Linux";
-			data = /incbin/("/tftpboot/zImage");
-			type = "kernel";
-			arch = "arm";
-			os = "linux";
-			compression = "none";
-			load = <0x8000>;
-			entry = <0x8000>;
-			hash-1 {
-				algo = "md5";
-			};
-		};
-	};
-
-	configurations {
-		default = "config-2";
-		config-1 {
-			description = "Linux";
-			kernel = "linux_kernel";
-			fdt = "fdt-1";
-		};
-
-		config-2 {
-			description = "Linux with fpga";
-			kernel = "linux_kernel";
-			fdt = "fdt-1";
-			loadables = "fpga";
-		};
-	};
-};
diff --git a/doc/uImage.FIT/multi-with-loadables.its b/doc/uImage.FIT/multi-with-loadables.its
deleted file mode 100644
index 4d4909f832..0000000000
--- a/doc/uImage.FIT/multi-with-loadables.its
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
- * This example makes use of the 'loadables' field
- */
-
-/dts-v1/;
-
-/ {
-	description = "Configuration to load a Xen Kernel";
-	#address-cells = <1>;
-
-	images {
-		xen_kernel {
-			description = "xen binary";
-			data = /incbin/("./xen");
-			type = "kernel";
-			arch = "arm";
-			os = "linux";
-			compression = "none";
-			load = <0xa0000000>;
-			entry = <0xa0000000>;
-			hash-1 {
-				algo = "md5";
-			};
-		};
-
-		fdt-1 {
-			description = "xexpress-ca15 tree blob";
-			data = /incbin/("./vexpress-v2p-ca15-tc1.dtb");
-			type = "flat_dt";
-			arch = "arm";
-			compression = "none";
-			load = <0xb0000000>;
-			hash-1 {
-				algo = "md5";
-			};
-		};
-
-		fdt-2 {
-			description = "xexpress-ca15 tree blob";
-			data = /incbin/("./vexpress-v2p-ca15-tc1.dtb");
-			type = "flat_dt";
-			arch = "arm";
-			compression = "none";
-			load = <0xb0400000>;
-			hash-1 {
-				algo = "md5";
-			};
-		};
-
-		linux_kernel {
-			description = "Linux Image";
-			data = /incbin/("./Image");
-			type = "kernel";
-			arch = "arm";
-			os = "linux";
-			compression = "none";
-			load = <0xa0000000>;
-			entry = <0xa0000000>;
-			hash-1 {
-				algo = "md5";
-			};
-		};
-	};
-
-	configurations {
-		default = "config-2";
-
-		config-1 {
-			description = "Just plain Linux";
-			kernel = "linux_kernel";
-			fdt = "fdt-1";
-		};
-
-		config-2 {
-			description = "Xen one loadable";
-			kernel = "xen_kernel";
-			fdt = "fdt-1";
-			loadables = "linux_kernel";
-		};
-
-		config-3 {
-			description = "Xen two loadables";
-			kernel = "xen_kernel";
-			fdt = "fdt-1";
-			loadables = "linux_kernel", "fdt-2";
-		};
-	};
-};
diff --git a/doc/uImage.FIT/multi.its b/doc/uImage.FIT/multi.its
deleted file mode 100644
index 26c8dad6a2..0000000000
--- a/doc/uImage.FIT/multi.its
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
- */
-
-/dts-v1/;
-
-/ {
-	description = "Various kernels, ramdisks and FDT blobs";
-	#address-cells = <1>;
-
-	images {
-		kernel-1 {
-			description = "vanilla-2.6.23";
-			data = /incbin/("./vmlinux.bin.gz");
-			type = "kernel";
-			arch = "ppc";
-			os = "linux";
-			compression = "gzip";
-			load = <00000000>;
-			entry = <00000000>;
-			hash-1 {
-				algo = "md5";
-			};
-			hash-2 {
-				algo = "sha1";
-			};
-		};
-
-		kernel-2 {
-			description = "2.6.23-denx";
-			data = /incbin/("./2.6.23-denx.bin.gz");
-			type = "kernel";
-			arch = "ppc";
-			os = "linux";
-			compression = "gzip";
-			load = <00000000>;
-			entry = <00000000>;
-			hash-1 {
-				algo = "sha1";
-			};
-		};
-
-		kernel-3 {
-			description = "2.4.25-denx";
-			data = /incbin/("./2.4.25-denx.bin.gz");
-			type = "kernel";
-			arch = "ppc";
-			os = "linux";
-			compression = "gzip";
-			load = <00000000>;
-			entry = <00000000>;
-			hash-1 {
-				algo = "md5";
-			};
-		};
-
-		ramdisk-1 {
-			description = "eldk-4.2-ramdisk";
-			data = /incbin/("./eldk-4.2-ramdisk");
-			type = "ramdisk";
-			arch = "ppc";
-			os = "linux";
-			compression = "gzip";
-			load = <00000000>;
-			entry = <00000000>;
-			hash-1 {
-				algo = "sha1";
-			};
-		};
-
-		ramdisk-2 {
-			description = "eldk-3.1-ramdisk";
-			data = /incbin/("./eldk-3.1-ramdisk");
-			type = "ramdisk";
-			arch = "ppc";
-			os = "linux";
-			compression = "gzip";
-			load = <00000000>;
-			entry = <00000000>;
-			hash-1 {
-				algo = "crc32";
-			};
-		};
-
-		fdt-1 {
-			description = "tqm5200-fdt";
-			data = /incbin/("./tqm5200.dtb");
-			type = "flat_dt";
-			arch = "ppc";
-			compression = "none";
-			hash-1 {
-				algo = "crc32";
-			};
-		};
-
-		fdt-2 {
-			description = "tqm5200s-fdt";
-			data = /incbin/("./tqm5200s.dtb");
-			type = "flat_dt";
-			arch = "ppc";
-			compression = "none";
-			load = <00700000>;
-			hash-1 {
-				algo = "sha1";
-			};
-		};
-
-	};
-
-	configurations {
-		default = "config-1";
-
-		config-1 {
-			description = "tqm5200 vanilla-2.6.23 configuration";
-			kernel = "kernel-1";
-			ramdisk = "ramdisk-1";
-			fdt = "fdt-1";
-		};
-
-		config-2 {
-			description = "tqm5200s denx-2.6.23 configuration";
-			kernel = "kernel-2";
-			ramdisk = "ramdisk-1";
-			fdt = "fdt-2";
-		};
-
-		config-3 {
-			description = "tqm5200s denx-2.4.25 configuration";
-			kernel = "kernel-3";
-			ramdisk = "ramdisk-2";
-		};
-	};
-};
diff --git a/doc/uImage.FIT/multi_spl.its b/doc/uImage.FIT/multi_spl.its
deleted file mode 100644
index 5942199744..0000000000
--- a/doc/uImage.FIT/multi_spl.its
+++ /dev/null
@@ -1,96 +0,0 @@
-/dts-v1/;
-
-/*
- * (Bogus) example FIT image description file demonstrating the usage
- * of multiple images loaded by the SPL.
- * Several binaries will be loaded at their respective load addresses.
- *
- * For booting U-Boot, "firmware" is searched first. If not found, "loadables"
- * is used to identify images to be loaded into memory. If falcon boot is
- * enabled, "kernel" is searched first. If not found, it falls back to the
- * same flow as booting U-Boot. Changing image type will result skipping
- * specific image.
- *
- * Finally the one image specifying an entry point will be entered by the SPL.
- */
-
-/ {
-	description = "multiple firmware blobs and U-Boot, loaded by SPL";
-	#address-cells = <0x1>;
-
-	images {
-
-		uboot {
-			description = "U-Boot (64-bit)";
-			type = "standalone";
-			arch = "arm64";
-			compression = "none";
-			load = <0x4a000000>;
-		};
-
-		atf {
-			description = "ARM Trusted Firmware";
-			type = "firmware";
-			arch = "arm64";
-			compression = "none";
-			load = <0x18000>;
-			entry = <0x18000>;
-		};
-
-		mgmt-firmware {
-			description = "arisc management processor firmware";
-			type = "firmware";
-			arch = "or1k";
-			compression = "none";
-			load = <0x40000>;
-		};
-
-		fdt-1 {
-			description = "Pine64+ DT";
-			type = "flat_dt";
-			compression = "none";
-			load = <0x4fa00000>;
-			arch = "arm64";
-		};
-
-		fdt-2 {
-			description = "Pine64 DT";
-			type = "flat_dt";
-			compression = "none";
-			load = <0x4fa00000>;
-			arch = "arm64";
-		};
-
-		kernel {
-			description = "4.7-rc5 kernel";
-			type = "kernel";
-			compression = "none";
-			load = <0x40080000>;
-			arch = "arm64";
-		};
-
-		initrd {
-			description = "Debian installer initrd";
-			type = "ramdisk";
-			compression = "none";
-			load = <0x4fe00000>;
-			arch = "arm64";
-		};
-	};
-
-	configurations {
-		default = "config-1";
-
-		config-1 {
-			description = "sun50i-a64-pine64-plus";
-			loadables = "uboot", "atf", "kernel", "initrd";
-			fdt = "fdt-1";
-		};
-
-		config-2 {
-			description = "sun50i-a64-pine64";
-			loadables = "uboot", "atf", "mgmt-firmware";
-			fdt = "fdt-2";
-		};
-	};
-};
diff --git a/doc/uImage.FIT/overlay-fdt-boot.txt b/doc/uImage.FIT/overlay-fdt-boot.txt
deleted file mode 100644
index dddc4db1a6..0000000000
--- a/doc/uImage.FIT/overlay-fdt-boot.txt
+++ /dev/null
@@ -1,225 +0,0 @@
-U-Boot FDT Overlay FIT usage
-============================
-
-Introduction
-------------
-In many cases it is desirable to have a single FIT image support a multitude
-of similar boards and their expansion options. The same kernel on DT enabled
-platforms can support this easily enough by providing a DT blob upon boot
-that matches the desired configuration.
-
-This document focuses on specifically using overlays as part of a FIT image.
-General information regarding overlays including its syntax and building it
-can be found in doc/README.fdt-overlays
-
-Configuration without overlays
-------------------------------
-
-Take a hypothetical board named 'foo' where there are different supported
-revisions, reva and revb. Assume that both board revisions can use add a bar
-add-on board, while only the revb board can use a baz add-on board.
-
-Without using overlays the configuration would be as follows for every case.
-
-	/dts-v1/;
-	/ {
-		images {
-			kernel {
-				data = /incbin/("./zImage");
-				type = "kernel";
-				arch = "arm";
-				os = "linux";
-				load = <0x82000000>;
-				entry = <0x82000000>;
-			};
-			fdt-1 {
-				data = /incbin/("./foo-reva.dtb");
-				type = "flat_dt";
-				arch = "arm";
-			};
-			fdt-2 {
-				data = /incbin/("./foo-revb.dtb");
-				type = "flat_dt";
-				arch = "arm";
-			};
-			fdt-3 {
-				data = /incbin/("./foo-reva-bar.dtb");
-				type = "flat_dt";
-				arch = "arm";
-			};
-			fdt-4 {
-				data = /incbin/("./foo-revb-bar.dtb");
-				type = "flat_dt";
-				arch = "arm";
-			};
-			fdt-5 {
-				data = /incbin/("./foo-revb-baz.dtb");
-				type = "flat_dt";
-				arch = "arm";
-			};
-			fdt-6 {
-				data = /incbin/("./foo-revb-bar-baz.dtb");
-				type = "flat_dt";
-				arch = "arm";
-			};
-		};
-
-		configurations {
-			default = "foo-reva.dtb;
-			foo-reva.dtb {
-				kernel = "kernel";
-				fdt = "fdt-1";
-			};
-			foo-revb.dtb {
-				kernel = "kernel";
-				fdt = "fdt-2";
-			};
-			foo-reva-bar.dtb {
-				kernel = "kernel";
-				fdt = "fdt-3";
-			};
-			foo-revb-bar.dtb {
-				kernel = "kernel";
-				fdt = "fdt-4";
-			};
-			foo-revb-baz.dtb {
-				kernel = "kernel";
-				fdt = "fdt-5";
-			};
-			foo-revb-bar-baz.dtb {
-				kernel = "kernel";
-				fdt = "fdt-6";
-			};
-		};
-	};
-
-Note the blob needs to be compiled for each case and the combinatorial explosion of
-configurations. A typical device tree blob is in the low hunderds of kbytes so a
-multitude of configuration grows the image quite a bit.
-
-Booting this image is done by using
-
-	# bootm <addr>#<config>
-
-Where config is one of:
-	foo-reva.dtb, foo-revb.dtb, foo-reva-bar.dtb, foo-revb-bar.dtb,
-	foo-revb-baz.dtb, foo-revb-bar-baz.dtb
-
-This selects the DTB to use when booting.
-
-Configuration using overlays
-----------------------------
-
-Device tree overlays can be applied to a base DT and result in the same blob
-being passed to the booting kernel. This saves on space and avoid the combinatorial
-explosion problem.
-
-	/dts-v1/;
-	/ {
-		images {
-			kernel {
-				data = /incbin/("./zImage");
-				type = "kernel";
-				arch = "arm";
-				os = "linux";
-				load = <0x82000000>;
-				entry = <0x82000000>;
-			};
-			fdt-1 {
-				data = /incbin/("./foo.dtb");
-				type = "flat_dt";
-				arch = "arm";
-				load = <0x87f00000>;
-			};
-			fdt-2 {
-				data = /incbin/("./reva.dtbo");
-				type = "flat_dt";
-				arch = "arm";
-				load = <0x87fc0000>;
-			};
-			fdt-3 {
-				data = /incbin/("./revb.dtbo");
-				type = "flat_dt";
-				arch = "arm";
-				load = <0x87fc0000>;
-			};
-			fdt-4 {
-				data = /incbin/("./bar.dtbo");
-				type = "flat_dt";
-				arch = "arm";
-				load = <0x87fc0000>;
-			};
-			fdt-5 {
-				data = /incbin/("./baz.dtbo");
-				type = "flat_dt";
-				arch = "arm";
-				load = <0x87fc0000>;
-			};
-		};
-
-		configurations {
-			default = "foo-reva.dtb;
-			foo-reva.dtb {
-				kernel = "kernel";
-				fdt = "fdt-1", "fdt-2";
-			};
-			foo-revb.dtb {
-				kernel = "kernel";
-				fdt = "fdt-1", "fdt-3";
-			};
-			foo-reva-bar.dtb {
-				kernel = "kernel";
-				fdt = "fdt-1", "fdt-2", "fdt-4";
-			};
-			foo-revb-bar.dtb {
-				kernel = "kernel";
-				fdt = "fdt-1", "fdt-3", "fdt-4";
-			};
-			foo-revb-baz.dtb {
-				kernel = "kernel";
-				fdt = "fdt-1", "fdt-3", "fdt-5";
-			};
-			foo-revb-bar-baz.dtb {
-				kernel = "kernel";
-				fdt = "fdt-1", "fdt-3", "fdt-4", "fdt-5";
-			};
-			bar {
-				fdt = "fdt-4";
-			};
-			baz {
-				fdt = "fdt-5";
-			};
-		};
-	};
-
-Booting this image is exactly the same as the non-overlay example.
-u-boot will retrieve the base blob and apply the overlays in sequence as
-they are declared in the configuration.
-
-Note the minimum amount of different DT blobs, as well as the requirement for
-the DT blobs to have a load address; the overlay application requires the blobs
-to be writeable.
-
-Configuration using overlays and feature selection
---------------------------------------------------
-
-Although the configuration in the previous section works is a bit inflexible
-since it requires all possible configuration options to be laid out before
-hand in the FIT image. For the add-on boards the extra config selection method
-might make sense.
-
-Note the two bar & baz configuration nodes. To boot a reva board with
-the bar add-on board enabled simply use:
-
-	# bootm <addr>#foo-reva.dtb#bar
-
-While booting a revb with bar and baz is as follows:
-
-	# bootm <addr>#foo-revb.dtb#bar#baz
-
-The limitation for a feature selection configuration node is that a single
-fdt option is currently supported.
-
-Pantelis Antoniou
-pantelis.antoniou@konsulko.com
-12/6/2017
diff --git a/doc/uImage.FIT/sec_firmware_ppa.its b/doc/uImage.FIT/sec_firmware_ppa.its
deleted file mode 100644
index a7acde17cf..0000000000
--- a/doc/uImage.FIT/sec_firmware_ppa.its
+++ /dev/null
@@ -1,49 +0,0 @@
-/dts-v1/;
-
-/*
- * Example FIT image description file demonstrating the usage
- * of SEC Firmware and multiple loadable images loaded by the u-boot.
- * For booting PPA (SEC Firmware), "firmware" is searched and loaded.
- *
- * Multiple binaries will be loaded as "loadables" (if present) at their
- * respective load offsets from firmware image address.
- */
-
-/{
-	description = "PPA Firmware";
-	#address-cells = <1>;
-	images {
-		firmware@1 {
-			description = "PPA Firmware: <version>";
-			data = /incbin/("../obj/monitor.bin");
-			type = "firmware";
-			arch = "arm64";
-			compression = "none";
-		};
-		trustedOS@1 {
-			description = "Trusted OS";
-			data = /incbin/("../../tee.bin");
-			type = "OS";
-			arch = "arm64";
-			compression = "none";
-			load = <0x00200000>;
-		};
-		fuse_scr {
-			description = "Fuse Script";
-			data = /incbin/("../../fuse_scr.bin");
-			type = "firmware";
-			arch = "arm64";
-			compression = "none";
-			load = <0x00180000>;
-		};
-	};
-
-	configurations {
-		default = "config-1";
-		config-1 {
-			description = "PPA Secure firmware";
-			firmware = "firmware@1";
-			loadables = "trustedOS@1", "fuse_scr";
-		};
-	};
-};
diff --git a/doc/uImage.FIT/sign-configs.its b/doc/uImage.FIT/sign-configs.its
deleted file mode 100644
index 9e992c1988..0000000000
--- a/doc/uImage.FIT/sign-configs.its
+++ /dev/null
@@ -1,45 +0,0 @@
-/dts-v1/;
-
-/ {
-	description = "Chrome OS kernel image with one or more FDT blobs";
-	#address-cells = <1>;
-
-	images {
-		kernel {
-			data = /incbin/("test-kernel.bin");
-			type = "kernel_noload";
-			arch = "sandbox";
-			os = "linux";
-			compression = "lzo";
-			load = <0x4>;
-			entry = <0x8>;
-			kernel-version = <1>;
-			hash-1 {
-				algo = "sha1";
-			};
-		};
-		fdt-1 {
-			description = "snow";
-			data = /incbin/("sandbox-kernel.dtb");
-			type = "flat_dt";
-			arch = "sandbox";
-			compression = "none";
-			fdt-version = <1>;
-			hash-1 {
-				algo = "sha1";
-			};
-		};
-	};
-	configurations {
-		default = "conf-1";
-		conf-1 {
-			kernel = "kernel";
-			fdt = "fdt-1";
-			signature {
-				algo = "sha1,rsa2048";
-				key-name-hint = "dev";
-				sign-images = "fdt", "kernel";
-			};
-		};
-	};
-};
diff --git a/doc/uImage.FIT/sign-images.its b/doc/uImage.FIT/sign-images.its
deleted file mode 100644
index 18c759e9e6..0000000000
--- a/doc/uImage.FIT/sign-images.its
+++ /dev/null
@@ -1,42 +0,0 @@
-/dts-v1/;
-
-/ {
-	description = "Chrome OS kernel image with one or more FDT blobs";
-	#address-cells = <1>;
-
-	images {
-		kernel {
-			data = /incbin/("test-kernel.bin");
-			type = "kernel_noload";
-			arch = "sandbox";
-			os = "linux";
-			compression = "none";
-			load = <0x4>;
-			entry = <0x8>;
-			kernel-version = <1>;
-			signature {
-				algo = "sha1,rsa2048";
-				key-name-hint = "dev";
-			};
-		};
-		fdt-1 {
-			description = "snow";
-			data = /incbin/("sandbox-kernel.dtb");
-			type = "flat_dt";
-			arch = "sandbox";
-			compression = "none";
-			fdt-version = <1>;
-			signature {
-				algo = "sha1,rsa2048";
-				key-name-hint = "dev";
-			};
-		};
-	};
-	configurations {
-		default = "conf-1";
-		conf-1 {
-			kernel = "kernel";
-			fdt = "fdt-1";
-		};
-	};
-};
diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt
deleted file mode 100644
index 21eb3894aa..0000000000
--- a/doc/uImage.FIT/signature.txt
+++ /dev/null
@@ -1,707 +0,0 @@
-U-Boot FIT Signature Verification
-=================================
-
-Introduction
-------------
-FIT supports hashing of images so that these hashes can be checked on
-loading. This protects against corruption of the image. However it does not
-prevent the substitution of one image for another.
-
-The signature feature allows the hash to be signed with a private key such
-that it can be verified using a public key later. Provided that the private
-key is kept secret and the public key is stored in a non-volatile place,
-any image can be verified in this way.
-
-See verified-boot.txt for more general information on verified boot.
-
-
-Concepts
---------
-Some familiarity with public key cryptography is assumed in this section.
-
-The procedure for signing is as follows:
-
-   - hash an image in the FIT
-   - sign the hash with a private key to produce a signature
-   - store the resulting signature in the FIT
-
-The procedure for verification is:
-
-   - read the FIT
-   - obtain the public key
-   - extract the signature from the FIT
-   - hash the image from the FIT
-   - verify (with the public key) that the extracted signature matches the
-       hash
-
-The signing is generally performed by mkimage, as part of making a firmware
-image for the device. The verification is normally done in U-Boot on the
-device.
-
-
-Algorithms
-----------
-In principle any suitable algorithm can be used to sign and verify a hash.
-U-Boot supports a few hashing and verification algorithms. See below for
-details.
-
-While it is acceptable to bring in large cryptographic libraries such as
-openssl on the host side (e.g. mkimage), it is not desirable for U-Boot.
-For the run-time verification side, it is important to keep code and data
-size as small as possible.
-
-For this reason the RSA image verification uses pre-processed public keys
-which can be used with a very small amount of code - just some extraction
-of data from the FDT and exponentiation mod n. Code size impact is a little
-under 5KB on Tegra Seaboard, for example.
-
-It is relatively straightforward to add new algorithms if required. If
-another RSA variant is needed, then it can be added with the
-U_BOOT_CRYPTO_ALGO() macro. If another algorithm is needed (such as DSA) then
-it can be placed in a directory alongside lib/rsa/, and its functions added
-using U_BOOT_CRYPTO_ALGO().
-
-
-Creating an RSA key pair and certificate
-----------------------------------------
-To create a new public/private key pair, size 2048 bits:
-
-$ openssl genpkey -algorithm RSA -out keys/dev.key \
-    -pkeyopt rsa_keygen_bits:2048 -pkeyopt rsa_keygen_pubexp:65537
-
-To create a certificate for this containing the public key:
-
-$ openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt
-
-If you like you can look at the public key also:
-
-$ openssl rsa -in keys/dev.key -pubout
-
-
-Device Tree Bindings
---------------------
-The following properties are required in the FIT's signature node(s) to
-allow the signer to operate. These should be added to the .its file.
-Signature nodes sit at the same level as hash nodes and are called
-signature-1, signature-2, etc.
-
-- algo: Algorithm name (e.g. "sha1,rsa2048")
-
-- key-name-hint: Name of key to use for signing. The keys will normally be in
-a single directory (parameter -k to mkimage). For a given key <name>, its
-private key is stored in <name>.key and the certificate is stored in
-<name>.crt.
-
-When the image is signed, the following properties are added (mandatory):
-
-- value: The signature data (e.g. 256 bytes for 2048-bit RSA)
-
-When the image is signed, the following properties are optional:
-
-- timestamp: Time when image was signed (standard Unix time_t format)
-
-- signer-name: Name of the signer (e.g. "mkimage")
-
-- signer-version: Version string of the signer (e.g. "2013.01")
-
-- comment: Additional information about the signer or image
-
-- padding: The padding algorithm, it may be pkcs-1.5 or pss,
-	if no value is provided we assume pkcs-1.5
-
-For config bindings (see Signed Configurations below), the following
-additional properties are optional:
-
-- sign-images: A list of images to sign, each being a property of the conf
-node that contains then. The default is "kernel,fdt" which means that these
-two images will be looked up in the config and signed if present.
-
-For config bindings, these properties are added by the signer:
-
-- hashed-nodes: A list of nodes which were hashed by the signer. Each is
-	a string - the full path to node. A typical value might be:
-
-	hashed-nodes = "/", "/configurations/conf-1", "/images/kernel",
-		"/images/kernel/hash-1", "/images/fdt-1",
-		"/images/fdt-1/hash-1";
-
-- hashed-strings: The start and size of the string region of the FIT that
-	was hashed
-
-Example: See sign-images.its for an example image tree source file and
-sign-configs.its for config signing.
-
-
-Public Key Storage
-------------------
-In order to verify an image that has been signed with a public key we need to
-have a trusted public key. This cannot be stored in the signed image, since
-it would be easy to alter. For this implementation we choose to store the
-public key in U-Boot's control FDT (using CONFIG_OF_CONTROL).
-
-Public keys should be stored as sub-nodes in a /signature node. Required
-properties are:
-
-- algo: Algorithm name (e.g. "sha1,rsa2048" or "sha256,ecdsa256")
-
-Optional properties are:
-
-- key-name-hint: Name of key used for signing. This is only a hint since it
-is possible for the name to be changed. Verification can proceed by checking
-all available signing keys until one matches.
-
-- required: If present this indicates that the key must be verified for the
-image / configuration to be considered valid. Only required keys are
-normally verified by the FIT image booting algorithm. Valid values are
-"image" to force verification of all images, and "conf" to force verification
-of the selected configuration (which then relies on hashes in the images to
-verify those).
-
-Each signing algorithm has its own additional properties.
-
-For RSA the following are mandatory:
-
-- rsa,num-bits: Number of key bits (e.g. 2048)
-- rsa,modulus: Modulus (N) as a big-endian multi-word integer
-- rsa,exponent: Public exponent (E) as a 64 bit unsigned integer
-- rsa,r-squared: (2^num-bits)^2 as a big-endian multi-word integer
-- rsa,n0-inverse: -1 / modulus[0] mod 2^32
-
-For ECDSA the following are mandatory:
-- ecdsa,curve: Name of ECDSA curve (e.g. "prime256v1")
-- ecdsa,x-point: Public key X coordinate as a big-endian multi-word integer
-- ecdsa,y-point: Public key Y coordinate as a big-endian multi-word integer
-
-These parameters can be added to a binary device tree using parameter -K of the
-mkimage command::
-
-    tools/mkimage -f fit.its -K control.dtb -k keys -r image.fit
-
-Here is an example of a generated device tree node::
-
-	signature {
-		key-dev {
-			required = "conf";
-			algo = "sha256,rsa2048";
-			rsa,r-squared = <0xb76d1acf 0xa1763ca5 0xeb2f126
-					0x742edc80 0xd3f42177 0x9741d9d9
-					0x35bb476e 0xff41c718 0xd3801430
-					0xf22537cb 0xa7e79960 0xae32a043
-					0x7da1427a 0x341d6492 0x3c2762f5
-					0xaac04726 0x5b262d96 0xf984e86d
-					0xb99443c7 0x17080c33 0x940f6892
-					0xd57a95d1 0x6ea7b691 0xc5038fa8
-					0x6bb48a6e 0x73f1b1ea 0x37160841
-					0xe05715ce 0xa7c45bbd 0x690d82d5
-					0x99c2454c 0x6ff117b3 0xd830683b
-					0x3f81c9cf 0x1ca38a91 0x0c3392e4
-					0xd817c625 0x7b8e9a24 0x175b89ea
-					0xad79f3dc 0x4d50d7b4 0x9d4e90f8
-					0xad9e2939 0xc165d6a4 0x0ada7e1b
-					0xfb1bf495 0xfc3131c2 0xb8c6e604
-					0xc2761124 0xf63de4a6 0x0e9565f9
-					0xc8e53761 0x7e7a37a5 0xe99dcdae
-					0x9aff7e1e 0xbd44b13d 0x6b0e6aa4
-					0x038907e4 0x8e0d6850 0xef51bc20
-					0xf73c94af 0x88bea7b1 0xcbbb1b30
-					0xd024b7f3>;
-			rsa,modulus = <0xc0711d6cb 0x9e86db7f 0x45986dbe
-				       0x023f1e8c9 0xe1a4c4d0 0x8a0dfdc9
-				       0x023ba0c48 0x06815f6a 0x5caa0654
-				       0x07078c4b7 0x3d154853 0x40729023
-				       0x0b007c8fe 0x5a3647e5 0x23b41e20
-				       0x024720591 0x66915305 0x0e0b29b0
-				       0x0de2ad30d 0x8589430f 0xb1590325
-				       0x0fb9f5d5e 0x9eba752a 0xd88e6de9
-				       0x056b3dcc6 0x9a6b8e61 0x6784f61f
-				       0x000f39c21 0x5eec6b33 0xd78e4f78
-				       0x0921a305f 0xaa2cc27e 0x1ca917af
-				       0x06e1134f4 0xd48cac77 0x4e914d07
-				       0x0f707aa5a 0x0d141f41 0x84677f1d
-				       0x0ad47a049 0x028aedb6 0xd5536fcf
-				       0x03fef1e4f 0x133a03d2 0xfd7a750a
-				       0x0f9159732 0xd207812e 0x6a807375
-				       0x06434230d 0xc8e22dad 0x9f29b3d6
-				       0x07c44ac2b 0xfa2aad88 0xe2429504
-				       0x041febd41 0x85d0d142 0x7b194d65
-				       0x06e5d55ea 0x41116961 0xf3181dde
-				       0x068bf5fbc 0x3dd82047 0x00ee647e
-				       0x0d7a44ab3>;
-			rsa,exponent = <0x00 0x10001>;
-			rsa,n0-inverse = <0xb3928b85>;
-			rsa,num-bits = <0x800>;
-			key-name-hint = "dev";
-		};
-	};
-
-
-Signed Configurations
----------------------
-While signing images is useful, it does not provide complete protection
-against several types of attack. For example, it it possible to create a
-FIT with the same signed images, but with the configuration changed such
-that a different one is selected (mix and match attack). It is also possible
-to substitute a signed image from an older FIT version into a newer FIT
-(roll-back attack).
-
-As an example, consider this FIT:
-
-/ {
-	images {
-		kernel-1 {
-			data = <data for kernel1>
-			signature-1 {
-				algo = "sha1,rsa2048";
-				value = <...kernel signature 1...>
-			};
-		};
-		kernel-2 {
-			data = <data for kernel2>
-			signature-1 {
-				algo = "sha1,rsa2048";
-				value = <...kernel signature 2...>
-			};
-		};
-		fdt-1 {
-			data = <data for fdt1>;
-			signature-1 {
-				algo = "sha1,rsa2048";
-				value = <...fdt signature 1...>
-			};
-		};
-		fdt-2 {
-			data = <data for fdt2>;
-			signature-1 {
-				algo = "sha1,rsa2048";
-				value = <...fdt signature 2...>
-			};
-		};
-	};
-	configurations {
-		default = "conf-1";
-		conf-1 {
-			kernel = "kernel-1";
-			fdt = "fdt-1";
-		};
-		conf-2 {
-			kernel = "kernel-2";
-			fdt = "fdt-2";
-		};
-	};
-};
-
-Since both kernels are signed it is easy for an attacker to add a new
-configuration 3 with kernel 1 and fdt 2:
-
-	configurations {
-		default = "conf-1";
-		conf-1 {
-			kernel = "kernel-1";
-			fdt = "fdt-1";
-		};
-		conf-2 {
-			kernel = "kernel-2";
-			fdt = "fdt-2";
-		};
-		conf-3 {
-			kernel = "kernel-1";
-			fdt = "fdt-2";
-		};
-	};
-
-With signed images, nothing protects against this. Whether it gains an
-advantage for the attacker is debatable, but it is not secure.
-
-To solve this problem, we support signed configurations. In this case it
-is the configurations that are signed, not the image. Each image has its
-own hash, and we include the hash in the configuration signature.
-
-So the above example is adjusted to look like this:
-
-/ {
-	images {
-		kernel-1 {
-			data = <data for kernel1>
-			hash-1 {
-				algo = "sha1";
-				value = <...kernel hash 1...>
-			};
-		};
-		kernel-2 {
-			data = <data for kernel2>
-			hash-1 {
-				algo = "sha1";
-				value = <...kernel hash 2...>
-			};
-		};
-		fdt-1 {
-			data = <data for fdt1>;
-			hash-1 {
-				algo = "sha1";
-				value = <...fdt hash 1...>
-			};
-		};
-		fdt-2 {
-			data = <data for fdt2>;
-			hash-1 {
-				algo = "sha1";
-				value = <...fdt hash 2...>
-			};
-		};
-	};
-	configurations {
-		default = "conf-1";
-		conf-1 {
-			kernel = "kernel-1";
-			fdt = "fdt-1";
-			signature-1 {
-				algo = "sha1,rsa2048";
-				value = <...conf 1 signature...>;
-			};
-		};
-		conf-2 {
-			kernel = "kernel-2";
-			fdt = "fdt-2";
-			signature-1 {
-				algo = "sha1,rsa2048";
-				value = <...conf 1 signature...>;
-			};
-		};
-	};
-};
-
-
-You can see that we have added hashes for all images (since they are no
-longer signed), and a signature to each configuration. In the above example,
-mkimage will sign configurations/conf-1, the kernel and fdt that are
-pointed to by the configuration (/images/kernel-1, /images/kernel-1/hash-1,
-/images/fdt-1, /images/fdt-1/hash-1) and the root structure of the image
-(so that it isn't possible to add or remove root nodes). The signature is
-written into /configurations/conf-1/signature-1/value. It can easily be
-verified later even if the FIT has been signed with other keys in the
-meantime.
-
-
-Details
--------
-The signature node contains a property ('hashed-nodes') which lists all the
-nodes that the signature was made over.  The image is walked in order and each
-tag processed as follows:
-- DTB_BEGIN_NODE: The tag and the following name are included in the signature
-  if the node or its parent are present in 'hashed-nodes'
-- DTB_END_NODE: The tag is included in the signature if the node or its parent
-  are present in 'hashed-nodes'
-- DTB_PROPERTY: The tag, the length word, the offset in the string table, and
-  the data are all included if the current node is present in 'hashed-nodes'
-  and the property name is not 'data'.
-- DTB_END: The tag is always included in the signature.
-- DTB_NOP: The tag is included in the signature if the current node is present
-  in 'hashed-nodes'
-
-In addition, the signature contains a property 'hashed-strings' which contains
-the offset and length in the string table of the strings that are to be
-included in the signature (this is done last).
-
-IMPORTANT:  To verify the signature outside u-boot, it is vital to not only
-calculate the hash of the image and verify the signature with that, but also to
-calculate the hashes of the kernel, fdt, and ramdisk images and check those
-match the hash values in the corresponding 'hash*' subnodes.
-
-
-Verification
-------------
-FITs are verified when loaded. After the configuration is selected a list
-of required images is produced. If there are 'required' public keys, then
-each image must be verified against those keys. This means that every image
-that might be used by the target needs to be signed with 'required' keys.
-
-This happens automatically as part of a bootm command when FITs are used.
-
-For Signed Configurations, the default verification behavior can be changed by
-the following optional property in /signature node in U-Boot's control FDT.
-
-- required-mode: Valid values are "any" to allow verified boot to succeed if
-the selected configuration is signed by any of the 'required' keys, and "all"
-to allow verified boot to succeed if the selected configuration is signed by
-all of the 'required' keys.
-
-This property can be added to a binary device tree using fdtput as shown in
-below examples::
-
-	fdtput -t s control.dtb /signature required-mode any
-	fdtput -t s control.dtb /signature required-mode all
-
-
-Enabling FIT Verification
--------------------------
-In addition to the options to enable FIT itself, the following CONFIGs must
-be enabled:
-
-CONFIG_FIT_SIGNATURE - enable signing and verification in FITs
-CONFIG_RSA - enable RSA algorithm for signing
-CONFIG_ECDSA - enable ECDSA algorithm for signing
-
-WARNING: When relying on signed FIT images with required signature check
-the legacy image format is default disabled by not defining
-CONFIG_LEGACY_IMAGE_FORMAT
-
-
-Testing
--------
-An easy way to test signing and verification is to use the test script
-provided in test/vboot/vboot_test.sh. This uses sandbox (a special version
-of U-Boot which runs under Linux) to show the operation of a 'bootm'
-command loading and verifying images.
-
-A sample run is show below:
-
-$ make O=sandbox sandbox_config
-$ make O=sandbox
-$ O=sandbox ./test/vboot/vboot_test.sh
-
-
-Simple Verified Boot Test
-=========================
-
-Please see doc/uImage.FIT/verified-boot.txt for more information
-
-/home/hs/ids/u-boot/sandbox/tools/mkimage -D -I dts -O dtb -p 2000
-Build keys
-do sha1 test
-Build FIT with signed images
-Test Verified Boot Run: unsigned signatures:: OK
-Sign images
-Test Verified Boot Run: signed images: OK
-Build FIT with signed configuration
-Test Verified Boot Run: unsigned config: OK
-Sign images
-Test Verified Boot Run: signed config: OK
-check signed config on the host
-Signature check OK
-OK
-Test Verified Boot Run: signed config: OK
-Test Verified Boot Run: signed config with bad hash: OK
-do sha256 test
-Build FIT with signed images
-Test Verified Boot Run: unsigned signatures:: OK
-Sign images
-Test Verified Boot Run: signed images: OK
-Build FIT with signed configuration
-Test Verified Boot Run: unsigned config: OK
-Sign images
-Test Verified Boot Run: signed config: OK
-check signed config on the host
-Signature check OK
-OK
-Test Verified Boot Run: signed config: OK
-Test Verified Boot Run: signed config with bad hash: OK
-
-Test passed
-
-
-Software signing: keydir vs keyfile
------------------------------------
-
-In the simplest case, signing is done by giving mkimage the 'keyfile'. This is
-the path to a file containing the signing key.
-
-The alternative is to pass the 'keydir' argument. In this case the filename of
-the key is derived from the 'keydir' and the "key-name-hint" property in the
-FIT. In this case the "key-name-hint" property is mandatory, and the key must
-exist in "<keydir>/<key-name-hint>.<ext>" Here the extension "ext" is
-specific to the signing algorithm.
-
-
-Hardware Signing with PKCS#11 or with HSM
------------------------------------------
-
-Securely managing private signing keys can challenging, especially when the
-keys are stored on the file system of a computer that is connected to the
-Internet. If an attacker is able to steal the key, they can sign malicious FIT
-images which will appear genuine to your devices.
-
-An alternative solution is to keep your signing key securely stored on hardware
-device like a smartcard, USB token or Hardware Security Module (HSM) and have
-them perform the signing. PKCS#11 is standard for interfacing with these crypto
-device.
-
-Requirements:
-Smartcard/USB token/HSM which can work with some openssl engine
-openssl
-
-For pkcs11 engine usage:
-libp11 (provides pkcs11 engine)
-p11-kit (recommended to simplify setup)
-opensc (for smartcards and smartcard like USB devices)
-gnutls (recommended for key generation, p11tool)
-
-For generic HSMs respective openssl engine must be installed and locateable by
-openssl. This may require setting up LD_LIBRARY_PATH if engine is not installed
-to openssl's default search paths.
-
-PKCS11 engine support forms "key id" based on "keydir" and with
-"key-name-hint". "key-name-hint" is used as "object" name (if not defined in
-keydir). "keydir" (if defined) is used to define (prefix for) which PKCS11 source
-is being used for lookup up for the key.
-
-PKCS11 engine key ids:
-   "pkcs11:<keydir>;object=<key-name-hint>;type=<public|private>"
-or, if keydir contains "object="
-   "pkcs11:<keydir>;type=<public|private>"
-or
-   "pkcs11:object=<key-name-hint>;type=<public|private>",
-
-Generic HSM engine support forms "key id" based on "keydir" and with
-"key-name-hint". If "keydir" is specified for mkimage it is used as a prefix in
-"key id" and is appended with "key-name-hint".
-
-Generic engine key ids:
-  "<keydir><key-name-hint>"
-or
-  "<key-name-hint>"
-
-In order to set the pin in the HSM, an environment variable "MKIMAGE_SIGN_PIN"
-can be specified.
-
-The following examples use the Nitrokey Pro using pkcs11 engine. Instructions
-for other devices may vary.
-
-Notes on pkcs11 engine setup:
-
-Make sure p11-kit, opensc are installed and that p11-kit is setup to use opensc.
-/usr/share/p11-kit/modules/opensc.module should be present on your system.
-
-
-Generating Keys On the Nitrokey:
-
-$ gpg --card-edit
-
-Reader ...........: Nitrokey Nitrokey Pro (xxxxxxxx0000000000000000) 00 00
-Application ID ...: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-Version ..........: 2.1
-Manufacturer .....: ZeitControl
-Serial number ....: xxxxxxxx
-Name of cardholder: [not set]
-Language prefs ...: de
-Sex ..............: unspecified
-URL of public key : [not set]
-Login data .......: [not set]
-Signature PIN ....: forced
-Key attributes ...: rsa2048 rsa2048 rsa2048
-Max. PIN lengths .: 32 32 32
-PIN retry counter : 3 0 3
-Signature counter : 0
-Signature key ....: [none]
-Encryption key....: [none]
-Authentication key: [none]
-General key info..: [none]
-
-gpg/card> generate
-Make off-card backup of encryption key? (Y/n) n
-
-Please note that the factory settings of the PINs are
-  PIN = '123456' Admin PIN = '12345678'
-You should change them using the command --change-pin
-
-What keysize do you want for the Signature key? (2048) 4096
-The card will now be re-configured to generate a key of 4096 bits
-Note: There is no guarantee that the card supports the requested size.
-  If the key generation does not succeed, please check the
-  documentation of your card to see what sizes are allowed.
-What keysize do you want for the Encryption key? (2048) 4096
-The card will now be re-configured to generate a key of 4096 bits
-What keysize do you want for the Authentication key? (2048) 4096
-The card will now be re-configured to generate a key of 4096 bits
-Please specify how long the key should be valid.
-  0 = key does not expire
-  <n> = key expires in n days
-  <n>w = key expires in n weeks
-  <n>m = key expires in n months
-  <n>y = key expires in n years
-Key is valid for? (0)
-Key does not expire at all
-Is this correct? (y/N) y
-
-GnuPG needs to construct a user ID to identify your key.
-
-Real name: John Doe
-Email address: john.doe@email.com
-Comment:
-You selected this USER-ID:
-  "John Doe <john.doe@email.com>"
-
-Change (N)ame, (C)omment, (E)mail or (O)kay/(Q)uit? o
-
-
-Using p11tool to get the token URL:
-
-Depending on system configuration, gpg-agent may need to be killed first.
-
-$ p11tool --provider /usr/lib/opensc-pkcs11.so --list-tokens
-Token 0:
-URL: pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29
-Label: OpenPGP card (User PIN (sig))
-Type: Hardware token
-Manufacturer: ZeitControl
-Model: PKCS#15 emulated
-Serial: 000xxxxxxxxx
-Module: (null)
-
-
-Token 1:
-URL: pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%29
-Label: OpenPGP card (User PIN)
-Type: Hardware token
-Manufacturer: ZeitControl
-Model: PKCS#15 emulated
-Serial: 000xxxxxxxxx
-Module: (null)
-
-Use the portion of the signature token URL after "pkcs11:" as the keydir argument (-k) to mkimage below.
-
-
-Use the URL of the token to list the private keys:
-
-$ p11tool --login --provider /usr/lib/opensc-pkcs11.so --list-privkeys \
-"pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29"
-Token 'OpenPGP card (User PIN (sig))' with URL 'pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29' requires user PIN
-Enter PIN:
-Object 0:
-URL: pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29;id=%01;object=Signature%20key;type=private
-Type: Private key
-Label: Signature key
-Flags: CKA_PRIVATE; CKA_NEVER_EXTRACTABLE; CKA_SENSITIVE;
-ID: 01
-
-Use the label, in this case "Signature key" as the key-name-hint in your FIT.
-
-Create the fitImage:
-$ ./tools/mkimage -f fit-image.its fitImage
-
-
-Sign the fitImage with the hardware key:
-
-$ ./tools/mkimage -F -k \
-"model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29" \
--K u-boot.dtb -N pkcs11 -r fitImage
-
-
-Future Work
------------
-- Roll-back protection using a TPM is done using the tpm command. This can
-be scripted, but we might consider a default way of doing this, built into
-bootm.
-
-
-Possible Future Work
---------------------
-- More sandbox tests for failure modes
-- Passwords for keys/certificates
-- Perhaps implement OAEP
-- Enhance bootm to permit scripted signature verification (so that a script
-can verify an image but not actually boot it)
-
-
-Simon Glass
-sjg@chromium.org
-1-1-13
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
deleted file mode 100644
index 269e1fa0b5..0000000000
--- a/doc/uImage.FIT/source_file_format.txt
+++ /dev/null
@@ -1,322 +0,0 @@
-U-Boot new uImage source file format (bindings definition)
-==========================================================
-
-Author: Marian Balakowicz <m8@semihalf.com>
-External data additions, 25/1/16 Simon Glass <sjg@chromium.org>
-
-1) Introduction
----------------
-
-Evolution of the 2.6 Linux kernel for embedded PowerPC systems introduced new
-booting method which requires that hardware description is available to the
-kernel in the form of Flattened Device Tree.
-
-Booting with a Flattened Device Tree is much more flexible and is intended to
-replace direct passing of 'struct bd_info' which was used to boot pre-FDT
-kernels.
-
-However, U-Boot needs to support both techniques to provide backward
-compatibility for platforms which are not FDT ready. Number of elements
-playing role in the booting process has increased and now includes the FDT
-blob. Kernel image, FDT blob and possibly ramdisk image - all must be placed
-in the system memory and passed to bootm as a arguments. Some of them may be
-missing: FDT is not present for legacy platforms, ramdisk is always optional.
-Additionally, old uImage format has been extended to support multi sub-images
-but the support is limited by simple format of the legacy uImage structure.
-Single binary header 'struct legacy_img_hdr' is not flexible enough to cover all
-possible scenarios.
-
-All those factors combined clearly show that there is a need for new, more
-flexible, multi component uImage format.
-
-
-2) New uImage format assumptions
---------------------------------
-
-a) Implementation
-
-Libfdt has been selected for the new uImage format implementation as (1) it
-provides needed functionality, (2) is actively maintained and developed and
-(3) increases code reuse as it is already part of the U-Boot source tree.
-
-b) Terminology
-
-This document defines new uImage structure by providing FDT bindings for new
-uImage internals. Bindings are defined from U-Boot perspective, i.e. describe
-final form of the uImage at the moment when it reaches U-Boot. User
-perspective may be simpler, as some of the properties (like timestamps and
-hashes) will need to be filled in automatically by the U-Boot mkimage tool.
-
-To avoid confusion with the kernel FDT the following naming convention is
-proposed for the new uImage format related terms:
-
-FIT	- Flattened uImage Tree
-
-FIT is formally a flattened device tree (in the libfdt meaning), which
-conforms to bindings defined in this document.
-
-.its	- image tree source
-.itb	- flattened image tree blob
-
-c) Image building procedure
-
-The following picture shows how the new uImage is prepared. Input consists of
-image source file (.its) and a set of data files. Image is created with the
-help of standard U-Boot mkimage tool which in turn uses dtc (device tree
-compiler) to produce image tree blob (.itb).  Resulting .itb file is the
-actual binary of a new uImage.
-
-
-tqm5200.its
-+
-vmlinux.bin.gz	   mkimage + dtc	       xfer to target
-eldk-4.2-ramdisk  --------------> tqm5200.itb --------------> bootm
-tqm5200.dtb			     /|\
-...				      |
-				 'new uImage'
-
-	- create .its file, automatically filled-in properties are omitted
-	- call mkimage tool on a .its file
-	- mkimage calls dtc to create .itb image and assures that
-	  missing properties are added
-	- .itb (new uImage) is uploaded onto the target and used therein
-
-
-d) Unique identifiers
-
-To identify FIT sub-nodes representing images, hashes, configurations (which
-are defined in the following sections), the "unit name" of the given sub-node
-is used as it's identifier as it assures uniqueness without additional
-checking required.
-
-
-3) Root node properties
------------------------
-
-Root node of the uImage Tree should have the following layout:
-
-/ o image-tree
-    |- description = "image description"
-    |- timestamp = <12399321>
-    |- #address-cells = <1>
-    |
-    o images
-    | |
-    | o image-1 {...}
-    | o image-2 {...}
-    | ...
-    |
-    o configurations
-      |- default = "conf-1"
-      |
-      o conf-1 {...}
-      o conf-2 {...}
-      ...
-
-
-  Optional property:
-  - description : Textual description of the uImage
-
-  Mandatory property:
-  - timestamp : Last image modification time being counted in seconds since
-    1970-01-01 00:00:00 - to be automatically calculated by mkimage tool.
-
-  Conditionally mandatory property:
-  - #address-cells : Number of 32bit cells required to represent entry and
-    load addresses supplied within sub-image nodes. May be omitted when no
-    entry or load addresses are used.
-
-  Mandatory nodes:
-  - images : This node contains a set of sub-nodes, each of them representing
-    single component sub-image (like kernel, ramdisk, etc.). At least one
-    sub-image is required.
-  - configurations : Contains a set of available configuration nodes and
-    defines a default configuration.
-
-
-4) '/images' node
------------------
-
-This node is a container node for component sub-image nodes. Each sub-node of
-the '/images' node should have the following layout:
-
- o image-1
-   |- description = "component sub-image description"
-   |- data = /incbin/("path/to/data/file.bin")
-   |- type = "sub-image type name"
-   |- arch = "ARCH name"
-   |- os = "OS name"
-   |- compression = "compression name"
-   |- load = <00000000>
-   |- entry = <00000000>
-   |
-   o hash-1 {...}
-   o hash-2 {...}
-   ...
-
-  Mandatory properties:
-  - description : Textual description of the component sub-image
-  - type : Name of component sub-image type, supported types are:
-    "standalone", "kernel", "kernel_noload", "ramdisk", "firmware", "script",
-    "filesystem", "flat_dt" and others (see uimage_type in common/image.c).
-  - data : Path to the external file which contains this node's binary data.
-  - compression : Compression used by included data. Supported compressions
-    are "gzip" and "bzip2". If no compression is used compression property
-    should be set to "none". If the data is compressed but it should not be
-    uncompressed by U-Boot (e.g. compressed ramdisk), this should also be set
-    to "none".
-
-  Conditionally mandatory property:
-  - os : OS name, mandatory for types "kernel". Valid OS names are:
-    "openbsd", "netbsd", "freebsd", "4_4bsd", "linux", "svr4", "esix",
-    "solaris", "irix", "sco", "dell", "ncr", "lynxos", "vxworks", "psos", "qnx",
-    "u-boot", "rtems", "unity", "integrity".
-  - arch : Architecture name, mandatory for types: "standalone", "kernel",
-    "firmware", "ramdisk" and "fdt". Valid architecture names are: "alpha",
-    "arm", "i386", "ia64", "mips", "mips64", "ppc", "s390", "sh", "sparc",
-    "sparc64", "m68k", "microblaze", "nios2", "blackfin", "avr32", "st200",
-    "sandbox".
-  - entry : entry point address, address size is determined by
-    '#address-cells' property of the root node.
-    Mandatory for types: "firmware", and "kernel".
-  - load : load address, address size is determined by '#address-cells'
-    property of the root node.
-    Mandatory for types: "firmware", and "kernel".
-  - compatible : compatible method for loading image.
-    Mandatory for types: "fpga", and images that do not specify a load address.
-    Supported compatible methods:
-    "u-boot,fpga-legacy" - the generic fpga loading routine.
-    "u-boot,zynqmp-fpga-ddrauth" - signed non-encrypted FPGA bitstream for
-    Xilinx Zynq UltraScale+ (ZymqMP) device.
-    "u-boot,zynqmp-fpga-enc" - encrypted FPGA bitstream for Xilinx Zynq
-    UltraScale+ (ZynqMP) device.
-  - phase : U-Boot phase for which the image is intended.
-    "spl" - image is an SPL image
-    "u-boot" - image is a U-Boot image
-
-  Optional nodes:
-  - hash-1 : Each hash sub-node represents separate hash or checksum
-    calculated for node's data according to specified algorithm.
-
-
-5) Hash nodes
--------------
-
-o hash-1
-  |- algo = "hash or checksum algorithm name"
-  |- value = [hash or checksum value]
-
-  Mandatory properties:
-  - algo : Algorithm name, supported are "crc32", "md5" and "sha1".
-  - value : Actual checksum or hash value, correspondingly 4, 16 or 20 bytes
-    long.
-
-
-6) '/configurations' node
--------------------------
-
-The 'configurations' node creates convenient, labeled boot configurations,
-which combine together kernel images with their ramdisks and fdt blobs.
-
-The 'configurations' node has has the following structure:
-
-o configurations
-  |- default = "default configuration sub-node unit name"
-  |
-  o config-1 {...}
-  o config-2 {...}
-  ...
-
-
-  Optional property:
-  - default : Selects one of the configuration sub-nodes as a default
-    configuration.
-
-  Mandatory nodes:
-  - configuration-sub-node-unit-name : At least one of the configuration
-    sub-nodes is required.
-
-
-7) Configuration nodes
-----------------------
-
-Each configuration has the following structure:
-
-o config-1
-  |- description = "configuration description"
-  |- kernel = "kernel sub-node unit name"
-  |- fdt = "fdt sub-node unit-name" [, "fdt overlay sub-node unit-name", ...]
-  |- loadables = "loadables sub-node unit-name"
-  |- script = "
-  |- compatible = "vendor,board-style device tree compatible string"
-
-
-  Mandatory properties:
-  - description : Textual configuration description.
-  - kernel or firmware: Unit name of the corresponding kernel or firmware
-    (u-boot, op-tee, etc) image. If both "kernel" and "firmware" are specified,
-    control is passed to the firmware image.
-
-  Optional properties:
-  - fdt : Unit name of the corresponding fdt blob (component image node of a
-    "fdt type"). Additional fdt overlay nodes can be supplied which signify
-    that the resulting device tree blob is generated by the first base fdt
-    blob with all subsequent overlays applied.
-  - fpga : Unit name of the corresponding fpga bitstream blob
-    (component image node of a "fpga type").
-  - loadables : Unit name containing a list of additional binaries to be
-    loaded at their given locations.  "loadables" is a comma-separated list
-    of strings. U-Boot will load each binary at its given start-address and
-    may optionally invoke additional post-processing steps on this binary based
-    on its component image node type.
-  - script : The image to use when loading a U-Boot script (for use with the
-    source command).
-  - compatible : The root compatible string of the U-Boot device tree that
-    this configuration shall automatically match when CONFIG_FIT_BEST_MATCH is
-    enabled. If this property is not provided, the compatible string will be
-    extracted from the fdt blob instead. This is only possible if the fdt is
-    not compressed, so images with compressed fdts that want to use compatible
-    string matching must always provide this property.
-
-The FDT blob is required to properly boot FDT based kernel, so the minimal
-configuration for 2.6 FDT kernel is (kernel, fdt) pair.
-
-Older, 2.4 kernel and 2.6 non-FDT kernel do not use FDT blob, in such cases
-'struct bd_info' must be passed instead of FDT blob, thus fdt property *must
-not* be specified in a configuration node.
-
-
-8) External data
-----------------
-
-The above format shows a 'data' property which holds the data for each image.
-It is also possible for this data to reside outside the FIT itself. This
-allows the FIT to be quite small, so that it can be loaded and scanned
-without loading a large amount of data. Then when an image is needed it can
-be loaded from an external source.
-
-In this case the 'data' property is omitted. Instead you can use:
-
-  - data-offset : offset of the data in a separate image store. The image
-    store is placed immediately after the last byte of the device tree binary,
-    aligned to a 4-byte boundary.
-  - data-size : size of the data in bytes
-
-The 'data-offset' property can be substituted with 'data-position', which
-defines an absolute position or address as the offset. This is helpful when
-booting U-Boot proper before performing relocation. Pass '-p [offset]' to
-mkimage to enable 'data-position'.
-
-Normal kernel FIT image has data embedded within FIT structure. U-Boot image
-for SPL boot has external data. Existence of 'data-offset' can be used to
-identify which format is used.
-
-For FIT image with external data, it would be better to align each blob of data
-to block(512 byte) for block device, so that we don't need to do the copy when
-read the image data in SPL. Pass '-B 0x200' to mkimage to align the FIT
-structure and data to 512 byte, other values available for other align size.
-
-9) Examples
------------
-
-Please see doc/uImage.FIT/*.its for actual image source files.
diff --git a/doc/uImage.FIT/uefi.its b/doc/uImage.FIT/uefi.its
deleted file mode 100644
index 378ca4ed8d..0000000000
--- a/doc/uImage.FIT/uefi.its
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Example FIT image description file demonstrating the usage of the
- * bootm command to launch UEFI binaries.
- *
- * Two boot configurations are available to enable booting GRUB2 on QEMU,
- * the former uses a FDT blob contained in the FIT image, while the later
- * relies on the FDT provided by the board emulator.
- */
-
-/dts-v1/;
-
-/ {
-	description = "GRUB2 EFI and QEMU FDT blob";
-	#address-cells = <1>;
-
-	images {
-		efi-grub {
-			description = "GRUB EFI Firmware";
-			data = /incbin/("bootarm.efi");
-			type = "kernel_noload";
-			arch = "arm";
-			os = "efi";
-			compression = "none";
-			load = <0x0>;
-			entry = <0x0>;
-			hash-1 {
-				algo = "sha256";
-			};
-		};
-
-		fdt-qemu {
-			description = "QEMU DTB";
-			data = /incbin/("qemu-arm.dtb");
-			type = "flat_dt";
-			arch = "arm";
-			compression = "none";
-			hash-1 {
-				algo = "sha256";
-			};
-		};
-	};
-
-	configurations {
-		default = "config-grub-fdt";
-
-		config-grub-fdt {
-			description = "GRUB EFI Boot w/ FDT";
-			kernel = "efi-grub";
-			fdt = "fdt-qemu";
-			signature-1 {
-				algo = "sha256,rsa2048";
-				key-name-hint = "dev";
-				sign-images = "kernel", "fdt";
-			};
-		};
-
-		config-grub-nofdt {
-			description = "GRUB EFI Boot w/o FDT";
-			kernel = "efi-grub";
-			signature-1 {
-				algo = "sha256,rsa2048";
-				key-name-hint = "dev";
-				sign-images = "kernel";
-			};
-		};
-	};
-};
diff --git a/doc/uImage.FIT/update3.its b/doc/uImage.FIT/update3.its
deleted file mode 100644
index 0659f20002..0000000000
--- a/doc/uImage.FIT/update3.its
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Example Automatic software update file.
- */
-
-/dts-v1/;
-
-/ {
-	description = "Automatic software updates: kernel, ramdisk, FDT";
-	#address-cells = <1>;
-
-	images {
-		update-1 {
-			description = "Linux kernel binary";
-			data = /incbin/("./vmlinux.bin.gz");
-			compression = "none";
-			type = "firmware";
-			load = <FF700000>;
-			hash-1 {
-				algo = "sha1";
-			};
-		};
-		update-2 {
-			description = "Ramdisk image";
-			data = /incbin/("./ramdisk_image.gz");
-			compression = "none";
-			type = "firmware";
-			load = <FF8E0000>;
-			hash-1 {
-				algo = "sha1";
-			};
-		};
-
-		update-3 {
-			description = "FDT blob";
-			data = /incbin/("./blob.fdt");
-			compression = "none";
-			type = "firmware";
-			load = <FFAC0000>;
-			hash-1 {
-				algo = "sha1";
-			};
-		};
-	};
-};
diff --git a/doc/uImage.FIT/update_uboot.its b/doc/uImage.FIT/update_uboot.its
deleted file mode 100644
index aec4826008..0000000000
--- a/doc/uImage.FIT/update_uboot.its
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Automatic software update for U-Boot
- * Make sure the flashing addresses ('load' prop) is correct for your board!
- */
-
-/dts-v1/;
-
-/ {
-	description = "Automatic U-Boot update";
-	#address-cells = <1>;
-
-	images {
-		update-1 {
-			description = "U-Boot binary";
-			data = /incbin/("./u-boot.bin");
-			compression = "none";
-			type = "firmware";
-			load = <0xFFFC0000>;
-			hash-1 {
-				algo = "sha1";
-			};
-		};
-	};
-};
diff --git a/doc/uImage.FIT/x86-fit-boot.txt b/doc/uImage.FIT/x86-fit-boot.txt
deleted file mode 100644
index 88d3460a83..0000000000
--- a/doc/uImage.FIT/x86-fit-boot.txt
+++ /dev/null
@@ -1,272 +0,0 @@
-Booting Linux on x86 with FIT
-=============================
-
-Background
-----------
-
-(corrections to the text below are welcome)
-
-Generally Linux x86 uses its own very complex booting method. There is a setup
-binary which contains all sorts of parameters and a compressed self-extracting
-binary for the kernel itself, often with a small built-in serial driver to
-display decompression progress.
-
-The x86 CPU has various processor modes. I am no expert on these, but my
-understanding is that an x86 CPU (even a really new one) starts up in a 16-bit
-'real' mode where only 1MB of memory is visible, moves to 32-bit 'protected'
-mode where 4GB is visible (or more with special memory access techniques) and
-then to 64-bit 'long' mode if 64-bit execution is required.
-
-Partly the self-extracting nature of Linux was introduced to cope with boot
-loaders that were barely capable of loading anything. Even changing to 32-bit
-mode was something of a challenge, so putting this logic in the kernel seemed
-to make sense.
-
-Bit by bit more and more logic has been added to this post-boot pre-Linux
-wrapper:
-
-- Changing to 32-bit mode
-- Decompression
-- Serial output (with drivers for various chips)
-- Load address randomisation
-- Elf loader complete with relocation (for the above)
-- Random number generator via 3 methods (again for the above)
-- Some sort of EFI mini-loader (1000+ glorious lines of code)
-- Locating and tacking on a device tree and ramdisk
-
-To my mind, if you sit back and look at things from first principles, this
-doesn't make a huge amount of sense. Any boot loader worth its salts already
-has most of the above features and more besides. The boot loader already knows
-the layout of memory, has a serial driver, can decompress things, includes an
-ELF loader and supports device tree and ramdisks. The decision to duplicate
-all these features in a Linux wrapper caters for the lowest common
-denominator: a boot loader which consists of a BIOS call to load something off
-disk, followed by a jmp instruction.
-
-(Aside: On ARM systems, we worry that the boot loader won't know where to load
-the kernel. It might be easier to just provide that information in the image,
-or in the boot loader rather than adding a self-relocator to put it in the
-right place. Or just use ELF?
-
-As a result, the x86 kernel boot process is needlessly complex. The file
-format is also complex, and obfuscates the contents to a degree that it is
-quite a challenge to extract anything from it. This bzImage format has become
-so prevalent that is actually isn't possible to produce the 'raw' kernel build
-outputs with the standard Makefile (as it is on ARM for example, at least at
-the time of writing).
-
-This document describes an alternative boot process which uses simple raw
-images which are loaded into the right place by the boot loader and then
-executed.
-
-
-Build the kernel
-----------------
-
-Note: these instructions assume a 32-bit kernel. U-Boot also supports directly
-booting a 64-bit kernel by jumping into 64-bit mode first (see below).
-
-You can build the kernel as normal with 'make'. This will create a file called
-'vmlinux'. This is a standard ELF file and you can look at it if you like:
-
-$ objdump -h vmlinux
-
-vmlinux:     file format elf32-i386
-
-Sections:
-Idx Name          Size      VMA       LMA       File off  Algn
-  0 .text         00416850  81000000  01000000  00001000  2**5
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
-  1 .notes        00000024  81416850  01416850  00417850  2**2
-                  CONTENTS, ALLOC, LOAD, READONLY, CODE
-  2 __ex_table    00000c50  81416880  01416880  00417880  2**3
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
-  3 .rodata       00154b9e  81418000  01418000  00419000  2**5
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
-  4 __bug_table   0000597c  8156cba0  0156cba0  0056dba0  2**0
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
-  5 .pci_fixup    00001b80  8157251c  0157251c  0057351c  2**2
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
-  6 .tracedata    00000024  8157409c  0157409c  0057509c  2**0
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
-  7 __ksymtab     00007ec0  815740c0  015740c0  005750c0  2**2
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
-  8 __ksymtab_gpl 00004a28  8157bf80  0157bf80  0057cf80  2**2
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
-  9 __ksymtab_strings 0001d6fc  815809a8  015809a8  005819a8  2**0
-                  CONTENTS, ALLOC, LOAD, READONLY, DATA
- 10 __init_rodata 00001c3c  8159e0a4  0159e0a4  0059f0a4  2**2
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
- 11 __param       00000ff0  8159fce0  0159fce0  005a0ce0  2**2
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
- 12 __modver      00000330  815a0cd0  015a0cd0  005a1cd0  2**2
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
- 13 .data         00063000  815a1000  015a1000  005a2000  2**12
-                  CONTENTS, ALLOC, LOAD, RELOC, DATA
- 14 .init.text    0002f104  81604000  01604000  00605000  2**2
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
- 15 .init.data    00040cdc  81634000  01634000  00635000  2**12
-                  CONTENTS, ALLOC, LOAD, RELOC, DATA
- 16 .x86_cpu_dev.init 0000001c  81674cdc  01674cdc  00675cdc  2**2
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
- 17 .altinstructions 0000267c  81674cf8  01674cf8  00675cf8  2**0
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
- 18 .altinstr_replacement 00000942  81677374  01677374  00678374  2**0
-                  CONTENTS, ALLOC, LOAD, READONLY, CODE
- 19 .iommu_table  00000014  81677cb8  01677cb8  00678cb8  2**2
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
- 20 .apicdrivers  00000004  81677cd0  01677cd0  00678cd0  2**2
-                  CONTENTS, ALLOC, LOAD, RELOC, DATA
- 21 .exit.text    00001a80  81677cd8  01677cd8  00678cd8  2**0
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
- 22 .data..percpu 00007880  8167a000  0167a000  0067b000  2**12
-                  CONTENTS, ALLOC, LOAD, RELOC, DATA
- 23 .smp_locks    00003000  81682000  01682000  00683000  2**2
-                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
- 24 .bss          000a1000  81685000  01685000  00686000  2**12
-                  ALLOC
- 25 .brk          00424000  81726000  01726000  00686000  2**0
-                  ALLOC
- 26 .comment      00000049  00000000  00000000  00686000  2**0
-                  CONTENTS, READONLY
- 27 .GCC.command.line 0003e055  00000000  00000000  00686049  2**0
-                  CONTENTS, READONLY
- 28 .debug_aranges 0000f4c8  00000000  00000000  006c40a0  2**3
-                  CONTENTS, RELOC, READONLY, DEBUGGING
- 29 .debug_info   0440b0df  00000000  00000000  006d3568  2**0
-                  CONTENTS, RELOC, READONLY, DEBUGGING
- 30 .debug_abbrev 0022a83b  00000000  00000000  04ade647  2**0
-                  CONTENTS, READONLY, DEBUGGING
- 31 .debug_line   004ead0d  00000000  00000000  04d08e82  2**0
-                  CONTENTS, RELOC, READONLY, DEBUGGING
- 32 .debug_frame  0010a960  00000000  00000000  051f3b90  2**2
-                  CONTENTS, RELOC, READONLY, DEBUGGING
- 33 .debug_str    001b442d  00000000  00000000  052fe4f0  2**0
-                  CONTENTS, READONLY, DEBUGGING
- 34 .debug_loc    007c7fa9  00000000  00000000  054b291d  2**0
-                  CONTENTS, RELOC, READONLY, DEBUGGING
- 35 .debug_ranges 00098828  00000000  00000000  05c7a8c8  2**3
-                  CONTENTS, RELOC, READONLY, DEBUGGING
-
-There is also the setup binary mentioned earlier. This is at
-arch/x86/boot/setup.bin and is about 12KB in size. It includes the command
-line and various settings need by the kernel. Arguably the boot loader should
-provide all of this also, but setting it up is some complex that the kernel
-helps by providing a head start.
-
-As you can see the code loads to address 0x01000000 and everything else
-follows after that. We could load this image using the 'bootelf' command but
-we would still need to provide the setup binary. This is not supported by
-U-Boot although I suppose you could mostly script it. This would permit the
-use of a relocatable kernel.
-
-All we need to boot is the vmlinux file and the setup.bin file.
-
-
-Create a FIT
-------------
-
-To create a FIT you will need a source file describing what should go in the
-FIT. See kernel.its for an example for x86 and also instructions on setting
-the 'arch' value for booting 64-bit kernels if desired. Put this into a file
-called image.its.
-
-Note that setup is loaded to the special address of 0x90000 (a special address
-you just have to know) and the kernel is loaded to 0x01000000 (the address you
-saw above). This means that you will need to load your FIT to a different
-address so that U-Boot doesn't overwrite it when decompressing. Something like
-0x02000000 will do so you can set CONFIG_SYS_LOAD_ADDR to that.
-
-In that example the kernel is compressed with lzo. Also we need to provide a
-flat binary, not an ELF. So the steps needed to set things are are:
-
-   # Create a flat binary
-   objcopy -O binary vmlinux vmlinux.bin
-
-   # Compress it into LZO format
-   lzop vmlinux.bin
-
-   # Build a FIT image
-   mkimage -f image.its image.fit
-
-(be careful to run the mkimage from your U-Boot tools directory since it
-will have x86_setup support.)
-
-You can take a look at the resulting fit file if you like:
-
-$ dumpimage -l image.fit
-FIT description: Simple image with single Linux kernel on x86
-Created:         Tue Oct  7 10:57:24 2014
- Image 0 (kernel)
-  Description:  Vanilla Linux kernel
-  Created:      Tue Oct  7 10:57:24 2014
-  Type:         Kernel Image
-  Compression:  lzo compressed
-  Data Size:    4591767 Bytes = 4484.15 kB = 4.38 MB
-  Architecture: Intel x86
-  OS:           Linux
-  Load Address: 0x01000000
-  Entry Point:  0x00000000
-  Hash algo:    sha1
-  Hash value:   446b5163ebfe0fb6ee20cbb7a8501b263cd92392
- Image 1 (setup)
-  Description:  Linux setup.bin
-  Created:      Tue Oct  7 10:57:24 2014
-  Type:         x86 setup.bin
-  Compression:  uncompressed
-  Data Size:    12912 Bytes = 12.61 kB = 0.01 MB
-  Hash algo:    sha1
-  Hash value:   a1f2099cf47ff9816236cd534c77af86e713faad
- Default Configuration: 'config-1'
- Configuration 0 (config-1)
-  Description:  Boot Linux kernel
-  Kernel:       kernel
-
-
-Booting the FIT
----------------
-
-To make it boot you need to load it and then use 'bootm' to boot it. A
-suitable script to do this from a network server is:
-
-   bootp
-   tftp image.fit
-   bootm
-
-This will load the image from the network and boot it. The command line (from
-the 'bootargs' environment variable) will be passed to the kernel.
-
-If you want a ramdisk you can add it as normal with FIT. If you want a device
-tree then x86 doesn't normally use those - it has ACPI instead.
-
-
-Why Bother?
------------
-
-1. It demystifies the process of booting an x86 kernel
-2. It allows use of the standard U-Boot boot file format
-3. It allows U-Boot to perform decompression - problems will provide an error
-message and you are still in the boot loader. It is possible to investigate.
-4. It avoids all the pre-loader code in the kernel which is quite complex to
-follow
-5. You can use verified/secure boot and other features which haven't yet been
-added to the pre-Linux
-6. It makes x86 more like other architectures in the way it boots a kernel.
-You can potentially use the same file format for the kernel, and the same
-procedure for building and packaging it.
-
-
-References
-----------
-
-In the Linux kernel, Documentation/x86/boot.txt defines the boot protocol for
-the kernel including the setup.bin format. This is handled in U-Boot in
-arch/x86/lib/zimage.c and arch/x86/lib/bootm.c.
-
-Various files in the same directory as this file describe the FIT format.
-
-
---
-Simon Glass
-sjg@chromium.org
-7-Oct-2014
diff --git a/doc/usage/blkmap.rst b/doc/usage/blkmap.rst
index dbfa8e5aad..7337ea507a 100644
--- a/doc/usage/blkmap.rst
+++ b/doc/usage/blkmap.rst
@@ -19,7 +19,7 @@ wherever they might be located.
 The implementation is loosely modeled on Linux's "Device Mapper"
 subsystem, see `kernel documentation`_ for more information.
 
-.. _kernel documentation: https://docs.kernel.org/admin-guide/device-mapper/index.html
+.. _kernel documentation: https://www.kernel.org/doc/html/latest/admin-guide/device-mapper/index.html
 
 
 Example: Netbooting an Ext4 Image
diff --git a/doc/usage/cmd/acpi.rst b/doc/usage/cmd/acpi.rst
index 14bafc8e35..6b9b8949f3 100644
--- a/doc/usage/cmd/acpi.rst
+++ b/doc/usage/cmd/acpi.rst
@@ -11,12 +11,14 @@ Synopis
     acpi list
     acpi items [-d]
     acpi dump <name>
+    acpi set <address>
 
 Description
 -----------
 
-The *acpi* command is used to dump the ACPI tables generated by U-Boot for passing
-to the operating systems.
+The *acpi* command is used to dump the ACPI tables generated by U-Boot for
+passing to the operating systems. It allows manually setting the address to take
+a look at existing ACPI tables.
 
 ACPI tables can be generated by various output functions and even devices can
 output material to include in the Differentiated System Description Table (DSDT)
@@ -231,5 +233,28 @@ Example
     00000000: 44 53 44 54 ea 32 00 00 02 eb 55 2d 42 4f 4f 54  DSDT.2....U-BOOT
     00000010: 55 2d 42 4f 4f 54 42 4c 25 07 11 20 49 4e 54 4c  U-BOOTBL%.. INTL
 
+This shows searching for tables in a known area of memory, then setting the
+pointer::
+
+    => acpi list
+    No ACPI tables present
+    => ms.s bff00000 80000 "RSD PTR"
+    bff75000: 52 53 44 20 50 54 52 20 cf 42 4f 43 48 53 20 00  RSD PTR .BOCHS .
+    1 match
+    => acpi set bff75000
+    Setting ACPI pointer to bff75000
+    => acpi list
+    Name      Base   Size  Detail
+    ----  --------  -----  ------
+    RSDP  bff75000      0  v00 BOCHS
+    RSDT  bff76a63     38  v01 BOCHS  BXPC     1 BXPC 1
+    FACP  bff768ff     74  v01 BOCHS  BXPC     1 BXPC 1
+    DSDT  bff75080   187f  v01 BOCHS  BXPC     1 BXPC 1
+    FACS  bff75040     40
+    APIC  bff76973     90  v01 BOCHS  BXPC     1 BXPC 1
+    HPET  bff76a03     38  v01 BOCHS  BXPC     1 BXPC 1
+    WAET  bff76a3b     28  v01 BOCHS  BXPC     1 BXPC 1
+    SSDT  bff95040     c5  v02 COREv4 COREBOOT 2a CORE 20221020
+
 
 .. _`ACPI specification`: https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf
diff --git a/doc/usage/cmd/armffa.rst b/doc/usage/cmd/armffa.rst
new file mode 100644
index 0000000000..13fa90c129
--- /dev/null
+++ b/doc/usage/cmd/armffa.rst
@@ -0,0 +1,94 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+
+armffa command
+==============
+
+Synopsis
+--------
+
+::
+
+   armffa [sub-command] [arguments]
+
+   sub-commands:
+
+        getpart [partition UUID]
+
+            lists the partition(s) info
+
+        ping [partition ID]
+
+            sends a data pattern to the specified partition
+
+        devlist
+
+            displays information about the FF-A device/driver
+
+Description
+-----------
+
+armffa is a command showcasing how to use the FF-A bus and how to invoke its operations.
+
+This provides a guidance to the client developers on how to call the FF-A bus interfaces.
+
+The command also allows to gather secure partitions information and ping these  partitions.
+
+The command is also helpful in testing the communication with secure partitions.
+
+Example
+-------
+
+The following examples are run on Corstone-1000 platform.
+
+* ping
+
+::
+
+   corstone1000# armffa ping 0x8003
+   SP response:
+   [LSB]
+   fffffffe
+   0
+   0
+   0
+   0
+
+* ping (failure case)
+
+::
+
+   corstone1000# armffa ping 0
+   Sending direct request error (-22)
+
+* getpart
+
+::
+
+   corstone1000# armffa getpart 33d532ed-e699-0942-c09c-a798d9cd722d
+   Partition: id = 8003 , exec_ctxt 1 , properties 3
+
+* getpart (failure case)
+
+::
+
+   corstone1000# armffa getpart 33d532ed-e699-0942-c09c-a798d9cd7221
+   INVALID_PARAMETERS: Unrecognized UUID
+   Failure in querying partitions count (error code: -22)
+
+* devlist
+
+::
+
+   corstone1000# armffa devlist
+   device name arm_ffa, dev 00000000fdf41c30, driver name arm_ffa, ops 00000000fffc0e98
+
+Configuration
+-------------
+
+The command is available if CONFIG_CMD_ARMFFA=y and CONFIG_ARM_FFA_TRANSPORT=y.
+
+Return value
+------------
+
+The return value $? is 0 (true) on success, 1 (false) on failure.
diff --git a/doc/usage/cmd/bind.rst b/doc/usage/cmd/bind.rst
new file mode 100644
index 0000000000..1a5cffcb72
--- /dev/null
+++ b/doc/usage/cmd/bind.rst
@@ -0,0 +1,103 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+bind command
+============
+
+Synopsis
+--------
+
+::
+
+    bind <node path> <driver>
+    bind <class> <index> <driver>
+
+Description
+-----------
+
+The bind command is used to bind a device to a driver. This makes the
+device available in U-Boot.
+
+While binding to a *node path* typically provides a working device
+binding by parent node and driver may lead to a device that is only
+partially initialized.
+
+node path
+    path of the device's device-tree node
+
+class
+    device class name
+
+index
+    index of the parent device in the device class
+
+driver
+    device driver name
+
+Example
+-------
+
+Given a system with a real time clock device with device path */pl031@9010000*
+and using driver rtc-pl031 unbinding and binding of the device is demonstrated
+using the two alternative bind syntaxes.
+
+.. code-block::
+
+    => dm tree
+     Class     Index  Probed  Driver                Name
+    -----------------------------------------------------------
+     root          0  [ + ]   root_driver           root_driver
+    ...
+     rtc           0  [   ]   rtc-pl031             |-- pl031@9010000
+    ...
+    => fdt addr $fdtcontroladdr
+    Working FDT set to 7ed7fdb0
+    => fdt print
+    / {
+            interrupt-parent = <0x00008003>;
+            model = "linux,dummy-virt";
+            #size-cells = <0x00000002>;
+            #address-cells = <0x00000002>;
+            compatible = "linux,dummy-virt";
+    ...
+            pl031@9010000 {
+                    clock-names = "apb_pclk";
+                    clocks = <0x00008000>;
+                    interrupts = <0x00000000 0x00000002 0x00000004>;
+                    reg = <0x00000000 0x09010000 0x00000000 0x00001000>;
+                    compatible = "arm,pl031", "arm,primecell";
+            };
+    ...
+    }
+    => unbind /pl031@9010000
+    => date
+    Cannot find RTC: err=-19
+    => dm tree
+     Class     Index  Probed  Driver                Name
+    -----------------------------------------------------------
+     root          0  [ + ]   root_driver           root_driver
+    ...
+    => bind /pl031@9010000 rtc-pl031
+    => dm tree
+     Class     Index  Probed  Driver                Name
+    -----------------------------------------------------------
+     root          0  [ + ]   root_driver           root_driver
+    ...
+     rtc           0  [   ]   rtc-pl031             |-- pl031@9010000
+    => date
+    Date: 2023-06-22 (Thursday)    Time: 15:14:51
+    => unbind rtc 0 rtc-pl031
+    => bind root 0 rtc-pl031
+    => date
+    Date: 1980-08-19 (Tuesday)    Time: 14:45:30
+
+Obviously the device is not initialized correctly by the last bind command.
+
+Configuration
+-------------
+
+The bind command is only available if CONFIG_CMD_BIND=y.
+
+Return code
+-----------
+
+The return code $? is 0 (true) on success and 1 (false) on failure.
diff --git a/doc/usage/cmd/bootflow.rst b/doc/usage/cmd/bootflow.rst
index 8590efca21..a8af1f8f60 100644
--- a/doc/usage/cmd/bootflow.rst
+++ b/doc/usage/cmd/bootflow.rst
@@ -13,7 +13,7 @@ Synopis
     bootflow select [<num|name>]
     bootflow info [-d]
     bootflow boot
-
+    bootflow cmdline [set|get|clear|delete|auto] <param> [<value>]
 
 Description
 -----------
@@ -198,6 +198,36 @@ bootflow boot
 This boots the current bootflow.
 
 
+bootflow cmdline
+~~~~~~~~~~~~~~~~
+
+Some bootmeths can obtain the OS command line since it is stored with the OS.
+In that case, you can use `bootflow cmdline` to adjust this. The command line
+is assumed to be in the format used by Linux, i.e. a space-separated set of
+parameters with optional values, e.g. "noinitrd console=/dev/tty0".
+
+To change or add a parameter, use::
+
+    bootflow cmdline set <param> <value>
+
+To clear a parameter value to empty you can use "" for the value, or use::
+
+    bootflow cmdline clear <param>
+
+To delete a parameter entirely, use::
+
+    bootflow cmdline delete <param>
+
+Automatic parameters are available in a very few cases. You can use these to
+add parmeters where the value is known by U-Boot. For example::
+
+    bootflow cmdline auto earlycon
+    bootflow cmdline auto console
+
+can be used to set the early console (or console) to a suitable value so that
+output appears on the serial port. This is only supported by the 16550 serial
+driver so far.
+
 Example
 -------
 
@@ -258,7 +288,6 @@ displayed and booted::
     Name:      mmc@7e202000.bootdev.part_2
     Device:    mmc@7e202000.bootdev
     Block dev: mmc@7e202000.blk
-    Sequence:  1
     Method:    distro
     State:     ready
     Partition: 2
@@ -266,6 +295,10 @@ displayed and booted::
     Filename:  extlinux/extlinux.conf
     Buffer:    3db7ae88
     Size:      232 (562 bytes)
+    OS:        Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
+    Cmdline:   (none)
+    Logo:      (none)
+    FDT:       <NULL>
     Error:     0
     U-Boot> bootflow boot
     ** Booting bootflow 'smsc95xx_eth.bootdev.0'
@@ -427,6 +460,69 @@ Here is am example using the -e flag to see all errors::
     (21 bootflows, 2 valid)
     U-Boot>
 
+Here is an example of booting ChromeOS, adjusting the console beforehand. Note that
+the cmdline is word-wrapped here and some parts of the command line are elided::
+
+    => bootfl list
+    Showing all bootflows
+    Seq  Method       State   Uclass    Part  Name                      Filename
+    ---  -----------  ------  --------  ----  ------------------------  ----------------
+    0  cros         ready   nvme         0  5.10.153-20434-g98da1eb2c <NULL>
+    1  efi          ready   nvme         c  nvme#0.blk#1.bootdev.part efi/boot/bootia32.efi
+    2  efi          ready   usb_mass_    2  usb_mass_storage.lun0.boo efi/boot/bootia32.efi
+    ---  -----------  ------  --------  ----  ------------------------  ----------------
+    (3 bootflows, 3 valid)
+    => bootfl sel 0
+    => bootfl inf
+    Name:      5.10.153-20434-g98da1eb2cf9d (chrome-bot@chromeos-release-builder-us-central1-b-x32-12-xijx) #1 SMP PREEMPT Tue Jan 24 19:38:23 PST 2023
+    Device:    nvme#0.blk#1.bootdev
+    Block dev: nvme#0.blk#1
+    Method:    cros
+    State:     ready
+    Partition: 0
+    Subdir:    (none)
+    Filename:  <NULL>
+    Buffer:    737a1400
+    Size:      c47000 (12873728 bytes)
+    OS:        ChromeOS
+    Cmdline:   console= loglevel=7 init=/sbin/init cros_secure drm.trace=0x106
+        root=/dev/dm-0 rootwait ro dm_verity.error_behavior=3
+        dm_verity.max_bios=-1 dm_verity.dev_wait=1
+        dm="1 vroot none ro 1,0 6348800
+          verity payload=PARTUUID=799c935b-ae62-d143-8493-816fa936eef7/PARTNROFF=1
+          hashtree=PARTUUID=799c935b-ae62-d143-8493-816fa936eef7/PARTNROFF=1
+          hashstart=6348800 alg=sha256
+          root_hexdigest=78cc462cd45aecbcd49ca476587b4dee59aa1b00ba5ece58e2c29ec9acd914ab
+          salt=8dec4dc80a75dd834a9b3175c674405e15b16a253fdfe05c79394ae5fd76f66a"
+        noinitrd vt.global_cursor_default=0
+        kern_guid=799c935b-ae62-d143-8493-816fa936eef7 add_efi_memmap boot=local
+        noresume noswap i915.modeset=1 ramoops.ecc=1 tpm_tis.force=0
+        intel_pmc_core.warn_on_s0ix_failures=1 i915.enable_guc=3 i915.enable_dc=4
+        xdomain=0 swiotlb=65536 intel_iommu=on i915.enable_psr=1
+        usb-storage.quirks=13fe:6500:u
+    X86 setup: 742e3400
+    Logo:      (none)
+    FDT:       <NULL>
+    Error:     0
+    => bootflow cmdline auto earlycon
+    => bootflow cmd auto console
+    => print bootargs
+    bootargs=console=ttyS0,115200n8 loglevel=7 ...
+        usb-storage.quirks=13fe:6500:u earlycon=uart8250,mmio32,0xfe03e000,115200n8
+    => bootflow cmd del console
+    => print bootargs
+    bootargs=loglevel=7 ... earlycon=uart8250,mmio32,0xfe03e000,115200n8
+    => bootfl boot
+    ** Booting bootflow '5.10.153-20434-g98da1eb2cf9d (chrome-bot@chromeos-release-builder-us-central1-b-x32-12-xijx) #1 SMP PREEMPT Tue Jan 24 19:38:23 PST 2023' with cros
+    Kernel command line: "loglevel=7 ... earlycon=uart8250,mmio32,0xfe03e000,115200n8"
+
+    Starting kernel ...
+
+    [    0.000000] Linux version 5.10.153-20434-g98da1eb2cf9d (chrome-bot@chromeos-release-builder-us-central1-b-x32-12-xijx) (Chromium OS 15.0_pre465103_p20220825-r4 clang version 15.0.0 (/var/tmp/portage/sys-devel/llvm-15.0_pre465103_p20220825-r4/work/llvm-15.0_pre465103_p20220825/clang db1978b67431ca3462ad8935bf662c15750b8252), LLD 15.0.0) #1 SMP PREEMPT Tue Jan 24 19:38:23 PST 2023
+    [    0.000000] Command line: loglevel=7 ... usb-storage.quirks=13fe:6500:u earlycon=uart8250,mmio32,0xfe03e000,115200n8
+    [    0.000000] x86/split lock detection: warning about user-space split_locks
+
+
 
 Return value
 ------------
diff --git a/doc/usage/cmd/bootm.rst b/doc/usage/cmd/bootm.rst
new file mode 100644
index 0000000000..a7e5f6ce69
--- /dev/null
+++ b/doc/usage/cmd/bootm.rst
@@ -0,0 +1,300 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+bootm command
+=============
+
+Synopsis
+--------
+
+::
+
+    bootm [fit_addr]#<conf>[#extra-conf]
+    bootm [[fit_addr]:<os_subimg>] [[<fit_addr2>]:<rd_subimg2>] [[<fit_addr3>]:<fdt_subimg>]
+
+    bootm <addr1> [[<addr2> [<addr3>]]    # Legacy boot
+
+Description
+-----------
+
+The *bootm* command is used to boot an Operating System. It has a large number
+of options depending on what needs to be booted.
+
+Note that the second form supports the first and/or second arguments to be
+omitted by using a hyphen '-' instead.
+
+fit_addr / fit_addr2 / fit_addr3
+    address of FIT to boot, defaults to CONFIG_SYS_LOAD_ADDR. See notes below.
+
+conf
+    configuration unit to boot (must be preceded by hash '#')
+
+extra-conf
+    extra configuration to boot. This is supported only for additional
+    devicetree overlays to apply on the base device tree supplied by the first
+    configuration unit.
+
+os_subimg
+    OS sub-image to boot (must be preceded by colon ':')
+
+rd_subimg
+    ramdisk sub-image to boot. Use a hyphen '-' if there is no ramdisk but an
+    FDT is needed.
+
+fdt_subimg
+    FDT sub-image to boot
+
+See below for legacy boot. Booting using :doc:`../fit/index` is recommended.
+
+Note on current image address
+-----------------------------
+
+When bootm is called without arguments, the image at current image address is
+booted. The current image address is the address set most recently by a load
+command, etc, and is by default equal to CONFIG_SYS_LOAD_ADDR. For example,
+consider the following commands::
+
+    tftp 200000 /tftpboot/kernel
+    bootm
+    # Last command is equivalent to:
+    # bootm 200000
+
+As shown above, with FIT the address portion of any argument
+can be omitted. If <addr3> is omitted, then it is assumed that image at
+<addr2> should be used. Similarly, when <addr2> is omitted, it is assumed that
+image at <addr1> should be used. If <addr1> is omitted, it is assumed that the
+current image address is to be used. For example, consider the following
+commands::
+
+    tftp 200000 /tftpboot/uImage
+    bootm :kernel-1
+    # Last command is equivalent to:
+    # bootm 200000:kernel-1
+
+    tftp 200000 /tftpboot/uImage
+    bootm 400000:kernel-1 :ramdisk-1
+    # Last command is equivalent to:
+    # bootm 400000:kernel-1 400000:ramdisk-1
+
+    tftp 200000 /tftpboot/uImage
+    bootm :kernel-1 400000:ramdisk-1 :fdt-1
+    # Last command is equivalent to:
+    # bootm 200000:kernel-1 400000:ramdisk-1 400000:fdt-1
+
+
+Legacy boot
+-----------
+
+U-Boot supports a legacy image format, enabled by `CONFIG_LEGACY_IMAGE_FORMAT`.
+This is not recommended as it is quite limited and insecure. Use
+:doc:`../fit/index` instead. It is documented here for old boards which still
+use it.
+
+Arguments are:
+
+addr1
+    address of legacy image to boot. If the image includes a second component
+    (ramdisk) it is used as well, unless the second parameter is hyphen '-'.
+
+addr2
+    address of legacy image to use as ramdisk
+
+addr3
+    address of legacy image to use as FDT
+
+
+Example syntax
+--------------
+
+This section provides various examples of possible usage::
+
+    1.  bootm       /* boot image at the current address, equivalent to 2,3,8 */
+
+This is equivalent to cases 2, 3 or 8, depending on the type of image at
+the current image address.
+
+Boot method: see cases 2,3,8
+
+Legacy uImage syntax
+~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    2.  bootm <addr1>            /* single image at <addr1> */
+
+Boot kernel image located at <addr1>.
+
+Boot method: non-FDT
+
+::
+
+    3.  bootm <addr1>            /* multi-image at <addr1>  */
+
+First and second components of the image at <addr1> are assumed to be a
+kernel and a ramdisk, respectively. The kernel is booted with initrd loaded
+with the ramdisk from the image.
+
+Boot method: depends on the number of components at <addr1>, and on whether
+U-Boot is compiled with OF support, which it should be.
+
+    ==================== ======================== ========================
+    Configuration        2 components             3 components
+                         (kernel, initrd)         (kernel, initrd, fdt)
+    ==================== ======================== ========================
+    #ifdef CONFIG_OF_*                   non-FDT                     FDT
+    #ifndef CONFIG_OF_*                  non-FDT                 non-FDT
+    ==================== ======================== ========================
+
+::
+
+    4.  bootm <addr1> -            /* multi-image at <addr1>  */
+
+Similar to case 3, but the kernel is booted without initrd.  Second
+component of the multi-image is irrelevant (it can be a dummy, 1-byte file).
+
+Boot method: see case 3
+
+::
+
+    5.  bootm <addr1> <addr2>        /* single image at <addr1> */
+
+Boot kernel image located at <addr1> with initrd loaded with ramdisk
+from the image at <addr2>.
+
+Boot method: non-FDT
+
+::
+
+    6.  bootm <addr1> <addr2> <addr3>   /* single image at <addr1> */
+
+<addr1> is the address of a kernel image, <addr2> is the address of a
+ramdisk image, and <addr3> is the address of a FDT binary blob.  Kernel is
+booted with initrd loaded with ramdisk from the image at <addr2>.
+
+Boot method: FDT
+
+::
+
+    7.  bootm <addr1> -      <addr3>   /* single image at <addr1> */
+
+<addr1> is the address of a kernel image and <addr3> is the address of
+a FDT binary blob. Kernel is booted without initrd.
+
+Boot method: FDT
+
+FIT syntax
+~~~~~~~~~~
+
+::
+
+    8.  bootm <addr1>
+
+Image at <addr1> is assumed to contain a default configuration, which
+is booted.
+
+Boot method: FDT or non-FDT, depending on whether the default configuration
+defines FDT
+
+::
+
+    9.  bootm [<addr1>]:<subimg1>
+
+Similar to case 2: boot kernel stored in <subimg1> from the image at
+address <addr1>.
+
+Boot method: non-FDT
+
+::
+
+    10. bootm [<addr1>]#<conf>[#<extra-conf[#...]]
+
+Boot configuration <conf> from the image at <addr1>.
+
+Boot method: FDT or non-FDT, depending on whether the configuration given
+defines FDT
+
+::
+
+    11. bootm [<addr1>]:<subimg1> [<addr2>]:<subimg2>
+
+Equivalent to case 5: boot kernel stored in <subimg1> from the image
+at <addr1> with initrd loaded with ramdisk <subimg2> from the image at
+<addr2>.
+
+Boot method: non-FDT
+
+::
+
+    12. bootm [<addr1>]:<subimg1> [<addr2>]:<subimg2> [<addr3>]:<subimg3>
+
+Equivalent to case 6: boot kernel stored in <subimg1> from the image
+at <addr1> with initrd loaded with ramdisk <subimg2> from the image at
+<addr2>, and pass FDT blob <subimg3> from the image at <addr3>.
+
+Boot method: FDT
+
+::
+
+    13. bootm [<addr1>]:<subimg1> [<addr2>]:<subimg2> <addr3>
+
+Similar to case 12, the difference being that <addr3> is the address
+of FDT binary blob that is to be passed to the kernel.
+
+Boot method: FDT
+
+::
+
+    14. bootm [<addr1>]:<subimg1> -              [<addr3>]:<subimg3>
+
+Equivalent to case 7: boot kernel stored in <subimg1> from the image
+at <addr1>, without initrd, and pass FDT blob <subimg3> from the image at
+<addr3>.
+
+Boot method: FDT
+
+    15. bootm [<addr1>]:<subimg1> -              <addr3>
+
+Similar to case 14, the difference being that <addr3> is the address
+of the FDT binary blob that is to be passed to the kernel.
+
+Boot method: FDT
+
+
+
+Example
+-------
+
+boot kernel "kernel-1" stored in a new uImage located at 200000::
+
+    bootm 200000:kernel-1
+
+boot configuration "cfg-1" from a new uImage located at 200000::
+
+    bootm 200000#cfg-1
+
+boot configuration "cfg-1" with extra "cfg-2" from a new uImage located
+at 200000::
+
+    bootm 200000#cfg-1#cfg-2
+
+boot "kernel-1" from a new uImage at 200000 with initrd "ramdisk-2" found in
+some other new uImage stored at address 800000::
+
+    bootm 200000:kernel-1 800000:ramdisk-2
+
+boot "kernel-2" from a new uImage at 200000, with initrd "ramdisk-1" and FDT
+"fdt-1", both stored in some other new uImage located at 800000::
+
+    bootm 200000:kernel-1 800000:ramdisk-1 800000:fdt-1
+
+boot kernel "kernel-2" with initrd "ramdisk-2", both stored in a new uImage
+at address 200000, with a raw FDT blob stored at address 600000::
+
+    bootm 200000:kernel-2 200000:ramdisk-2 600000
+
+boot kernel "kernel-2" from new uImage at 200000 with FDT "fdt-1" from the
+same new uImage::
+
+    bootm 200000:kernel-2 - 200000:fdt-1
+
+.. sectionauthor:: Bartlomiej Sieka <tur@semihalf.com>
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
diff --git a/doc/usage/cmd/cedit.rst b/doc/usage/cmd/cedit.rst
new file mode 100644
index 0000000000..8e1110c7c7
--- /dev/null
+++ b/doc/usage/cmd/cedit.rst
@@ -0,0 +1,31 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+cedit command
+=============
+
+Synopis
+-------
+
+::
+
+    cedit load <interface> <dev[:part]> <filename>
+    cedit run
+
+Description
+-----------
+
+The *cedit* command is used to load a configuration-editor description and allow
+the user to interact with it.
+
+It makes use of the expo subsystem.
+
+The description is in the form of a devicetree file, as documented at
+:ref:`expo_format`.
+
+Example
+-------
+
+::
+
+    => cedit load hostfs - fred.dtb
+    => cedit run
diff --git a/doc/usage/cmd/loadb.rst b/doc/usage/cmd/loadb.rst
index b37d1d7b59..0464b1f41c 100644
--- a/doc/usage/cmd/loadb.rst
+++ b/doc/usage/cmd/loadb.rst
@@ -13,7 +13,7 @@ Synopsis
 Description
 -----------
 
-The loady command is used to transfer a file to the device via the serial line
+The loadb command is used to transfer a file to the device via the serial line
 using the Kermit protocol.
 
 The number of transferred bytes is saved in environment variable filesize.
diff --git a/doc/usage/cmd/loads.rst b/doc/usage/cmd/loads.rst
new file mode 100644
index 0000000000..e4cb063df6
--- /dev/null
+++ b/doc/usage/cmd/loads.rst
@@ -0,0 +1,96 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+loads command
+=============
+
+Synopsis
+--------
+
+::
+
+    loads [offset [baud]]
+
+Description
+-----------
+
+The loads command is used to transfer a file to the device via the serial line
+using the Motorola S-record file format.
+
+offset
+    offset added to the addresses in the S-record file
+
+baud
+    baud rate to use for download. This parameter is only available if
+    CONFIG_SYS_LOADS_BAUD_CHANGE=y
+
+Example
+-------
+
+As example file to be transferred we use a script printing 'hello s-record'.
+Here are the commands to create the S-record file:
+
+.. code-block:: bash
+
+    $ echo 'echo hello s-record' > script.txt
+    $ mkimage -T script -d script.txt script.scr
+    Image Name:
+    Created:      Sun Jun 25 10:35:02 2023
+    Image Type:   PowerPC Linux Script (gzip compressed)
+    Data Size:    28 Bytes = 0.03 KiB = 0.00 MiB
+    Load Address: 00000000
+    Entry Point:  00000000
+    Contents:
+       Image 0: 20 Bytes = 0.02 KiB = 0.00 MiB
+    $ srec_cat script.scr -binary -CRLF -Output script.srec
+    $ echo -e "S9030000FC\r" >> script.srec
+    $ cat script.srec
+    S0220000687474703A2F2F737265636F72642E736F75726365666F7267652E6E65742F1D
+    S1230000270519566D773EB6649815E30000001700000000000000003DE3D97005070601E2
+    S12300200000000000000000000000000000000000000000000000000000000000000000BC
+    S11A00400000000F0000000068656C6C6F20732D7265636F72640A39
+    S5030003F9
+    S9030000FC
+    $
+
+The load address in the first S1 record is 0x0000.
+
+The terminal emulation program picocom is invoked with *cat* as the send
+command to transfer the file.
+
+.. code-block::
+
+    picocom --send-cmd 'cat' --baud 115200 /dev/ttyUSB0
+
+After entering the *loads* command the key sequence <CTRL-A><CTRL-S> is used to
+let picocom prompt for the file name. Picocom invokes the program *cat* for the
+file transfer. The loaded script is executed using the *source* command.
+
+.. code-block::
+
+    => loads $scriptaddr
+    ## Ready for S-Record download ...
+
+    *** file: script.srec
+    $ cat script.srec
+
+    *** exit status: 0 ***
+
+    ## First Load Addr = 0x4FC00000
+    ## Last  Load Addr = 0x4FC0005B
+    ## Total Size      = 0x0000005C = 92 Bytes
+    ## Start Addr      = 0x00000000
+    => source $scriptaddr
+    ## Executing script at 4fc00000
+    hello s-record
+    =>
+
+Configuration
+-------------
+
+The command is only available if CONFIG_CMD_LOADS=y. The parameter to set the
+baud rate is only available if CONFIG_SYS_LOADS_BAUD_CHANGE=y
+
+Return value
+------------
+
+The return value $? is 0 (true) on success, 1 (false) otherwise.
diff --git a/doc/usage/cmd/mtrr.rst b/doc/usage/cmd/mtrr.rst
new file mode 100644
index 0000000000..531153bb3e
--- /dev/null
+++ b/doc/usage/cmd/mtrr.rst
@@ -0,0 +1,151 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+mtrr command
+============
+
+Synopis
+-------
+
+    mtrr [list]
+    mtrr set <reg> <type> <start> <size>
+    mtrr disable <reg>
+    mtrr enable
+
+
+Description
+-----------
+
+The *mtrr* command is used to dump the Memory Type Range Registers (MTRRs) on
+an x86 machine. These register control cache behaviour in selected memory
+ranges.
+
+Note that the number of registers can vary between CPUs.
+
+
+mtrr [list]
+~~~~~~~~~~~
+
+List the MTRRs. The table shows the following information:
+
+Reg
+    Register number (the first is register 0)
+
+Valid
+    Shows Y if the register is valid (has bit 11 set), N if not
+
+Write-type
+    Shows the behaviour when writing to the memory region. The types are
+    abbreviated to fit a reasonable line length. Valid types shown below.
+
+    ======  ==============  ====================================================
+    Value   Type            Meaning
+    ======  ==============  ====================================================
+    0       Uncacheable     Skip cache and write directly to memory
+    1       Combine         Multiple writes can be combined into one transaction
+    4       Through         Update cache and also write to memory
+    5       Protect         Writes are prohibited
+    6       Back            Update cache but don't write to memory
+    ======  ==============  ====================================================
+
+Base
+    Base memory address from which the register controls behaviour
+
+Mask
+    Mask value, which also indicates the size
+
+Size
+    Length of memory region within which the register controls behaviour
+
+
+mtrr set
+~~~~~~~~
+
+This sets the value of a particular MTRR. Parameters are:
+
+reg
+    Register number to set, with 0 being the first
+
+type
+    Access type to set. See Write-type above for valid types. This uses the name
+    rather than its numeric value.
+
+start
+    Base memory address from which the register should control behaviour
+
+size
+    Length of memory region within which the register controls behaviour
+
+
+mtrr disable
+~~~~~~~~~~~~
+
+This disables a particular register, by clearing its `valid` bit (11).
+
+
+mtrr enable
+~~~~~~~~~~~
+
+This enables a particular register, by setting its `valid` bit (11).
+
+
+Example
+-------
+
+This shows disabling and enabling an MTRR, as well as setting its type::
+
+    => mtrr
+    CPU 0:
+    Reg Valid Write-type   Base   ||        Mask   ||        Size   ||
+    0   Y     Back         0000000000000000 0000000f80000000 0000000080000000
+    1   Y     Back         0000000080000000 0000000fe0000000 0000000020000000
+    2   Y     Back         00000000a0000000 0000000ff0000000 0000000010000000
+    3   Y     Uncacheable  00000000ad000000 0000000fff000000 0000000001000000
+    4   Y     Uncacheable  00000000ae000000 0000000ffe000000 0000000002000000
+    5   Y     Combine      00000000d0000000 0000000ff0000000 0000000010000000
+    6   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    7   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    8   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    9   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    => mtrr d 5
+    => mtrr
+    CPU 0:
+    Reg Valid Write-type   Base   ||        Mask   ||        Size   ||
+    0   Y     Back         0000000000000000 0000000f80000000 0000000080000000
+    1   Y     Back         0000000080000000 0000000fe0000000 0000000020000000
+    2   Y     Back         00000000a0000000 0000000ff0000000 0000000010000000
+    3   Y     Uncacheable  00000000ad000000 0000000fff000000 0000000001000000
+    4   Y     Uncacheable  00000000ae000000 0000000ffe000000 0000000002000000
+    5   N     Combine      00000000d0000000 0000000ff0000000 0000000010000000
+    6   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    7   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    8   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    9   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    => mtrr e 5
+    => mtrr
+    CPU 0:
+    Reg Valid Write-type   Base   ||        Mask   ||        Size   ||
+    0   Y     Back         0000000000000000 0000000f80000000 0000000080000000
+    1   Y     Back         0000000080000000 0000000fe0000000 0000000020000000
+    2   Y     Back         00000000a0000000 0000000ff0000000 0000000010000000
+    3   Y     Uncacheable  00000000ad000000 0000000fff000000 0000000001000000
+    4   Y     Uncacheable  00000000ae000000 0000000ffe000000 0000000002000000
+    5   Y     Combine      00000000d0000000 0000000ff0000000 0000000010000000
+    6   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    7   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    8   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    9   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    => mtrr set 5 Uncacheable d0000000 10000000
+    => mtrr
+    CPU 0:
+    Reg Valid Write-type   Base   ||        Mask   ||        Size   ||
+    0   Y     Back         0000000000000000 0000000f80000000 0000000080000000
+    1   Y     Back         0000000080000000 0000000fe0000000 0000000020000000
+    2   Y     Back         00000000a0000000 0000000ff0000000 0000000010000000
+    3   Y     Uncacheable  00000000ad000000 0000000fff000000 0000000001000000
+    4   Y     Uncacheable  00000000ae000000 0000000ffe000000 0000000002000000
+    5   Y     Uncacheable  00000000d0000000 0000000ff0000000 0000000010000000
+    6   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    7   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    8   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    9   N     Uncacheable  0000000000000000 0000000000000000 0000001000000000
+    =>
diff --git a/doc/usage/cmd/part.rst b/doc/usage/cmd/part.rst
index 8d2a280391..8a594aaff2 100644
--- a/doc/usage/cmd/part.rst
+++ b/doc/usage/cmd/part.rst
@@ -13,6 +13,7 @@ Synopis
     part start <interface> <dev> <part> <varname>
     part size <interface> <dev> <part> <varname>
     part number <interface> <dev> <part> <varname>
+    part set <interface> <dev> <part> <type>
     part type <interface> <dev>:<part> [varname]
     part types
 
@@ -82,6 +83,18 @@ part must be specified as partition name.
     varname
         a variable to store the current partition number value into
 
+The 'part set' command sets the type of a partition. This is useful when
+autodetection fails or does not do the correct thing:
+
+    interface
+        interface for accessing the block device (mmc, sata, scsi, usb, ....)
+    dev
+        device number
+    part
+        partition number
+    type
+        partition type to use (see 'part types') to check available types
+
 The 'part type' command prints or sets an environment variable to the partition type UUID.
 
     interface
@@ -147,6 +160,67 @@ Examples
     => part types
     Supported partition tables: EFI, AMIGA, DOS, ISO, MAC
 
+This shows looking at a device with multiple partition tables::
+
+    => virtio scan
+    => part list virtio 0
+
+    Partition Map for VirtIO device 0  --   Partition Type: EFI
+
+    Part	Start LBA	End LBA		Name
+            Attributes
+            Type GUID
+            Partition GUID
+    1	0x00000040	0x0092b093	"ISO9660"
+            attrs:	0x1000000000000001
+            type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
+            guid:	a0891d7e-b930-4513-94d8-f629dbd637b2
+    2	0x0092b094	0x0092d7e7	"Appended2"
+            attrs:	0x0000000000000000
+            type:	c12a7328-f81f-11d2-ba4b-00a0c93ec93b
+            guid:	a0891d7e-b930-4513-94db-f629dbd637b2
+    3	0x0092d7e8	0x0092da3f	"Gap1"
+            attrs:	0x1000000000000001
+            type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
+            guid:	a0891d7e-b930-4513-94da-f629dbd637b2
+    => ls virtio 0:3
+    => part types
+    Supported partition tables: EFI, DOS, ISO
+    => part set virtio 0 dos
+
+    Partition Map for VirtIO device 0  --   Partition Type: DOS
+
+    Part	Start Sector	Num Sectors	UUID		Type
+    1	1         	9624191   	00000000-01	ee
+    => part set virtio 0 iso
+
+    Partition Map for VirtIO device 0  --   Partition Type: ISO
+
+    Part   Start     Sect x Size Type
+    1     3020        4    512 U-Boot
+    2  9613460    10068    512 U-Boot
+    => part set virtio 0 efi
+
+    Partition Map for VirtIO device 0  --   Partition Type: EFI
+
+    Part	Start LBA	End LBA		Name
+            Attributes
+            Type GUID
+            Partition GUID
+    1	0x00000040	0x0092b093	"ISO9660"
+            attrs:	0x1000000000000001
+            type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
+            guid:	a0891d7e-b930-4513-94d8-f629dbd637b2
+    2	0x0092b094	0x0092d7e7	"Appended2"
+            attrs:	0x0000000000000000
+            type:	c12a7328-f81f-11d2-ba4b-00a0c93ec93b
+            guid:	a0891d7e-b930-4513-94db-f629dbd637b2
+    3	0x0092d7e8	0x0092da3f	"Gap1"
+            attrs:	0x1000000000000001
+            type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
+            guid:	a0891d7e-b930-4513-94da-f629dbd637b2
+    =>
+
 Return value
 ------------
 
diff --git a/doc/usage/cmd/qfw.rst b/doc/usage/cmd/qfw.rst
index cc0e27c277..ec13e0967a 100644
--- a/doc/usage/cmd/qfw.rst
+++ b/doc/usage/cmd/qfw.rst
@@ -41,18 +41,21 @@ QEMU firmware files are listed via the *qfw list* command:
 ::
 
     => qfw list
-    etc/boot-fail-wait
-    etc/smbios/smbios-tables
-    etc/smbios/smbios-anchor
-    etc/e820
-    genroms/kvmvapic.bin
-    genroms/linuxboot.bin
-    etc/system-states
-    etc/acpi/tables
-    etc/table-loader
-    etc/tpm/log
-    etc/acpi/rsdp
-    bootorder
+    00000000 bios-geometry
+    00000000 bootorder
+    000f0060 etc/acpi/rsdp
+    bed14040 etc/acpi/tables
+    00000000 etc/boot-fail-wait
+    00000000 etc/e820
+    00000000 etc/smbios/smbios-anchor
+    00000000 etc/smbios/smbios-tables
+    00000000 etc/system-states
+    00000000 etc/table-loader
+    00000000 etc/tpm/log
+    00000000 genroms/kvmvapic.bin
+
+Where an address is shown, it indicates where the data is available for
+inspection, e.g. using the :doc:`md`.
 
 The available CPUs can be shown via the *qfw cpus* command:
 
diff --git a/doc/usage/cmd/saves.rst b/doc/usage/cmd/saves.rst
new file mode 100644
index 0000000000..5823f88379
--- /dev/null
+++ b/doc/usage/cmd/saves.rst
@@ -0,0 +1,88 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+saves command
+=============
+
+Synopsis
+--------
+
+::
+
+    saves [offset [size [baud]]]
+
+Description
+-----------
+
+The *saves* command is used to transfer a file from the device via the serial
+line using the Motorola S-record file format.
+
+offset
+    start address of memory area to save, defaults to 0x0
+
+size
+    size of memory area to save, defaults to 0x0
+
+baud
+    baud rate to use for upload. This parameter is only available if
+    CONFIG_SYS_LOADS_BAUD_CHANGE=y
+
+Example
+-------
+
+In the example the *screen* command is used to connect to the U-Boot serial
+console.
+
+In a first screen session a file is loaded from the SD-card and the *saves*
+command is invoked. <CTRL+A><k> is used to kill the screen session.
+
+A new screen session is started which logs the output to a file and the
+<ENTER> key is hit to start the file output. <CTRL+A><k> is issued to kill the
+screen session.
+
+The log file is converted to a binary file using the *srec_cat* command.
+A negative offset of -1337982976 (= -0x4c000000) is applied to compensate for
+the offset used in the *saves* command.
+
+.. code-block::
+
+    $ screen /dev/ttyUSB0 115200
+    => echo $scriptaddr
+    0x4FC00000
+    => load mmc 0:1 $scriptaddr boot.txt
+    124 bytes read in 1 ms (121.1 KiB/s)
+    => saves $scriptaddr $filesize
+    ## Ready for S-Record upload, press ENTER to proceed ...
+    Really kill this window [y/n]
+    $ screen -Logfile out.srec -L /dev/ttyUSB0 115200
+    S0030000FC
+    S3154FC00000736574656E76206175746F6C6F616420AD
+    S3154FC000106E6F0A646863700A6C6F6164206D6D633E
+    S3154FC0002020303A3120246664745F616464725F72B3
+    S3154FC00030206474620A6C6F6164206D6D6320303AC0
+    S3154FC000403120246B65726E656C5F616464725F72DA
+    S3154FC0005020736E702E6566690A626F6F74656669C6
+    S3154FC0006020246B65726E656C5F616464725F7220CB
+    S3114FC00070246664745F616464725F720A38
+    S70500000000FA
+    ## S-Record upload complete
+    =>
+    Really kill this window [y/n]
+    $ srec_cat out.srec -offset -1337982976 -Output out.txt -binary 2>/dev/null
+    $ cat out.txt
+    setenv autoload no
+    dhcp
+    load mmc 0:1 $fdt_addr_r dtb
+    load mmc 0:1 $kernel_addr_r snp.efi
+    bootefi $kernel_addr_r $fdt_addr_r
+    $
+
+Configuration
+-------------
+
+The command is only available if CONFIG_CMD_SAVES=y. The parameter to set the
+baud rate is only available if CONFIG_SYS_LOADS_BAUD_CHANGE=y
+
+Return value
+------------
+
+The return value $? is 0 (true) on success, 1 (false) otherwise.
diff --git a/doc/usage/cmd/source.rst b/doc/usage/cmd/source.rst
index 61a4505909..697f644745 100644
--- a/doc/usage/cmd/source.rst
+++ b/doc/usage/cmd/source.rst
@@ -22,7 +22,7 @@ Two formats for script files exist:
 * Flat Image Tree (FIT)
 
 The benefit of the FIT images is that they can be signed and verifed as
-decribed in :download:`signature.txt <../../uImage.FIT/signature.txt>`.
+described in :doc:`../fit/signature`.
 
 Both formats can be created with the mkimage tool.
 
@@ -161,7 +161,7 @@ The boot scripts (boot.scr) is created with:
 
     mkimage -T script -n 'Test script' -d boot.txt boot.scr
 
-The script can be execute in U-boot like this:
+The script can be execute in U-Boot like this:
 
 .. code-block::
 
diff --git a/doc/usage/cmd/unbind.rst b/doc/usage/cmd/unbind.rst
new file mode 100644
index 0000000000..594e4f0689
--- /dev/null
+++ b/doc/usage/cmd/unbind.rst
@@ -0,0 +1,95 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+unbind command
+==============
+
+Synopsis
+--------
+
+::
+
+    unbind <node path>
+    unbind <class> <index>
+    unbind <class> <index> <driver>
+
+Description
+-----------
+
+The unbind command is used to unbind a device from a driver. This makes the
+device unavailable in U-Boot.
+
+node path
+    path of the device's device-tree node
+
+class
+    device class name
+
+index
+    index of the device in the device class
+
+driver
+    device driver name
+
+Example
+-------
+
+Given a system with a real time clock device with device path */pl031@9010000*
+and using driver rtc-pl031 unbinding and binding of the device is demonstrated
+using the three alternative unbind syntaxes.
+
+.. code-block::
+
+    => dm tree
+     Class     Index  Probed  Driver                Name
+    -----------------------------------------------------------
+     root          0  [ + ]   root_driver           root_driver
+    ...
+     rtc           0  [   ]   rtc-pl031             |-- pl031@9010000
+    ...
+    => fdt addr $fdtcontroladdr
+    Working FDT set to 7ed7fdb0
+    => fdt print
+    / {
+            interrupt-parent = <0x00008003>;
+            model = "linux,dummy-virt";
+            #size-cells = <0x00000002>;
+            #address-cells = <0x00000002>;
+            compatible = "linux,dummy-virt";
+    ...
+            pl031@9010000 {
+                    clock-names = "apb_pclk";
+                    clocks = <0x00008000>;
+                    interrupts = <0x00000000 0x00000002 0x00000004>;
+                    reg = <0x00000000 0x09010000 0x00000000 0x00001000>;
+                    compatible = "arm,pl031", "arm,primecell";
+            };
+    ...
+    }
+    => unbind /pl031@9010000
+    => dm tree
+     Class     Index  Probed  Driver                Name
+    -----------------------------------------------------------
+     root          0  [ + ]   root_driver           root_driver
+    ...
+    => unbind /pl031@9010000
+    Cannot find a device with path /pl031@9010000
+    => bind /pl031@9010000 rtc-pl031
+    => dm tree
+     Class     Index  Probed  Driver                Name
+    -----------------------------------------------------------
+     root          0  [ + ]   root_driver           root_driver
+    ...
+     rtc           0  [   ]   rtc-pl031             |-- pl031@9010000
+    => unbind rtc 0
+    => bind /pl031@9010000 rtc-pl031
+    => unbind rtc 0 rtc-pl031
+
+Configuration
+-------------
+
+The unbind command is only available if CONFIG_CMD_BIND=y.
+
+Return code
+-----------
+
+The return code $? is 0 (true) on success and 1 (false) on failure.
diff --git a/doc/usage/dfu.rst b/doc/usage/dfu.rst
index ed47ff561e..68cacbbef6 100644
--- a/doc/usage/dfu.rst
+++ b/doc/usage/dfu.rst
@@ -9,7 +9,7 @@ Overview
 The Device Firmware Upgrade (DFU) allows to download and upload firmware
 to/from U-Boot connected over USB.
 
-U-boot follows the Universal Serial Bus Device Class Specification for
+U-Boot follows the Universal Serial Bus Device Class Specification for
 Device Firmware Upgrade Version 1.1 the USB forum (DFU v1.1 in www.usb.org).
 
 U-Boot implements this DFU capability (CONFIG_DFU) with the command dfu
diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst
index 2c44e5da6a..c6439dde66 100644
--- a/doc/usage/environment.rst
+++ b/doc/usage/environment.rst
@@ -81,6 +81,12 @@ Example::
         echo CONFIG_SYS_BOARD boot failed - please check your image
         echo Load address is CONFIG_SYS_LOAD_ADDR
 
+Settings which are common to a group of boards can use #include to bring in
+a common file in the `include/env` directory, containing environment
+settings. For example::
+
+   #include <env/ti/mmc.env>
+
 If CONFIG_ENV_SOURCE_FILE is empty and the default filename is not present, then
 the old-style C environment is used instead. See below.
 
@@ -94,7 +100,7 @@ to add environment variables.
 
 Board maintainers are encouraged to migrate to the text-based environment as it
 is easier to maintain. The distro-board script still requires the old-style
-environment but work is underway to address this.
+environments, so use :doc:`../develop/bootstd` instead.
 
 
 List of environment variables
diff --git a/doc/usage/fit/beaglebone_vboot.rst b/doc/usage/fit/beaglebone_vboot.rst
new file mode 100644
index 0000000000..0580ee10bd
--- /dev/null
+++ b/doc/usage/fit/beaglebone_vboot.rst
@@ -0,0 +1,612 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Verified Boot on the Beaglebone Black
+=====================================
+
+Introduction
+------------
+
+Before reading this, please read :doc:`verified-boot` and :doc:`signature`.
+These instructions are for mainline U-Boot from v2014.07 onwards.
+
+There is quite a bit of documentation in this directory describing how
+verified boot works in U-Boot. There is also a test which runs through the
+entire process of signing an image and running U-Boot (sandbox) to check it.
+However, it might be useful to also have an example on a real board.
+
+Beaglebone Black is a fairly common board so seems to be a reasonable choice
+for an example of how to enable verified boot using U-Boot.
+
+First a note that may to help avoid confusion. U-Boot and Linux both use
+device tree. They may use the same device tree source, but it is seldom useful
+for them to use the exact same binary from the same place. More typically,
+U-Boot has its device tree packaged with it, and the kernel's device tree is
+packaged with the kernel. In particular this is important with verified boot,
+since U-Boot's device tree must be immutable. If it can be changed then the
+public keys can be changed and verified boot is useless. An attacker can
+simply generate a new key and put his public key into U-Boot so that
+everything verifies. On the other hand the kernel's device tree typically
+changes when the kernel changes, so it is useful to package an updated device
+tree with the kernel binary. U-Boot supports the latter with its flexible FIT
+format (Flat Image Tree).
+
+
+Overview
+--------
+
+The steps are roughly as follows:
+
+#. Build U-Boot for the board, with the verified boot options enabled.
+
+#. Obtain a suitable Linux kernel
+
+#. Create a Image Tree Source file (ITS) file describing how you want the
+   kernel to be packaged, compressed and signed.
+
+#. Create a key pair
+
+#. Sign the kernel
+
+#. Put the public key into U-Boot's image
+
+#. Put U-Boot and the kernel onto the board
+
+#. Try it
+
+
+Step 1: Build U-Boot
+--------------------
+
+a. Set up the environment variable to point to your toolchain. You will need
+   this for U-Boot and also for the kernel if you build it. For example if you
+   installed a Linaro version manually it might be something like::
+
+       export CROSS_COMPILE=/opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.08_linux/bin/arm-linux-gnueabihf-
+
+   or if you just installed gcc-arm-linux-gnueabi then it might be::
+
+       export CROSS_COMPILE=arm-linux-gnueabi-
+
+b. Configure and build U-Boot with verified boot enabled::
+
+    export UBOOT=/path/to/u-boot
+    cd $UBOOT
+    # You can add -j10 if you have 10 CPUs to make it faster
+    make O=b/am335x_boneblack_vboot am335x_boneblack_vboot_config all
+    export UOUT=$UBOOT/b/am335x_boneblack_vboot
+
+c. You will now have a U-Boot image::
+
+    file b/am335x_boneblack_vboot/u-boot-dtb.img
+    b/am335x_boneblack_vboot/u-boot-dtb.img: u-boot legacy uImage,
+      U-Boot 2014.07-rc2-00065-g2f69f8, Firmware/ARM, Firmware Image
+      (Not compressed), 395375 bytes, Sat May 31 16:19:04 2014,
+      Load Address: 0x80800000, Entry Point: 0x00000000,
+      Header CRC: 0x0ABD6ACA, Data CRC: 0x36DEF7E4
+
+
+Step 2: Build Linux
+--------------------
+
+a. Find the kernel image ('Image') and device tree (.dtb) file you plan to
+   use. In our case it is am335x-boneblack.dtb and it is built with the kernel.
+   At the time of writing an SD Boot image can be obtained from here::
+
+       http://www.elinux.org/Beagleboard:Updating_The_Software#Image_For_Booting_From_microSD
+
+   You can write this to an SD card and then mount it to extract the kernel and
+   device tree files.
+
+   You can also build a kernel. Instructions for this are are here::
+
+       http://elinux.org/Building_BBB_Kernel
+
+   or you can use your favourite search engine. Following these instructions
+   produces a kernel Image and device tree files. For the record the steps
+   were::
+
+        export KERNEL=/path/to/kernel
+        cd $KERNEL
+        git clone git://github.com/beagleboard/kernel.git .
+        git checkout v3.14
+        ./patch.sh
+        cp configs/beaglebone kernel/arch/arm/configs/beaglebone_defconfig
+        cd kernel
+        make beaglebone_defconfig
+        make uImage dtbs   # -j10 if you have 10 CPUs
+        export OKERNEL=$KERNEL/kernel/arch/arm/boot
+
+b. You now have the 'Image' and 'am335x-boneblack.dtb' files needed to boot.
+
+
+Step 3: Create the ITS
+----------------------
+
+Set up a directory for your work::
+
+   export WORK=/path/to/dir
+   cd $WORK
+
+Put this into a file in that directory called sign.its::
+
+    /dts-v1/;
+
+    / {
+        description = "Beaglebone black";
+        #address-cells = <1>;
+
+        images {
+            kernel {
+                data = /incbin/("Image.lzo");
+                type = "kernel";
+                arch = "arm";
+                os = "linux";
+                compression = "lzo";
+                load = <0x80008000>;
+                entry = <0x80008000>;
+                hash-1 {
+                    algo = "sha1";
+                };
+            };
+            fdt-1 {
+                description = "beaglebone-black";
+                data = /incbin/("am335x-boneblack.dtb");
+                type = "flat_dt";
+                arch = "arm";
+                compression = "none";
+                hash-1 {
+                    algo = "sha1";
+                };
+            };
+        };
+        configurations {
+            default = "conf-1";
+            conf-1 {
+                kernel = "kernel";
+                fdt = "fdt-1";
+                signature-1 {
+                    algo = "sha1,rsa2048";
+                    key-name-hint = "dev";
+                    sign-images = "fdt", "kernel";
+                };
+            };
+        };
+    };
+
+
+The explanation for this is all in the documentation you have already read.
+But briefly it packages a kernel and device tree, and provides a single
+configuration to be signed with a key named 'dev'. The kernel is compressed
+with LZO to make it smaller.
+
+
+Step 4: Create a key pair
+-------------------------
+
+See :doc:`signature` for details on this step::
+
+   cd $WORK
+   mkdir keys
+   openssl genrsa -F4 -out keys/dev.key 2048
+   openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt
+
+Note: keys/dev.key contains your private key and is very secret. If anyone
+gets access to that file they can sign kernels with it. Keep it secure.
+
+
+Step 5: Sign the kernel
+-----------------------
+
+We need to use mkimage (which was built when you built U-Boot) to package the
+Linux kernel into a FIT (Flat Image Tree, a flexible file format that U-Boot
+can load) using the ITS file you just created.
+
+At the same time we must put the public key into U-Boot device tree, with the
+'required' property, which tells U-Boot that this key must be verified for the
+image to be valid. You will make this key available to U-Boot for booting in
+step 6::
+
+   ln -s $OKERNEL/dts/am335x-boneblack.dtb
+   ln -s $OKERNEL/Image
+   ln -s $UOUT/u-boot-dtb.img
+   cp $UOUT/arch/arm/dts/am335x-boneblack.dtb am335x-boneblack-pubkey.dtb
+   lzop Image
+   $UOUT/tools/mkimage -f sign.its -K am335x-boneblack-pubkey.dtb -k keys -r image.fit
+
+You should see something like this::
+
+    FIT description: Beaglebone black
+    Created:         Sun Jun  1 12:50:30 2014
+     Image 0 (kernel)
+      Description:  unavailable
+      Created:      Sun Jun  1 12:50:30 2014
+      Type:         Kernel Image
+      Compression:  lzo compressed
+      Data Size:    7790938 Bytes = 7608.34 kB = 7.43 MB
+      Architecture: ARM
+      OS:           Linux
+      Load Address: 0x80008000
+      Entry Point:  0x80008000
+      Hash algo:    sha1
+      Hash value:   c94364646427e10f423837e559898ef02c97b988
+     Image 1 (fdt-1)
+      Description:  beaglebone-black
+      Created:      Sun Jun  1 12:50:30 2014
+      Type:         Flat Device Tree
+      Compression:  uncompressed
+      Data Size:    31547 Bytes = 30.81 kB = 0.03 MB
+      Architecture: ARM
+      Hash algo:    sha1
+      Hash value:   cb09202f889d824f23b8e4404b781be5ad38a68d
+     Default Configuration: 'conf-1'
+     Configuration 0 (conf-1)
+      Description:  unavailable
+      Kernel:       kernel
+      FDT:          fdt-1
+
+
+Now am335x-boneblack-pubkey.dtb contains the public key and image.fit contains
+the signed kernel. Jump to step 6 if you like, or continue reading to increase
+your understanding.
+
+You can also run fit_check_sign to check it::
+
+   $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb
+
+which results in::
+
+    Verifying Hash Integrity ... sha1,rsa2048:dev+
+    ## Loading kernel from FIT Image at 7fc6ee469000 ...
+       Using 'conf-1' configuration
+       Verifying Hash Integrity ...
+    sha1,rsa2048:dev+
+    OK
+
+       Trying 'kernel' kernel subimage
+         Description:  unavailable
+         Created:      Sun Jun  1 12:50:30 2014
+         Type:         Kernel Image
+         Compression:  lzo compressed
+         Data Size:    7790938 Bytes = 7608.34 kB = 7.43 MB
+         Architecture: ARM
+         OS:           Linux
+         Load Address: 0x80008000
+         Entry Point:  0x80008000
+         Hash algo:    sha1
+         Hash value:   c94364646427e10f423837e559898ef02c97b988
+       Verifying Hash Integrity ...
+    sha1+
+    OK
+
+    Unimplemented compression type 4
+    ## Loading fdt from FIT Image at 7fc6ee469000 ...
+       Using 'conf-1' configuration
+       Trying 'fdt-1' fdt subimage
+         Description:  beaglebone-black
+         Created:      Sun Jun  1 12:50:30 2014
+         Type:         Flat Device Tree
+         Compression:  uncompressed
+         Data Size:    31547 Bytes = 30.81 kB = 0.03 MB
+         Architecture: ARM
+         Hash algo:    sha1
+         Hash value:   cb09202f889d824f23b8e4404b781be5ad38a68d
+       Verifying Hash Integrity ...
+    sha1+
+    OK
+
+       Loading Flat Device Tree ... OK
+
+    ## Loading ramdisk from FIT Image at 7fc6ee469000 ...
+       Using 'conf-1' configuration
+    Could not find subimage node
+
+    Signature check OK
+
+
+At the top, you see "sha1,rsa2048:dev+". This means that it checked an RSA key
+of size 2048 bits using SHA1 as the hash algorithm. The key name checked was
+'dev' and the '+' means that it verified. If it showed '-' that would be bad.
+
+Once the configuration is verified it is then possible to rely on the hashes
+in each image referenced by that configuration. So fit_check_sign goes on to
+load each of the images. We have a kernel and an FDT but no ramkdisk. In each
+case fit_check_sign checks the hash and prints sha1+ meaning that the SHA1
+hash verified. This means that none of the images has been tampered with.
+
+There is a test in test/vboot which uses U-Boot's sandbox build to verify that
+the above flow works.
+
+But it is fun to do this by hand, so you can load image.fit into a hex editor
+like ghex, and change a byte in the kernel::
+
+    $UOUT/tools/fit_info -f image.fit -n /images/kernel -p data
+    NAME: kernel
+    LEN: 7790938
+    OFF: 168
+
+This tells us that the kernel starts at byte offset 168 (decimal) in image.fit
+and extends for about 7MB. Try changing a byte at 0x2000 (say) and run
+fit_check_sign again. You should see something like::
+
+    Verifying Hash Integrity ... sha1,rsa2048:dev+
+    ## Loading kernel from FIT Image at 7f5a39571000 ...
+       Using 'conf-1' configuration
+       Verifying Hash Integrity ...
+    sha1,rsa2048:dev+
+    OK
+
+       Trying 'kernel' kernel subimage
+         Description:  unavailable
+         Created:      Sun Jun  1 13:09:21 2014
+         Type:         Kernel Image
+         Compression:  lzo compressed
+         Data Size:    7790938 Bytes = 7608.34 kB = 7.43 MB
+         Architecture: ARM
+         OS:           Linux
+         Load Address: 0x80008000
+         Entry Point:  0x80008000
+         Hash algo:    sha1
+         Hash value:   c94364646427e10f423837e559898ef02c97b988
+       Verifying Hash Integrity ...
+    sha1 error
+    Bad hash value for 'hash-1' hash node in 'kernel' image node
+    Bad Data Hash
+
+    ## Loading fdt from FIT Image at 7f5a39571000 ...
+       Using 'conf-1' configuration
+       Trying 'fdt-1' fdt subimage
+         Description:  beaglebone-black
+         Created:      Sun Jun  1 13:09:21 2014
+         Type:         Flat Device Tree
+         Compression:  uncompressed
+         Data Size:    31547 Bytes = 30.81 kB = 0.03 MB
+         Architecture: ARM
+         Hash algo:    sha1
+         Hash value:   cb09202f889d824f23b8e4404b781be5ad38a68d
+       Verifying Hash Integrity ...
+    sha1+
+    OK
+
+       Loading Flat Device Tree ... OK
+
+    ## Loading ramdisk from FIT Image at 7f5a39571000 ...
+       Using 'conf-1' configuration
+    Could not find subimage node
+
+    Signature check Bad (error 1)
+
+
+It has detected the change in the kernel.
+
+You can also be sneaky and try to switch images, using the libfdt utilities
+that come with dtc (package name is device-tree-compiler but you will need a
+recent version like 1.4::
+
+    dtc -v
+    Version: DTC 1.4.0
+
+First we can check which nodes are actually hashed by the configuration::
+
+    $ fdtget -l image.fit /
+    images
+    configurations
+
+    $ fdtget -l image.fit /configurations
+    conf-1
+    fdtget -l image.fit /configurations/conf-1
+    signature-1
+
+    $ fdtget -p image.fit /configurations/conf-1/signature-1
+    hashed-strings
+    hashed-nodes
+    timestamp
+    signer-version
+    signer-name
+    value
+    algo
+    key-name-hint
+    sign-images
+
+    $ fdtget image.fit /configurations/conf-1/signature-1 hashed-nodes
+    / /configurations/conf-1 /images/fdt-1 /images/fdt-1/hash /images/kernel /images/kernel/hash-1
+
+This gives us a bit of a look into the signature that mkimage added. Note you
+can also use fdtdump to list the entire device tree.
+
+Say we want to change the kernel that this configuration uses
+(/images/kernel). We could just put a new kernel in the image, but we will
+need to change the hash to match. Let's simulate that by changing a byte of
+the hash::
+
+    fdtget -tx image.fit /images/kernel/hash-1 value
+    c9436464 6427e10f 423837e5 59898ef0 2c97b988
+    fdtput -tx image.fit /images/kernel/hash-1 value c9436464 6427e10f 423837e5 59898ef0 2c97b981
+
+Now check it again::
+
+    $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb
+    Verifying Hash Integrity ... sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13
+    rsa_verify_with_keynode: RSA failed to verify: -13
+    -
+    Failed to verify required signature 'key-dev'
+    Signature check Bad (error 1)
+
+This time we don't even get as far as checking the images, since the
+configuration signature doesn't match. We can't change any hashes without the
+signature check noticing. The configuration is essentially locked. U-Boot has
+a public key for which it requires a match, and will not permit the use of any
+configuration that does not match that public key. The only way the
+configuration will match is if it was signed by the matching private key.
+
+It would also be possible to add a new signature node that does match your new
+configuration. But that won't work since you are not allowed to change the
+configuration in any way. Try it with a fresh (valid) image if you like by
+running the mkimage link again. Then::
+
+    fdtput -p image.fit /configurations/conf-1/signature-1 value fred
+    $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb
+    Verifying Hash Integrity ... -
+    sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13
+    rsa_verify_with_keynode: RSA failed to verify: -13
+    -
+    Failed to verify required signature 'key-dev'
+    Signature check Bad (error 1)
+
+
+Of course it would be possible to add an entirely new configuration and boot
+with that, but it still needs to be signed, so it won't help.
+
+
+6. Put the public key into U-Boot's image
+-----------------------------------------
+
+Having confirmed that the signature is doing its job, let's try it out in
+U-Boot on the board. U-Boot needs access to the public key corresponding to
+the private key that you signed with so that it can verify any kernels that
+you sign::
+
+    cd $UBOOT
+    make O=b/am335x_boneblack_vboot EXT_DTB=${WORK}/am335x-boneblack-pubkey.dtb
+
+Here we are overriding the normal device tree file with our one, which
+contains the public key.
+
+Now you have a special U-Boot image with the public key. It can verify can
+kernel that you sign with the private key as in step 5.
+
+If you like you can take a look at the public key information that mkimage
+added to U-Boot's device tree::
+
+    fdtget -p am335x-boneblack-pubkey.dtb /signature/key-dev
+    required
+    algo
+    rsa,r-squared
+    rsa,modulus
+    rsa,n0-inverse
+    rsa,num-bits
+    key-name-hint
+
+This has information about the key and some pre-processed values which U-Boot
+can use to verify against it. These values are obtained from the public key
+certificate by mkimage, but require quite a bit of code to generate. To save
+code space in U-Boot, the information is extracted and written in raw form for
+U-Boot to easily use. The same mechanism is used in Google's Chrome OS.
+
+Notice the 'required' property. This marks the key as required - U-Boot will
+not boot any image that does not verify against this key.
+
+
+7. Put U-Boot and the kernel onto the board
+-------------------------------------------
+
+The method here varies depending on how you are booting. For this example we
+are booting from an micro-SD card with two partitions, one for U-Boot and one
+for Linux. Put it into your machine and write U-Boot and the kernel to it.
+Here the card is /dev/sde::
+
+    cd $WORK
+    export UDEV=/dev/sde1   # Change thes two lines to the correct device
+    export KDEV=/dev/sde2
+    sudo mount $UDEV /mnt/tmp && sudo cp $UOUT/u-boot-dtb.img /mnt/tmp/u-boot.img  && sleep 1 && sudo umount $UDEV
+    sudo mount $KDEV /mnt/tmp && sudo cp $WORK/image.fit /mnt/tmp/boot/image.fit && sleep 1 && sudo umount $KDEV
+
+
+8. Try it
+---------
+
+Boot the board using the commands below::
+
+    setenv bootargs console=ttyO0,115200n8 quiet root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait
+    ext2load mmc 0:2 82000000 /boot/image.fit
+    bootm 82000000
+
+You should then see something like this::
+
+    U-Boot# setenv bootargs console=ttyO0,115200n8 quiet root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait
+    U-Boot# ext2load mmc 0:2 82000000 /boot/image.fit
+    7824930 bytes read in 589 ms (12.7 MiB/s)
+    U-Boot# bootm 82000000
+    ## Loading kernel from FIT Image at 82000000 ...
+       Using 'conf-1' configuration
+       Verifying Hash Integrity ... sha1,rsa2048:dev+ OK
+       Trying 'kernel' kernel subimage
+         Description:  unavailable
+         Created:      2014-06-01  19:32:54 UTC
+         Type:         Kernel Image
+         Compression:  lzo compressed
+         Data Start:   0x820000a8
+         Data Size:    7790938 Bytes = 7.4 MiB
+         Architecture: ARM
+         OS:           Linux
+         Load Address: 0x80008000
+         Entry Point:  0x80008000
+         Hash algo:    sha1
+         Hash value:   c94364646427e10f423837e559898ef02c97b988
+       Verifying Hash Integrity ... sha1+ OK
+    ## Loading fdt from FIT Image at 82000000 ...
+       Using 'conf-1' configuration
+       Trying 'fdt-1' fdt subimage
+         Description:  beaglebone-black
+         Created:      2014-06-01  19:32:54 UTC
+         Type:         Flat Device Tree
+         Compression:  uncompressed
+         Data Start:   0x8276e2ec
+         Data Size:    31547 Bytes = 30.8 KiB
+         Architecture: ARM
+         Hash algo:    sha1
+         Hash value:   cb09202f889d824f23b8e4404b781be5ad38a68d
+       Verifying Hash Integrity ... sha1+ OK
+       Booting using the fdt blob at 0x8276e2ec
+       Uncompressing Kernel Image ... OK
+       Loading Device Tree to 8fff5000, end 8ffffb3a ... OK
+
+    Starting kernel ...
+
+    [    0.582377] omap_init_mbox: hwmod doesn't have valid attrs
+    [    2.589651] musb-hdrc musb-hdrc.0.auto: Failed to request rx1.
+    [    2.595830] musb-hdrc musb-hdrc.0.auto: musb_init_controller failed with status -517
+    [    2.606470] musb-hdrc musb-hdrc.1.auto: Failed to request rx1.
+    [    2.612723] musb-hdrc musb-hdrc.1.auto: musb_init_controller failed with status -517
+    [    2.940808] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
+    [    7.248889] libphy: PHY 4a101000.mdio:01 not found
+    [    7.253995] net eth0: phy 4a101000.mdio:01 not found on slave 1
+    systemd-fsck[83]: Angstrom: clean, 50607/218160 files, 306348/872448 blocks
+
+    .---O---.
+    |       |                  .-.           o o
+    |   |   |-----.-----.-----.| |   .----..-----.-----.
+    |       |     | __  |  ---'| '--.|  .-'|     |     |
+    |   |   |  |  |     |---  ||  --'|  |  |  '  | | | |
+    '---'---'--'--'--.  |-----''----''--'  '-----'-'-'-'
+                    -'  |
+                    '---'
+
+    The Angstrom Distribution beaglebone ttyO0
+
+    Angstrom v2012.12 - Kernel 3.14.1+
+
+    beaglebone login:
+
+At this point your kernel has been verified and you can be sure that it is one
+that you signed. As an exercise, try changing image.fit as in step 5 and see
+what happens.
+
+
+Further Improvements
+--------------------
+
+Several of the steps here can be easily automated. In particular it would be
+capital if signing and packaging a kernel were easy, perhaps a simple make
+target in the kernel.
+
+Some mention of how to use multiple .dtb files in a FIT might be useful.
+
+U-Boot's verified boot mechanism has not had a robust and independent security
+review. Such a review should look at the implementation and its resistance to
+attacks.
+
+Perhaps the verified boot feature could be integrated into the Amstrom
+distribution.
+
+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>, 2-June-14
diff --git a/doc/usage/fit/howto.rst b/doc/usage/fit/howto.rst
new file mode 100644
index 0000000000..c933703d1d
--- /dev/null
+++ b/doc/usage/fit/howto.rst
@@ -0,0 +1,419 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+How to use images in the new image format
+=========================================
+
+Overview
+--------
+
+The new uImage format allows more flexibility in handling images of various
+types (kernel, ramdisk, etc.), it also enhances integrity protection of images
+with sha1 and md5 checksums.
+
+Two auxiliary tools are needed on the development host system in order to
+create an uImage in the new format: mkimage and dtc, although only one
+(mkimage) is invoked directly. dtc is called from within mkimage and operates
+behind the scenes, but needs to be present in the $PATH nevertheless. It is
+important that the dtc used has support for binary includes -- refer to::
+
+    git://git.kernel.org/pub/scm/utils/dtc/dtc.git
+
+for its latest version. mkimage (together with dtc) takes as input
+an image source file, which describes the contents of the image and defines
+its various properties used during booting. By convention, image source file
+has the ".its" extension, also, the details of its format are given in
+doc/uImage.FIT/source_file_format.txt. The actual data that is to be included in
+the uImage (kernel, ramdisk, etc.) is specified in the image source file in the
+form of paths to appropriate data files. The outcome of the image creation
+process is a binary file (by convention with the ".itb" extension) that
+contains all the referenced data (kernel, ramdisk, etc.) and other information
+needed by U-Boot to handle the uImage properly. The uImage file is then
+transferred to the target (e.g., via tftp) and booted using the bootm command.
+
+To summarize the prerequisites needed for new uImage creation:
+
+- mkimage
+- dtc (with support for binary includes)
+- image source file (`*.its`)
+- image data file(s)
+
+
+Here's a graphical overview of the image creation and booting process::
+
+    image source file     mkimage + dtc          transfer to target
+        +          ---------------> image file --------------------> bootm
+    image data file(s)
+
+SPL usage
+---------
+
+The SPL can make use of the new image format as well, this traditionally
+is used to ship multiple device tree files within one image. Code in the SPL
+will choose the one matching the current board and append this to the
+U-Boot proper binary to be automatically used up by it.
+Aside from U-Boot proper and one device tree blob the SPL can load multiple,
+arbitrary image files as well. These binaries should be specified in their
+own subnode under the /images node, which should then be referenced from one or
+multiple /configurations subnodes. The required images must be enumerated in
+the "loadables" property as a list of strings.
+
+If a platform specific image source file (.its) is shipped with the U-Boot
+source, it can be specified using the CONFIG_SPL_FIT_SOURCE Kconfig symbol.
+In this case it will be automatically used by U-Boot's Makefile to generate
+the image.
+If a static source file is not flexible enough, CONFIG_SPL_FIT_GENERATOR
+can point to a script which generates this image source file during
+the build process. It gets passed a list of device tree files (taken from the
+CONFIG_OF_LIST symbol).
+
+The SPL also records to a DT all additional images (called loadables) which are
+loaded. The information about loadables locations is passed via the DT node with
+fit-images name.
+
+Finally, if there are multiple xPL phases (e.g. SPL, VPL), images can be marked
+as intended for a particular phase using the 'phase' property. For example, if
+fit_image_load() is called with image_ph(IH_PHASE_SPL, IH_TYPE_FIRMWARE), then
+only the image listed into the "firmware" property where phase is set to "spl"
+will be loaded.
+
+Loadables Example
+-----------------
+Consider the following case for an ARM64 platform where U-Boot runs in EL2
+started by ATF where SPL is loading U-Boot (as loadables) and ATF (as firmware).
+
+::
+
+    /dts-v1/;
+
+    / {
+        description = "Configuration to load ATF before U-Boot";
+
+        images {
+            uboot {
+                description = "U-Boot (64-bit)";
+                data = /incbin/("u-boot-nodtb.bin");
+                type = "firmware";
+                os = "u-boot";
+                arch = "arm64";
+                compression = "none";
+                load = <0x8 0x8000000>;
+                entry = <0x8 0x8000000>;
+                hash {
+                    algo = "md5";
+                };
+            };
+            atf {
+                description = "ARM Trusted Firmware";
+                data = /incbin/("bl31.bin");
+                type = "firmware";
+                os = "arm-trusted-firmware";
+                arch = "arm64";
+                compression = "none";
+                load = <0xfffea000>;
+                entry = <0xfffea000>;
+                hash {
+                    algo = "md5";
+                };
+            };
+            fdt_1 {
+                description = "zynqmp-zcu102-revA";
+                data = /incbin/("arch/arm/dts/zynqmp-zcu102-revA.dtb");
+                type = "flat_dt";
+                arch = "arm64";
+                compression = "none";
+                load = <0x100000>;
+                hash {
+                    algo = "md5";
+                };
+            };
+        };
+        configurations {
+            default = "config_1";
+
+            config_1 {
+                description = "zynqmp-zcu102-revA";
+                firmware = "atf";
+                loadables = "uboot";
+                fdt = "fdt_1";
+            };
+        };
+    };
+
+In this case the SPL records via fit-images DT node the information about
+loadables U-Boot image::
+
+    ZynqMP> fdt addr $fdtcontroladdr
+    ZynqMP> fdt print /fit-images
+    fit-images {
+        uboot {
+            os = "u-boot";
+            type = "firmware";
+            size = <0x001017c8>;
+            entry = <0x00000008 0x08000000>;
+            load = <0x00000008 0x08000000>;
+        };
+    };
+
+As you can see entry and load properties are 64bit wide to support loading
+images above 4GB (in past entry and load properties where just 32bit).
+
+
+Example 1 -- old-style (non-FDT) kernel booting
+-----------------------------------------------
+
+Consider a simple scenario, where a PPC Linux kernel built from sources on the
+development host is to be booted old-style (non-FDT) by U-Boot on an embedded
+target. Assume that the outcome of the build is vmlinux.bin.gz, a file which
+contains a gzip-compressed PPC Linux kernel (the only data file in this case).
+The uImage can be produced using the image source file
+doc/uImage.FIT/kernel.its (note that kernel.its assumes that vmlinux.bin.gz is
+in the current working directory; if desired, an alternative path can be
+specified in the kernel.its file). Here's how to create the image and inspect
+its contents:
+
+[on the host system]::
+
+    $ mkimage -f kernel.its kernel.itb
+    DTC: dts->dtb  on file "kernel.its"
+    $
+    $ mkimage -l kernel.itb
+    FIT description: Simple image with single Linux kernel
+    Created:     Tue Mar 11 17:26:15 2008
+     Image 0 (kernel)
+      Description:    Vanilla Linux kernel
+      Type:        Kernel Image
+      Compression:    gzip compressed
+      Data Size:    943347 Bytes = 921.24 kB = 0.90 MB
+      Architecture: PowerPC
+      OS:        Linux
+      Load Address: 0x00000000
+      Entry Point:    0x00000000
+      Hash algo:    crc32
+      Hash value:    2ae2bb40
+      Hash algo:    sha1
+      Hash value:    3c200f34e2c226ddc789240cca0c59fc54a67cf4
+     Default Configuration: 'config-1'
+     Configuration 0 (config-1)
+      Description:    Boot Linux kernel
+      Kernel:    kernel
+
+
+The resulting image file kernel.itb can be now transferred to the target,
+inspected and booted (note that first three U-Boot commands below are shown
+for completeness -- they are part of the standard booting procedure and not
+specific to the new image format).
+
+[on the target system]::
+
+    => print nfsargs
+    nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
+    => print addip
+    addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off panic=1
+    => run nfsargs addip
+    => tftp 900000 /path/to/tftp/location/kernel.itb
+    Using FEC device
+    TFTP from server 192.168.1.1; our IP address is 192.168.160.5
+    Filename '/path/to/tftp/location/kernel.itb'.
+    Load address: 0x900000
+    Loading: #################################################################
+    done
+    Bytes transferred = 944464 (e6950 hex)
+    => iminfo
+
+    ## Checking Image at 00900000 ...
+       FIT image found
+       FIT description: Simple image with single Linux kernel
+       Created:        2008-03-11    16:26:15 UTC
+        Image 0 (kernel)
+         Description:  Vanilla Linux kernel
+         Type:       Kernel Image
+         Compression:  gzip compressed
+         Data Start:   0x009000e0
+         Data Size:    943347 Bytes = 921.2 kB
+         Architecture: PowerPC
+         OS:       Linux
+         Load Address: 0x00000000
+         Entry Point:  0x00000000
+         Hash algo:    crc32
+         Hash value:   2ae2bb40
+         Hash algo:    sha1
+         Hash value:   3c200f34e2c226ddc789240cca0c59fc54a67cf4
+        Default Configuration: 'config-1'
+        Configuration 0 (config-1)
+         Description:  Boot Linux kernel
+         Kernel:       kernel
+
+    => bootm
+    ## Booting kernel from FIT Image at 00900000 ...
+       Using 'config-1' configuration
+       Trying 'kernel' kernel subimage
+         Description:  Vanilla Linux kernel
+         Type:       Kernel Image
+         Compression:  gzip compressed
+         Data Start:   0x009000e0
+         Data Size:    943347 Bytes = 921.2 kB
+         Architecture: PowerPC
+         OS:       Linux
+         Load Address: 0x00000000
+         Entry Point:  0x00000000
+         Hash algo:    crc32
+         Hash value:   2ae2bb40
+         Hash algo:    sha1
+         Hash value:   3c200f34e2c226ddc789240cca0c59fc54a67cf4
+       Verifying Hash Integrity ... crc32+ sha1+ OK
+       Uncompressing Kernel Image ... OK
+    Memory BAT mapping: BAT2=256Mb, BAT3=0Mb, residual: 0Mb
+    Linux version 2.4.25 (m8@hekate) (gcc version 4.0.0 (DENX ELDK 4.0 4.0.0)) #2 czw lip 5 17:56:18 CEST 2007
+    On node 0 totalpages: 65536
+    zone(0): 65536 pages.
+    zone(1): 0 pages.
+    zone(2): 0 pages.
+    Kernel command line: root=/dev/nfs rw nfsroot=192.168.1.1:/opt/eldk-4.1/ppc_6xx ip=192.168.160.5:192.168.1.1::255.255.0.0:lite5200b:eth0:off panic=1
+    Calibrating delay loop... 307.20 BogoMIPS
+
+
+Example 2 -- new-style (FDT) kernel booting
+-------------------------------------------
+
+Consider another simple scenario, where a PPC Linux kernel is to be booted
+new-style, i.e., with a FDT blob. In this case there are two prerequisite data
+files: vmlinux.bin.gz (Linux kernel) and target.dtb (FDT blob). The uImage can
+be produced using image source file doc/uImage.FIT/kernel_fdt.its like this
+(note again, that both prerequisite data files are assumed to be present in
+the current working directory -- image source file kernel_fdt.its can be
+modified to take the files from some other location if needed):
+
+[on the host system]::
+
+    $ mkimage -f kernel_fdt.its kernel_fdt.itb
+    DTC: dts->dtb  on file "kernel_fdt.its"
+    $
+    $ mkimage -l kernel_fdt.itb
+    FIT description: Simple image with single Linux kernel and FDT blob
+    Created:     Tue Mar 11 16:29:22 2008
+     Image 0 (kernel)
+      Description:    Vanilla Linux kernel
+      Type:        Kernel Image
+      Compression:    gzip compressed
+      Data Size:    1092037 Bytes = 1066.44 kB = 1.04 MB
+      Architecture: PowerPC
+      OS:        Linux
+      Load Address: 0x00000000
+      Entry Point:    0x00000000
+      Hash algo:    crc32
+      Hash value:    2c0cc807
+      Hash algo:    sha1
+      Hash value:    264b59935470e42c418744f83935d44cdf59a3bb
+     Image 1 (fdt-1)
+      Description:    Flattened Device Tree blob
+      Type:        Flat Device Tree
+      Compression:    uncompressed
+      Data Size:    16384 Bytes = 16.00 kB = 0.02 MB
+      Architecture: PowerPC
+      Hash algo:    crc32
+      Hash value:    0d655d71
+      Hash algo:    sha1
+      Hash value:    25ab4e15cd4b8a5144610394560d9c318ce52def
+     Default Configuration: 'conf-1'
+     Configuration 0 (conf-1)
+      Description:    Boot Linux kernel with FDT blob
+      Kernel:    kernel
+      FDT:        fdt-1
+
+
+The resulting image file kernel_fdt.itb can be now transferred to the target,
+inspected and booted:
+
+[on the target system]::
+
+    => tftp 900000 /path/to/tftp/location/kernel_fdt.itb
+    Using FEC device
+    TFTP from server 192.168.1.1; our IP address is 192.168.160.5
+    Filename '/path/to/tftp/location/kernel_fdt.itb'.
+    Load address: 0x900000
+    Loading: #################################################################
+         ###########
+    done
+    Bytes transferred = 1109776 (10ef10 hex)
+    => iminfo
+
+    ## Checking Image at 00900000 ...
+       FIT image found
+       FIT description: Simple image with single Linux kernel and FDT blob
+       Created:        2008-03-11    15:29:22 UTC
+        Image 0 (kernel)
+         Description:  Vanilla Linux kernel
+         Type:       Kernel Image
+         Compression:  gzip compressed
+         Data Start:   0x009000ec
+         Data Size:    1092037 Bytes =  1 MB
+         Architecture: PowerPC
+         OS:       Linux
+         Load Address: 0x00000000
+         Entry Point:  0x00000000
+         Hash algo:    crc32
+         Hash value:   2c0cc807
+         Hash algo:    sha1
+         Hash value:   264b59935470e42c418744f83935d44cdf59a3bb
+        Image 1 (fdt-1)
+         Description:  Flattened Device Tree blob
+         Type:       Flat Device Tree
+         Compression:  uncompressed
+         Data Start:   0x00a0abdc
+         Data Size:    16384 Bytes = 16 kB
+         Architecture: PowerPC
+         Hash algo:    crc32
+         Hash value:   0d655d71
+         Hash algo:    sha1
+         Hash value:   25ab4e15cd4b8a5144610394560d9c318ce52def
+        Default Configuration: 'conf-1'
+        Configuration 0 (conf-1)
+         Description:  Boot Linux kernel with FDT blob
+         Kernel:       kernel
+         FDT:       fdt-1
+    => bootm
+    ## Booting kernel from FIT Image at 00900000 ...
+       Using 'conf-1' configuration
+       Trying 'kernel' kernel subimage
+         Description:  Vanilla Linux kernel
+         Type:       Kernel Image
+         Compression:  gzip compressed
+         Data Start:   0x009000ec
+         Data Size:    1092037 Bytes =  1 MB
+         Architecture: PowerPC
+         OS:       Linux
+         Load Address: 0x00000000
+         Entry Point:  0x00000000
+         Hash algo:    crc32
+         Hash value:   2c0cc807
+         Hash algo:    sha1
+         Hash value:   264b59935470e42c418744f83935d44cdf59a3bb
+       Verifying Hash Integrity ... crc32+ sha1+ OK
+       Uncompressing Kernel Image ... OK
+    ## Flattened Device Tree from FIT Image at 00900000
+       Using 'conf-1' configuration
+       Trying 'fdt-1' FDT blob subimage
+         Description:  Flattened Device Tree blob
+         Type:       Flat Device Tree
+         Compression:  uncompressed
+         Data Start:   0x00a0abdc
+         Data Size:    16384 Bytes = 16 kB
+         Architecture: PowerPC
+         Hash algo:    crc32
+         Hash value:   0d655d71
+         Hash algo:    sha1
+         Hash value:   25ab4e15cd4b8a5144610394560d9c318ce52def
+       Verifying Hash Integrity ... crc32+ sha1+ OK
+       Booting using the fdt blob at 0xa0abdc
+       Loading Device Tree to 007fc000, end 007fffff ... OK
+    [    0.000000] Using lite5200 machine description
+    [    0.000000] Linux version 2.6.24-rc6-gaebecdfc (m8@hekate) (gcc version 4.0.0 (DENX ELDK 4.1 4.0.0)) #1 Sat Jan 12 15:38:48 CET 2008
+
+
+Example 3 -- advanced booting
+-----------------------------
+
+Refer to :doc:`multi` for an image source file that allows more
+sophisticated booting scenarios (multiple kernels, ramdisks and fdt blobs).
+
+.. sectionauthor:: Bartlomiej Sieka <tur@semihalf.com>
diff --git a/doc/usage/fit.rst b/doc/usage/fit/index.rst
index 7037434057..bd25bd30b2 100644
--- a/doc/usage/fit.rst
+++ b/doc/usage/fit/index.rst
@@ -6,3 +6,14 @@ Flat Image Tree (FIT)
 U-Boot uses Flat Image Tree (FIT) as a standard file format for packaging
 images that it it reads and boots. Documentation about FIT is available at
 doc/uImage.FIT
+
+.. toctree::
+    :maxdepth: 1
+
+    source_file_format
+    howto
+    x86-fit-boot
+    signature
+    verified-boot
+    beaglebone_vboot
+    overlay-fdt-boot
diff --git a/doc/usage/fit/kernel.rst b/doc/usage/fit/kernel.rst
new file mode 100644
index 0000000000..012a81efea
--- /dev/null
+++ b/doc/usage/fit/kernel.rst
@@ -0,0 +1,93 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Single kernel
+=============
+
+::
+
+    /dts-v1/;
+
+    / {
+        description = "Simple image with single Linux kernel";
+        #address-cells = <1>;
+
+        images {
+            kernel {
+                description = "Vanilla Linux kernel";
+                data = /incbin/("./vmlinux.bin.gz");
+                type = "kernel";
+                arch = "ppc";
+                os = "linux";
+                compression = "gzip";
+                load = <00000000>;
+                entry = <00000000>;
+                hash-1 {
+                    algo = "crc32";
+                };
+                hash-2 {
+                    algo = "sha1";
+                };
+            };
+        };
+
+        configurations {
+            default = "config-1";
+            config-1 {
+                description = "Boot Linux kernel";
+                kernel = "kernel";
+            };
+        };
+    };
+
+
+For x86 a setup node is also required: see x86-fit-boot::
+
+    /dts-v1/;
+
+    / {
+        description = "Simple image with single Linux kernel on x86";
+        #address-cells = <1>;
+
+        images {
+            kernel {
+                description = "Vanilla Linux kernel";
+                data = /incbin/("./image.bin.lzo");
+                type = "kernel";
+                arch = "x86";
+                os = "linux";
+                compression = "lzo";
+                load = <0x01000000>;
+                entry = <0x00000000>;
+                hash-2 {
+                    algo = "sha1";
+                };
+            };
+
+            setup {
+                description = "Linux setup.bin";
+                data = /incbin/("./setup.bin");
+                type = "x86_setup";
+                arch = "x86";
+                os = "linux";
+                compression = "none";
+                load = <0x00090000>;
+                entry = <0x00090000>;
+                hash-2 {
+                    algo = "sha1";
+                };
+            };
+        };
+
+        configurations {
+            default = "config-1";
+            config-1 {
+                description = "Boot Linux kernel";
+                kernel = "kernel";
+                setup = "setup";
+            };
+        };
+    };
+
+Note: the above assumes a 32-bit kernel. To directly boot a 64-bit kernel,
+change both arch values to "x86_64". U-Boot will then change to 64-bit mode
+before booting the kernel (see boot_linux_kernel()).
diff --git a/doc/usage/fit/kernel_fdt.rst b/doc/usage/fit/kernel_fdt.rst
new file mode 100644
index 0000000000..8eee13af78
--- /dev/null
+++ b/doc/usage/fit/kernel_fdt.rst
@@ -0,0 +1,54 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Single kernel and FDT blob
+==========================
+
+::
+
+	/dts-v1/;
+
+	/ {
+	description = "Simple image with single Linux kernel and FDT blob";
+	#address-cells = <1>;
+
+	images {
+		kernel {
+		description = "Vanilla Linux kernel";
+		data = /incbin/("./vmlinux.bin.gz");
+		type = "kernel";
+		arch = "ppc";
+		os = "linux";
+		compression = "gzip";
+		load = <00000000>;
+		entry = <00000000>;
+		hash-1 {
+			algo = "crc32";
+		};
+		hash-2 {
+			algo = "sha1";
+		};
+		};
+		fdt-1 {
+		description = "Flattened Device Tree blob";
+		data = /incbin/("./target.dtb");
+		type = "flat_dt";
+		arch = "ppc";
+		compression = "none";
+		hash-1 {
+			algo = "crc32";
+		};
+		hash-2 {
+			algo = "sha1";
+		};
+		};
+	};
+
+	configurations {
+		default = "conf-1";
+		conf-1 {
+		description = "Boot Linux kernel with FDT blob";
+		kernel = "kernel";
+		fdt = "fdt-1";
+		};
+	};
+	};
diff --git a/doc/usage/fit/kernel_fdts_compressed.rst b/doc/usage/fit/kernel_fdts_compressed.rst
new file mode 100644
index 0000000000..0b169c7c27
--- /dev/null
+++ b/doc/usage/fit/kernel_fdts_compressed.rst
@@ -0,0 +1,77 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kernel and multiple compressed FDT blobs
+========================================
+
+Since the FDTs are compressed, configurations must provide a compatible
+string to match directly.
+
+::
+
+    /dts-v1/;
+
+    / {
+        description = "Image with single Linux kernel and compressed FDT blobs";
+        #address-cells = <1>;
+
+        images {
+            kernel {
+                description = "Vanilla Linux kernel";
+                data = /incbin/("./vmlinux.bin.gz");
+                type = "kernel";
+                arch = "ppc";
+                os = "linux";
+                compression = "gzip";
+                load = <00000000>;
+                entry = <00000000>;
+                hash-1 {
+                    algo = "crc32";
+                };
+                hash-2 {
+                    algo = "sha1";
+                };
+            };
+            fdt@1 {
+                description = "Flattened Device Tree blob 1";
+                data = /incbin/("./myboard-var1.dtb");
+                type = "flat_dt";
+                arch = "ppc";
+                compression = "gzip";
+                hash-1 {
+                    algo = "crc32";
+                };
+                hash-2 {
+                    algo = "sha1";
+                };
+            };
+            fdt@2 {
+                description = "Flattened Device Tree blob 2";
+                data = /incbin/("./myboard-var2.dtb");
+                type = "flat_dt";
+                arch = "ppc";
+                compression = "lzma";
+                hash-1 {
+                    algo = "crc32";
+                };
+                hash-2 {
+                    algo = "sha1";
+                };
+            };
+        };
+
+        configurations {
+            default = "conf@1";
+            conf@1 {
+                description = "Boot Linux kernel with FDT blob 1";
+                kernel = "kernel";
+                fdt = "fdt@1";
+                compatible = "myvendor,myboard-variant1";
+            };
+            conf@2 {
+                description = "Boot Linux kernel with FDT blob 2";
+                kernel = "kernel";
+                fdt = "fdt@2";
+                compatible = "myvendor,myboard-variant2";
+            };
+        };
+    };
diff --git a/doc/usage/fit/multi-with-fpga.rst b/doc/usage/fit/multi-with-fpga.rst
new file mode 100644
index 0000000000..28d7d5d262
--- /dev/null
+++ b/doc/usage/fit/multi-with-fpga.rst
@@ -0,0 +1,70 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Multiple kernels, ramdisks and FDT blobs with FPGA
+==================================================
+
+This example makes use of the 'loadables' field::
+
+    /dts-v1/;
+
+    / {
+        description = "Configuration to load fpga before Kernel";
+        #address-cells = <1>;
+
+        images {
+            fdt-1 {
+                description = "zc706";
+                data = /incbin/("/tftpboot/devicetree.dtb");
+                type = "flat_dt";
+                arch = "arm";
+                compression = "none";
+                load = <0x10000000>;
+                hash-1 {
+                    algo = "md5";
+                };
+            };
+
+            fpga {
+                description = "FPGA";
+                data = /incbin/("/tftpboot/download.bit");
+                type = "fpga";
+                arch = "arm";
+                compression = "none";
+                load = <0x30000000>;
+                compatible = "u-boot,fpga-legacy"
+                hash-1 {
+                    algo = "md5";
+                };
+            };
+
+            linux_kernel {
+                description = "Linux";
+                data = /incbin/("/tftpboot/zImage");
+                type = "kernel";
+                arch = "arm";
+                os = "linux";
+                compression = "none";
+                load = <0x8000>;
+                entry = <0x8000>;
+                hash-1 {
+                    algo = "md5";
+                };
+            };
+        };
+
+        configurations {
+            default = "config-2";
+            config-1 {
+                description = "Linux";
+                kernel = "linux_kernel";
+                fdt = "fdt-1";
+            };
+
+            config-2 {
+                description = "Linux with fpga";
+                kernel = "linux_kernel";
+                fdt = "fdt-1";
+                loadables = "fpga";
+            };
+        };
+    };
diff --git a/doc/usage/fit/multi-with-loadables.rst b/doc/usage/fit/multi-with-loadables.rst
new file mode 100644
index 0000000000..a0241df96c
--- /dev/null
+++ b/doc/usage/fit/multi-with-loadables.rst
@@ -0,0 +1,91 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Multiple kernels, ramdisks and FDT blobs with Xen
+=================================================
+
+This example makes use of the 'loadables' field::
+
+    /dts-v1/;
+
+    / {
+        description = "Configuration to load a Xen Kernel";
+        #address-cells = <1>;
+
+        images {
+            xen_kernel {
+                description = "xen binary";
+                data = /incbin/("./xen");
+                type = "kernel";
+                arch = "arm";
+                os = "linux";
+                compression = "none";
+                load = <0xa0000000>;
+                entry = <0xa0000000>;
+                hash-1 {
+                    algo = "md5";
+                };
+            };
+
+            fdt-1 {
+                description = "xexpress-ca15 tree blob";
+                data = /incbin/("./vexpress-v2p-ca15-tc1.dtb");
+                type = "flat_dt";
+                arch = "arm";
+                compression = "none";
+                load = <0xb0000000>;
+                hash-1 {
+                    algo = "md5";
+                };
+            };
+
+            fdt-2 {
+                description = "xexpress-ca15 tree blob";
+                data = /incbin/("./vexpress-v2p-ca15-tc1.dtb");
+                type = "flat_dt";
+                arch = "arm";
+                compression = "none";
+                load = <0xb0400000>;
+                hash-1 {
+                    algo = "md5";
+                };
+            };
+
+            linux_kernel {
+                description = "Linux Image";
+                data = /incbin/("./Image");
+                type = "kernel";
+                arch = "arm";
+                os = "linux";
+                compression = "none";
+                load = <0xa0000000>;
+                entry = <0xa0000000>;
+                hash-1 {
+                    algo = "md5";
+                };
+            };
+        };
+
+        configurations {
+            default = "config-2";
+
+            config-1 {
+                description = "Just plain Linux";
+                kernel = "linux_kernel";
+                fdt = "fdt-1";
+            };
+
+            config-2 {
+                description = "Xen one loadable";
+                kernel = "xen_kernel";
+                fdt = "fdt-1";
+                loadables = "linux_kernel";
+            };
+
+            config-3 {
+                description = "Xen two loadables";
+                kernel = "xen_kernel";
+                fdt = "fdt-1";
+                loadables = "linux_kernel", "fdt-2";
+            };
+        };
+    };
diff --git a/doc/usage/fit/multi.rst b/doc/usage/fit/multi.rst
new file mode 100644
index 0000000000..2e6ae58c40
--- /dev/null
+++ b/doc/usage/fit/multi.rst
@@ -0,0 +1,136 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Multiple kernels, ramdisks and FDT blobs
+========================================
+
+::
+
+    /dts-v1/;
+
+    / {
+        description = "Various kernels, ramdisks and FDT blobs";
+        #address-cells = <1>;
+
+        images {
+            kernel-1 {
+                description = "vanilla-2.6.23";
+                data = /incbin/("./vmlinux.bin.gz");
+                type = "kernel";
+                arch = "ppc";
+                os = "linux";
+                compression = "gzip";
+                load = <00000000>;
+                entry = <00000000>;
+                hash-1 {
+                    algo = "md5";
+                };
+                hash-2 {
+                    algo = "sha1";
+                };
+            };
+
+            kernel-2 {
+                description = "2.6.23-denx";
+                data = /incbin/("./2.6.23-denx.bin.gz");
+                type = "kernel";
+                arch = "ppc";
+                os = "linux";
+                compression = "gzip";
+                load = <00000000>;
+                entry = <00000000>;
+                hash-1 {
+                    algo = "sha1";
+                };
+            };
+
+            kernel-3 {
+                description = "2.4.25-denx";
+                data = /incbin/("./2.4.25-denx.bin.gz");
+                type = "kernel";
+                arch = "ppc";
+                os = "linux";
+                compression = "gzip";
+                load = <00000000>;
+                entry = <00000000>;
+                hash-1 {
+                    algo = "md5";
+                };
+            };
+
+            ramdisk-1 {
+                description = "eldk-4.2-ramdisk";
+                data = /incbin/("./eldk-4.2-ramdisk");
+                type = "ramdisk";
+                arch = "ppc";
+                os = "linux";
+                compression = "gzip";
+                load = <00000000>;
+                entry = <00000000>;
+                hash-1 {
+                    algo = "sha1";
+                };
+            };
+
+            ramdisk-2 {
+                description = "eldk-3.1-ramdisk";
+                data = /incbin/("./eldk-3.1-ramdisk");
+                type = "ramdisk";
+                arch = "ppc";
+                os = "linux";
+                compression = "gzip";
+                load = <00000000>;
+                entry = <00000000>;
+                hash-1 {
+                    algo = "crc32";
+                };
+            };
+
+            fdt-1 {
+                description = "tqm5200-fdt";
+                data = /incbin/("./tqm5200.dtb");
+                type = "flat_dt";
+                arch = "ppc";
+                compression = "none";
+                hash-1 {
+                    algo = "crc32";
+                };
+            };
+
+            fdt-2 {
+                description = "tqm5200s-fdt";
+                data = /incbin/("./tqm5200s.dtb");
+                type = "flat_dt";
+                arch = "ppc";
+                compression = "none";
+                load = <00700000>;
+                hash-1 {
+                    algo = "sha1";
+                };
+            };
+
+        };
+
+        configurations {
+            default = "config-1";
+
+            config-1 {
+                description = "tqm5200 vanilla-2.6.23 configuration";
+                kernel = "kernel-1";
+                ramdisk = "ramdisk-1";
+                fdt = "fdt-1";
+            };
+
+            config-2 {
+                description = "tqm5200s denx-2.6.23 configuration";
+                kernel = "kernel-2";
+                ramdisk = "ramdisk-1";
+                fdt = "fdt-2";
+            };
+
+            config-3 {
+                description = "tqm5200s denx-2.4.25 configuration";
+                kernel = "kernel-3";
+                ramdisk = "ramdisk-2";
+            };
+        };
+    };
diff --git a/doc/usage/fit/multi_spl.rst b/doc/usage/fit/multi_spl.rst
new file mode 100644
index 0000000000..74b6f865ab
--- /dev/null
+++ b/doc/usage/fit/multi_spl.rst
@@ -0,0 +1,101 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Multiple images for SPL
+=======================
+
+(Bogus) example FIT image description file demonstrating the usage
+of multiple images loaded by the SPL.
+Several binaries will be loaded at their respective load addresses.
+
+For booting U-Boot, "firmware" is searched first. If not found, "loadables"
+is used to identify images to be loaded into memory. If falcon boot is
+enabled, "kernel" is searched first. If not found, it falls back to the
+same flow as booting U-Boot. Changing image type will result skipping
+specific image.
+
+Finally the one image specifying an entry point will be entered by the SPL.
+
+::
+
+    /dts-v1/;
+
+    / {
+        description = "multiple firmware blobs and U-Boot, loaded by SPL";
+        #address-cells = <0x1>;
+
+        images {
+
+            uboot {
+                description = "U-Boot (64-bit)";
+                type = "standalone";
+                arch = "arm64";
+                compression = "none";
+                load = <0x4a000000>;
+            };
+
+            atf {
+                description = "ARM Trusted Firmware";
+                type = "firmware";
+                arch = "arm64";
+                compression = "none";
+                load = <0x18000>;
+                entry = <0x18000>;
+            };
+
+            mgmt-firmware {
+                description = "arisc management processor firmware";
+                type = "firmware";
+                arch = "or1k";
+                compression = "none";
+                load = <0x40000>;
+            };
+
+            fdt-1 {
+                description = "Pine64+ DT";
+                type = "flat_dt";
+                compression = "none";
+                load = <0x4fa00000>;
+                arch = "arm64";
+            };
+
+            fdt-2 {
+                description = "Pine64 DT";
+                type = "flat_dt";
+                compression = "none";
+                load = <0x4fa00000>;
+                arch = "arm64";
+            };
+
+            kernel {
+                description = "4.7-rc5 kernel";
+                type = "kernel";
+                compression = "none";
+                load = <0x40080000>;
+                arch = "arm64";
+            };
+
+            initrd {
+                description = "Debian installer initrd";
+                type = "ramdisk";
+                compression = "none";
+                load = <0x4fe00000>;
+                arch = "arm64";
+            };
+        };
+
+        configurations {
+            default = "config-1";
+
+            config-1 {
+                description = "sun50i-a64-pine64-plus";
+                loadables = "uboot", "atf", "kernel", "initrd";
+                fdt = "fdt-1";
+            };
+
+            config-2 {
+                description = "sun50i-a64-pine64";
+                loadables = "uboot", "atf", "mgmt-firmware";
+                fdt = "fdt-2";
+            };
+        };
+    };
diff --git a/doc/usage/fit/overlay-fdt-boot.rst b/doc/usage/fit/overlay-fdt-boot.rst
new file mode 100644
index 0000000000..a7db1a37f7
--- /dev/null
+++ b/doc/usage/fit/overlay-fdt-boot.rst
@@ -0,0 +1,227 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot FDT Overlay FIT usage
+============================
+
+Introduction
+------------
+
+In many cases it is desirable to have a single FIT image support a multitude
+of similar boards and their expansion options. The same kernel on DT enabled
+platforms can support this easily enough by providing a DT blob upon boot
+that matches the desired configuration.
+
+This document focuses on specifically using overlays as part of a FIT image.
+General information regarding overlays including its syntax and building it
+can be found in doc/README.fdt-overlays
+
+Configuration without overlays
+------------------------------
+
+Take a hypothetical board named 'foo' where there are different supported
+revisions, reva and revb. Assume that both board revisions can use add a bar
+add-on board, while only the revb board can use a baz add-on board.
+
+Without using overlays the configuration would be as follows for every case::
+
+	/dts-v1/;
+	/ {
+	    images {
+	    kernel {
+		data = /incbin/("./zImage");
+		type = "kernel";
+		arch = "arm";
+		os = "linux";
+		load = <0x82000000>;
+		entry = <0x82000000>;
+	    };
+	    fdt-1 {
+		data = /incbin/("./foo-reva.dtb");
+		type = "flat_dt";
+		arch = "arm";
+	    };
+	    fdt-2 {
+		data = /incbin/("./foo-revb.dtb");
+		type = "flat_dt";
+		arch = "arm";
+	    };
+	    fdt-3 {
+		data = /incbin/("./foo-reva-bar.dtb");
+		type = "flat_dt";
+		arch = "arm";
+	    };
+	    fdt-4 {
+		data = /incbin/("./foo-revb-bar.dtb");
+		type = "flat_dt";
+		arch = "arm";
+	    };
+	    fdt-5 {
+		data = /incbin/("./foo-revb-baz.dtb");
+		type = "flat_dt";
+		arch = "arm";
+	    };
+	    fdt-6 {
+		data = /incbin/("./foo-revb-bar-baz.dtb");
+		type = "flat_dt";
+		arch = "arm";
+	    };
+	    };
+
+	    configurations {
+	    default = "foo-reva.dtb;
+	    foo-reva.dtb {
+		kernel = "kernel";
+		fdt = "fdt-1";
+	    };
+	    foo-revb.dtb {
+		kernel = "kernel";
+		fdt = "fdt-2";
+	    };
+	    foo-reva-bar.dtb {
+		kernel = "kernel";
+		fdt = "fdt-3";
+	    };
+	    foo-revb-bar.dtb {
+		kernel = "kernel";
+		fdt = "fdt-4";
+	    };
+	    foo-revb-baz.dtb {
+		kernel = "kernel";
+		fdt = "fdt-5";
+	    };
+	    foo-revb-bar-baz.dtb {
+		kernel = "kernel";
+		fdt = "fdt-6";
+	    };
+	    };
+	};
+
+Note the blob needs to be compiled for each case and the combinatorial explosion of
+configurations. A typical device tree blob is in the low hunderds of kbytes so a
+multitude of configuration grows the image quite a bit.
+
+Booting this image is done by using::
+
+    # bootm <addr>#<config>
+
+Where config is one of::
+
+    foo-reva.dtb, foo-revb.dtb, foo-reva-bar.dtb, foo-revb-bar.dtb,
+    foo-revb-baz.dtb, foo-revb-bar-baz.dtb
+
+This selects the DTB to use when booting.
+
+Configuration using overlays
+----------------------------
+
+Device tree overlays can be applied to a base DT and result in the same blob
+being passed to the booting kernel. This saves on space and avoid the combinatorial
+explosion problem::
+
+    /dts-v1/;
+    / {
+        images {
+            kernel {
+                data = /incbin/("./zImage");
+                type = "kernel";
+                arch = "arm";
+                os = "linux";
+                load = <0x82000000>;
+                entry = <0x82000000>;
+            };
+            fdt-1 {
+                data = /incbin/("./foo.dtb");
+                type = "flat_dt";
+                arch = "arm";
+                load = <0x87f00000>;
+            };
+            fdt-2 {
+                data = /incbin/("./reva.dtbo");
+                type = "flat_dt";
+                arch = "arm";
+                load = <0x87fc0000>;
+            };
+            fdt-3 {
+                data = /incbin/("./revb.dtbo");
+                type = "flat_dt";
+                arch = "arm";
+                load = <0x87fc0000>;
+            };
+            fdt-4 {
+                data = /incbin/("./bar.dtbo");
+                type = "flat_dt";
+                arch = "arm";
+                load = <0x87fc0000>;
+            };
+            fdt-5 {
+                data = /incbin/("./baz.dtbo");
+                type = "flat_dt";
+                arch = "arm";
+                load = <0x87fc0000>;
+            };
+        };
+
+        configurations {
+            default = "foo-reva.dtb;
+            foo-reva.dtb {
+                kernel = "kernel";
+                fdt = "fdt-1", "fdt-2";
+            };
+            foo-revb.dtb {
+                kernel = "kernel";
+                fdt = "fdt-1", "fdt-3";
+            };
+            foo-reva-bar.dtb {
+                kernel = "kernel";
+                fdt = "fdt-1", "fdt-2", "fdt-4";
+            };
+            foo-revb-bar.dtb {
+                kernel = "kernel";
+                fdt = "fdt-1", "fdt-3", "fdt-4";
+            };
+            foo-revb-baz.dtb {
+                kernel = "kernel";
+                fdt = "fdt-1", "fdt-3", "fdt-5";
+            };
+            foo-revb-bar-baz.dtb {
+                kernel = "kernel";
+                fdt = "fdt-1", "fdt-3", "fdt-4", "fdt-5";
+            };
+            bar {
+                fdt = "fdt-4";
+            };
+            baz {
+                fdt = "fdt-5";
+            };
+        };
+    };
+
+Booting this image is exactly the same as the non-overlay example.
+u-boot will retrieve the base blob and apply the overlays in sequence as
+they are declared in the configuration.
+
+Note the minimum amount of different DT blobs, as well as the requirement for
+the DT blobs to have a load address; the overlay application requires the blobs
+to be writeable.
+
+Configuration using overlays and feature selection
+--------------------------------------------------
+
+Although the configuration in the previous section works is a bit inflexible
+since it requires all possible configuration options to be laid out before
+hand in the FIT image. For the add-on boards the extra config selection method
+might make sense.
+
+Note the two bar & baz configuration nodes. To boot a reva board with
+the bar add-on board enabled simply use::
+
+    => bootm <addr>#foo-reva.dtb#bar
+
+While booting a revb with bar and baz is as follows::
+
+    => bootm <addr>#foo-revb.dtb#bar#baz
+
+The limitation for a feature selection configuration node is that a single
+fdt option is currently supported.
+
+.. sectionauthor:: Pantelis Antoniou <pantelis.antoniou@konsulko.com>, 12/6/2017
diff --git a/doc/usage/fit/sec_firmware_ppa.rst b/doc/usage/fit/sec_firmware_ppa.rst
new file mode 100644
index 0000000000..4cb292cb4e
--- /dev/null
+++ b/doc/usage/fit/sec_firmware_ppa.rst
@@ -0,0 +1,54 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+SEC Firmware and multiple loadable images
+=========================================
+
+Example FIT image description file demonstrating the usage
+of SEC Firmware and multiple loadable images loaded by U-Boot.
+For booting PPA (SEC Firmware), "firmware" is searched and loaded.
+
+Multiple binaries will be loaded as "loadables" (if present) at their
+respective load offsets from firmware image address.
+
+::
+
+    /dts-v1/;
+
+    /{
+        description = "PPA Firmware";
+        #address-cells = <1>;
+        images {
+            firmware@1 {
+                description = "PPA Firmware: <version>";
+                data = /incbin/("../obj/monitor.bin");
+                type = "firmware";
+                arch = "arm64";
+                compression = "none";
+            };
+            trustedOS@1 {
+                description = "Trusted OS";
+                data = /incbin/("../../tee.bin");
+                type = "OS";
+                arch = "arm64";
+                compression = "none";
+                load = <0x00200000>;
+            };
+            fuse_scr {
+                description = "Fuse Script";
+                data = /incbin/("../../fuse_scr.bin");
+                type = "firmware";
+                arch = "arm64";
+                compression = "none";
+                load = <0x00180000>;
+            };
+        };
+
+        configurations {
+            default = "config-1";
+            config-1 {
+                description = "PPA Secure firmware";
+                firmware = "firmware@1";
+                loadables = "trustedOS@1", "fuse_scr";
+            };
+        };
+    };
diff --git a/doc/usage/fit/sign-configs.rst b/doc/usage/fit/sign-configs.rst
new file mode 100644
index 0000000000..6a3df8f2c5
--- /dev/null
+++ b/doc/usage/fit/sign-configs.rst
@@ -0,0 +1,52 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Signed configurations
+=====================
+
+::
+
+    /dts-v1/;
+
+    / {
+        description = "Chrome OS kernel image with one or more FDT blobs";
+        #address-cells = <1>;
+
+        images {
+            kernel {
+                data = /incbin/("test-kernel.bin");
+                type = "kernel_noload";
+                arch = "sandbox";
+                os = "linux";
+                compression = "lzo";
+                load = <0x4>;
+                entry = <0x8>;
+                kernel-version = <1>;
+                hash-1 {
+                    algo = "sha1";
+                };
+            };
+            fdt-1 {
+                description = "snow";
+                data = /incbin/("sandbox-kernel.dtb");
+                type = "flat_dt";
+                arch = "sandbox";
+                compression = "none";
+                fdt-version = <1>;
+                hash-1 {
+                    algo = "sha1";
+                };
+            };
+        };
+        configurations {
+            default = "conf-1";
+            conf-1 {
+                kernel = "kernel";
+                fdt = "fdt-1";
+                signature {
+                    algo = "sha1,rsa2048";
+                    key-name-hint = "dev";
+                    sign-images = "fdt", "kernel";
+                };
+            };
+        };
+    };
diff --git a/doc/usage/fit/sign-images.rst b/doc/usage/fit/sign-images.rst
new file mode 100644
index 0000000000..7d54d702c9
--- /dev/null
+++ b/doc/usage/fit/sign-images.rst
@@ -0,0 +1,49 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Signed Images
+=============
+
+::
+
+    /dts-v1/;
+
+    / {
+        description = "Chrome OS kernel image with one or more FDT blobs";
+        #address-cells = <1>;
+
+        images {
+            kernel {
+                data = /incbin/("test-kernel.bin");
+                type = "kernel_noload";
+                arch = "sandbox";
+                os = "linux";
+                compression = "none";
+                load = <0x4>;
+                entry = <0x8>;
+                kernel-version = <1>;
+                signature {
+                    algo = "sha1,rsa2048";
+                    key-name-hint = "dev";
+                };
+            };
+            fdt-1 {
+                description = "snow";
+                data = /incbin/("sandbox-kernel.dtb");
+                type = "flat_dt";
+                arch = "sandbox";
+                compression = "none";
+                fdt-version = <1>;
+                signature {
+                    algo = "sha1,rsa2048";
+                    key-name-hint = "dev";
+                };
+            };
+        };
+        configurations {
+            default = "conf-1";
+            conf-1 {
+                kernel = "kernel";
+                fdt = "fdt-1";
+            };
+        };
+    };
diff --git a/doc/usage/fit/signature.rst b/doc/usage/fit/signature.rst
new file mode 100644
index 0000000000..0804bffd1e
--- /dev/null
+++ b/doc/usage/fit/signature.rst
@@ -0,0 +1,696 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot FIT Signature Verification
+=================================
+
+Introduction
+------------
+
+FIT supports hashing of images so that these hashes can be checked on
+loading. This protects against corruption of the image. However it does not
+prevent the substitution of one image for another.
+
+The signature feature allows the hash to be signed with a private key such
+that it can be verified using a public key later. Provided that the private
+key is kept secret and the public key is stored in a non-volatile place,
+any image can be verified in this way.
+
+See verified-boot.txt for more general information on verified boot.
+
+
+Concepts
+--------
+
+Some familiarity with public key cryptography is assumed in this section.
+
+The procedure for signing is as follows:
+
+   - hash an image in the FIT
+   - sign the hash with a private key to produce a signature
+   - store the resulting signature in the FIT
+
+The procedure for verification is:
+
+   - read the FIT
+   - obtain the public key
+   - extract the signature from the FIT
+   - hash the image from the FIT
+   - verify (with the public key) that the extracted signature matches the
+     hash
+
+The signing is generally performed by mkimage, as part of making a firmware
+image for the device. The verification is normally done in U-Boot on the
+device.
+
+
+Algorithms
+----------
+In principle any suitable algorithm can be used to sign and verify a hash.
+U-Boot supports a few hashing and verification algorithms. See below for
+details.
+
+While it is acceptable to bring in large cryptographic libraries such as
+openssl on the host side (e.g. mkimage), it is not desirable for U-Boot.
+For the run-time verification side, it is important to keep code and data
+size as small as possible.
+
+For this reason the RSA image verification uses pre-processed public keys
+which can be used with a very small amount of code - just some extraction
+of data from the FDT and exponentiation mod n. Code size impact is a little
+under 5KB on Tegra Seaboard, for example.
+
+It is relatively straightforward to add new algorithms if required. If
+another RSA variant is needed, then it can be added with the
+U_BOOT_CRYPTO_ALGO() macro. If another algorithm is needed (such as DSA) then
+it can be placed in a directory alongside lib/rsa/, and its functions added
+using U_BOOT_CRYPTO_ALGO().
+
+
+Creating an RSA key pair and certificate
+----------------------------------------
+To create a new public/private key pair, size 2048 bits::
+
+    $ openssl genpkey -algorithm RSA -out keys/dev.key \
+        -pkeyopt rsa_keygen_bits:2048 -pkeyopt rsa_keygen_pubexp:65537
+
+To create a certificate for this containing the public key::
+
+    $ openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt
+
+If you like you can look at the public key also::
+
+    $ openssl rsa -in keys/dev.key -pubout
+
+
+Public Key Storage
+------------------
+In order to verify an image that has been signed with a public key we need to
+have a trusted public key. This cannot be stored in the signed image, since
+it would be easy to alter. For this implementation we choose to store the
+public key in U-Boot's control FDT (using CONFIG_OF_CONTROL).
+
+Public keys should be stored as sub-nodes in a /signature node. Required
+properties are:
+
+algo
+    Algorithm name (e.g. "sha1,rsa2048" or "sha256,ecdsa256")
+
+Optional properties are:
+
+key-name-hint
+    Name of key used for signing. This is only a hint since it
+    is possible for the name to be changed. Verification can proceed by checking
+    all available signing keys until one matches.
+
+required
+    If present this indicates that the key must be verified for the
+    image / configuration to be considered valid. Only required keys are
+    normally verified by the FIT image booting algorithm. Valid values are
+    "image" to force verification of all images, and "conf" to force verification
+    of the selected configuration (which then relies on hashes in the images to
+    verify those).
+
+Each signing algorithm has its own additional properties.
+
+For RSA the following are mandatory:
+
+rsa,num-bits
+    Number of key bits (e.g. 2048)
+
+rsa,modulus
+    Modulus (N) as a big-endian multi-word integer
+
+rsa,exponent
+    Public exponent (E) as a 64 bit unsigned integer
+
+rsa,r-squared
+    (2^num-bits)^2 as a big-endian multi-word integer
+
+rsa,n0-inverse
+    -1 / modulus[0] mod 2^32
+
+For ECDSA the following are mandatory:
+
+ecdsa,curve
+    Name of ECDSA curve (e.g. "prime256v1")
+
+ecdsa,x-point
+    Public key X coordinate as a big-endian multi-word integer
+
+ecdsa,y-point
+    Public key Y coordinate as a big-endian multi-word integer
+
+These parameters can be added to a binary device tree using parameter -K of the
+mkimage command::
+
+    tools/mkimage -f fit.its -K control.dtb -k keys -r image.fit
+
+Here is an example of a generated device tree node::
+
+    signature {
+        key-dev {
+            required = "conf";
+            algo = "sha256,rsa2048";
+            rsa,r-squared = <0xb76d1acf 0xa1763ca5 0xeb2f126
+                    0x742edc80 0xd3f42177 0x9741d9d9
+                    0x35bb476e 0xff41c718 0xd3801430
+                    0xf22537cb 0xa7e79960 0xae32a043
+                    0x7da1427a 0x341d6492 0x3c2762f5
+                    0xaac04726 0x5b262d96 0xf984e86d
+                    0xb99443c7 0x17080c33 0x940f6892
+                    0xd57a95d1 0x6ea7b691 0xc5038fa8
+                    0x6bb48a6e 0x73f1b1ea 0x37160841
+                    0xe05715ce 0xa7c45bbd 0x690d82d5
+                    0x99c2454c 0x6ff117b3 0xd830683b
+                    0x3f81c9cf 0x1ca38a91 0x0c3392e4
+                    0xd817c625 0x7b8e9a24 0x175b89ea
+                    0xad79f3dc 0x4d50d7b4 0x9d4e90f8
+                    0xad9e2939 0xc165d6a4 0x0ada7e1b
+                    0xfb1bf495 0xfc3131c2 0xb8c6e604
+                    0xc2761124 0xf63de4a6 0x0e9565f9
+                    0xc8e53761 0x7e7a37a5 0xe99dcdae
+                    0x9aff7e1e 0xbd44b13d 0x6b0e6aa4
+                    0x038907e4 0x8e0d6850 0xef51bc20
+                    0xf73c94af 0x88bea7b1 0xcbbb1b30
+                    0xd024b7f3>;
+            rsa,modulus = <0xc0711d6cb 0x9e86db7f 0x45986dbe
+                       0x023f1e8c9 0xe1a4c4d0 0x8a0dfdc9
+                       0x023ba0c48 0x06815f6a 0x5caa0654
+                       0x07078c4b7 0x3d154853 0x40729023
+                       0x0b007c8fe 0x5a3647e5 0x23b41e20
+                       0x024720591 0x66915305 0x0e0b29b0
+                       0x0de2ad30d 0x8589430f 0xb1590325
+                       0x0fb9f5d5e 0x9eba752a 0xd88e6de9
+                       0x056b3dcc6 0x9a6b8e61 0x6784f61f
+                       0x000f39c21 0x5eec6b33 0xd78e4f78
+                       0x0921a305f 0xaa2cc27e 0x1ca917af
+                       0x06e1134f4 0xd48cac77 0x4e914d07
+                       0x0f707aa5a 0x0d141f41 0x84677f1d
+                       0x0ad47a049 0x028aedb6 0xd5536fcf
+                       0x03fef1e4f 0x133a03d2 0xfd7a750a
+                       0x0f9159732 0xd207812e 0x6a807375
+                       0x06434230d 0xc8e22dad 0x9f29b3d6
+                       0x07c44ac2b 0xfa2aad88 0xe2429504
+                       0x041febd41 0x85d0d142 0x7b194d65
+                       0x06e5d55ea 0x41116961 0xf3181dde
+                       0x068bf5fbc 0x3dd82047 0x00ee647e
+                       0x0d7a44ab3>;
+            rsa,exponent = <0x00 0x10001>;
+            rsa,n0-inverse = <0xb3928b85>;
+            rsa,num-bits = <0x800>;
+            key-name-hint = "dev";
+        };
+    };
+
+
+Signed Configurations
+---------------------
+While signing images is useful, it does not provide complete protection
+against several types of attack. For example, it is possible to create a
+FIT with the same signed images, but with the configuration changed such
+that a different one is selected (mix and match attack). It is also possible
+to substitute a signed image from an older FIT version into a newer FIT
+(roll-back attack).
+
+As an example, consider this FIT::
+
+    / {
+        images {
+            kernel-1 {
+                data = <data for kernel1>
+                signature-1 {
+                    algo = "sha1,rsa2048";
+                    value = <...kernel signature 1...>
+                };
+            };
+            kernel-2 {
+                data = <data for kernel2>
+                signature-1 {
+                    algo = "sha1,rsa2048";
+                    value = <...kernel signature 2...>
+                };
+            };
+            fdt-1 {
+                data = <data for fdt1>;
+                signature-1 {
+                    algo = "sha1,rsa2048";
+                    value = <...fdt signature 1...>
+                };
+            };
+            fdt-2 {
+                data = <data for fdt2>;
+                signature-1 {
+                    algo = "sha1,rsa2048";
+                    value = <...fdt signature 2...>
+                };
+            };
+        };
+        configurations {
+            default = "conf-1";
+            conf-1 {
+                kernel = "kernel-1";
+                fdt = "fdt-1";
+            };
+            conf-2 {
+                kernel = "kernel-2";
+                fdt = "fdt-2";
+            };
+        };
+    };
+
+Since both kernels are signed it is easy for an attacker to add a new
+configuration 3 with kernel 1 and fdt 2::
+
+    configurations {
+        default = "conf-1";
+        conf-1 {
+            kernel = "kernel-1";
+            fdt = "fdt-1";
+        };
+        conf-2 {
+            kernel = "kernel-2";
+            fdt = "fdt-2";
+        };
+        conf-3 {
+            kernel = "kernel-1";
+            fdt = "fdt-2";
+        };
+    };
+
+With signed images, nothing protects against this. Whether it gains an
+advantage for the attacker is debatable, but it is not secure.
+
+To solve this problem, we support signed configurations. In this case it
+is the configurations that are signed, not the image. Each image has its
+own hash, and we include the hash in the configuration signature.
+
+So the above example is adjusted to look like this::
+
+    / {
+        images {
+            kernel-1 {
+                data = <data for kernel1>
+                hash-1 {
+                    algo = "sha1";
+                    value = <...kernel hash 1...>
+                };
+            };
+            kernel-2 {
+                data = <data for kernel2>
+                hash-1 {
+                    algo = "sha1";
+                    value = <...kernel hash 2...>
+                };
+            };
+            fdt-1 {
+                data = <data for fdt1>;
+                hash-1 {
+                    algo = "sha1";
+                    value = <...fdt hash 1...>
+                };
+            };
+            fdt-2 {
+                data = <data for fdt2>;
+                hash-1 {
+                    algo = "sha1";
+                    value = <...fdt hash 2...>
+                };
+            };
+        };
+        configurations {
+            default = "conf-1";
+            conf-1 {
+                kernel = "kernel-1";
+                fdt = "fdt-1";
+                signature-1 {
+                    algo = "sha1,rsa2048";
+                    value = <...conf 1 signature...>;
+                };
+            };
+            conf-2 {
+                kernel = "kernel-2";
+                fdt = "fdt-2";
+                signature-1 {
+                    algo = "sha1,rsa2048";
+                    value = <...conf 1 signature...>;
+                };
+            };
+        };
+    };
+
+
+You can see that we have added hashes for all images (since they are no
+longer signed), and a signature to each configuration. In the above example,
+mkimage will sign configurations/conf-1, the kernel and fdt that are
+pointed to by the configuration (/images/kernel-1, /images/kernel-1/hash-1,
+/images/fdt-1, /images/fdt-1/hash-1) and the root structure of the image
+(so that it isn't possible to add or remove root nodes). The signature is
+written into /configurations/conf-1/signature-1/value. It can easily be
+verified later even if the FIT has been signed with other keys in the
+meantime.
+
+
+Details
+-------
+The signature node contains a property ('hashed-nodes') which lists all the
+nodes that the signature was made over.  The image is walked in order and each
+tag processed as follows:
+
+DTB_BEGIN_NODE
+    The tag and the following name are included in the signature
+    if the node or its parent are present in 'hashed-nodes'
+
+DTB_END_NODE
+    The tag is included in the signature if the node or its parent
+    are present in 'hashed-nodes'
+
+DTB_PROPERTY
+    The tag, the length word, the offset in the string table, and
+    the data are all included if the current node is present in 'hashed-nodes'
+    and the property name is not 'data'.
+
+DTB_END
+    The tag is always included in the signature.
+
+DTB_NOP
+    The tag is included in the signature if the current node is present
+    in 'hashed-nodes'
+
+In addition, the signature contains a property 'hashed-strings' which contains
+the offset and length in the string table of the strings that are to be
+included in the signature (this is done last).
+
+IMPORTANT:  To verify the signature outside u-boot, it is vital to not only
+calculate the hash of the image and verify the signature with that, but also to
+calculate the hashes of the kernel, fdt, and ramdisk images and check those
+match the hash values in the corresponding 'hash*' subnodes.
+
+
+Verification
+------------
+FITs are verified when loaded. After the configuration is selected a list
+of required images is produced. If there are 'required' public keys, then
+each image must be verified against those keys. This means that every image
+that might be used by the target needs to be signed with 'required' keys.
+
+This happens automatically as part of a bootm command when FITs are used.
+
+For Signed Configurations, the default verification behavior can be changed by
+the following optional property in /signature node in U-Boot's control FDT.
+
+required-mode
+    Valid values are "any" to allow verified boot to succeed if
+    the selected configuration is signed by any of the 'required' keys, and "all"
+    to allow verified boot to succeed if the selected configuration is signed by
+    all of the 'required' keys.
+
+This property can be added to a binary device tree using fdtput as shown in
+below examples::
+
+    fdtput -t s control.dtb /signature required-mode any
+    fdtput -t s control.dtb /signature required-mode all
+
+
+Enabling FIT Verification
+-------------------------
+In addition to the options to enable FIT itself, the following CONFIGs must
+be enabled:
+
+CONFIG_FIT_SIGNATURE
+    enable signing and verification in FITs
+
+CONFIG_RSA
+    enable RSA algorithm for signing
+
+CONFIG_ECDSA
+    enable ECDSA algorithm for signing
+
+WARNING: When relying on signed FIT images with required signature check
+the legacy image format is default disabled by not defining
+CONFIG_LEGACY_IMAGE_FORMAT
+
+
+Testing
+-------
+
+An easy way to test signing and verification is to use the test script
+provided in test/vboot/vboot_test.sh. This uses sandbox (a special version
+of U-Boot which runs under Linux) to show the operation of a 'bootm'
+command loading and verifying images.
+
+A sample run is show below::
+
+    $ make O=sandbox sandbox_config
+    $ make O=sandbox
+    $ O=sandbox ./test/vboot/vboot_test.sh
+
+
+Simple Verified Boot Test
+-------------------------
+
+Please see :doc:`verified-boot` for more information::
+
+    /home/hs/ids/u-boot/sandbox/tools/mkimage -D -I dts -O dtb -p 2000
+    Build keys
+    do sha1 test
+    Build FIT with signed images
+    Test Verified Boot Run: unsigned signatures:: OK
+    Sign images
+    Test Verified Boot Run: signed images: OK
+    Build FIT with signed configuration
+    Test Verified Boot Run: unsigned config: OK
+    Sign images
+    Test Verified Boot Run: signed config: OK
+    check signed config on the host
+    Signature check OK
+    OK
+    Test Verified Boot Run: signed config: OK
+    Test Verified Boot Run: signed config with bad hash: OK
+    do sha256 test
+    Build FIT with signed images
+    Test Verified Boot Run: unsigned signatures:: OK
+    Sign images
+    Test Verified Boot Run: signed images: OK
+    Build FIT with signed configuration
+    Test Verified Boot Run: unsigned config: OK
+    Sign images
+    Test Verified Boot Run: signed config: OK
+    check signed config on the host
+    Signature check OK
+    OK
+    Test Verified Boot Run: signed config: OK
+    Test Verified Boot Run: signed config with bad hash: OK
+
+    Test passed
+
+
+Software signing: keydir vs keyfile
+-----------------------------------
+
+In the simplest case, signing is done by giving mkimage the 'keyfile'. This is
+the path to a file containing the signing key.
+
+The alternative is to pass the 'keydir' argument. In this case the filename of
+the key is derived from the 'keydir' and the "key-name-hint" property in the
+FIT. In this case the "key-name-hint" property is mandatory, and the key must
+exist in "<keydir>/<key-name-hint>.<ext>" Here the extension "ext" is
+specific to the signing algorithm.
+
+
+Hardware Signing with PKCS#11 or with HSM
+-----------------------------------------
+
+Securely managing private signing keys can challenging, especially when the
+keys are stored on the file system of a computer that is connected to the
+Internet. If an attacker is able to steal the key, they can sign malicious FIT
+images which will appear genuine to your devices.
+
+An alternative solution is to keep your signing key securely stored on hardware
+device like a smartcard, USB token or Hardware Security Module (HSM) and have
+them perform the signing. PKCS#11 is standard for interfacing with these crypto
+device.
+
+Requirements:
+    - Smartcard/USB token/HSM which can work with some openssl engine
+    - openssl
+
+For pkcs11 engine usage:
+    - libp11 (provides pkcs11 engine)
+    - p11-kit (recommended to simplify setup)
+    - opensc (for smartcards and smartcard like USB devices)
+    - gnutls (recommended for key generation, p11tool)
+
+For generic HSMs respective openssl engine must be installed and locateable by
+openssl. This may require setting up LD_LIBRARY_PATH if engine is not installed
+to openssl's default search paths.
+
+PKCS11 engine support forms "key id" based on "keydir" and with
+"key-name-hint". "key-name-hint" is used as "object" name (if not defined in
+keydir). "keydir" (if defined) is used to define (prefix for) which PKCS11 source
+is being used for lookup up for the key.
+
+PKCS11 engine key ids
+    "pkcs11:<keydir>;object=<key-name-hint>;type=<public|private>"
+
+or, if keydir contains "object="
+    "pkcs11:<keydir>;type=<public|private>"
+
+or
+    "pkcs11:object=<key-name-hint>;type=<public|private>",
+
+Generic HSM engine support forms "key id" based on "keydir" and with
+"key-name-hint". If "keydir" is specified for mkimage it is used as a prefix in
+"key id" and is appended with "key-name-hint".
+
+Generic engine key ids:
+    "<keydir><key-name-hint>"
+
+or
+    "<  key-name-hint>"
+
+In order to set the pin in the HSM, an environment variable "MKIMAGE_SIGN_PIN"
+can be specified.
+
+The following examples use the Nitrokey Pro using pkcs11 engine. Instructions
+for other devices may vary.
+
+Notes on pkcs11 engine setup:
+
+Make sure p11-kit, opensc are installed and that p11-kit is setup to use opensc.
+/usr/share/p11-kit/modules/opensc.module should be present on your system.
+
+
+Generating Keys On the Nitrokey::
+
+    $ gpg --card-edit
+
+    Reader ...........: Nitrokey Nitrokey Pro (xxxxxxxx0000000000000000) 00 00
+    Application ID ...: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    Version ..........: 2.1
+    Manufacturer .....: ZeitControl
+    Serial number ....: xxxxxxxx
+    Name of cardholder: [not set]
+    Language prefs ...: de
+    Sex ..............: unspecified
+    URL of public key : [not set]
+    Login data .......: [not set]
+    Signature PIN ....: forced
+    Key attributes ...: rsa2048 rsa2048 rsa2048
+    Max. PIN lengths .: 32 32 32
+    PIN retry counter : 3 0 3
+    Signature counter : 0
+    Signature key ....: [none]
+    Encryption key....: [none]
+    Authentication key: [none]
+    General key info..: [none]
+
+    gpg/card> generate
+    Make off-card backup of encryption key? (Y/n) n
+
+    Please note that the factory settings of the PINs are
+    PIN = '123456' Admin PIN = '12345678'
+    You should change them using the command --change-pin
+
+    What keysize do you want for the Signature key? (2048) 4096
+    The card will now be re-configured to generate a key of 4096 bits
+    Note: There is no guarantee that the card supports the requested size.
+    If the key generation does not succeed, please check the
+    documentation of your card to see what sizes are allowed.
+    What keysize do you want for the Encryption key? (2048) 4096
+    The card will now be re-configured to generate a key of 4096 bits
+    What keysize do you want for the Authentication key? (2048) 4096
+    The card will now be re-configured to generate a key of 4096 bits
+    Please specify how long the key should be valid.
+    0 = key does not expire
+    <n> = key expires in n days
+    <n>w = key expires in n weeks
+    <n>m = key expires in n months
+    <n>y = key expires in n years
+    Key is valid for? (0)
+    Key does not expire at all
+    Is this correct? (y/N) y
+
+    GnuPG needs to construct a user ID to identify your key.
+
+    Real name: John Doe
+    Email address: john.doe@email.com
+    Comment:
+    You selected this USER-ID:
+    "John Doe <john.doe@email.com>"
+
+    Change (N)ame, (C)omment, (E)mail or (O)kay/(Q)uit? o
+
+
+Using p11tool to get the token URL:
+
+Depending on system configuration, gpg-agent may need to be killed first::
+
+    $ p11tool --provider /usr/lib/opensc-pkcs11.so --list-tokens
+    Token 0:
+    URL: pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29
+    Label: OpenPGP card (User PIN (sig))
+    Type: Hardware token
+    Manufacturer: ZeitControl
+    Model: PKCS#15 emulated
+    Serial: 000xxxxxxxxx
+    Module: (null)
+
+
+    Token 1:
+    URL: pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%29
+    Label: OpenPGP card (User PIN)
+    Type: Hardware token
+    Manufacturer: ZeitControl
+    Model: PKCS#15 emulated
+    Serial: 000xxxxxxxxx
+    Module: (null)
+
+Use the portion of the signature token URL after "pkcs11:" as the keydir argument (-k) to mkimage below.
+
+
+Use the URL of the token to list the private keys::
+
+    $ p11tool --login --provider /usr/lib/opensc-pkcs11.so --list-privkeys \
+    "pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29"
+    Token 'OpenPGP card (User PIN (sig))' with URL 'pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29' requires user PIN
+    Enter PIN:
+    Object 0:
+    URL: pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29;id=%01;object=Signature%20key;type=private
+    Type: Private key
+    Label: Signature key
+    Flags: CKA_PRIVATE; CKA_NEVER_EXTRACTABLE; CKA_SENSITIVE;
+    ID: 01
+
+Use the label, in this case "Signature key" as the key-name-hint in your FIT.
+
+Create the fitImage::
+
+    $ ./tools/mkimage -f fit-image.its fitImage
+
+
+Sign the fitImage with the hardware key::
+
+    $ ./tools/mkimage -F -k \
+    "model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29" \
+    -K u-boot.dtb -N pkcs11 -r fitImage
+
+
+Future Work
+-----------
+
+- Roll-back protection using a TPM is done using the tpm command. This can
+  be scripted, but we might consider a default way of doing this, built into
+  bootm.
+
+
+Possible Future Work
+--------------------
+
+- More sandbox tests for failure modes
+- Passwords for keys/certificates
+- Perhaps implement OAEP
+- Enhance bootm to permit scripted signature verification (so that a script
+  can verify an image but not actually boot it)
+
+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>, 1-1-13
diff --git a/doc/usage/fit/source_file_format.rst b/doc/usage/fit/source_file_format.rst
new file mode 100644
index 0000000000..b2b1e42bd7
--- /dev/null
+++ b/doc/usage/fit/source_file_format.rst
@@ -0,0 +1,684 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Flattened Image Tree (FIT) Format
+=================================
+
+Introduction
+------------
+
+The number of elements playing a role in the kernel booting process has
+increased over time and now typically includes the devicetree, kernel image and
+possibly a ramdisk image. Generally, all must be placed in the system memory and
+booted together.
+
+For firmware images a similar process has taken place, with various binaries
+loaded at different addresses, such as ARM's ATF, OpenSBI, FPGA and U-Boot
+itself.
+
+FIT provides a flexible and extensible format to deal with this complexity. It
+provides support for multiple components. It also supports multiple
+configurations, so that the same FIT can be used to boot multiple boards, with
+some components in common (e.g. kernel) and some specific to that board (e.g.
+devicetree).
+
+Terminology
+~~~~~~~~~~~
+
+This document defines FIT by providing FDT (Flat Device Tree) bindings. These
+describe the final form of the FIT at the moment when it is used. The user
+perspective may be simpler, as some of the properties (like timestamps and
+hashes) are filled in automatically by the U-Boot mkimage tool.
+
+To avoid confusion with the kernel FDT the following naming convention is used:
+
+FIT
+    Flattened Image Tree
+
+FIT is formally a flattened devicetree (in the libfdt meaning), which conforms
+to bindings defined in this document.
+
+.its
+    image tree source
+
+.itb
+    flattened image tree blob
+
+Image-building procedure
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+The following picture shows how the FIT is prepared. Input consists of
+image source file (.its) and a set of data files. Image is created with the
+help of standard U-Boot mkimage tool which in turn uses dtc (device tree
+compiler) to produce image tree blob (.itb). The resulting .itb file is the
+actual binary of a new FIT::
+
+    tqm5200.its
+    +
+    vmlinux.bin.gz     mkimage + dtc               xfer to target
+    eldk-4.2-ramdisk  --------------> tqm5200.itb --------------> boot
+    tqm5200.dtb                          /|\
+                                          |
+                                     'new FIT'
+
+Steps:
+
+#. Create .its file, automatically filled-in properties are omitted
+
+#. Call mkimage tool on a .its file
+
+#. mkimage calls dtc to create .itb image and assures that
+   missing properties are added
+
+#. .itb (new FIT) is uploaded onto the target and used therein
+
+
+Unique identifiers
+~~~~~~~~~~~~~~~~~~
+
+To identify FIT sub-nodes representing images, hashes, configurations (which
+are defined in the following sections), the "unit name" of the given sub-node
+is used as it's identifier as it assures uniqueness without additional
+checking required.
+
+
+External data
+~~~~~~~~~~~~~
+
+FIT is normally built initially with image data in the 'data' property of each
+image node. It is also possible for this data to reside outside the FIT itself.
+This allows the 'FDT' part of the FIT to be quite small, so that it can be
+loaded and scanned without loading a large amount of data. Then when an image is
+needed it can be loaded from an external source.
+
+External FITs use 'data-offset' or 'data-position' instead of 'data'.
+
+The mkimage tool can convert a FIT to use external data using the `-E` argument,
+optionally using `-p` to specific a fixed position.
+
+It is often desirable to align each image to a block size or cache-line size
+(e.g. 512 bytes), so that there is no need to copy it to an aligned address when
+reading the image data. The mkimage tool provides a `-B` argument to support
+this.
+
+Root-node properties
+--------------------
+
+The root node of the FIT should have the following layout::
+
+    / o image-tree
+        |- description = "image description"
+        |- timestamp = <12399321>
+        |- #address-cells = <1>
+        |
+        o images
+        | |
+        | o image-1 {...}
+        | o image-2 {...}
+        | ...
+        |
+        o configurations
+          |- default = "conf-1"
+          |
+          o conf-1 {...}
+          o conf-2 {...}
+          ...
+
+Optional property
+~~~~~~~~~~~~~~~~~
+
+description
+    Textual description of the FIT
+
+Mandatory property
+~~~~~~~~~~~~~~~~~~
+
+timestamp
+    Last image modification time being counted in seconds since
+    1970-01-01 00:00:00 - to be automatically calculated by mkimage tool.
+
+Conditionally mandatory property
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+#address-cells
+    Number of 32bit cells required to represent entry and
+    load addresses supplied within sub-image nodes. May be omitted when no
+    entry or load addresses are used.
+
+Mandatory nodes
+~~~~~~~~~~~~~~~
+
+images
+    This node contains a set of sub-nodes, each of them representing
+    single component sub-image (like kernel, ramdisk, etc.). At least one
+    sub-image is required.
+
+configurations
+    Contains a set of available configuration nodes and
+    defines a default configuration.
+
+
+'/images' node
+--------------
+
+This node is a container node for component sub-image nodes. Each sub-node of
+the '/images' node should have the following layout::
+
+    o image-1
+        |- description = "component sub-image description"
+        |- data = /incbin/("path/to/data/file.bin")
+        |- type = "sub-image type name"
+        |- arch = "ARCH name"
+        |- os = "OS name"
+        |- compression = "compression name"
+        |- load = <00000000>
+        |- entry = <00000000>
+        |
+        o hash-1 {...}
+        o hash-2 {...}
+        ...
+
+Mandatory properties
+~~~~~~~~~~~~~~~~~~~~
+
+description
+    Textual description of the component sub-image
+
+type
+    Name of component sub-image type. Supported types are:
+
+    ====================  ==================
+    Sub-image type        Meaning
+    ====================  ==================
+    invalid               Invalid Image
+    aisimage              Davinci AIS image
+    atmelimage            ATMEL ROM-Boot Image
+    copro                 Coprocessor Image}
+    fdt_legacy            legacy Image with Flat Device Tree
+    filesystem            Filesystem Image
+    firmware              Firmware
+    firmware_ivt          Firmware with HABv4 IVT }
+    flat_dt               Flat Device Tree
+    fpga                  FPGA Image }
+    gpimage               TI Keystone SPL Image
+    imx8image             NXP i.MX8 Boot Image
+    imx8mimage            NXP i.MX8M Boot Image
+    imximage              Freescale i.MX Boot Image
+    kernel                Kernel Image
+    kernel_noload         Kernel Image (no loading done)
+    kwbimage              Kirkwood Boot Image
+    lpc32xximage          LPC32XX Boot Image
+    mtk_image             MediaTek BootROM loadable Image }
+    multi                 Multi-File Image
+    mxsimage              Freescale MXS Boot Image
+    omapimage             TI OMAP SPL With GP CH
+    pblimage              Freescale PBL Boot Image
+    pmmc                  TI Power Management Micro-Controller Firmware
+    ramdisk               RAMDisk Image
+    rkimage               Rockchip Boot Image }
+    rksd                  Rockchip SD Boot Image }
+    rkspi                 Rockchip SPI Boot Image }
+    script                Script
+    socfpgaimage          Altera SoCFPGA CV/AV preloader
+    socfpgaimage_v1       Altera SoCFPGA A10 preloader
+    spkgimage             Renesas SPKG Image }
+    standalone            Standalone Program
+    stm32image            STMicroelectronics STM32 Image }
+    sunxi_egon            Allwinner eGON Boot Image }
+    sunxi_toc0            Allwinner TOC0 Boot Image }
+    tee                   Trusted Execution Environment Image
+    ublimage              Davinci UBL image
+    vybridimage           Vybrid Boot Image
+    x86_setup             x86 setup.bin
+    zynqimage             Xilinx Zynq Boot Image }
+    zynqmpbif             Xilinx ZynqMP Boot Image (bif) }
+    zynqmpimage           Xilinx ZynqMP Boot Image }
+    ====================  ==================
+
+compression
+    Compression used by included data. If no compression is used, the
+    compression property should be set to "none". If the data is compressed but
+    it should not be uncompressed by the loader (e.g. compressed ramdisk), this
+    should also be set to "none".
+
+    Supported compression types are:
+
+    ====================  ==================
+    Compression type      Meaning
+    ====================  ==================
+    none                  uncompressed
+    bzip2                 bzip2 compressed
+    gzip                  gzip compressed
+    lz4                   lz4 compressed
+    lzma                  lzma compressed
+    lzo                   lzo compressed
+    zstd                  zstd compressed
+    ====================  ==================
+
+data-size
+    size of the data in bytes
+
+
+Conditionally mandatory property
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+data
+    Path to the external file which contains this node's binary data. Within
+    the FIT this is the contents of the file. This is mandatory unless
+    external data is used.
+
+data-offset
+    Offset of the data in a separate image store. The image store is placed
+    immediately after the last byte of the device tree binary, aligned to a
+    4-byte boundary. This is mandatory if external data is used, with an offset.
+
+data-position
+    Machine address at which the data is to be found. This is a fixed address
+    not relative to the loading of the FIT. This is mandatory if external data
+    used with a fixed address.
+
+os
+    OS name, mandatory for types "kernel". Valid OS names are:
+
+    ====================  ==================
+    OS name               Meaning
+    ====================  ==================
+    invalid               Invalid OS
+    4_4bsd                4_4BSD
+    arm-trusted-firmware  ARM Trusted Firmware
+    dell                  Dell
+    efi                   EFI Firmware
+    esix                  Esix
+    freebsd               FreeBSD
+    integrity             INTEGRITY
+    irix                  Irix
+    linux                 Linux
+    ncr                   NCR
+    netbsd                NetBSD
+    openbsd               OpenBSD
+    openrtos              OpenRTOS
+    opensbi               RISC-V OpenSBI
+    ose                   Enea OSE
+    plan9                 Plan 9
+    psos                  pSOS
+    qnx                   QNX
+    rtems                 RTEMS
+    sco                   SCO
+    solaris               Solaris
+    svr4                  SVR4
+    tee                   Trusted Execution Environment
+    u-boot                U-Boot
+    vxworks               VxWorks
+    ====================  ==================
+
+arch
+    Architecture name, mandatory for types: "standalone", "kernel",
+    "firmware", "ramdisk" and "fdt". Valid architecture names are:
+
+    ====================  ==================
+    Architecture type     Meaning
+    ====================  ==================
+    invalid               Invalid ARCH
+    alpha                 Alpha
+    arc                   ARC
+    arm64                 AArch64
+    arm                   ARM
+    avr32                 AVR32
+    blackfin              Blackfin
+    ia64                  IA64
+    m68k                  M68K
+    microblaze            MicroBlaze
+    mips64                MIPS 64 Bit
+    mips                  MIPS
+    nds32                 NDS32
+    nios2                 NIOS II
+    or1k                  OpenRISC 1000
+    powerpc               PowerPC
+    ppc                   PowerPC
+    riscv                 RISC-V
+    s390                  IBM S390
+    sandbox               Sandbox
+    sh                    SuperH
+    sparc64               SPARC 64 Bit
+    sparc                 SPARC
+    x86_64                AMD x86_64
+    x86                   Intel x86
+    xtensa                Xtensa
+    ====================  ==================
+
+entry
+    entry point address, address size is determined by
+    '#address-cells' property of the root node.
+    Mandatory for types: "firmware", and "kernel".
+
+load
+    load address, address size is determined by '#address-cells'
+    property of the root node.
+    Mandatory for types: "firmware", and "kernel".
+
+compatible
+    compatible method for loading image.
+    Mandatory for types: "fpga", and images that do not specify a load address.
+    Supported compatible methods:
+
+    ==========================  =========================================
+    Compatible string           Meaning
+    ==========================  =========================================
+    u-boot,fpga-legacy          Generic fpga loading routine.
+    u-boot,zynqmp-fpga-ddrauth  Signed non-encrypted FPGA bitstream for
+                                Xilinx Zynq UltraScale+ (ZymqMP) device.
+    u-boot,zynqmp-fpga-enc      Encrypted FPGA bitstream for Xilinx Zynq
+                                UltraScale+ (ZynqMP) device.
+    ==========================  =========================================
+
+phase
+    U-Boot phase for which the image is intended.
+
+    "spl"
+        image is an SPL image
+
+    "u-boot"
+        image is a U-Boot image
+
+Optional nodes:
+
+hash-1
+    Each hash sub-node represents separate hash or checksum
+    calculated for node's data according to specified algorithm.
+
+signature-1
+    Each signature sub-node represents separate signature
+    calculated for node's data according to specified algorithm.
+
+
+Hash nodes
+----------
+
+::
+
+    o hash-1
+        |- algo = "hash or checksum algorithm name"
+        |- value = [hash or checksum value]
+
+Mandatory properties
+~~~~~~~~~~~~~~~~~~~~
+
+algo
+    Algorithm name. Supported algoriths and their value sizes are:
+
+    ==================== ============ =========================================
+    Sub-image type       Size (bytes) Meaning
+    ==================== ============ =========================================
+    crc16-ccitt          2            Cyclic Redundancy Check 16-bit
+                                      (Consultative Committee for International
+                                      Telegraphy and Telephony)
+    crc32                4            Cyclic Redundancy Check 32-bit
+    md5                  16           Message Digest 5 (MD5)
+    sha1                 20           Secure Hash Algorithm 1 (SHA1)
+    sha256               32           Secure Hash Algorithm 2 (SHA256)
+    sha384               48           Secure Hash Algorithm 2 (SHA384)
+    sha512               64           Secure Hash Algorithm 2 (SHA512)
+    ==================== ============ =========================================
+
+value
+    Actual checksum or hash value.
+
+Image-signature nodes
+---------------------
+
+::
+
+    o signature-1
+        |- algo = "algorithm name"
+        |- key-name-hint = "key name"
+        |- value = [hash or checksum value]
+
+
+Mandatory properties
+~~~~~~~~~~~~~~~~~~~~
+
+_`FIT Algorithm`:
+
+algo
+    Algorithm name. Supported algoriths and their value sizes are shown below.
+    Note that the hash is specified separately from the signing algorithm, so
+    it is possible to mix and match any SHA algorithm with any signing
+    algorithm. The size of the signature relates to the signing algorithm, not
+    the hash, since it is the hash that is signed.
+
+    ==================== ============ =========================================
+    Sub-image type       Size (bytes) Meaning
+    ==================== ============ =========================================
+    sha1,rsa2048         256          SHA1 hash signed with 2048-bit
+                                      Rivest–Shamir–Adleman algorithm
+    sha1,rsa3072         384          SHA1 hash signed with 2048-bit RSA
+    sha1,rsa4096         512          SHA1 hash signed with 2048-bit RSA
+    sha1,ecdsa256        32           SHA1 hash signed with 256-bit  Elliptic
+                                      Curve Digital Signature Algorithm
+    sha256,...
+    sha384,...
+    sha512,...
+    ==================== ============ =========================================
+
+key-name-hint
+    Name of key to use for signing. The keys will normally be in
+    a single directory (parameter -k to mkimage). For a given key <name>, its
+    private key is stored in <name>.key and the certificate is stored in
+    <name>.crt.
+
+sign-images
+    A list of images to sign, each being a property of the conf
+    node that contains then. The default is "kernel,fdt" which means that these
+    two images will be looked up in the config and signed if present. This is
+    used by mkimage to determine which images to sign.
+
+The following properies are added as part of signing, and are mandatory:
+
+value
+    Actual signature value. This is added by mkimage.
+
+hashed-nodes
+    A list of nodes which were hashed by the signer. Each is
+    a string - the full path to node. A typical value might be::
+
+	hashed-nodes = "/", "/configurations/conf-1", "/images/kernel",
+	    "/images/kernel/hash-1", "/images/fdt-1",
+	    "/images/fdt-1/hash-1";
+
+hashed-strings
+    The start and size of the string region of the FIT that was hashed. The
+    start is normally 0, indicating the first byte of the string table. The size
+    indicates the number of bytes hashed as part of signing.
+
+The following properies are added as part of signing, and are optional:
+
+timestamp
+    Time when image was signed (standard Unix time_t format)
+
+signer-name
+    Name of the signer (e.g. "mkimage")
+
+signer-version
+    Version string of the signer (e.g. "2013.01")
+
+comment
+    Additional information about the signer or image
+
+padding
+    The padding algorithm, it may be pkcs-1.5 or pss,
+    if no value is provided we assume pkcs-1.5
+
+
+'/configurations' node
+----------------------
+
+The 'configurations' node creates convenient, labeled boot configurations,
+which combine together kernel images with their ramdisks and fdt blobs.
+
+The 'configurations' node has the following structure::
+
+    o configurations
+        |- default = "default configuration sub-node unit name"
+        |
+        o config-1 {...}
+        o config-2 {...}
+        ...
+
+
+Optional property
+~~~~~~~~~~~~~~~~~
+
+default
+    Selects one of the configuration sub-nodes as a default configuration.
+
+Mandatory nodes
+~~~~~~~~~~~~~~~
+
+configuration-sub-node-unit-name
+    At least one of the configuration sub-nodes is required.
+
+Optional nodes
+~~~~~~~~~~~~~~
+
+signature-1
+    Each signature sub-node represents separate signature
+    calculated for the configuration according to specified algorithm.
+
+
+Configuration nodes
+-------------------
+
+Each configuration has the following structure::
+
+    o config-1
+        |- description = "configuration description"
+        |- kernel = "kernel sub-node unit name"
+        |- fdt = "fdt sub-node unit-name" [, "fdt overlay sub-node unit-name", ...]
+        |- loadables = "loadables sub-node unit-name"
+        |- script = "
+        |- compatible = "vendor,board-style device tree compatible string"
+        o signature-1 {...}
+
+Mandatory properties
+~~~~~~~~~~~~~~~~~~~~
+
+description
+    Textual configuration description.
+
+kernel or firmware
+    Unit name of the corresponding kernel or firmware
+    (u-boot, op-tee, etc) image. If both "kernel" and "firmware" are specified,
+    control is passed to the firmware image.
+
+Optional properties
+~~~~~~~~~~~~~~~~~~~
+
+fdt
+    Unit name of the corresponding fdt blob (component image node of a
+    "fdt type"). Additional fdt overlay nodes can be supplied which signify
+    that the resulting device tree blob is generated by the first base fdt
+    blob with all subsequent overlays applied.
+
+fpga
+    Unit name of the corresponding fpga bitstream blob
+    (component image node of a "fpga type").
+
+loadables
+    Unit name containing a list of additional binaries to be
+    loaded at their given locations.  "loadables" is a comma-separated list
+    of strings. U-Boot will load each binary at its given start-address and
+    may optionally invoke additional post-processing steps on this binary based
+    on its component image node type.
+
+script
+    The image to use when loading a U-Boot script (for use with the
+    source command).
+
+compatible
+    The root compatible string of the U-Boot device tree that
+    this configuration shall automatically match when CONFIG_FIT_BEST_MATCH is
+    enabled. If this property is not provided, the compatible string will be
+    extracted from the fdt blob instead. This is only possible if the fdt is
+    not compressed, so images with compressed fdts that want to use compatible
+    string matching must always provide this property.
+
+The FDT blob is required to properly boot FDT based kernel, so the minimal
+configuration for 2.6 FDT kernel is (kernel, fdt) pair.
+
+Older, 2.4 kernel and 2.6 non-FDT kernel do not use FDT blob, in such cases
+'struct bd_info' must be passed instead of FDT blob, thus fdt property *must
+not* be specified in a configuration node.
+
+Configuration-signature nodes
+-----------------------------
+
+::
+
+    o signature-1
+        |- algo = "algorithm name"
+        |- key-name-hint = "key name"
+        |- sign-images = "path1", "path2";
+        |- value = [hash or checksum value]
+        |- hashed-strings = <0 len>
+
+
+Mandatory properties
+~~~~~~~~~~~~~~~~~~~~
+
+algo
+    See `FIT Algorithm`_.
+
+key-name-hint
+    Name of key to use for signing. The keys will normally be in
+    a single directory (parameter -k to mkimage). For a given key <name>, its
+    private key is stored in <name>.key and the certificate is stored in
+    <name>.crt.
+
+The following properies are added as part of signing, and are mandatory:
+
+value
+    Actual signature value. This is added by mkimage.
+
+The following properies are added as part of signing, and are optional:
+
+timestamp
+    Time when image was signed (standard Unix time_t format)
+
+signer-name
+    Name of the signer (e.g. "mkimage")
+
+signer-version
+    Version string of the signer (e.g. "2013.01")
+
+comment
+    Additional information about the signer or image
+
+padding
+    The padding algorithm, it may be pkcs-1.5 or pss,
+    if no value is provided we assume pkcs-1.5
+
+
+
+Examples
+--------
+
+Some example files are available here, showing various scenarios
+
+.. toctree::
+    :maxdepth: 1
+
+    kernel
+    kernel_fdt
+    kernel_fdts_compressed
+    multi
+    multi_spl
+    multi-with-fpga
+    multi-with-loadables
+    sec_firmware_ppa
+    sign-configs
+    sign-images
+    uefi
+    update3
+    update_uboot
+
+.. sectionauthor:: Marian Balakowicz <m8@semihalf.com>
+.. sectionauthor:: External data additions, 25/1/16 Simon Glass <sjg@chromium.org>
diff --git a/doc/usage/fit/uefi.rst b/doc/usage/fit/uefi.rst
new file mode 100644
index 0000000000..3bbacb5cad
--- /dev/null
+++ b/doc/usage/fit/uefi.rst
@@ -0,0 +1,72 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+UEFI
+====
+
+Example FIT image description file demonstrating the usage of the
+bootm command to launch UEFI binaries.
+
+Two boot configurations are available to enable booting GRUB2 on QEMU,
+the former uses a FDT blob contained in the FIT image, while the later
+relies on the FDT provided by the board emulator.
+
+::
+
+    /dts-v1/;
+
+    / {
+        description = "GRUB2 EFI and QEMU FDT blob";
+        #address-cells = <1>;
+
+        images {
+            efi-grub {
+                description = "GRUB EFI Firmware";
+                data = /incbin/("bootarm.efi");
+                type = "kernel_noload";
+                arch = "arm";
+                os = "efi";
+                compression = "none";
+                load = <0x0>;
+                entry = <0x0>;
+                hash-1 {
+                    algo = "sha256";
+                };
+            };
+
+            fdt-qemu {
+                description = "QEMU DTB";
+                data = /incbin/("qemu-arm.dtb");
+                type = "flat_dt";
+                arch = "arm";
+                compression = "none";
+                hash-1 {
+                    algo = "sha256";
+                };
+            };
+        };
+
+        configurations {
+            default = "config-grub-fdt";
+
+            config-grub-fdt {
+                description = "GRUB EFI Boot w/ FDT";
+                kernel = "efi-grub";
+                fdt = "fdt-qemu";
+                signature-1 {
+                    algo = "sha256,rsa2048";
+                    key-name-hint = "dev";
+                    sign-images = "kernel", "fdt";
+                };
+            };
+
+            config-grub-nofdt {
+                description = "GRUB EFI Boot w/o FDT";
+                kernel = "efi-grub";
+                signature-1 {
+                    algo = "sha256,rsa2048";
+                    key-name-hint = "dev";
+                    sign-images = "kernel";
+                };
+            };
+        };
+    };
diff --git a/doc/usage/fit/update3.rst b/doc/usage/fit/update3.rst
new file mode 100644
index 0000000000..4ff3950c01
--- /dev/null
+++ b/doc/usage/fit/update3.rst
@@ -0,0 +1,47 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Automatic software update: multiple files
+=========================================
+
+::
+
+    /dts-v1/;
+
+    / {
+        description = "Automatic software updates: kernel, ramdisk, FDT";
+        #address-cells = <1>;
+
+        images {
+            update-1 {
+                description = "Linux kernel binary";
+                data = /incbin/("./vmlinux.bin.gz");
+                compression = "none";
+                type = "firmware";
+                load = <FF700000>;
+                hash-1 {
+                    algo = "sha1";
+                };
+            };
+            update-2 {
+                description = "Ramdisk image";
+                data = /incbin/("./ramdisk_image.gz");
+                compression = "none";
+                type = "firmware";
+                load = <FF8E0000>;
+                hash-1 {
+                    algo = "sha1";
+                };
+            };
+
+            update-3 {
+                description = "FDT blob";
+                data = /incbin/("./blob.fdt");
+                compression = "none";
+                type = "firmware";
+                load = <FFAC0000>;
+                hash-1 {
+                    algo = "sha1";
+                };
+            };
+        };
+    };
diff --git a/doc/usage/fit/update_uboot.rst b/doc/usage/fit/update_uboot.rst
new file mode 100644
index 0000000000..a9288ee636
--- /dev/null
+++ b/doc/usage/fit/update_uboot.rst
@@ -0,0 +1,28 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Automatic software update
+=========================
+
+Make sure the flashing addresses ('load' prop) is correct for your board!
+
+::
+
+    /dts-v1/;
+
+    / {
+        description = "Automatic U-Boot update";
+        #address-cells = <1>;
+
+        images {
+            update-1 {
+                description = "U-Boot binary";
+                data = /incbin/("./u-boot.bin");
+                compression = "none";
+                type = "firmware";
+                load = <0xFFFC0000>;
+                hash-1 {
+                    algo = "sha1";
+                };
+            };
+        };
+    };
diff --git a/doc/uImage.FIT/verified-boot.txt b/doc/usage/fit/verified-boot.rst
index 41c9fa9e09..301207711d 100644
--- a/doc/uImage.FIT/verified-boot.txt
+++ b/doc/usage/fit/verified-boot.rst
@@ -1,8 +1,11 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
 U-Boot Verified Boot
 ====================
 
 Introduction
 ------------
+
 Verified boot here means the verification of all software loaded into a
 machine during the boot process to ensure that it is authorised and correct
 for that machine.
@@ -21,6 +24,7 @@ memory, so that firmware can easily be upgraded in a secure manner.
 
 Signing
 -------
+
 Verified boot uses cryptographic algorithms to 'sign' software images.
 Images are signed using a private key known only to the signer, but can
 be verified using a public key. As its name suggests the public key can be
@@ -28,31 +32,31 @@ made available without risk to the verification process. The private and
 public keys are mathematically related. For more information on how this
 works look up "public key cryptography" and "RSA" (a particular algorithm).
 
-The signing and verification process looks something like this:
-
-
-      Signing                                      Verification
-      =======                                      ============
-
- +--------------+                   *
- | RSA key pair |                   *             +---------------+
- | .key  .crt   |                   *             | Public key in |
- +--------------+       +------> public key ----->| trusted place |
-       |                |           *             +---------------+
-       |                |           *                    |
-       v                |           *                    v
-   +---------+          |           *              +--------------+
-   |         |----------+           *              |              |
-   | signer  |                      *              |    U-Boot    |
-   |         |----------+           *              |  signature   |--> yes/no
-   +---------+          |           *              | verification |
-      ^                 |           *              |              |
-      |                 |           *              +--------------+
-      |                 |           *                    ^
- +----------+           |           *                    |
- | Software |           +----> signed image -------------+
- |  image   |                       *
- +----------+                       *
+The signing and verification process looks something like this::
+
+
+          Signing                                      Verification
+          =======                                      ============
+
+      +--------------+                 *
+      | RSA key pair |                 *             +---------------+
+      | .key  .crt   |                 *             | Public key in |
+      +--------------+     +------> public key ----->| trusted place |
+            |              |           *             +---------------+
+            |              |           *                    |
+            v              |           *                    v
+       +---------+         |           *             +--------------+
+       |         |---------+           *             |              |
+       | signer  |                     *             |    U-Boot    |
+       |         |---------+           *             |  signature   |--> yes/no
+       +---------+         |           *             | verification |
+            ^              |           *             |              |
+            |              |           *             +--------------+
+            |              |           *                    ^
+       +----------+        |           *                    |
+       | Software |        +----> signed image -------------+
+       |  image   |                    *
+       +----------+                    *
 
 
 The signature algorithm relies only on the public key to do its work. Using
@@ -70,23 +74,25 @@ the verification is worthless.
 
 Chaining Images
 ---------------
+
 The above method works for a signer providing images to a run-time U-Boot.
 It is also possible to extend this scheme to a second level, like this:
 
-1. Master private key is used by the signer to sign a first-stage image.
-2. Master public key is placed in read-only memory.
-2. Secondary private key is created and used to sign second-stage images.
-3. Secondary public key is placed in first stage images
-4. We use the master public key to verify the first-stage image. We then
-use the secondary public key in the first-stage image to verify the second-
-state image.
-5. This chaining process can go on indefinitely. It is recommended to use a
-different key at each stage, so that a compromise in one place will not
-affect the whole change.
+#. Master private key is used by the signer to sign a first-stage image.
+#. Master public key is placed in read-only memory.
+#. Secondary private key is created and used to sign second-stage images.
+#. Secondary public key is placed in first stage images
+#. We use the master public key to verify the first-stage image. We then
+   use the secondary public key in the first-stage image to verify the second-
+   state image.
+#. This chaining process can go on indefinitely. It is recommended to use a
+   different key at each stage, so that a compromise in one place will not
+   affect the whole change.
 
 
 Flattened Image Tree (FIT)
 --------------------------
+
 The FIT format is already widely used in U-Boot. It is a flattened device
 tree (FDT) in a particular format, with images contained within. FITs
 include hashes to verify images, so it is relatively straightforward to
@@ -96,9 +102,6 @@ The public key can be stored in U-Boot's CONFIG_OF_CONTROL device tree in
 a standard place. Then when a FIT is loaded it can be verified using that
 public key. Multiple keys and multiple signatures are supported.
 
-See signature.txt for more information.
-
+See :doc:`signature` for more information.
 
-Simon Glass
-sjg@chromium.org
-1-1-13
+.. sectionauthor:: Simon Glass <sjg@chromium.org> 1-1-13
diff --git a/doc/usage/fit/x86-fit-boot.rst b/doc/usage/fit/x86-fit-boot.rst
new file mode 100644
index 0000000000..93b73bb901
--- /dev/null
+++ b/doc/usage/fit/x86-fit-boot.rst
@@ -0,0 +1,269 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Booting Linux on x86 with FIT
+=============================
+
+Background
+----------
+
+Generally Linux x86 uses its own very complex booting method. There is a setup
+binary which contains all sorts of parameters and a compressed self-extracting
+binary for the kernel itself, often with a small built-in serial driver to
+display decompression progress.
+
+The x86 CPU has various processor modes. I am no expert on these, but my
+understanding is that an x86 CPU (even a really new one) starts up in a 16-bit
+'real' mode where only 1MB of memory is visible, moves to 32-bit 'protected'
+mode where 4GB is visible (or more with special memory access techniques) and
+then to 64-bit 'long' mode if 64-bit execution is required.
+
+Partly the self-extracting nature of Linux was introduced to cope with boot
+loaders that were barely capable of loading anything. Even changing to 32-bit
+mode was something of a challenge, so putting this logic in the kernel seemed
+to make sense.
+
+Bit by bit more and more logic has been added to this post-boot pre-Linux
+wrapper:
+
+- Changing to 32-bit mode
+- Decompression
+- Serial output (with drivers for various chips)
+- Load address randomisation
+- Elf loader complete with relocation (for the above)
+- Random number generator via 3 methods (again for the above)
+- Some sort of EFI mini-loader (1000+ glorious lines of code)
+- Locating and tacking on a device tree and ramdisk
+
+To my mind, if you sit back and look at things from first principles, this
+doesn't make a huge amount of sense. Any boot loader worth its salts already
+has most of the above features and more besides. The boot loader already knows
+the layout of memory, has a serial driver, can decompress things, includes an
+ELF loader and supports device tree and ramdisks. The decision to duplicate
+all these features in a Linux wrapper caters for the lowest common
+denominator: a boot loader which consists of a BIOS call to load something off
+disk, followed by a jmp instruction.
+
+(Aside: On ARM systems, we worry that the boot loader won't know where to load
+the kernel. It might be easier to just provide that information in the image,
+or in the boot loader rather than adding a self-relocator to put it in the
+right place. Or just use ELF?
+
+As a result, the x86 kernel boot process is needlessly complex. The file
+format is also complex, and obfuscates the contents to a degree that it is
+quite a challenge to extract anything from it. This bzImage format has become
+so prevalent that is actually isn't possible to produce the 'raw' kernel build
+outputs with the standard Makefile (as it is on ARM for example, at least at
+the time of writing).
+
+This document describes an alternative boot process which uses simple raw
+images which are loaded into the right place by the boot loader and then
+executed.
+
+
+Build the kernel
+----------------
+
+Note: these instructions assume a 32-bit kernel. U-Boot also supports directly
+booting a 64-bit kernel by jumping into 64-bit mode first (see below).
+
+You can build the kernel as normal with 'make'. This will create a file called
+'vmlinux'. This is a standard ELF file and you can look at it if you like::
+
+    $ objdump -h vmlinux
+
+    vmlinux:     file format elf32-i386
+
+    Sections:
+    Idx Name          Size      VMA       LMA       File off  Algn
+      0 .text         00416850  81000000  01000000  00001000  2**5
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+      1 .notes        00000024  81416850  01416850  00417850  2**2
+                      CONTENTS, ALLOC, LOAD, READONLY, CODE
+      2 __ex_table    00000c50  81416880  01416880  00417880  2**3
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+      3 .rodata       00154b9e  81418000  01418000  00419000  2**5
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+      4 __bug_table   0000597c  8156cba0  0156cba0  0056dba0  2**0
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+      5 .pci_fixup    00001b80  8157251c  0157251c  0057351c  2**2
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+      6 .tracedata    00000024  8157409c  0157409c  0057509c  2**0
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+      7 __ksymtab     00007ec0  815740c0  015740c0  005750c0  2**2
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+      8 __ksymtab_gpl 00004a28  8157bf80  0157bf80  0057cf80  2**2
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+      9 __ksymtab_strings 0001d6fc  815809a8  015809a8  005819a8  2**0
+                      CONTENTS, ALLOC, LOAD, READONLY, DATA
+     10 __init_rodata 00001c3c  8159e0a4  0159e0a4  0059f0a4  2**2
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+     11 __param       00000ff0  8159fce0  0159fce0  005a0ce0  2**2
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+     12 __modver      00000330  815a0cd0  015a0cd0  005a1cd0  2**2
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+     13 .data         00063000  815a1000  015a1000  005a2000  2**12
+                      CONTENTS, ALLOC, LOAD, RELOC, DATA
+     14 .init.text    0002f104  81604000  01604000  00605000  2**2
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+     15 .init.data    00040cdc  81634000  01634000  00635000  2**12
+                      CONTENTS, ALLOC, LOAD, RELOC, DATA
+     16 .x86_cpu_dev.init 0000001c  81674cdc  01674cdc  00675cdc  2**2
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+     17 .altinstructions 0000267c  81674cf8  01674cf8  00675cf8  2**0
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+     18 .altinstr_replacement 00000942  81677374  01677374  00678374  2**0
+                      CONTENTS, ALLOC, LOAD, READONLY, CODE
+     19 .iommu_table  00000014  81677cb8  01677cb8  00678cb8  2**2
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+     20 .apicdrivers  00000004  81677cd0  01677cd0  00678cd0  2**2
+                      CONTENTS, ALLOC, LOAD, RELOC, DATA
+     21 .exit.text    00001a80  81677cd8  01677cd8  00678cd8  2**0
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+     22 .data..percpu 00007880  8167a000  0167a000  0067b000  2**12
+                      CONTENTS, ALLOC, LOAD, RELOC, DATA
+     23 .smp_locks    00003000  81682000  01682000  00683000  2**2
+                      CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+     24 .bss          000a1000  81685000  01685000  00686000  2**12
+                      ALLOC
+     25 .brk          00424000  81726000  01726000  00686000  2**0
+                      ALLOC
+     26 .comment      00000049  00000000  00000000  00686000  2**0
+                      CONTENTS, READONLY
+     27 .GCC.command.line 0003e055  00000000  00000000  00686049  2**0
+                      CONTENTS, READONLY
+     28 .debug_aranges 0000f4c8  00000000  00000000  006c40a0  2**3
+                      CONTENTS, RELOC, READONLY, DEBUGGING
+     29 .debug_info   0440b0df  00000000  00000000  006d3568  2**0
+                      CONTENTS, RELOC, READONLY, DEBUGGING
+     30 .debug_abbrev 0022a83b  00000000  00000000  04ade647  2**0
+                      CONTENTS, READONLY, DEBUGGING
+     31 .debug_line   004ead0d  00000000  00000000  04d08e82  2**0
+                      CONTENTS, RELOC, READONLY, DEBUGGING
+     32 .debug_frame  0010a960  00000000  00000000  051f3b90  2**2
+                      CONTENTS, RELOC, READONLY, DEBUGGING
+     33 .debug_str    001b442d  00000000  00000000  052fe4f0  2**0
+                      CONTENTS, READONLY, DEBUGGING
+     34 .debug_loc    007c7fa9  00000000  00000000  054b291d  2**0
+                      CONTENTS, RELOC, READONLY, DEBUGGING
+     35 .debug_ranges 00098828  00000000  00000000  05c7a8c8  2**3
+                      CONTENTS, RELOC, READONLY, DEBUGGING
+
+There is also the setup binary mentioned earlier. This is at
+arch/x86/boot/setup.bin and is about 12KB in size. It includes the command
+line and various settings need by the kernel. Arguably the boot loader should
+provide all of this also, but setting it up is some complex that the kernel
+helps by providing a head start.
+
+As you can see the code loads to address 0x01000000 and everything else
+follows after that. We could load this image using the 'bootelf' command but
+we would still need to provide the setup binary. This is not supported by
+U-Boot although I suppose you could mostly script it. This would permit the
+use of a relocatable kernel.
+
+All we need to boot is the vmlinux file and the setup.bin file.
+
+
+Create a FIT
+------------
+
+To create a FIT you will need a source file describing what should go in the
+FIT. See kernel.its for an example for x86 and also instructions on setting
+the 'arch' value for booting 64-bit kernels if desired. Put this into a file
+called image.its.
+
+Note that setup is loaded to the special address of 0x90000 (a special address
+you just have to know) and the kernel is loaded to 0x01000000 (the address you
+saw above). This means that you will need to load your FIT to a different
+address so that U-Boot doesn't overwrite it when decompressing. Something like
+0x02000000 will do so you can set CONFIG_SYS_LOAD_ADDR to that.
+
+In that example the kernel is compressed with lzo. Also we need to provide a
+flat binary, not an ELF. So the steps needed to set things are are::
+
+    # Create a flat binary
+    objcopy -O binary vmlinux vmlinux.bin
+
+    # Compress it into LZO format
+    lzop vmlinux.bin
+
+    # Build a FIT image
+    mkimage -f image.its image.fit
+
+(be careful to run the mkimage from your U-Boot tools directory since it
+will have x86_setup support.)
+
+You can take a look at the resulting fit file if you like::
+
+    $ dumpimage -l image.fit
+    FIT description: Simple image with single Linux kernel on x86
+    Created:         Tue Oct  7 10:57:24 2014
+     Image 0 (kernel)
+      Description:  Vanilla Linux kernel
+      Created:      Tue Oct  7 10:57:24 2014
+      Type:         Kernel Image
+      Compression:  lzo compressed
+      Data Size:    4591767 Bytes = 4484.15 kB = 4.38 MB
+      Architecture: Intel x86
+      OS:           Linux
+      Load Address: 0x01000000
+      Entry Point:  0x00000000
+      Hash algo:    sha1
+      Hash value:   446b5163ebfe0fb6ee20cbb7a8501b263cd92392
+     Image 1 (setup)
+      Description:  Linux setup.bin
+      Created:      Tue Oct  7 10:57:24 2014
+      Type:         x86 setup.bin
+      Compression:  uncompressed
+      Data Size:    12912 Bytes = 12.61 kB = 0.01 MB
+      Hash algo:    sha1
+      Hash value:   a1f2099cf47ff9816236cd534c77af86e713faad
+     Default Configuration: 'config-1'
+     Configuration 0 (config-1)
+      Description:  Boot Linux kernel
+      Kernel:       kernel
+
+
+Booting the FIT
+---------------
+
+To make it boot you need to load it and then use 'bootm' to boot it. A
+suitable script to do this from a network server is::
+
+    bootp
+    tftp image.fit
+    bootm
+
+This will load the image from the network and boot it. The command line (from
+the 'bootargs' environment variable) will be passed to the kernel.
+
+If you want a ramdisk you can add it as normal with FIT. If you want a device
+tree then x86 doesn't normally use those - it has ACPI instead.
+
+
+Why Bother?
+-----------
+
+#. It demystifies the process of booting an x86 kernel
+#. It allows use of the standard U-Boot boot file format
+#. It allows U-Boot to perform decompression - problems will provide an error
+   message and you are still in the boot loader. It is possible to investigate.
+#. It avoids all the pre-loader code in the kernel which is quite complex to
+   follow
+#. You can use verified/secure boot and other features which haven't yet been
+   added to the pre-Linux
+#. It makes x86 more like other architectures in the way it boots a kernel.
+   You can potentially use the same file format for the kernel, and the same
+   procedure for building and packaging it.
+
+
+References
+----------
+
+In the Linux kernel, Documentation/x86/boot.txt defines the boot protocol for
+the kernel including the setup.bin format. This is handled in U-Boot in
+arch/x86/lib/zimage.c and arch/x86/lib/bootm.c.
+
+Various files in the same directory as this file describe the FIT format.
+
+
+.. sectionauthor:: Simon Glass <sjg@chromium.org> 7-Oct-2014
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index 54ef89edb2..3326ec82ff 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -8,7 +8,7 @@ Use U-Boot
    dfu
    environment
    fdt_overlays
-   fit
+   fit/index
    netconsole
    partitions
    cmdline
@@ -22,21 +22,25 @@ Shell commands
 
    cmd/acpi
    cmd/addrmap
+   cmd/armffa
    cmd/askenv
    cmd/base
    cmd/bdinfo
+   cmd/bind
    cmd/blkcache
    cmd/bootd
    cmd/bootdev
    cmd/bootefi
    cmd/bootflow
    cmd/booti
+   cmd/bootm
    cmd/bootmenu
    cmd/bootmeth
    cmd/button
    cmd/bootz
    cmd/cat
    cmd/cbsysinfo
+   cmd/cedit
    cmd/cls
    cmd/cmp
    cmd/coninfo
@@ -66,12 +70,14 @@ Shell commands
    cmd/load
    cmd/loadb
    cmd/loadm
+   cmd/loads
    cmd/loadx
    cmd/loady
    cmd/mbr
    cmd/md
    cmd/mmc
    cmd/mtest
+   cmd/mtrr
    cmd/panic
    cmd/part
    cmd/pause
@@ -82,6 +88,7 @@ Shell commands
    cmd/read
    cmd/reset
    cmd/rng
+   cmd/saves
    cmd/sbi
    cmd/sf
    cmd/scp03
@@ -97,6 +104,7 @@ Shell commands
    cmd/trace
    cmd/true
    cmd/ums
+   cmd/unbind
    cmd/ut
    cmd/wdt
    cmd/wget
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 75937fbb6d..a25f6ae02f 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -10,6 +10,8 @@ source "drivers/ata/Kconfig"
 
 source "drivers/axi/Kconfig"
 
+source "drivers/bios_emulator/Kconfig"
+
 source "drivers/bus/Kconfig"
 
 source "drivers/block/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 29be78a3f2..efc2a4afb2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+obj-$(CONFIG_$(SPL_TPL_)BIOSEMU) += bios_emulator/
 obj-$(CONFIG_$(SPL_TPL_)BLK) += block/
 obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
 obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/
@@ -35,8 +36,11 @@ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/
 obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/
 obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/
 obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
+obj-$(CONFIG_$(SPL_)NVME) += nvme/
 obj-$(CONFIG_XEN) += xen/
 obj-$(CONFIG_$(SPL_)FPGA) += fpga/
+obj-$(CONFIG_$(SPL_)VIDEO) += video/
+
 obj-y += bus/
 
 ifndef CONFIG_TPL_BUILD
@@ -62,7 +66,6 @@ obj-$(CONFIG_SPL_USB_HOST) += usb/host/
 obj-$(CONFIG_SPL_SATA) += ata/ scsi/
 obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/
 obj-$(CONFIG_SPL_THERMAL) += thermal/
-obj-$(CONFIG_SPL_VIDEO) +=video/
 
 endif
 endif
@@ -79,7 +82,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 obj-y += adc/
 obj-y += ata/
 obj-$(CONFIG_DM_DEMO) += demo/
-obj-$(CONFIG_BIOSEMU) += bios_emulator/
 obj-y += block/
 obj-y += cache/
 obj-$(CONFIG_CPU) += cpu/
@@ -98,7 +100,6 @@ obj-y += rtc/
 obj-y += scsi/
 obj-y += sound/
 obj-y += spmi/
-obj-y += video/
 obj-y += watchdog/
 obj-$(CONFIG_QE) += qe/
 obj-$(CONFIG_U_QE) += qe/
@@ -114,6 +115,7 @@ obj-y += iommu/
 obj-y += smem/
 obj-y += thermal/
 obj-$(CONFIG_TEE) += tee/
+obj-$(CONFIG_ARM_FFA_TRANSPORT) += firmware/arm-ffa/
 obj-y += axi/
 obj-y += ufs/
 obj-$(CONFIG_W1) += w1/
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig
index e719c38bb3..4336732dee 100644
--- a/drivers/adc/Kconfig
+++ b/drivers/adc/Kconfig
@@ -63,3 +63,11 @@ config STM32_ADC
 	  - core driver to deal with common resources
 	  - child driver to deal with individual ADC resources (declare ADC
 	  device and associated channels, start/stop conversions)
+
+config ADC_IMX93
+	bool "Enable NXP IMX93 ADC driver"
+	help
+	  This enables basic driver for NXP IMX93 ADC.
+	  It provides:
+	  - 4 analog input channels
+	  - 12-bit resolution
diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile
index c1387f3a34..5336c82097 100644
--- a/drivers/adc/Makefile
+++ b/drivers/adc/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
 obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o
 obj-$(CONFIG_SARADC_MESON) += meson-saradc.o
 obj-$(CONFIG_STM32_ADC) += stm32-adc.o stm32-adc-core.o
+obj-$(CONFIG_ADC_IMX93) += imx93-adc.o
diff --git a/drivers/adc/imx93-adc.c b/drivers/adc/imx93-adc.c
new file mode 100644
index 0000000000..41d04e0426
--- /dev/null
+++ b/drivers/adc/imx93-adc.c
@@ -0,0 +1,290 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 ASEM Srl
+ * Author: Luca Ellero <l.ellero@asem.it>
+ *
+ * Originally based on NXP linux-imx kernel v5.15 drivers/iio/adc/imx93_adc.c
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <linux/bitfield.h>
+#include <linux/iopoll.h>
+#include <clk.h>
+#include <adc.h>
+
+#define IMX93_ADC_MCR			0x00
+#define IMX93_ADC_MSR			0x04
+#define IMX93_ADC_ISR			0x10
+#define IMX93_ADC_IMR			0x20
+#define IMX93_ADC_CIMR0			0x24
+#define IMX93_ADC_CTR0			0x94
+#define IMX93_ADC_NCMR0			0xA4
+#define IMX93_ADC_PCDR0			0x100
+#define IMX93_ADC_PCDR1			0x104
+#define IMX93_ADC_PCDR2			0x108
+#define IMX93_ADC_PCDR3			0x10c
+#define IMX93_ADC_PCDR4			0x110
+#define IMX93_ADC_PCDR5			0x114
+#define IMX93_ADC_PCDR6			0x118
+#define IMX93_ADC_PCDR7			0x11c
+#define IMX93_ADC_CALSTAT		0x39C
+
+#define IMX93_ADC_MCR_MODE_MASK		BIT(29)
+#define IMX93_ADC_MCR_NSTART_MASK	BIT(24)
+#define IMX93_ADC_MCR_CALSTART_MASK	BIT(14)
+#define IMX93_ADC_MCR_ADCLKSE_MASK	BIT(8)
+#define IMX93_ADC_MCR_PWDN_MASK		BIT(0)
+
+#define IMX93_ADC_MSR_CALFAIL_MASK	BIT(30)
+#define IMX93_ADC_MSR_CALBUSY_MASK	BIT(29)
+#define IMX93_ADC_MSR_ADCSTATUS_MASK	GENMASK(2, 0)
+
+#define IMX93_ADC_ISR_EOC_MASK		BIT(1)
+
+#define IMX93_ADC_IMR_EOC_MASK		BIT(1)
+#define IMX93_ADC_IMR_ECH_MASK		BIT(0)
+
+#define IMX93_ADC_PCDR_CDATA_MASK	GENMASK(11, 0)
+
+#define IDLE				0
+#define POWER_DOWN			1
+#define WAIT_STATE			2
+#define BUSY_IN_CALIBRATION		3
+#define SAMPLE				4
+#define CONVERSION			6
+
+#define IMX93_ADC_MAX_CHANNEL		3
+#define IMX93_ADC_DAT_MASK		0xfff
+#define IMX93_ADC_TIMEOUT		100000
+
+struct imx93_adc_priv {
+	int active_channel;
+	void __iomem *regs;
+	struct clk ipg_clk;
+};
+
+static void imx93_adc_power_down(struct imx93_adc_priv *adc)
+{
+	u32 mcr, msr;
+	int ret;
+
+	mcr = readl(adc->regs + IMX93_ADC_MCR);
+	mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
+	writel(mcr, adc->regs + IMX93_ADC_MCR);
+
+	ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr,
+		((msr & IMX93_ADC_MSR_ADCSTATUS_MASK) == POWER_DOWN), 50);
+	if (ret == -ETIMEDOUT)
+		pr_warn("ADC not in power down mode, current MSR: %x\n", msr);
+}
+
+static void imx93_adc_power_up(struct imx93_adc_priv *adc)
+{
+	u32 mcr;
+
+	/* bring ADC out of power down state, in idle state */
+	mcr = readl(adc->regs + IMX93_ADC_MCR);
+	mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
+	writel(mcr, adc->regs + IMX93_ADC_MCR);
+}
+
+static void imx93_adc_config_ad_clk(struct imx93_adc_priv *adc)
+{
+	u32 mcr;
+
+	/* put adc in power down mode */
+	imx93_adc_power_down(adc);
+
+	/* config the AD_CLK equal to bus clock */
+	mcr = readl(adc->regs + IMX93_ADC_MCR);
+	mcr |= FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);
+	writel(mcr, adc->regs + IMX93_ADC_MCR);
+
+	/* bring ADC out of power down state, in idle state */
+	imx93_adc_power_up(adc);
+}
+
+static int imx93_adc_calibration(struct imx93_adc_priv *adc)
+{
+	u32 mcr, msr;
+	int ret;
+
+	/* make sure ADC is in power down mode */
+	imx93_adc_power_down(adc);
+
+	/* config SAR controller operating clock */
+	mcr = readl(adc->regs + IMX93_ADC_MCR);
+	mcr &= ~FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);
+	writel(mcr, adc->regs + IMX93_ADC_MCR);
+
+	/* bring ADC out of power down state */
+	imx93_adc_power_up(adc);
+
+	/*
+	 * we use the default TSAMP/NRSMPL/AVGEN in MCR,
+	 * can add the setting of these bit if need
+	 */
+
+	/* run calibration */
+	mcr = readl(adc->regs + IMX93_ADC_MCR);
+	mcr |= FIELD_PREP(IMX93_ADC_MCR_CALSTART_MASK, 1);
+	writel(mcr, adc->regs + IMX93_ADC_MCR);
+
+	/* wait calibration to be finished */
+	ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr,
+		!(msr & IMX93_ADC_MSR_CALBUSY_MASK), 2000000);
+	if (ret == -ETIMEDOUT) {
+		pr_warn("ADC calibration timeout\n");
+		return ret;
+	}
+
+	/* check whether calbration is successful or not */
+	msr = readl(adc->regs + IMX93_ADC_MSR);
+	if (msr & IMX93_ADC_MSR_CALFAIL_MASK) {
+		pr_warn("ADC calibration failed!\n");
+		return -EAGAIN;
+	}
+
+	return 0;
+}
+
+static int imx93_adc_channel_data(struct udevice *dev, int channel,
+			    unsigned int *data)
+{
+	struct imx93_adc_priv *adc = dev_get_priv(dev);
+	u32 isr, pcda;
+	int ret;
+
+	if (channel != adc->active_channel) {
+		pr_err("Requested channel is not active!\n");
+		return -EINVAL;
+	}
+
+	ret = readl_poll_timeout(adc->regs + IMX93_ADC_ISR, isr,
+		(isr & IMX93_ADC_ISR_EOC_MASK), IMX93_ADC_TIMEOUT);
+
+	/* clear interrupts */
+	writel(isr, adc->regs + IMX93_ADC_ISR);
+
+	if (ret == -ETIMEDOUT) {
+		pr_warn("ADC conversion timeout!\n");
+		return ret;
+	}
+
+	pcda = readl(adc->regs + IMX93_ADC_PCDR0 + channel * 4);
+
+	*data = FIELD_GET(IMX93_ADC_PCDR_CDATA_MASK, pcda);
+
+	return 0;
+}
+
+static int imx93_adc_start_channel(struct udevice *dev, int channel)
+{
+	struct imx93_adc_priv *adc = dev_get_priv(dev);
+	u32 imr, mcr;
+
+	/* config channel mask register */
+	writel(1 << channel, adc->regs + IMX93_ADC_NCMR0);
+
+	/* config interrupt mask */
+	imr = FIELD_PREP(IMX93_ADC_IMR_EOC_MASK, 1);
+	writel(imr, adc->regs + IMX93_ADC_IMR);
+	writel(1 << channel, adc->regs + IMX93_ADC_CIMR0);
+
+	/* config one-shot mode */
+	mcr = readl(adc->regs + IMX93_ADC_MCR);
+	mcr &= ~FIELD_PREP(IMX93_ADC_MCR_MODE_MASK, 1);
+	writel(mcr, adc->regs + IMX93_ADC_MCR);
+
+	/* start normal conversion */
+	mcr = readl(adc->regs + IMX93_ADC_MCR);
+	mcr |= FIELD_PREP(IMX93_ADC_MCR_NSTART_MASK, 1);
+	writel(mcr, adc->regs + IMX93_ADC_MCR);
+
+	adc->active_channel = channel;
+
+	return 0;
+}
+
+static int imx93_adc_stop(struct udevice *dev)
+{
+	struct imx93_adc_priv *adc = dev_get_priv(dev);
+
+	imx93_adc_power_down(adc);
+
+	adc->active_channel = -1;
+
+	return 0;
+}
+
+static int imx93_adc_probe(struct udevice *dev)
+{
+	struct imx93_adc_priv *adc = dev_get_priv(dev);
+	unsigned int ret;
+
+	ret = imx93_adc_calibration(adc);
+	if (ret < 0)
+		return ret;
+
+	imx93_adc_config_ad_clk(adc);
+
+	adc->active_channel = -1;
+
+	return 0;
+}
+
+static int imx93_adc_of_to_plat(struct udevice *dev)
+{
+	struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
+	struct imx93_adc_priv *adc = dev_get_priv(dev);
+	unsigned int ret;
+
+	adc->regs = dev_read_addr_ptr(dev);
+	if (adc->regs == (struct imx93_adc *)FDT_ADDR_T_NONE) {
+		pr_err("Dev: %s - can't get address!", dev->name);
+		return -ENODATA;
+	}
+
+	ret = clk_get_by_name(dev, "ipg", &adc->ipg_clk);
+	if (ret < 0) {
+		pr_err("Can't get ADC ipg clk: %d\n", ret);
+		return ret;
+	}
+	ret = clk_enable(&adc->ipg_clk);
+	if(ret) {
+		pr_err("Can't enable ADC ipg clk: %d\n", ret);
+		return ret;
+	}
+
+	uc_pdata->data_mask = IMX93_ADC_DAT_MASK;
+	uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
+	uc_pdata->data_timeout_us = IMX93_ADC_TIMEOUT;
+
+	/* Mask available channel bits: [0:3] */
+	uc_pdata->channel_mask = (2 << IMX93_ADC_MAX_CHANNEL) - 1;
+
+	return 0;
+}
+
+static const struct adc_ops imx93_adc_ops = {
+	.start_channel = imx93_adc_start_channel,
+	.channel_data = imx93_adc_channel_data,
+	.stop = imx93_adc_stop,
+};
+
+static const struct udevice_id imx93_adc_ids[] = {
+	{ .compatible = "nxp,imx93-adc" },
+	{ }
+};
+
+U_BOOT_DRIVER(imx93_adc) = {
+	.name		= "imx93-adc",
+	.id		= UCLASS_ADC,
+	.of_match	= imx93_adc_ids,
+	.ops		= &imx93_adc_ops,
+	.probe		= imx93_adc_probe,
+	.of_to_plat	= imx93_adc_of_to_plat,
+	.priv_auto	= sizeof(struct imx93_adc_priv),
+};
diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c
index 826fea71cc..1dc91e7fce 100644
--- a/drivers/ata/dwc_ahci.c
+++ b/drivers/ata/dwc_ahci.c
@@ -13,7 +13,9 @@
 #include <ahci.h>
 #include <scsi.h>
 #include <sata.h>
+#ifdef CONFIG_ARCH_OMAP2PLUS
 #include <asm/arch/sata.h>
+#endif
 #include <asm/io.h>
 #include <generic-phy.h>
 
@@ -72,12 +74,14 @@ static int dwc_ahci_probe(struct udevice *dev)
 		return ret;
 	}
 
+#ifdef CONFIG_ARCH_OMAP2PLUS
 	if (priv->wrapper_base) {
 		u32 val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
 
 		/* Enable SATA module, No Idle, No Standby */
 		writel(val, priv->wrapper_base + TI_SATA_SYSCONFIG);
 	}
+#endif
 
 	return ahci_probe_scsi(dev, (ulong)priv->base);
 }
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index 43bcc59cd2..47366438fd 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2015 - 2016 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 #include <common.h>
 #include <dm.h>
diff --git a/drivers/axi/axi-emul-uclass.c b/drivers/axi/axi-emul-uclass.c
index 793336d8c4..e6f3ef0720 100644
--- a/drivers/axi/axi-emul-uclass.c
+++ b/drivers/axi/axi-emul-uclass.c
@@ -14,7 +14,7 @@
 #include <asm/axi.h>
 
 int axi_sandbox_get_emul(struct udevice *bus, ulong address,
-			 enum axi_size_t size, struct udevice **emulp)
+			 const enum axi_size_t size, struct udevice **emulp)
 {
 	struct udevice *dev;
 	u32 reg[2];
diff --git a/drivers/bios_emulator/Kconfig b/drivers/bios_emulator/Kconfig
new file mode 100644
index 0000000000..3660576772
--- /dev/null
+++ b/drivers/bios_emulator/Kconfig
@@ -0,0 +1,10 @@
+config BIOSEMU
+	bool
+	select X86EMU_RAW_IO
+
+config SPL_BIOSEMU
+	bool
+	select X86EMU_RAW_IO
+
+config X86EMU_RAW_IO
+	bool
diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h
index 7853015c1e..954cd88315 100644
--- a/drivers/bios_emulator/biosemui.h
+++ b/drivers/bios_emulator/biosemui.h
@@ -128,19 +128,19 @@ typedef struct {
 	u32 finalVal;
 } BE_portInfo;
 
-#define PM_inpb(port)	inb(port+VIDEO_IO_OFFSET)
-#define PM_inpw(port)	inw(port+VIDEO_IO_OFFSET)
-#define PM_inpd(port)	inl(port+VIDEO_IO_OFFSET)
-#define PM_outpb(port,val)	outb(val,port+VIDEO_IO_OFFSET)
-#define PM_outpw(port,val)	outw(val,port+VIDEO_IO_OFFSET)
-#define PM_outpd(port,val)	outl(val,port+VIDEO_IO_OFFSET)
+#define PM_inpb(port)	inb(port)
+#define PM_inpw(port)	inw(port)
+#define PM_inpd(port)	inl(port)
+#define PM_outpb(port, val)	outb(val, port)
+#define PM_outpw(port, val)	outw(val, port)
+#define PM_outpd(port, val)	outl(val, port)
 
 #define LOG_inpb(port)	PM_inpb(port)
 #define LOG_inpw(port)	PM_inpw(port)
 #define LOG_inpd(port)	PM_inpd(port)
-#define LOG_outpb(port,val)	PM_outpb(port,val)
-#define LOG_outpw(port,val)	PM_outpw(port,val)
-#define LOG_outpd(port,val)	PM_outpd(port,val)
+#define LOG_outpb(port, val)	PM_outpb(port, val)
+#define LOG_outpw(port, val)	PM_outpw(port, val)
+#define LOG_outpd(port, val)	PM_outpd(port, val)
 
 /*-------------------------- Function Prototypes --------------------------*/
 
diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c
index c2db1213fe..882a8a34cc 100644
--- a/drivers/bios_emulator/x86emu/sys.c
+++ b/drivers/bios_emulator/x86emu/sys.c
@@ -44,6 +44,7 @@
 
 /*------------------------- Global Variables ------------------------------*/
 
+/* Note: bios.c defines this if the emulator is not enabled */
 X86EMU_sysEnv _X86EMU_env;	/* Global emulator machine state */
 X86EMU_intrFuncs _X86EMU_intrTab[256];
 
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 5a1aeb3d2b..6baaa6f071 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -107,6 +107,13 @@ config EFI_MEDIA
 
 	  For sandbox there is a test driver.
 
+config SPL_BLK_FS
+	bool "Load images from filesystems on block devices"
+	depends on SPL_BLK
+	help
+	  Use generic support to load images from fat/ext filesystems on
+	  different types of block devices such as NVMe.
+
 if EFI_MEDIA
 
 config EFI_MEDIA_SANDBOX
diff --git a/drivers/block/ide.c b/drivers/block/ide.c
index 89201dd4d2..c698f9cbd5 100644
--- a/drivers/block/ide.c
+++ b/drivers/block/ide.c
@@ -1059,9 +1059,9 @@ static int ide_probe(struct udevice *udev)
 		desc->lba48 = pdesc.lba48;
 		desc->type = pdesc.type;
 
-		ret = bootdev_setup_for_dev(udev, "ide_bootdev");
+		ret = bootdev_setup_for_sibling_blk(blk, "ide_bootdev");
 		if (ret)
-			return log_msg_ret("bootdev", ret);
+			return log_msg_ret("bd", ret);
 	}
 
 	return 0;
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 3ad5af964f..29859cdfa1 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -160,6 +160,7 @@ config SANDBOX_CLK_CCF
 
 config CLK_SCMI
 	bool "Enable SCMI clock driver"
+	depends on CLK
 	depends on SCMI_FIRMWARE
 	help
 	  Enable this option if you want to support clock devices exposed
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 184d426d0b..017f25f7a5 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -184,7 +184,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
 	if (!mux)
 		return ERR_PTR(-ENOMEM);
 
-	/* U-boot specific assignments */
+	/* U-Boot specific assignments */
 	mux->parent_names = parent_names;
 	mux->num_parents = num_parents;
 
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index faebbab1c6..b3b3333123 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2019 Xilinx, Inc.
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 #include <common.h>
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 45c679a627..1cfe0e25b1 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -12,6 +12,7 @@
 #include <linux/bitops.h>
 #include <clk-uclass.h>
 #include <clk.h>
+#include <zynqmp_firmware.h>
 #include <asm/arch/sys_proto.h>
 #include <dm.h>
 #include <linux/err.h>
@@ -269,17 +270,22 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
 	case usb3_dual_ref:
 		return CRL_APB_USB3_DUAL_REF_CTRL;
 	case gem_tsu_ref:
+	case gem_tsu:
 		return CRL_APB_GEM_TSU_REF_CTRL;
 	case gem0_tx:
+	case gem0_rx:
 	case gem0_ref:
 		return CRL_APB_GEM0_REF_CTRL;
 	case gem1_tx:
+	case gem1_rx:
 	case gem1_ref:
 		return CRL_APB_GEM1_REF_CTRL;
 	case gem2_tx:
+	case gem2_rx:
 	case gem2_ref:
 		return CRL_APB_GEM2_REF_CTRL;
 	case gem3_tx:
+	case gem3_rx:
 	case gem3_ref:
 		return CRL_APB_GEM3_REF_CTRL;
 	case usb0_bus_ref:
@@ -691,6 +697,7 @@ static ulong zynqmp_clk_get_rate(struct clk *clk)
 	case topsw_lsbus:
 	case sata_ref ... gpu_pp1_ref:
 		two_divs = true;
+		fallthrough;
 	case cpu_r5:
 	case dbg_fpd:
 	case ams_ref:
@@ -717,6 +724,8 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
 	switch (id) {
 	case gem0_ref ... gem3_ref:
 	case gem0_tx ... gem3_tx:
+	case gem0_rx ... gem3_rx:
+	case gem_tsu:
 	case qspi_ref ... can1_ref:
 	case usb0_bus_ref ... usb3_dual_ref:
 		return zynqmp_clk_set_peripheral_rate(priv, id,
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 09bef596f2..a21a3ce34b 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -337,7 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
 	clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
 	clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
-	clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "usb_core_ref", base + 0x44d0, 0));
+	clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0));
+	clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0));
 	clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
 	clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 	clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 1decf31a77..e74c6f9780 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
 obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
 obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o
 obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o
+obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o
 obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
 obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
 obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
new file mode 100644
index 0000000000..34e7b2d734
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -0,0 +1,1123 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7988 SoC
+ *
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dm.h>
+#include <log.h>
+#include <asm/arch-mediatek/reset.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt7988-clk.h>
+#include <linux/bitops.h>
+
+#include "clk-mtk.h"
+
+#define MT7988_CLK_PDN		0x250
+#define MT7988_CLK_PDN_EN_WRITE BIT(31)
+
+#define MT7988_ETHDMA_RST_CTRL_OFS	0x34
+#define MT7988_ETHWARP_RST_CTRL_OFS	0x8
+
+#define XTAL_FACTOR(_id, _name, _parent, _mult, _div)                          \
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
+
+#define PLL_FACTOR(_id, _name, _parent, _mult, _div)                           \
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define TOP_FACTOR(_id, _name, _parent, _mult, _div)                           \
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define INFRA_FACTOR(_id, _name, _parent, _mult, _div)                         \
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
+
+/* FIXED PLLS */
+static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
+	FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
+	FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
+	FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
+	FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
+	FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
+	FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
+	FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
+	FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
+	FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
+	FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
+	FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
+	FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
+};
+
+/* TOPCKGEN FIXED DIV */
+static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
+	XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1),
+	PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
+	PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
+	PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
+	PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
+	PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
+	PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
+	PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
+	PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
+	PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
+	PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
+	PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
+	PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
+	PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
+		   1),
+	PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4),
+	PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
+	PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
+	PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
+	PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
+	PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
+	PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
+	PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
+	PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
+	PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1,
+		   128),
+	PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
+		   1),
+	PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
+	PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
+	PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
+	PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
+	PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
+	PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8),
+	PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
+		   CK_APMIXED_WEDMCUPLL, 1, 1),
+	PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
+	PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m",
+		   CK_APMIXED_NETSYSPLL, 1, 1),
+	PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1,
+		   1),
+	TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
+	TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
+		   1250),
+	TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
+		   1220),
+	TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1,
+		   1),
+	XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1),
+	TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1,
+		   1),
+	TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
+		   CK_TOP_NETSYS_MCU_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1,
+		   1),
+	TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1,
+		   1),
+	TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
+		   1),
+	TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1",
+		   CK_TOP_USB_FRMCNT_P1_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL,
+		   1, 1),
+	TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1),
+	TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1),
+};
+
+/* TOPCKGEN MUX PARENTS */
+static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
+				      CK_TOP_CB_MM_D2 };
+
+static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
+					   CK_TOP_CB_NET1_D5,
+					   CK_TOP_NET1_D5_D2 };
+
+static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
+					 CK_TOP_CB_NET2_800M,
+					 CK_TOP_CB_MM_720M };
+
+static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4,
+					  CK_TOP_CB_NET1_D5 };
+
+static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
+
+static const int netsys_mcu_parents[] = {
+	CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M,
+	CK_TOP_CB_NET1_D4,  CK_TOP_CB_NET1_D5,   CK_TOP_CB_M_416M
+};
+
+static const int eip197_parents[] = {
+	CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M,
+	CK_TOP_CB_MM_720M,  CK_TOP_CB_NET1_D4,     CK_TOP_CB_NET1_D5
+};
+
+static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M,
+					 CK_TOP_NET1_D8_D2 };
+
+static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
+				    CK_TOP_M_D8_D2 };
+
+static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2,
+					 CK_TOP_CB_MM_D4 };
+
+static const int emmc_400m_parents[] = {
+	CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2,
+	CK_TOP_CB_M_D2,     CK_TOP_CB_MM_D4,     CK_TOP_NET1_D8_D2
+};
+
+static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
+				   CK_TOP_CB_MM_D4,    CK_TOP_NET1_D8_D2,
+				   CK_TOP_CB_NET2_D6,  CK_TOP_NET1_D5_D4,
+				   CK_TOP_CB_M_D4,     CK_TOP_NET1_D8_D4 };
+
+static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
+				     CK_TOP_NET1_D8_D2,  CK_TOP_CB_NET2_D6,
+				     CK_TOP_CB_M_D4,     CK_TOP_CB_MM_D8,
+				     CK_TOP_NET1_D8_D4,  CK_TOP_CB_M_D8 };
+
+static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
+				      CK_TOP_NET1_D5_D4,  CK_TOP_CB_M_D4,
+				      CK_TOP_CB_MM_D8,    CK_TOP_NET1_D8_D4,
+				      CK_TOP_MM_D6_D2,    CK_TOP_CB_M_D8 };
+
+static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
+				   CK_TOP_NET1_D5_D4,  CK_TOP_CB_M_D4,
+				   CK_TOP_M_D8_D2,     CK_TOP_CB_RTC_32K };
+
+static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
+				   CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+
+static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
+					       CK_TOP_NET1_D5_D2 };
+
+static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
+					   CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8,
+					   CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
+
+static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
+					  CK_TOP_CB_MM_D3_D5 };
+
+static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
+
+static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 };
+
+static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
+				     CK_TOP_M_D8_D2 };
+
+static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
+
+static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M,
+					      CK_TOP_NET1_D8_D4 };
+
+static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M };
+
+static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
+
+static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M,
+					     CK_TOP_NET2_D4_D4 };
+
+static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M,
+					    CK_TOP_CB_NET2_D4 };
+
+static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8,
+					 CK_TOP_NET1_D8_D16 };
+
+static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
+					CK_TOP_CB_NET2_D2 };
+
+static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M,
+					CK_TOP_CB_NET2_800M };
+
+static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
+					  CK_TOP_CB_WEDMCU_208M };
+
+static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M,
+					     CK_TOP_CB_NET2_D8 };
+
+static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M,
+						  CK_TOP_CB_NET1_D4 };
+
+static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M,
+				      CK_TOP_CB_NET1_D8 };
+
+static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M,
+						CK_TOP_CB_NET2_D2 };
+
+static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 };
+
+#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,    \
+		_shift, _width, _gate, _upd_ofs, _upd)                         \
+	{                                                                      \
+		.id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs,   \
+		.mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs,              \
+		.upd_shift = _upd, .mux_shift = _shift,                        \
+		.mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs,             \
+		.gate_shift = _gate, .parent = _parents,                       \
+		.num_parents = ARRAY_SIZE(_parents),                           \
+		.flags = CLK_MUX_SETCLR_UPD,                                   \
+	}
+
+/* TOPCKGEN MUX_GATE */
+static const struct mtk_composite topckgen_mtk_muxes[] = {
+	TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
+		0, 2, 7, 0x1c0, 0),
+	TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
+		0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1),
+	TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
+		0x4, 0x8, 16, 2, 23, 0x1c0, 2),
+	TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
+		0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3),
+	TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
+		0x14, 0x18, 0, 1, 7, 0x1c0, 4),
+	TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
+		0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5),
+	TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
+		netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6),
+	TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
+		0x18, 24, 3, 31, 0x1c0, 7),
+	TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
+		0x24, 0x28, 0, 1, 7, 0x1c0, 8),
+	TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
+		2, 15, 0x1c0, 9),
+	TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
+		0x24, 0x28, 16, 2, 23, 0x1c0, 10),
+	TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
+		0x24, 0x28, 24, 3, 31, 0x1c0, 11),
+	TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
+		7, 0x1c0, 12),
+	TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
+		0x38, 8, 3, 15, 0x1c0, 13),
+	TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
+		16, 3, 23, 0x1c0, 14),
+	TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
+		0x38, 24, 3, 31, 0x1c0, 15),
+	TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
+		7, 0x1c0, 16),
+	TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
+		15, 0x1c0, 17),
+	TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
+		pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0,
+		18),
+	TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
+		0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
+	TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
+		pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20),
+	TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
+		pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21),
+	TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
+		pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22),
+	TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
+		0x58, 24, 1, 31, 0x1c0, 23),
+	TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
+		0x64, 0x68, 0, 1, 7, 0x1c0, 24),
+	TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
+		0x64, 0x68, 8, 1, 15, 0x1c0, 25),
+	TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
+		0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26),
+	TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
+		0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27),
+	TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
+		usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28),
+	TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
+		15, 0x1c0, 29),
+	TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
+		16, 1, 23, 0x1c0, 30),
+	TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
+		24, 2, 31, 0x1c4, 0),
+	TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
+		0x88, 0, 1, 7, 0x1c4, 1),
+	TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
+		0x88, 8, 1, 15, 0x1c4, 2),
+	TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
+		0x88, 16, 1, 23, 0x1c4, 3),
+	TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
+		usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4),
+	TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
+		usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5),
+	TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
+		8, 1, 15, 0x1c4, 6),
+	TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
+		0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7),
+	TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
+		24, 1, 31, 0x1c4, 8),
+	TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
+		0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9),
+	TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
+		0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10),
+	TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
+		0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11),
+	TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
+		0xa8, 24, 1, 31, 0x1c4, 12),
+	TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
+		0xb8, 0, 1, 7, 0x1c4, 13),
+	TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
+		eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14),
+	TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
+		eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15),
+	TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
+		0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16),
+	TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
+		0xc4, 0xc8, 0, 2, 7, 0x1c4, 17),
+	TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
+		0xc4, 0xc8, 8, 2, 15, 0x1c4, 18),
+	TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
+		0xc4, 0xc8, 16, 1, 23, 0x1c4, 19),
+	TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
+		24, 1, 31, 0x1c4, 20),
+	TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
+		0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21),
+	TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
+		0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22),
+	TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
+		0xd8, 16, 1, 23, 0x1c4, 23),
+	TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
+		0xd8, 24, 1, 31, 0x1c4, 24),
+	TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
+		0xe8, 0, 1, 7, 0x1c4, 25),
+	TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
+		0xe8, 8, 1, 15, 0x1c4, 26),
+	TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
+		da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27),
+	TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
+		da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28),
+	TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
+		da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29),
+	TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
+		da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30),
+	TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
+		1, 23, 0x1c8, 0),
+	TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents,
+		0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1),
+	TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
+		0x108, 0, 1, 7, 0x1c8, 2),
+	TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
+		0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3),
+	TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
+		mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23,
+		0x1c8, 4),
+	TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
+		pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8,
+		5),
+	TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
+		0x118, 0, 2, 7, 0x1c8, 6),
+	TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
+		netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8,
+		7),
+	TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
+		pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8,
+		8),
+	TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
+		0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9),
+	TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
+		0x124, 0x128, 0, 1, 7, 0x1c8, 10),
+	TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel",
+		netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
+};
+
+/* INFRA FIXED DIV */
+static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = {
+	TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1,
+		   1),
+	TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1),
+	TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0",
+		   CK_TOP_PEXTP_TL_SEL, 1, 1),
+	TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1",
+		   CK_TOP_PEXTP_TL_P1_SEL, 1, 1),
+	TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2",
+		   CK_TOP_PEXTP_TL_P2_SEL, 1, 1),
+	TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3",
+		   CK_TOP_PEXTP_TL_P3_SEL, 1, 1),
+	TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
+	INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK,
+		     1, 1),
+	INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
+		     1),
+	TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1),
+	TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1),
+	TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1,
+		   1),
+	TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1),
+	TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1),
+	TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1),
+	TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1),
+	TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1),
+	TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1,
+		   1),
+	TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1),
+	TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1),
+	INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC,
+		     1, 1),
+	TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1),
+	TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1,
+		   1),
+	TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ",
+		   CK_TOP_EMMC_250M, 1, 1),
+	TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
+	TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1),
+	TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1),
+	TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o",
+		   CK_TOP_USB_FRMCNT, 1, 1),
+	TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1",
+		   CK_TOP_USB_FRMCNT_P1, 1, 1),
+	TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1,
+		   1),
+	TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1",
+		   CK_TOP_USB_XHCI_P1, 1, 1),
+	XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1),
+	XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1,
+		    1),
+	XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1),
+	XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1,
+		    1),
+	XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
+		    CLK_XTAL, 1, 1),
+	XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1",
+		    CLK_XTAL, 1, 1),
+	XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2",
+		    CLK_XTAL, 1, 1),
+	XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3",
+		    CLK_XTAL, 1, 1),
+	TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1),
+	TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1),
+	TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
+	TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1),
+	TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1,
+		   1),
+	TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1),
+	TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1",
+		   CK_TOP_USB_SYS_P1, 1, 1),
+};
+
+/* INFRASYS MUX PARENTS */
+static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M,
+					       CK_INFRA_UART_O0 };
+
+static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M,
+					       CK_INFRA_UART_O1 };
+
+static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M,
+					       CK_INFRA_UART_O2 };
+
+static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O };
+
+static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O };
+
+static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K,
+					     CK_INFRA_CK_F26M, CK_INFRA_66M_MCK,
+					     CK_INFRA_PWM_O };
+
+static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
+	CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
+	CK_INFRA_PCIE_OCC_P0
+};
+
+static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
+	CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
+	CK_INFRA_PCIE_OCC_P1
+};
+
+static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
+	CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
+	CK_INFRA_PCIE_OCC_P2
+};
+
+static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
+	CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
+	CK_INFRA_PCIE_OCC_P3
+};
+
+#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width)                  \
+	{                                                                      \
+		.id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0,   \
+		.mux_clr_reg = _reg + 0x4, .mux_shift = _shift,                \
+		.mux_mask = BIT(_width) - 1, .parent = _parents,               \
+		.num_parents = ARRAY_SIZE(_parents),                           \
+		.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS,             \
+	}
+
+/* INFRA MUX */
+static const struct mtk_composite infracfg_mtk_mux[] = {
+	INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
+		  infra_mux_uart0_parents, 0x10, 0, 1),
+	INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
+		  infra_mux_uart1_parents, 0x10, 1, 1),
+	INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
+		  infra_mux_uart2_parents, 0x10, 2, 1),
+	INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
+		  infra_mux_spi0_parents, 0x10, 4, 1),
+	INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
+		  infra_mux_spi1_parents, 0x10, 5, 1),
+	INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
+		  infra_mux_spi0_parents, 0x10, 6, 1),
+	INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
+		  0x10, 14, 2),
+	INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
+		  infra_pwm_bck_parents, 0x10, 16, 2),
+	INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
+		  infra_pwm_bck_parents, 0x10, 18, 2),
+	INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
+		  infra_pwm_bck_parents, 0x10, 20, 2),
+	INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
+		  infra_pwm_bck_parents, 0x10, 22, 2),
+	INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
+		  infra_pwm_bck_parents, 0x10, 24, 2),
+	INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
+		  infra_pwm_bck_parents, 0x10, 26, 2),
+	INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
+		  infra_pwm_bck_parents, 0x10, 28, 2),
+	INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
+		  infra_pwm_bck_parents, 0x10, 30, 2),
+	INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
+		  "infra_pcie_gfmux_tl_o_p0_sel",
+		  infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2),
+	INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
+		  "infra_pcie_gfmux_tl_o_p1_sel",
+		  infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2),
+	INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
+		  "infra_pcie_gfmux_tl_o_p2_sel",
+		  infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2),
+	INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
+		  "infra_pcie_gfmux_tl_o_p3_sel",
+		  infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2),
+};
+
+static const struct mtk_gate_regs infra_0_cg_regs = {
+	.set_ofs = 0x10,
+	.clr_ofs = 0x14,
+	.sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs infra_1_cg_regs = {
+	.set_ofs = 0x40,
+	.clr_ofs = 0x44,
+	.sta_ofs = 0x48,
+};
+
+static const struct mtk_gate_regs infra_2_cg_regs = {
+	.set_ofs = 0x50,
+	.clr_ofs = 0x54,
+	.sta_ofs = 0x58,
+};
+
+static const struct mtk_gate_regs infra_3_cg_regs = {
+	.set_ofs = 0x60,
+	.clr_ofs = 0x64,
+	.sta_ofs = 0x68,
+};
+
+#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .parent = _parent, .regs = &infra_0_cg_regs,        \
+		.shift = _shift,                                               \
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
+	}
+
+#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .parent = _parent, .regs = &infra_1_cg_regs,        \
+		.shift = _shift,                                               \
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
+	}
+
+#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .parent = _parent, .regs = &infra_2_cg_regs,        \
+		.shift = _shift,                                               \
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
+	}
+
+#define GATE_INFRA3(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .parent = _parent, .regs = &infra_3_cg_regs,        \
+		.shift = _shift,                                               \
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
+	}
+
+/* INFRA GATE */
+static const struct mtk_gate infracfg_mtk_gates[] = {
+	GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
+		    CK_INFRA_66M_MCK, 0),
+	GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
+		    CK_INFRA_66M_MCK, 1),
+	GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
+		    CK_INFRA_PWM_SEL, 2),
+	GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
+		    CK_INFRA_PWM_CK1_SEL, 3),
+	GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
+		    CK_INFRA_PWM_CK2_SEL, 4),
+	GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
+		    CK_INFRA_PWM_CK3_SEL, 5),
+	GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
+		    CK_INFRA_PWM_CK4_SEL, 6),
+	GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
+		    CK_INFRA_PWM_CK5_SEL, 7),
+	GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
+		    CK_INFRA_PWM_CK6_SEL, 8),
+	GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
+		    CK_INFRA_PWM_CK7_SEL, 9),
+	GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
+		    CK_INFRA_PWM_CK8_SEL, 10),
+	GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
+		    CK_INFRA_133M_MCK, 12),
+	GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
+		    CK_INFRA_66M_PHCK, 13),
+	GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14),
+	GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15),
+	GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O,
+		    16),
+	GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O,
+		    18),
+	GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M,
+		    19),
+	GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
+		    CK_INFRA_133M_MCK, 20),
+	GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
+		    CK_INFRA_66M_MCK, 21),
+	GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
+		    CK_INFRA_66M_MCK, 29),
+	GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
+		    CK_INFRA_CK_F26M, 30),
+	GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O,
+		    31),
+	GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
+		    CK_INFRA_CK_F26M, 0),
+	GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1),
+	GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
+		    CK_INFRA_66M_MCK, 3),
+	GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
+		    CK_INFRA_66M_MCK, 4),
+	GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
+		    CK_INFRA_66M_MCK, 5),
+	GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
+		    CK_INFRA_MUX_UART0_SEL, 3),
+	GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
+		    CK_INFRA_MUX_UART1_SEL, 4),
+	GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
+		    CK_INFRA_MUX_UART2_SEL, 5),
+	GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9),
+	GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10),
+	GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
+		    CK_INFRA_66M_MCK, 11),
+	GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
+		    CK_INFRA_MUX_SPI0_SEL, 12),
+	GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
+		    CK_INFRA_MUX_SPI1_SEL, 13),
+	GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
+		    CK_INFRA_MUX_SPI2_SEL, 14),
+	GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
+		    CK_INFRA_66M_MCK, 15),
+	GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
+		    CK_INFRA_66M_MCK, 16),
+	GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
+		    CK_INFRA_66M_MCK, 17),
+	GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
+		    CK_INFRA_66M_MCK, 18),
+	GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19),
+	GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
+		    CK_INFRA_F26M_O1, 20),
+	GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
+		    21),
+	GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O,
+		    22),
+	GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
+		    CK_INFRA_FMSDC2_HCK_OCC, 23),
+	GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
+		    CK_INFRA_PERI_133M, 24),
+	GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
+		    CK_INFRA_66M_PHCK, 25),
+	GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
+		    CK_INFRA_133M_MCK, 26),
+	GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O,
+		    27),
+	GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
+		    CK_INFRA_133M_MCK, 29),
+	GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
+		    CK_INFRA_66M_PHCK, 31),
+	GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
+		    CK_INFRA_133M_PHCK, 0),
+	GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
+		    CK_INFRA_133M_PHCK, 1),
+	GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
+		    CK_INFRA_66M_PHCK, 2),
+	GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
+		    CK_INFRA_66M_PHCK, 3),
+	GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4),
+	GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
+		    CK_INFRA_USB_SYS_O_P1, 5),
+	GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6),
+	GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1,
+		    7),
+	GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
+		    CK_INFRA_USB_FRMCNT_O, 8),
+	GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
+		    CK_INFRA_USB_FRMCNT_O_P1, 9),
+	GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O,
+		    10),
+	GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
+		    CK_INFRA_USB_PIPE_O_P1, 11),
+	GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O,
+		    12),
+	GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
+		    CK_INFRA_USB_UTMI_O_P1, 13),
+	GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O,
+		    14),
+	GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
+		    CK_INFRA_USB_XHCI_O_P1, 15),
+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
+		    CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
+		    CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
+		    CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
+		    CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
+		    CK_INFRA_PCIE_PIPE_OCC_P0, 24),
+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
+		    CK_INFRA_PCIE_PIPE_OCC_P1, 25),
+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
+		    CK_INFRA_PCIE_PIPE_OCC_P2, 26),
+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
+		    CK_INFRA_PCIE_PIPE_OCC_P3, 27),
+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
+		    CK_INFRA_133M_PHCK, 28),
+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
+		    CK_INFRA_133M_PHCK, 29),
+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
+		    CK_INFRA_133M_PHCK, 30),
+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
+		    CK_INFRA_133M_PHCK, 31),
+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
+		    "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7),
+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
+		    "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8),
+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
+		    "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9),
+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3,
+		    "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10),
+};
+
+static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
+	.fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
+	.fclks = apmixedsys_mtk_plls,
+	.xtal_rate = 40 * MHZ,
+};
+
+static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
+	.fdivs_offs = CK_TOP_CB_CKSQ_40M,
+	.muxes_offs = CK_TOP_NETSYS_SEL,
+	.fdivs = topckgen_mtk_fixed_factors,
+	.muxes = topckgen_mtk_muxes,
+	.flags = CLK_BYPASS_XTAL,
+	.xtal_rate = 40 * MHZ,
+};
+
+static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
+	.fdivs_offs = CK_INFRA_CK_F26M,
+	.muxes_offs = CK_INFRA_MUX_UART0_SEL,
+	.fdivs = infracfg_mtk_fixed_factor,
+	.muxes = infracfg_mtk_mux,
+	.flags = CLK_BYPASS_XTAL,
+	.xtal_rate = 40 * MHZ,
+};
+
+static const struct udevice_id mt7988_fixed_pll_compat[] = {
+	{ .compatible = "mediatek,mt7988-fixed-plls" },
+	{}
+};
+
+static const struct udevice_id mt7988_topckgen_compat[] = {
+	{ .compatible = "mediatek,mt7988-topckgen" },
+	{}
+};
+
+static int mt7988_fixed_pll_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt7988_fixed_pll_clk_tree);
+}
+
+static int mt7988_topckgen_probe(struct udevice *dev)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -ENOENT;
+
+	writel(MT7988_CLK_PDN_EN_WRITE, priv->base + MT7988_CLK_PDN);
+	return mtk_common_clk_init(dev, &mt7988_topckgen_clk_tree);
+}
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+	.name = "mt7988-clock-fixed-pll",
+	.id = UCLASS_CLK,
+	.of_match = mt7988_fixed_pll_compat,
+	.probe = mt7988_fixed_pll_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+	.name = "mt7988-clock-topckgen",
+	.id = UCLASS_CLK,
+	.of_match = mt7988_topckgen_compat,
+	.probe = mt7988_topckgen_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+static const struct udevice_id mt7988_infracfg_compat[] = {
+	{ .compatible = "mediatek,mt7988-infracfg" },
+	{}
+};
+
+static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = {
+	{ .compatible = "mediatek,mt7988-infracfg_ao_cgs" },
+	{}
+};
+
+static int mt7988_infracfg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree);
+}
+
+static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree,
+					infracfg_mtk_gates);
+}
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+	.name = "mt7988-clock-infracfg",
+	.id = UCLASS_CLK,
+	.of_match = mt7988_infracfg_compat,
+	.probe = mt7988_infracfg_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_infrasys_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = {
+	.name = "mt7988-clock-infracfg_ao_cgs",
+	.id = UCLASS_CLK,
+	.of_match = mt7988_infracfg_ao_cgs_compat,
+	.probe = mt7988_infracfg_ao_cgs_probe,
+	.priv_auto = sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+/* ETHDMA */
+
+static const struct mtk_gate_regs ethdma_cg_regs = {
+	.set_ofs = 0x30,
+	.clr_ofs = 0x30,
+	.sta_ofs = 0x30,
+};
+
+#define GATE_ETHDMA(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .parent = _parent, .regs = &ethdma_cg_regs,         \
+		.shift = _shift,                                               \
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
+	}
+
+static const struct mtk_gate ethdma_mtk_gate[] = {
+	GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6),
+};
+
+static int mt7988_ethdma_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
+					ethdma_mtk_gate);
+}
+
+static int mt7988_ethdma_bind(struct udevice *dev)
+{
+	int ret = 0;
+
+	if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
+		ret = mediatek_reset_bind(dev, MT7988_ETHDMA_RST_CTRL_OFS, 1);
+		if (ret)
+			debug("Warning: failed to bind reset controller\n");
+	}
+
+	return ret;
+}
+
+static const struct udevice_id mt7988_ethdma_compat[] = {
+	{
+		.compatible = "mediatek,mt7988-ethdma",
+	},
+	{}
+};
+
+U_BOOT_DRIVER(mtk_clk_ethdma) = {
+	.name = "mt7988-clock-ethdma",
+	.id = UCLASS_CLK,
+	.of_match = mt7988_ethdma_compat,
+	.probe = mt7988_ethdma_probe,
+	.bind = mt7988_ethdma_bind,
+	.priv_auto = sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
+
+/* SGMIISYS_0 */
+
+static const struct mtk_gate_regs sgmii0_cg_regs = {
+	.set_ofs = 0xE4,
+	.clr_ofs = 0xE4,
+	.sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII0(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .parent = _parent, .regs = &sgmii0_cg_regs,         \
+		.shift = _shift,                                               \
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
+	}
+
+static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
+	/* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
+	GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2),
+	/* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
+	GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3),
+};
+
+static int mt7988_sgmiisys_0_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
+					sgmiisys_0_mtk_gate);
+}
+
+static const struct udevice_id mt7988_sgmiisys_0_compat[] = {
+	{
+		.compatible = "mediatek,mt7988-sgmiisys_0",
+	},
+	{}
+};
+
+U_BOOT_DRIVER(mtk_clk_sgmiisys_0) = {
+	.name = "mt7988-clock-sgmiisys_0",
+	.id = UCLASS_CLK,
+	.of_match = mt7988_sgmiisys_0_compat,
+	.probe = mt7988_sgmiisys_0_probe,
+	.priv_auto = sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
+
+/* SGMIISYS_1 */
+
+static const struct mtk_gate_regs sgmii1_cg_regs = {
+	.set_ofs = 0xE4,
+	.clr_ofs = 0xE4,
+	.sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII1(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .parent = _parent, .regs = &sgmii1_cg_regs,         \
+		.shift = _shift,                                               \
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
+	}
+
+static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
+	/* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
+	GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2),
+	/* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
+	GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3),
+};
+
+static int mt7988_sgmiisys_1_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
+					sgmiisys_1_mtk_gate);
+}
+
+static const struct udevice_id mt7988_sgmiisys_1_compat[] = {
+	{
+		.compatible = "mediatek,mt7988-sgmiisys_1",
+	},
+	{}
+};
+
+U_BOOT_DRIVER(mtk_clk_sgmiisys_1) = {
+	.name = "mt7988-clock-sgmiisys_1",
+	.id = UCLASS_CLK,
+	.of_match = mt7988_sgmiisys_1_compat,
+	.probe = mt7988_sgmiisys_1_probe,
+	.priv_auto = sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
+
+/* ETHWARP */
+
+static const struct mtk_gate_regs ethwarp_cg_regs = {
+	.set_ofs = 0x14,
+	.clr_ofs = 0x14,
+	.sta_ofs = 0x14,
+};
+
+#define GATE_ETHWARP(_id, _name, _parent, _shift)                              \
+	{                                                                      \
+		.id = _id, .parent = _parent, .regs = &ethwarp_cg_regs,        \
+		.shift = _shift,                                               \
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
+	}
+
+static const struct mtk_gate ethwarp_mtk_gate[] = {
+	GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
+		     CK_TOP_NETSYS_WED_MCU, 13),
+	GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
+		     CK_TOP_NETSYS_WED_MCU, 14),
+	GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
+		     CK_TOP_NETSYS_WED_MCU, 15),
+};
+
+static int mt7988_ethwarp_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
+					ethwarp_mtk_gate);
+}
+
+static int mt7988_ethwarp_bind(struct udevice *dev)
+{
+	int ret = 0;
+
+	if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
+		ret = mediatek_reset_bind(dev, MT7988_ETHWARP_RST_CTRL_OFS, 2);
+		if (ret)
+			debug("Warning: failed to bind reset controller\n");
+	}
+
+	return ret;
+}
+
+static const struct udevice_id mt7988_ethwarp_compat[] = {
+	{
+		.compatible = "mediatek,mt7988-ethwarp",
+	},
+	{}
+};
+
+U_BOOT_DRIVER(mtk_clk_ethwarp) = {
+	.name = "mt7988-clock-ethwarp",
+	.id = UCLASS_CLK,
+	.of_match = mt7988_ethwarp_compat,
+	.probe = mt7988_ethwarp_probe,
+	.bind = mt7988_ethwarp_bind,
+	.priv_auto = sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c
index 64f33587e2..d0a3f65446 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -150,7 +150,7 @@ static ulong rk3308_i2c_get_clk(struct clk *clk)
 	}
 
 	con = readl(&cru->clksel_con[con_id]);
-	div = con >> CLK_I2C_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
+	div = (con & CLK_I2C_DIV_CON_MASK) >> CLK_I2C_DIV_CON_SHIFT;
 
 	return DIV_TO_RATE(priv->dpll_hz, div);
 }
@@ -314,7 +314,7 @@ static ulong rk3308_saradc_get_clk(struct clk *clk)
 	u32 div, con;
 
 	con = readl(&cru->clksel_con[34]);
-	div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
+	div = (con & CLK_SARADC_DIV_CON_MASK) >> CLK_SARADC_DIV_CON_SHIFT;
 
 	return DIV_TO_RATE(OSC_HZ, div);
 }
@@ -342,7 +342,7 @@ static ulong rk3308_tsadc_get_clk(struct clk *clk)
 	u32 div, con;
 
 	con = readl(&cru->clksel_con[33]);
-	div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
+	div = (con & CLK_SARADC_DIV_CON_MASK) >> CLK_SARADC_DIV_CON_SHIFT;
 
 	return DIV_TO_RATE(OSC_HZ, div);
 }
@@ -385,7 +385,7 @@ static ulong rk3308_spi_get_clk(struct clk *clk)
 	}
 
 	con = readl(&cru->clksel_con[con_id]);
-	div = con >> CLK_SPI_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK;
+	div = (con & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
 
 	return DIV_TO_RATE(priv->dpll_hz, div);
 }
@@ -429,7 +429,7 @@ static ulong rk3308_pwm_get_clk(struct clk *clk)
 	u32 div, con;
 
 	con = readl(&cru->clksel_con[29]);
-	div = con >> CLK_PWM_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK;
+	div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
 
 	return DIV_TO_RATE(priv->dpll_hz, div);
 }
@@ -451,6 +451,58 @@ static ulong rk3308_pwm_set_clk(struct clk *clk, uint hz)
 	return rk3308_pwm_get_clk(clk);
 }
 
+static ulong rk3308_uart_get_clk(struct clk *clk)
+{
+	struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
+	struct rk3308_cru *cru = priv->cru;
+	u32 div, pll_sel, con, con_id, parent;
+
+	switch (clk->id) {
+	case SCLK_UART0:
+		con_id = 10;
+		break;
+	case SCLK_UART1:
+		con_id = 13;
+		break;
+	case SCLK_UART2:
+		con_id = 16;
+		break;
+	case SCLK_UART3:
+		con_id = 19;
+		break;
+	case SCLK_UART4:
+		con_id = 22;
+		break;
+	default:
+		printf("do not support this uart interface\n");
+		return -EINVAL;
+	}
+
+	con = readl(&cru->clksel_con[con_id]);
+	pll_sel = (con & CLK_UART_PLL_SEL_MASK) >> CLK_UART_PLL_SEL_SHIFT;
+	div = (con & CLK_UART_DIV_CON_MASK) >> CLK_UART_DIV_CON_SHIFT;
+
+	switch (pll_sel) {
+	case CLK_UART_PLL_SEL_DPLL:
+		parent = priv->dpll_hz;
+		break;
+	case CLK_UART_PLL_SEL_VPLL0:
+		parent = priv->vpll0_hz;
+		break;
+	case CLK_UART_PLL_SEL_VPLL1:
+		parent = priv->vpll0_hz;
+		break;
+	case CLK_UART_PLL_SEL_24M:
+		parent = OSC_HZ;
+		break;
+	default:
+		printf("do not support this uart pll sel\n");
+		return -EINVAL;
+	}
+
+	return DIV_TO_RATE(parent, div);
+}
+
 static ulong rk3308_vop_get_clk(struct clk *clk)
 {
 	struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
@@ -813,6 +865,13 @@ static ulong rk3308_clk_get_rate(struct clk *clk)
 	case SCLK_EMMC_SAMPLE:
 		rate = rk3308_mmc_get_clk(clk);
 		break;
+	case SCLK_UART0:
+	case SCLK_UART1:
+	case SCLK_UART2:
+	case SCLK_UART3:
+	case SCLK_UART4:
+		rate = rk3308_uart_get_clk(clk);
+		break;
 	case SCLK_I2C0:
 	case SCLK_I2C1:
 	case SCLK_I2C2:
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 969b7a8581..ef97381f0e 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -681,6 +681,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
 	case ACLK_GMAC:
 	case PCLK_GMAC:
 	case SCLK_USB3OTG_SUSPEND:
+	case USB480M:
 		return 0;
 	default:
 		return -ENOENT;
@@ -771,6 +772,7 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
 	case SCLK_MAC2IO_EXT:
 		return rk3328_gmac2io_ext_set_parent(clk, parent);
 	case DCLK_LCDC:
+	case USB480M:
 	case SCLK_PDM:
 	case SCLK_RTC32K:
 	case SCLK_UART0:
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 6bdd96f35b..599b7b130e 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -427,6 +427,7 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate)
 		break;
 	case CLK_PCIEPHY0_REF:
 	case CLK_PCIEPHY1_REF:
+	case CLK_PCIEPHY2_REF:
 		return 0;
 	default:
 		return -ENOENT;
@@ -701,7 +702,10 @@ static ulong rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv,
 	}
 
 	div = DIV_ROUND_UP(priv->cpll_hz, rate);
-	assert(div - 1 <= 31);
+	if (clk_id == CPLL_25M)
+		assert(div - 1 <= 63);
+	else
+		assert(div - 1 <= 31);
 	rk_clrsetreg(&cru->clksel_con[con],
 		     mask, (div - 1) << shift);
 	return rk3568_cpll_div_get_rate(priv, clk_id);
@@ -1141,7 +1145,7 @@ static ulong rk3568_pwm_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 
 	switch (clk_id) {
 	case CLK_PWM1:
-		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
+		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
 		break;
 	case CLK_PWM2:
 		sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
@@ -2185,6 +2189,7 @@ static ulong rk3568_rkvdec_set_clk(struct rk3568_clk_priv *priv,
 
 	return rk3568_rkvdec_get_clk(priv, clk_id);
 }
+#endif
 
 static ulong rk3568_uart_get_rate(struct rk3568_clk_priv *priv, ulong clk_id)
 {
@@ -2320,7 +2325,6 @@ static ulong rk3568_uart_set_rate(struct rk3568_clk_priv *priv,
 
 	return rk3568_uart_get_rate(priv, clk_id);
 }
-#endif
 
 static ulong rk3568_clk_get_rate(struct clk *clk)
 {
@@ -2459,6 +2463,7 @@ static ulong rk3568_clk_get_rate(struct clk *clk)
 	case TCLK_WDT_NS:
 		rate = OSC_HZ;
 		break;
+#endif
 	case SCLK_UART1:
 	case SCLK_UART2:
 	case SCLK_UART3:
@@ -2470,7 +2475,6 @@ static ulong rk3568_clk_get_rate(struct clk *clk)
 	case SCLK_UART9:
 		rate = rk3568_uart_get_rate(priv, clk->id);
 		break;
-#endif
 	case ACLK_SECURE_FLASH:
 	case ACLK_CRYPTO_NS:
 	case HCLK_SECURE_FLASH:
@@ -2644,6 +2648,7 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
 	case TCLK_WDT_NS:
 		ret = OSC_HZ;
 		break;
+#endif
 	case SCLK_UART1:
 	case SCLK_UART2:
 	case SCLK_UART3:
@@ -2655,7 +2660,6 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
 	case SCLK_UART9:
 		ret = rk3568_uart_set_rate(priv, clk->id, rate);
 		break;
-#endif
 	case ACLK_SECURE_FLASH:
 	case ACLK_CRYPTO_NS:
 	case HCLK_SECURE_FLASH:
@@ -2839,6 +2843,10 @@ static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent)
 	case CLK_RKVDEC_CORE:
 		return rk3568_rkvdec_set_parent(clk, parent);
 	case I2S1_MCLKOUT_TX:
+	case SCLK_GMAC0_RGMII_SPEED:
+	case SCLK_GMAC0_RMII_SPEED:
+	case SCLK_GMAC1_RGMII_SPEED:
+	case SCLK_GMAC1_RMII_SPEED:
 		break;
 	default:
 		return -ENOENT;
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index 51348b1ddc..84859d92ab 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -1,5 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-obj-y += sifive-prci.o
-
-obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o fu740-prci.o
+obj-$(CONFIG_CLK_SIFIVE_PRCI) +=  sifive-prci.o fu540-prci.o fu740-prci.o
diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c
index 02e6d9000e..1568a1f4cd 100644
--- a/drivers/clk/starfive/clk-jh7110-pll.c
+++ b/drivers/clk/starfive/clk-jh7110-pll.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2022-23 StarFive Technology Co., Ltd.
  *
  * Author:	Yanhong Wang <yanhong.wang@starfivetech.com>
+ *		Xingyu Wu <xingyu.wu@starfivetech.com>
  */
 
 #include <common.h>
@@ -11,6 +12,8 @@
 #include <clk-uclass.h>
 #include <div64.h>
 #include <dm/device.h>
+#include <dm/read.h>
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
 #include <linux/bitops.h>
 #include <linux/clk-provider.h>
 #include <linux/delay.h>
@@ -30,6 +33,47 @@
 #define CLK_DDR_BUS_PLL1_DIV4	2
 #define CLK_DDR_BUS_PLL1_DIV8	3
 
+#define JH7110_PLL_ID_TRANS(id)	((id) + JH7110_EXTCLK_END)
+
+enum starfive_pll_type {
+	PLL0 = 0,
+	PLL1,
+	PLL2,
+	PLL_MAX = PLL2
+};
+
+struct starfive_pllx_rate {
+	u64 rate;
+	u32 prediv;
+	u32 fbdiv;
+	u32 frac;
+};
+
+struct starfive_pllx_offset {
+	u32 pd;
+	u32 prediv;
+	u32 fbdiv;
+	u32 frac;
+	u32 postdiv1;
+	u32 dacpd;
+	u32 dsmpd;
+	u32 pd_mask;
+	u32 prediv_mask;
+	u32 fbdiv_mask;
+	u32 frac_mask;
+	u32 postdiv1_mask;
+	u32 dacpd_mask;
+	u32 dsmpd_mask;
+};
+
+struct starfive_pllx_clk {
+	enum starfive_pll_type type;
+	const struct starfive_pllx_offset *offset;
+	const struct starfive_pllx_rate *rate_table;
+	int rate_count;
+	int flags;
+};
+
 struct clk_jh7110_pllx {
 	struct clk		clk;
 	void __iomem	*base;
@@ -185,7 +229,7 @@ static void jh7110_pll_set_rate(struct clk_jh7110_pllx *pll,
 	PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, 1);
 	PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv);
 	PLLX_SET(pll->offset->fbdiv, pll->offset->fbdiv_mask, rate->fbdiv);
-	PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1, 0);
+	PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1_mask, 0);
 	PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_ON);
 
 	if (set) {
@@ -271,7 +315,7 @@ static ulong jh7110_pllx_set_rate(struct clk *clk, ulong drate)
 	return jh7110_pllx_recalc_rate(clk);
 }
 
-static const struct clk_ops clk_jh7110_ops = {
+static const struct clk_ops jh7110_clk_pllx_ops = {
 	.set_rate	= jh7110_pllx_set_rate,
 	.get_rate	= jh7110_pllx_recalc_rate,
 };
@@ -314,8 +358,63 @@ struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
 	return clk;
 }
 
+/* PLLx clock implementation */
 U_BOOT_DRIVER(jh7110_clk_pllx) = {
 	.name	= UBOOT_DM_CLK_JH7110_PLLX,
 	.id	= UCLASS_CLK,
-	.ops	= &clk_jh7110_ops,
+	.ops	= &jh7110_clk_pllx_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+};
+
+static int jh7110_pll_clk_probe(struct udevice *dev)
+{
+	void __iomem *reg =  (void __iomem *)dev_read_addr_ptr(dev->parent);
+	fdt_addr_t sysreg = ofnode_get_addr(ofnode_by_compatible(ofnode_null(),
+					    "starfive,jh7110-syscrg"));
+
+	if (sysreg == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL0_OUT),
+	       starfive_jh7110_pll("pll0_out", "oscillator", reg,
+				   (void __iomem *)sysreg, &starfive_jh7110_pll0));
+	clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL1_OUT),
+	       starfive_jh7110_pll("pll1_out", "oscillator", reg,
+				   (void __iomem *)sysreg, &starfive_jh7110_pll1));
+	clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL2_OUT),
+	       starfive_jh7110_pll("pll2_out", "oscillator", reg,
+				   (void __iomem *)sysreg, &starfive_jh7110_pll2));
+
+	return 0;
+}
+
+static int jh7110_pll_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+	if (args->args_count > 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (args->args_count)
+		clk->id = JH7110_PLL_ID_TRANS(args->args[0]);
+	else
+		clk->id = 0;
+
+	return 0;
+}
+
+static const struct udevice_id jh7110_pll_clk_of_match[] = {
+	{ .compatible = "starfive,jh7110-pll", },
+	{ }
+};
+
+JH7110_CLK_OPS(pll);
+
+/* PLL clk device */
+U_BOOT_DRIVER(jh7110_pll_clk) = {
+	.name	= "jh7110_pll_clk",
+	.id	= UCLASS_CLK,
+	.of_match	= jh7110_pll_clk_of_match,
+	.probe	= jh7110_pll_clk_probe,
+	.ops	= &jh7110_pll_clk_ops,
 };
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index a74b70906a..31aaf3340f 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2022-23 StarFive Technology Co., Ltd.
  *
  * Author:	Yanhong Wang <yanhong.wang@starfivetech.com>
+ *		Xingyu Wu <xingyu.wu@starfivetech.com>
  */
 
 #include <common.h>
@@ -24,8 +25,10 @@
 #define STARFIVE_CLK_DIV_SHIFT		0  /* [23:0] */
 
 #define OFFSET(id) ((id) * 4)
-#define AONOFFSET(id) (((id) - JH7110_SYSCLK_END) * 4)
-#define STGOFFSET(id) (((id) - JH7110_AONCLK_END) * 4)
+
+#define JH7110_SYS_ID_TRANS(id) ((id) + JH7110_PLLCLK_END + JH7110_EXTCLK_END)
+#define JH7110_AON_ID_TRANS(id) ((id) + JH7110_SYS_ID_TRANS(JH7110_SYSCLK_END))
+#define JH7110_STG_ID_TRANS(id) ((id) + JH7110_AON_ID_TRANS(JH7110_AONCLK_END))
 
 typedef int (*jh1710_init_fn)(struct udevice *dev);
 
@@ -230,224 +233,204 @@ static struct clk *starfive_clk_gate_divider(void __iomem *reg,
 static int jh7110_syscrg_init(struct udevice *dev)
 {
 	struct jh7110_clk_priv *priv = dev_get_priv(dev);
-	struct ofnode_phandle_args args;
-	fdt_addr_t addr;
 	struct clk *pclk;
-	int ret;
-
-	ret = ofnode_parse_phandle_with_args(dev->node_, "starfive,sys-syscon", NULL, 0, 0, &args);
-	if (ret)
-		return ret;
-
-	addr =  ofnode_get_addr(args.node);
-	if (addr == FDT_ADDR_T_NONE)
-		return -EINVAL;
 
-	clk_dm(JH7110_SYSCLK_PLL0_OUT,
-	       starfive_jh7110_pll("pll0_out", "oscillator", (void __iomem *)addr,
-				   priv->reg, &starfive_jh7110_pll0));
-	clk_dm(JH7110_SYSCLK_PLL1_OUT,
-	       starfive_jh7110_pll("pll1_out", "oscillator", (void __iomem *)addr,
-				   priv->reg, &starfive_jh7110_pll1));
-	clk_dm(JH7110_SYSCLK_PLL2_OUT,
-	       starfive_jh7110_pll("pll2_out", "oscillator", (void __iomem *)addr,
-				   priv->reg, &starfive_jh7110_pll2));
-	clk_dm(JH7110_SYSCLK_CPU_ROOT,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_CPU_ROOT),
 	       starfive_clk_mux(priv->reg, "cpu_root",
 				OFFSET(JH7110_SYSCLK_CPU_ROOT), 1,
 				cpu_root_sels, ARRAY_SIZE(cpu_root_sels)));
-	clk_dm(JH7110_SYSCLK_CPU_CORE,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_CPU_CORE),
 	       starfive_clk_divider(priv->reg,
 				    "cpu_core", "cpu_root",
 				    OFFSET(JH7110_SYSCLK_CPU_CORE), 3));
-	clk_dm(JH7110_SYSCLK_CPU_BUS,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_CPU_BUS),
 	       starfive_clk_divider(priv->reg,
 				    "cpu_bus", "cpu_core",
 				    OFFSET(JH7110_SYSCLK_CPU_BUS), 2));
-	clk_dm(JH7110_SYSCLK_PERH_ROOT,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_PERH_ROOT),
 	       starfive_clk_composite(priv->reg,
 				      "perh_root",
 				      perh_root_sels, ARRAY_SIZE(perh_root_sels),
 				      OFFSET(JH7110_SYSCLK_PERH_ROOT), 1, 0, 2));
-	clk_dm(JH7110_SYSCLK_BUS_ROOT,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_BUS_ROOT),
 	       starfive_clk_mux(priv->reg, "bus_root",
 				OFFSET(JH7110_SYSCLK_BUS_ROOT), 1,
 				bus_root_sels,	ARRAY_SIZE(bus_root_sels)));
-	clk_dm(JH7110_SYSCLK_NOCSTG_BUS,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_NOCSTG_BUS),
 	       starfive_clk_divider(priv->reg,
 				    "nocstg_bus", "bus_root",
 				    OFFSET(JH7110_SYSCLK_NOCSTG_BUS), 3));
-	clk_dm(JH7110_SYSCLK_AXI_CFG0,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_AXI_CFG0),
 	       starfive_clk_divider(priv->reg,
 				    "axi_cfg0", "bus_root",
 				    OFFSET(JH7110_SYSCLK_AXI_CFG0), 2));
-	clk_dm(JH7110_SYSCLK_STG_AXIAHB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_STG_AXIAHB),
 	       starfive_clk_divider(priv->reg,
 				    "stg_axiahb", "axi_cfg0",
 				    OFFSET(JH7110_SYSCLK_STG_AXIAHB), 2));
-	clk_dm(JH7110_SYSCLK_AHB0,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_AHB0),
 	       starfive_clk_gate(priv->reg,
 				 "ahb0", "stg_axiahb",
 				 OFFSET(JH7110_SYSCLK_AHB0)));
-	clk_dm(JH7110_SYSCLK_AHB1,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_AHB1),
 	       starfive_clk_gate(priv->reg,
 				 "ahb1", "stg_axiahb",
 				 OFFSET(JH7110_SYSCLK_AHB1)));
-	clk_dm(JH7110_SYSCLK_APB_BUS,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_APB_BUS),
 	       starfive_clk_divider(priv->reg,
 				    "apb_bus", "stg_axiahb",
 				    OFFSET(JH7110_SYSCLK_APB_BUS), 4));
-	clk_dm(JH7110_SYSCLK_APB0,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_APB0),
 	       starfive_clk_gate(priv->reg,
 				 "apb0", "apb_bus",
 				 OFFSET(JH7110_SYSCLK_APB0)));
-	clk_dm(JH7110_SYSCLK_QSPI_AHB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_QSPI_AHB),
 	       starfive_clk_gate(priv->reg,
 				 "qspi_ahb", "ahb1",
 				 OFFSET(JH7110_SYSCLK_QSPI_AHB)));
-	clk_dm(JH7110_SYSCLK_QSPI_APB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_QSPI_APB),
 	       starfive_clk_gate(priv->reg,
 				 "qspi_apb", "apb_bus",
 				 OFFSET(JH7110_SYSCLK_QSPI_APB)));
-	clk_dm(JH7110_SYSCLK_QSPI_REF_SRC,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_QSPI_REF_SRC),
 	       starfive_clk_divider(priv->reg,
 				    "qspi_ref_src", "pll0_out",
 				    OFFSET(JH7110_SYSCLK_QSPI_REF_SRC), 5));
-	clk_dm(JH7110_SYSCLK_QSPI_REF,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_QSPI_REF),
 	       starfive_clk_composite(priv->reg,
 				      "qspi_ref",
 				      qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels),
 				      OFFSET(JH7110_SYSCLK_QSPI_REF), 1, 1, 0));
-	clk_dm(JH7110_SYSCLK_SDIO0_AHB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_SDIO0_AHB),
 	       starfive_clk_gate(priv->reg,
 				 "sdio0_ahb", "ahb0",
 				 OFFSET(JH7110_SYSCLK_SDIO0_AHB)));
-	clk_dm(JH7110_SYSCLK_SDIO1_AHB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_SDIO1_AHB),
 	       starfive_clk_gate(priv->reg,
 				 "sdio1_ahb", "ahb0",
 				 OFFSET(JH7110_SYSCLK_SDIO1_AHB)));
-	clk_dm(JH7110_SYSCLK_SDIO0_SDCARD,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_SDIO0_SDCARD),
 	       starfive_clk_fix_parent_composite(priv->reg,
 						 "sdio0_sdcard", "axi_cfg0",
 						 OFFSET(JH7110_SYSCLK_SDIO0_SDCARD), 0, 1, 4));
-	clk_dm(JH7110_SYSCLK_SDIO1_SDCARD,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_SDIO1_SDCARD),
 	       starfive_clk_fix_parent_composite(priv->reg,
 						 "sdio1_sdcard", "axi_cfg0",
 						 OFFSET(JH7110_SYSCLK_SDIO1_SDCARD), 0, 1, 4));
-	clk_dm(JH7110_SYSCLK_USB_125M,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_USB_125M),
 	       starfive_clk_divider(priv->reg,
 				    "usb_125m", "pll0_out",
 				    OFFSET(JH7110_SYSCLK_USB_125M), 4));
-	clk_dm(JH7110_SYSCLK_NOC_BUS_STG_AXI,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_NOC_BUS_STG_AXI),
 	       starfive_clk_gate(priv->reg,
 				 "noc_bus_stg_axi", "nocstg_bus",
 				 OFFSET(JH7110_SYSCLK_NOC_BUS_STG_AXI)));
-	clk_dm(JH7110_SYSCLK_GMAC1_AHB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_AHB),
 	       starfive_clk_gate(priv->reg,
 				 "gmac1_ahb", "ahb0",
 				 OFFSET(JH7110_SYSCLK_GMAC1_AHB)));
-	clk_dm(JH7110_SYSCLK_GMAC1_AXI,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_AXI),
 	       starfive_clk_gate(priv->reg,
 				 "gmac1_axi", "stg_axiahb",
 				 OFFSET(JH7110_SYSCLK_GMAC1_AXI)));
-	clk_dm(JH7110_SYSCLK_GMAC_SRC,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC_SRC),
 	       starfive_clk_divider(priv->reg,
 				    "gmac_src", "pll0_out",
 				    OFFSET(JH7110_SYSCLK_GMAC_SRC), 3));
-	clk_dm(JH7110_SYSCLK_GMAC1_GTXCLK,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_GTXCLK),
 	       starfive_clk_divider(priv->reg,
 				    "gmac1_gtxclk", "pll0_out",
 				    OFFSET(JH7110_SYSCLK_GMAC1_GTXCLK), 4));
-	clk_dm(JH7110_SYSCLK_GMAC1_GTXC,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_GTXC),
 	       starfive_clk_gate(priv->reg,
 				 "gmac1_gtxc", "gmac1_gtxclk",
 				 OFFSET(JH7110_SYSCLK_GMAC1_GTXC)));
-	clk_dm(JH7110_SYSCLK_GMAC1_RMII_RTX,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_RMII_RTX),
 	       starfive_clk_divider(priv->reg,
 				    "gmac1_rmii_rtx", "gmac1-rmii-refin-clock",
 				    OFFSET(JH7110_SYSCLK_GMAC1_RMII_RTX), 5));
-	clk_dm(JH7110_SYSCLK_GMAC1_PTP,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_PTP),
 	       starfive_clk_gate_divider(priv->reg,
 					 "gmac1_ptp", "gmac_src",
 					 OFFSET(JH7110_SYSCLK_GMAC1_PTP), 5));
-	clk_dm(JH7110_SYSCLK_GMAC1_RX,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_RX),
 	       starfive_clk_mux(priv->reg, "gmac1_rx",
 				OFFSET(JH7110_SYSCLK_GMAC1_RX), 1,
 				gmac1_rx_sels,	ARRAY_SIZE(gmac1_rx_sels)));
-	clk_dm(JH7110_SYSCLK_GMAC1_TX,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_TX),
 	       starfive_clk_composite(priv->reg,
 				      "gmac1_tx",
 				      gmac1_tx_sels, ARRAY_SIZE(gmac1_tx_sels),
 				      OFFSET(JH7110_SYSCLK_GMAC1_TX), 1, 1, 0));
-	clk_dm(JH7110_SYSCLK_GMAC1_TX_INV,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_TX_INV),
 	       starfive_clk_inv(priv->reg,
 				"gmac1_tx_inv", "gmac1_tx",
 				OFFSET(JH7110_SYSCLK_GMAC1_TX_INV)));
-	clk_dm(JH7110_SYSCLK_GMAC0_GTXCLK,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC0_GTXCLK),
 	       starfive_clk_gate_divider(priv->reg,
 					 "gmac0_gtxclk", "pll0_out",
 					 OFFSET(JH7110_SYSCLK_GMAC0_GTXCLK), 4));
-	clk_dm(JH7110_SYSCLK_GMAC0_PTP,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC0_PTP),
 	       starfive_clk_gate_divider(priv->reg,
 					 "gmac0_ptp", "gmac_src",
 					 OFFSET(JH7110_SYSCLK_GMAC0_PTP), 5));
-	clk_dm(JH7110_SYSCLK_GMAC0_GTXC,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC0_GTXC),
 	       starfive_clk_gate(priv->reg,
 				 "gmac0_gtxc", "gmac0_gtxclk",
 				 OFFSET(JH7110_SYSCLK_GMAC0_GTXC)));
-	clk_dm(JH7110_SYSCLK_UART0_APB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART0_APB),
 	       starfive_clk_gate(priv->reg,
 				 "uart0_apb", "apb0",
 				 OFFSET(JH7110_SYSCLK_UART0_APB)));
-	clk_dm(JH7110_SYSCLK_UART0_CORE,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART0_CORE),
 	       starfive_clk_gate(priv->reg,
 				 "uart0_core", "oscillator",
 				 OFFSET(JH7110_SYSCLK_UART0_CORE)));
-	clk_dm(JH7110_SYSCLK_UART1_APB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART1_APB),
 	       starfive_clk_gate(priv->reg,
 				 "uart1_apb", "apb0",
 				 OFFSET(JH7110_SYSCLK_UART1_APB)));
-	clk_dm(JH7110_SYSCLK_UART1_CORE,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART1_CORE),
 	       starfive_clk_gate(priv->reg,
 				 "uart1_core", "oscillator",
 				 OFFSET(JH7110_SYSCLK_UART1_CORE)));
-	clk_dm(JH7110_SYSCLK_UART2_APB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART2_APB),
 	       starfive_clk_gate(priv->reg,
 				 "uart2_apb", "apb0",
 				 OFFSET(JH7110_SYSCLK_UART2_APB)));
-	clk_dm(JH7110_SYSCLK_UART2_CORE,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART2_CORE),
 	       starfive_clk_gate(priv->reg,
 				 "uart2_core", "oscillator",
 				 OFFSET(JH7110_SYSCLK_UART2_CORE)));
-	clk_dm(JH7110_SYSCLK_UART3_APB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART3_APB),
 	       starfive_clk_gate(priv->reg,
 				 "uart3_apb", "apb0",
 				 OFFSET(JH7110_SYSCLK_UART3_APB)));
-	clk_dm(JH7110_SYSCLK_UART3_CORE,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART3_CORE),
 	       starfive_clk_gate_divider(priv->reg,
 					 "uart3_core", "perh_root",
 					 OFFSET(JH7110_SYSCLK_UART3_CORE), 8));
-	clk_dm(JH7110_SYSCLK_UART4_APB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART4_APB),
 	       starfive_clk_gate(priv->reg,
 				 "uart4_apb", "apb0",
 				 OFFSET(JH7110_SYSCLK_UART4_APB)));
-	clk_dm(JH7110_SYSCLK_UART4_CORE,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART4_CORE),
 	       starfive_clk_gate_divider(priv->reg,
 					 "uart4_core", "perh_root",
 					 OFFSET(JH7110_SYSCLK_UART4_CORE), 8));
-	clk_dm(JH7110_SYSCLK_UART5_APB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART5_APB),
 	       starfive_clk_gate(priv->reg,
 				 "uart5_apb", "apb0",
 				 OFFSET(JH7110_SYSCLK_UART5_APB)));
-	clk_dm(JH7110_SYSCLK_UART5_CORE,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART5_CORE),
 	       starfive_clk_gate_divider(priv->reg,
 					 "uart5_core", "perh_root",
 					 OFFSET(JH7110_SYSCLK_UART5_CORE), 8));
-	clk_dm(JH7110_SYSCLK_I2C2_APB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_I2C2_APB),
 	       starfive_clk_gate(priv->reg,
 				 "i2c2_apb", "apb0",
 				 OFFSET(JH7110_SYSCLK_I2C2_APB)));
-	clk_dm(JH7110_SYSCLK_I2C5_APB,
+	clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_I2C5_APB),
 	       starfive_clk_gate(priv->reg,
 				 "i2c5_apb", "apb0",
 				 OFFSET(JH7110_SYSCLK_I2C5_APB)));
@@ -463,39 +446,39 @@ static int jh7110_aoncrg_init(struct udevice *dev)
 {
 	struct jh7110_clk_priv *priv = dev_get_priv(dev);
 
-	clk_dm(JH7110_AONCLK_OSC_DIV4,
+	clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_OSC_DIV4),
 	       starfive_clk_divider(priv->reg,
 				    "osc_div4", "oscillator",
-				    AONOFFSET(JH7110_AONCLK_OSC_DIV4), 5));
-	clk_dm(JH7110_AONCLK_APB_FUNC,
+				    OFFSET(JH7110_AONCLK_OSC_DIV4), 5));
+	clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_APB_FUNC),
 	       starfive_clk_mux(priv->reg, "apb_func",
-				AONOFFSET(JH7110_AONCLK_APB_FUNC), 1,
+				OFFSET(JH7110_AONCLK_APB_FUNC), 1,
 				apb_func_sels,	ARRAY_SIZE(apb_func_sels)));
-	clk_dm(JH7110_AONCLK_GMAC0_AHB,
+	clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_GMAC0_AHB),
 	       starfive_clk_gate(priv->reg,
 				 "gmac0_ahb", "stg_axiahb",
-				 AONOFFSET(JH7110_AONCLK_GMAC0_AHB)));
-	clk_dm(JH7110_AONCLK_GMAC0_AXI,
+				 OFFSET(JH7110_AONCLK_GMAC0_AHB)));
+	clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_GMAC0_AXI),
 	       starfive_clk_gate(priv->reg,
 				 "gmac0_axi", "stg_axiahb",
-				 AONOFFSET(JH7110_AONCLK_GMAC0_AXI)));
-	clk_dm(JH7110_AONCLK_GMAC0_RMII_RTX,
+				 OFFSET(JH7110_AONCLK_GMAC0_AXI)));
+	clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_GMAC0_RMII_RTX),
 	       starfive_clk_divider(priv->reg,
 				    "gmac0_rmii_rtx", "gmac0-rmii-refin-clock",
-				    AONOFFSET(JH7110_AONCLK_GMAC0_RMII_RTX), 5));
-	clk_dm(JH7110_AONCLK_GMAC0_TX,
+				    OFFSET(JH7110_AONCLK_GMAC0_RMII_RTX), 5));
+	clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_GMAC0_TX),
 	       starfive_clk_composite(priv->reg,
 				      "gmac0_tx", gmac0_tx_sels,
 				      ARRAY_SIZE(gmac0_tx_sels),
-				      AONOFFSET(JH7110_AONCLK_GMAC0_TX), 1, 1, 0));
-	clk_dm(JH7110_AONCLK_GMAC0_TX_INV,
+				      OFFSET(JH7110_AONCLK_GMAC0_TX), 1, 1, 0));
+	clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_GMAC0_TX_INV),
 	       starfive_clk_inv(priv->reg,
 				"gmac0_tx_inv", "gmac0_tx",
-				AONOFFSET(JH7110_AONCLK_GMAC0_TX_INV)));
-	clk_dm(JH7110_AONCLK_OTPC_APB,
+				OFFSET(JH7110_AONCLK_GMAC0_TX_INV)));
+	clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_OTPC_APB),
 	       starfive_clk_gate(priv->reg,
 				 "otpc_apb", "apb_bus",
-				 AONOFFSET(JH7110_AONCLK_OTPC_APB)));
+				 OFFSET(JH7110_AONCLK_OTPC_APB)));
 
 	return 0;
 }
@@ -504,57 +487,57 @@ static int jh7110_stgcrg_init(struct udevice *dev)
 {
 	struct jh7110_clk_priv *priv = dev_get_priv(dev);
 
-	clk_dm(JH7110_STGCLK_USB_APB,
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APB),
 	       starfive_clk_gate(priv->reg,
 				 "usb_apb", "apb_bus",
-				 STGOFFSET(JH7110_STGCLK_USB_APB)));
-	clk_dm(JH7110_STGCLK_USB_UTMI_APB,
+				 OFFSET(JH7110_STGCLK_USB_APB)));
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_UTMI_APB),
 	       starfive_clk_gate(priv->reg,
 				 "usb_utmi_apb", "apb_bus",
-				 STGOFFSET(JH7110_STGCLK_USB_UTMI_APB)));
-	clk_dm(JH7110_STGCLK_USB_AXI,
+				 OFFSET(JH7110_STGCLK_USB_UTMI_APB)));
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_AXI),
 	       starfive_clk_gate(priv->reg,
 				 "usb_axi", "stg_axiahb",
-				 STGOFFSET(JH7110_STGCLK_USB_AXI)));
-	clk_dm(JH7110_STGCLK_USB_LPM,
+				 OFFSET(JH7110_STGCLK_USB_AXI)));
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_LPM),
 	       starfive_clk_gate_divider(priv->reg,
 					 "usb_lpm", "oscillator",
-					 STGOFFSET(JH7110_STGCLK_USB_LPM), 2));
-	clk_dm(JH7110_STGCLK_USB_STB,
+					 OFFSET(JH7110_STGCLK_USB_LPM), 2));
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_STB),
 	       starfive_clk_gate_divider(priv->reg,
 					 "usb_stb", "oscillator",
-					 STGOFFSET(JH7110_STGCLK_USB_STB), 3));
-	clk_dm(JH7110_STGCLK_USB_APP_125,
+					 OFFSET(JH7110_STGCLK_USB_STB), 3));
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APP_125),
 	       starfive_clk_gate(priv->reg,
 				 "usb_app_125", "usb_125m",
-				 STGOFFSET(JH7110_STGCLK_USB_APP_125)));
-	clk_dm(JH7110_STGCLK_USB_REFCLK,
+				 OFFSET(JH7110_STGCLK_USB_APP_125)));
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_REFCLK),
 	       starfive_clk_divider(priv->reg, "usb_refclk", "oscillator",
-				    STGOFFSET(JH7110_STGCLK_USB_REFCLK), 2));
-	clk_dm(JH7110_STGCLK_PCIE0_AXI,
+				    OFFSET(JH7110_STGCLK_USB_REFCLK), 2));
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI),
 	       starfive_clk_gate(priv->reg,
 				 "pcie0_axi", "stg_axiahb",
-				 STGOFFSET(JH7110_STGCLK_PCIE0_AXI)));
-	clk_dm(JH7110_STGCLK_PCIE0_APB,
+				 OFFSET(JH7110_STGCLK_PCIE0_AXI)));
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_APB),
 	       starfive_clk_gate(priv->reg,
 				 "pcie0_apb", "apb_bus",
-				 STGOFFSET(JH7110_STGCLK_PCIE0_APB)));
-	clk_dm(JH7110_STGCLK_PCIE0_TL,
+				 OFFSET(JH7110_STGCLK_PCIE0_APB)));
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_TL),
 	       starfive_clk_gate(priv->reg,
 				 "pcie0_tl", "stg_axiahb",
-				 STGOFFSET(JH7110_STGCLK_PCIE0_TL)));
-	clk_dm(JH7110_STGCLK_PCIE1_AXI,
+				 OFFSET(JH7110_STGCLK_PCIE0_TL)));
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI),
 	       starfive_clk_gate(priv->reg,
 				 "pcie1_axi", "stg_axiahb",
-				 STGOFFSET(JH7110_STGCLK_PCIE1_AXI)));
-	clk_dm(JH7110_STGCLK_PCIE1_APB,
+				 OFFSET(JH7110_STGCLK_PCIE1_AXI)));
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_APB),
 	       starfive_clk_gate(priv->reg,
 				 "pcie1_apb", "apb_bus",
-				 STGOFFSET(JH7110_STGCLK_PCIE1_APB)));
-	clk_dm(JH7110_STGCLK_PCIE1_TL,
+				 OFFSET(JH7110_STGCLK_PCIE1_APB)));
+	clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_TL),
 	       starfive_clk_gate(priv->reg,
 				 "pcie1_tl", "stg_axiahb",
-				 STGOFFSET(JH7110_STGCLK_PCIE1_TL)));
+				 OFFSET(JH7110_STGCLK_PCIE1_TL)));
 
 	return 0;
 }
@@ -579,25 +562,104 @@ static int jh7110_clk_bind(struct udevice *dev)
 							dev_ofnode(dev), NULL);
 }
 
-static const struct udevice_id jh7110_clk_of_match[] = {
+static int jh7110_sys_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+	if (args->args_count > 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (args->args_count)
+		clk->id = JH7110_SYS_ID_TRANS(args->args[0]);
+	else
+		clk->id = 0;
+
+	return 0;
+}
+
+static int jh7110_aon_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+	if (args->args_count > 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (args->args_count)
+		clk->id = JH7110_AON_ID_TRANS(args->args[0]);
+	else
+		clk->id = 0;
+
+	return 0;
+}
+
+static int jh7110_stg_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+	if (args->args_count > 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (args->args_count)
+		clk->id = JH7110_STG_ID_TRANS(args->args[0]);
+	else
+		clk->id = 0;
+
+	return 0;
+}
+
+static const struct udevice_id jh7110_sys_clk_of_match[] = {
 	{ .compatible = "starfive,jh7110-syscrg",
 	  .data = (ulong)&jh7110_syscrg_init
 	},
-	{ .compatible = "starfive,jh7110-stgcrg",
-	  .data = (ulong)&jh7110_stgcrg_init
-	},
+	{ }
+};
+
+JH7110_CLK_OPS(sys);
+
+U_BOOT_DRIVER(jh7110_sys_clk) = {
+	.name = "jh7110_sys_clk",
+	.id = UCLASS_CLK,
+	.of_match = jh7110_sys_clk_of_match,
+	.probe = jh7110_clk_probe,
+	.ops = &jh7110_sys_clk_ops,
+	.priv_auto = sizeof(struct jh7110_clk_priv),
+	.bind = jh7110_clk_bind,
+};
+
+static const struct udevice_id jh7110_aon_clk_of_match[] = {
 	{ .compatible = "starfive,jh7110-aoncrg",
 	  .data = (ulong)&jh7110_aoncrg_init
 	},
 	{ }
 };
 
-U_BOOT_DRIVER(jh7110_clk) = {
-	.name = "jh7110_clk",
+JH7110_CLK_OPS(aon);
+
+U_BOOT_DRIVER(jh7110_aon_clk) = {
+	.name = "jh7110_aon_clk",
+	.id = UCLASS_CLK,
+	.of_match = jh7110_aon_clk_of_match,
+	.probe = jh7110_clk_probe,
+	.ops = &jh7110_aon_clk_ops,
+	.priv_auto = sizeof(struct jh7110_clk_priv),
+	.bind = jh7110_clk_bind,
+};
+
+static const struct udevice_id jh7110_stg_clk_of_match[] = {
+	{ .compatible = "starfive,jh7110-stgcrg",
+	  .data = (ulong)&jh7110_stgcrg_init
+	},
+	{ }
+};
+
+JH7110_CLK_OPS(stg);
+
+U_BOOT_DRIVER(jh7110_stg_clk) = {
+	.name = "jh7110_stg_clk",
 	.id = UCLASS_CLK,
-	.of_match = jh7110_clk_of_match,
+	.of_match = jh7110_stg_clk_of_match,
 	.probe = jh7110_clk_probe,
-	.ops = &ccf_clk_ops,
+	.ops = &jh7110_stg_clk_ops,
 	.priv_auto = sizeof(struct jh7110_clk_priv),
-	.bind		= jh7110_clk_bind,
+	.bind = jh7110_clk_bind,
 };
diff --git a/drivers/clk/starfive/clk.h b/drivers/clk/starfive/clk.h
index 4dee12fe89..9d20ed0bba 100644
--- a/drivers/clk/starfive/clk.h
+++ b/drivers/clk/starfive/clk.h
@@ -1,57 +1,25 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2022 Starfive, Inc.
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
  * Author:	Yanhong Wang <yanhong.wang@starfivetech.com>
- *
  */
 
 #ifndef __CLK_STARFIVE_H
 #define __CLK_STARFIVE_H
 
-enum starfive_pll_type {
-	PLL0 = 0,
-	PLL1,
-	PLL2,
-	PLL_MAX = PLL2
-};
+/* the number of fixed clocks in DTS */
+#define JH7110_EXTCLK_END	12
 
-struct starfive_pllx_rate {
-	u64 rate;
-	u32 prediv;
-	u32 fbdiv;
-	u32 frac;
-};
+#define _JH7110_CLK_OPS(_name)					\
+static const struct clk_ops jh7110_##_name##_clk_ops = {	\
+	.set_rate = ccf_clk_set_rate,				\
+	.get_rate = ccf_clk_get_rate,				\
+	.set_parent = ccf_clk_set_parent,			\
+	.enable = ccf_clk_enable,				\
+	.disable = ccf_clk_disable,				\
+	.of_xlate = jh7110_##_name##_clk_of_xlate,		\
+}
 
-struct starfive_pllx_offset {
-	u32 pd;
-	u32 prediv;
-	u32 fbdiv;
-	u32 frac;
-	u32 postdiv1;
-	u32 dacpd;
-	u32 dsmpd;
-	u32 pd_mask;
-	u32 prediv_mask;
-	u32 fbdiv_mask;
-	u32 frac_mask;
-	u32 postdiv1_mask;
-	u32 dacpd_mask;
-	u32 dsmpd_mask;
-};
+#define JH7110_CLK_OPS(name) _JH7110_CLK_OPS(name)
 
-struct starfive_pllx_clk {
-	enum starfive_pll_type type;
-	const struct starfive_pllx_offset *offset;
-	const struct starfive_pllx_rate *rate_table;
-	int rate_count;
-	int flags;
-};
-
-extern struct starfive_pllx_clk starfive_jh7110_pll0;
-extern struct starfive_pllx_clk starfive_jh7110_pll1;
-extern struct starfive_pllx_clk starfive_jh7110_pll2;
-
-struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
-				void __iomem *base, void __iomem *sysreg,
-				const struct starfive_pllx_clk *pll_clk);
 #endif
diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c
index 4f4524fcb2..6150287694 100644
--- a/drivers/clk/stm32/clk-stm32mp1.c
+++ b/drivers/clk/stm32/clk-stm32mp1.c
@@ -881,7 +881,8 @@ static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 		return sel[s].parent[p];
 	}
 
-	log_err("no parents defined for clk id %d\n", (u32)id);
+	/* clock is DISABLED when the clock src is not in clk_parent[] range */
+	log_debug("no parents defined for clk id %d\n", (u32)id);
 
 	return -EINVAL;
 }
diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index 81a307992c..57f10445b1 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -593,11 +593,14 @@ int of_read_u64(const struct device_node *np, const char *propname, u64 *outp)
 int of_property_match_string(const struct device_node *np, const char *propname,
 			     const char *string)
 {
-	const struct property *prop = of_find_property(np, propname, NULL);
+	int len = 0;
+	const struct property *prop = of_find_property(np, propname, &len);
 	size_t l;
 	int i;
 	const char *p, *end;
 
+	if (!prop && len == -FDT_ERR_NOTFOUND)
+		return -ENOENT;
 	if (!prop)
 		return -EINVAL;
 	if (!prop->value)
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index ec574c4460..8df16e56af 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -12,6 +12,7 @@
 #include <fdt_support.h>
 #include <log.h>
 #include <malloc.h>
+#include <of_live.h>
 #include <linux/libfdt.h>
 #include <dm/of_access.h>
 #include <dm/of_addr.h>
@@ -51,6 +52,20 @@ static oftree oftree_ensure(void *fdt)
 	oftree tree;
 	int i;
 
+	if (of_live_active()) {
+		struct device_node *root;
+		int ret;
+
+		ret = unflatten_device_tree(fdt, &root);
+		if (ret) {
+			log_err("Failed to create live tree: err=%d\n", ret);
+			return oftree_null();
+		}
+		tree = oftree_from_np(root);
+
+		return tree;
+	}
+
 	if (gd->flags & GD_FLG_RELOC) {
 		i = oftree_find(fdt);
 		if (i == -1) {
@@ -67,7 +82,7 @@ static oftree oftree_ensure(void *fdt)
 		}
 	} else {
 		if (fdt != gd->fdt_blob) {
-			log_debug("Cannot only access control FDT before relocation\n");
+			log_debug("Only the control FDT can be accessed before relocation\n");
 			return oftree_null();
 		}
 	}
@@ -77,6 +92,12 @@ static oftree oftree_ensure(void *fdt)
 	return tree;
 }
 
+void oftree_dispose(oftree tree)
+{
+	if (of_live_active())
+		of_live_free(tree.np);
+}
+
 void *ofnode_lookup_fdt(ofnode node)
 {
 	if (gd->flags & GD_FLG_RELOC) {
@@ -133,6 +154,10 @@ oftree oftree_from_fdt(void *fdt)
 	if (CONFIG_IS_ENABLED(OFNODE_MULTI_TREE))
 		return oftree_ensure(fdt);
 
+#ifdef OF_CHECKS
+	if (of_live_active())
+		return oftree_null();
+#endif
 	tree.fdt = fdt;
 
 	return tree;
diff --git a/drivers/core/read.c b/drivers/core/read.c
index 0289a2edb6..49066b59cd 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -150,6 +150,17 @@ fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index,
 		return devfdt_get_addr_size_index(dev, index, size);
 }
 
+void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index,
+				   fdt_size_t *size)
+{
+	fdt_addr_t addr = dev_read_addr_size_index(dev, index, size);
+
+	if (addr == FDT_ADDR_T_NONE)
+		return NULL;
+
+	return map_sysmem(addr, 0);
+}
+
 void *dev_remap_addr_index(const struct udevice *dev, int index)
 {
 	fdt_addr_t addr = dev_read_addr_index(dev, index);
@@ -211,10 +222,9 @@ void *dev_remap_addr(const struct udevice *dev)
 	return dev_remap_addr_index(dev, 0);
 }
 
-fdt_addr_t dev_read_addr_size(const struct udevice *dev, const char *property,
-			      fdt_size_t *sizep)
+fdt_addr_t dev_read_addr_size(const struct udevice *dev, fdt_size_t *sizep)
 {
-	return ofnode_get_addr_size(dev_ofnode(dev), property, sizep);
+	return dev_read_addr_size_index(dev, 0, sizep);
 }
 
 const char *dev_read_name(const struct udevice *dev)
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
index 8d7f13dcb0..4e80e85d10 100644
--- a/drivers/dfu/Kconfig
+++ b/drivers/dfu/Kconfig
@@ -35,13 +35,13 @@ config DFU_TIMEOUT
 
 config DFU_MMC
 	bool "MMC back end for DFU"
+	depends on MMC
 	help
 	  This option enables using DFU to read and write to MMC based storage.
 
 config DFU_MTD
 	bool "MTD back end for DFU"
 	depends on DM_MTD
-	depends on CMD_MTDPARTS
 	help
 	  This option enables using DFU to read and write to on any MTD device.
 
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 516dda6179..b2ee5f1ede 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -135,6 +135,7 @@ int dfu_config_interfaces(char *env)
 			a = s;
 		do {
 			part = strsep(&a, ";");
+			part = skip_spaces(part);
 			ret = dfu_alt_add(dfu, i, d, part);
 			if (ret)
 				return ret;
@@ -629,6 +630,7 @@ int dfu_config_entities(char *env, char *interface, char *devstr)
 
 	for (i = 0; i < dfu_alt_num; i++) {
 		s = strsep(&env, ";");
+		s = skip_spaces(s);
 		ret = dfu_alt_add(dfu, interface, devstr, s);
 		if (ret) {
 			/* We will free "dfu" in dfu_free_entities() */
diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c
index c7075f12ec..75e2f6a421 100644
--- a/drivers/dfu/dfu_mtd.c
+++ b/drivers/dfu/dfu_mtd.c
@@ -10,7 +10,6 @@
 #include <common.h>
 #include <dfu.h>
 #include <mtd.h>
-#include <jffs2/load_kernel.h>
 #include <linux/err.h>
 #include <linux/ctype.h>
 
@@ -275,7 +274,7 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char **argv, int a
 {
 	char *s;
 	struct mtd_info *mtd;
-	int ret, part;
+	int part;
 
 	mtd = get_mtd_device_nm(devstr);
 	if (IS_ERR_OR_NULL(mtd))
@@ -299,10 +298,9 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char **argv, int a
 		if (*s)
 			return -EINVAL;
 	} else if ((!strcmp(argv[0], "part")) || (!strcmp(argv[0], "partubi"))) {
-		char mtd_id[32];
-		struct mtd_device *mtd_dev;
-		u8 part_num;
-		struct part_info *pi;
+		struct mtd_info *partition;
+		int partnum = 0;
+		bool part_found = false;
 
 		if (argc != 2)
 			return -EINVAL;
@@ -313,19 +311,25 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char **argv, int a
 		if (*s)
 			return -EINVAL;
 
-		sprintf(mtd_id, "%s,%d", devstr, part - 1);
-		printf("using id '%s'\n", mtd_id);
+		/* register partitions with MTDIDS/MTDPARTS or OF fallback */
+		mtd_probe_devices();
 
-		mtdparts_init();
-
-		ret = find_dev_and_part(mtd_id, &mtd_dev, &part_num, &pi);
-		if (ret != 0) {
-			printf("Could not locate '%s'\n", mtd_id);
+		partnum = 0;
+		list_for_each_entry(partition, &mtd->partitions, node) {
+			partnum++;
+			if (partnum == part) {
+				part_found = true;
+				break;
+			}
+		}
+		if (!part_found) {
+			printf("No partition %d in %s\n", part, mtd->name);
 			return -1;
 		}
+		log_debug("partition %d:%s in %s\n", partnum, partition->name, mtd->name);
 
-		dfu->data.mtd.start = pi->offset;
-		dfu->data.mtd.size = pi->size;
+		dfu->data.mtd.start = partition->offset;
+		dfu->data.mtd.size = partition->size;
 		if (!strcmp(argv[0], "partubi"))
 			dfu->data.mtd.ubi = 1;
 	} else {
diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c
index 621146bc6b..4e9d9b719c 100644
--- a/drivers/fastboot/fb_common.c
+++ b/drivers/fastboot/fb_common.c
@@ -135,7 +135,7 @@ void fastboot_boot(void)
 	s = env_get("fastboot_bootcmd");
 	if (s) {
 		run_command(s, CMD_FLAG_ENV);
-	} else {
+	} else if (IS_ENABLED(CONFIG_CMD_BOOTM)) {
 		static char boot_addr_start[20];
 		static char *const bootm_args[] = {
 			"bootm", boot_addr_start, NULL
diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
index 9d25c40202..060918e491 100644
--- a/drivers/fastboot/fb_mmc.c
+++ b/drivers/fastboot/fb_mmc.c
@@ -19,8 +19,6 @@
 #include <linux/compat.h>
 #include <android_image.h>
 
-#define FASTBOOT_MAX_BLK_WRITE 16384
-
 #define BOOT_PARTITION_NAME "boot"
 
 struct fb_mmc_sparse {
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index eae1c8ddc9..8789b1ea14 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -45,4 +45,5 @@ config ARM_SMCCC_FEATURES
 	  the PSCI driver is always probed and binds dirvers registered to the Arm SMCCC
 	  services if any and reported as supported by the SMCCC firmware.
 
+source "drivers/firmware/arm-ffa/Kconfig"
 source "drivers/firmware/scmi/Kconfig"
diff --git a/drivers/firmware/arm-ffa/Kconfig b/drivers/firmware/arm-ffa/Kconfig
new file mode 100644
index 0000000000..d75f8b53fd
--- /dev/null
+++ b/drivers/firmware/arm-ffa/Kconfig
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config ARM_FFA_TRANSPORT
+	bool "Enable Arm Firmware Framework for Armv8-A driver"
+	depends on DM && (ARM64 || SANDBOX)
+	select ARM_SMCCC if !SANDBOX
+	select ARM_SMCCC_FEATURES if !SANDBOX
+	imply CMD_ARMFFA
+	select LIB_UUID
+	select DEVRES
+	help
+	  The Firmware Framework for Arm A-profile processors (FF-A)
+	  describes interfaces (ABIs) that standardize communication
+	  between the Secure World and Normal World leveraging TrustZone
+	  technology.
+
+	  The FF-A support in U-Boot is based on FF-A specification v1.0 and uses SMC32
+	  calling convention.
+
+	  FF-A specification:
+
+	  https://developer.arm.com/documentation/den0077/a/?lang=en
+
+	  In U-Boot FF-A design, FF-A is considered as a discoverable bus.
+	  FF-A bus is discovered using ARM_SMCCC_FEATURES mechanism performed
+	  by the PSCI driver.
+	  The Secure World is considered as one entity to communicate with
+	  using the FF-A bus.
+	  FF-A communication is handled by one device and one instance (the bus).
+	  The FF-A support on U-Boot  takes care of all the interactions between Normal
+	  world and Secure World.
+
+	  Generic FF-A methods are implemented in the Uclass (arm-ffa-uclass.c).
+	  Arm specific methods are implemented in the Arm driver (arm-ffa.c).
+
+	  FF-A sandbox is provided to run FF-A under sandbox and allows to test the FF-A Uclass.
+	  Sandbox support includes an emulator for Arm FF-A which emulates the FF-A side of
+	  the Secure World and provides FF-A ABIs inspection methods (ffa-emul-uclass.c).
+	  An FF-A sandbox driver is also provided for FF-A communication with the emulated
+	  Secure World (sandbox_ffa.c).
+
+	  For more details about the FF-A support, please refer to doc/arch/arm64.ffa.rst
diff --git a/drivers/firmware/arm-ffa/Makefile b/drivers/firmware/arm-ffa/Makefile
new file mode 100644
index 0000000000..318123a7f4
--- /dev/null
+++ b/drivers/firmware/arm-ffa/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+#
+# Authors:
+#   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+# build the generic FF-A methods
+obj-y += arm-ffa-uclass.o
+ifeq ($(CONFIG_SANDBOX),y)
+# build the FF-A sandbox emulator and driver
+obj-y += ffa-emul-uclass.o sandbox_ffa.o
+else
+# build the Arm64 FF-A driver
+obj-y += arm-ffa.o
+endif
diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c
new file mode 100644
index 0000000000..8c17b19eaf
--- /dev/null
+++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c
@@ -0,0 +1,1065 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+#include <common.h>
+#include <arm_ffa.h>
+#include <arm_ffa_priv.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <string.h>
+#include <uuid.h>
+#include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <dm/devres.h>
+#include <dm/root.h>
+#include <linux/errno.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Error mapping declarations */
+
+int ffa_to_std_errmap[MAX_NUMBER_FFA_ERR] = {
+	[NOT_SUPPORTED] = -EOPNOTSUPP,
+	[INVALID_PARAMETERS] = -EINVAL,
+	[NO_MEMORY] = -ENOMEM,
+	[BUSY] = -EBUSY,
+	[INTERRUPTED] = -EINTR,
+	[DENIED] = -EACCES,
+	[RETRY] = -EAGAIN,
+	[ABORTED] = -ECANCELED,
+};
+
+static struct ffa_abi_errmap err_msg_map[FFA_ERRMAP_COUNT] = {
+	[FFA_ID_TO_ERRMAP_ID(FFA_VERSION)] = {
+		{
+			[NOT_SUPPORTED] =
+			"NOT_SUPPORTED: A Firmware Framework implementation does not exist",
+		},
+	},
+	[FFA_ID_TO_ERRMAP_ID(FFA_ID_GET)] = {
+		{
+			[NOT_SUPPORTED] =
+			"NOT_SUPPORTED: This function is not implemented at this FF-A instance",
+		},
+	},
+	[FFA_ID_TO_ERRMAP_ID(FFA_FEATURES)] = {
+		{
+			[NOT_SUPPORTED] =
+			"NOT_SUPPORTED: FFA_RXTX_MAP is not implemented at this FF-A instance",
+		},
+	},
+	[FFA_ID_TO_ERRMAP_ID(FFA_PARTITION_INFO_GET)] = {
+		{
+			[NOT_SUPPORTED] =
+			"NOT_SUPPORTED: This function is not implemented at this FF-A instance",
+			[INVALID_PARAMETERS] =
+			"INVALID_PARAMETERS: Unrecognized UUID",
+			[NO_MEMORY] =
+			"NO_MEMORY: Results cannot fit in RX buffer of the caller",
+			[BUSY] =
+			"BUSY: RX buffer of the caller is not free",
+			[DENIED] =
+			"DENIED: Callee is not in a state to handle this request",
+		},
+	},
+	[FFA_ID_TO_ERRMAP_ID(FFA_RXTX_UNMAP)] = {
+		{
+			[NOT_SUPPORTED] =
+			"NOT_SUPPORTED: FFA_RXTX_UNMAP is not implemented at this FF-A instance",
+			[INVALID_PARAMETERS] =
+			"INVALID_PARAMETERS: No buffer pair registered on behalf of the caller",
+		},
+	},
+	[FFA_ID_TO_ERRMAP_ID(FFA_RX_RELEASE)] = {
+		{
+			[NOT_SUPPORTED] =
+			"NOT_SUPPORTED: FFA_RX_RELEASE is not implemented at this FF-A instance",
+			[DENIED] =
+			"DENIED: Caller did not have ownership of the RX buffer",
+		},
+	},
+	[FFA_ID_TO_ERRMAP_ID(FFA_RXTX_MAP)] = {
+		{
+			[NOT_SUPPORTED] =
+			"NOT_SUPPORTED: This function is not implemented at this FF-A instance",
+			[INVALID_PARAMETERS] =
+			"INVALID_PARAMETERS: Field(s) in input parameters incorrectly encoded",
+			[NO_MEMORY] =
+			"NO_MEMORY: Not enough memory",
+			[DENIED] =
+			"DENIED: Buffer pair already registered",
+		},
+	},
+};
+
+/**
+ * ffa_to_std_errno() - convert FF-A error code to standard error code
+ * @ffa_errno:	Error code returned by the FF-A ABI
+ *
+ * Map the given FF-A error code as specified
+ * by the spec to a u-boot standard error code.
+ *
+ * Return:
+ *
+ * The standard error code on success. . Otherwise, failure
+ */
+static int ffa_to_std_errno(int ffa_errno)
+{
+	int err_idx = -ffa_errno;
+
+	/* Map the FF-A error code to the standard u-boot error code */
+	if (err_idx > 0 && err_idx < MAX_NUMBER_FFA_ERR)
+		return ffa_to_std_errmap[err_idx];
+	return -EINVAL;
+}
+
+/**
+ * ffa_print_error_log() - print the error log corresponding to the selected FF-A ABI
+ * @ffa_id:	FF-A ABI ID
+ * @ffa_errno:	Error code returned by the FF-A ABI
+ *
+ * Map the FF-A error code to the error log relevant to the
+ * selected FF-A ABI. Then the error log is printed.
+ *
+ * Return:
+ *
+ * 0 on success. . Otherwise, failure
+ */
+static int ffa_print_error_log(u32 ffa_id, int ffa_errno)
+{
+	int err_idx = -ffa_errno, abi_idx = 0;
+
+	/* Map the FF-A error code to the corresponding error log */
+
+	if (err_idx <= 0 || err_idx >= MAX_NUMBER_FFA_ERR)
+		return -EINVAL;
+
+	if (ffa_id < FFA_FIRST_ID || ffa_id > FFA_LAST_ID)
+		return -EINVAL;
+
+	abi_idx = FFA_ID_TO_ERRMAP_ID(ffa_id);
+	if (abi_idx < 0 || abi_idx >= FFA_ERRMAP_COUNT)
+		return -EINVAL;
+
+	if (!err_msg_map[abi_idx].err_str[err_idx])
+		return -EINVAL;
+
+	log_err("%s\n", err_msg_map[abi_idx].err_str[err_idx]);
+
+	return 0;
+}
+
+/* FF-A ABIs implementation (U-Boot side) */
+
+/**
+ * invoke_ffa_fn() - SMC wrapper
+ * @args: FF-A ABI arguments to be copied to Xn registers
+ * @res: FF-A ABI return data to be copied from Xn registers
+ *
+ * Calls low level SMC implementation.
+ * This function should be implemented by the user driver.
+ */
+void __weak invoke_ffa_fn(ffa_value_t args, ffa_value_t *res)
+{
+}
+
+/**
+ * ffa_get_version_hdlr() - FFA_VERSION handler function
+ * @dev: The FF-A bus device
+ *
+ * Implement FFA_VERSION FF-A function
+ * to get from the secure world the FF-A framework version
+ * FFA_VERSION is used to discover the FF-A framework.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_get_version_hdlr(struct udevice *dev)
+{
+	u16 major, minor;
+	ffa_value_t res = {0};
+	int ffa_errno;
+	struct ffa_priv *uc_priv;
+
+	invoke_ffa_fn((ffa_value_t){
+			.a0 = FFA_SMC_32(FFA_VERSION), .a1 = FFA_VERSION_1_0,
+			}, &res);
+
+	ffa_errno = res.a0;
+	if (ffa_errno < 0) {
+		ffa_print_error_log(FFA_VERSION, ffa_errno);
+		return ffa_to_std_errno(ffa_errno);
+	}
+
+	major = GET_FFA_MAJOR_VERSION(res.a0);
+	minor = GET_FFA_MINOR_VERSION(res.a0);
+
+	log_debug("FF-A driver %d.%d\nFF-A framework %d.%d\n",
+		 FFA_MAJOR_VERSION, FFA_MINOR_VERSION, major, minor);
+
+	if (major == FFA_MAJOR_VERSION && minor >= FFA_MINOR_VERSION) {
+		log_debug("FF-A versions are compatible\n");
+
+		if (dev) {
+			uc_priv = dev_get_uclass_priv(dev);
+			if (uc_priv)
+				uc_priv->fwk_version = res.a0;
+		}
+
+		return 0;
+	}
+
+	log_err("versions are incompatible\nExpected: %d.%d , Found: %d.%d\n",
+		FFA_MAJOR_VERSION, FFA_MINOR_VERSION, major, minor);
+
+	return -EPROTONOSUPPORT;
+}
+
+/**
+ * ffa_get_endpoint_id() - FFA_ID_GET handler function
+ * @dev: The FF-A bus device
+ *
+ * Implement FFA_ID_GET FF-A function
+ * to get from the secure world u-boot endpoint ID
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_get_endpoint_id(struct udevice *dev)
+{
+	ffa_value_t res = {0};
+	int ffa_errno;
+	struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	invoke_ffa_fn((ffa_value_t){
+			.a0 = FFA_SMC_32(FFA_ID_GET),
+			}, &res);
+
+	if (res.a0 == FFA_SMC_32(FFA_SUCCESS)) {
+		uc_priv->id = GET_SELF_ENDPOINT_ID((u32)res.a2);
+		log_debug("FF-A endpoint ID is %u\n", uc_priv->id);
+
+		return 0;
+	}
+
+	ffa_errno = res.a2;
+
+	ffa_print_error_log(FFA_ID_GET, ffa_errno);
+
+	return ffa_to_std_errno(ffa_errno);
+}
+
+/**
+ * ffa_set_rxtx_buffers_pages_cnt() - set the minimum number of pages in each of the RX/TX buffers
+ * @dev: The FF-A bus device
+ * @prop_field: properties field obtained from FFA_FEATURES ABI
+ *
+ * Set the minimum number of pages in each of the RX/TX buffers in uc_priv
+ *
+ * Return:
+ *
+ * rxtx_min_pages field contains the returned number of pages
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_set_rxtx_buffers_pages_cnt(struct udevice *dev, u32 prop_field)
+{
+	struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	switch (prop_field) {
+	case RXTX_4K:
+		uc_priv->pair.rxtx_min_pages = 1;
+		break;
+	case RXTX_16K:
+		uc_priv->pair.rxtx_min_pages = 4;
+		break;
+	case RXTX_64K:
+		uc_priv->pair.rxtx_min_pages = 16;
+		break;
+	default:
+		log_err("RX/TX buffer size not supported\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
+ * ffa_get_rxtx_map_features_hdlr() - FFA_FEATURES handler function with FFA_RXTX_MAP argument
+ * @dev: The FF-A bus device
+ *
+ * Implement FFA_FEATURES FF-A function to retrieve the FFA_RXTX_MAP features
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_get_rxtx_map_features_hdlr(struct udevice *dev)
+{
+	ffa_value_t res = {0};
+	int ffa_errno;
+
+	invoke_ffa_fn((ffa_value_t){
+			.a0 = FFA_SMC_32(FFA_FEATURES),
+			.a1 = FFA_SMC_64(FFA_RXTX_MAP),
+			}, &res);
+
+	if (res.a0 == FFA_SMC_32(FFA_SUCCESS))
+		return ffa_set_rxtx_buffers_pages_cnt(dev, res.a2);
+
+	ffa_errno = res.a2;
+	ffa_print_error_log(FFA_FEATURES, ffa_errno);
+
+	return ffa_to_std_errno(ffa_errno);
+}
+
+/**
+ * ffa_free_rxtx_buffers() - free the RX/TX buffers
+ * @dev: The FF-A bus device
+ *
+ * Free the RX/TX buffers
+ */
+static void ffa_free_rxtx_buffers(struct udevice *dev)
+{
+	struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	log_debug("Freeing FF-A RX/TX buffers\n");
+
+	if (uc_priv->pair.rxbuf) {
+		free(uc_priv->pair.rxbuf);
+		uc_priv->pair.rxbuf = NULL;
+	}
+
+	if (uc_priv->pair.txbuf) {
+		free(uc_priv->pair.txbuf);
+		uc_priv->pair.txbuf = NULL;
+	}
+}
+
+/**
+ * ffa_alloc_rxtx_buffers() - allocate the RX/TX buffers
+ * @dev: The FF-A bus device
+ *
+ * Used by ffa_map_rxtx_buffers to allocate
+ * the RX/TX buffers before mapping them. The allocated memory is physically
+ * contiguous since memalign ends up calling malloc which allocates
+ * contiguous memory in u-boot.
+ * The size of the memory allocated is the minimum allowed.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_alloc_rxtx_buffers(struct udevice *dev)
+{
+	u64 bytes;
+	struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	log_debug("Using %lu 4KB page(s) for FF-A RX/TX buffers size\n",
+		  uc_priv->pair.rxtx_min_pages);
+
+	bytes = uc_priv->pair.rxtx_min_pages * SZ_4K;
+
+	/*
+	 * The alignment of the RX and TX buffers must be equal
+	 * to the larger translation granule size
+	 * Assumption: Memory allocated with memalign is always physically contiguous
+	 */
+
+	uc_priv->pair.rxbuf = memalign(bytes, bytes);
+	if (!uc_priv->pair.rxbuf) {
+		log_err("failure to allocate RX buffer\n");
+		return -ENOBUFS;
+	}
+
+	log_debug("FF-A RX buffer at virtual address %p\n", uc_priv->pair.rxbuf);
+
+	uc_priv->pair.txbuf = memalign(bytes, bytes);
+	if (!uc_priv->pair.txbuf) {
+		free(uc_priv->pair.rxbuf);
+		uc_priv->pair.rxbuf = NULL;
+		log_err("failure to allocate the TX buffer\n");
+		return -ENOBUFS;
+	}
+
+	log_debug("FF-A TX buffer at virtual address %p\n", uc_priv->pair.txbuf);
+
+	/* Make sure the buffers are cleared before use */
+	memset(uc_priv->pair.rxbuf, 0, bytes);
+	memset(uc_priv->pair.txbuf, 0, bytes);
+
+	return 0;
+}
+
+/**
+ * ffa_map_rxtx_buffers_hdlr() - FFA_RXTX_MAP handler function
+ * @dev: The FF-A bus device
+ *
+ * Implement FFA_RXTX_MAP FF-A function to map the RX/TX buffers
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_map_rxtx_buffers_hdlr(struct udevice *dev)
+{
+	int ret;
+	ffa_value_t res = {0};
+	int ffa_errno;
+	struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	ret = ffa_alloc_rxtx_buffers(dev);
+	if (ret)
+		return ret;
+
+	/*
+	 * we need to pass the physical addresses of the RX/TX buffers
+	 * in u-boot physical/virtual mapping is 1:1
+	 * no need to convert from virtual to physical
+	 */
+
+	invoke_ffa_fn((ffa_value_t){
+			.a0 = FFA_SMC_64(FFA_RXTX_MAP),
+			.a1 = map_to_sysmem(uc_priv->pair.txbuf),
+			.a2 = map_to_sysmem(uc_priv->pair.rxbuf),
+			.a3 = uc_priv->pair.rxtx_min_pages,
+			}, &res);
+
+	if (res.a0 == FFA_SMC_32(FFA_SUCCESS)) {
+		log_debug("FF-A RX/TX buffers mapped\n");
+		return 0;
+	}
+
+	ffa_errno = res.a2;
+	ffa_print_error_log(FFA_RXTX_MAP, ffa_errno);
+
+	ffa_free_rxtx_buffers(dev);
+
+	return ffa_to_std_errno(ffa_errno);
+}
+
+/**
+ * ffa_unmap_rxtx_buffers_hdlr() - FFA_RXTX_UNMAP handler function
+ * @dev: The FF-A bus device
+ *
+ * Implement FFA_RXTX_UNMAP FF-A function to unmap the RX/TX buffers
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_unmap_rxtx_buffers_hdlr(struct udevice *dev)
+{
+	ffa_value_t res = {0};
+	int ffa_errno;
+	struct ffa_priv *uc_priv;
+
+	log_debug("unmapping FF-A RX/TX buffers\n");
+
+	uc_priv = dev_get_uclass_priv(dev);
+
+	invoke_ffa_fn((ffa_value_t){
+			.a0 = FFA_SMC_32(FFA_RXTX_UNMAP),
+			.a1 = PREP_SELF_ENDPOINT_ID(uc_priv->id),
+			}, &res);
+
+	if (res.a0 == FFA_SMC_32(FFA_SUCCESS)) {
+		ffa_free_rxtx_buffers(dev);
+		return 0;
+	}
+
+	ffa_errno = res.a2;
+	ffa_print_error_log(FFA_RXTX_UNMAP, ffa_errno);
+
+	return ffa_to_std_errno(ffa_errno);
+}
+
+/**
+ * ffa_release_rx_buffer_hdlr() - FFA_RX_RELEASE handler function
+ * @dev: The FF-A bus device
+ *
+ * Invoke FFA_RX_RELEASE FF-A function to release the ownership of the RX buffer
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_release_rx_buffer_hdlr(struct udevice *dev)
+{
+	ffa_value_t res = {0};
+	int ffa_errno;
+
+	invoke_ffa_fn((ffa_value_t){
+			.a0 = FFA_SMC_32(FFA_RX_RELEASE),
+			}, &res);
+
+	if (res.a0 == FFA_SMC_32(FFA_SUCCESS))
+		return 0;
+
+	ffa_errno = res.a2;
+	ffa_print_error_log(FFA_RX_RELEASE, ffa_errno);
+
+	return ffa_to_std_errno(ffa_errno);
+}
+
+/**
+ * ffa_uuid_are_identical() - check whether two given UUIDs are identical
+ * @uuid1: first UUID
+ * @uuid2: second UUID
+ *
+ * Used by ffa_read_partitions_info to search for a UUID in the partitions descriptors table
+ *
+ * Return:
+ *
+ * 1 when UUIDs match. Otherwise, 0
+ */
+static bool ffa_uuid_are_identical(const struct ffa_partition_uuid *uuid1,
+				   const struct ffa_partition_uuid *uuid2)
+{
+	if (!uuid1 || !uuid2)
+		return 0;
+
+	return !memcmp(uuid1, uuid2, sizeof(struct ffa_partition_uuid));
+}
+
+/**
+ * ffa_read_partitions_info() - read queried partition data
+ * @dev: The FF-A bus device
+ * @count: The number of partitions queried
+ * @part_uuid: Pointer to the partition(s) UUID
+ *
+ * Read the partitions information returned by the FFA_PARTITION_INFO_GET and saves it in uc_priv
+ *
+ * Return:
+ *
+ * uc_priv is updated with the partition(s) information
+ * 0 is returned on success. Otherwise, failure
+ */
+static int ffa_read_partitions_info(struct udevice *dev, u32 count,
+				    struct ffa_partition_uuid *part_uuid)
+{
+	struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	if (!count) {
+		log_err("no partition detected\n");
+		return -ENODATA;
+	}
+
+	log_debug("Reading FF-A partitions data from the RX buffer\n");
+
+	if (!part_uuid) {
+		/* Querying information of all partitions */
+		u64 buf_bytes;
+		u64 data_bytes;
+		u32 desc_idx;
+		struct ffa_partition_info *parts_info;
+
+		data_bytes = count * sizeof(struct ffa_partition_desc);
+
+		buf_bytes = uc_priv->pair.rxtx_min_pages * SZ_4K;
+
+		if (data_bytes > buf_bytes) {
+			log_err("partitions data size exceeds the RX buffer size:\n");
+			log_err("    sizes in bytes: data %llu , RX buffer %llu\n",
+				data_bytes,
+				buf_bytes);
+
+			return -ENOMEM;
+		}
+
+		uc_priv->partitions.descs = devm_kmalloc(dev, data_bytes, __GFP_ZERO);
+		if (!uc_priv->partitions.descs) {
+			log_err("cannot  allocate partitions data buffer\n");
+			return -ENOMEM;
+		}
+
+		parts_info = uc_priv->pair.rxbuf;
+
+		for (desc_idx = 0 ; desc_idx < count ; desc_idx++) {
+			uc_priv->partitions.descs[desc_idx].info =
+				parts_info[desc_idx];
+
+			log_debug("FF-A partition ID %x : info cached\n",
+				  uc_priv->partitions.descs[desc_idx].info.id);
+		}
+
+		uc_priv->partitions.count = count;
+
+		log_debug("%d FF-A partition(s) found and cached\n", count);
+
+	} else {
+		u32 rx_desc_idx, cached_desc_idx;
+		struct ffa_partition_info *parts_info;
+		u8 desc_found;
+
+		parts_info = uc_priv->pair.rxbuf;
+
+		/*
+		 * Search for the SP IDs read from the RX buffer
+		 * in the already cached SPs.
+		 * Update the UUID when ID found.
+		 */
+		for (rx_desc_idx = 0; rx_desc_idx < count ; rx_desc_idx++) {
+			desc_found = 0;
+
+			/* Search the current ID in the cached partitions */
+			for (cached_desc_idx = 0;
+			     cached_desc_idx < uc_priv->partitions.count;
+			     cached_desc_idx++) {
+				/* Save the UUID */
+				if (uc_priv->partitions.descs[cached_desc_idx].info.id ==
+				    parts_info[rx_desc_idx].id) {
+					uc_priv->partitions.descs[cached_desc_idx].sp_uuid =
+						*part_uuid;
+
+					desc_found = 1;
+					break;
+				}
+			}
+
+			if (!desc_found)
+				return -ENODATA;
+		}
+	}
+
+	return  0;
+}
+
+/**
+ * ffa_query_partitions_info() - invoke FFA_PARTITION_INFO_GET and save partitions data
+ * @dev: The FF-A bus device
+ * @part_uuid: Pointer to the partition(s) UUID
+ * @pcount: Pointer to the number of partitions variable filled when querying
+ *
+ * Execute the FFA_PARTITION_INFO_GET to query the partitions data.
+ * Then, call ffa_read_partitions_info to save the data in uc_priv.
+ *
+ * After reading the data the RX buffer is released using ffa_release_rx_buffer
+ *
+ * Return:
+ *
+ * When part_uuid is NULL, all partitions data are retrieved from secure world
+ * When part_uuid is non NULL, data for partitions matching the given UUID are
+ * retrieved and the number of partitions is returned
+ * 0 is returned on success. Otherwise, failure
+ */
+static int ffa_query_partitions_info(struct udevice *dev, struct ffa_partition_uuid *part_uuid,
+				     u32 *pcount)
+{
+	struct ffa_partition_uuid query_uuid = {0};
+	ffa_value_t res = {0};
+	int ffa_errno;
+
+	/*
+	 * If a UUID is specified. Information for one or more
+	 * partitions in the system is queried. Otherwise, information
+	 * for all installed partitions is queried
+	 */
+
+	if (part_uuid) {
+		if (!pcount)
+			return -EINVAL;
+
+		query_uuid = *part_uuid;
+	} else if (pcount) {
+		return -EINVAL;
+	}
+
+	invoke_ffa_fn((ffa_value_t){
+			.a0 = FFA_SMC_32(FFA_PARTITION_INFO_GET),
+			.a1 = query_uuid.a1,
+			.a2 = query_uuid.a2,
+			.a3 = query_uuid.a3,
+			.a4 = query_uuid.a4,
+			}, &res);
+
+	if (res.a0 == FFA_SMC_32(FFA_SUCCESS)) {
+		int ret;
+
+		/*
+		 * res.a2 contains the count of partition information descriptors
+		 * populated in the RX buffer
+		 */
+		if (res.a2) {
+			ret = ffa_read_partitions_info(dev, (u32)res.a2, part_uuid);
+			if (ret) {
+				log_err("failed reading SP(s) data , err (%d)\n", ret);
+				ffa_release_rx_buffer_hdlr(dev);
+				return -EINVAL;
+			}
+		}
+
+		/* Return the SP count (when querying using a UUID) */
+		if (pcount)
+			*pcount = (u32)res.a2;
+
+		/*
+		 * After calling FFA_PARTITION_INFO_GET the buffer ownership
+		 * is assigned to the consumer (u-boot). So, we need to give
+		 * the ownership back to the SPM or hypervisor
+		 */
+		ret = ffa_release_rx_buffer_hdlr(dev);
+
+		return ret;
+	}
+
+	ffa_errno = res.a2;
+	ffa_print_error_log(FFA_PARTITION_INFO_GET, ffa_errno);
+
+	return ffa_to_std_errno(ffa_errno);
+}
+
+/**
+ * ffa_get_partitions_info_hdlr() - FFA_PARTITION_INFO_GET handler function
+ *	@uuid_str: pointer to the UUID string
+ *	@sp_count: address of the variable containing the number of partitions matching the UUID
+ *			 The variable is set by the driver
+ *	@sp_descs: address of the descriptors of the partitions matching the UUID
+ *			 The address is set by the driver
+ *
+ * Return the number of partitions and their descriptors matching the UUID
+ *
+ * Query the secure partition data from uc_priv.
+ * If not found, invoke FFA_PARTITION_INFO_GET FF-A function to query the partition information
+ * from secure world.
+ *
+ * A client of the FF-A driver should know the UUID of the service it wants to
+ * access. It should use the UUID to request the FF-A driver to provide the
+ * partition(s) information of the service. The FF-A driver uses
+ * PARTITION_INFO_GET to obtain this information. This is implemented through
+ * ffa_get_partitions_info_hdlr() function.
+ * If the partition(s) matching the UUID found, the partition(s) information and the
+ * number are returned.
+ * If no partition matching the UUID is found in the cached area, a new FFA_PARTITION_INFO_GET
+ * call is issued.
+ * If not done yet, the UUID is updated in the cached area.
+ * This assumes that partitions data does not change in the secure world.
+ * Otherwise u-boot will have an outdated partition data. The benefit of caching
+ * the information in the FF-A driver is to accommodate discovery after
+ * ExitBootServices().
+ *
+ * Return:
+ *
+ * @sp_count: the number of partitions
+ * @sp_descs: address of the partitions descriptors
+ *
+ * On success 0 is returned. Otherwise, failure
+ */
+int ffa_get_partitions_info_hdlr(struct udevice *dev, const char *uuid_str,
+				 u32 *sp_count, struct ffa_partition_desc **sp_descs)
+{
+	u32 i;
+	struct ffa_partition_uuid part_uuid = {0};
+	struct ffa_priv *uc_priv;
+	struct ffa_partition_desc *rx_descs;
+
+	uc_priv = dev_get_uclass_priv(dev);
+
+	if (!uc_priv->partitions.count || !uc_priv->partitions.descs) {
+		log_err("no partition installed\n");
+		return -EINVAL;
+	}
+
+	if (!uuid_str) {
+		log_err("no UUID provided\n");
+		return -EINVAL;
+	}
+
+	if (!sp_count) {
+		log_err("no count argument provided\n");
+		return -EINVAL;
+	}
+
+	if (!sp_descs) {
+		log_err("no info argument provided\n");
+		return -EINVAL;
+	}
+
+	if (uuid_str_to_le_bin(uuid_str, (unsigned char *)&part_uuid)) {
+		log_err("invalid UUID\n");
+		return -EINVAL;
+	}
+
+	log_debug("Searching FF-A partitions using the provided UUID\n");
+
+	*sp_count = 0;
+	*sp_descs = uc_priv->pair.rxbuf;
+	rx_descs = *sp_descs;
+
+	/* Search in the cached partitions */
+	for (i = 0; i < uc_priv->partitions.count; i++)
+		if (ffa_uuid_are_identical(&uc_priv->partitions.descs[i].sp_uuid,
+					   &part_uuid)) {
+			log_debug("FF-A partition ID %x matches the provided UUID\n",
+				  uc_priv->partitions.descs[i].info.id);
+
+			(*sp_count)++;
+			*rx_descs++ = uc_priv->partitions.descs[i];
+			}
+
+	if (!(*sp_count)) {
+		int ret;
+
+		log_debug("No FF-A partition found. Querying framework ...\n");
+
+		ret = ffa_query_partitions_info(dev, &part_uuid, sp_count);
+
+		if (!ret) {
+			log_debug("Number of FF-A partition(s) matching the UUID: %d\n", *sp_count);
+
+			if (*sp_count)
+				ret = ffa_get_partitions_info_hdlr(dev, uuid_str, sp_count,
+								   sp_descs);
+			else
+				ret = -ENODATA;
+		}
+
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * ffa_cache_partitions_info() - Query and saves all secure partitions data
+ * @dev: The FF-A bus device
+ *
+ * Invoke FFA_PARTITION_INFO_GET FF-A function to query from secure world
+ * all partitions information.
+ *
+ * The FFA_PARTITION_INFO_GET call is issued with nil UUID as an argument.
+ * All installed partitions information are returned. We cache them in uc_priv
+ * and we keep the UUID field empty (in FF-A 1.0 UUID is not provided by the partition descriptor)
+ *
+ * Called at the device probing level.
+ * ffa_cache_partitions_info uses ffa_query_partitions_info to get the data
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_cache_partitions_info(struct udevice *dev)
+{
+	return ffa_query_partitions_info(dev, NULL, NULL);
+}
+
+/**
+ * ffa_msg_send_direct_req_hdlr() - FFA_MSG_SEND_DIRECT_{REQ,RESP} handler function
+ * @dev: The FF-A bus device
+ * @dst_part_id: destination partition ID
+ * @msg: pointer to the message data preallocated by the client (in/out)
+ * @is_smc64: select 64-bit or 32-bit FF-A ABI
+ *
+ * Implement FFA_MSG_SEND_DIRECT_{REQ,RESP}
+ * FF-A functions.
+ *
+ * FFA_MSG_SEND_DIRECT_REQ is used to send the data to the secure partition.
+ * The response from the secure partition is handled by reading the
+ * FFA_MSG_SEND_DIRECT_RESP arguments.
+ *
+ * The maximum size of the data that can be exchanged is 40 bytes which is
+ * sizeof(struct ffa_send_direct_data) as defined by the FF-A specification 1.0
+ * in the section relevant to FFA_MSG_SEND_DIRECT_{REQ,RESP}
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_msg_send_direct_req_hdlr(struct udevice *dev, u16 dst_part_id,
+				 struct ffa_send_direct_data *msg, bool is_smc64)
+{
+	ffa_value_t res = {0};
+	int ffa_errno;
+	u64 req_mode, resp_mode;
+	struct ffa_priv *uc_priv;
+
+	uc_priv = dev_get_uclass_priv(dev);
+
+	/* No partition installed */
+	if (!uc_priv->partitions.count || !uc_priv->partitions.descs)
+		return -ENODEV;
+
+	if (is_smc64) {
+		req_mode = FFA_SMC_64(FFA_MSG_SEND_DIRECT_REQ);
+		resp_mode = FFA_SMC_64(FFA_MSG_SEND_DIRECT_RESP);
+	} else {
+		req_mode = FFA_SMC_32(FFA_MSG_SEND_DIRECT_REQ);
+		resp_mode = FFA_SMC_32(FFA_MSG_SEND_DIRECT_RESP);
+	}
+
+	invoke_ffa_fn((ffa_value_t){
+			.a0 = req_mode,
+			.a1 = PREP_SELF_ENDPOINT_ID(uc_priv->id) |
+				PREP_PART_ENDPOINT_ID(dst_part_id),
+			.a2 = 0,
+			.a3 = msg->data0,
+			.a4 = msg->data1,
+			.a5 = msg->data2,
+			.a6 = msg->data3,
+			.a7 = msg->data4,
+			}, &res);
+
+	while (res.a0 == FFA_SMC_32(FFA_INTERRUPT))
+		invoke_ffa_fn((ffa_value_t){
+			.a0 = FFA_SMC_32(FFA_RUN),
+			.a1 = res.a1,
+			}, &res);
+
+	if (res.a0 == FFA_SMC_32(FFA_SUCCESS)) {
+		/* Message sent with no response */
+		return 0;
+	}
+
+	if (res.a0 == resp_mode) {
+		/* Message sent with response extract the return data */
+		msg->data0 = res.a3;
+		msg->data1 = res.a4;
+		msg->data2 = res.a5;
+		msg->data3 = res.a6;
+		msg->data4 = res.a7;
+
+		return 0;
+	}
+
+	ffa_errno = res.a2;
+	return ffa_to_std_errno(ffa_errno);
+}
+
+/* FF-A driver operations (used by clients for communicating with FF-A)*/
+
+/**
+ * ffa_partition_info_get() - FFA_PARTITION_INFO_GET driver operation
+ *	@uuid_str: pointer to the UUID string
+ *	@sp_count: address of the variable containing the number of partitions matching the UUID
+ *			 The variable is set by the driver
+ *	@sp_descs: address of the descriptors of the partitions matching the UUID
+ *			 The address is set by the driver
+ *
+ * Driver operation for FFA_PARTITION_INFO_GET.
+ * Please see ffa_get_partitions_info_hdlr() description for more details.
+ *
+ * Return:
+ *
+ * @sp_count: the number of partitions
+ * @sp_descs: address of the partitions descriptors
+ *
+ * On success 0 is returned. Otherwise, failure
+ */
+int ffa_partition_info_get(struct udevice *dev, const char *uuid_str,
+			   u32 *sp_count, struct ffa_partition_desc **sp_descs)
+{
+	struct ffa_bus_ops *ops = ffa_get_ops(dev);
+
+	if (!ops->partition_info_get)
+		return -ENOSYS;
+
+	return ops->partition_info_get(dev, uuid_str, sp_count, sp_descs);
+}
+
+/**
+ * ffa_sync_send_receive() - FFA_MSG_SEND_DIRECT_{REQ,RESP} driver operation
+ * @dev: The FF-A bus device
+ * @dst_part_id: destination partition ID
+ * @msg: pointer to the message data preallocated by the client (in/out)
+ * @is_smc64: select 64-bit or 32-bit FF-A ABI
+ *
+ * Driver operation for FFA_MSG_SEND_DIRECT_{REQ,RESP}.
+ * Please see ffa_msg_send_direct_req_hdlr() description for more details.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_sync_send_receive(struct udevice *dev, u16 dst_part_id,
+			  struct ffa_send_direct_data *msg, bool is_smc64)
+{
+	struct ffa_bus_ops *ops = ffa_get_ops(dev);
+
+	if (!ops->sync_send_receive)
+		return -ENOSYS;
+
+	return ops->sync_send_receive(dev, dst_part_id, msg, is_smc64);
+}
+
+/**
+ * ffa_rxtx_unmap() - FFA_RXTX_UNMAP driver operation
+ * @dev: The FF-A bus device
+ *
+ * Driver operation for FFA_RXTX_UNMAP.
+ * Please see ffa_unmap_rxtx_buffers_hdlr() description for more details.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_rxtx_unmap(struct udevice *dev)
+{
+	struct ffa_bus_ops *ops = ffa_get_ops(dev);
+
+	if (!ops->rxtx_unmap)
+		return -ENOSYS;
+
+	return ops->rxtx_unmap(dev);
+}
+
+/**
+ * ffa_do_probe() - probing FF-A framework
+ * @dev:	the FF-A bus device (arm_ffa)
+ *
+ * Probing is triggered on demand by clients searching for the uclass.
+ * At probe level the following actions are done:
+ *	- saving the FF-A framework version in uc_priv
+ *	- querying from secure world the u-boot endpoint ID
+ *	- querying from secure world the supported features of FFA_RXTX_MAP
+ *	- mapping the RX/TX buffers
+ *	- querying from secure world all the partitions information
+ *
+ * All data queried from secure world is saved in uc_priv.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_do_probe(struct udevice *dev)
+{
+	int ret;
+
+	ret = ffa_get_version_hdlr(dev);
+	if (ret)
+		return ret;
+
+	ret = ffa_get_endpoint_id(dev);
+	if (ret)
+		return ret;
+
+	ret = ffa_get_rxtx_map_features_hdlr(dev);
+	if (ret)
+		return ret;
+
+	ret = ffa_map_rxtx_buffers_hdlr(dev);
+	if (ret)
+		return ret;
+
+	ret = ffa_cache_partitions_info(dev);
+	if (ret) {
+		ffa_unmap_rxtx_buffers_hdlr(dev);
+		return ret;
+	}
+
+	return 0;
+}
+
+UCLASS_DRIVER(ffa) = {
+	.name			= "ffa",
+	.id			= UCLASS_FFA,
+	.pre_probe		= ffa_do_probe,
+	.pre_remove		= ffa_unmap_rxtx_buffers_hdlr,
+	.per_device_auto	= sizeof(struct ffa_priv)
+};
diff --git a/drivers/firmware/arm-ffa/arm-ffa.c b/drivers/firmware/arm-ffa/arm-ffa.c
new file mode 100644
index 0000000000..ee0bf9a55b
--- /dev/null
+++ b/drivers/firmware/arm-ffa/arm-ffa.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <arm_ffa.h>
+#include <arm_ffa_priv.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * invoke_ffa_fn() - SMC wrapper
+ * @args: FF-A ABI arguments to be copied to Xn registers
+ * @res: FF-A ABI return data to be copied from Xn registers
+ *
+ * Calls low level SMC assembly function
+ */
+void invoke_ffa_fn(ffa_value_t args, ffa_value_t *res)
+{
+	arm_smccc_1_2_smc(&args, res);
+}
+
+/**
+ * arm_ffa_discover() - perform FF-A discovery
+ * @dev: The Arm FF-A bus device (arm_ffa)
+ * Try to discover the FF-A framework. Discovery is performed by
+ * querying the FF-A framework version from secure world using the FFA_VERSION ABI.
+ * Return:
+ *
+ * true on success. Otherwise, false.
+ */
+static bool arm_ffa_discover(struct udevice *dev)
+{
+	int ret;
+
+	log_debug("Arm FF-A framework discovery\n");
+
+	ret = ffa_get_version_hdlr(dev);
+	if (ret)
+		return false;
+
+	return true;
+}
+
+/**
+ * arm_ffa_is_supported() - FF-A bus discovery callback
+ * @invoke_fn: legacy SMC invoke function (not used)
+ *
+ * Perform FF-A discovery by calling arm_ffa_discover().
+ * Discovery is performed by querying the FF-A framework version from
+ * secure world using the FFA_VERSION ABI.
+ *
+ * The FF-A driver is registered as an SMCCC feature driver. So, features discovery
+ * callbacks are called by the PSCI driver (PSCI device is the SMCCC features
+ * root device).
+ *
+ * The FF-A driver supports the SMCCCv1.2 extended input/output registers.
+ * So, the legacy SMC invocation is not used.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static bool arm_ffa_is_supported(void (*invoke_fn)(ulong a0, ulong a1,
+						   ulong a2, ulong a3,
+						   ulong a4, ulong a5,
+						   ulong a6, ulong a7,
+						   struct arm_smccc_res *res))
+{
+	return arm_ffa_discover(NULL);
+}
+
+/* Arm FF-A driver operations */
+
+static const struct ffa_bus_ops ffa_ops = {
+	.partition_info_get = ffa_get_partitions_info_hdlr,
+	.sync_send_receive = ffa_msg_send_direct_req_hdlr,
+	.rxtx_unmap = ffa_unmap_rxtx_buffers_hdlr,
+};
+
+/* Registering the FF-A driver as an SMCCC feature driver */
+
+ARM_SMCCC_FEATURE_DRIVER(arm_ffa) = {
+	.driver_name = FFA_DRV_NAME,
+	.is_supported = arm_ffa_is_supported,
+};
+
+/* Declaring the FF-A driver under UCLASS_FFA */
+
+U_BOOT_DRIVER(arm_ffa) = {
+	.name		= FFA_DRV_NAME,
+	.id		= UCLASS_FFA,
+	.flags		= DM_REMOVE_OS_PREPARE,
+	.ops		= &ffa_ops,
+};
diff --git a/drivers/firmware/arm-ffa/ffa-emul-uclass.c b/drivers/firmware/arm-ffa/ffa-emul-uclass.c
new file mode 100644
index 0000000000..4bf9f6041f
--- /dev/null
+++ b/drivers/firmware/arm-ffa/ffa-emul-uclass.c
@@ -0,0 +1,720 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+#include <common.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <string.h>
+#include <asm/global_data.h>
+#include <asm/sandbox_arm_ffa.h>
+#include <asm/sandbox_arm_ffa_priv.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+#include <linux/errno.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* The partitions (SPs) table */
+static struct ffa_partition_desc sandbox_partitions[SANDBOX_PARTITIONS_CNT] = {
+	{
+		.info = { .id = SANDBOX_SP1_ID, .exec_ctxt = 0x5687, .properties = 0x89325621 },
+		.sp_uuid = {
+			.a1 = SANDBOX_SERVICE1_UUID_A1,
+			.a2 = SANDBOX_SERVICE1_UUID_A2,
+			.a3 = SANDBOX_SERVICE1_UUID_A3,
+			.a4 = SANDBOX_SERVICE1_UUID_A4,
+		}
+	},
+	{
+		.info = { .id = SANDBOX_SP3_ID, .exec_ctxt = 0x7687, .properties = 0x23325621 },
+		.sp_uuid = {
+			.a1 = SANDBOX_SERVICE2_UUID_A1,
+			.a2 = SANDBOX_SERVICE2_UUID_A2,
+			.a3 = SANDBOX_SERVICE2_UUID_A3,
+			.a4 = SANDBOX_SERVICE2_UUID_A4,
+		}
+	},
+	{
+		.info = { .id = SANDBOX_SP2_ID, .exec_ctxt = 0x9587, .properties = 0x45325621 },
+		.sp_uuid = {
+			.a1 = SANDBOX_SERVICE1_UUID_A1,
+			.a2 = SANDBOX_SERVICE1_UUID_A2,
+			.a3 = SANDBOX_SERVICE1_UUID_A3,
+			.a4 = SANDBOX_SERVICE1_UUID_A4,
+		}
+	},
+	{
+		.info = { .id = SANDBOX_SP4_ID, .exec_ctxt = 0x1487, .properties = 0x70325621 },
+		.sp_uuid = {
+			.a1 = SANDBOX_SERVICE2_UUID_A1,
+			.a2 = SANDBOX_SERVICE2_UUID_A2,
+			.a3 = SANDBOX_SERVICE2_UUID_A3,
+			.a4 = SANDBOX_SERVICE2_UUID_A4,
+		}
+	}
+
+};
+
+/* The emulator functions */
+
+/**
+ * sandbox_ffa_version() - Emulated FFA_VERSION handler function
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res:  The SMC return data
+ *
+ * Emulate FFA_VERSION FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+
+static int sandbox_ffa_version(struct udevice *emul, ffa_value_t *pargs, ffa_value_t *res)
+{
+	struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+	priv->fwk_version = FFA_VERSION_1_0;
+	res->a0 = priv->fwk_version;
+
+	/* x1-x7 MBZ */
+	memset(FFA_X1X7_MBZ_REG_START, 0, FFA_X1X7_MBZ_CNT * sizeof(ulong));
+
+	return 0;
+}
+
+/**
+ * sandbox_ffa_id_get() - Emulated FFA_ID_GET handler function
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res:  The SMC return data
+ *
+ * Emulate FFA_ID_GET FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_id_get(struct udevice *emul, ffa_value_t *pargs, ffa_value_t *res)
+{
+	struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+	res->a0 = FFA_SMC_32(FFA_SUCCESS);
+	res->a1 = 0;
+
+	priv->id = NS_PHYS_ENDPOINT_ID;
+	res->a2 = priv->id;
+
+	/* x3-x7 MBZ */
+	memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+
+	return 0;
+}
+
+/**
+ * sandbox_ffa_features() - Emulated FFA_FEATURES handler function
+ * @pargs: The SMC call input arguments a0-a7
+ * @res:  The SMC return data
+ *
+ * Emulate FFA_FEATURES FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_features(ffa_value_t *pargs, ffa_value_t *res)
+{
+	res->a1 = 0;
+
+	if (pargs->a1 == FFA_SMC_64(FFA_RXTX_MAP)) {
+		res->a0 = FFA_SMC_32(FFA_SUCCESS);
+		res->a2 = RXTX_BUFFERS_MIN_SIZE;
+		res->a3 = 0;
+		/* x4-x7 MBZ */
+		memset(FFA_X4X7_MBZ_REG_START, 0, FFA_X4X7_MBZ_CNT * sizeof(ulong));
+		return 0;
+	}
+
+	res->a0 = FFA_SMC_32(FFA_ERROR);
+	res->a2 = -NOT_SUPPORTED;
+	/* x3-x7 MBZ */
+	memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+	log_err("FF-A interface %lx not implemented\n", pargs->a1);
+
+	return ffa_to_std_errmap[NOT_SUPPORTED];
+}
+
+/**
+ * sandbox_ffa_partition_info_get() - Emulated FFA_PARTITION_INFO_GET handler
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res:  The SMC return data
+ *
+ * Emulate FFA_PARTITION_INFO_GET FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_partition_info_get(struct udevice *emul, ffa_value_t *pargs,
+					  ffa_value_t *res)
+{
+	struct ffa_partition_info *rxbuf_desc_info = NULL;
+	u32 descs_cnt;
+	u32 descs_size_bytes;
+	int ret;
+	struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+	res->a0 = FFA_SMC_32(FFA_ERROR);
+
+	if (!priv->pair.rxbuf) {
+		res->a2 = -DENIED;
+		ret = ffa_to_std_errmap[DENIED];
+		goto cleanup;
+	}
+
+	if (priv->pair_info.rxbuf_owned) {
+		res->a2 = -BUSY;
+		ret = ffa_to_std_errmap[BUSY];
+		goto cleanup;
+	}
+
+	if (!priv->partitions.descs) {
+		priv->partitions.descs = sandbox_partitions;
+		priv->partitions.count = SANDBOX_PARTITIONS_CNT;
+	}
+
+	descs_size_bytes = SANDBOX_PARTITIONS_CNT *
+		sizeof(struct ffa_partition_desc);
+
+	/* Abort if the RX buffer size is smaller than the descs buffer size */
+	if ((priv->pair_info.rxtx_buf_size * SZ_4K) < descs_size_bytes) {
+		res->a2 = -NO_MEMORY;
+		ret = ffa_to_std_errmap[NO_MEMORY];
+		goto cleanup;
+	}
+
+	rxbuf_desc_info = priv->pair.rxbuf;
+
+	/* No UUID specified. Return the information of all partitions */
+	if (!pargs->a1 && !pargs->a2 && !pargs->a3 && !pargs->a4) {
+		for (descs_cnt = 0; descs_cnt < SANDBOX_PARTITIONS_CNT; descs_cnt++)
+			*(rxbuf_desc_info++) = priv->partitions.descs[descs_cnt].info;
+
+		res->a0 = FFA_SMC_32(FFA_SUCCESS);
+		res->a2 = SANDBOX_PARTITIONS_CNT;
+		/* Transfer ownership to the consumer: the non secure world */
+		priv->pair_info.rxbuf_owned = 1;
+		ret = 0;
+
+		goto cleanup;
+	}
+
+	/* A UUID specified. Return the info of all SPs matching the UUID */
+
+	for (descs_cnt = 0 ; descs_cnt < SANDBOX_PARTITIONS_CNT ; descs_cnt++)
+		if (pargs->a1 == priv->partitions.descs[descs_cnt].sp_uuid.a1 &&
+		    pargs->a2 == priv->partitions.descs[descs_cnt].sp_uuid.a2 &&
+		    pargs->a3 == priv->partitions.descs[descs_cnt].sp_uuid.a3 &&
+		    pargs->a4 == priv->partitions.descs[descs_cnt].sp_uuid.a4) {
+			*(rxbuf_desc_info++) = priv->partitions.descs[descs_cnt].info;
+		}
+
+	if (rxbuf_desc_info != priv->pair.rxbuf) {
+		res->a0 = FFA_SMC_32(FFA_SUCCESS);
+		/* Store the partitions count */
+		res->a2 = (ulong)
+			(rxbuf_desc_info - (struct ffa_partition_info *)
+			 priv->pair.rxbuf);
+		ret = 0;
+
+		/* Transfer ownership to the consumer: the non secure world */
+		priv->pair_info.rxbuf_owned = 1;
+	} else {
+		/* Unrecognized UUID */
+		res->a2 = -INVALID_PARAMETERS;
+		ret = ffa_to_std_errmap[INVALID_PARAMETERS];
+	}
+
+cleanup:
+
+	log_err("FFA_PARTITION_INFO_GET (%ld)\n", res->a2);
+
+	res->a1 = 0;
+
+	/* x3-x7 MBZ */
+	memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+
+	return ret;
+}
+
+/**
+ * sandbox_ffa_rxtx_map() - Emulated FFA_RXTX_MAP handler
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res:  The SMC return data
+ *
+ * Emulate FFA_RXTX_MAP FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_rxtx_map(struct udevice *emul, ffa_value_t *pargs, ffa_value_t *res)
+{
+	int ret;
+	struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+	res->a0 = FFA_SMC_32(FFA_ERROR);
+
+	if (priv->pair.txbuf && priv->pair.rxbuf) {
+		res->a2 = -DENIED;
+		ret = ffa_to_std_errmap[DENIED];
+		goto feedback;
+	}
+
+	if (pargs->a3 >= RXTX_BUFFERS_MIN_PAGES && pargs->a1 && pargs->a2) {
+		priv->pair.txbuf = map_sysmem(pargs->a1, 0);
+		priv->pair.rxbuf = map_sysmem(pargs->a2, 0);
+		priv->pair_info.rxtx_buf_size = pargs->a3;
+		priv->pair_info.rxbuf_mapped = 1;
+		res->a0 = FFA_SMC_32(FFA_SUCCESS);
+		res->a2 = 0;
+		ret = 0;
+		goto feedback;
+	}
+
+	if (!pargs->a1 || !pargs->a2) {
+		res->a2 = -INVALID_PARAMETERS;
+		ret = ffa_to_std_errmap[INVALID_PARAMETERS];
+	} else {
+		res->a2 = -NO_MEMORY;
+		ret = ffa_to_std_errmap[NO_MEMORY];
+	}
+
+	log_err("Error in FFA_RXTX_MAP arguments (%d)\n",
+		(int)res->a2);
+
+feedback:
+
+	res->a1 = 0;
+
+	/* x3-x7 MBZ */
+	memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+
+	return ret;
+}
+
+/**
+ * sandbox_ffa_rxtx_unmap() - Emulated FFA_RXTX_UNMAP handler
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res:  The SMC return data
+ *
+ * Emulate FFA_RXTX_UNMAP FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_rxtx_unmap(struct udevice *emul, ffa_value_t *pargs, ffa_value_t *res)
+{
+	int ret;
+	struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+	res->a0 = FFA_SMC_32(FFA_ERROR);
+	res->a2 = -INVALID_PARAMETERS;
+	ret = ffa_to_std_errmap[INVALID_PARAMETERS];
+
+	if (GET_NS_PHYS_ENDPOINT_ID(pargs->a1) != priv->id)
+		goto feedback;
+
+	if (priv->pair.txbuf && priv->pair.rxbuf) {
+		priv->pair.txbuf = 0;
+		priv->pair.rxbuf = 0;
+		priv->pair_info.rxtx_buf_size = 0;
+		priv->pair_info.rxbuf_mapped = 0;
+		res->a0 = FFA_SMC_32(FFA_SUCCESS);
+		res->a2 = 0;
+		ret = 0;
+		goto feedback;
+	}
+
+	log_err("No buffer pair registered on behalf of the caller\n");
+
+feedback:
+
+	res->a1 = 0;
+
+	/* x3-x7 MBZ */
+	memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+
+	return ret;
+}
+
+/**
+ * sandbox_ffa_rx_release() - Emulated FFA_RX_RELEASE handler
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res:  The SMC return data
+ *
+ * Emulate FFA_RX_RELEASE FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_rx_release(struct udevice *emul, ffa_value_t *pargs, ffa_value_t *res)
+{
+	int ret;
+	struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+	if (!priv->pair_info.rxbuf_owned) {
+		res->a0 = FFA_SMC_32(FFA_ERROR);
+		res->a2 = -DENIED;
+		ret = ffa_to_std_errmap[DENIED];
+	} else {
+		priv->pair_info.rxbuf_owned = 0;
+		res->a0 = FFA_SMC_32(FFA_SUCCESS);
+		res->a2 = 0;
+		ret = 0;
+	}
+
+	res->a1 = 0;
+
+	/* x3-x7 MBZ */
+	memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+
+	return ret;
+}
+
+/**
+ * sandbox_ffa_sp_valid() - Check SP validity
+ * @emul: The sandbox FF-A emulator device
+ * @part_id:	partition ID to check
+ *
+ * Search the input ID in the descriptors table.
+ *
+ * Return:
+ *
+ * 1 on success (Partition found). Otherwise, failure
+ */
+static int sandbox_ffa_sp_valid(struct udevice *emul, u16 part_id)
+{
+	u32 descs_cnt;
+	struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+	for (descs_cnt = 0 ; descs_cnt < SANDBOX_PARTITIONS_CNT ; descs_cnt++)
+		if (priv->partitions.descs[descs_cnt].info.id == part_id)
+			return 1;
+
+	return 0;
+}
+
+/**
+ * sandbox_ffa_msg_send_direct_req() - Emulated FFA_MSG_SEND_DIRECT_{REQ,RESP} handler
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res:  The SMC return data
+ *
+ * Emulate FFA_MSG_SEND_DIRECT_{REQ,RESP} FF-A ABIs.
+ * Only SMC 64-bit is supported in Sandbox.
+ *
+ * Emulating interrupts is not supported. So, FFA_RUN and FFA_INTERRUPT are not
+ * supported. In case of success FFA_MSG_SEND_DIRECT_RESP is returned with
+ * default pattern data (0xff).
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_msg_send_direct_req(struct udevice *emul,
+					   ffa_value_t *pargs, ffa_value_t *res)
+{
+	u16 part_id;
+	struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+	part_id = GET_DST_SP_ID(pargs->a1);
+
+	if (GET_NS_PHYS_ENDPOINT_ID(pargs->a1) != priv->id ||
+	    !sandbox_ffa_sp_valid(emul, part_id) || pargs->a2) {
+		res->a0 = FFA_SMC_32(FFA_ERROR);
+		res->a1 = 0;
+		res->a2 = -INVALID_PARAMETERS;
+
+		/* x3-x7 MBZ */
+		memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+
+		return ffa_to_std_errmap[INVALID_PARAMETERS];
+	}
+
+	res->a0 = FFA_SMC_64(FFA_MSG_SEND_DIRECT_RESP);
+
+	res->a1 = PREP_SRC_SP_ID(part_id) |
+		PREP_NS_PHYS_ENDPOINT_ID(priv->id);
+
+	res->a2 = 0;
+
+	/* Return 0xff bytes as a response */
+	res->a3 = -1UL;
+	res->a4 = -1UL;
+	res->a5 = -1UL;
+	res->a6 = -1UL;
+	res->a7 = -1UL;
+
+	return 0;
+}
+
+/**
+ * sandbox_ffa_get_rxbuf_flags() - Read the mapping/ownership flags
+ * @emul: The sandbox FF-A emulator device
+ * @queried_func_id:	The FF-A function to be queried
+ * @func_data:  Pointer to the FF-A function arguments container structure
+ *
+ * Query the status flags of the following emulated
+ * ABIs: FFA_RXTX_MAP, FFA_RXTX_UNMAP, FFA_RX_RELEASE.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_get_rxbuf_flags(struct udevice *emul, u32 queried_func_id,
+				       struct ffa_sandbox_data *func_data)
+{
+	struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+	if (!func_data)
+		return -EINVAL;
+
+	if (!func_data->data0 || func_data->data0_size != sizeof(u8))
+		return -EINVAL;
+
+	switch (queried_func_id) {
+	case FFA_RXTX_MAP:
+	case FFA_RXTX_UNMAP:
+		*((u8 *)func_data->data0) = priv->pair_info.rxbuf_mapped;
+		return 0;
+	case FFA_RX_RELEASE:
+		*((u8 *)func_data->data0) = priv->pair_info.rxbuf_owned;
+		return 0;
+	default:
+		log_err("The querried FF-A interface flag (%d) undefined\n",
+			queried_func_id);
+		return -EINVAL;
+	}
+}
+
+/**
+ * sandbox_ffa_get_fwk_version() - Return the FFA framework version
+ * @emul: The sandbox FF-A emulator device
+ * @func_data:  Pointer to the FF-A function arguments container structure
+ *
+ * Return the FFA framework version read from the FF-A emulator data.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_get_fwk_version(struct udevice *emul, struct ffa_sandbox_data *func_data)
+{
+	struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+	if (!func_data)
+		return -EINVAL;
+
+	if (!func_data->data0 ||
+	    func_data->data0_size != sizeof(priv->fwk_version))
+		return -EINVAL;
+
+	*((u32 *)func_data->data0) = priv->fwk_version;
+
+	return 0;
+}
+
+/**
+ * sandbox_ffa_get_parts() - Return the address of partitions data
+ * @emul: The sandbox FF-A emulator device
+ * @func_data:  Pointer to the FF-A function arguments container structure
+ *
+ * Return the address of partitions data read from the FF-A emulator data.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_get_parts(struct udevice *emul, struct ffa_sandbox_data *func_data)
+{
+	struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+	if (!func_data)
+		return -EINVAL;
+
+	if (!func_data->data0 ||
+	    func_data->data0_size != sizeof(struct ffa_partitions *))
+		return -EINVAL;
+
+	*((struct ffa_partitions **)func_data->data0) = &priv->partitions;
+
+	return 0;
+}
+
+/**
+ * sandbox_query_ffa_emul_state() - Inspect the FF-A ABIs
+ * @queried_func_id:	The FF-A function to be queried
+ * @func_data:  Pointer to the FF-A function arguments container structure
+ *
+ * Query the status of FF-A ABI specified in the input argument.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int sandbox_query_ffa_emul_state(u32 queried_func_id,
+				 struct ffa_sandbox_data *func_data)
+{
+	struct udevice *emul;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_FFA_EMUL, &emul);
+	if (ret) {
+		log_err("Cannot find FF-A emulator during querying state\n");
+		return ret;
+	}
+
+	switch (queried_func_id) {
+	case FFA_RXTX_MAP:
+	case FFA_RXTX_UNMAP:
+	case FFA_RX_RELEASE:
+		return sandbox_ffa_get_rxbuf_flags(emul, queried_func_id, func_data);
+	case FFA_VERSION:
+		return sandbox_ffa_get_fwk_version(emul, func_data);
+	case FFA_PARTITION_INFO_GET:
+		return sandbox_ffa_get_parts(emul, func_data);
+	default:
+		log_err("Undefined FF-A interface (%d)\n",
+			queried_func_id);
+		return -EINVAL;
+	}
+}
+
+/**
+ * sandbox_arm_ffa_smccc_smc() - FF-A SMC call emulation
+ * @args:	the SMC call arguments
+ * @res:	the SMC call returned data
+ *
+ * Emulate the FF-A ABIs SMC call.
+ * The emulated FF-A ABI is identified and invoked.
+ * FF-A emulation is based on the FF-A specification 1.0
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure.
+ * FF-A protocol error codes are returned using the registers arguments as
+ * described by the specification
+ */
+void sandbox_arm_ffa_smccc_smc(ffa_value_t *args, ffa_value_t *res)
+{
+	int ret = 0;
+	struct udevice *emul;
+
+	ret = uclass_first_device_err(UCLASS_FFA_EMUL, &emul);
+	if (ret) {
+		log_err("Cannot find FF-A emulator during SMC emulation\n");
+		return;
+	}
+
+	switch (args->a0) {
+	case FFA_SMC_32(FFA_VERSION):
+		ret = sandbox_ffa_version(emul, args, res);
+		break;
+	case FFA_SMC_32(FFA_PARTITION_INFO_GET):
+		ret = sandbox_ffa_partition_info_get(emul, args, res);
+		break;
+	case FFA_SMC_32(FFA_RXTX_UNMAP):
+		ret = sandbox_ffa_rxtx_unmap(emul, args, res);
+		break;
+	case FFA_SMC_64(FFA_MSG_SEND_DIRECT_REQ):
+		ret = sandbox_ffa_msg_send_direct_req(emul, args, res);
+		break;
+	case FFA_SMC_32(FFA_ID_GET):
+		ret = sandbox_ffa_id_get(emul, args, res);
+		break;
+	case FFA_SMC_32(FFA_FEATURES):
+		ret = sandbox_ffa_features(args, res);
+		break;
+	case FFA_SMC_64(FFA_RXTX_MAP):
+		ret = sandbox_ffa_rxtx_map(emul, args, res);
+		break;
+	case FFA_SMC_32(FFA_RX_RELEASE):
+		ret = sandbox_ffa_rx_release(emul, args, res);
+		break;
+	default:
+		log_err("Undefined FF-A interface (%lx)\n",
+			args->a0);
+	}
+
+	if (ret != 0)
+		log_err("FF-A ABI internal failure (%d)\n", ret);
+}
+
+/**
+ * invoke_ffa_fn() - SMC wrapper
+ * @args: FF-A ABI arguments to be copied to Xn registers
+ * @res: FF-A ABI return data to be copied from Xn registers
+ *
+ * Calls the emulated SMC call.
+ */
+void invoke_ffa_fn(ffa_value_t args, ffa_value_t *res)
+{
+	sandbox_arm_ffa_smccc_smc(&args, res);
+}
+
+/**
+ * ffa_emul_find() - Find the FF-A emulator
+ * @dev:	the sandbox FF-A device (sandbox-arm-ffa)
+ * @emulp:	the FF-A emulator device (sandbox-ffa-emul)
+ *
+ * Search for the FF-A emulator and returns its device pointer.
+ *
+ * Return:
+ * 0 on success. Otherwise, failure
+ */
+int ffa_emul_find(struct udevice *dev, struct udevice **emulp)
+{
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_FFA_EMUL, emulp);
+	if (ret) {
+		log_err("Cannot find FF-A emulator\n");
+		return ret;
+	}
+
+	log_debug("FF-A emulator ready to use\n");
+
+	return 0;
+}
+
+UCLASS_DRIVER(ffa_emul) = {
+	.name		= "ffa_emul",
+	.id		= UCLASS_FFA_EMUL,
+	.post_bind = dm_scan_fdt_dev,
+};
+
+static const struct udevice_id sandbox_ffa_emul_ids[] = {
+	{ .compatible = "sandbox,arm-ffa-emul" },
+	{ }
+};
+
+/* Declaring the sandbox FF-A emulator under UCLASS_FFA_EMUL */
+U_BOOT_DRIVER(sandbox_ffa_emul) = {
+	.name		= "sandbox_ffa_emul",
+	.id		= UCLASS_FFA_EMUL,
+	.of_match	= sandbox_ffa_emul_ids,
+	.priv_auto	= sizeof(struct sandbox_ffa_emul),
+};
diff --git a/drivers/firmware/arm-ffa/sandbox_ffa.c b/drivers/firmware/arm-ffa/sandbox_ffa.c
new file mode 100644
index 0000000000..11142429c0
--- /dev/null
+++ b/drivers/firmware/arm-ffa/sandbox_ffa.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+#include <common.h>
+#include <arm_ffa.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/sandbox_arm_ffa_priv.h>
+#include <dm/device-internal.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * sandbox_ffa_discover() - perform sandbox FF-A discovery
+ * @dev: The sandbox FF-A bus device
+ * Try to discover the FF-A framework. Discovery is performed by
+ * querying the FF-A framework version from secure world using the FFA_VERSION ABI.
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_discover(struct udevice *dev)
+{
+	int ret;
+	struct udevice *emul;
+
+	log_debug("Emulated FF-A framework discovery\n");
+
+	ret = ffa_emul_find(dev, &emul);
+	if (ret) {
+		log_err("Cannot find FF-A emulator\n");
+		return ret;
+	}
+
+	ret = ffa_get_version_hdlr(dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/**
+ * sandbox_ffa_probe() - The sandbox FF-A driver probe function
+ * @dev:	the sandbox-arm-ffa device
+ * Save the emulator device in uc_priv.
+ * Return:
+ *
+ * 0 on success.
+ */
+static int sandbox_ffa_probe(struct udevice *dev)
+{
+	int ret;
+	struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	ret = uclass_first_device_err(UCLASS_FFA_EMUL, &uc_priv->emul);
+	if (ret) {
+		log_err("Cannot find FF-A emulator\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * sandbox_ffa_bind() - The sandbox FF-A driver bind function
+ * @dev:	the sandbox-arm-ffa device
+ * Try to discover the emulated FF-A bus.
+ * Return:
+ *
+ * 0 on success.
+ */
+static int sandbox_ffa_bind(struct udevice *dev)
+{
+	int ret;
+
+	ret = sandbox_ffa_discover(dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/* Sandbox Arm FF-A emulator operations */
+
+static const struct ffa_bus_ops sandbox_ffa_ops = {
+	.partition_info_get = ffa_get_partitions_info_hdlr,
+	.sync_send_receive = ffa_msg_send_direct_req_hdlr,
+	.rxtx_unmap = ffa_unmap_rxtx_buffers_hdlr,
+};
+
+static const struct udevice_id sandbox_ffa_id[] = {
+	{ "sandbox,arm-ffa", 0 },
+	{ },
+};
+
+/* Declaring the sandbox FF-A driver under UCLASS_FFA */
+U_BOOT_DRIVER(sandbox_arm_ffa) = {
+	.name		= "sandbox_arm_ffa",
+	.of_match = sandbox_ffa_id,
+	.id		= UCLASS_FFA,
+	.bind		= sandbox_ffa_bind,
+	.probe		= sandbox_ffa_probe,
+	.ops		= &sandbox_ffa_ops,
+};
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index dc8e3ad2b9..ab4c4f1a69 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -23,10 +23,10 @@
 #define XST_PM_NO_ACCESS	2002L
 #define XST_PM_ALREADY_CONFIGURED	2009L
 
-struct zynqmp_power {
+static struct zynqmp_power {
 	struct mbox_chan tx_chan;
 	struct mbox_chan rx_chan;
-} zynqmp_power = {};
+} zynqmp_power __section(".data");
 
 #define NODE_ID_LOCATION	5
 
@@ -63,29 +63,32 @@ static unsigned int xpm_configobject_close[] = {
 
 int zynqmp_pmufw_config_close(void)
 {
-	zynqmp_pmufw_load_config_object(xpm_configobject_close,
-					sizeof(xpm_configobject_close));
-	return 0;
+	return zynqmp_pmufw_load_config_object(xpm_configobject_close,
+					       sizeof(xpm_configobject_close));
 }
 
 int zynqmp_pmufw_node(u32 id)
 {
-	static bool skip_config;
-	int ret;
+	static bool check = true;
+	static bool permission = true;
+
+	if (check) {
+		check = false;
+
+		if (zynqmp_pmufw_node(NODE_OCM_BANK_0) == -EACCES) {
+			printf("PMUFW:  No permission to change config object\n");
+			permission = false;
+		}
+	}
 
-	if (skip_config)
+	if (!permission)
 		return 0;
 
 	/* Record power domain id */
 	xpm_configobject[NODE_ID_LOCATION] = id;
 
-	ret = zynqmp_pmufw_load_config_object(xpm_configobject,
-					      sizeof(xpm_configobject));
-
-	if (ret == XST_PM_NO_ACCESS && id == NODE_OCM_BANK_0)
-		skip_config = true;
-
-	return 0;
+	return zynqmp_pmufw_load_config_object(xpm_configobject,
+					       sizeof(xpm_configobject));
 }
 
 static int do_pm_probe(void)
@@ -235,8 +238,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
  *
  * @cfg_obj: Pointer to the configuration object
  * @size:    Size of @cfg_obj in bytes
- * Return:   0 on success otherwise negative errno. If the config object
- *           is not loadable returns positive errno XST_PM_NO_ACCESS(2002)
+ * Return:   0 on success otherwise negative errno.
  */
 int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
 {
@@ -251,10 +253,6 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
 	err = xilinx_pm_request(PM_SET_CONFIGURATION, (u32)(u64)cfg_obj, 0, 0,
 				0, ret_payload);
 	if (err == XST_PM_NO_ACCESS) {
-		if (((u32 *)cfg_obj)[NODE_ID_LOCATION] == NODE_OCM_BANK_0) {
-			printf("PMUFW:  No permission to change config object\n");
-			return err;
-		}
 		return -EACCES;
 	}
 
@@ -298,9 +296,6 @@ static int zynqmp_power_probe(struct udevice *dev)
 	       ret >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
 	       ret & ZYNQMP_PM_VERSION_MINOR_MASK);
 
-	if (IS_ENABLED(CONFIG_ARCH_ZYNQMP))
-		zynqmp_pmufw_node(NODE_OCM_BANK_0);
-
 	return 0;
 };
 
@@ -320,7 +315,8 @@ U_BOOT_DRIVER(zynqmp_power) = {
 int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
 				     u32 arg3, u32 *ret_payload)
 {
-	debug("%s at EL%d, API ID: 0x%0x\n", __func__, current_el(), api_id);
+	debug("%s at EL%d, API ID: 0x%0x, 0x%0x, 0x%0x, 0x%0x, 0x%0x\n",
+	      __func__, current_el(), api_id, arg0, arg1, arg2, arg3);
 
 	if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 #if defined(CONFIG_ZYNQMP_IPI)
@@ -398,7 +394,7 @@ static int zynqmp_firmware_bind(struct udevice *dev)
 		}
 	}
 
-	return dm_scan_fdt_dev(dev);
+	return 0;
 }
 
 U_BOOT_DRIVER(zynqmp_firmware) = {
diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c
index 54d563d929..02de692d66 100644
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
@@ -46,7 +46,7 @@ int scmi_to_linux_errno(s32 scmi_code)
 
 	for (n = 0; n < ARRAY_SIZE(scmi_linux_errmap); n++)
 		if (scmi_code == scmi_linux_errmap[n].scmi)
-			return scmi_linux_errmap[1].errno;
+			return scmi_linux_errmap[n].errno;
 
 	return -EPROTO;
 }
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index bd7379ae55..72f572d824 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -265,7 +265,7 @@ static int ti_sci_do_xfer(struct ti_sci_info *info,
 	if (xfer->rx_len) {
 		ret = ti_sci_get_response(info, xfer, &info->chan_rx);
 		if (!ti_sci_is_response_ack(xfer->tx_message.buf)) {
-			dev_err(info->dev, "Message not acknowledged");
+			dev_err(info->dev, "Message not acknowledged\n");
 			ret = -ENODEV;
 		}
 	}
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 7f6b6bc73a..81e6d8ffc0 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -244,6 +244,21 @@ int fpga_loads(int devnum, const void *buf, size_t size,
 }
 #endif
 
+static int fpga_load_event_notify(const void *buf, size_t bsize, int result)
+{
+	if (CONFIG_IS_ENABLED(EVENT)) {
+		struct event_fpga_load load = {
+			.buf = buf,
+			.bsize = bsize,
+			.result = result
+		};
+
+		return event_notify(EVT_FPGA_LOAD, &load, sizeof(load));
+	}
+
+	return 0;
+}
+
 /*
  * Generic multiplexing code
  */
@@ -251,6 +266,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype,
 	      int flags)
 {
 	int ret_val = FPGA_FAIL;           /* assume failure */
+	int ret_notify;
 	const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
 					      (char *)__func__);
 
@@ -284,6 +300,10 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype,
 		}
 	}
 
+	ret_notify = fpga_load_event_notify(buf, bsize, ret_val);
+	if (ret_notify)
+		return ret_notify;
+
 	return ret_val;
 }
 
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c
index d3876a8f54..be58db5427 100644
--- a/drivers/fpga/versalpl.c
+++ b/drivers/fpga/versalpl.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * (C) Copyright 2019, Xilinx, Inc,
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 #include <common.h>
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index 7b5128fe27..b1f201fb18 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * (C) Copyright 2015 - 2016, Xilinx, Inc,
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
  */
 
 #include <console.h>
diff --git a/drivers/fwu-mdata/Kconfig b/drivers/fwu-mdata/Kconfig
index 36c4479a59..42736a5e43 100644
--- a/drivers/fwu-mdata/Kconfig
+++ b/drivers/fwu-mdata/Kconfig
@@ -6,6 +6,11 @@ config FWU_MDATA
 	  FWU Metadata partitions reside on the same storage device
 	  which contains the other FWU updatable firmware images.
 
+choice
+	prompt "Storage Layout Scheme"
+	depends on FWU_MDATA
+	default FWU_MDATA_GPT_BLK
+
 config FWU_MDATA_GPT_BLK
 	bool "FWU Metadata access for GPT partitioned Block devices"
 	select PARTITION_TYPE_GUID
@@ -14,3 +19,13 @@ config FWU_MDATA_GPT_BLK
 	help
 	  Enable support for accessing FWU Metadata on GPT partitioned
 	  block devices.
+
+config FWU_MDATA_MTD
+	bool "Raw MTD devices"
+	depends on MTD
+	help
+	  Enable support for accessing FWU Metadata on non-partitioned
+	  (or non-GPT partitioned, e.g. partition nodes in devicetree)
+	  MTD devices.
+
+endchoice
diff --git a/drivers/fwu-mdata/Makefile b/drivers/fwu-mdata/Makefile
index 3fee64c10c..06c49747ba 100644
--- a/drivers/fwu-mdata/Makefile
+++ b/drivers/fwu-mdata/Makefile
@@ -6,3 +6,4 @@
 
 obj-$(CONFIG_FWU_MDATA) += fwu-mdata-uclass.o
 obj-$(CONFIG_FWU_MDATA_GPT_BLK) += gpt_blk.o
+obj-$(CONFIG_FWU_MDATA_MTD) += raw_mtd.o
diff --git a/drivers/fwu-mdata/fwu-mdata-uclass.c b/drivers/fwu-mdata/fwu-mdata-uclass.c
index b477e9603f..0a8edaaa41 100644
--- a/drivers/fwu-mdata/fwu-mdata-uclass.c
+++ b/drivers/fwu-mdata/fwu-mdata-uclass.c
@@ -14,170 +14,39 @@
 
 #include <linux/errno.h>
 #include <linux/types.h>
-#include <u-boot/crc.h>
 
 /**
- * fwu_get_mdata_part_num() - Get the FWU metadata partition numbers
- * @dev: FWU metadata device
- * @mdata_parts: array for storing the metadata partition numbers
- *
- * Get the partition numbers on the storage device on which the
- * FWU metadata is stored. Two partition numbers will be returned.
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_get_mdata_part_num(struct udevice *dev, uint *mdata_parts)
-{
-	const struct fwu_mdata_ops *ops = device_get_ops(dev);
-
-	if (!ops->get_mdata_part_num) {
-		log_debug("get_mdata_part_num() method not defined\n");
-		return -ENOSYS;
-	}
-
-	return ops->get_mdata_part_num(dev, mdata_parts);
-}
-
-/**
- * fwu_read_mdata_partition() - Read the FWU metadata from a partition
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- * @part_num: Partition number from which FWU metadata is to be read
- *
- * Read the FWU metadata from the specified partition number
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_read_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata,
-			     uint part_num)
-{
-	const struct fwu_mdata_ops *ops = device_get_ops(dev);
-
-	if (!ops->read_mdata_partition) {
-		log_debug("read_mdata_partition() method not defined\n");
-		return -ENOSYS;
-	}
-
-	return ops->read_mdata_partition(dev, mdata, part_num);
-}
-
-/**
- * fwu_write_mdata_partition() - Write the FWU metadata to a partition
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- * @part_num: Partition number to which FWU metadata is to be written
- *
- * Write the FWU metadata to the specified partition number
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_write_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata,
-			      uint part_num)
-{
-	const struct fwu_mdata_ops *ops = device_get_ops(dev);
-
-	if (!ops->write_mdata_partition) {
-		log_debug("write_mdata_partition() method not defined\n");
-		return -ENOSYS;
-	}
-
-	return ops->write_mdata_partition(dev, mdata, part_num);
-}
-
-/**
- * fwu_mdata_check() - Check if the FWU metadata is valid
- * @dev: FWU metadata device
- *
- * Validate both copies of the FWU metadata. If one of the copies
- * has gone bad, restore it from the other copy.
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_mdata_check(struct udevice *dev)
-{
-	const struct fwu_mdata_ops *ops = device_get_ops(dev);
-
-	if (!ops->check_mdata) {
-		log_debug("check_mdata() method not defined\n");
-		return -ENOSYS;
-	}
-
-	return ops->check_mdata(dev);
-}
-
-/**
- * fwu_get_mdata() - Get a FWU metadata copy
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- *
- * Get a valid copy of the FWU metadata.
- *
- * Note: This function is to be called first when modifying any fields
- * in the metadata. The sequence of calls to modify any field in the
- * metadata would  be 1) fwu_get_mdata 2) Modify metadata, followed by
- * 3) fwu_update_mdata
+ * fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata()
  *
  * Return: 0 if OK, -ve on error
- *
  */
-int fwu_get_mdata(struct udevice *dev, struct fwu_mdata *mdata)
+int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
 {
 	const struct fwu_mdata_ops *ops = device_get_ops(dev);
 
-	if (!ops->get_mdata) {
-		log_debug("get_mdata() method not defined\n");
+	if (!ops->read_mdata) {
+		log_debug("read_mdata() method not defined\n");
 		return -ENOSYS;
 	}
 
-	return ops->get_mdata(dev, mdata);
+	return ops->read_mdata(dev, mdata, primary);
 }
 
 /**
- * fwu_update_mdata() - Update the FWU metadata
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- *
- * Update the FWU metadata structure by writing to the
- * FWU metadata partitions.
- *
- * Note: This function is not to be called directly to update the
- * metadata fields. The sequence of function calls should be
- * 1) fwu_get_mdata() 2) Modify the medata fields 3) fwu_update_mdata()
- *
- * The sequence of updating the partitions should be, update the
- * primary metadata partition (first partition encountered), followed
- * by updating the secondary partition. With this update sequence, in
- * the rare scenario that the two metadata partitions are valid but do
- * not match, maybe due to power outage at the time of updating the
- * metadata copies, the secondary partition can be updated from the
- * primary.
+ * fwu_write_mdata() - Wrapper around fwu_mdata_ops.write_mdata()
  *
  * Return: 0 if OK, -ve on error
- *
  */
-int fwu_update_mdata(struct udevice *dev, struct fwu_mdata *mdata)
+int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
 {
-	void *buf;
 	const struct fwu_mdata_ops *ops = device_get_ops(dev);
 
-	if (!ops->update_mdata) {
-		log_debug("get_mdata() method not defined\n");
+	if (!ops->write_mdata) {
+		log_debug("write_mdata() method not defined\n");
 		return -ENOSYS;
 	}
 
-	/*
-	 * Calculate the crc32 for the updated FWU metadata
-	 * and put the updated value in the FWU metadata crc32
-	 * field
-	 */
-	buf = &mdata->version;
-	mdata->crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32));
-
-	return ops->update_mdata(dev, mdata);
+	return ops->write_mdata(dev, mdata, primary);
 }
 
 UCLASS_DRIVER(fwu_mdata) = {
diff --git a/drivers/fwu-mdata/gpt_blk.c b/drivers/fwu-mdata/gpt_blk.c
index d35ce49c5c..c7284916c4 100644
--- a/drivers/fwu-mdata/gpt_blk.c
+++ b/drivers/fwu-mdata/gpt_blk.c
@@ -24,38 +24,40 @@ enum {
 	MDATA_WRITE,
 };
 
-static int gpt_get_mdata_partitions(struct blk_desc *desc,
-				    uint mdata_parts[2])
+static uint g_mdata_part[2]; /* = {0, 0} to check against uninit parts */
+
+static int gpt_get_mdata_partitions(struct blk_desc *desc)
 {
-	int i, ret;
+	int i;
 	u32 nparts;
 	efi_guid_t part_type_guid;
 	struct disk_partition info;
 	const efi_guid_t fwu_mdata_guid = FWU_MDATA_GUID;
 
+	/* if primary and secondary partitions already found */
+	if (g_mdata_part[0] && g_mdata_part[1])
+		return 0;
+
 	nparts = 0;
-	for (i = 1; i < MAX_SEARCH_PARTITIONS; i++) {
+	for (i = 1; i < MAX_SEARCH_PARTITIONS && nparts < 2; i++) {
 		if (part_get_info(desc, i, &info))
 			continue;
 		uuid_str_to_bin(info.type_guid, part_type_guid.b,
 				UUID_STR_FORMAT_GUID);
 
-		if (!guidcmp(&fwu_mdata_guid, &part_type_guid)) {
-			if (nparts < 2)
-				mdata_parts[nparts] = i;
-			++nparts;
-		}
+		if (!guidcmp(&fwu_mdata_guid, &part_type_guid))
+			g_mdata_part[nparts++] = i;
 	}
 
 	if (nparts != 2) {
 		log_debug("Expect two copies of the FWU metadata instead of %d\n",
 			  nparts);
-		ret = -EINVAL;
-	} else {
-		ret = 0;
+		g_mdata_part[0] = 0;
+		g_mdata_part[1] = 0;
+		return -EINVAL;
 	}
 
-	return ret;
+	return 0;
 }
 
 static int gpt_get_mdata_disk_part(struct blk_desc *desc,
@@ -123,112 +125,6 @@ static int gpt_read_write_mdata(struct blk_desc *desc,
 	return 0;
 }
 
-static int fwu_gpt_update_mdata(struct udevice *dev, struct fwu_mdata *mdata)
-{
-	int ret;
-	struct blk_desc *desc;
-	uint mdata_parts[2];
-	struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
-
-	desc = dev_get_uclass_plat(priv->blk_dev);
-
-	ret = gpt_get_mdata_partitions(desc, mdata_parts);
-	if (ret < 0) {
-		log_debug("Error getting the FWU metadata partitions\n");
-		return -ENOENT;
-	}
-
-	/* First write the primary partition */
-	ret = gpt_read_write_mdata(desc, mdata, MDATA_WRITE, mdata_parts[0]);
-	if (ret < 0) {
-		log_debug("Updating primary FWU metadata partition failed\n");
-		return ret;
-	}
-
-	/* And now the replica */
-	ret = gpt_read_write_mdata(desc, mdata, MDATA_WRITE, mdata_parts[1]);
-	if (ret < 0) {
-		log_debug("Updating secondary FWU metadata partition failed\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int gpt_get_mdata(struct blk_desc *desc, struct fwu_mdata *mdata)
-{
-	int ret;
-	uint mdata_parts[2];
-
-	ret = gpt_get_mdata_partitions(desc, mdata_parts);
-
-	if (ret < 0) {
-		log_debug("Error getting the FWU metadata partitions\n");
-		return -ENOENT;
-	}
-
-	ret = gpt_read_write_mdata(desc, mdata, MDATA_READ, mdata_parts[0]);
-	if (ret < 0) {
-		log_debug("Failed to read the FWU metadata from the device\n");
-		return -EIO;
-	}
-
-	ret = fwu_verify_mdata(mdata, 1);
-	if (!ret)
-		return 0;
-
-	/*
-	 * Verification of the primary FWU metadata copy failed.
-	 * Try to read the replica.
-	 */
-	memset(mdata, '\0', sizeof(struct fwu_mdata));
-	ret = gpt_read_write_mdata(desc, mdata, MDATA_READ, mdata_parts[1]);
-	if (ret < 0) {
-		log_debug("Failed to read the FWU metadata from the device\n");
-		return -EIO;
-	}
-
-	ret = fwu_verify_mdata(mdata, 0);
-	if (!ret)
-		return 0;
-
-	/* Both the FWU metadata copies are corrupted. */
-	return -EIO;
-}
-
-static int fwu_gpt_get_mdata(struct udevice *dev, struct fwu_mdata *mdata)
-{
-	struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
-
-	return gpt_get_mdata(dev_get_uclass_plat(priv->blk_dev), mdata);
-}
-
-static int fwu_gpt_get_mdata_partitions(struct udevice *dev, uint *mdata_parts)
-{
-	struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
-
-	return gpt_get_mdata_partitions(dev_get_uclass_plat(priv->blk_dev),
-					mdata_parts);
-}
-
-static int fwu_gpt_read_mdata_partition(struct udevice *dev,
-					struct fwu_mdata *mdata, uint part_num)
-{
-	struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
-
-	return gpt_read_write_mdata(dev_get_uclass_plat(priv->blk_dev),
-				    mdata, MDATA_READ, part_num);
-}
-
-static int fwu_gpt_write_mdata_partition(struct udevice *dev,
-					struct fwu_mdata *mdata, uint part_num)
-{
-	struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
-
-	return gpt_read_write_mdata(dev_get_uclass_plat(priv->blk_dev),
-				    mdata, MDATA_WRITE, part_num);
-}
-
 static int fwu_get_mdata_device(struct udevice *dev, struct udevice **mdata_dev)
 {
 	u32 phandle;
@@ -267,12 +163,43 @@ static int fwu_mdata_gpt_blk_probe(struct udevice *dev)
 	return 0;
 }
 
+static int fwu_gpt_read_mdata(struct udevice *dev, struct fwu_mdata *mdata,
+			      bool primary)
+{
+	struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
+	struct blk_desc *desc = dev_get_uclass_plat(priv->blk_dev);
+	int ret;
+
+	ret = gpt_get_mdata_partitions(desc);
+	if (ret < 0) {
+		log_debug("Error getting the FWU metadata partitions\n");
+		return -ENOENT;
+	}
+
+	return gpt_read_write_mdata(desc, mdata, MDATA_READ,
+				    primary ? g_mdata_part[0] : g_mdata_part[1]);
+}
+
+static int fwu_gpt_write_mdata(struct udevice *dev, struct fwu_mdata *mdata,
+			       bool primary)
+{
+	struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
+	struct blk_desc *desc = dev_get_uclass_plat(priv->blk_dev);
+	int ret;
+
+	ret = gpt_get_mdata_partitions(desc);
+	if (ret < 0) {
+		log_debug("Error getting the FWU metadata partitions\n");
+		return -ENOENT;
+	}
+
+	return gpt_read_write_mdata(desc, mdata, MDATA_WRITE,
+				    primary ? g_mdata_part[0] : g_mdata_part[1]);
+}
+
 static const struct fwu_mdata_ops fwu_gpt_blk_ops = {
-	.get_mdata = fwu_gpt_get_mdata,
-	.update_mdata = fwu_gpt_update_mdata,
-	.get_mdata_part_num = fwu_gpt_get_mdata_partitions,
-	.read_mdata_partition = fwu_gpt_read_mdata_partition,
-	.write_mdata_partition = fwu_gpt_write_mdata_partition,
+	.read_mdata = fwu_gpt_read_mdata,
+	.write_mdata = fwu_gpt_write_mdata,
 };
 
 static const struct udevice_id fwu_mdata_ids[] = {
diff --git a/drivers/fwu-mdata/raw_mtd.c b/drivers/fwu-mdata/raw_mtd.c
new file mode 100644
index 0000000000..17e4517973
--- /dev/null
+++ b/drivers/fwu-mdata/raw_mtd.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#define LOG_CATEGORY UCLASS_FWU_MDATA
+
+#include <fwu.h>
+#include <fwu_mdata.h>
+#include <memalign.h>
+
+#include <linux/errno.h>
+#include <linux/types.h>
+
+/* Internal helper structure to move data around */
+struct fwu_mdata_mtd_priv {
+	struct mtd_info *mtd;
+	char pri_label[50];
+	char sec_label[50];
+	u32 pri_offset;
+	u32 sec_offset;
+};
+
+enum fwu_mtd_op {
+	FWU_MTD_READ,
+	FWU_MTD_WRITE,
+};
+
+extern struct fwu_mtd_image_info fwu_mtd_images[];
+
+static bool mtd_is_aligned_with_block_size(struct mtd_info *mtd, u64 size)
+{
+	return !do_div(size, mtd->erasesize);
+}
+
+static int mtd_io_data(struct mtd_info *mtd, u32 offs, u32 size, void *data,
+		       enum fwu_mtd_op op)
+{
+	struct mtd_oob_ops io_op = {};
+	u64 lock_len;
+	size_t len;
+	void *buf;
+	int ret;
+
+	if (!mtd_is_aligned_with_block_size(mtd, offs)) {
+		log_err("Offset unaligned with a block (0x%x)\n", mtd->erasesize);
+		return -EINVAL;
+	}
+
+	/* This will expand erase size to align with the block size */
+	lock_len = round_up(size, mtd->erasesize);
+
+	ret = mtd_unlock(mtd, offs, lock_len);
+	if (ret && ret != -EOPNOTSUPP)
+		return ret;
+
+	if (op == FWU_MTD_WRITE) {
+		struct erase_info erase_op = {};
+
+		erase_op.mtd = mtd;
+		erase_op.addr = offs;
+		erase_op.len = lock_len;
+		erase_op.scrub = 0;
+
+		ret = mtd_erase(mtd, &erase_op);
+		if (ret)
+			goto lock;
+	}
+
+	/* Also, expand the write size to align with the write size */
+	len = round_up(size, mtd->writesize);
+
+	buf = memalign(ARCH_DMA_MINALIGN, len);
+	if (!buf) {
+		ret = -ENOMEM;
+		goto lock;
+	}
+	memset(buf, 0xff, len);
+
+	io_op.mode = MTD_OPS_AUTO_OOB;
+	io_op.len = len;
+	io_op.datbuf = buf;
+
+	if (op == FWU_MTD_WRITE) {
+		memcpy(buf, data, size);
+		ret = mtd_write_oob(mtd, offs, &io_op);
+	} else {
+		ret = mtd_read_oob(mtd, offs, &io_op);
+		if (!ret)
+			memcpy(data, buf, size);
+	}
+	free(buf);
+
+lock:
+	mtd_lock(mtd, offs, lock_len);
+
+	return ret;
+}
+
+static int fwu_mtd_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
+{
+	struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
+	struct mtd_info *mtd = mtd_priv->mtd;
+	u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset;
+
+	return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_READ);
+}
+
+static int fwu_mtd_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
+{
+	struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
+	struct mtd_info *mtd = mtd_priv->mtd;
+	u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset;
+
+	return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_WRITE);
+}
+
+static int flash_partition_offset(struct udevice *dev, const char *part_name, fdt_addr_t *offset)
+{
+	ofnode node, parts_node;
+	fdt_addr_t size = 0;
+
+	parts_node = ofnode_by_compatible(dev_ofnode(dev), "fixed-partitions");
+	node = ofnode_by_prop_value(parts_node, "label", part_name, strlen(part_name) + 1);
+	if (!ofnode_valid(node)) {
+		log_err("Warning: Failed to find partition by label <%s>\n", part_name);
+		return -ENOENT;
+	}
+
+	*offset = ofnode_get_addr_size_index_notrans(node, 0, &size);
+
+	return (int)size;
+}
+
+static int fwu_mdata_mtd_of_to_plat(struct udevice *dev)
+{
+	struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
+	const fdt32_t *phandle_p = NULL;
+	struct udevice *mtd_dev;
+	struct mtd_info *mtd;
+	const char *label;
+	fdt_addr_t offset;
+	int ret, size;
+	u32 phandle;
+	ofnode bank;
+	int off_img;
+
+	/* Find the FWU mdata storage device */
+	phandle_p = ofnode_get_property(dev_ofnode(dev),
+					"fwu-mdata-store", &size);
+	if (!phandle_p) {
+		log_err("FWU meta data store not defined in device-tree\n");
+		return -ENOENT;
+	}
+
+	phandle = fdt32_to_cpu(*phandle_p);
+
+	ret = device_get_global_by_ofnode(ofnode_get_by_phandle(phandle),
+					  &mtd_dev);
+	if (ret) {
+		log_err("FWU: failed to get mtd device\n");
+		return ret;
+	}
+
+	mtd_probe_devices();
+
+	mtd_for_each_device(mtd) {
+		if (mtd->dev == mtd_dev) {
+			mtd_priv->mtd = mtd;
+			log_debug("Found the FWU mdata mtd device %s\n", mtd->name);
+			break;
+		}
+	}
+	if (!mtd_priv->mtd) {
+		log_err("Failed to find mtd device by fwu-mdata-store\n");
+		return -ENODEV;
+	}
+
+	/* Get the offset of primary and secondary mdata */
+	ret = ofnode_read_string_index(dev_ofnode(dev), "mdata-parts", 0, &label);
+	if (ret)
+		return ret;
+	strncpy(mtd_priv->pri_label, label, 50);
+
+	ret = flash_partition_offset(mtd_dev, mtd_priv->pri_label, &offset);
+	if (ret <= 0)
+		return ret;
+	mtd_priv->pri_offset = offset;
+
+	ret = ofnode_read_string_index(dev_ofnode(dev), "mdata-parts", 1, &label);
+	if (ret)
+		return ret;
+	strncpy(mtd_priv->sec_label, label, 50);
+
+	ret = flash_partition_offset(mtd_dev, mtd_priv->sec_label, &offset);
+	if (ret <= 0)
+		return ret;
+	mtd_priv->sec_offset = offset;
+
+	off_img = 0;
+
+	ofnode_for_each_subnode(bank, dev_ofnode(dev)) {
+		int bank_num, bank_offset, bank_size;
+		const char *bank_name;
+		ofnode image;
+
+		ofnode_read_u32(bank, "id", &bank_num);
+		bank_name = ofnode_read_string(bank, "label");
+		bank_size = flash_partition_offset(mtd_dev, bank_name, &offset);
+		if (bank_size <= 0)
+			return bank_size;
+		bank_offset = offset;
+		log_debug("Bank%d: %s [0x%x - 0x%x]\n",
+			  bank_num, bank_name, bank_offset, bank_offset + bank_size);
+
+		ofnode_for_each_subnode(image, bank) {
+			int image_num, image_offset, image_size;
+			const char *uuid;
+
+			if (off_img == CONFIG_FWU_NUM_BANKS *
+						CONFIG_FWU_NUM_IMAGES_PER_BANK) {
+				log_err("DT provides more images than configured!\n");
+				break;
+			}
+
+			uuid = ofnode_read_string(image, "uuid");
+			ofnode_read_u32(image, "id", &image_num);
+			ofnode_read_u32(image, "offset", &image_offset);
+			ofnode_read_u32(image, "size", &image_size);
+
+			fwu_mtd_images[off_img].start = bank_offset + image_offset;
+			fwu_mtd_images[off_img].size = image_size;
+			fwu_mtd_images[off_img].bank_num = bank_num;
+			fwu_mtd_images[off_img].image_num = image_num;
+			strcpy(fwu_mtd_images[off_img].uuidbuf, uuid);
+			log_debug("\tImage%d: %s @0x%x\n\n",
+				  image_num, uuid, bank_offset + image_offset);
+			off_img++;
+		}
+	}
+
+	return 0;
+}
+
+static int fwu_mdata_mtd_probe(struct udevice *dev)
+{
+	/* Ensure the metadata can be read. */
+	return fwu_get_mdata(NULL);
+}
+
+static struct fwu_mdata_ops fwu_mtd_ops = {
+	.read_mdata = fwu_mtd_read_mdata,
+	.write_mdata = fwu_mtd_write_mdata,
+};
+
+static const struct udevice_id fwu_mdata_ids[] = {
+	{ .compatible = "u-boot,fwu-mdata-mtd" },
+	{ }
+};
+
+U_BOOT_DRIVER(fwu_mdata_mtd) = {
+	.name		= "fwu-mdata-mtd",
+	.id		= UCLASS_FWU_MDATA,
+	.of_match	= fwu_mdata_ids,
+	.ops		= &fwu_mtd_ops,
+	.probe		= fwu_mdata_mtd_probe,
+	.of_to_plat	= fwu_mdata_mtd_of_to_plat,
+	.priv_auto	= sizeof(struct fwu_mdata_mtd_priv),
+};
diff --git a/drivers/gpio/gpio-fxl6408.c b/drivers/gpio/gpio-fxl6408.c
index 902da050fb..ca7aa14eeb 100644
--- a/drivers/gpio/gpio-fxl6408.c
+++ b/drivers/gpio/gpio-fxl6408.c
@@ -27,7 +27,7 @@
  *   https://patchwork.kernel.org/patch/9148419/
  * - the Toradex version by Max Krummenacher <max.krummenacher@toradex.com>:
  *   http://git.toradex.com/cgit/linux-toradex.git/tree/drivers/gpio/gpio-fxl6408.c?h=toradex_5.4-2.3.x-imx
- * - the U-boot PCA953x driver by Peng Fan <van.freenix@gmail.com>:
+ * - the U-Boot PCA953x driver by Peng Fan <van.freenix@gmail.com>:
  *   drivers/gpio/pca953x_gpio.c
  *
  * TODO:
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 9ffb4a5625..d6cfbd231a 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -130,20 +130,9 @@ static int rcar_gpio_get_function(struct udevice *dev, unsigned offset)
 		return GPIOF_INPUT;
 }
 
-static int rcar_gpio_request(struct udevice *dev, unsigned offset,
-			     const char *label)
-{
-	return pinctrl_gpio_request(dev, offset, label);
-}
-
-static int rcar_gpio_free(struct udevice *dev, unsigned offset)
-{
-	return pinctrl_gpio_free(dev, offset);
-}
-
 static const struct dm_gpio_ops rcar_gpio_ops = {
-	.request		= rcar_gpio_request,
-	.rfree			= rcar_gpio_free,
+	.request		= pinctrl_gpio_request,
+	.rfree			= pinctrl_gpio_free,
 	.direction_input	= rcar_gpio_direction_input,
 	.direction_output	= rcar_gpio_direction_output,
 	.get_value		= rcar_gpio_get_value,
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 712119c341..31027f3d99 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -1474,7 +1474,7 @@ static int gpio_post_bind(struct udevice *dev)
 	}
 #endif
 
-	if (CONFIG_IS_ENABLED(GPIO_HOG)) {
+	if (CONFIG_IS_ENABLED(GPIO_HOG) && dev_has_ofnode(dev)) {
 		struct udevice *child;
 		ofnode node;
 
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 63a07b9592..2ed0d0bea9 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -26,6 +26,8 @@
  * reserved or subject to arcane restrictions.
  */
 
+#define LOG_CATEGORY	UCLASS_GPIO
+
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
@@ -155,8 +157,7 @@ static int ich6_gpio_request(struct udevice *dev, unsigned offset,
 	 */
 	tmplong = inl(bank->use_sel);
 	if (!(tmplong & (1UL << offset))) {
-		debug("%s: gpio %d is reserved for internal use\n", __func__,
-		      offset);
+		log_debug("gpio %d is reserved for internal use\n", offset);
 		return -EPERM;
 	}
 
diff --git a/drivers/gpio/npcm_gpio.c b/drivers/gpio/npcm_gpio.c
index 8afd57fa8e..98e5dc79c1 100644
--- a/drivers/gpio/npcm_gpio.c
+++ b/drivers/gpio/npcm_gpio.c
@@ -37,14 +37,14 @@ static int npcm_gpio_direction_output(struct udevice *dev, unsigned int offset,
 {
 	struct npcm_gpio_priv *priv = dev_get_priv(dev);
 
-	clrbits_le32(priv->base + GPIO_IEM, BIT(offset));
-	writel(BIT(offset), priv->base + GPIO_OES);
-
 	if (value)
 		setbits_le32(priv->base + GPIO_DOUT, BIT(offset));
 	else
 		clrbits_le32(priv->base + GPIO_DOUT, BIT(offset));
 
+	clrbits_le32(priv->base + GPIO_IEM, BIT(offset));
+	writel(BIT(offset), priv->base + GPIO_OES);
+
 	return 0;
 }
 
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 05b14d2451..4c76fd7e41 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -231,6 +231,15 @@ config SYS_I2C_DW
 	  controller is used in various SoCs, e.g. the ST SPEAr, Altera
 	  SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
 
+config SYS_I2C_DW_PCI
+	bool "Designware PCI I2C Controller"
+	depends on SYS_I2C_DW && PCI && ACPIGEN
+	default y
+	help
+	  Say yes here to select the Designware PCI I2C Host Controller.
+	  This PCI I2C controller is the base on Desigware I2C host
+	  controller.
+
 config SYS_I2C_AST2600
     bool "AST2600 I2C Controller"
     depends on DM_I2C && ARCH_ASPEED
@@ -744,7 +753,6 @@ config SYS_I2C_SPEED
 config SYS_I2C_BUS_MAX
 	int "Max I2C busses"
 	depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
-	default 2 if TI816X
 	default 3 if OMAP34XX || AM33XX || AM43XX
 	default 4 if ARCH_SOCFPGA || OMAP44XX
 	default 5 if OMAP54XX
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 99545df2e5..d5b85f398d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -18,9 +18,7 @@ obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
 obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o
 obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
 obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
-ifdef CONFIG_PCI
-obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o
-endif
+obj-$(CONFIG_SYS_I2C_DW_PCI) += designware_i2c_pci.o
 obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
 obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
 obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c
index 4ed9e9e7cd..c1fc290bd2 100644
--- a/drivers/i2c/i2c-gpio.c
+++ b/drivers/i2c/i2c-gpio.c
@@ -339,7 +339,7 @@ static int i2c_gpio_of_to_plat(struct udevice *dev)
 	/* "gpios" is deprecated and replaced by "sda-gpios" + "scl-gpios". */
 	ret = gpio_request_list_by_name(dev, "gpios", bus->gpios,
 					ARRAY_SIZE(bus->gpios), 0);
-	if (ret == -ENOENT) {
+	if (ret == 0) {
 		ret = gpio_request_by_name(dev, "sda-gpios", 0,
 					   &bus->gpios[PIN_SDA], 0);
 		if (ret < 0)
diff --git a/drivers/i2c/mtk_i2c.c b/drivers/i2c/mtk_i2c.c
index 5528bcd7cc..2f331d3216 100644
--- a/drivers/i2c/mtk_i2c.c
+++ b/drivers/i2c/mtk_i2c.c
@@ -183,9 +183,36 @@ static const uint mt_i2c_regs_v2[] = {
 	[REG_DCM_EN] = 0xf88,
 };
 
+static const uint mt_i2c_regs_v3[] = {
+	[REG_PORT] = 0x0,
+	[REG_INTR_MASK] = 0x8,
+	[REG_INTR_STAT] = 0xc,
+	[REG_CONTROL] = 0x10,
+	[REG_TRANSFER_LEN] = 0x14,
+	[REG_TRANSAC_LEN] = 0x18,
+	[REG_DELAY_LEN] = 0x1c,
+	[REG_TIMING] = 0x20,
+	[REG_START] = 0x24,
+	[REG_EXT_CONF] = 0x28,
+	[REG_LTIMING] = 0x2c,
+	[REG_HS] = 0x30,
+	[REG_IO_CONFIG] = 0x34,
+	[REG_FIFO_ADDR_CLR] = 0x38,
+	[REG_TRANSFER_LEN_AUX] = 0x44,
+	[REG_CLOCK_DIV] = 0x48,
+	[REG_SOFTRESET] = 0x50,
+	[REG_SLAVE_ADDR] = 0x94,
+	[REG_DEBUGSTAT] = 0xe4,
+	[REG_DEBUGCTRL] = 0xe8,
+	[REG_FIFO_STAT] = 0xf4,
+	[REG_FIFO_THRESH] = 0xf8,
+	[REG_DCM_EN] = 0xf88,
+};
+
 struct mtk_i2c_soc_data {
 	const uint *regs;
 	uint dma_sync: 1;
+	uint ltiming_adjust: 1;
 };
 
 struct mtk_i2c_priv {
@@ -401,6 +428,10 @@ static int mtk_i2c_set_speed(struct udevice *dev, uint speed)
 				(sample_cnt << HS_SAMPLE_OFFSET) |
 				(step_cnt << HS_STEP_OFFSET);
 		i2c_writel(priv, REG_HS, high_speed_reg);
+		if (priv->soc_data->ltiming_adjust) {
+			timing_reg = (sample_cnt << 12) | (step_cnt << 9);
+			i2c_writel(priv, REG_LTIMING, timing_reg);
+		}
 	} else {
 		ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
 					      &step_cnt, &sample_cnt);
@@ -412,7 +443,12 @@ static int mtk_i2c_set_speed(struct udevice *dev, uint speed)
 		high_speed_reg = I2C_TIME_CLR_VALUE;
 		i2c_writel(priv, REG_TIMING, timing_reg);
 		i2c_writel(priv, REG_HS, high_speed_reg);
+		if (priv->soc_data->ltiming_adjust) {
+			timing_reg = (sample_cnt << 6) | step_cnt;
+			i2c_writel(priv, REG_LTIMING, timing_reg);
+		}
 	}
+
 exit:
 	if (mtk_i2c_clk_disable(priv))
 		return log_msg_ret("set_speed disable clk", -1);
@@ -725,7 +761,6 @@ static int mtk_i2c_probe(struct udevice *dev)
 		return log_msg_ret("probe enable clk", -1);
 
 	mtk_i2c_init_hw(priv);
-
 	if (mtk_i2c_clk_disable(priv))
 		return log_msg_ret("probe disable clk", -1);
 
@@ -750,31 +785,37 @@ static int mtk_i2c_deblock(struct udevice *dev)
 static const struct mtk_i2c_soc_data mt76xx_soc_data = {
 	.regs = mt_i2c_regs_v1,
 	.dma_sync = 0,
+	.ltiming_adjust = 0,
 };
 
 static const struct mtk_i2c_soc_data mt7981_soc_data = {
-	.regs = mt_i2c_regs_v1,
+	.regs = mt_i2c_regs_v3,
 	.dma_sync = 1,
+	.ltiming_adjust = 1,
 };
 
 static const struct mtk_i2c_soc_data mt7986_soc_data = {
 	.regs = mt_i2c_regs_v1,
 	.dma_sync = 1,
+	.ltiming_adjust = 0,
 };
 
 static const struct mtk_i2c_soc_data mt8183_soc_data = {
 	.regs = mt_i2c_regs_v2,
 	.dma_sync = 1,
+	.ltiming_adjust = 0,
 };
 
 static const struct mtk_i2c_soc_data mt8518_soc_data = {
 	.regs = mt_i2c_regs_v1,
 	.dma_sync = 0,
+	.ltiming_adjust = 0,
 };
 
 static const struct mtk_i2c_soc_data mt8512_soc_data = {
 	.regs = mt_i2c_regs_v1,
 	.dma_sync = 1,
+	.ltiming_adjust = 0,
 };
 
 static const struct dm_i2c_ops mtk_i2c_ops = {
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 93bbc6916e..14cdb0f663 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -142,6 +142,8 @@ enum mvtwsi_ctrl_register_fields {
  * code.
  */
 enum mvstwsi_status_values {
+	/* Protocol violation on bus; this is a terminal state */
+	MVTWSI_BUS_ERROR		= 0x00,
 	/* START condition transmitted */
 	MVTWSI_STATUS_START		= 0x08,
 	/* Repeated START condition transmitted */
@@ -526,6 +528,36 @@ static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
 }
 
 /*
+ * __twsi_i2c_reinit() - Reset and reinitialize the I2C controller.
+ *
+ * This function should be called to get the MVTWSI controller out of the
+ * "bus error" state. It saves and restores the baud and address registers.
+ *
+ * @twsi:	The MVTWSI register structure to use.
+ * @tick:	The duration of a clock cycle at the current I2C speed.
+ */
+static void __twsi_i2c_reinit(struct mvtwsi_registers *twsi, uint tick)
+{
+	uint baud;
+	uint slaveadd;
+
+	/* Save baud, address registers */
+	baud = readl(&twsi->baudrate);
+	slaveadd = readl(&twsi->slave_address);
+
+	/* Reset controller */
+	twsi_reset(twsi);
+
+	/* Restore baud, address registers */
+	writel(baud, &twsi->baudrate);
+	writel(slaveadd, &twsi->slave_address);
+	writel(0, &twsi->xtnd_slave_addr);
+
+	/* Assert STOP, but don't care for the result */
+	(void) twsi_stop(twsi, tick);
+}
+
+/*
  * i2c_begin() - Start a I2C transaction.
  *
  * Begin a I2C transaction with a given expected start status and chip address.
@@ -621,6 +653,11 @@ static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
 	int stop_status;
 	int expected_start = MVTWSI_STATUS_START;
 
+	/* Check for (and clear) a bus error from a previous failed transaction
+	 * or another master on the same bus */
+	if (readl(&twsi->status) == MVTWSI_BUS_ERROR)
+		__twsi_i2c_reinit(twsi, tick);
+
 	if (alen > 0) {
 		/* Begin i2c write to send the address bytes */
 		status = i2c_begin(twsi, expected_start, (chip << 1), tick);
@@ -668,6 +705,11 @@ static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
 {
 	int status, stop_status;
 
+	/* Check for (and clear) a bus error from a previous failed transaction
+	 * or another master on the same bus */
+	if (readl(&twsi->status) == MVTWSI_BUS_ERROR)
+		__twsi_i2c_reinit(twsi, tick);
+
 	/* Begin i2c write to send first the address bytes, then the
 	 * data bytes */
 	status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick);
diff --git a/drivers/led/led_bcm6753.c b/drivers/led/led_bcm6753.c
index 88b650cbfc..2466d93011 100644
--- a/drivers/led/led_bcm6753.c
+++ b/drivers/led/led_bcm6753.c
@@ -174,57 +174,65 @@ static const struct led_ops bcm6753_led_ops = {
 
 static int bcm6753_led_probe(struct udevice *dev)
 {
-	struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
-
-	/* Top-level LED node */
-	if (!uc_plat->label) {
-		void __iomem *regs;
-		u32 set_bits = 0;
-
-		regs = dev_remap_addr(dev);
-		if (!regs)
-			return -EINVAL;
-
-		if (dev_read_bool(dev, "brcm,serial-led-msb-first"))
-			set_bits |= CLED_CTRL_SERIAL_LED_MSB_FIRST;
-		if (dev_read_bool(dev, "brcm,serial-led-en-pol"))
-			set_bits |= CLED_CTRL_SERIAL_LED_EN_POL;
-		if (dev_read_bool(dev, "brcm,serial-led-clk-pol"))
-			set_bits |= CLED_CTRL_SERIAL_LED_CLK_POL;
-		if (dev_read_bool(dev, "brcm,serial-led-data-ppol"))
-			set_bits |= CLED_CTRL_SERIAL_LED_DATA_PPOL;
-
-		clrsetbits_32(regs + CLED_CTRL_REG, CLED_CTRL_MASK, set_bits);
-	} else {
-		struct bcm6753_led_priv *priv = dev_get_priv(dev);
-		void __iomem *regs;
-		unsigned int pin;
-
-		regs = dev_remap_addr(dev_get_parent(dev));
-		if (!regs)
-			return -EINVAL;
-
-		pin = dev_read_u32_default(dev, "reg", LEDS_MAX);
-		if (pin >= LEDS_MAX)
-			return -EINVAL;
-
-		priv->regs = regs;
-		priv->pin = pin;
-
-		/* this led is managed by software */
-		clrbits_32(regs + CLED_HW_LED_EN_REG, 1 << pin);
-
-		/* configure the polarity */
-		if (dev_read_bool(dev, "active-low"))
-			clrbits_32(regs + CLED_PLED_OP_PPOL_REG, 1 << pin);
-		else
-			setbits_32(regs + CLED_PLED_OP_PPOL_REG, 1 << pin);
-	}
+	struct bcm6753_led_priv *priv = dev_get_priv(dev);
+	void __iomem *regs;
+	unsigned int pin;
+
+	regs = dev_remap_addr(dev_get_parent(dev));
+	if (!regs)
+		return -EINVAL;
+
+	pin = dev_read_u32_default(dev, "reg", LEDS_MAX);
+	if (pin >= LEDS_MAX)
+		return -EINVAL;
+
+	priv->regs = regs;
+	priv->pin = pin;
+
+	/* this led is managed by software */
+	clrbits_32(regs + CLED_HW_LED_EN_REG, 1 << pin);
+
+	/* configure the polarity */
+	if (dev_read_bool(dev, "active-low"))
+		clrbits_32(regs + CLED_PLED_OP_PPOL_REG, 1 << pin);
+	else
+		setbits_32(regs + CLED_PLED_OP_PPOL_REG, 1 << pin);
 
 	return 0;
 }
 
-static int bcm6753_led_bind(struct udevice *parent)
+U_BOOT_DRIVER(bcm6753_led) = {
+	.name = "bcm6753-led",
+	.id = UCLASS_LED,
+	.probe = bcm6753_led_probe,
+	.priv_auto = sizeof(struct bcm6753_led_priv),
+	.ops = &bcm6753_led_ops,
+};
+
+static int bcm6753_led_wrap_probe(struct udevice *dev)
+{
+	void __iomem *regs;
+	u32 set_bits = 0;
+
+	regs = dev_remap_addr(dev);
+	if (!regs)
+		return -EINVAL;
+
+	if (dev_read_bool(dev, "brcm,serial-led-msb-first"))
+		set_bits |= CLED_CTRL_SERIAL_LED_MSB_FIRST;
+	if (dev_read_bool(dev, "brcm,serial-led-en-pol"))
+		set_bits |= CLED_CTRL_SERIAL_LED_EN_POL;
+	if (dev_read_bool(dev, "brcm,serial-led-clk-pol"))
+		set_bits |= CLED_CTRL_SERIAL_LED_CLK_POL;
+	if (dev_read_bool(dev, "brcm,serial-led-data-ppol"))
+		set_bits |= CLED_CTRL_SERIAL_LED_DATA_PPOL;
+
+	clrsetbits_32(regs + CLED_CTRL_REG, CLED_CTRL_MASK, set_bits);
+
+	return 0;
+}
+
+static int bcm6753_led_wrap_bind(struct udevice *parent)
 {
 	ofnode node;
 
@@ -247,12 +255,10 @@ static const struct udevice_id bcm6753_led_ids[] = {
 	{ /* sentinel */ }
 };
 
-U_BOOT_DRIVER(bcm6753_led) = {
-	.name = "bcm6753-led",
-	.id = UCLASS_LED,
+U_BOOT_DRIVER(bcm6753_led_wrap) = {
+	.name	= "bcm6753_led_wrap",
+	.id	= UCLASS_NOP,
 	.of_match = bcm6753_led_ids,
-	.bind = bcm6753_led_bind,
-	.probe = bcm6753_led_probe,
-	.priv_auto = sizeof(struct bcm6753_led_priv),
-	.ops = &bcm6753_led_ops,
+	.probe = bcm6753_led_wrap_probe,
+	.bind = bcm6753_led_wrap_bind,
 };
diff --git a/drivers/led/led_bcm6858.c b/drivers/led/led_bcm6858.c
index 6b3698674b..397dc0d869 100644
--- a/drivers/led/led_bcm6858.c
+++ b/drivers/led/led_bcm6858.c
@@ -180,63 +180,71 @@ static const struct led_ops bcm6858_led_ops = {
 
 static int bcm6858_led_probe(struct udevice *dev)
 {
-	struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
-
-	/* Top-level LED node */
-	if (!uc_plat->label) {
-		void __iomem *regs;
-		u32 set_bits = 0;
-
-		regs = dev_remap_addr(dev);
-		if (!regs)
-			return -EINVAL;
-
-		if (dev_read_bool(dev, "brcm,serial-led-msb-first"))
-			set_bits |= LED_CTRL_SERIAL_LED_MSB_FIRST;
-		if (dev_read_bool(dev, "brcm,serial-led-en-pol"))
-			set_bits |= LED_CTRL_SERIAL_LED_EN_POL;
-		if (dev_read_bool(dev, "brcm,serial-led-clk-pol"))
-			set_bits |= LED_CTRL_SERIAL_LED_CLK_POL;
-		if (dev_read_bool(dev, "brcm,serial-led-data-ppol"))
-			set_bits |= LED_CTRL_SERIAL_LED_DATA_PPOL;
-		if (dev_read_bool(dev, "brcm,led-test-mode"))
-			set_bits |= LED_CTRL_LED_TEST_MODE;
-
-		clrsetbits_32(regs + LED_CTRL_REG, ~0, set_bits);
-	} else {
-		struct bcm6858_led_priv *priv = dev_get_priv(dev);
-		void __iomem *regs;
-		unsigned int pin, brightness;
-
-		regs = dev_remap_addr(dev_get_parent(dev));
-		if (!regs)
-			return -EINVAL;
-
-		pin = dev_read_u32_default(dev, "reg", LEDS_MAX);
-		if (pin >= LEDS_MAX)
-			return -EINVAL;
-
-		priv->regs = regs;
-		priv->pin = pin;
-
-		/* this led is managed by software */
-		clrbits_32(regs + LED_HW_LED_EN_REG, 1 << pin);
-
-		/* configure the polarity */
-		if (dev_read_bool(dev, "active-low"))
-			clrbits_32(regs + LED_PLED_OP_PPOL_REG, 1 << pin);
-		else
-			setbits_32(regs + LED_PLED_OP_PPOL_REG, 1 << pin);
+	struct bcm6858_led_priv *priv = dev_get_priv(dev);
+	void __iomem *regs;
+	unsigned int pin, brightness;
+
+	regs = dev_remap_addr(dev_get_parent(dev));
+	if (!regs)
+		return -EINVAL;
+
+	pin = dev_read_u32_default(dev, "reg", LEDS_MAX);
+	if (pin >= LEDS_MAX)
+		return -EINVAL;
+
+	priv->regs = regs;
+	priv->pin = pin;
+
+	/* this led is managed by software */
+	clrbits_32(regs + LED_HW_LED_EN_REG, 1 << pin);
 
-		brightness = dev_read_u32_default(dev, "default-brightness",
+	/* configure the polarity */
+	if (dev_read_bool(dev, "active-low"))
+		clrbits_32(regs + LED_PLED_OP_PPOL_REG, 1 << pin);
+	else
+		setbits_32(regs + LED_PLED_OP_PPOL_REG, 1 << pin);
+
+	brightness = dev_read_u32_default(dev, "default-brightness",
 						  LEDS_MAX_BRIGHTNESS);
-		led_set_brightness(dev, brightness);
-	}
+	led_set_brightness(dev, brightness);
 
 	return 0;
 }
 
-static int bcm6858_led_bind(struct udevice *parent)
+U_BOOT_DRIVER(bcm6858_led) = {
+	.name = "bcm6858-led",
+	.id = UCLASS_LED,
+	.probe = bcm6858_led_probe,
+	.priv_auto	= sizeof(struct bcm6858_led_priv),
+	.ops = &bcm6858_led_ops,
+};
+
+static int bcm6858_led_wrap_probe(struct udevice *dev)
+{
+	void __iomem *regs;
+	u32 set_bits = 0;
+
+	regs = dev_remap_addr(dev);
+	if (!regs)
+		return -EINVAL;
+
+	if (dev_read_bool(dev, "brcm,serial-led-msb-first"))
+		set_bits |= LED_CTRL_SERIAL_LED_MSB_FIRST;
+	if (dev_read_bool(dev, "brcm,serial-led-en-pol"))
+		set_bits |= LED_CTRL_SERIAL_LED_EN_POL;
+	if (dev_read_bool(dev, "brcm,serial-led-clk-pol"))
+		set_bits |= LED_CTRL_SERIAL_LED_CLK_POL;
+	if (dev_read_bool(dev, "brcm,serial-led-data-ppol"))
+		set_bits |= LED_CTRL_SERIAL_LED_DATA_PPOL;
+	if (dev_read_bool(dev, "brcm,led-test-mode"))
+		set_bits |= LED_CTRL_LED_TEST_MODE;
+
+	clrsetbits_32(regs + LED_CTRL_REG, ~0, set_bits);
+
+	return 0;
+}
+
+static int bcm6858_led_wrap_bind(struct udevice *parent)
 {
 	ofnode node;
 
@@ -259,12 +267,10 @@ static const struct udevice_id bcm6858_led_ids[] = {
 	{ /* sentinel */ }
 };
 
-U_BOOT_DRIVER(bcm6858_led) = {
-	.name = "bcm6858-led",
-	.id = UCLASS_LED,
+U_BOOT_DRIVER(bcm6858_led_wrap) = {
+	.name	= "bcm6858_led_wrap",
+	.id	= UCLASS_NOP,
 	.of_match = bcm6858_led_ids,
-	.bind = bcm6858_led_bind,
-	.probe = bcm6858_led_probe,
-	.priv_auto	= sizeof(struct bcm6858_led_priv),
-	.ops = &bcm6858_led_ops,
+	.probe = bcm6858_led_wrap_probe,
+	.bind = bcm6858_led_wrap_bind,
 };
diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c
index a862e55bc3..815808498f 100644
--- a/drivers/mailbox/k3-sec-proxy.c
+++ b/drivers/mailbox/k3-sec-proxy.c
@@ -94,11 +94,6 @@ static inline u32 sp_readl(void __iomem *addr, unsigned int offset)
 	return readl(addr + offset);
 }
 
-static inline void sp_writel(void __iomem *addr, unsigned int offset, u32 data)
-{
-	writel(data, addr + offset);
-}
-
 /**
  * k3_sec_proxy_of_xlate() - Translation of phandle to channel
  * @chan:	Mailbox channel
@@ -241,15 +236,20 @@ static int k3_sec_proxy_send(struct mbox_chan *chan, const void *data)
 		/* Ensure all unused data is 0 */
 		data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes));
 		writel(data_trail, data_reg);
-		data_reg++;
+		data_reg += sizeof(u32);
 	}
 
 	/*
 	 * 'data_reg' indicates next register to write. If we did not already
 	 * write on tx complete reg(last reg), we must do so for transmit
+	 * In addition, we also need to make sure all intermediate data
+	 * registers(if any required), are reset to 0 for TISCI backward
+	 * compatibility to be maintained.
 	 */
-	if (data_reg <= (spt->data + spm->desc->data_end_offset))
-		sp_writel(spt->data, spm->desc->data_end_offset, 0);
+	while (data_reg <= (spt->data + spm->desc->data_end_offset)) {
+		writel(0x0, data_reg);
+		data_reg += sizeof(u32);
+	}
 
 	debug("%s: Message successfully sent on thread %ld\n",
 	      __func__, chan->id);
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 04460f1acb..b9f5c7a37a 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -364,8 +364,8 @@ config NPCM_OTP
 	  To compile this driver as a module, choose M here: the module
 	  will be called npcm_otp.
 
-config IMX_SENTINEL
-	bool "Enable i.MX Sentinel MU driver and API"
+config IMX_ELE
+	bool "Enable i.MX EdgeLock Enclave MU driver and API"
 	depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
 	help
 	  If you say Y here to enable Message Unit driver to work with
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 52aed09602..fd8805f34b 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -47,7 +47,7 @@ obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o
 obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
 obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
 obj-$(CONFIG_IMX8) += imx8/
-obj-$(CONFIG_IMX_SENTINEL) += sentinel/
+obj-$(CONFIG_IMX_ELE) += imx_ele/
 obj-$(CONFIG_LED_STATUS) += status_led.o
 obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
 obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
index dfede7f1d5..3e3002ba6d 100644
--- a/drivers/misc/imx8/scu_api.c
+++ b/drivers/misc/imx8/scu_api.c
@@ -481,6 +481,22 @@ int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
 	return 0;
 }
 
+void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status)
+{
+	struct sc_rpc_msg_s msg;
+	struct udevice *dev = gd->arch.scu_dev;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 1U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = (u8)(MISC_FUNC_GET_BUTTON_STATUS);
+
+	misc_call(dev, SC_FALSE, &msg, 1U, &msg, 1U);
+
+	if (status)
+		*status = (sc_bool_t)(!!(RPC_U8(&msg, 0U)));
+}
+
 /* RM */
 sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
 {
@@ -851,6 +867,21 @@ int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
 	return ret;
 }
 
+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int size = sizeof(struct sc_rpc_msg_s);
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = (u8)(PM_FUNC_REBOOT);
+	RPC_U8(&msg, 0U) = (u8)(type);
+	RPC_SIZE(&msg) = 2U;
+
+	misc_call(dev, SC_TRUE, &msg, size, &msg, size);
+}
+
 int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
 				  sc_pm_power_mode_t *mode)
 {
@@ -877,6 +908,28 @@ int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
 	return ret;
 }
 
+int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int size = sizeof(struct sc_rpc_msg_s);
+	int ret;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 2U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = (u8)(TIMER_FUNC_SET_WDOG_WINDOW);
+
+	RPC_U32(&msg, 0U) = (u32)(window);
+
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret)
+		printf("%s: window:%u: res:%d\n",
+		       __func__, window, RPC_R8(&msg));
+
+	return ret;
+}
+
 int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
 			 sc_faddr_t addr)
 {
@@ -974,6 +1027,31 @@ void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit)
 		*commit = RPC_U32(&msg, 4U);
 }
 
+int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int size = sizeof(struct sc_rpc_msg_s);
+	int ret;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 1U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = (u8)(SECO_FUNC_V2X_BUILD_INFO);
+
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret)
+		printf("%s: res:%d\n", __func__, RPC_R8(&msg));
+
+	if (version)
+		*version = RPC_U32(&msg, 0U);
+
+	if (commit)
+		*commit = RPC_U32(&msg, 4U);
+
+	return ret;
+}
+
 int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event)
 {
 	struct udevice *dev = gd->arch.scu_dev;
diff --git a/drivers/misc/sentinel/Makefile b/drivers/misc/imx_ele/Makefile
index 446154cb20..f8d8c55f98 100644
--- a/drivers/misc/sentinel/Makefile
+++ b/drivers/misc/imx_ele/Makefile
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-obj-y += s400_api.o s4mu.o
+obj-y += ele_api.o ele_mu.o
 obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/imx_ele/ele_api.c
index 6c0d0b3f18..0c017734a4 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/imx_ele/ele_api.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2020 NXP
+ * Copyright 2020, 2023 NXP
  *
  */
 
@@ -9,25 +9,37 @@
 #include <malloc.h>
 #include <asm/io.h>
 #include <dm.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
 #include <misc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
+static u32 compute_crc(const struct ele_msg *msg)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	u32 crc = 0;
+	size_t i = 0;
+	u32 *data = (u32 *)msg;
+
+	for (i = 0; i < (msg->size - 1); i++)
+		crc ^= data[i];
+
+	return crc;
+}
+
+int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response)
+{
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 2;
 	msg.command = ELE_RELEASE_RDC_REQ;
 	switch (xrdc) {
@@ -59,20 +71,20 @@ int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
 	return ret;
 }
 
-int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
+int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 3;
 	msg.command = ELE_OEM_CNTN_AUTH_REQ;
 	msg.data[0] = upper_32_bits(ctnr_addr);
@@ -89,20 +101,20 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
 	return ret;
 }
 
-int ahab_release_container(u32 *response)
+int ele_release_container(u32 *response)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 1;
 	msg.command = ELE_RELEASE_CONTAINER_REQ;
 
@@ -117,20 +129,20 @@ int ahab_release_container(u32 *response)
 	return ret;
 }
 
-int ahab_verify_image(u32 img_id, u32 *response)
+int ele_verify_image(u32 img_id, u32 *response)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 2;
 	msg.command = ELE_VERIFY_IMAGE_REQ;
 	msg.data[0] = 1 << img_id;
@@ -146,20 +158,20 @@ int ahab_verify_image(u32 img_id, u32 *response)
 	return ret;
 }
 
-int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
+int ele_forward_lifecycle(u16 life_cycle, u32 *response)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 2;
 	msg.command = ELE_FWD_LIFECYCLE_UP_REQ;
 	msg.data[0] = life_cycle;
@@ -175,15 +187,15 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
 	return ret;
 }
 
-int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response)
+int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
@@ -198,8 +210,8 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respo
 		return -EINVAL;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 2;
 	msg.command = ELE_READ_FUSE_REQ;
 	msg.data[0] = fuse_id;
@@ -223,20 +235,20 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respo
 	return ret;
 }
 
-int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
+int ele_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 3;
 	msg.command = ELE_WRITE_FUSE_REQ;
 	msg.data[0] = (32 << 16) | (fuse_id << 5);
@@ -256,20 +268,20 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
 	return ret;
 }
 
-int ahab_release_caam(u32 core_did, u32 *response)
+int ele_release_caam(u32 core_did, u32 *response)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 2;
 	msg.command = ELE_RELEASE_CAAM_REQ;
 	msg.data[0] = core_did;
@@ -285,15 +297,15 @@ int ahab_release_caam(u32 core_did, u32 *response)
 	return ret;
 }
 
-int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response)
+int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
@@ -307,8 +319,8 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response)
 		return -EINVAL;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 1;
 	msg.command = ELE_GET_FW_VERSION_REQ;
 
@@ -326,20 +338,20 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response)
 	return ret;
 }
 
-int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
+int ele_dump_buffer(u32 *buffer, u32 buffer_length)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret, i = 0;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 1;
 	msg.command = ELE_DUMP_DEBUG_BUFFER_REQ;
 
@@ -360,25 +372,25 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
 	return i;
 }
 
-int ahab_get_info(struct sentinel_get_info_data *info, u32 *response)
+int ele_get_info(struct ele_get_info_data *info, u32 *response)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 4;
 	msg.command = ELE_GET_INFO_REQ;
 	msg.data[0] = upper_32_bits((ulong)info);
 	msg.data[1] = lower_32_bits((ulong)info);
-	msg.data[2] = sizeof(struct sentinel_get_info_data);
+	msg.data[2] = sizeof(struct ele_get_info_data);
 
 	ret = misc_call(dev, false, &msg, size, &msg, size);
 	if (ret)
@@ -391,20 +403,20 @@ int ahab_get_info(struct sentinel_get_info_data *info, u32 *response)
 	return ret;
 }
 
-int ahab_get_fw_status(u32 *status, u32 *response)
+int ele_get_fw_status(u32 *status, u32 *response)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 1;
 	msg.command = ELE_GET_FW_STATUS_REQ;
 
@@ -421,20 +433,20 @@ int ahab_get_fw_status(u32 *status, u32 *response)
 	return ret;
 }
 
-int ahab_release_m33_trout(void)
+int ele_release_m33_trout(void)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 1;
 	msg.command = ELE_ENABLE_RTC_REQ;
 
@@ -446,16 +458,16 @@ int ahab_release_m33_trout(void)
 	return ret;
 }
 
-int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response)
+int ele_get_events(u32 *events, u32 *events_cnt, u32 *response)
 {
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct sentinel_msg);
-	struct sentinel_msg msg;
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
 	int ret, i = 0;
 	u32 actual_events;
 
 	if (!dev) {
-		printf("s400 dev is not initialized\n");
+		printf("ele dev is not initialized\n");
 		return -ENODEV;
 	}
 
@@ -464,8 +476,8 @@ int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response)
 		return -EINVAL;
 	}
 
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
 	msg.size = 1;
 	msg.command = ELE_GET_EVENTS_REQ;
 
@@ -490,3 +502,122 @@ int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response)
 
 	return ret;
 }
+
+int ele_start_rng(void)
+{
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("ele dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 1;
+	msg.command = ELE_START_RNG;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+	return ret;
+}
+
+int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response)
+{
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("ele dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 3;
+	msg.command = ELE_WRITE_SECURE_FUSE_REQ;
+
+	msg.data[0] = upper_32_bits(signed_msg_blk);
+	msg.data[1] = lower_32_bits(signed_msg_blk);
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, response 0x%x, failed fuse row index %u\n",
+		       __func__, ret, msg.data[0], msg.data[1]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response)
+{
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("ele dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 3;
+	msg.command = ELE_RET_LIFECYCLE_UP_REQ;
+
+	msg.data[0] = upper_32_bits(signed_msg_blk);
+	msg.data[1] = lower_32_bits(signed_msg_blk);
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, response 0x%x, failed fuse row index %u\n",
+		       __func__, ret, msg.data[0], msg.data[1]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_output_size)
+{
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("ele dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 8;
+	msg.command = ELE_GENERATE_DEK_BLOB;
+	msg.data[0] = key_id;
+	msg.data[1] = 0x0;
+	msg.data[2] = src_paddr;
+	msg.data[3] = 0x0;
+	msg.data[4] = dst_paddr;
+	msg.data[5] = max_output_size;
+	msg.data[6] = compute_crc(&msg);
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret 0x%x, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+	return ret;
+}
diff --git a/drivers/misc/sentinel/s4mu.c b/drivers/misc/imx_ele/ele_mu.c
index 794fc40c62..053cdcf0fe 100644
--- a/drivers/misc/sentinel/s4mu.c
+++ b/drivers/misc/imx_ele/ele_mu.c
@@ -9,7 +9,7 @@
 #include <dm/lists.h>
 #include <dm/root.h>
 #include <dm/device-internal.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
 #include <asm/arch/imx-regs.h>
 #include <linux/iopoll.h>
 #include <misc.h>
@@ -22,7 +22,7 @@ struct imx8ulp_mu {
 
 #define MU_SR_TE0_MASK		BIT(0)
 #define MU_SR_RF0_MASK		BIT(0)
-#define MU_TR_COUNT		4
+#define MU_TR_COUNT		8
 #define MU_RR_COUNT		4
 
 void mu_hal_init(ulong base)
@@ -42,7 +42,7 @@ int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg)
 
 	assert(reg_index < MU_TR_COUNT);
 
-	debug("sendmsg sr 0x%x\n", readl(&mu_base->sr));
+	debug("sendmsg tsr 0x%x\n", readl(&mu_base->tsr));
 
 	/* Wait TX register to be empty. */
 	ret = readl_poll_timeout(&mu_base->tsr, val, val & mask, 10000);
@@ -64,14 +64,24 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
 	u32 mask = MU_SR_RF0_MASK << reg_index;
 	u32 val;
 	int ret;
+	u32 count = 10;
 
-	assert(reg_index < MU_TR_COUNT);
+	assert(reg_index < MU_RR_COUNT);
 
-	debug("receivemsg sr 0x%x\n", readl(&mu_base->sr));
+	debug("receivemsg rsr 0x%x\n", readl(&mu_base->rsr));
 
-	/* Wait RX register to be full. */
-	ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 10000);
-	if (ret < 0) {
+	do {
+		/* Wait RX register to be full. */
+		ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 1000000);
+		if (ret < 0) {
+			count--;
+			printf("mu receive msg wait %us\n", 10 - count);
+		} else {
+			break;
+		}
+	} while (count > 0);
+
+	if (count == 0) {
 		debug("%s timeout\n", __func__);
 		return -ETIMEDOUT;
 	}
@@ -85,7 +95,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
 
 static int imx8ulp_mu_read(struct mu_type *base, void *data)
 {
-	struct sentinel_msg *msg = (struct sentinel_msg *)data;
+	struct ele_msg *msg = (struct ele_msg *)data;
 	int ret;
 	u8 count = 0;
 
@@ -99,7 +109,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data)
 	count++;
 
 	/* Check size */
-	if (msg->size > S400_MAX_MSG) {
+	if (msg->size > ELE_MAX_MSG) {
 		*((u32 *)msg) = 0;
 		return -EINVAL;
 	}
@@ -118,7 +128,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data)
 
 static int imx8ulp_mu_write(struct mu_type *base, void *data)
 {
-	struct sentinel_msg *msg = (struct sentinel_msg *)data;
+	struct ele_msg *msg = (struct ele_msg *)data;
 	int ret;
 	u8 count = 0;
 
@@ -126,7 +136,7 @@ static int imx8ulp_mu_write(struct mu_type *base, void *data)
 		return -EINVAL;
 
 	/* Check size */
-	if (msg->size > S400_MAX_MSG)
+	if (msg->size > ELE_MAX_MSG)
 		return -EINVAL;
 
 	/* Write first word */
@@ -171,7 +181,7 @@ static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg,
 			return ret;
 	}
 
-	result = ((struct sentinel_msg *)rx_msg)->data[0];
+	result = ((struct ele_msg *)rx_msg)->data[0];
 	if ((result & 0xff) == 0xd6)
 		return 0;
 
@@ -196,7 +206,7 @@ static int imx8ulp_mu_probe(struct udevice *dev)
 	/* U-Boot not enable interrupts, so need to enable RX interrupts */
 	mu_hal_init((ulong)priv->base);
 
-	gd->arch.s400_dev = dev;
+	gd->arch.ele_dev = dev;
 
 	return 0;
 }
diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/imx_ele/fuse.c
index 99342d33c0..4e4dcb42cd 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/imx_ele/fuse.c
@@ -10,7 +10,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/imx-regs.h>
 #include <env.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -24,11 +24,11 @@ struct fsb_map_entry {
 	bool redundancy;
 };
 
-struct s400_map_entry {
+struct ele_map_entry {
 	s32 fuse_bank;
 	u32 fuse_words;
 	u32 fuse_offset;
-	u32 s400_index;
+	u32 ele_index;
 };
 
 #if defined(CONFIG_IMX8ULP)
@@ -65,7 +65,7 @@ u32 nonecc_fuse_banks[] = {
 	0, 1, 8, 12, 16, 22, 24, 25, 26, 27, 36, 41, 51, 56
 };
 
-struct s400_map_entry s400_api_mapping_table[] = {
+struct ele_map_entry ele_api_mapping_table[] = {
 	{ 1, 8 },	/* LOCK */
 	{ 2, 8 },	/* ECID */
 	{ 7, 4, 0, 1 },	/* OTP_UNIQ_ID */
@@ -122,7 +122,7 @@ struct fsb_map_entry fsb_mapping_table[] = {
 	{ 63, 8 },
 };
 
-struct s400_map_entry s400_api_mapping_table[] = {
+struct ele_map_entry ele_api_mapping_table[] = {
 	{ 7, 1, 7, 63 },
 	{ 16, 8, },
 	{ 17, 8, },
@@ -159,18 +159,18 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
 	return word + word_pos;
 }
 
-static s32 map_s400_fuse_index(u32 bank, u32 word)
+static s32 map_ele_fuse_index(u32 bank, u32 word)
 {
-	s32 size = ARRAY_SIZE(s400_api_mapping_table);
+	s32 size = ARRAY_SIZE(ele_api_mapping_table);
 	s32 i;
 
 	/* map the fuse from ocotp fuse map to FSB*/
 	for (i = 0; i < size; i++) {
-		if (s400_api_mapping_table[i].fuse_bank != -1 &&
-		    s400_api_mapping_table[i].fuse_bank == bank) {
-			if (word >= s400_api_mapping_table[i].fuse_offset &&
-			    word < (s400_api_mapping_table[i].fuse_offset +
-			    s400_api_mapping_table[i].fuse_words))
+		if (ele_api_mapping_table[i].fuse_bank != -1 &&
+		    ele_api_mapping_table[i].fuse_bank == bank) {
+			if (word >= ele_api_mapping_table[i].fuse_offset &&
+			    word < (ele_api_mapping_table[i].fuse_offset +
+			    ele_api_mapping_table[i].fuse_words))
 				break;
 		}
 	}
@@ -178,10 +178,10 @@ static s32 map_s400_fuse_index(u32 bank, u32 word)
 	if (i == size)
 		return -1; /* Failed to find */
 
-	if (s400_api_mapping_table[i].s400_index != 0)
-		return s400_api_mapping_table[i].s400_index;
+	if (ele_api_mapping_table[i].ele_index != 0)
+		return ele_api_mapping_table[i].ele_index;
 
-	return s400_api_mapping_table[i].fuse_bank * 8 + word;
+	return ele_api_mapping_table[i].fuse_bank * 8 + word;
 }
 
 #if defined(CONFIG_IMX8ULP)
@@ -202,7 +202,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
 		return 0;
 	}
 
-	word_index = map_s400_fuse_index(bank, word);
+	word_index = map_ele_fuse_index(bank, word);
 	if (word_index >= 0) {
 		u32 data[4];
 		u32 res, size = 4;
@@ -212,7 +212,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
 		if (word_index != 1)
 			size = 1;
 
-		ret = ahab_read_common_fuse(word_index, data, size, &res);
+		ret = ele_read_common_fuse(word_index, data, size, &res);
 		if (ret) {
 			printf("ahab read fuse failed %d, 0x%x\n", ret, res);
 			return ret;
@@ -255,13 +255,13 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
 		return 0;
 	}
 
-	word_index = map_s400_fuse_index(bank, word);
+	word_index = map_ele_fuse_index(bank, word);
 	if (word_index >= 0) {
 		u32 data;
 		u32 res, size = 1;
 		int ret;
 
-		ret = ahab_read_common_fuse(word_index, &data, size, &res);
+		ret = ele_read_common_fuse(word_index, &data, size, &res);
 		if (ret) {
 			printf("ahab read fuse failed %d, 0x%x\n", ret, res);
 			return ret;
@@ -304,7 +304,7 @@ int fuse_prog(u32 bank, u32 word, u32 val)
 		lock = true;
 #endif
 
-	ret = ahab_write_fuse((bank * 8 + word), val, lock, &res);
+	ret = ele_write_fuse((bank * 8 + word), val, lock, &res);
 	if (ret) {
 		printf("ahab write fuse failed %d, 0x%x\n", ret, res);
 		return ret;
diff --git a/drivers/misc/npcm_host_intf.c b/drivers/misc/npcm_host_intf.c
index 0244e40457..79f57f57d8 100644
--- a/drivers/misc/npcm_host_intf.c
+++ b/drivers/misc/npcm_host_intf.c
@@ -50,9 +50,6 @@ static int npcm_host_intf_bind(struct udevice *dev)
 	const char *type;
 	int ret;
 
-	/* Release host wait */
-	setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT);
-
 	syscon = syscon_regmap_lookup_by_phandle(dev, "syscon");
 	if (IS_ERR(syscon)) {
 		dev_err(dev, "%s: unable to get syscon, dev %s\n", __func__, dev->name);
@@ -93,6 +90,9 @@ static int npcm_host_intf_bind(struct udevice *dev)
 		regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, MFSEL1_LPCSEL);
 	}
 
+	/* Release host wait */
+	setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT);
+
 	return 0;
 }
 
diff --git a/drivers/misc/npcm_otp.c b/drivers/misc/npcm_otp.c
index 304910888b..08029724c0 100644
--- a/drivers/misc/npcm_otp.c
+++ b/drivers/misc/npcm_otp.c
@@ -33,7 +33,7 @@ static int npcm_otp_check_inputs(u32 arr, u32 word)
 	if (arr >= NPCM_NUM_OF_SA) {
 		if (IS_ENABLED(CONFIG_ARCH_NPCM8XX))
 			printf("\nError: npcm8XX otp includs only one bank: 0\n");
-		if (IS_ENABLED(CONFIG_ARCH_NPCM7XX))
+		if (IS_ENABLED(CONFIG_ARCH_NPCM7xx))
 			printf("\nError: npcm7XX otp includs only two banks: 0 and 1\n");
 		return -1;
 	}
diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c
index 9ef95caa89..7c01bf23d5 100644
--- a/drivers/misc/qfw.c
+++ b/drivers/misc/qfw.c
@@ -18,6 +18,7 @@
 #include <dm.h>
 #include <misc.h>
 #include <tables_csum.h>
+#include <asm/acpi_table.h>
 
 #if defined(CONFIG_GENERATE_ACPI_TABLE) && !defined(CONFIG_SANDBOX)
 /*
@@ -64,6 +65,11 @@ static int bios_linker_allocate(struct udevice *dev,
 			printf("error: allocating resource\n");
 			return -ENOMEM;
 		}
+		if (aligned_addr < gd->arch.table_start_high)
+			gd->arch.table_start_high = aligned_addr;
+		if (aligned_addr + size > gd->arch.table_end_high)
+			gd->arch.table_end_high = aligned_addr + size;
+
 	} else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
 		aligned_addr = ALIGN(*addr, align);
 	} else {
@@ -188,6 +194,10 @@ ulong write_acpi_tables(ulong addr)
 		return addr;
 	}
 
+	/* QFW always puts tables at high addresses */
+	gd->arch.table_start_high = (ulong)table_loader;
+	gd->arch.table_end_high = (ulong)table_loader;
+
 	qfw_read_entry(dev, be16_to_cpu(file->cfg.select), size, table_loader);
 
 	for (i = 0; i < (size / sizeof(*entry)); i++) {
@@ -227,6 +237,9 @@ out:
 	}
 
 	free(table_loader);
+
+	gd_set_acpi_start(acpi_get_rsdp_addr());
+
 	return addr;
 }
 
diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
index 37b0beeed4..5347ba9043 100644
--- a/drivers/mmc/atmel_sdhci.c
+++ b/drivers/mmc/atmel_sdhci.c
@@ -15,6 +15,9 @@
 #define ATMEL_SDHC_MIN_FREQ	400000
 #define ATMEL_SDHC_GCK_RATE	240000000
 
+#define ATMEL_SDHC_MC1R 0x204
+#define ATMEL_SDHC_MC1R_FCD	0x80
+
 #ifndef CONFIG_DM_MMC
 int atmel_sdhci_init(void *regbase, u32 id)
 {
@@ -52,11 +55,37 @@ struct atmel_sdhci_plat {
 	struct mmc mmc;
 };
 
+static void atmel_sdhci_config_fcd(struct sdhci_host *host)
+{
+	u8 mc1r;
+
+	/* If nonremovable, assume that the card is always present.
+	 *
+	 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
+	 */
+	if ((host->mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
+#if CONFIG_IS_ENABLED(DM_GPIO)
+		|| dm_gpio_get_value(&host->cd_gpio) >= 0
+#endif
+	   ) {
+		sdhci_readb(host, ATMEL_SDHC_MC1R);
+		mc1r |= ATMEL_SDHC_MC1R_FCD;
+		sdhci_writeb(host, mc1r, ATMEL_SDHC_MC1R);
+	}
+}
+
 static int atmel_sdhci_deferred_probe(struct sdhci_host *host)
 {
 	struct udevice *dev = host->mmc->dev;
+	int ret;
 
-	return sdhci_probe(dev);
+	ret = sdhci_probe(dev);
+	if (ret)
+		return ret;
+
+	atmel_sdhci_config_fcd(host);
+
+	return 0;
 }
 
 static const struct sdhci_ops atmel_sdhci_ops = {
@@ -120,7 +149,13 @@ static int atmel_sdhci_probe(struct udevice *dev)
 
 	clk_free(&clk);
 
-	return sdhci_probe(dev);
+	ret = sdhci_probe(dev);
+	if (ret)
+		return ret;
+
+	atmel_sdhci_config_fcd(host);
+
+	return 0;
 }
 
 static int atmel_sdhci_bind(struct udevice *dev)
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 01d9b0201f..0e157672ea 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -421,7 +421,7 @@ int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
 	mmc->cfg = cfg;
 	mmc->priv = dev;
 
-	ret = bootdev_setup_sibling_blk(bdev, "mmc_bootdev");
+	ret = bootdev_setup_for_sibling_blk(bdev, "mmc_bootdev");
 	if (ret)
 		return log_msg_ret("bootdev", ret);
 
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 1af6af82e6..31cfda2885 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -398,6 +398,26 @@ int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
 }
 #endif
 
+int mmc_send_stop_transmission(struct mmc *mmc, bool write)
+{
+	struct mmc_cmd cmd;
+
+	cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
+	cmd.cmdarg = 0;
+	/*
+	 * JEDEC Standard No. 84-B51 Page 126
+	 * CMD12 STOP_TRANSMISSION R1/R1b[3]
+	 * NOTE 3 R1 for read cases and R1b for write cases.
+	 *
+	 * Physical Layer Simplified Specification Version 9.00
+	 * 7.3.1.3 Detailed Command Description
+	 * CMD12 R1b
+	 */
+	cmd.resp_type = (IS_SD(mmc) || write) ? MMC_RSP_R1b : MMC_RSP_R1;
+
+	return mmc_send_cmd(mmc, &cmd, NULL);
+}
+
 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 			   lbaint_t blkcnt)
 {
@@ -425,10 +445,7 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 		return 0;
 
 	if (blkcnt > 1) {
-		cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
-		cmd.cmdarg = 0;
-		cmd.resp_type = MMC_RSP_R1b;
-		if (mmc_send_cmd(mmc, &cmd, NULL)) {
+		if (mmc_send_stop_transmission(mmc, false)) {
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 			pr_err("mmc fail to send stop cmd\n");
 #endif
@@ -2223,6 +2240,7 @@ error:
 			mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 				   EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
 			mmc_select_mode(mmc, MMC_LEGACY);
+			mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
 			mmc_set_bus_width(mmc, 1);
 		}
 	}
@@ -2262,7 +2280,7 @@ static int mmc_startup_v4(struct mmc *mmc)
 		return 0;
 
 	if (!mmc->ext_csd)
-		memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
+		memset(ext_csd_bkup, 0, MMC_MAX_BLOCK_LEN);
 
 	err = mmc_send_ext_csd(mmc, ext_csd);
 	if (err)
diff --git a/drivers/mmc/mmc_bootdev.c b/drivers/mmc/mmc_bootdev.c
index b57b8a6227..55ecead2dd 100644
--- a/drivers/mmc/mmc_bootdev.c
+++ b/drivers/mmc/mmc_bootdev.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Bootdevice for MMC
+ * Bootdev for MMC
  *
  * Copyright 2021 Google LLC
  * Written by Simon Glass <sjg@chromium.org>
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 280d96dbc2..8e716f7449 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -611,6 +611,17 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
 			priv->smpcmp |= BIT(i);
 
 		mdelay(1);
+
+		/*
+		 * eMMC specification specifies that CMD12 can be used to stop a tuning
+		 * command, but SD specification does not, so do nothing unless it is
+		 * eMMC.
+		 */
+		if (ret && (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
+			ret = mmc_send_stop_transmission(mmc, false);
+			if (ret < 0)
+				dev_dbg(dev, "Tuning abort fail (%d)\n", ret);
+		}
 	}
 
 	ret = renesas_sdhi_select_tuning(priv, taps);
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index e44868aaec..935540d171 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -422,7 +422,8 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 
 	mdelay(1);
 
-	arasan_zynqmp_dll_reset(host, priv->node_id);
+	if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a"))
+		arasan_zynqmp_dll_reset(host, priv->node_id);
 
 	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
@@ -468,7 +469,9 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 	}
 
 	udelay(1);
-	arasan_zynqmp_dll_reset(host, priv->node_id);
+
+	if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a"))
+		arasan_zynqmp_dll_reset(host, priv->node_id);
 
 	/* Enable only interrupts served by the SD controller */
 	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
@@ -873,7 +876,7 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
 		if (ret)
 			return ret;
 	} else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
-		   device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
+		   device_is_compatible(dev, "xlnx,versal-net-emmc")) {
 		if (mmc->clock >= MIN_PHY_CLK_HZ)
 			if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN)
 				iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL;
@@ -948,7 +951,7 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev)
 	}
 
 	if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
-	    device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
+	    device_is_compatible(dev, "xlnx,versal-net-emmc")) {
 		for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
 			clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i];
 			clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i];
@@ -1102,7 +1105,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
 		}
 	}
 #endif
-	if (device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
+	if (device_is_compatible(dev, "xlnx,versal-net-emmc"))
 		priv->internal_phy_reg = true;
 
 	ret = clk_get_by_index(dev, 0, &clk);
@@ -1136,7 +1139,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
 		host->quirks |= SDHCI_QUIRK_NO_1_8_V;
 
 	if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) &&
-	    device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
+	    device_is_compatible(dev, "xlnx,versal-net-emmc"))
 		host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400;
 
 	plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
@@ -1219,7 +1222,7 @@ static int arasan_sdhci_bind(struct udevice *dev)
 
 static const struct udevice_id arasan_sdhci_ids[] = {
 	{ .compatible = "arasan,sdhci-8.9a" },
-	{ .compatible = "xlnx,versal-net-5.1-emmc" },
+	{ .compatible = "xlnx,versal-net-emmc" },
 	{ }
 };
 
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 5fa88dae5f..c56840c849 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -128,7 +128,7 @@ config FLASH_SPANSION_S29WS_N
 
 config FLASH_CFI_MTD
 	bool "Enable CFI MTD driver"
-	depends on FLASH_CFI_DRIVER
+	depends on FLASH_CFI_DRIVER && MTD
 	help
 	  This option enables the building of the cfi_mtd driver
 	  in the drivers directory. The driver exports CFI flash
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index d115fcf841..d624589a89 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -553,7 +553,7 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
 	bool "Enable use of 1st stage bootloader timing for NAND"
 	depends on NAND_ZYNQ
 	help
-	  This flag prevent U-boot reconfigure NAND flash controller and reuse
+	  This flag prevent U-Boot reconfigure NAND flash controller and reuse
 	  the NAND timing from 1st stage bootloader.
 
 config NAND_OCTEONTX
@@ -732,10 +732,10 @@ config SYS_NAND_BAD_BLOCK_POS
 	default 5 if HAS_NAND_SMALL_BADBLOCK_POS
 
 config SYS_NAND_U_BOOT_LOCATIONS
-	bool "Define U-boot binaries locations in NAND"
+	bool "Define U-Boot binaries locations in NAND"
 	help
 	Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
-	This option should not be enabled when compiling U-boot for boards
+	This option should not be enabled when compiling U-Boot for boards
 	defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
 	file.
 
diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c
index 60a865b566..c67065eaf8 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c
@@ -275,8 +275,8 @@ void nand_boot(void)
 
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/*
-	 * U-Boot header is appended at end of U-boot image, so
-	 * calculate U-boot header address using U-boot header size.
+	 * U-Boot header is appended at end of U-Boot image, so
+	 * calculate U-Boot header address using U-Boot header size.
 	 */
 #define FSL_U_BOOT_HDR_ADDR \
 		((CFG_SYS_NAND_U_BOOT_START + \
diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c
index fcd1b9c636..d502e967f9 100644
--- a/drivers/mtd/nand/raw/pxa3xx_nand.c
+++ b/drivers/mtd/nand/raw/pxa3xx_nand.c
@@ -125,6 +125,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* System control register and bit to enable NAND on some SoCs */
 #define GENCONF_SOC_DEVICE_MUX	0x208
 #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
+#define GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN BIT(27)
 
 /*
  * This should be large enough to read 'ONFI' and 'JEDEC'.
@@ -167,6 +168,7 @@ enum pxa3xx_nand_variant {
 	PXA3XX_NAND_VARIANT_PXA,
 	PXA3XX_NAND_VARIANT_ARMADA370,
 	PXA3XX_NAND_VARIANT_ARMADA_8K,
+	PXA3XX_NAND_VARIANT_AC5,
 };
 
 struct pxa3xx_nand_host {
@@ -391,6 +393,10 @@ static const struct udevice_id pxa3xx_nand_dt_ids[] = {
 		.compatible = "marvell,armada-8k-nand-controller",
 		.data = PXA3XX_NAND_VARIANT_ARMADA_8K,
 	},
+	{
+		.compatible = "marvell,mvebu-ac5-pxa3xx-nand",
+		.data = PXA3XX_NAND_VARIANT_AC5,
+	},
 	{}
 };
 
@@ -505,6 +511,9 @@ static int pxa3xx_nand_init_timings(struct pxa3xx_nand_host *host)
 		if (mode < 0)
 			mode = 0;
 
+		if (info->variant == PXA3XX_NAND_VARIANT_AC5)
+			mode = min(mode, 3);
+
 		timings = onfi_async_timing_mode_to_sdr_timings(mode);
 		if (IS_ERR(timings))
 			return PTR_ERR(timings);
@@ -730,7 +739,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
 
 		/* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
 		if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
-			info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
+			info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K ||
+			info->variant == PXA3XX_NAND_VARIANT_AC5)
 			nand_writel(info, NDCB0, info->ndcb3);
 	}
 
@@ -1579,7 +1589,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
 
 	/* Device detection must be done with ECC disabled */
 	if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
-		info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
+		info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K ||
+		info->variant == PXA3XX_NAND_VARIANT_AC5)
 		nand_writel(info, NDECCCTRL, 0x0);
 
 	if (nand_scan_ident(mtd, 1, NULL))
@@ -1630,7 +1641,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
 	 */
 	if (mtd->writesize > info->chunk_size) {
 		if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
-			info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) {
+			info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K ||
+			info->variant == PXA3XX_NAND_VARIANT_AC5) {
 			chip->cmdfunc = nand_cmdfunc_extended;
 		} else {
 			dev_err(mtd->dev,
@@ -1728,7 +1740,7 @@ static int alloc_nand_resource(struct udevice *dev, struct pxa3xx_nand_info *inf
 			return PTR_ERR(sysctrl_base);
 
 		regmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, &reg);
-		reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN;
+		reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN | GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN;
 		regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);
 	}
 
diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c
index 5fcf6a6bfc..274489ecbc 100644
--- a/drivers/mtd/nand/raw/rockchip_nfc.c
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -525,7 +525,7 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd,
 	int pages_per_blk = mtd->erasesize / mtd->writesize;
 	int ret = 0, i, boot_rom_mode = 0;
 	dma_addr_t dma_data, dma_oob;
-	u32 reg;
+	u32 tmp;
 	u8 *oob;
 
 	nand_prog_page_begin_op(chip, page, 0, NULL, 0);
@@ -552,6 +552,13 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd,
 	 *
 	 *   0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ...
 	 *
+	 * The code here just swaps the first 4 bytes with the last
+	 * 4 bytes without losing any data.
+	 *
+	 * The chip->oob_poi data layout:
+	 *
+	 *    BBM  OOB1 OOB2 OOB3 |......|  PA0  PA1  PA2  PA3
+	 *
 	 * Configure the ECC algorithm supported by the boot ROM.
 	 */
 	if (page < (pages_per_blk * rknand->boot_blks)) {
@@ -561,21 +568,17 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd,
 	}
 
 	for (i = 0; i < ecc->steps; i++) {
-		if (!i) {
-			reg = 0xFFFFFFFF;
-		} else {
+		if (!i)
+			oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE;
+		else
 			oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
-			reg = oob[0] | oob[1] << 8 | oob[2] << 16 |
-			      oob[3] << 24;
-		}
 
-		if (!i && boot_rom_mode)
-			reg = (page & (pages_per_blk - 1)) * 4;
+		tmp = oob[0] | oob[1] << 8 | oob[2] << 16 | oob[3] << 24;
 
 		if (nfc->cfg->type == NFC_V9)
-			nfc->oob_buf[i] = reg;
+			nfc->oob_buf[i] = tmp;
 		else
-			nfc->oob_buf[i * (oob_step / 4)] = reg;
+			nfc->oob_buf[i * (oob_step / 4)] = tmp;
 	}
 
 	dma_data = dma_map_single((void *)nfc->page_buf,
@@ -720,12 +723,17 @@ static int rk_nfc_read_page_hwecc(struct mtd_info *mtd,
 		goto timeout_err;
 	}
 
-	for (i = 1; i < ecc->steps; i++) {
-		oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
+	for (i = 0; i < ecc->steps; i++) {
+		if (!i)
+			oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE;
+		else
+			oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
+
 		if (nfc->cfg->type == NFC_V9)
 			tmp = nfc->oob_buf[i];
 		else
 			tmp = nfc->oob_buf[i * (oob_step / 4)];
+
 		*oob++ = (u8)tmp;
 		*oob++ = (u8)(tmp >> 8);
 		*oob++ = (u8)(tmp >> 16);
diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c
index 9e3ee7412d..545fdd7b69 100644
--- a/drivers/mtd/nand/raw/zynq_nand.c
+++ b/drivers/mtd/nand/raw/zynq_nand.c
@@ -285,7 +285,7 @@ static int zynq_nand_init_nand_flash(struct mtd_info *mtd, int option)
 {
 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
 	struct nand_drv *smc = nand_get_controller_data(nand_chip);
-	u32 status;
+	int status;
 
 	/* disable interrupts */
 	writel(ZYNQ_NAND_CLR_CONFIG, &smc->reg->cfr);
@@ -332,7 +332,7 @@ static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
 	struct nand_drv *smc = nand_get_controller_data(nand_chip);
 	u32 ecc_value = 0;
 	u8 ecc_reg, ecc_byte;
-	u32 ecc_status;
+	int ecc_status;
 
 	/* Wait till the ECC operation is complete */
 	ecc_status = zynq_nand_waitfor_ecc_completion(mtd);
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 3f8b796789..4587215984 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -446,6 +446,11 @@ const struct flash_info spi_nor_ids[] = {
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
+	{
+		INFO("w25q256jwm", 0xef8019, 0, 64 * 1024, 512,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+	},
 	{ INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) },
 	{
 		INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128,
@@ -528,8 +533,42 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 #endif
 #ifdef CONFIG_SPI_FLASH_XTX
-	/* XTX Technology (Shenzhen) Limited */
-	{ INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	/* XTX Technology Limited */
+	/* adding these 3V QSPI flash parts */
+	{ INFO("xt25f08", 0x0b4014, 0, 64 * 1024, 16,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("xt25f16", 0x0b4015, 0, 64 * 1024, 32,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("xt25f32", 0x0b4016, 0, 64 * 1024, 64,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("xt25f64", 0x0b4017, 0, 64 * 1024, 128,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("xt25f128", 0x0b4018, 0, 64 * 1024, 256,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("xt25f256", 0x0b4019, 0, 64 * 1024, 512,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	/* adding these 1.8V QSPI flash parts */
+	{ INFO("xt25q08", 0x0b6014, 0, 64 * 1024, 16,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("xt25q16", 0x0b6015, 0, 64 * 1024, 32,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("xt25q32", 0x0b6016, 0, 64 * 1024, 64,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("xt25q64", 0x0b6017, 0, 64 * 1024, 128,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("xt25q128", 0x0b6018, 0, 64 * 1024, 256,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("xt25q256", 0x0b6019, 0, 64 * 1024, 512,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("xt25q512", 0x0b601A, 0, 64 * 1024, 1024,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("xt25q01g", 0x0b601B, 0, 64 * 1024, 2048,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	/* adding these wide voltage QSPI flash parts */
+	{ INFO("xt25w512", 0x0b651A, 0, 64 * 1024, 1024,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("xt25w01g", 0x0b651B, 0, 64 * 1024, 2048,
+	       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 #endif
 	{ },
 };
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 39eee98ca7..0ed39a61e4 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
 	  The Synopsys Designware Ethernet QOS IP block with specific
 	  configuration used in Qcom QCS404 SoC.
 
+config DWC_ETH_QOS_STARFIVE
+	bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
+	depends on DWC_ETH_QOS
+	help
+	  The Synopsys Designware Ethernet QOS IP block with specific
+	  configuration used in STARFIVE  JH7110 soc.
+
 config E1000
 	bool "Intel PRO/1000 Gigabit Ethernet support"
 	depends on PCI
@@ -696,6 +703,7 @@ config SUN8I_EMAC
 config SH_ETHER
 	bool "Renesas SH Ethernet MAC"
 	select PHYLIB
+	select PHY_ETHERNET_ID
 	help
 	  This driver supports the Ethernet for Renesas SH and ARM SoCs.
 
@@ -765,6 +773,7 @@ config RENESAS_RAVB
 	bool "Renesas Ethernet AVB MAC"
 	depends on RCAR_64
 	select PHYLIB
+	select PHY_ETHERNET_ID
 	help
 	  This driver implements support for the Ethernet AVB block in
 	  Renesas M3 and H3 SoCs.
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 46a40e2ed9..d4af253b6f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
 obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
 obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
 obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
+obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
 obj-$(CONFIG_E1000) += e1000.o
 obj-$(CONFIG_E1000_SPI) += e1000_spi.o
 obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c
index 912d28fca2..e2340936fa 100644
--- a/drivers/net/altera_tse.c
+++ b/drivers/net/altera_tse.c
@@ -430,17 +430,11 @@ static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
 static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
 {
 	struct phy_device *phydev;
-	unsigned int mask = 0xffffffff;
 
-	if (priv->phyaddr)
-		mask = 1 << priv->phyaddr;
-
-	phydev = phy_find_by_mask(priv->bus, mask);
+	phydev = phy_connect(priv->bus, -1, dev, priv->interface);
 	if (!phydev)
 		return -ENODEV;
 
-	phy_connect_dev(phydev, dev, priv->interface);
-
 	phydev->supported &= PHY_GBIT_FEATURES;
 	phydev->advertising = phydev->supported;
 
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9bbba6eed0..1e92bd9ca9 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1725,6 +1725,12 @@ static const struct udevice_id eqos_ids[] = {
 		.data = (ulong)&eqos_qcom_config
 	},
 #endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
+	{
+		.compatible = "starfive,jh7110-dwmac",
+		.data = (ulong)&eqos_jh7110_config
+	},
+#endif
 
 	{ }
 };
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index fddbe9336c..a6b719af80 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -289,3 +289,4 @@ int eqos_null_ops(struct udevice *dev);
 
 extern struct eqos_config eqos_imx_config;
 extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_starfive.c b/drivers/net/dwc_eth_qos_starfive.c
new file mode 100644
index 0000000000..5be8ac0f1a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_starfive.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/cache.h>
+#include <asm/gpio.h>
+#include <clk.h>
+#include <dm.h>
+#include <eth_phy.h>
+#include <net.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+
+#include "dwc_eth_qos.h"
+
+#define STARFIVE_DWMAC_PHY_INFT_RGMII	0x1
+#define STARFIVE_DWMAC_PHY_INFT_RMII	0x4
+#define STARFIVE_DWMAC_PHY_INFT_FIELD	0x7U
+
+struct starfive_platform_data {
+	struct regmap *regmap;
+	struct reset_ctl_bulk resets;
+	struct clk_bulk clks;
+	phy_interface_t interface;
+	u32 offset;
+	u32 shift;
+	bool tx_use_rgmii_clk;
+};
+
+static int eqos_interface_init_jh7110(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct starfive_platform_data *data = pdata->priv_pdata;
+	struct ofnode_phandle_args args;
+	unsigned int mode;
+	int ret;
+
+	switch (data->interface) {
+	case PHY_INTERFACE_MODE_RMII:
+		mode = STARFIVE_DWMAC_PHY_INFT_RMII;
+		break;
+
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+		mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
+					 2, 0, &args);
+	if (ret)
+		return ret;
+
+	if (args.args_count != 2)
+		return -EINVAL;
+
+	data->offset = args.args[0];
+	data->shift = args.args[1];
+	data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
+	if (IS_ERR(data->regmap)) {
+		ret = PTR_ERR(data->regmap);
+		pr_err("Failed to get regmap: %d\n", ret);
+		return ret;
+	}
+
+	return regmap_update_bits(data->regmap, data->offset,
+				  STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
+				  mode << data->shift);
+}
+
+static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
+{
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct starfive_platform_data *data = pdata->priv_pdata;
+	struct clk *pclk, *c;
+	ulong rate;
+	int ret;
+
+	/* Generally, the rgmii_tx clock is provided by the internal clock,
+	 * which needs to match the corresponding clock frequency according
+	 * to different speeds. If the rgmii_tx clock is provided by the
+	 * external rgmii_rxin, there is no need to configure the clock
+	 * internally, because rgmii_rxin will be adaptively adjusted.
+	 */
+	if (data->tx_use_rgmii_clk)
+		return 0;
+
+	switch (eqos->phy->speed) {
+	case SPEED_1000:
+		rate = 125 * 1000 * 1000;
+		break;
+	case SPEED_100:
+		rate = 25 * 1000 * 1000;
+		break;
+	case SPEED_10:
+		rate = 2.5 * 1000 * 1000;
+		break;
+	default:
+		pr_err("invalid speed %d", eqos->phy->speed);
+		return -EINVAL;
+	}
+
+	/* eqos->clk_tx clock has no set rate operation, so just set the parent
+	 * clock rate directly
+	 */
+	ret = clk_get_by_id(eqos->clk_tx.id, &c);
+	if (ret)
+		return ret;
+
+	pclk = clk_get_parent(c);
+	if (pclk) {
+		ret = clk_set_rate(pclk, rate);
+		if (ret < 0) {
+			pr_err("jh7110 (clk_tx, %lu) failed: %d", rate, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static ulong eqos_get_tick_clk_rate_jh7110(struct udevice *dev)
+{
+	struct eqos_priv *eqos = dev_get_priv(dev);
+
+	return clk_get_rate(&eqos->clk_tx);
+}
+
+static int eqos_start_clks_jh7110(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct starfive_platform_data *data = pdata->priv_pdata;
+
+	return clk_enable_bulk(&data->clks);
+}
+
+static int eqos_stop_clks_jh7110(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct starfive_platform_data *data = pdata->priv_pdata;
+
+	return clk_disable_bulk(&data->clks);
+}
+
+static int eqos_start_resets_jh7110(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct starfive_platform_data *data = pdata->priv_pdata;
+
+	return reset_deassert_bulk(&data->resets);
+}
+
+static int eqos_stop_resets_jh7110(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct starfive_platform_data *data = pdata->priv_pdata;
+
+	return reset_assert_bulk(&data->resets);
+}
+
+static int eqos_remove_resources_jh7110(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct starfive_platform_data *data = pdata->priv_pdata;
+
+	reset_assert_bulk(&data->resets);
+	clk_disable_bulk(&data->clks);
+
+	return 0;
+}
+
+static int eqos_probe_resources_jh7110(struct udevice *dev)
+{
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct starfive_platform_data *data;
+	int ret;
+
+	data = calloc(1, sizeof(struct starfive_platform_data));
+	if (!data)
+		return -ENOMEM;
+
+	pdata->priv_pdata = data;
+	data->interface = eqos->config->interface(dev);
+	if (data->interface == PHY_INTERFACE_MODE_NA) {
+		pr_err("Invalid PHY interface\n");
+		return -EINVAL;
+	}
+
+	ret = reset_get_bulk(dev, &data->resets);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_get_bulk(dev, &data->clks);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_get_by_name(dev, "gtx", &eqos->clk_tx);
+	if (ret)
+		return ret;
+
+	data->tx_use_rgmii_clk = dev_read_bool(dev, "starfive,tx-use-rgmii-clk");
+
+	return eqos_interface_init_jh7110(dev);
+}
+
+static struct eqos_ops eqos_jh7110_ops = {
+	.eqos_inval_desc = eqos_inval_desc_generic,
+	.eqos_flush_desc = eqos_flush_desc_generic,
+	.eqos_inval_buffer = eqos_inval_buffer_generic,
+	.eqos_flush_buffer = eqos_flush_buffer_generic,
+	.eqos_probe_resources = eqos_probe_resources_jh7110,
+	.eqos_remove_resources = eqos_remove_resources_jh7110,
+	.eqos_stop_resets = eqos_stop_resets_jh7110,
+	.eqos_start_resets = eqos_start_resets_jh7110,
+	.eqos_stop_clks = eqos_stop_clks_jh7110,
+	.eqos_start_clks = eqos_start_clks_jh7110,
+	.eqos_calibrate_pads = eqos_null_ops,
+	.eqos_disable_calibration = eqos_null_ops,
+	.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_jh7110,
+	.eqos_get_enetaddr = eqos_null_ops,
+	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_jh7110
+};
+
+/* mdio_wait: There is no need to wait after setting the MAC_MDIO_Address register
+ * swr_wait: Software reset bit must be read at least 4 CSR clock cycles
+ *          after it is written to 1.
+ * config_mac: Enable rx queue to DCB mode.
+ * config_mac_mdio: CSR clock range is 250-300 Mhz.
+ * axi_bus_width: The width of the data bus is 64 bit.
+ */
+struct eqos_config __maybe_unused eqos_jh7110_config = {
+	.reg_access_always_ok = false,
+	.mdio_wait = 0,
+	.swr_wait = 4,
+	.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
+	.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
+	.axi_bus_width = EQOS_AXI_WIDTH_64,
+	.interface = dev_read_phy_mode,
+	.ops = &eqos_jh7110_ops
+};
diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c
index 27b77444a0..9d1e8d38ff 100644
--- a/drivers/net/eth-phy-uclass.c
+++ b/drivers/net/eth-phy-uclass.c
@@ -144,10 +144,18 @@ static int eth_phy_of_to_plat(struct udevice *dev)
 	uc_priv->reset_assert_delay = dev_read_u32_default(dev, "reset-assert-us", 0);
 	uc_priv->reset_deassert_delay = dev_read_u32_default(dev, "reset-deassert-us", 0);
 
+	/* These are used by some DTs, try these as a fallback. */
+	if (!uc_priv->reset_assert_delay && !uc_priv->reset_deassert_delay) {
+		uc_priv->reset_assert_delay =
+			dev_read_u32_default(dev, "reset-delay-us", 0);
+		uc_priv->reset_deassert_delay =
+			dev_read_u32_default(dev, "reset-post-delay-us", 0);
+	}
+
 	return 0;
 }
 
-void eth_phy_reset(struct udevice *dev, int value)
+static void eth_phy_reset(struct udevice *dev, int value)
 {
 	struct eth_phy_device_priv *uc_priv = dev_get_uclass_priv(dev);
 	u32 delay;
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index 29067e9e94..13fad8119b 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -608,18 +608,16 @@ static int ethoc_mdio_init(const char *name, struct ethoc *priv)
 static int ethoc_phy_init(struct ethoc *priv, void *dev)
 {
 	struct phy_device *phydev;
-	int mask = 0xffffffff;
+	int mask = -1;
 
 #ifdef CONFIG_PHY_ADDR
-	mask = 1 << CONFIG_PHY_ADDR;
+	mask = CONFIG_PHY_ADDR;
 #endif
 
-	phydev = phy_find_by_mask(priv->bus, mask);
+	phydev = phy_connect(priv->bus, mask, dev, PHY_INTERFACE_MODE_MII);
 	if (!phydev)
 		return -ENODEV;
 
-	phy_connect_dev(phydev, dev, PHY_INTERFACE_MODE_MII);
-
 	phydev->supported &= PHY_BASIC_FEATURES;
 	phydev->advertising = phydev->supported;
 
diff --git a/drivers/net/fsl-mc/dpbp.c b/drivers/net/fsl-mc/dpbp.c
index c609efb9ab..5e17ccf73d 100644
--- a/drivers/net/fsl-mc/dpbp.c
+++ b/drivers/net/fsl-mc/dpbp.c
@@ -3,25 +3,40 @@
  * Freescale Layerscape MC I/O wrapper
  *
  * Copyright 2013-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2023 NXP
  */
 #include <fsl-mc/fsl_mc_sys.h>
 #include <fsl-mc/fsl_mc_cmd.h>
 #include <fsl-mc/fsl_dpbp.h>
 
-int dpbp_open(struct fsl_mc_io *mc_io,
-	      uint32_t cmd_flags,
-	      int dpbp_id,
-	      uint16_t *token)
+/**
+ * dpbp_open() - Open a control session for the specified object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpbp_id:	DPBP unique ID
+ * @token:	Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpbp_create function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpbp_id, u16 *token)
 {
+	struct dpbp_cmd_open *cmd_params;
 	struct mc_command cmd = { 0 };
 	int err;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPBP_CMDID_OPEN,
-					  cmd_flags,
-					  0);
-	DPBP_CMD_OPEN(cmd, dpbp_id);
+					  cmd_flags, 0);
+	cmd_params = (struct dpbp_cmd_open *)cmd.params;
+	cmd_params->dpbp_id = cpu_to_le32(dpbp_id);
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -29,14 +44,23 @@ int dpbp_open(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+	*token = mc_cmd_hdr_read_token(&cmd);
 
 	return err;
 }
 
-int dpbp_close(struct fsl_mc_io *mc_io,
-	       uint32_t cmd_flags,
-	       uint16_t token)
+/**
+ * dpbp_close() - Close the control session of the object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
@@ -48,11 +72,26 @@ int dpbp_close(struct fsl_mc_io *mc_io,
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpbp_create(struct fsl_mc_io *mc_io,
-		uint16_t dprc_token,
-		uint32_t cmd_flags,
-		const struct dpbp_cfg *cfg,
-		uint32_t *obj_id)
+/**
+ * dpbp_create() - Create the DPBP object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @dprc_token:	Parent container token; '0' for default container
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg:	Configuration structure
+ * @obj_id:	Returned object id; use in subsequent API calls
+ *
+ * Create the DPBP object, allocate required resources and
+ * perform required initialization.
+ *
+ * This function accepts an authentication token of a parent
+ * container that this object should be assigned to and returns
+ * an object id. This object_id will be used in all subsequent calls to
+ * this specific object.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		const struct dpbp_cfg *cfg, u32 *obj_id)
 {
 	struct mc_command cmd = { 0 };
 	int err;
@@ -61,8 +100,7 @@ int dpbp_create(struct fsl_mc_io *mc_io,
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE,
-					  cmd_flags,
-					  dprc_token);
+					  cmd_flags, dprc_token);
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -70,33 +108,46 @@ int dpbp_create(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	MC_CMD_READ_OBJ_ID(cmd, *obj_id);
+	*obj_id = mc_cmd_read_object_id(&cmd);
 
 	return 0;
 }
 
-int dpbp_destroy(struct fsl_mc_io *mc_io,
-		 uint16_t dprc_token,
-		 uint32_t cmd_flags,
-		 uint32_t obj_id)
+/**
+ * dpbp_destroy() - Destroy the DPBP object and release all its resources.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @dprc_token:	Parent container token; '0' for default container
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @obj_id:	ID of DPBP object
+ *
+ * Return:	'0' on Success; error code otherwise.
+ */
+int dpbp_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		 u32 obj_id)
 {
+	struct dpbp_cmd_destroy *cmd_params;
 	struct mc_command cmd = { 0 };
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY,
-					  cmd_flags,
-					  dprc_token);
+					  cmd_flags, dprc_token);
 
-	/* set object id to destroy */
-	CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
+	cmd_params = (struct dpbp_cmd_destroy *)cmd.params;
+	cmd_params->object_id = cpu_to_le32(obj_id);
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpbp_enable(struct fsl_mc_io *mc_io,
-		uint32_t cmd_flags,
-		uint16_t token)
+/**
+ * dpbp_enable() - Enable the DPBP.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
@@ -108,48 +159,66 @@ int dpbp_enable(struct fsl_mc_io *mc_io,
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpbp_disable(struct fsl_mc_io *mc_io,
-		 uint32_t cmd_flags,
-		 uint16_t token)
+/**
+ * dpbp_disable() - Disable the DPBP.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPBP_CMDID_DISABLE,
-					  cmd_flags,
-					  token);
+					  cmd_flags, token);
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpbp_reset(struct fsl_mc_io *mc_io,
-	       uint32_t cmd_flags,
-	       uint16_t token)
+/**
+ * dpbp_reset() - Reset the DPBP, returns the object to initial state.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPBP_CMDID_RESET,
-					  cmd_flags,
-					  token);
+					  cmd_flags, token);
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpbp_get_attributes(struct fsl_mc_io *mc_io,
-			uint32_t cmd_flags,
-			uint16_t token,
+/**
+ * dpbp_get_attributes - Retrieve DPBP attributes.
+ *
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ * @attr:	Returned object's attributes
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
 			struct dpbp_attr *attr)
 {
+	struct dpbp_rsp_get_attributes *rsp_params;
 	struct mc_command cmd = { 0 };
 	int err;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_ATTR,
-					  cmd_flags,
-					  token);
+					  cmd_flags, token);
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -157,15 +226,24 @@ int dpbp_get_attributes(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	DPBP_RSP_GET_ATTRIBUTES(cmd, attr);
+	rsp_params = (struct dpbp_rsp_get_attributes *)cmd.params;
+	attr->bpid = le16_to_cpu(rsp_params->bpid);
+	attr->id = le32_to_cpu(rsp_params->id);
 
 	return 0;
 }
 
-int dpbp_get_api_version(struct fsl_mc_io *mc_io,
-			 u32 cmd_flags,
-			 u16 *major_ver,
-			 u16 *minor_ver)
+/**
+ * dpbp_get_api_version - Get Data Path Buffer Pool API version
+ * @mc_io:	Pointer to Mc portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver:	Major version of Buffer Pool API
+ * @minor_ver:	Minor version of Buffer Pool API
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+			 u16 *major_ver, u16 *minor_ver)
 {
 	struct mc_command cmd = { 0 };
 	int err;
diff --git a/drivers/net/fsl-mc/dpio/dpio.c b/drivers/net/fsl-mc/dpio/dpio.c
index 8884455963..d17210bf45 100644
--- a/drivers/net/fsl-mc/dpio/dpio.c
+++ b/drivers/net/fsl-mc/dpio/dpio.c
@@ -1,18 +1,34 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017, 2023 NXP
  */
 
 #include <fsl-mc/fsl_mc_sys.h>
 #include <fsl-mc/fsl_mc_cmd.h>
 #include <fsl-mc/fsl_dpio.h>
 
-int dpio_open(struct fsl_mc_io *mc_io,
-	      uint32_t cmd_flags,
-	      uint32_t dpio_id,
-	      uint16_t *token)
+/**
+ * dpio_open() - Open a control session for the specified object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpio_id:	DPIO unique ID
+ * @token:	Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpio_create() function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and any MC portals
+ * assigned to the parent container; this token must be used in
+ * all subsequent commands for this specific object.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpio_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpio_id,
+	      u16 *token)
 {
+	struct dpio_cmd_open *cmd_params;
 	struct mc_command cmd = { 0 };
 	int err;
 
@@ -20,7 +36,8 @@ int dpio_open(struct fsl_mc_io *mc_io,
 	cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN,
 					  cmd_flags,
 					  0);
-	DPIO_CMD_OPEN(cmd, dpio_id);
+	cmd_params = (struct dpio_cmd_open *)cmd.params;
+	cmd_params->dpio_id = cpu_to_le32(dpio_id);
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -28,14 +45,20 @@ int dpio_open(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+	*token = mc_cmd_hdr_read_token(&cmd);
 
 	return 0;
 }
 
-int dpio_close(struct fsl_mc_io *mc_io,
-	       uint32_t cmd_flags,
-	       uint16_t token)
+/**
+ * dpio_close() - Close the control session of the object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPIO object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpio_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
@@ -48,12 +71,32 @@ int dpio_close(struct fsl_mc_io *mc_io,
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpio_create(struct fsl_mc_io *mc_io,
-		uint16_t dprc_token,
-		uint32_t cmd_flags,
-		const struct dpio_cfg *cfg,
-		uint32_t *obj_id)
+/**
+ * dpio_create() - Create the DPIO object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @dprc_token:	Parent container token; '0' for default container
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg:	Configuration structure
+ * @obj_id:	Returned object id
+ *
+ * Create the DPIO object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ *
+ * The function accepts an authentication token of a parent
+ * container that this object should be assigned to. The token
+ * can be '0' so the object will be assigned to the default container.
+ * The newly created object can be opened with the returned
+ * object id and using the container's associated tokens and MC portals.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpio_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		const struct dpio_cfg *cfg, u32 *obj_id)
 {
+	struct dpio_cmd_create *cmd_params;
 	struct mc_command cmd = { 0 };
 	int err;
 
@@ -61,7 +104,11 @@ int dpio_create(struct fsl_mc_io *mc_io,
 	cmd.header = mc_encode_cmd_header(DPIO_CMDID_CREATE,
 					  cmd_flags,
 					  dprc_token);
-	DPIO_CMD_CREATE(cmd, cfg);
+	cmd_params = (struct dpio_cmd_create *)cmd.params;
+	cmd_params->num_priorities = cfg->num_priorities;
+	dpio_set_field(cmd_params->channel_mode,
+		       CHANNEL_MODE,
+		       cfg->channel_mode);
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -69,33 +116,54 @@ int dpio_create(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	MC_CMD_READ_OBJ_ID(cmd, *obj_id);
+	*obj_id = mc_cmd_read_object_id(&cmd);
 
 	return 0;
 }
 
-int dpio_destroy(struct fsl_mc_io *mc_io,
-		 uint16_t dprc_token,
-		 uint32_t cmd_flags,
-		 uint32_t obj_id)
+/**
+ * dpio_destroy() - Destroy the DPIO object and release all its resources.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @dprc_token: Parent container token; '0' for default container
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @object_id:	The object id; it must be a valid id within the container that
+ *		created this object;
+ *
+ * The function accepts the authentication token of the parent container that
+ * created the object (not the one that currently owns the object). The object
+ * is searched within parent using the provided 'object_id'.
+ * All tokens to the object must be closed before calling destroy.
+ *
+ * Return:	'0' on Success; Error code otherwise
+ */
+int dpio_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		 u32 object_id)
 {
+	struct dpio_cmd_destroy *cmd_params;
 	struct mc_command cmd = { 0 };
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPIO_CMDID_DESTROY,
-					  cmd_flags,
-					  dprc_token);
+			cmd_flags,
+			dprc_token);
 
 	/* set object id to destroy */
-	CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
+	cmd_params = (struct dpio_cmd_destroy *)cmd.params;
+	cmd_params->dpio_id = cpu_to_le32(object_id);
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpio_enable(struct fsl_mc_io *mc_io,
-		uint32_t cmd_flags,
-		uint16_t token)
+/**
+ * dpio_enable() - Enable the DPIO, allow I/O portal operations.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPIO object
+ *
+ * Return:	'0' on Success; Error code otherwise
+ */
+int dpio_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
@@ -108,9 +176,15 @@ int dpio_enable(struct fsl_mc_io *mc_io,
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpio_disable(struct fsl_mc_io *mc_io,
-		 uint32_t cmd_flags,
-		 uint16_t token)
+/**
+ * dpio_disable() - Disable the DPIO, stop any I/O portal operation.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPIO object
+ *
+ * Return:	'0' on Success; Error code otherwise
+ */
+int dpio_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
@@ -123,26 +197,19 @@ int dpio_disable(struct fsl_mc_io *mc_io,
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpio_reset(struct fsl_mc_io *mc_io,
-	       uint32_t cmd_flags,
-	       uint16_t token)
-{
-	struct mc_command cmd = { 0 };
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPIO_CMDID_RESET,
-					  cmd_flags,
-					  token);
-
-	/* send command to mc*/
-	return mc_send_command(mc_io, &cmd);
-}
-
-int dpio_get_attributes(struct fsl_mc_io *mc_io,
-			uint32_t cmd_flags,
-			uint16_t token,
+/**
+ * dpio_get_attributes() - Retrieve DPIO attributes
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPIO object
+ * @attr:	Returned object's attributes
+ *
+ * Return:	'0' on Success; Error code otherwise
+ */
+int dpio_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
 			struct dpio_attr *attr)
 {
+	struct dpio_rsp_get_attr *rsp_params;
 	struct mc_command cmd = { 0 };
 	int err;
 
@@ -157,29 +224,42 @@ int dpio_get_attributes(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	DPIO_RSP_GET_ATTR(cmd, attr);
+	rsp_params = (struct dpio_rsp_get_attr *)cmd.params;
+	attr->id = le32_to_cpu(rsp_params->id);
+	attr->qbman_portal_id = le16_to_cpu(rsp_params->qbman_portal_id);
+	attr->num_priorities = rsp_params->num_priorities;
+	attr->qbman_portal_ce_offset = le64_to_cpu(rsp_params->qbman_portal_ce_offset);
+	attr->qbman_portal_ci_offset = le64_to_cpu(rsp_params->qbman_portal_ci_offset);
+	attr->qbman_version = le32_to_cpu(rsp_params->qbman_version);
+	attr->clk = le32_to_cpu(rsp_params->clk);
+	attr->channel_mode = dpio_get_field(rsp_params->channel_mode, ATTR_CHANNEL_MODE);
 
 	return 0;
 }
 
-int dpio_get_api_version(struct fsl_mc_io *mc_io,
-			 u32 cmd_flags,
-			 u16 *major_ver,
-			 u16 *minor_ver)
+/**
+ * dpio_get_api_version() - Get Data Path I/O API version
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver:	Major version of data path i/o API
+ * @minor_ver:	Minor version of data path i/o API
+ *
+ * Return:  '0' on Success; Error code otherwise.
+ */
+int dpio_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+			 u16 *major_ver, u16 *minor_ver)
 {
 	struct mc_command cmd = { 0 };
 	int err;
 
-	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_API_VERSION,
-					  cmd_flags, 0);
+					cmd_flags,
+					0);
 
-	/* send command to mc */
 	err = mc_send_command(mc_io, &cmd);
 	if (err)
 		return err;
 
-	/* retrieve response parameters */
 	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
 
 	return 0;
diff --git a/drivers/net/fsl-mc/dpmac.c b/drivers/net/fsl-mc/dpmac.c
index 43a2ff43f8..5d4f6c67fd 100644
--- a/drivers/net/fsl-mc/dpmac.c
+++ b/drivers/net/fsl-mc/dpmac.c
@@ -11,19 +11,33 @@
 #include <fsl-mc/fsl_mc_cmd.h>
 #include <fsl-mc/fsl_dpmac.h>
 
-int dpmac_open(struct fsl_mc_io *mc_io,
-	       uint32_t cmd_flags,
-	       int dpmac_id,
-	       uint16_t *token)
+/**
+ * dpmac_open() - Open a control session for the specified object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpmac_id:	DPMAC unique ID
+ * @token:	Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpmac_create function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpmac_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpmac_id, u16 *token)
 {
+	struct dpmac_cmd_open *cmd_params;
 	struct mc_command cmd = { 0 };
 	int err;
 
 	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN,
-					  cmd_flags,
-					  0);
-	DPMAC_CMD_OPEN(cmd, dpmac_id);
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN, cmd_flags, 0);
+	cmd_params = (struct dpmac_cmd_open *)cmd.params;
+	cmd_params->dpmac_id = cpu_to_le32(dpmac_id);
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -31,39 +45,63 @@ int dpmac_open(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+	*token = mc_cmd_hdr_read_token(&cmd);
 
 	return err;
 }
 
-int dpmac_close(struct fsl_mc_io *mc_io,
-		uint32_t cmd_flags,
-		uint16_t token)
+/**
+ * dpmac_close() - Close the control session of the object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPMAC object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpmac_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
 	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags,
-					  token);
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags, token);
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpmac_create(struct fsl_mc_io *mc_io,
-		 uint16_t dprc_token,
-		 uint32_t cmd_flags,
-		 const struct dpmac_cfg *cfg,
-		 uint32_t *obj_id)
+/**
+ * dpmac_create() - Create the DPMAC object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @dprc_token: Parent container token; '0' for default container
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg:	Configuration structure
+ * @obj_id:	Returned object id
+ *
+ * Create the DPMAC object, allocate required resources and
+ * perform required initialization.
+ *
+ * The function accepts an authentication token of a parent
+ * container that this object should be assigned to. The token
+ * can be '0' so the object will be assigned to the default container.
+ * The newly created object can be opened with the returned
+ * object id and using the container's associated tokens and MC portals.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpmac_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		 const struct dpmac_cfg *cfg, u32 *obj_id)
 {
+	struct dpmac_cmd_create *cmd_params;
 	struct mc_command cmd = { 0 };
 	int err;
 
 	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE,
-					  cmd_flags,
-					  dprc_token);
-	DPMAC_CMD_CREATE(cmd, cfg);
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE, cmd_flags, dprc_token);
+	cmd_params = (struct dpmac_cmd_create *)cmd.params;
+	cmd_params->mac_id = cpu_to_le32(cfg->mac_id);
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -71,142 +109,87 @@ int dpmac_create(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	MC_CMD_READ_OBJ_ID(cmd, *obj_id);
+	*obj_id = mc_cmd_read_object_id(&cmd);
 
 	return 0;
 }
 
-int dpmac_destroy(struct fsl_mc_io *mc_io,
-		  uint16_t dprc_token,
-		  uint32_t cmd_flags,
-		  uint32_t obj_id)
+/**
+ * dpmac_destroy() - Destroy the DPMAC object and release all its resources.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @dprc_token: Parent container token; '0' for default container
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @object_id:	The object id; it must be a valid id within the container that
+ * created this object;
+ *
+ * The function accepts the authentication token of the parent container that
+ * created the object (not the one that currently owns the object). The object
+ * is searched within parent using the provided 'object_id'.
+ * All tokens to the object must be closed before calling destroy.
+ *
+ * Return:	'0' on Success; error code otherwise.
+ */
+int dpmac_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		  u32 object_id)
 {
+	struct dpmac_cmd_destroy *cmd_params;
 	struct mc_command cmd = { 0 };
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY,
 					  cmd_flags,
 					  dprc_token);
-
-	/* set object id to destroy */
-	CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
-
-	/* send command to mc*/
-	return mc_send_command(mc_io, &cmd);
-}
-
-int dpmac_get_attributes(struct fsl_mc_io *mc_io,
-			 uint32_t cmd_flags,
-			 uint16_t token,
-			 struct dpmac_attr *attr)
-{
-	struct mc_command cmd = { 0 };
-	int err;
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR,
-					  cmd_flags,
-					  token);
-
-	/* send command to mc*/
-	err = mc_send_command(mc_io, &cmd);
-	if (err)
-		return err;
-
-	/* retrieve response parameters */
-	DPMAC_RSP_GET_ATTRIBUTES(cmd, attr);
-
-	return 0;
-}
-
-int dpmac_mdio_read(struct fsl_mc_io *mc_io,
-		    uint32_t cmd_flags,
-		    uint16_t token,
-		    struct dpmac_mdio_cfg *cfg)
-{
-	struct mc_command cmd = { 0 };
-	int err;
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_READ,
-					  cmd_flags,
-					  token);
-	DPMAC_CMD_MDIO_READ(cmd, cfg);
-
-	/* send command to mc*/
-	err = mc_send_command(mc_io, &cmd);
-	if (err)
-		return err;
-
-	/* retrieve response parameters */
-	DPMAC_RSP_MDIO_READ(cmd, cfg->data);
-
-	return 0;
-}
-
-int dpmac_mdio_write(struct fsl_mc_io *mc_io,
-		     uint32_t cmd_flags,
-		     uint16_t token,
-		     struct dpmac_mdio_cfg *cfg)
-{
-	struct mc_command cmd = { 0 };
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_WRITE,
-					  cmd_flags,
-					  token);
-	DPMAC_CMD_MDIO_WRITE(cmd, cfg);
+	cmd_params = (struct dpmac_cmd_destroy *)cmd.params;
+	cmd_params->dpmac_id = cpu_to_le32(object_id);
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
-		       uint32_t cmd_flags,
-		       uint16_t token,
-		       struct dpmac_link_cfg *cfg)
-{
-	struct mc_command cmd = { 0 };
-	int err = 0;
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG,
-					  cmd_flags,
-					  token);
-
-	/* send command to mc*/
-	err = mc_send_command(mc_io, &cmd);
-	if (err)
-		return err;
-
-	DPMAC_RSP_GET_LINK_CFG(cmd, cfg);
-
-	return 0;
-}
-
-int dpmac_set_link_state(struct fsl_mc_io *mc_io,
-			 uint32_t cmd_flags,
-			 uint16_t token,
+/**
+ * dpmac_set_link_state() - Set the Ethernet link status
+ * @mc_io:	Pointer to opaque I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPMAC object
+ * @link_state:	Link state configuration
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpmac_set_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
 			 struct dpmac_link_state *link_state)
 {
+	struct dpmac_cmd_set_link_state *cmd_params;
 	struct mc_command cmd = { 0 };
 
 	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE,
-					  cmd_flags,
-					  token);
-	DPMAC_CMD_SET_LINK_STATE(cmd, link_state);
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE, cmd_flags, token);
+	cmd_params = (struct dpmac_cmd_set_link_state *)cmd.params;
+	cmd_params->options = cpu_to_le64(link_state->options);
+	cmd_params->rate = cpu_to_le32(link_state->rate);
+	cmd_params->up = dpmac_get_field(link_state->up, STATE);
+	dpmac_set_field(cmd_params->up, STATE_VALID, link_state->state_valid);
+	cmd_params->supported = cpu_to_le64(link_state->supported);
+	cmd_params->advertising = cpu_to_le64(link_state->advertising);
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpmac_get_counter(struct fsl_mc_io *mc_io,
-		      uint32_t cmd_flags,
-		      uint16_t token,
-		      enum dpmac_counter type,
-		      uint64_t *counter)
+/**
+ * dpmac_get_counter() - Read a specific DPMAC counter
+ * @mc_io:	Pointer to opaque I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPMAC object
+ * @type:	The requested counter
+ * @counter:	Returned counter value
+ *
+ * Return:	The requested counter; '0' otherwise.
+ */
+int dpmac_get_counter(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		      enum dpmac_counter type, uint64_t *counter)
 {
+	struct dpmac_cmd_get_counter *dpmac_cmd;
+	struct dpmac_rsp_get_counter *dpmac_rsp;
 	struct mc_command cmd = { 0 };
 	int err = 0;
 
@@ -214,36 +197,43 @@ int dpmac_get_counter(struct fsl_mc_io *mc_io,
 	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER,
 					  cmd_flags,
 					  token);
-	DPMAC_CMD_GET_COUNTER(cmd, type);
+	dpmac_cmd = (struct dpmac_cmd_get_counter *)cmd.params;
+	dpmac_cmd->type = type;
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
 	if (err)
 		return err;
 
-	DPMAC_RSP_GET_COUNTER(cmd, *counter);
+	dpmac_rsp = (struct dpmac_rsp_get_counter *)cmd.params;
+	*counter = le64_to_cpu(dpmac_rsp->counter);
 
 	return 0;
 }
 
-int dpmac_get_api_version(struct fsl_mc_io *mc_io,
-			 u32 cmd_flags,
-			 u16 *major_ver,
-			 u16 *minor_ver)
+/**
+ * dpmac_get_api_version() - Get Data Path MAC version
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver:	Major version of data path mac API
+ * @minor_ver:	Minor version of data path mac API
+ *
+ * Return:  '0' on Success; Error code otherwise.
+ */
+int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+			  u16 *major_ver, u16 *minor_ver)
 {
 	struct mc_command cmd = { 0 };
 	int err;
 
-	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_API_VERSION,
-					  cmd_flags, 0);
+					cmd_flags,
+					0);
 
-	/* send command to mc */
 	err = mc_send_command(mc_io, &cmd);
 	if (err)
 		return err;
 
-	/* retrieve response parameters */
 	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
 
 	return 0;
diff --git a/drivers/net/fsl-mc/dpmng.c b/drivers/net/fsl-mc/dpmng.c
index 8314243f35..147ca6da9e 100644
--- a/drivers/net/fsl-mc/dpmng.c
+++ b/drivers/net/fsl-mc/dpmng.c
@@ -1,15 +1,24 @@
 // SPDX-License-Identifier: GPL-2.0+
 /* Copyright 2013-2015 Freescale Semiconductor Inc.
+ * Copyright 2023 NXP
  */
 #include <fsl-mc/fsl_mc_sys.h>
 #include <fsl-mc/fsl_mc_cmd.h>
 #include <fsl-mc/fsl_dpmng.h>
 #include "fsl_dpmng_cmd.h"
 
-int mc_get_version(struct fsl_mc_io *mc_io,
-		   uint32_t cmd_flags,
-		   struct mc_version *mc_ver_info)
+/**
+ * mc_get_version() - Retrieves the Management Complex firmware
+ *			version information
+ * @mc_io:		Pointer to opaque I/O object
+ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
+ * @mc_ver_info:	Returned version information structure
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int mc_get_version(struct fsl_mc_io *mc_io, uint32_t cmd_flags, struct mc_version *mc_ver_info)
 {
+	struct dpmng_rsp_get_version *rsp_params;
 	struct mc_command cmd = { 0 };
 	int err;
 
@@ -24,7 +33,10 @@ int mc_get_version(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	DPMNG_RSP_GET_VERSION(cmd, mc_ver_info);
+	rsp_params = (struct dpmng_rsp_get_version *)cmd.params;
+	mc_ver_info->revision = le32_to_cpu(rsp_params->revision);
+	mc_ver_info->major = le32_to_cpu(rsp_params->version_major);
+	mc_ver_info->minor = le32_to_cpu(rsp_params->version_minor);
 
 	return 0;
 }
diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c
index 5290be20c8..5b815a45a9 100644
--- a/drivers/net/fsl-mc/dpni.c
+++ b/drivers/net/fsl-mc/dpni.c
@@ -1,46 +1,43 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017, 2023 NXP
  */
 
 #include <fsl-mc/fsl_mc_sys.h>
 #include <fsl-mc/fsl_mc_cmd.h>
 #include <fsl-mc/fsl_dpni.h>
 
-int dpni_prepare_cfg(const struct dpni_cfg	*cfg,
-		     uint8_t			*cfg_buf)
-{
-	uint64_t *params = (uint64_t *)cfg_buf;
-
-	DPNI_PREP_CFG(params, cfg);
-
-	return 0;
-}
-
-int dpni_extract_cfg(struct dpni_cfg	*cfg,
-		     const uint8_t	*cfg_buf)
-{
-	uint64_t *params = (uint64_t *)cfg_buf;
-
-	DPNI_EXT_CFG(params, cfg);
-
-	return 0;
-}
-
-int dpni_open(struct fsl_mc_io *mc_io,
-	      uint32_t cmd_flags,
-	      int dpni_id,
-	      uint16_t *token)
+/**
+ * dpni_open() - Open a control session for the specified object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpni_id:	DPNI unique ID
+ * @token:	Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpni_create() function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpni_id, u16 *token)
 {
+	struct dpni_cmd_open *cmd_params;
 	struct mc_command cmd = { 0 };
+
 	int err;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_OPEN,
 					  cmd_flags,
 					  0);
-	DPNI_CMD_OPEN(cmd, dpni_id);
+	cmd_params = (struct dpni_cmd_open *)cmd.params;
+	cmd_params->dpni_id = cpu_to_le32(dpni_id);
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -48,14 +45,23 @@ int dpni_open(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+	*token = mc_cmd_hdr_read_token(&cmd);
 
 	return 0;
 }
 
-int dpni_close(struct fsl_mc_io *mc_io,
-	       uint32_t cmd_flags,
-	       uint16_t token)
+/**
+ * dpni_close() - Close the control session of the object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
@@ -68,12 +74,32 @@ int dpni_close(struct fsl_mc_io *mc_io,
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpni_create(struct fsl_mc_io *mc_io,
-		uint16_t dprc_token,
-		uint32_t cmd_flags,
-		const struct dpni_cfg *cfg,
-		uint32_t *obj_id)
+/**
+ * dpni_create() - Create the DPNI object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @dprc_token:	Parent container token; '0' for default container
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg:	Configuration structure
+ * @obj_id:	Returned object id
+ *
+ * Create the DPNI object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ *
+ * The function accepts an authentication token of a parent
+ * container that this object should be assigned to. The token
+ * can be '0' so the object will be assigned to the default container.
+ * The newly created object can be opened with the returned
+ * object id and using the container's associated tokens and MC portals.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		const struct dpni_cfg *cfg, u32 *obj_id)
 {
+	struct dpni_cmd_create *cmd_params;
 	struct mc_command cmd = { 0 };
 	int err;
 
@@ -81,7 +107,19 @@ int dpni_create(struct fsl_mc_io *mc_io,
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_CREATE,
 					  cmd_flags,
 					  dprc_token);
-	DPNI_CMD_CREATE(cmd, cfg);
+	cmd_params = (struct dpni_cmd_create *)cmd.params;
+	cmd_params->options = cpu_to_le32(cfg->options);
+	cmd_params->num_queues = cfg->num_queues;
+	cmd_params->num_tcs = cfg->num_tcs;
+	cmd_params->mac_filter_entries = cfg->mac_filter_entries;
+	cmd_params->num_rx_tcs = cfg->num_rx_tcs;
+	cmd_params->vlan_filter_entries =  cfg->vlan_filter_entries;
+	cmd_params->qos_entries = cfg->qos_entries;
+	cmd_params->fs_entries = cpu_to_le16(cfg->fs_entries);
+	cmd_params->num_cgs = cfg->num_cgs;
+	cmd_params->num_opr = cfg->num_opr;
+	cmd_params->dist_key_size = cfg->dist_key_size;
+	cmd_params->num_channels = cfg->num_channels;
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -89,50 +127,94 @@ int dpni_create(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	 MC_CMD_READ_OBJ_ID(cmd, *obj_id);
+	*obj_id = mc_cmd_read_object_id(&cmd);
 
 	return 0;
 }
 
-int dpni_destroy(struct fsl_mc_io *mc_io,
-		 uint16_t dprc_token,
-		 uint32_t cmd_flags,
-		 uint32_t obj_id)
+/**
+ * dpni_destroy() - Destroy the DPNI object and release all its resources.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @dprc_token: Parent container token; '0' for default container
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @object_id:	The object id; it must be a valid id within the container that
+ * created this object;
+ *
+ * The function accepts the authentication token of the parent container that
+ * created the object (not the one that currently owns the object). The object
+ * is searched within parent using the provided 'object_id'.
+ * All tokens to the object must be closed before calling destroy.
+ *
+ * Return:	'0' on Success; error code otherwise.
+ */
+int dpni_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		 u32 object_id)
 {
+	struct dpni_cmd_destroy *cmd_params;
 	struct mc_command cmd = { 0 };
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_DESTROY,
 					  cmd_flags,
 					  dprc_token);
-
 	/* set object id to destroy */
-	CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
+	cmd_params = (struct dpni_cmd_destroy *)cmd.params;
+	cmd_params->dpni_id = cpu_to_le32(object_id);
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpni_set_pools(struct fsl_mc_io *mc_io,
-		   uint32_t cmd_flags,
-		   uint16_t token,
+/**
+ * dpni_set_pools() - Set buffer pools configuration
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @cfg:	Buffer pools configuration
+ *
+ * mandatory for DPNI operation
+ * warning:Allowed only when DPNI is disabled
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_set_pools(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
 		   const struct dpni_pools_cfg *cfg)
 {
 	struct mc_command cmd = { 0 };
+	struct dpni_cmd_set_pools *cmd_params;
+	int i;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_POOLS,
 					  cmd_flags,
 					  token);
-	DPNI_CMD_SET_POOLS(cmd, cfg);
+	cmd_params = (struct dpni_cmd_set_pools *)cmd.params;
+	cmd_params->num_dpbp = cfg->num_dpbp;
+	cmd_params->pool_options = cfg->pool_options;
+	for (i = 0; i < DPNI_MAX_DPBP; i++) {
+		cmd_params->pool[i].dpbp_id =
+			cpu_to_le16(cfg->pools[i].dpbp_id);
+		cmd_params->pool[i].priority_mask =
+			cfg->pools[i].priority_mask;
+		cmd_params->buffer_size[i] =
+			cpu_to_le16(cfg->pools[i].buffer_size);
+		cmd_params->backup_pool_mask |=
+			DPNI_BACKUP_POOL(cfg->pools[i].backup_pool, i);
+	}
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpni_enable(struct fsl_mc_io *mc_io,
-		uint32_t cmd_flags,
-		uint16_t token)
+/**
+ * dpni_enable() - Enable the DPNI, allow sending and receiving frames.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
@@ -145,9 +227,15 @@ int dpni_enable(struct fsl_mc_io *mc_io,
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpni_disable(struct fsl_mc_io *mc_io,
-		 uint32_t cmd_flags,
-		 uint16_t token)
+/**
+ * dpni_disable() - Disable the DPNI, stop sending and receiving frames.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
@@ -160,9 +248,15 @@ int dpni_disable(struct fsl_mc_io *mc_io,
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpni_reset(struct fsl_mc_io *mc_io,
-	       uint32_t cmd_flags,
-	       uint16_t token)
+/**
+ * dpni_reset() - Reset the DPNI, returns the object to initial state.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
@@ -175,76 +269,121 @@ int dpni_reset(struct fsl_mc_io *mc_io,
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpni_get_attributes(struct fsl_mc_io *mc_io,
-			uint32_t cmd_flags,
-			uint16_t token,
+/**
+ * dpni_get_attributes() - Retrieve DPNI attributes.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @attr:	Object's attributes
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
 			struct dpni_attr *attr)
 {
 	struct mc_command cmd = { 0 };
+	struct dpni_rsp_get_attr *rsp_params;
+
 	int err;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR,
 					  cmd_flags,
 					  token);
+
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
 	if (err)
 		return err;
 
 	/* retrieve response parameters */
-	DPNI_RSP_GET_ATTR(cmd, attr);
+	rsp_params = (struct dpni_rsp_get_attr *)cmd.params;
+	attr->options = le32_to_cpu(rsp_params->options);
+	attr->num_queues = rsp_params->num_queues;
+	attr->num_rx_tcs = rsp_params->num_rx_tcs;
+	attr->num_tx_tcs = rsp_params->num_tx_tcs;
+	attr->mac_filter_entries = rsp_params->mac_filter_entries;
+	attr->vlan_filter_entries = rsp_params->vlan_filter_entries;
+	attr->num_channels = rsp_params->num_channels;
+	attr->qos_entries = rsp_params->qos_entries;
+	attr->fs_entries = le16_to_cpu(rsp_params->fs_entries);
+	attr->num_opr = le16_to_cpu(rsp_params->num_opr);
+	attr->qos_key_size = rsp_params->qos_key_size;
+	attr->fs_key_size = rsp_params->fs_key_size;
+	attr->wriop_version = le16_to_cpu(rsp_params->wriop_version);
+	attr->num_cgs = rsp_params->num_cgs;
 
 	return 0;
 }
 
-int dpni_set_errors_behavior(struct fsl_mc_io *mc_io,
-			     uint32_t cmd_flags,
-			     uint16_t token,
-			      struct dpni_error_cfg *cfg)
-{
-	struct mc_command cmd = { 0 };
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_ERRORS_BEHAVIOR,
-					  cmd_flags,
-					  token);
-	DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg);
-
-	/* send command to mc*/
-	return mc_send_command(mc_io, &cmd);
-}
-
-int dpni_set_buffer_layout(struct fsl_mc_io *mc_io,
-			   uint32_t cmd_flags,
-			   uint16_t token,
-			   const struct dpni_buffer_layout *layout,
-			   enum dpni_queue_type type)
+/**
+ * dpni_set_buffer_layout() - Set buffer layout configuration.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @qtype:	Type of queue this configuration applies to
+ * @layout:	Buffer layout configuration
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ *
+ * @warning	Allowed only when DPNI is disabled
+ */
+int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			   enum dpni_queue_type qtype,
+			   const struct dpni_buffer_layout *layout)
 {
+	struct dpni_cmd_set_buffer_layout *cmd_params;
 	struct mc_command cmd = { 0 };
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_BUFFER_LAYOUT,
 					  cmd_flags,
 					  token);
-	DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, type);
+	cmd_params = (struct dpni_cmd_set_buffer_layout *)cmd.params;
+	cmd_params->qtype = qtype;
+	cmd_params->options = cpu_to_le16((u16)layout->options);
+	dpni_set_field(cmd_params->flags, PASS_TS, layout->pass_timestamp);
+	dpni_set_field(cmd_params->flags, PASS_PR, layout->pass_parser_result);
+	dpni_set_field(cmd_params->flags, PASS_FS, layout->pass_frame_status);
+	dpni_set_field(cmd_params->flags, PASS_SWO, layout->pass_sw_opaque);
+	cmd_params->private_data_size = cpu_to_le16(layout->private_data_size);
+	cmd_params->data_align = cpu_to_le16(layout->data_align);
+	cmd_params->head_room = cpu_to_le16(layout->data_head_room);
+	cmd_params->tail_room = cpu_to_le16(layout->data_tail_room);
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpni_get_qdid(struct fsl_mc_io *mc_io,
-		  uint32_t cmd_flags,
-		  uint16_t token,
-		  uint16_t *qdid)
+/**
+ * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used
+ *			for enqueue operations
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @qtype:	Type of queue to receive QDID for
+ * @qdid:	Returned virtual QDID value that should be used as an argument
+ *			in all enqueue operations
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ *
+ * If dpni object is created using multiple Tc channels this function will return
+ * qdid value for the first channel
+ */
+int dpni_get_qdid(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		  enum dpni_queue_type qtype, u16 *qdid)
 {
 	struct mc_command cmd = { 0 };
+	struct dpni_cmd_get_qdid *cmd_params;
+	struct dpni_rsp_get_qdid *rsp_params;
 	int err;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QDID,
 					  cmd_flags,
 					  token);
+	cmd_params = (struct dpni_cmd_get_qdid *)cmd.params;
+	cmd_params->qtype = qtype;
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -252,17 +391,26 @@ int dpni_get_qdid(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	DPNI_RSP_GET_QDID(cmd, *qdid);
+	rsp_params = (struct dpni_rsp_get_qdid *)cmd.params;
+	*qdid = le16_to_cpu(rsp_params->qdid);
 
 	return 0;
 }
 
-int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io,
-			    uint32_t cmd_flags,
-			    uint16_t token,
-			    uint16_t *data_offset)
+/**
+ * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer)
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @data_offset: Tx data offset (from start of buffer)
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			    u16 *data_offset)
 {
 	struct mc_command cmd = { 0 };
+	struct dpni_rsp_get_tx_data_offset *rsp_params;
 	int err;
 
 	/* prepare command */
@@ -276,34 +424,54 @@ int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	DPNI_RSP_GET_TX_DATA_OFFSET(cmd, *data_offset);
+	rsp_params = (struct dpni_rsp_get_tx_data_offset *)cmd.params;
+	*data_offset = le16_to_cpu(rsp_params->data_offset);
 
 	return 0;
 }
 
-int dpni_set_link_cfg(struct fsl_mc_io *mc_io,
-		      uint32_t cmd_flags,
-		      uint16_t token,
+/**
+ * dpni_set_link_cfg() - set the link configuration.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @cfg:	Link configuration
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_set_link_cfg(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
 		      const struct dpni_link_cfg *cfg)
 {
 	struct mc_command cmd = { 0 };
+	struct dpni_cmd_set_link_cfg *cmd_params;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_LINK_CFG,
 					  cmd_flags,
 					  token);
-	DPNI_CMD_SET_LINK_CFG(cmd, cfg);
+	cmd_params = (struct dpni_cmd_set_link_cfg *)cmd.params;
+	cmd_params->rate = cpu_to_le32(cfg->rate);
+	cmd_params->options = cpu_to_le64(cfg->options);
+	cmd_params->advertising = cpu_to_le64(cfg->advertising);
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpni_get_link_state(struct fsl_mc_io *mc_io,
-			uint32_t cmd_flags,
-			uint16_t token,
+/**
+ * dpni_get_link_state() - Return the link state (either up or down)
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @state:	Returned link state;
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_get_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
 			struct dpni_link_state *state)
 {
 	struct mc_command cmd = { 0 };
+	struct dpni_rsp_get_link_state *rsp_params;
 	int err;
 
 	/* prepare command */
@@ -317,211 +485,279 @@ int dpni_get_link_state(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	DPNI_RSP_GET_LINK_STATE(cmd, state);
-
-	return 0;
-}
-
-
-int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io,
-			      uint32_t cmd_flags,
-			      uint16_t token,
-			      const uint8_t mac_addr[6])
-{
-	struct mc_command cmd = { 0 };
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_PRIM_MAC,
-					  cmd_flags,
-					  token);
-	DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr);
-
-	/* send command to mc*/
-	return mc_send_command(mc_io, &cmd);
-}
-
-int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io,
-			      uint32_t cmd_flags,
-			      uint16_t token,
-			      uint8_t mac_addr[6])
-{
-	struct mc_command cmd = { 0 };
-	int err;
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_PRIM_MAC,
-					  cmd_flags,
-					  token);
-
-	/* send command to mc*/
-	err = mc_send_command(mc_io, &cmd);
-	if (err)
-		return err;
-
-	/* retrieve response parameters */
-	DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr);
+	rsp_params = (struct dpni_rsp_get_link_state *)cmd.params;
+	state->up = dpni_get_field(rsp_params->flags, LINK_STATE);
+	state->state_valid = dpni_get_field(rsp_params->flags, STATE_VALID);
+	state->rate = le32_to_cpu(rsp_params->rate);
+	state->options = le64_to_cpu(rsp_params->options);
+	state->supported = le64_to_cpu(rsp_params->supported);
+	state->advertising = le64_to_cpu(rsp_params->advertising);
 
 	return 0;
 }
 
-int dpni_add_mac_addr(struct fsl_mc_io *mc_io,
-		      uint32_t cmd_flags,
-		      uint16_t token,
-		      const uint8_t mac_addr[6])
+/**
+ * dpni_add_mac_addr() - Add MAC address filter
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @mac_addr:	MAC address to add
+ * @flags :0 - tc_id and flow_id will be ignored.
+ *				 Pkt with this mac_id will be passed to the next
+ *				 classification stages
+ *          DPNI_MAC_SET_QUEUE_ACTION
+ *				 Pkt with this mac will be forward directly to
+ *				 queue defined by the tc_id and flow_id
+ * @tc_id : Traffic class selection (0-7)
+ * @flow_id : Selects the specific queue out of the set allocated for the
+ *            same as tc_id. Value must be in range 0 to NUM_QUEUES - 1
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_add_mac_addr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		      const u8 mac_addr[6], u8 flags,
+		      u8 tc_id, u8 flow_id)
 {
+	struct dpni_cmd_add_mac_addr *cmd_params;
 	struct mc_command cmd = { 0 };
+	int i;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_MAC_ADDR,
 					  cmd_flags,
 					  token);
-	DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr);
+	cmd_params = (struct dpni_cmd_add_mac_addr *)cmd.params;
+	cmd_params->flags = flags;
+	cmd_params->tc_id = tc_id;
+	cmd_params->fq_id = flow_id;
 
-	/* send command to mc*/
-	return mc_send_command(mc_io, &cmd);
-}
-
-int dpni_remove_mac_addr(struct fsl_mc_io *mc_io,
-			 uint32_t cmd_flags,
-			 uint16_t token,
-			 const uint8_t mac_addr[6])
-{
-	struct mc_command cmd = { 0 };
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_MAC_ADDR,
-					  cmd_flags,
-					  token);
-	DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr);
+	for (i = 0; i < 6; i++)
+		cmd_params->mac_addr[i] = mac_addr[5 - i];
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpni_get_api_version(struct fsl_mc_io *mc_io,
-			 u32 cmd_flags,
-			 u16 *major_ver,
-			 u16 *minor_ver)
+/**
+ * dpni_get_api_version() - Get Data Path Network Interface API version
+ * @mc_io:  Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver:	Major version of data path network interface API
+ * @minor_ver:	Minor version of data path network interface API
+ *
+ * Return:  '0' on Success; Error code otherwise.
+ */
+int dpni_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+			 u16 *major_ver, u16 *minor_ver)
 {
 	struct mc_command cmd = { 0 };
 	int err;
 
-	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_API_VERSION,
-					  cmd_flags, 0);
+					cmd_flags,
+					0);
 
-	/* send command to mc */
 	err = mc_send_command(mc_io, &cmd);
 	if (err)
 		return err;
 
-	/* retrieve response parameters */
 	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
 
 	return 0;
 }
 
-int dpni_set_queue(struct fsl_mc_io *mc_io,
-	uint32_t cmd_flags,
-	uint16_t token,
-	enum dpni_queue_type type,
-	uint8_t tc,
-	uint8_t index,
-	const struct dpni_queue *queue)
+/**
+ * dpni_set_queue() - Set queue parameters
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @qtype:	Type of queue - all queue types are supported, although
+ *		the command is ignored for Tx
+ * @tc:		Traffic class, in range 0 to NUM_TCS - 1
+ * @index:	Selects the specific queue out of the set allocated for the
+ *		same TC. Value must be in range 0 to NUM_QUEUES - 1
+ * @options:	A combination of DPNI_QUEUE_OPT_ values that control what
+ *		configuration options are set on the queue
+ * @queue:	Queue structure
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_set_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		   enum dpni_queue_type qtype, u16 param, u8 index,
+		   u8 options, const struct dpni_queue *queue)
 {
 	struct mc_command cmd = { 0 };
+	struct dpni_cmd_set_queue *cmd_params;
+
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_QUEUE,
 					  cmd_flags,
 					  token);
-	DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue);
+	cmd_params = (struct dpni_cmd_set_queue *)cmd.params;
+	cmd_params->qtype = qtype;
+	cmd_params->tc = (u8)(param & 0xff);
+	cmd_params->channel_id = (u8)((param >> 8) & 0xff);
+	cmd_params->index = index;
+	cmd_params->options = options;
+	cmd_params->dest_id = cpu_to_le32(queue->destination.id);
+	cmd_params->dest_prio = queue->destination.priority;
+	dpni_set_field(cmd_params->flags, DEST_TYPE, queue->destination.type);
+	dpni_set_field(cmd_params->flags, STASH_CTRL, queue->flc.stash_control);
+	dpni_set_field(cmd_params->flags, HOLD_ACTIVE,
+		       queue->destination.hold_active);
+	cmd_params->flc = cpu_to_le64(queue->flc.value);
+	cmd_params->user_context = cpu_to_le64(queue->user_context);
+	cmd_params->cgid = queue->cgid;
 
-	/* send command to mc*/
+	/* send command to mc */
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpni_get_queue(struct fsl_mc_io *mc_io,
-	uint32_t cmd_flags,
-	uint16_t token,
-	enum dpni_queue_type type,
-	uint8_t tc,
-	uint8_t index,
-	struct dpni_queue *queue)
+/**
+ * dpni_get_queue() - Get queue parameters
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @qtype:	Type of queue - all queue types are supported
+ * @param:	Traffic class and channel ID.
+ *			MSB - channel id; used only for DPNI_QUEUE_TX and
+ *			DPNI_QUEUE_TX_CONFIRM, ignored for the rest
+ *			LSB - traffic class
+ *			Use macro DPNI_BUILD_PARAM() to build correct value.
+ *			If dpni uses a single channel (uses only channel zero)
+ *			the parameter can receive traffic class directly.
+ * @index:	Selects the specific queue out of the set allocated for the
+ *		same TC. Value must be in range 0 to NUM_QUEUES - 1
+ * @queue:	Queue configuration structure
+ * @qid:	Queue identification
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_get_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		   enum dpni_queue_type qtype, u16 param, u8 index,
+		   struct dpni_queue *queue, struct dpni_queue_id *qid)
 {
 	struct mc_command cmd = { 0 };
+	struct dpni_cmd_get_queue *cmd_params;
+	struct dpni_rsp_get_queue *rsp_params;
 	int err;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QUEUE,
 					  cmd_flags,
 					  token);
-	DPNI_CMD_GET_QUEUE(cmd, type, tc, index);
+	cmd_params = (struct dpni_cmd_get_queue *)cmd.params;
+	cmd_params->qtype = qtype;
+	cmd_params->tc = (u8)(param & 0xff);
+	cmd_params->index = index;
+	cmd_params->channel_id = (u8)((param >> 8) & 0xff);
 
-	/* send command to mc*/
+	/* send command to mc */
 	err = mc_send_command(mc_io, &cmd);
 	if (err)
 		return err;
 
 	/* retrieve response parameters */
-	DPNI_RSP_GET_QUEUE(cmd, queue);
+	rsp_params = (struct dpni_rsp_get_queue *)cmd.params;
+	queue->destination.id = le32_to_cpu(rsp_params->dest_id);
+	queue->destination.priority = rsp_params->dest_prio;
+	queue->destination.type = dpni_get_field(rsp_params->flags, DEST_TYPE);
+	queue->flc.stash_control = dpni_get_field(rsp_params->flags, STASH_CTRL);
+	queue->destination.hold_active = dpni_get_field(rsp_params->flags, HOLD_ACTIVE);
+	queue->flc.value = le64_to_cpu(rsp_params->flc);
+	queue->user_context = le64_to_cpu(rsp_params->user_context);
+	qid->fqid = le32_to_cpu(rsp_params->fqid);
+	qid->qdbin = le16_to_cpu(rsp_params->qdbin);
+	if (dpni_get_field(rsp_params->flags, CGID_VALID))
+		queue->cgid = rsp_params->cgid;
+	else
+		queue->cgid = -1;
+
 	return 0;
 }
 
-int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io,
-	uint32_t cmd_flags,
-	uint16_t token,
-	enum dpni_confirmation_mode mode)
+/**
+ * dpni_set_tx_confirmation_mode() - Tx confirmation mode
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @ceetm_ch_idx:	ceetm channel index
+ * @mode:	Tx confirmation mode
+ *
+ * This function is useful only when 'DPNI_OPT_TX_CONF_DISABLED' is not
+ * selected at DPNI creation.
+ * Calling this function with 'mode' set to DPNI_CONF_DISABLE disables all
+ * transmit confirmation (including the private confirmation queues), regardless
+ * of previous settings; Note that in this case, Tx error frames are still
+ * enqueued to the general transmit errors queue.
+ * Calling this function with 'mode' set to DPNI_CONF_SINGLE switches all
+ * Tx confirmations to a shared Tx conf queue. 'index' field in dpni_get_queue
+ * command will be ignored.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+				  u8 ceetm_ch_idx, enum dpni_confirmation_mode mode)
 {
 	struct dpni_tx_confirmation_mode *cmd_params;
 	struct mc_command cmd = { 0 };
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONFIRMATION_MODE,
-					  cmd_flags,
-					  token);
-
+					  cmd_flags, token);
 	cmd_params = (struct dpni_tx_confirmation_mode *)cmd.params;
+	cmd_params->ceetm_ch_idx = ceetm_ch_idx;
 	cmd_params->confirmation_mode = mode;
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpni_get_statistics(struct fsl_mc_io *mc_io,
-			uint32_t cmd_flags,
-			uint16_t token,
-			uint8_t  page,
-			struct dpni_statistics *stat)
+/**
+ * dpni_get_statistics() - Get DPNI statistics
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @page:	Selects the statistics page to retrieve, see
+ *		DPNI_GET_STATISTICS output. Pages are numbered 0 to 6.
+ * @param:  Custom parameter for some pages used to select
+ *		 a certain statistic source, for example the TC.
+ *		 - page_0: not used
+ *		 - page_1: not used
+ *		 - page_2: not used
+ *		 - page_3: high_byte - channel_id, low_byte - traffic class
+ *		 - page_4: high_byte - queue_index have meaning only if dpni is
+ *		 created using option DPNI_OPT_CUSTOM_CG, low_byte - traffic class
+ *		 - page_5: not used
+ *		 - page_6: not used
+ * @stat:	Structure containing the statistics
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_get_statistics(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			u8 page, u16 param, union dpni_statistics *stat)
 {
+	struct dpni_cmd_get_statistics *cmd_params;
+	struct dpni_rsp_get_statistics *rsp_params;
 	struct mc_command cmd = { 0 };
-	int err;
+	int i, err;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_STATISTICS,
-					  cmd_flags, token);
-	DPNI_CMD_GET_STATISTICS(cmd, page);
+					  cmd_flags,
+					  token);
+	cmd_params = (struct dpni_cmd_get_statistics *)cmd.params;
+	cmd_params->page_number = page;
+	cmd_params->param = param;
 
-	/* send command to mc*/
+	/* send command to mc */
 	err = mc_send_command(mc_io, &cmd);
 	if (err)
 		return err;
 
 	/* retrieve response parameters */
-	DPNI_RSP_GET_STATISTICS(cmd, stat);
+	rsp_params = (struct dpni_rsp_get_statistics *)cmd.params;
+	for (i = 0; i < DPNI_STATISTICS_CNT; i++)
+		stat->raw.counter[i] = le64_to_cpu(rsp_params->counter[i]);
 
 	return 0;
 }
-
-int dpni_reset_statistics(struct fsl_mc_io *mc_io,
-			  uint32_t cmd_flags,
-			  uint16_t token)
-{
-	struct mc_command cmd = { 0 };
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET_STATISTICS,
-					  cmd_flags, token);
-
-	/* send command to mc*/
-	return mc_send_command(mc_io, &cmd);
-}
diff --git a/drivers/net/fsl-mc/dprc.c b/drivers/net/fsl-mc/dprc.c
index e0a2865ab8..d1a74ab47a 100644
--- a/drivers/net/fsl-mc/dprc.c
+++ b/drivers/net/fsl-mc/dprc.c
@@ -3,16 +3,22 @@
  * Freescale Layerscape MC I/O wrapper
  *
  * Copyright 2013-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017, 2023 NXP
  */
 
 #include <fsl-mc/fsl_mc_sys.h>
 #include <fsl-mc/fsl_mc_cmd.h>
 #include <fsl-mc/fsl_dprc.h>
 
-int dprc_get_container_id(struct fsl_mc_io *mc_io,
-			  uint32_t cmd_flags,
-			  int *container_id)
+/**
+ * dprc_get_container_id - Get container ID associated with a given portal.
+ * @mc_io:		Pointer to Mc portal's I/O object
+ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
+ * @container_id:	Requested container id
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_get_container_id(struct fsl_mc_io *mc_io, u32 cmd_flags, int *container_id)
 {
 	struct mc_command cmd = { 0 };
 	int err;
@@ -28,23 +34,33 @@ int dprc_get_container_id(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	DPRC_RSP_GET_CONTAINER_ID(cmd, *container_id);
+	*container_id = (int)mc_cmd_read_object_id(&cmd);
 
 	return 0;
 }
 
-int dprc_open(struct fsl_mc_io *mc_io,
-	      uint32_t cmd_flags,
-	      int container_id,
-	      uint16_t *token)
+/**
+ * dprc_open() - Open DPRC object for use
+ * @mc_io:		Pointer to MC portal's I/O object
+ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
+ * @container_id:	Container ID to open
+ * @token:		Returned token of DPRC object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ *
+ * @warning	Required before any operation on the object.
+ */
+int dprc_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int container_id, u16 *token)
 {
+	struct dprc_cmd_open *cmd_params;
 	struct mc_command cmd = { 0 };
 	int err;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPRC_CMDID_OPEN, cmd_flags,
 					  0);
-	DPRC_CMD_OPEN(cmd, container_id);
+	cmd_params = (struct dprc_cmd_open *)cmd.params;
+	cmd_params->container_id = cpu_to_le32(container_id);
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -52,14 +68,23 @@ int dprc_open(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+	*token = mc_cmd_hdr_read_token(&cmd);
 
 	return 0;
 }
 
-int dprc_close(struct fsl_mc_io *mc_io,
-	       uint32_t cmd_flags,
-	       uint16_t token)
+/**
+ * dprc_close() - Close the control session of the object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
@@ -71,22 +96,35 @@ int dprc_close(struct fsl_mc_io *mc_io,
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dprc_create_container(struct fsl_mc_io *mc_io,
-			  uint32_t cmd_flags,
-			  uint16_t token,
-			  struct dprc_cfg *cfg,
-			  int *child_container_id,
-			  uint64_t *child_portal_paddr)
+/**
+ * dprc_create_container() - Create child container
+ * @mc_io:		Pointer to MC portal's I/O object
+ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:		Token of DPRC object
+ * @cfg:		Child container configuration
+ * @child_container_id:	Returned child container ID
+ * @child_portal_offset:Returned child portal offset from MC portal base
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_create_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			  struct dprc_cfg *cfg, int *child_container_id,
+			  uint64_t *child_portal_offset)
 {
+	struct dprc_cmd_create_container *cmd_params;
+	struct dprc_rsp_create_container *rsp_params;
 	struct mc_command cmd = { 0 };
-	int err;
+	int err, i;
 
 	/* prepare command */
-	DPRC_CMD_CREATE_CONTAINER(cmd, cfg);
-
 	cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT,
-					  cmd_flags,
-					  token);
+					  cmd_flags, token);
+	cmd_params = (struct dprc_cmd_create_container *)cmd.params;
+	cmd_params->options = cpu_to_le32(cfg->options);
+	cmd_params->icid = cpu_to_le32(cfg->icid);
+	cmd_params->portal_id = cpu_to_le32(cfg->portal_id);
+	for (i = 0; i < 16; i++)
+		cmd_params->label[i] = cfg->label[i];
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -94,253 +132,156 @@ int dprc_create_container(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	DPRC_RSP_CREATE_CONTAINER(cmd, *child_container_id,
-				  *child_portal_paddr);
+	rsp_params = (struct dprc_rsp_create_container *)cmd.params;
+	*child_container_id = le32_to_cpu(rsp_params->child_container_id);
+	*child_portal_offset = le64_to_cpu(rsp_params->child_portal_addr);
 
 	return 0;
 }
 
-int dprc_destroy_container(struct fsl_mc_io *mc_io,
-			   uint32_t cmd_flags,
-			   uint16_t token,
+/**
+ * dprc_destroy_container() - Destroy child container.
+ * @mc_io:		Pointer to MC portal's I/O object
+ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:		Token of DPRC object
+ * @child_container_id:	ID of the container to destroy
+ *
+ * This function terminates the child container, so following this call the
+ * child container ID becomes invalid.
+ *
+ * Notes:
+ * - All resources and objects of the destroyed container are returned to the
+ * parent container or destroyed if were created be the destroyed container.
+ * - This function destroy all the child containers of the specified
+ *   container prior to destroying the container itself.
+ *
+ * warning: Only the parent container is allowed to destroy a child policy
+ *		Container 0 can't be destroyed
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ *
+ */
+int dprc_destroy_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
 			   int child_container_id)
 {
+	struct dprc_cmd_destroy_container *cmd_params;
 	struct mc_command cmd = { 0 };
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT,
-					  cmd_flags,
-					  token);
-	DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id);
+					  cmd_flags, token);
+	cmd_params = (struct dprc_cmd_destroy_container *)cmd.params;
+	cmd_params->child_container_id = cpu_to_le32(child_container_id);
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dprc_reset_container(struct fsl_mc_io *mc_io,
-			 uint32_t cmd_flags,
-			 uint16_t token,
-			 int child_container_id)
-{
-	struct mc_command cmd = { 0 };
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_RESET_CONT,
-					  cmd_flags,
-					  token);
-	DPRC_CMD_RESET_CONTAINER(cmd, child_container_id);
-
-	/* send command to mc*/
-	return mc_send_command(mc_io, &cmd);
-}
-
-int dprc_get_attributes(struct fsl_mc_io *mc_io,
-			uint32_t cmd_flags,
-			uint16_t token,
-			struct dprc_attributes *attr)
-{
-	struct mc_command cmd = { 0 };
-	int err;
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_ATTR,
-					  cmd_flags,
-					  token);
-
-	/* send command to mc*/
-	err = mc_send_command(mc_io, &cmd);
-	if (err)
-		return err;
-
-	/* retrieve response parameters */
-	DPRC_RSP_GET_ATTRIBUTES(cmd, attr);
-
-	return 0;
-}
-
-int dprc_get_obj_count(struct fsl_mc_io *mc_io,
-		       uint32_t cmd_flags,
-		       uint16_t token,
-		       int *obj_count)
-{
-	struct mc_command cmd = { 0 };
-	int err;
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_COUNT,
-					  cmd_flags,
-					  token);
-
-	/* send command to mc*/
-	err = mc_send_command(mc_io, &cmd);
-	if (err)
-		return err;
-
-	/* retrieve response parameters */
-	DPRC_RSP_GET_OBJ_COUNT(cmd, *obj_count);
-
-	return 0;
-}
-
-int dprc_get_obj(struct fsl_mc_io *mc_io,
-		 uint32_t cmd_flags,
-		 uint16_t token,
-		 int obj_index,
-		 struct dprc_obj_desc *obj_desc)
-{
-	struct mc_command cmd = { 0 };
-	int err;
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ,
-					  cmd_flags,
-					  token);
-	DPRC_CMD_GET_OBJ(cmd, obj_index);
-
-	/* send command to mc*/
-	err = mc_send_command(mc_io, &cmd);
-	if (err)
-		return err;
-
-	/* retrieve response parameters */
-	DPRC_RSP_GET_OBJ(cmd, obj_desc);
-
-	return 0;
-}
-
-int dprc_get_res_count(struct fsl_mc_io *mc_io,
-		       uint32_t cmd_flags,
-		       uint16_t token,
-		       char *type,
-		       int *res_count)
-{
-	struct mc_command cmd = { 0 };
-	int err;
-
-	*res_count = 0;
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_COUNT,
-					  cmd_flags,
-					  token);
-	DPRC_CMD_GET_RES_COUNT(cmd, type);
-
-	/* send command to mc*/
-	err = mc_send_command(mc_io, &cmd);
-	if (err)
-		return err;
-
-	/* retrieve response parameters */
-	DPRC_RSP_GET_RES_COUNT(cmd, *res_count);
-
-	return 0;
-}
-
-int dprc_get_res_ids(struct fsl_mc_io *mc_io,
-		     uint32_t cmd_flags,
-		     uint16_t token,
-		     char *type,
-		     struct dprc_res_ids_range_desc *range_desc)
-{
-	struct mc_command cmd = { 0 };
-	int err;
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_IDS,
-					  cmd_flags,
-					  token);
-	DPRC_CMD_GET_RES_IDS(cmd, range_desc, type);
-
-	/* send command to mc*/
-	err = mc_send_command(mc_io, &cmd);
-	if (err)
-		return err;
-
-	/* retrieve response parameters */
-	DPRC_RSP_GET_RES_IDS(cmd, range_desc);
-
-	return 0;
-}
-
-int dprc_get_obj_region(struct fsl_mc_io *mc_io,
-			uint32_t cmd_flags,
-			uint16_t token,
-			char *obj_type,
-			int obj_id,
-			uint8_t region_index,
-			struct dprc_region_desc *region_desc)
-{
-	struct mc_command cmd = { 0 };
-	int err;
-
-	/* prepare command */
-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_REG,
-					  cmd_flags,
-					  token);
-	DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index);
-
-	/* send command to mc*/
-	err = mc_send_command(mc_io, &cmd);
-	if (err)
-		return err;
-
-	/* retrieve response parameters */
-	DPRC_RSP_GET_OBJ_REGION(cmd, region_desc);
-
-	return 0;
-}
-
-int dprc_connect(struct fsl_mc_io *mc_io,
-		 uint32_t cmd_flags,
-		 uint16_t token,
+/**
+ * dprc_connect() - Connect two endpoints to create a network link between them
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @endpoint1:	Endpoint 1 configuration parameters
+ * @endpoint2:	Endpoint 2 configuration parameters
+ * @cfg:	Connection configuration. The connection configuration
+ *		is ignored for connections made to DPMAC objects, where
+ *		rate is retrieved from the MAC configuration.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_connect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
 		 const struct dprc_endpoint *endpoint1,
 		 const struct dprc_endpoint *endpoint2,
 		 const struct dprc_connection_cfg *cfg)
 {
+	struct dprc_cmd_connect *cmd_params;
 	struct mc_command cmd = { 0 };
+	int i;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPRC_CMDID_CONNECT,
 					  cmd_flags,
 					  token);
-	DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg);
+	cmd_params = (struct dprc_cmd_connect *)cmd.params;
+	cmd_params->ep1_id = cpu_to_le32(endpoint1->id);
+	cmd_params->ep1_interface_id = cpu_to_le16(endpoint1->if_id);
+	cmd_params->ep2_id = cpu_to_le32(endpoint2->id);
+	cmd_params->ep2_interface_id = cpu_to_le16(endpoint2->if_id);
+	cmd_params->max_rate = cpu_to_le32(cfg->max_rate);
+	cmd_params->committed_rate = cpu_to_le32(cfg->committed_rate);
+	for (i = 0; i < 16; i++) {
+		cmd_params->ep1_type[i] = endpoint1->type[i];
+		cmd_params->ep2_type[i] = endpoint2->type[i];
+	}
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dprc_disconnect(struct fsl_mc_io *mc_io,
-		    uint32_t cmd_flags,
-		    uint16_t token,
+/**
+ * dprc_disconnect() - Disconnect one endpoint to remove its network connection
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @endpoint:	Endpoint configuration parameters
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_disconnect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
 		    const struct dprc_endpoint *endpoint)
 {
+	struct dprc_cmd_disconnect *cmd_params;
 	struct mc_command cmd = { 0 };
+	int i;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPRC_CMDID_DISCONNECT,
 					  cmd_flags,
 					  token);
-	DPRC_CMD_DISCONNECT(cmd, endpoint);
+	cmd_params = (struct dprc_cmd_disconnect *)cmd.params;
+	cmd_params->id = cpu_to_le32(endpoint->id);
+	cmd_params->interface_id = cpu_to_le32(endpoint->if_id);
+	for (i = 0; i < 16; i++)
+		cmd_params->type[i] = endpoint->type[i];
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dprc_get_connection(struct fsl_mc_io *mc_io,
-			uint32_t cmd_flags,
-			uint16_t token,
+/**
+ * dprc_get_connection() - Get connected endpoint and link status if connection
+ *			exists.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @endpoint1:	Endpoint 1 configuration parameters
+ * @endpoint2:	Returned endpoint 2 configuration parameters
+ * @state:	Returned link state:
+ *		1 - link is up;
+ *		0 - link is down;
+ *		-1 - no connection (endpoint2 information is irrelevant)
+ *
+ * Return:     '0' on Success; -ENAVAIL if connection does not exist.
+ */
+int dprc_get_connection(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
 			const struct dprc_endpoint *endpoint1,
-			struct dprc_endpoint *endpoint2,
-			int *state)
+			struct dprc_endpoint *endpoint2, int *state)
 {
+	struct dprc_cmd_get_connection *cmd_params;
+	struct dprc_rsp_get_connection *rsp_params;
 	struct mc_command cmd = { 0 };
-	int err;
+	int err, i;
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONNECTION,
 					  cmd_flags,
 					  token);
-	DPRC_CMD_GET_CONNECTION(cmd, endpoint1);
+	cmd_params = (struct dprc_cmd_get_connection *)cmd.params;
+	cmd_params->ep1_id = cpu_to_le32(endpoint1->id);
+	cmd_params->ep1_interface_id = cpu_to_le16(endpoint1->if_id);
+	for (i = 0; i < 16; i++)
+		cmd_params->ep1_type[i] = endpoint1->type[i];
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -348,15 +289,27 @@ int dprc_get_connection(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	DPRC_RSP_GET_CONNECTION(cmd, endpoint2, *state);
+	rsp_params = (struct dprc_rsp_get_connection *)cmd.params;
+	endpoint2->id = le32_to_cpu(rsp_params->ep2_id);
+	endpoint2->if_id = le16_to_cpu(rsp_params->ep2_interface_id);
+	*state = le32_to_cpu(rsp_params->state);
+	for (i = 0; i < 16; i++)
+		endpoint2->type[i] = rsp_params->ep2_type[i];
 
 	return 0;
 }
 
-int dprc_get_api_version(struct fsl_mc_io *mc_io,
-			 u32 cmd_flags,
-			 u16 *major_ver,
-			 u16 *minor_ver)
+/**
+ * dprc_get_api_version - Get Data Path Resource Container API version
+ * @mc_io:	Pointer to Mc portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver:	Major version of Data Path Resource Container API
+ * @minor_ver:	Minor version of Data Path Resource Container API
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+			 u16 *major_ver, u16 *minor_ver)
 {
 	struct mc_command cmd = { 0 };
 	int err;
diff --git a/drivers/net/fsl-mc/dpsparser.c b/drivers/net/fsl-mc/dpsparser.c
index cfd1ba66a0..09dfb8f1fc 100644
--- a/drivers/net/fsl-mc/dpsparser.c
+++ b/drivers/net/fsl-mc/dpsparser.c
@@ -2,15 +2,29 @@
 /*
  * Data Path Soft Parser
  *
- * Copyright 2018 NXP
+ * Copyright 2018, 2023 NXP
  */
 #include <fsl-mc/fsl_mc_sys.h>
 #include <fsl-mc/fsl_mc_cmd.h>
 #include <fsl-mc/fsl_dpsparser.h>
 
-int dpsparser_open(struct fsl_mc_io *mc_io,
-		   u32 cmd_flags,
-		   u16 *token)
+/**
+ * dpsparser_open() - Open a control session for the specified object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpsparser_create function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpsparser_open(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 *token)
 {
 	struct mc_command cmd = { 0 };
 	int err;
@@ -26,14 +40,23 @@ int dpsparser_open(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+	*token = mc_cmd_hdr_read_token(&cmd);
 
 	return err;
 }
 
-int dpsparser_close(struct fsl_mc_io *mc_io,
-		    u32 cmd_flags,
-		    u16 token)
+/**
+ * dpsparser_close() - Close the control session of the object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPSPARSER object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpsparser_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
 {
 	struct mc_command cmd = { 0 };
 
@@ -45,9 +68,27 @@ int dpsparser_close(struct fsl_mc_io *mc_io,
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpsparser_create(struct fsl_mc_io *mc_io,
-		     u16 token,
-		     u32 cmd_flags,
+/**
+ * dpsparser_create() - Create the DPSPARSER object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Returned token; use in subsequent API calls
+ *
+ * Create the DPSPARSER object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpsparser_open function to get an authentication
+ * token first.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpsparser_create(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags,
 		     u32 *obj_id)
 {
 	struct mc_command cmd = { 0 };
@@ -64,36 +105,51 @@ int dpsparser_create(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters */
-	MC_CMD_READ_OBJ_ID(cmd, *obj_id);
+	*obj_id = mc_cmd_read_object_id(&cmd);
 
 	return 0;
 }
 
-int dpsparser_destroy(struct fsl_mc_io *mc_io,
-		      u16 token,
-		      u32 cmd_flags,
+/**
+ * dpsparser_destroy() - Destroy the DPSPARSER object and release all its resources.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPSPARSER object
+ *
+ * Return:	'0' on Success; error code otherwise.
+ */
+int dpsparser_destroy(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags,
 		      u32 obj_id)
 {
+	struct dpsparser_cmd_destroy *cmd_params;
 	struct mc_command cmd = { 0 };
 
 	/* prepare command */
 	cmd.header = mc_encode_cmd_header(DPSPARSER_CMDID_DESTROY,
 					  cmd_flags,
 					  token);
-
-	/* set object id to destroy */
-	CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
+	cmd_params = (struct dpsparser_cmd_destroy *)cmd.params;
+	cmd_params->dpsparser_id = cpu_to_le32(obj_id);
 
 	/* send command to mc*/
 	return mc_send_command(mc_io, &cmd);
 }
 
-int dpsparser_apply_spb(struct fsl_mc_io *mc_io,
-			u32 cmd_flags,
-			u16 token,
-			u64 blob_addr,
-			u16 *error)
+/**
+ * dpsparser_apply_spb() - Applies the Soft Parser Blob loaded at specified address.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPSPARSER object
+ * @blob_addr:	Blob loading address
+ * @error: Error reported by MC related to SP Blob parsing and apply
+ *
+ * Return:	'0' on Success; error code otherwise.
+ */
+int dpsparser_apply_spb(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			u64 blob_addr, u16 *error)
 {
+	struct dpsparser_rsp_blob_report_error *rsp_params;
+	struct dpsparser_cmd_blob_set_address *cmd_params;
 	struct mc_command cmd = { 0 };
 	int err;
 
@@ -101,7 +157,8 @@ int dpsparser_apply_spb(struct fsl_mc_io *mc_io,
 	cmd.header = mc_encode_cmd_header(DPSPARSER_CMDID_APPLY_SPB,
 					  cmd_flags,
 					  token);
-	DPSPARSER_CMD_BLOB_SET_ADDR(cmd, blob_addr);
+	cmd_params = (struct dpsparser_cmd_blob_set_address *)cmd.params;
+	cmd_params->blob_addr = cpu_to_le64(blob_addr);
 
 	/* send command to mc*/
 	err = mc_send_command(mc_io, &cmd);
@@ -109,15 +166,24 @@ int dpsparser_apply_spb(struct fsl_mc_io *mc_io,
 		return err;
 
 	/* retrieve response parameters: MC error code */
-	DPSPARSER_CMD_BLOB_REPORT_ERROR(cmd, *error);
+	rsp_params = (struct dpsparser_rsp_blob_report_error *)cmd.params;
+	*error = le16_to_cpu(rsp_params->error);
 
 	return 0;
 }
 
-int dpsparser_get_api_version(struct fsl_mc_io *mc_io,
-			      u32 cmd_flags,
-			      u16 *major_ver,
-			      u16 *minor_ver)
+/**
+ * dpsparser_get_api_version - Retrieve DPSPARSER Major and Minor version info.
+ *
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver:	DPSPARSER major version
+ * @minor_ver:	DPSPARSER minor version
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpsparser_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+			      u16 *major_ver, u16 *minor_ver)
 {
 	struct mc_command cmd = { 0 };
 	int err;
diff --git a/drivers/net/fsl-mc/fsl_dpmng_cmd.h b/drivers/net/fsl-mc/fsl_dpmng_cmd.h
index e18c88da09..e6efceab7a 100644
--- a/drivers/net/fsl-mc/fsl_dpmng_cmd.h
+++ b/drivers/net/fsl-mc/fsl_dpmng_cmd.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /* Copyright 2013-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017, 2023 NXP
  */
 #ifndef __FSL_DPMNG_CMD_H
 #define __FSL_DPMNG_CMD_H
@@ -8,12 +8,13 @@
 /* Command IDs */
 #define DPMNG_CMDID_GET_VERSION			0x8311
 
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \
-do { \
-	MC_RSP_OP(cmd, 0, 0,  32, uint32_t, mc_ver_info->revision); \
-	MC_RSP_OP(cmd, 0, 32, 32, uint32_t, mc_ver_info->major); \
-	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, mc_ver_info->minor); \
-} while (0)
+#pragma pack(push, 1)
+struct dpmng_rsp_get_version {
+	__le32 revision;
+	__le32 version_major;
+	__le32 version_minor;
+};
+
+#pragma pack(pop)
 
 #endif /* __FSL_DPMNG_CMD_H */
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 78a40f285a..984616fb65 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -1353,10 +1353,9 @@ err:
 
 static int dpni_init(void)
 {
-	int err;
-	uint8_t	cfg_buf[256] = {0};
-	struct dpni_cfg dpni_cfg;
+	struct dpni_cfg dpni_cfg = {0};
 	uint16_t major_ver, minor_ver;
+	int err;
 
 	dflt_dpni = calloc(sizeof(struct fsl_dpni_obj), 1);
 	if (!dflt_dpni) {
@@ -1365,14 +1364,6 @@ static int dpni_init(void)
 		goto err_calloc;
 	}
 
-	memset(&dpni_cfg, 0, sizeof(dpni_cfg));
-	err = dpni_prepare_cfg(&dpni_cfg, &cfg_buf[0]);
-	if (err < 0) {
-		err = -ENODEV;
-		printf("dpni_prepare_cfg() failed: %d\n", err);
-		goto err_prepare_cfg;
-	}
-
 	err = dpni_create(dflt_mc_io,
 			  dflt_dprc_handle,
 			  MC_CMD_NO_FLAGS,
@@ -1429,7 +1420,6 @@ err_get_version:
 		     MC_CMD_NO_FLAGS,
 		     dflt_dpni->dpni_id);
 err_create:
-err_prepare_cfg:
 	free(dflt_dpni);
 err_calloc:
 	return err;
diff --git a/drivers/net/fsl-mc/mc_sys.c b/drivers/net/fsl-mc/mc_sys.c
index b5ae2ea3eb..4d32516b00 100644
--- a/drivers/net/fsl-mc/mc_sys.c
+++ b/drivers/net/fsl-mc/mc_sys.c
@@ -13,8 +13,13 @@
 #include <asm/io.h>
 #include <linux/delay.h>
 
-#define MC_CMD_HDR_READ_CMDID(_hdr) \
-	((uint16_t)mc_dec((_hdr), MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S))
+static u16 mc_cmd_hdr_read_cmdid(struct mc_command *cmd)
+{
+	struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
+	u16 cmd_id = le16_to_cpu(hdr->cmd_id);
+
+	return cmd_id;
+}
 
 /**
  * mc_send_command - Send MC command and wait for response
@@ -52,8 +57,8 @@ int mc_send_command(struct fsl_mc_io *mc_io,
 	if (status != MC_CMD_STATUS_OK) {
 		printf("Error: MC command failed (portal: %p, obj handle: %#x, command: %#x, status: %#x)\n",
 		       mc_io->mmio_regs,
-			(unsigned int)MC_CMD_HDR_READ_TOKEN(cmd->header),
-		       (unsigned int)MC_CMD_HDR_READ_CMDID(cmd->header),
+			(unsigned int)mc_cmd_hdr_read_token(cmd),
+		       (unsigned int)mc_cmd_hdr_read_cmdid(cmd),
 		       (unsigned int)status);
 
 		return -EIO;
diff --git a/drivers/net/ksz9477.c b/drivers/net/ksz9477.c
index 6b59b5fcd2..43baa69961 100644
--- a/drivers/net/ksz9477.c
+++ b/drivers/net/ksz9477.c
@@ -16,6 +16,10 @@
 
 #include <asm-generic/gpio.h>
 
+/* Used with variable features to indicate capabilities. */
+#define NEW_XMII			BIT(1)
+#define IS_9893				BIT(2)
+
 /* Global registers */
 
 /* Chip ID */
@@ -41,6 +45,13 @@
 #define PORT_RMII_SEL			0x1
 #define PORT_GMII_SEL			0x2
 #define PORT_MII_SEL			0x3
+/* S1 */
+#define PORT_MII_1000MBIT_S1		BIT(6)
+/* S1 */
+#define PORT_MII_SEL_S1			0x0
+#define PORT_RMII_SEL_S1		0x1
+#define PORT_GMII_SEL_S1		0x2
+#define PORT_RGMII_SEL_S1		0x3
 
 /* Port MSTP State Register */
 #define REG_PORT_MSTP_STATE		0x0b04
@@ -62,6 +73,8 @@
 
 struct ksz_dsa_priv {
 	struct udevice *dev;
+
+	u32 features;			/* chip specific features */
 };
 
 static inline int ksz_read8(struct udevice *dev, u32 reg, u8 *val)
@@ -284,6 +297,60 @@ U_BOOT_DRIVER(ksz_mdio) = {
 	.plat_auto	= sizeof(struct mdio_perdev_priv),
 };
 
+static void ksz9477_set_gbit(struct ksz_dsa_priv *priv, bool gbit, u8 *data)
+{
+	if (priv->features & NEW_XMII) {
+		if (gbit)
+			*data &= ~PORT_MII_NOT_1GBIT;
+		else
+			*data |= PORT_MII_NOT_1GBIT;
+	} else {
+		if (gbit)
+			*data |= PORT_MII_1000MBIT_S1;
+		else
+			*data &= ~PORT_MII_1000MBIT_S1;
+	}
+}
+
+static void ksz9477_set_xmii(struct ksz_dsa_priv *priv, int mode, u8 *data)
+{
+	u8 xmii;
+
+	if (priv->features & NEW_XMII) {
+		switch (mode) {
+		case 0:
+			xmii = PORT_MII_SEL;
+			break;
+		case 1:
+			xmii = PORT_RMII_SEL;
+			break;
+		case 2:
+			xmii = PORT_GMII_SEL;
+			break;
+		default:
+			xmii = PORT_RGMII_SEL;
+			break;
+		}
+	} else {
+		switch (mode) {
+		case 0:
+			xmii = PORT_MII_SEL_S1;
+			break;
+		case 1:
+			xmii = PORT_RMII_SEL_S1;
+			break;
+		case 2:
+			xmii = PORT_GMII_SEL_S1;
+			break;
+		default:
+			xmii = PORT_RGMII_SEL_S1;
+			break;
+		}
+	}
+	*data &= ~PORT_MII_SEL_M;
+	*data |= xmii;
+}
+
 static int ksz_port_setup(struct udevice *dev, int port,
 			  phy_interface_t interface)
 {
@@ -293,9 +360,11 @@ static int ksz_port_setup(struct udevice *dev, int port,
 	dev_dbg(dev, "%s P%d %s\n", __func__, port + 1,
 		(port == pdata->cpu_port) ? "cpu" : "");
 
+	struct ksz_dsa_priv *priv = dev_get_priv(dev);
 	if (port != pdata->cpu_port) {
-		/* phy port: config errata and leds */
-		ksz_phy_errata_setup(dev, port);
+		if (priv->features & NEW_XMII)
+			/* phy port: config errata and leds */
+			ksz_phy_errata_setup(dev, port);
 	} else {
 		/* cpu port: configure MAC interface mode */
 		ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
@@ -303,24 +372,20 @@ static int ksz_port_setup(struct udevice *dev, int port,
 			phy_string_for_interface(interface));
 		switch (interface) {
 		case PHY_INTERFACE_MODE_MII:
-			data8 &= ~PORT_MII_SEL_M;
-			data8 |= PORT_MII_SEL;
-			data8 |= PORT_MII_NOT_1GBIT;
+			ksz9477_set_xmii(priv, 0, &data8);
+			ksz9477_set_gbit(priv, false, &data8);
 			break;
 		case PHY_INTERFACE_MODE_RMII:
-			data8 &= ~PORT_MII_SEL_M;
-			data8 |= PORT_RMII_SEL;
-			data8 |= PORT_MII_NOT_1GBIT;
+			ksz9477_set_xmii(priv, 1, &data8);
+			ksz9477_set_gbit(priv, false, &data8);
 			break;
 		case PHY_INTERFACE_MODE_GMII:
-			data8 &= ~PORT_MII_SEL_M;
-			data8 |= PORT_GMII_SEL;
-			data8 &= ~PORT_MII_NOT_1GBIT;
+			ksz9477_set_xmii(priv, 2, &data8);
+			ksz9477_set_gbit(priv, true, &data8);
 			break;
 		default:
-			data8 &= ~PORT_MII_SEL_M;
-			data8 |= PORT_RGMII_SEL;
-			data8 &= ~PORT_MII_NOT_1GBIT;
+			ksz9477_set_xmii(priv, 3, &data8);
+			ksz9477_set_gbit(priv, true, &data8);
 			data8 &= ~PORT_RGMII_ID_IG_ENABLE;
 			data8 &= ~PORT_RGMII_ID_EG_ENABLE;
 			if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
@@ -329,6 +394,8 @@ static int ksz_port_setup(struct udevice *dev, int port,
 			if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
 			    interface == PHY_INTERFACE_MODE_RGMII_TXID)
 				data8 |= PORT_RGMII_ID_EG_ENABLE;
+			if (priv->features & IS_9893)
+				data8 &= ~PORT_MII_MAC_MODE;
 			break;
 		}
 		ksz_write8(dev, PORT_CTRL_ADDR(port, REG_PORT_XMII_CTRL_1), data8);
@@ -479,10 +546,17 @@ static int ksz_i2c_probe(struct udevice *dev)
 	case 0x00989700:
 		puts("KSZ9897S: ");
 		break;
+	case 0x00989300:
+		puts("KSZ9893R: ");
+		break;
 	default:
 		dev_err(dev, "invalid chip id: 0x%08x\n", id);
 		return -EINVAL;
 	}
+	if ((id & 0xf00) == 0x300)
+		priv->features |= IS_9893;
+	else
+		priv->features |= NEW_XMII;
 
 	/* probe mdio bus */
 	ret = ksz_probe_mdio(dev);
@@ -503,6 +577,7 @@ static const struct udevice_id ksz_i2c_ids[] = {
 	{ .compatible = "microchip,ksz9897" },
 	{ .compatible = "microchip,ksz9477" },
 	{ .compatible = "microchip,ksz9567" },
+	{ .compatible = "microchip,ksz9893" },
 	{ }
 };
 
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 2cb6e9b7d7..87fbada06b 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -38,146 +38,90 @@ static void init_phy(struct udevice *dev)
 }
 #endif
 
-#ifdef DEBUG
-
-#define DPNI_STATS_PER_PAGE 6
-
-static const char *dpni_statistics[][DPNI_STATS_PER_PAGE] = {
-	{
-	"DPNI_CNT_ING_ALL_FRAMES",
-	"DPNI_CNT_ING_ALL_BYTES",
-	"DPNI_CNT_ING_MCAST_FRAMES",
-	"DPNI_CNT_ING_MCAST_BYTES",
-	"DPNI_CNT_ING_BCAST_FRAMES",
-	"DPNI_CNT_ING_BCAST_BYTES",
-	}, {
-	"DPNI_CNT_EGR_ALL_FRAMES",
-	"DPNI_CNT_EGR_ALL_BYTES",
-	"DPNI_CNT_EGR_MCAST_FRAMES",
-	"DPNI_CNT_EGR_MCAST_BYTES",
-	"DPNI_CNT_EGR_BCAST_FRAMES",
-	"DPNI_CNT_EGR_BCAST_BYTES",
-	}, {
-	"DPNI_CNT_ING_FILTERED_FRAMES",
-	"DPNI_CNT_ING_DISCARDED_FRAMES",
-	"DPNI_CNT_ING_NOBUFFER_DISCARDS",
-	"DPNI_CNT_EGR_DISCARDED_FRAMES",
-	"DPNI_CNT_EGR_CNF_FRAMES",
-	""
-	},
-};
-
-static void print_dpni_stats(const char *strings[],
-			     struct dpni_statistics dpni_stats)
+static void ldpaa_eth_collect_dpni_stats(struct udevice *dev, u64 *data)
 {
-	uint64_t *stat;
-	int i;
+	union dpni_statistics dpni_stats;
+	int dpni_stats_page_size[DPNI_STATISTICS_CNT] = {
+		sizeof(dpni_stats.page_0),
+		sizeof(dpni_stats.page_1),
+		sizeof(dpni_stats.page_2),
+		sizeof(dpni_stats.page_3),
+		sizeof(dpni_stats.page_4),
+		sizeof(dpni_stats.page_5),
+		sizeof(dpni_stats.page_6),
+	};
+	int j, k, num_cnt, err, i = 0;
 
-	stat = (uint64_t *)&dpni_stats;
-	for (i = 0; i < DPNI_STATS_PER_PAGE; i++) {
-		if (strcmp(strings[i], "\0") == 0)
-			break;
-		printf("%s= %llu\n", strings[i], *stat);
-		stat++;
+	for (j = 0; j <= 6; j++) {
+		/* We're not interested in pages 4 & 5 for now */
+		if (j == 4 || j == 5)
+			continue;
+		err = dpni_get_statistics(dflt_mc_io, MC_CMD_NO_FLAGS,
+					  dflt_dpni->dpni_handle,
+					  j, 0, &dpni_stats);
+		if (err) {
+			memset(&dpni_stats, 0, sizeof(dpni_stats));
+			printf("dpni_get_stats(%d) failed\n", j);
+		}
+
+		num_cnt = dpni_stats_page_size[j] / sizeof(u64);
+		for (k = 0; k < num_cnt; k++)
+			*(data + i++) = dpni_stats.raw.counter[k];
 	}
 }
 
-static void ldpaa_eth_get_dpni_counter(void)
+static void ldpaa_eth_add_dpni_stats(struct udevice *dev, u64 *data)
 {
-	int err = 0;
-	unsigned int page = 0;
-	struct dpni_statistics dpni_stats;
+	struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+	int i;
 
-	printf("DPNI counters ..\n");
-	for (page = 0; page < 3; page++) {
-		err = dpni_get_statistics(dflt_mc_io, MC_CMD_NO_FLAGS,
-					  dflt_dpni->dpni_handle, page,
-					  &dpni_stats);
-		if (err < 0) {
-			printf("dpni_get_statistics: failed:");
-			printf("%d for page[%d]\n", err, page);
-			return;
-		}
-		print_dpni_stats(dpni_statistics[page], dpni_stats);
-	}
+	for (i = 0; i < LDPAA_ETH_DPNI_NUM_STATS; i++)
+		priv->dpni_stats[i] += data[i];
 }
 
-static void ldpaa_eth_get_dpmac_counter(struct udevice *dev)
+static void ldpaa_eth_collect_dpmac_stats(struct udevice *dev, u64 *data)
 {
 	struct ldpaa_eth_priv *priv = dev_get_priv(dev);
-	int err = 0;
+	int err, i;
 	u64 value;
 
-	err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
-		     priv->dpmac_handle,
-		     DPMAC_CNT_ING_BYTE,
-		     &value);
-	if (err < 0) {
-		printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n");
-		return;
-	}
-	printf("\nDPMAC counters ..\n");
-	printf("DPMAC_CNT_ING_BYTE=%lld\n", value);
+	for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++) {
+		err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+					priv->dpmac_handle, i,
+					&value);
+		if (err)
+			printf("dpmac_get_counter(%d) failed\n", i);
 
-	err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
-		     priv->dpmac_handle,
-		     DPMAC_CNT_ING_FRAME_DISCARD,
-		     &value);
-	if (err < 0) {
-		printf("dpmac_get_counter: DPMAC_CNT_ING_FRAME_DISCARD failed\n");
-		return;
+		*(data + i) = value;
 	}
-	printf("DPMAC_CNT_ING_FRAME_DISCARD=%lld\n", value);
+}
 
-	err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
-		     priv->dpmac_handle,
-		     DPMAC_CNT_ING_ALIGN_ERR,
-		     &value);
-	if (err < 0) {
-		printf("dpmac_get_counter: DPMAC_CNT_ING_ALIGN_ERR failed\n");
-		return;
-	}
-	printf("DPMAC_CNT_ING_ALIGN_ERR =%lld\n", value);
+static void ldpaa_eth_add_dpmac_stats(struct udevice *dev, u64 *data)
+{
+	struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+	int i;
 
-	err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
-		     priv->dpmac_handle,
-		     DPMAC_CNT_ING_BYTE,
-		     &value);
-	if (err < 0) {
-		printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n");
-		return;
-	}
-	printf("DPMAC_CNT_ING_BYTE=%lld\n", value);
+	for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++)
+		priv->dpmac_stats[i] += data[i];
+}
 
-	err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
-		     priv->dpmac_handle,
-		     DPMAC_CNT_ING_ERR_FRAME,
-		     &value);
-	if (err < 0) {
-		printf("dpmac_get_counter: DPMAC_CNT_ING_ERR_FRAME failed\n");
-		return;
-	}
-	printf("DPMAC_CNT_ING_ERR_FRAME=%lld\n", value);
+#ifdef DEBUG
+static void ldpaa_eth_dump_dpni_stats(struct udevice *dev, u64 *data)
+{
+	int i;
 
-	err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
-		     priv->dpmac_handle,
-		     DPMAC_CNT_EGR_BYTE ,
-		     &value);
-	if (err < 0) {
-		printf("dpmac_get_counter: DPMAC_CNT_EGR_BYTE failed\n");
-		return;
-	}
-	printf("DPMAC_CNT_EGR_BYTE =%lld\n", value);
+	printf("DPNI counters:\n");
+	for (i = 0; i < LDPAA_ETH_DPNI_NUM_STATS; i++)
+		printf("  %s: %llu\n", ldpaa_eth_dpni_stat_strings[i], data[i]);
+}
 
-	err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
-		     priv->dpmac_handle,
-		     DPMAC_CNT_EGR_ERR_FRAME ,
-		     &value);
-	if (err < 0) {
-		printf("dpmac_get_counter: DPMAC_CNT_EGR_ERR_FRAME failed\n");
-		return;
-	}
-	printf("DPMAC_CNT_EGR_ERR_FRAME =%lld\n", value);
+static void ldpaa_eth_dump_dpmac_stats(struct udevice *dev, u64 *data)
+{
+	int i;
+
+	printf("DPMAC counters:\n");
+	for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++)
+		printf("  %s: %llu\n", ldpaa_eth_dpmac_stat_strings[i], data[i]);
 }
 #endif
 
@@ -434,7 +378,8 @@ static int ldpaa_eth_open(struct udevice *dev)
 	struct dpni_link_state link_state;
 #endif
 	int err = 0;
-	struct dpni_queue d_queue;
+	struct dpni_queue d_queue_cfg = { 0 };
+	struct dpni_queue_id d_queue;
 
 	if (eth_is_active(dev))
 		return 0;
@@ -478,7 +423,7 @@ static int ldpaa_eth_open(struct udevice *dev)
 		goto err_dpni_bind;
 
 	err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
-				dflt_dpni->dpni_handle, plat->enetaddr);
+				dflt_dpni->dpni_handle, plat->enetaddr, 0, 0, 0);
 	if (err) {
 		printf("dpni_add_mac_addr() failed\n");
 		return err;
@@ -517,7 +462,7 @@ static int ldpaa_eth_open(struct udevice *dev)
 	memset(&d_queue, 0, sizeof(struct dpni_queue));
 	err = dpni_get_queue(dflt_mc_io, MC_CMD_NO_FLAGS,
 			     dflt_dpni->dpni_handle, DPNI_QUEUE_RX,
-			     0, 0, &d_queue);
+			     0, 0, &d_queue_cfg, &d_queue);
 	if (err) {
 		printf("dpni_get_queue failed\n");
 		goto err_get_queue;
@@ -526,7 +471,7 @@ static int ldpaa_eth_open(struct udevice *dev)
 	priv->rx_dflt_fqid = d_queue.fqid;
 
 	err = dpni_get_qdid(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle,
-			    &priv->tx_qdid);
+			    DPNI_QUEUE_TX, &priv->tx_qdid);
 	if (err) {
 		printf("dpni_get_qdid() failed\n");
 		goto err_qdid;
@@ -556,14 +501,30 @@ static void ldpaa_eth_stop(struct udevice *dev)
 	struct ldpaa_eth_priv *priv = dev_get_priv(dev);
 	struct phy_device *phydev = NULL;
 	int err = 0;
+	u64 *data;
 
 	if (!eth_is_active(dev))
 		return;
 
+	data = kzalloc(sizeof(u64) * LDPAA_ETH_DPNI_NUM_STATS, GFP_KERNEL);
+	if (data) {
+		ldpaa_eth_collect_dpni_stats(dev, data);
+		ldpaa_eth_add_dpni_stats(dev, data);
 #ifdef DEBUG
-	ldpaa_eth_get_dpni_counter();
-	ldpaa_eth_get_dpmac_counter(dev);
+		ldpaa_eth_dump_dpni_stats(dev, data);
 #endif
+	}
+	kfree(data);
+
+	data = kzalloc(sizeof(u64) * LDPAA_ETH_DPMAC_NUM_STATS, GFP_KERNEL);
+	if (data) {
+		ldpaa_eth_collect_dpmac_stats(dev, data);
+		ldpaa_eth_add_dpmac_stats(dev, data);
+#ifdef DEBUG
+		ldpaa_eth_dump_dpmac_stats(dev, data);
+#endif
+	}
+	kfree(data);
 
 	err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS,
 			      dflt_dprc_handle, &dpmac_endpoint);
@@ -885,7 +846,7 @@ static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv)
 	/* ...rx, ... */
 	err = dpni_set_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
 				     dflt_dpni->dpni_handle,
-				     &dflt_dpni->buf_layout, DPNI_QUEUE_RX);
+				     DPNI_QUEUE_RX, &dflt_dpni->buf_layout);
 	if (err) {
 		printf("dpni_set_buffer_layout() failed");
 		goto err_buf_layout;
@@ -897,7 +858,7 @@ static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv)
 				      DPNI_BUF_LAYOUT_OPT_PARSER_RESULT);
 	err = dpni_set_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
 				     dflt_dpni->dpni_handle,
-				     &dflt_dpni->buf_layout, DPNI_QUEUE_TX);
+				     DPNI_QUEUE_TX, &dflt_dpni->buf_layout);
 	if (err) {
 		printf("dpni_set_buffer_layout() failed");
 		goto err_buf_layout;
@@ -907,8 +868,7 @@ static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv)
 	dflt_dpni->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
 	err = dpni_set_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
 				     dflt_dpni->dpni_handle,
-				     &dflt_dpni->buf_layout,
-				     DPNI_QUEUE_TX_CONFIRM);
+				     DPNI_QUEUE_TX_CONFIRM, &dflt_dpni->buf_layout);
 	if (err) {
 		printf("dpni_set_buffer_layout() failed");
 		goto err_buf_layout;
@@ -963,7 +923,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv)
 
 	err = dpni_set_queue(dflt_mc_io, MC_CMD_NO_FLAGS,
 			     dflt_dpni->dpni_handle,
-			     DPNI_QUEUE_TX, 0, 0, &tx_queue);
+			     DPNI_QUEUE_TX, 0, 0, 0, &tx_queue);
 
 	if (err) {
 		printf("dpni_set_queue() failed\n");
@@ -972,7 +932,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv)
 
 	err = dpni_set_tx_confirmation_mode(dflt_mc_io, MC_CMD_NO_FLAGS,
 					    dflt_dpni->dpni_handle,
-					    DPNI_CONF_DISABLE);
+					    0, DPNI_CONF_DISABLE);
 	if (err) {
 		printf("dpni_set_tx_confirmation_mode() failed\n");
 		return err;
@@ -1038,11 +998,47 @@ static int ldpaa_eth_of_to_plat(struct udevice *dev)
 	return 0;
 }
 
+static int ldpaa_eth_get_sset_count(struct udevice *dev)
+{
+	return LDPAA_ETH_DPNI_NUM_STATS + LDPAA_ETH_DPMAC_NUM_STATS;
+}
+
+static void ldpaa_eth_get_strings(struct udevice *dev, u8 *data)
+{
+	u8 *p = data;
+	int i;
+
+	for (i = 0; i < LDPAA_ETH_DPNI_NUM_STATS; i++) {
+		strlcpy(p, ldpaa_eth_dpni_stat_strings[i], ETH_GSTRING_LEN);
+		p += ETH_GSTRING_LEN;
+	}
+
+	for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++) {
+		strlcpy(p, ldpaa_eth_dpmac_stat_strings[i], ETH_GSTRING_LEN);
+		p += ETH_GSTRING_LEN;
+	}
+}
+
+static void ldpaa_eth_get_stats(struct udevice *dev, u64 *data)
+{
+	struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+	int i, j = 0;
+
+	for (i = 0; i < LDPAA_ETH_DPNI_NUM_STATS; i++)
+		*(data + j++) = priv->dpni_stats[i];
+
+	for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++)
+		*(data + j++) = priv->dpmac_stats[i];
+}
+
 static const struct eth_ops ldpaa_eth_ops = {
-	.start	= ldpaa_eth_open,
-	.send	= ldpaa_eth_tx,
-	.recv	= ldpaa_eth_pull_dequeue_rx,
-	.stop	= ldpaa_eth_stop,
+	.start = ldpaa_eth_open,
+	.send = ldpaa_eth_tx,
+	.recv = ldpaa_eth_pull_dequeue_rx,
+	.stop = ldpaa_eth_stop,
+	.get_sset_count = ldpaa_eth_get_sset_count,
+	.get_strings = ldpaa_eth_get_strings,
+	.get_stats = ldpaa_eth_get_stats,
 };
 
 static const struct udevice_id ldpaa_eth_of_ids[] = {
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h
index 16d0106233..af082e34ca 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.h
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.h
@@ -115,6 +115,66 @@ struct ldpaa_fas {
 					 LDPAA_ETH_FAS_MNLE	| \
 					 LDPAA_ETH_FAS_TIDE)
 
+static const char ldpaa_eth_dpni_stat_strings[][ETH_GSTRING_LEN] = {
+	"[dpni ] rx frames",
+	"[dpni ] rx bytes",
+	"[dpni ] rx mcast frames",
+	"[dpni ] rx mcast bytes",
+	"[dpni ] rx bcast frames",
+	"[dpni ] rx bcast bytes",
+	"[dpni ] tx frames",
+	"[dpni ] tx bytes",
+	"[dpni ] tx mcast frames",
+	"[dpni ] tx mcast bytes",
+	"[dpni ] tx bcast frames",
+	"[dpni ] tx bcast bytes",
+	"[dpni ] rx filtered frames",
+	"[dpni ] rx discarded frames",
+	"[dpni ] rx nobuffer discards",
+	"[dpni ] tx discarded frames",
+	"[dpni ] tx confirmed frames",
+	"[dpni ] tx dequeued bytes",
+	"[dpni ] tx dequeued frames",
+	"[dpni ] tx rejected bytes",
+	"[dpni ] tx rejected frames",
+	"[dpni ] tx pending frames",
+};
+
+#define LDPAA_ETH_DPNI_NUM_STATS	ARRAY_SIZE(ldpaa_eth_dpni_stat_strings)
+
+static const char ldpaa_eth_dpmac_stat_strings[][ETH_GSTRING_LEN] = {
+	[DPMAC_CNT_ING_ALL_FRAME]		= "[mac] rx all frames",
+	[DPMAC_CNT_ING_GOOD_FRAME]		= "[mac] rx frames ok",
+	[DPMAC_CNT_ING_ERR_FRAME]		= "[mac] rx frame errors",
+	[DPMAC_CNT_ING_FRAME_DISCARD]		= "[mac] rx frame discards",
+	[DPMAC_CNT_ING_UCAST_FRAME]		= "[mac] rx u-cast",
+	[DPMAC_CNT_ING_BCAST_FRAME]		= "[mac] rx b-cast",
+	[DPMAC_CNT_ING_MCAST_FRAME]		= "[mac] rx m-cast",
+	[DPMAC_CNT_ING_FRAME_64]		= "[mac] rx 64 bytes",
+	[DPMAC_CNT_ING_FRAME_127]		= "[mac] rx 65-127 bytes",
+	[DPMAC_CNT_ING_FRAME_255]		= "[mac] rx 128-255 bytes",
+	[DPMAC_CNT_ING_FRAME_511]		= "[mac] rx 256-511 bytes",
+	[DPMAC_CNT_ING_FRAME_1023]		= "[mac] rx 512-1023 bytes",
+	[DPMAC_CNT_ING_FRAME_1518]		= "[mac] rx 1024-1518 bytes",
+	[DPMAC_CNT_ING_FRAME_1519_MAX]		= "[mac] rx 1519-max bytes",
+	[DPMAC_CNT_ING_FRAG]			= "[mac] rx frags",
+	[DPMAC_CNT_ING_JABBER]			= "[mac] rx jabber",
+	[DPMAC_CNT_ING_ALIGN_ERR]		= "[mac] rx align errors",
+	[DPMAC_CNT_ING_OVERSIZED]		= "[mac] rx oversized",
+	[DPMAC_CNT_ING_VALID_PAUSE_FRAME]	= "[mac] rx pause",
+	[DPMAC_CNT_ING_BYTE]			= "[mac] rx bytes",
+	[DPMAC_CNT_EGR_GOOD_FRAME]		= "[mac] tx frames ok",
+	[DPMAC_CNT_EGR_UCAST_FRAME]		= "[mac] tx u-cast",
+	[DPMAC_CNT_EGR_MCAST_FRAME]		= "[mac] tx m-cast",
+	[DPMAC_CNT_EGR_BCAST_FRAME]		= "[mac] tx b-cast",
+	[DPMAC_CNT_EGR_ERR_FRAME]		= "[mac] tx frame errors",
+	[DPMAC_CNT_EGR_UNDERSIZED]		= "[mac] tx undersized",
+	[DPMAC_CNT_EGR_VALID_PAUSE_FRAME]	= "[mac] tx b-pause",
+	[DPMAC_CNT_EGR_BYTE]			= "[mac] tx bytes",
+};
+
+#define LDPAA_ETH_DPMAC_NUM_STATS	ARRAY_SIZE(ldpaa_eth_dpmac_stat_strings)
+
 struct ldpaa_eth_priv {
 	struct phy_device *phy;
 	int phy_mode;
@@ -129,6 +189,10 @@ struct ldpaa_eth_priv {
 	uint16_t tx_flow_id;
 
 	enum ldpaa_eth_type type;	/* 1G or 10G ethernet */
+
+	/* SW kept statistics */
+	u64 dpni_stats[LDPAA_ETH_DPNI_NUM_STATS];
+	u64 dpmac_stats[LDPAA_ETH_DPMAC_NUM_STATS];
 };
 
 struct dprc_endpoint dpmac_endpoint;
diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index 4c9fb266c7..d4111e73df 100644
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -54,6 +54,16 @@
 	(DP_PDMA << MC_DP_S) | \
 	(DP_PDMA << UN_DP_S))
 
+#define GDMA_BRIDGE_TO_CPU \
+	(0xC0000000 | \
+	GDM_ICS_EN | \
+	GDM_TCS_EN | \
+	GDM_UCS_EN | \
+	(DP_PDMA << MYMAC_DP_S) | \
+	(DP_PDMA << BC_DP_S) | \
+	(DP_PDMA << MC_DP_S) | \
+	(DP_PDMA << UN_DP_S))
+
 #define GDMA_FWD_DISCARD \
 	(0x20000000 | \
 	GDM_ICS_EN | \
@@ -68,7 +78,8 @@
 enum mtk_switch {
 	SW_NONE,
 	SW_MT7530,
-	SW_MT7531
+	SW_MT7531,
+	SW_MT7988,
 };
 
 /* struct mtk_soc_data -	This is the structure holding all differences
@@ -76,6 +87,7 @@ enum mtk_switch {
  * @caps			Flags shown the extra capability for the SoC
  * @ana_rgc3:			The offset for register ANA_RGC3 related to
  *				sgmiisys syscon
+ * @gdma_count:			Number of GDMAs
  * @pdma_base:			Register base of PDMA block
  * @txd_size:			Tx DMA descriptor size.
  * @rxd_size:			Rx DMA descriptor size.
@@ -83,6 +95,7 @@ enum mtk_switch {
 struct mtk_soc_data {
 	u32 caps;
 	u32 ana_rgc3;
+	u32 gdma_count;
 	u32 pdma_base;
 	u32 txd_size;
 	u32 rxd_size;
@@ -100,9 +113,17 @@ struct mtk_eth_priv {
 	void __iomem *fe_base;
 	void __iomem *gmac_base;
 	void __iomem *sgmii_base;
+	void __iomem *gsw_base;
 
 	struct regmap *ethsys_regmap;
 
+	struct regmap *infra_regmap;
+
+	struct regmap *usxgmii_regmap;
+	struct regmap *xfi_pextp_regmap;
+	struct regmap *xfi_pll_regmap;
+	struct regmap *toprgu_regmap;
+
 	struct mii_dev *mdio_bus;
 	int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
 	int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
@@ -123,8 +144,11 @@ struct mtk_eth_priv {
 
 	enum mtk_switch sw;
 	int (*switch_init)(struct mtk_eth_priv *priv);
+	void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable);
 	u32 mt753x_smi_addr;
 	u32 mt753x_phy_base;
+	u32 mt753x_pmcr;
+	u32 mt753x_reset_wait_time;
 
 	struct gpio_desc rst_gpio;
 	int mcm;
@@ -149,7 +173,9 @@ static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg,
 {
 	u32 gdma_base;
 
-	if (no == 1)
+	if (no == 2)
+		gdma_base = GDMA3_BASE;
+	else if (no == 1)
 		gdma_base = GDMA2_BASE;
 	else
 		gdma_base = GDMA1_BASE;
@@ -157,6 +183,11 @@ static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg,
 	writel(val, priv->fe_base + gdma_base + reg);
 }
 
+static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
+{
+	clrsetbits_le32(priv->fe_base + reg, clr, set);
+}
+
 static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
 {
 	return readl(priv->gmac_base + reg);
@@ -183,6 +214,27 @@ static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
 	regmap_write(priv->ethsys_regmap, reg, val);
 }
 
+static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
+			  u32 set)
+{
+	uint val;
+
+	regmap_read(priv->infra_regmap, reg, &val);
+	val &= ~clr;
+	val |= set;
+	regmap_write(priv->infra_regmap, reg, val);
+}
+
+static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg)
+{
+	return readl(priv->gsw_base + reg);
+}
+
+static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
+{
+	writel(val, priv->gsw_base + reg);
+}
+
 /* Direct MDIO clause 22/45 access via SoC */
 static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
 		      u32 cmd, u32 st)
@@ -195,7 +247,7 @@ static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
 	      (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
 	      (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
 
-	if (cmd == MDIO_CMD_WRITE)
+	if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
 		val |= data & MDIO_RW_DATA_M;
 
 	mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
@@ -207,7 +259,7 @@ static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
 		return ret;
 	}
 
-	if (cmd == MDIO_CMD_READ) {
+	if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
 		val = mtk_gmac_read(priv, GMAC_PIAC_REG);
 		return val & MDIO_RW_DATA_M;
 	}
@@ -317,6 +369,11 @@ static int mt753x_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data)
 {
 	int ret, low_word, high_word;
 
+	if (priv->sw == SW_MT7988) {
+		*data = mtk_gsw_read(priv, reg);
+		return 0;
+	}
+
 	/* Write page address */
 	ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
 	if (ret)
@@ -342,6 +399,11 @@ static int mt753x_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data)
 {
 	int ret;
 
+	if (priv->sw == SW_MT7988) {
+		mtk_gsw_write(priv, reg, data);
+		return 0;
+	}
+
 	/* Write page address */
 	ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
 	if (ret)
@@ -433,7 +495,8 @@ static int mt7531_mii_ind_write(struct mtk_eth_priv *priv, u8 phy, u8 reg,
 			     MDIO_ST_C22);
 }
 
-int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
+static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
+			       u16 reg)
 {
 	u8 phy_addr;
 	int ret;
@@ -511,6 +574,7 @@ static int mtk_mdio_register(struct udevice *dev)
 		priv->mmd_write = mtk_mmd_ind_write;
 		break;
 	case SW_MT7531:
+	case SW_MT7988:
 		priv->mii_read = mt7531_mii_ind_read;
 		priv->mii_write = mt7531_mii_ind_write;
 		priv->mmd_read = mt7531_mmd_ind_read;
@@ -613,6 +677,16 @@ static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode)
 	return 0;
 }
 
+static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable)
+{
+	u32 pmcr = FORCE_MODE;
+
+	if (enable)
+		pmcr = priv->mt753x_pmcr;
+
+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
+}
+
 static int mt7530_setup(struct mtk_eth_priv *priv)
 {
 	u16 phy_addr, phy_val;
@@ -663,11 +737,14 @@ static int mt7530_setup(struct mtk_eth_priv *priv)
 	      FORCE_DPX | FORCE_LINK;
 
 	/* MT7530 Port6: Forced 1000M/FD, FC disabled */
-	mt753x_reg_write(priv, PMCR_REG(6), val);
+	priv->mt753x_pmcr = val;
 
 	/* MT7530 Port5: Forced link down */
 	mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
 
+	/* Keep MAC link down before starting eth */
+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
+
 	/* MT7530 Port6: Set to RGMII */
 	mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
 
@@ -823,6 +900,17 @@ static void mt7531_phy_setting(struct mtk_eth_priv *priv)
 	}
 }
 
+static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable)
+{
+	u32 pmcr = FORCE_MODE_LNK;
+
+	if (enable)
+		pmcr = priv->mt753x_pmcr;
+
+	mt753x_reg_write(priv, PMCR_REG(5), pmcr);
+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
+}
+
 static int mt7531_setup(struct mtk_eth_priv *priv)
 {
 	u16 phy_addr, phy_val;
@@ -865,7 +953,7 @@ static int mt7531_setup(struct mtk_eth_priv *priv)
 		if (!port5_sgmii)
 			mt7531_port_rgmii_init(priv, 5);
 		break;
-	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_2500BASEX:
 		mt7531_port_sgmii_init(priv, 6);
 		if (port5_sgmii)
 			mt7531_port_sgmii_init(priv, 5);
@@ -882,8 +970,11 @@ static int mt7531_setup(struct mtk_eth_priv *priv)
 	       (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
 	       FORCE_LINK;
 
-	mt753x_reg_write(priv, PMCR_REG(5), pmcr);
-	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
+	priv->mt753x_pmcr = pmcr;
+
+	/* Keep MAC link down before starting eth */
+	mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
 
 	/* Turn on PHYs */
 	for (i = 0; i < MT753X_NUM_PHYS; i++) {
@@ -904,7 +995,104 @@ static int mt7531_setup(struct mtk_eth_priv *priv)
 	return 0;
 }
 
-int mt753x_switch_init(struct mtk_eth_priv *priv)
+static void mt7988_phy_setting(struct mtk_eth_priv *priv)
+{
+	u16 val;
+	u32 i;
+
+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
+		/* Enable HW auto downshift */
+		priv->mii_write(priv, i, 0x1f, 0x1);
+		val = priv->mii_read(priv, i, PHY_EXT_REG_14);
+		val |= PHY_EN_DOWN_SHFIT;
+		priv->mii_write(priv, i, PHY_EXT_REG_14, val);
+
+		/* PHY link down power saving enable */
+		val = priv->mii_read(priv, i, PHY_EXT_REG_17);
+		val |= PHY_LINKDOWN_POWER_SAVING_EN;
+		priv->mii_write(priv, i, PHY_EXT_REG_17, val);
+	}
+}
+
+static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable)
+{
+	u32 pmcr = FORCE_MODE_LNK;
+
+	if (enable)
+		pmcr = priv->mt753x_pmcr;
+
+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
+}
+
+static int mt7988_setup(struct mtk_eth_priv *priv)
+{
+	u16 phy_addr, phy_val;
+	u32 pmcr;
+	int i;
+
+	priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE;
+
+	priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
+				MT753X_SMI_ADDR_MASK;
+
+	/* Turn off PHYs */
+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
+		phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
+		phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
+		phy_val |= BMCR_PDOWN;
+		priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
+	}
+
+	switch (priv->phy_interface) {
+	case PHY_INTERFACE_MODE_USXGMII:
+		/* Use CPU bridge instead of actual USXGMII path */
+
+		/* Set GDM1 no drop */
+		mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1);
+
+		/* Enable GDM1 to GSW CPU bridge */
+		mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0));
+
+		/* XGMAC force link up */
+		mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK);
+
+		/* Setup GSW CPU bridge IPG */
+		mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M,
+			     (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S));
+		break;
+	default:
+		printf("Error: MT7988 GSW does not support %s interface\n",
+		       phy_string_for_interface(priv->phy_interface));
+		break;
+	}
+
+	pmcr = MT7988_FORCE_MODE |
+	       (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
+	       MAC_MODE | MAC_TX_EN | MAC_RX_EN |
+	       BKOFF_EN | BACKPR_EN |
+	       FORCE_RX_FC | FORCE_TX_FC |
+	       (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
+	       FORCE_LINK;
+
+	priv->mt753x_pmcr = pmcr;
+
+	/* Keep MAC link down before starting eth */
+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
+
+	/* Turn on PHYs */
+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
+		phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
+		phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
+		phy_val &= ~BMCR_PDOWN;
+		priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
+	}
+
+	mt7988_phy_setting(priv);
+
+	return 0;
+}
+
+static int mt753x_switch_init(struct mtk_eth_priv *priv)
 {
 	int ret;
 	int i;
@@ -914,12 +1102,12 @@ int mt753x_switch_init(struct mtk_eth_priv *priv)
 		reset_assert(&priv->rst_mcm);
 		udelay(1000);
 		reset_deassert(&priv->rst_mcm);
-		mdelay(1000);
+		mdelay(priv->mt753x_reset_wait_time);
 	} else if (dm_gpio_is_valid(&priv->rst_gpio)) {
 		dm_gpio_set_value(&priv->rst_gpio, 0);
 		udelay(1000);
 		dm_gpio_set_value(&priv->rst_gpio, 1);
-		mdelay(1000);
+		mdelay(priv->mt753x_reset_wait_time);
 	}
 
 	ret = priv->switch_init(priv);
@@ -945,6 +1133,42 @@ int mt753x_switch_init(struct mtk_eth_priv *priv)
 	return 0;
 }
 
+static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv)
+{
+	u16 lcl_adv = 0, rmt_adv = 0;
+	u8 flowctrl;
+	u32 mcr;
+
+	mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id));
+	mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC);
+
+	if (priv->phydev->duplex) {
+		if (priv->phydev->pause)
+			rmt_adv = LPA_PAUSE_CAP;
+		if (priv->phydev->asym_pause)
+			rmt_adv |= LPA_PAUSE_ASYM;
+
+		if (priv->phydev->advertising & ADVERTISED_Pause)
+			lcl_adv |= ADVERTISE_PAUSE_CAP;
+		if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
+			lcl_adv |= ADVERTISE_PAUSE_ASYM;
+
+		flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+
+		if (flowctrl & FLOW_CTRL_TX)
+			mcr |= XGMAC_FORCE_TX_FC;
+		if (flowctrl & FLOW_CTRL_RX)
+			mcr |= XGMAC_FORCE_RX_FC;
+
+		debug("rx pause %s, tx pause %s\n",
+		      flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
+		      flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
+	}
+
+	mcr &= ~(XGMAC_TRX_DISABLE);
+	mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr);
+}
+
 static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
 {
 	u16 lcl_adv = 0, rmt_adv = 0;
@@ -955,6 +1179,7 @@ static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
 	      (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
 	      MAC_MODE | FORCE_MODE |
 	      MAC_TX_EN | MAC_RX_EN |
+	      DEL_RXFIFO_CLR |
 	      BKOFF_EN | BACKPR_EN;
 
 	switch (priv->phydev->speed) {
@@ -965,6 +1190,7 @@ static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
 		mcr |= (SPEED_100M << FORCE_SPD_S);
 		break;
 	case SPEED_1000:
+	case SPEED_2500:
 		mcr |= (SPEED_1000M << FORCE_SPD_S);
 		break;
 	};
@@ -1017,7 +1243,12 @@ static int mtk_phy_start(struct mtk_eth_priv *priv)
 		return 0;
 	}
 
-	mtk_phy_link_adjust(priv);
+	if (!priv->force_mode) {
+		if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
+			mtk_xphy_link_adjust(priv);
+		else
+			mtk_phy_link_adjust(priv);
+	}
 
 	debug("Speed: %d, %s duplex%s\n", phydev->speed,
 	      (phydev->duplex) ? "full" : "half",
@@ -1045,7 +1276,31 @@ static int mtk_phy_probe(struct udevice *dev)
 	return 0;
 }
 
-static void mtk_sgmii_init(struct mtk_eth_priv *priv)
+static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
+{
+	/* Set SGMII GEN1 speed(1G) */
+	clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
+			SGMSYS_SPEED_2500, 0);
+
+	/* Enable SGMII AN */
+	setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
+		     SGMII_AN_ENABLE);
+
+	/* SGMII AN mode setting */
+	writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
+
+	/* SGMII PN SWAP setting */
+	if (priv->pn_swap) {
+		setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
+			     SGMII_PN_SWAP_TX_RX);
+	}
+
+	/* Release PHYA power down state */
+	clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
+			SGMII_PHYA_PWD, 0);
+}
+
+static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
 {
 	/* Set SGMII GEN2 speed(2.5G) */
 	setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
@@ -1069,6 +1324,112 @@ static void mtk_sgmii_init(struct mtk_eth_priv *priv)
 			SGMII_PHYA_PWD, 0);
 }
 
+static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv)
+{
+	u32 val = 0;
+
+	/* Add software workaround for USXGMII PLL TCL issue */
+	regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8,
+		     RG_XFI_PLL_ANA_SWWA);
+
+	regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val);
+	val |= RG_XFI_PLL_EN;
+	regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val);
+}
+
+static void mtk_usxgmii_reset(struct mtk_eth_priv *priv)
+{
+	switch (priv->gmac_id) {
+	case 1:
+		regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004);
+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004);
+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
+		regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
+		break;
+	case 2:
+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002);
+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002);
+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
+		regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
+		break;
+	}
+
+	mdelay(10);
+}
+
+static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv)
+{
+	regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D);
+	regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000);
+	ndelay(1020);
+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000);
+	ndelay(1020);
+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000);
+
+	regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
+	regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
+	regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
+	regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
+	regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
+	regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
+	regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
+	regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
+	regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
+	regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
+	regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
+	regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
+	regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
+	regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
+	regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
+	regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
+	regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
+	regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
+	regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
+	regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
+	regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
+	regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
+	regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
+	ndelay(1020);
+	regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
+	regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
+	regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
+	regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
+	regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
+	regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
+	regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
+	regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000);
+	regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000);
+	regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA);
+	regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
+	regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
+	regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
+	udelay(150);
+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
+	ndelay(1020);
+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
+	udelay(15);
+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
+	ndelay(1020);
+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
+	udelay(100);
+	regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
+	regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
+	regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
+	udelay(400);
+}
+
+static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
+{
+	mtk_xfi_pll_enable(priv);
+	mtk_usxgmii_reset(priv);
+	mtk_usxgmii_setup_phya_an_10000(priv);
+}
+
 static void mtk_mac_init(struct mtk_eth_priv *priv)
 {
 	int i, ge_mode = 0;
@@ -1080,10 +1441,19 @@ static void mtk_mac_init(struct mtk_eth_priv *priv)
 		ge_mode = GE_MODE_RGMII;
 		break;
 	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) {
+			mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK,
+				      SGMII_QPHY_SEL);
+		}
+
 		ge_mode = GE_MODE_RGMII;
 		mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
 			       SYSCFG0_SGMII_SEL(priv->gmac_id));
-		mtk_sgmii_init(priv);
+		if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
+			mtk_sgmii_an_init(priv);
+		else
+			mtk_sgmii_force_init(priv);
 		break;
 	case PHY_INTERFACE_MODE_MII:
 	case PHY_INTERFACE_MODE_GMII:
@@ -1117,6 +1487,7 @@ static void mtk_mac_init(struct mtk_eth_priv *priv)
 			mcr |= SPEED_100M << FORCE_SPD_S;
 			break;
 		case SPEED_1000:
+		case SPEED_2500:
 			mcr |= SPEED_1000M << FORCE_SPD_S;
 			break;
 		}
@@ -1141,6 +1512,36 @@ static void mtk_mac_init(struct mtk_eth_priv *priv)
 	}
 }
 
+static void mtk_xmac_init(struct mtk_eth_priv *priv)
+{
+	u32 sts;
+
+	switch (priv->phy_interface) {
+	case PHY_INTERFACE_MODE_USXGMII:
+		mtk_usxgmii_an_init(priv);
+		break;
+	default:
+		break;
+	}
+
+	/* Set GMAC to the correct mode */
+	mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
+		       SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
+		       0);
+
+	if (priv->gmac_id == 1) {
+		mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
+			      NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
+	} else if (priv->gmac_id == 2) {
+		sts = mtk_gmac_read(priv, XGMAC_STS(priv->gmac_id));
+		sts |= XGMAC_FORCE_LINK;
+		mtk_gmac_write(priv, XGMAC_STS(priv->gmac_id), sts);
+	}
+
+	/* Force GMAC link down */
+	mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
+}
+
 static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
 {
 	char *pkt_base = priv->pkt_pool;
@@ -1167,7 +1568,10 @@ static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
 		txd->txd1 = virt_to_phys(pkt_base);
 		txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0;
 
-		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
+			txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ?
+							   15 : priv->gmac_id + 1);
+		else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
 			txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1);
 		else
 			txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1);
@@ -1180,7 +1584,8 @@ static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
 
 		rxd->rxd1 = virt_to_phys(pkt_base);
 
-		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+		    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
 			rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
 		else
 			rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
@@ -1204,7 +1609,7 @@ static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
 static int mtk_eth_start(struct udevice *dev)
 {
 	struct mtk_eth_priv *priv = dev_get_priv(dev);
-	int ret;
+	int i, ret;
 
 	/* Reset FE */
 	reset_assert(&priv->rst_fe);
@@ -1212,21 +1617,37 @@ static int mtk_eth_start(struct udevice *dev)
 	reset_deassert(&priv->rst_fe);
 	mdelay(10);
 
-	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
 		setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2);
 
 	/* Packets forward to PDMA */
 	mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
 
-	if (priv->gmac_id == 0)
-		mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
-	else
-		mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
+	for (i = 0; i < priv->soc->gdma_count; i++) {
+		if (i == priv->gmac_id)
+			continue;
+
+		mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
+	}
+
+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
+		if (priv->sw == SW_MT7988 && priv->gmac_id == 0) {
+			mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG,
+				       GDMA_BRIDGE_TO_CPU);
+		}
+
+		mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
+			       GDMA_CPU_BRIDGE_EN);
+	}
 
 	udelay(500);
 
 	mtk_eth_fifo_init(priv);
 
+	if (priv->switch_mac_control)
+		priv->switch_mac_control(priv, true);
+
 	/* Start PHY */
 	if (priv->sw == SW_NONE) {
 		ret = mtk_phy_start(priv);
@@ -1245,6 +1666,9 @@ static void mtk_eth_stop(struct udevice *dev)
 {
 	struct mtk_eth_priv *priv = dev_get_priv(dev);
 
+	if (priv->switch_mac_control)
+		priv->switch_mac_control(priv, false);
+
 	mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
 		     TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
 	udelay(500);
@@ -1289,7 +1713,8 @@ static int mtk_eth_send(struct udevice *dev, void *packet, int length)
 	flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
 			   roundup(length, ARCH_DMA_MINALIGN));
 
-	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
 		txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length);
 	else
 		txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length);
@@ -1315,7 +1740,8 @@ static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 		return -EAGAIN;
 	}
 
-	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
 		length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2);
 	else
 		length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2);
@@ -1338,7 +1764,8 @@ static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
 
 	rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
 
-	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
 		rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
 	else
 		rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
@@ -1376,7 +1803,10 @@ static int mtk_eth_probe(struct udevice *dev)
 				ARCH_DMA_MINALIGN);
 
 	/* Set MAC mode */
-	mtk_mac_init(priv);
+	if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
+		mtk_xmac_init(priv);
+	else
+		mtk_mac_init(priv);
 
 	/* Probe phy if switch is not specified */
 	if (priv->sw == SW_NONE)
@@ -1428,6 +1858,19 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
 	if (IS_ERR(priv->ethsys_regmap))
 		return PTR_ERR(priv->ethsys_regmap);
 
+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) {
+		/* get corresponding infracfg phandle */
+		ret = dev_read_phandle_with_args(dev, "mediatek,infracfg",
+						 NULL, 0, 0, &args);
+
+		if (ret)
+			return ret;
+
+		priv->infra_regmap = syscon_node_to_regmap(args.node);
+		if (IS_ERR(priv->infra_regmap))
+			return PTR_ERR(priv->infra_regmap);
+	}
+
 	/* Reset controllers */
 	ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
 	if (ret) {
@@ -1453,13 +1896,15 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
 		priv->duplex = ofnode_read_bool(subnode, "full-duplex");
 
 		if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
-		    priv->speed != SPEED_1000) {
+		    priv->speed != SPEED_1000 && priv->speed != SPEED_2500 &&
+		    priv->speed != SPEED_10000) {
 			printf("error: no valid speed set in fixed-link\n");
 			return -EINVAL;
 		}
 	}
 
-	if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+	if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+	    priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
 		/* get corresponding sgmii phandle */
 		ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
 						 NULL, 0, 0, &args);
@@ -1479,22 +1924,73 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
 		}
 
 		priv->pn_swap = ofnode_read_bool(args.node, "pn_swap");
+	} else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
+		/* get corresponding usxgmii phandle */
+		ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
+						 NULL, 0, 0, &args);
+		if (ret)
+			return ret;
+
+		priv->usxgmii_regmap = syscon_node_to_regmap(args.node);
+		if (IS_ERR(priv->usxgmii_regmap))
+			return PTR_ERR(priv->usxgmii_regmap);
+
+		/* get corresponding xfi_pextp phandle */
+		ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp",
+						 NULL, 0, 0, &args);
+		if (ret)
+			return ret;
+
+		priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node);
+		if (IS_ERR(priv->xfi_pextp_regmap))
+			return PTR_ERR(priv->xfi_pextp_regmap);
+
+		/* get corresponding xfi_pll phandle */
+		ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll",
+						 NULL, 0, 0, &args);
+		if (ret)
+			return ret;
+
+		priv->xfi_pll_regmap = syscon_node_to_regmap(args.node);
+		if (IS_ERR(priv->xfi_pll_regmap))
+			return PTR_ERR(priv->xfi_pll_regmap);
+
+		/* get corresponding toprgu phandle */
+		ret = dev_read_phandle_with_args(dev, "mediatek,toprgu",
+						 NULL, 0, 0, &args);
+		if (ret)
+			return ret;
+
+		priv->toprgu_regmap = syscon_node_to_regmap(args.node);
+		if (IS_ERR(priv->toprgu_regmap))
+			return PTR_ERR(priv->toprgu_regmap);
 	}
 
 	/* check for switch first, otherwise phy will be used */
 	priv->sw = SW_NONE;
 	priv->switch_init = NULL;
+	priv->switch_mac_control = NULL;
 	str = dev_read_string(dev, "mediatek,switch");
 
 	if (str) {
 		if (!strcmp(str, "mt7530")) {
 			priv->sw = SW_MT7530;
 			priv->switch_init = mt7530_setup;
+			priv->switch_mac_control = mt7530_mac_control;
 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
+			priv->mt753x_reset_wait_time = 1000;
 		} else if (!strcmp(str, "mt7531")) {
 			priv->sw = SW_MT7531;
 			priv->switch_init = mt7531_setup;
+			priv->switch_mac_control = mt7531_mac_control;
 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
+			priv->mt753x_reset_wait_time = 200;
+		} else if (!strcmp(str, "mt7988")) {
+			priv->sw = SW_MT7988;
+			priv->switch_init = mt7988_setup;
+			priv->switch_mac_control = mt7988_mac_control;
+			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
+			priv->mt753x_reset_wait_time = 50;
 		} else {
 			printf("error: unsupported switch\n");
 			return -EINVAL;
@@ -1529,17 +2025,28 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
 	return 0;
 }
 
+static const struct mtk_soc_data mt7988_data = {
+	.caps = MT7988_CAPS,
+	.ana_rgc3 = 0x128,
+	.gdma_count = 3,
+	.pdma_base = PDMA_V3_BASE,
+	.txd_size = sizeof(struct mtk_tx_dma_v2),
+	.rxd_size = sizeof(struct mtk_rx_dma_v2),
+};
+
 static const struct mtk_soc_data mt7986_data = {
 	.caps = MT7986_CAPS,
 	.ana_rgc3 = 0x128,
+	.gdma_count = 2,
 	.pdma_base = PDMA_V2_BASE,
 	.txd_size = sizeof(struct mtk_tx_dma_v2),
 	.rxd_size = sizeof(struct mtk_rx_dma_v2),
 };
 
 static const struct mtk_soc_data mt7981_data = {
-	.caps = MT7986_CAPS,
+	.caps = MT7981_CAPS,
 	.ana_rgc3 = 0x128,
+	.gdma_count = 2,
 	.pdma_base = PDMA_V2_BASE,
 	.txd_size = sizeof(struct mtk_tx_dma_v2),
 	.rxd_size = sizeof(struct mtk_rx_dma_v2),
@@ -1547,6 +2054,7 @@ static const struct mtk_soc_data mt7981_data = {
 
 static const struct mtk_soc_data mt7629_data = {
 	.ana_rgc3 = 0x128,
+	.gdma_count = 2,
 	.pdma_base = PDMA_V1_BASE,
 	.txd_size = sizeof(struct mtk_tx_dma),
 	.rxd_size = sizeof(struct mtk_rx_dma),
@@ -1554,6 +2062,7 @@ static const struct mtk_soc_data mt7629_data = {
 
 static const struct mtk_soc_data mt7623_data = {
 	.caps = MT7623_CAPS,
+	.gdma_count = 2,
 	.pdma_base = PDMA_V1_BASE,
 	.txd_size = sizeof(struct mtk_tx_dma),
 	.rxd_size = sizeof(struct mtk_rx_dma),
@@ -1561,6 +2070,7 @@ static const struct mtk_soc_data mt7623_data = {
 
 static const struct mtk_soc_data mt7622_data = {
 	.ana_rgc3 = 0x2028,
+	.gdma_count = 2,
 	.pdma_base = PDMA_V1_BASE,
 	.txd_size = sizeof(struct mtk_tx_dma),
 	.rxd_size = sizeof(struct mtk_rx_dma),
@@ -1568,12 +2078,14 @@ static const struct mtk_soc_data mt7622_data = {
 
 static const struct mtk_soc_data mt7621_data = {
 	.caps = MT7621_CAPS,
+	.gdma_count = 2,
 	.pdma_base = PDMA_V1_BASE,
 	.txd_size = sizeof(struct mtk_tx_dma),
 	.rxd_size = sizeof(struct mtk_rx_dma),
 };
 
 static const struct udevice_id mtk_eth_ids[] = {
+	{ .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data },
 	{ .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
 	{ .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
 	{ .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h
index 1382ccbeb2..491cac56a8 100644
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -15,35 +15,53 @@
 enum mkt_eth_capabilities {
 	MTK_TRGMII_BIT,
 	MTK_TRGMII_MT7621_CLK_BIT,
+	MTK_U3_COPHY_V2_BIT,
+	MTK_INFRA_BIT,
 	MTK_NETSYS_V2_BIT,
+	MTK_NETSYS_V3_BIT,
 
 	/* PATH BITS */
 	MTK_ETH_PATH_GMAC1_TRGMII_BIT,
+	MTK_ETH_PATH_GMAC2_SGMII_BIT,
 };
 
 #define MTK_TRGMII			BIT(MTK_TRGMII_BIT)
 #define MTK_TRGMII_MT7621_CLK		BIT(MTK_TRGMII_MT7621_CLK_BIT)
+#define MTK_U3_COPHY_V2			BIT(MTK_U3_COPHY_V2_BIT)
+#define MTK_INFRA			BIT(MTK_INFRA_BIT)
 #define MTK_NETSYS_V2			BIT(MTK_NETSYS_V2_BIT)
+#define MTK_NETSYS_V3			BIT(MTK_NETSYS_V3_BIT)
 
 /* Supported path present on SoCs */
 #define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
 
+#define MTK_ETH_PATH_GMAC2_SGMII	BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
+
 #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
 
+#define MTK_GMAC2_U3_QPHY	(MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA)
+
 #define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))
 
 #define MT7621_CAPS  (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
 
 #define MT7623_CAPS  (MTK_GMAC1_TRGMII)
 
+#define MT7981_CAPS  (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
+
 #define MT7986_CAPS  (MTK_NETSYS_V2)
 
+#define MT7988_CAPS  (MTK_NETSYS_V3 | MTK_INFRA)
+
 /* Frame Engine Register Bases */
 #define PDMA_V1_BASE			0x0800
 #define PDMA_V2_BASE			0x6000
+#define PDMA_V3_BASE			0x6800
 #define GDMA1_BASE			0x0500
 #define GDMA2_BASE			0x1500
+#define GDMA3_BASE			0x0540
 #define GMAC_BASE			0x10000
+#define GSW_BASE			0x20000
 
 /* Ethernet subsystem registers */
 
@@ -56,6 +74,16 @@ enum mkt_eth_capabilities {
 #define ETHSYS_CLKCFG0_REG		0x2c
 #define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
 
+/* Top misc registers */
+#define TOPMISC_NETSYS_PCS_MUX		0x84
+#define NETSYS_PCS_MUX_MASK		GENMASK(1, 0)
+#define MUX_G2_USXGMII_SEL		BIT(1)
+#define MUX_HSGMII1_G1_SEL		BIT(0)
+
+#define USB_PHY_SWITCH_REG		0x218
+#define QPHY_SEL_MASK			0x3
+#define SGMII_QPHY_SEL			0x2
+
 /* SYSCFG0_GE_MODE: GE Modes */
 #define GE_MODE_RGMII			0
 #define GE_MODE_MII			1
@@ -69,6 +97,7 @@ enum mkt_eth_capabilities {
 #define SGMII_AN_RESTART		BIT(9)
 
 #define SGMSYS_SGMII_MODE		0x20
+#define SGMII_AN_MODE			0x31120103
 #define SGMII_FORCE_MODE		0x31120019
 
 #define SGMSYS_QPHY_PWR_STATE_CTRL	0xe8
@@ -81,7 +110,19 @@ enum mkt_eth_capabilities {
 #define SGMSYS_GEN2_SPEED_V2		0x128
 #define SGMSYS_SPEED_2500		BIT(2)
 
+/* USXGMII subsystem config registers */
+/* Register to control USXGMII XFI PLL digital */
+#define XFI_PLL_DIG_GLB8		0x08
+#define RG_XFI_PLL_EN			BIT(31)
+
+/* Register to control USXGMII XFI PLL analog */
+#define XFI_PLL_ANA_GLB8		0x108
+#define RG_XFI_PLL_ANA_SWWA		0x02283248
+
 /* Frame Engine Registers */
+#define PSE_NO_DROP_CFG_REG		0x108
+#define PSE_NO_DROP_GDM1		BIT(1)
+
 #define FE_GLO_MISC_REG			0x124
 #define PDMA_VER_V2			BIT(4)
 
@@ -122,6 +163,9 @@ enum mkt_eth_capabilities {
 #define UN_DP_S				0
 #define UN_DP_M				0x0f
 
+#define GDMA_EG_CTRL_REG		0x004
+#define GDMA_CPU_BRIDGE_EN		BIT(31)
+
 #define GDMA_MAC_LSB_REG		0x008
 
 #define GDMA_MAC_MSB_REG		0x00c
@@ -149,6 +193,17 @@ enum mkt_eth_capabilities {
 #define MDIO_RW_DATA_S			0
 #define MDIO_RW_DATA_M			0xffff
 
+#define GMAC_XGMAC_STS_REG		0x000c
+#define P1_XGMAC_FORCE_LINK		BIT(15)
+
+#define GMAC_MAC_MISC_REG		0x0010
+
+#define GMAC_GSW_CFG_REG		0x0080
+#define GSWTX_IPG_M			0xF0000
+#define GSWTX_IPG_S			16
+#define GSWRX_IPG_M			0xF
+#define GSWRX_IPG_S			0
+
 /* MDIO_CMD: MDIO commands */
 #define MDIO_CMD_ADDR			0
 #define MDIO_CMD_WRITE			1
@@ -168,6 +223,7 @@ enum mkt_eth_capabilities {
 #define FORCE_MODE			BIT(15)
 #define MAC_TX_EN			BIT(14)
 #define MAC_RX_EN			BIT(13)
+#define DEL_RXFIFO_CLR			BIT(12)
 #define BKOFF_EN			BIT(9)
 #define BACKPR_EN			BIT(8)
 #define FORCE_RX_FC			BIT(5)
@@ -203,6 +259,16 @@ enum mkt_eth_capabilities {
 #define TD_DM_DRVP_S			0
 #define TD_DM_DRVP_M			0x0f
 
+/* XGMAC Status Registers */
+#define XGMAC_STS(x)			(((x) == 2) ? 0x001C : 0x000C)
+#define XGMAC_FORCE_LINK		BIT(15)
+
+/* XGMAC Registers */
+#define XGMAC_PORT_MCR(x)		(0x2000 + (((x) - 1) * 0x1000))
+#define XGMAC_TRX_DISABLE		0xf
+#define XGMAC_FORCE_TX_FC		BIT(5)
+#define XGMAC_FORCE_RX_FC		BIT(4)
+
 /* MT7530 Registers */
 
 #define PCR_REG(p)			(0x2004 + (p) * 0x100)
@@ -236,6 +302,9 @@ enum mkt_eth_capabilities {
 					FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
 					FORCE_MODE_DPX   | FORCE_MODE_SPD | \
 					FORCE_MODE_LNK
+#define MT7988_FORCE_MODE		FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
+					FORCE_MODE_DPX   | FORCE_MODE_SPD | \
+					FORCE_MODE_LNK
 
 /* MT7531 SGMII Registers */
 #define MT7531_SGMII_REG_BASE		0x5000
diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c
index ad7b5b8e99..ecf8c28fe4 100644
--- a/drivers/net/pch_gbe.c
+++ b/drivers/net/pch_gbe.c
@@ -414,16 +414,13 @@ static int pch_gbe_phy_init(struct udevice *dev)
 	struct pch_gbe_priv *priv = dev_get_priv(dev);
 	struct eth_pdata *plat = dev_get_plat(dev);
 	struct phy_device *phydev;
-	int mask = 0xffffffff;
 
-	phydev = phy_find_by_mask(priv->bus, mask);
+	phydev = phy_connect(priv->bus, -1, dev, plat->phy_interface);
 	if (!phydev) {
 		printf("pch_gbe: cannot find the phy\n");
 		return -1;
 	}
 
-	phy_connect_dev(phydev, dev, plat->phy_interface);
-
 	phydev->supported &= PHY_GBIT_FEATURES;
 	phydev->advertising = phydev->supported;
 
diff --git a/drivers/net/pfe_eth/pfe_hw.c b/drivers/net/pfe_eth/pfe_hw.c
index 4db6f3158c..9f2f92d116 100644
--- a/drivers/net/pfe_eth/pfe_hw.c
+++ b/drivers/net/pfe_eth/pfe_hw.c
@@ -814,7 +814,7 @@ static inline void class_set_config(struct class_cfg *cfg)
 	writel(0x1, CLASS_AXI_CTRL);
 
 	/*Make Util AXI transactions non-bufferable */
-	/*Util is disabled in U-boot, do it from here */
+	/*Util is disabled in U-Boot, do it from here */
 	writel(0x1, UTIL_AXI_CTRL);
 }
 
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 24158776f5..0c3c39a550 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -220,6 +220,12 @@ config PHY_MICREL_KSZ8XXX
 
 endif # PHY_MICREL
 
+config PHY_MOTORCOMM
+	tristate "Motorcomm PHYs"
+	help
+	  Enables support for Motorcomm network PHYs.
+	  Currently supports the YT8531 Gigabit Ethernet PHYs.
+
 config PHY_MSCC
 	bool "Microsemi Corp Ethernet PHYs support"
 
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 85d17f109c..2487f366e1 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o
 obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
 obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
 obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
+obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o
 obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
 obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
 obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index fb9f1e4c70..0970449d0f 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -155,6 +155,18 @@ static int adin_ext_write(struct phy_device *phydev, const u32 regnum, const u16
 	return phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_DATA, val);
 }
 
+static int adin_extread(struct phy_device *phydev, int addr, int devaddr,
+			int regnum)
+{
+	return adin_ext_read(phydev, regnum);
+}
+
+static int adin_extwrite(struct phy_device *phydev, int addr,
+			 int devaddr, int regnum, u16 val)
+{
+	return adin_ext_write(phydev, regnum, val);
+}
+
 static int adin_config_clk_out(struct phy_device *phydev)
 {
 	ofnode node = phy_get_ofnode(phydev);
@@ -260,4 +272,6 @@ U_BOOT_PHY_DRIVER(ADIN1300) = {
 	.config = adin1300_config,
 	.startup = genphy_startup,
 	.shutdown = genphy_shutdown,
+	.readext = adin_extread,
+	.writeext = adin_extwrite,
 };
diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c
index a715e83db9..877a51c3d0 100644
--- a/drivers/net/phy/ethernet_id.c
+++ b/drivers/net/phy/ethernet_id.c
@@ -7,6 +7,8 @@
 
 #include <common.h>
 #include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
 #include <phy.h>
 #include <linux/delay.h>
 #include <asm/gpio.h>
@@ -17,6 +19,8 @@ struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev,
 	struct phy_device *phydev;
 	struct ofnode_phandle_args phandle_args;
 	struct gpio_desc gpio;
+	const char *node_name;
+	struct udevice *pdev;
 	ofnode node;
 	u32 id, assert, deassert;
 	u16 vendor, device;
@@ -72,5 +76,18 @@ struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev,
 	if (phydev)
 		phydev->node = node;
 
+	if (IS_ENABLED(CONFIG_DM_ETH_PHY) && ofnode_valid(node)) {
+		node_name = ofnode_get_name(node);
+		ret = device_bind_driver_to_node(dev, "eth_phy_generic_drv",
+						 node_name, node,
+						 &pdev);
+		if (ret)
+			return NULL;
+
+		ret = device_probe(pdev);
+		if (ret)
+			return NULL;
+	}
+
 	return phydev;
 }
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
new file mode 100644
index 0000000000..e822fd76f2
--- /dev/null
+++ b/drivers/net/phy/motorcomm.c
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Motorcomm 8531 PHY driver.
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <phy.h>
+#include <linux/bitfield.h>
+
+#define PHY_ID_YT8531				0x4f51e91b
+#define PHY_ID_MASK				GENMASK(31, 0)
+
+/* Extended Register's Address Offset Register */
+#define YTPHY_PAGE_SELECT			0x1E
+
+/* Extended Register's Data Register */
+#define YTPHY_PAGE_DATA			0x1F
+
+#define YTPHY_SYNCE_CFG_REG			0xA012
+
+#define YTPHY_DTS_OUTPUT_CLK_DIS		0
+#define YTPHY_DTS_OUTPUT_CLK_25M		25000000
+#define YTPHY_DTS_OUTPUT_CLK_125M		125000000
+
+#define YT8531_SCR_SYNCE_ENABLE		BIT(6)
+/* 1b0 output 25m clock   *default*
+ * 1b1 output 125m clock
+ */
+#define YT8531_SCR_CLK_FRE_SEL_125M		BIT(4)
+#define YT8531_SCR_CLK_SRC_MASK		GENMASK(3, 1)
+#define YT8531_SCR_CLK_SRC_PLL_125M		0
+#define YT8531_SCR_CLK_SRC_UTP_RX		1
+#define YT8531_SCR_CLK_SRC_SDS_RX		2
+#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL	3
+#define YT8531_SCR_CLK_SRC_REF_25M		4
+#define YT8531_SCR_CLK_SRC_SSC_25M		5
+
+/* 1b0 use original tx_clk_rgmii  *default*
+ * 1b1 use inverted tx_clk_rgmii.
+ */
+#define YT8531_RC1R_TX_CLK_SEL_INVERTED	BIT(14)
+#define YT8531_RC1R_RX_DELAY_MASK		GENMASK(13, 10)
+#define YT8531_RC1R_FE_TX_DELAY_MASK		GENMASK(7, 4)
+#define YT8531_RC1R_GE_TX_DELAY_MASK		GENMASK(3, 0)
+#define YT8531_RC1R_RGMII_0_000_NS		0
+#define YT8531_RC1R_RGMII_0_150_NS		1
+#define YT8531_RC1R_RGMII_0_300_NS		2
+#define YT8531_RC1R_RGMII_0_450_NS		3
+#define YT8531_RC1R_RGMII_0_600_NS		4
+#define YT8531_RC1R_RGMII_0_750_NS		5
+#define YT8531_RC1R_RGMII_0_900_NS		6
+#define YT8531_RC1R_RGMII_1_050_NS		7
+#define YT8531_RC1R_RGMII_1_200_NS		8
+#define YT8531_RC1R_RGMII_1_350_NS		9
+#define YT8531_RC1R_RGMII_1_500_NS		10
+#define YT8531_RC1R_RGMII_1_650_NS		11
+#define YT8531_RC1R_RGMII_1_800_NS		12
+#define YT8531_RC1R_RGMII_1_950_NS		13
+#define YT8531_RC1R_RGMII_2_100_NS		14
+#define YT8531_RC1R_RGMII_2_250_NS		15
+
+/* Phy gmii clock gating Register */
+#define YT8531_CLOCK_GATING_REG		0xC
+#define YT8531_CGR_RX_CLK_EN			BIT(12)
+
+/* Specific Status Register */
+#define YTPHY_SPECIFIC_STATUS_REG		0x11
+#define YTPHY_DUPLEX_MASK			BIT(13)
+#define YTPHY_DUPLEX_SHIFT			13
+#define YTPHY_SPEED_MODE_MASK			GENMASK(15, 14)
+#define YTPHY_SPEED_MODE_SHIFT			14
+
+#define YT8531_EXTREG_SLEEP_CONTROL1_REG	0x27
+#define YT8531_ESC1R_SLEEP_SW			BIT(15)
+#define YT8531_ESC1R_PLLON_SLP			BIT(14)
+
+#define YT8531_RGMII_CONFIG1_REG		0xA003
+
+#define YT8531_CHIP_CONFIG_REG			0xA001
+#define YT8531_CCR_SW_RST			BIT(15)
+/* 1b0 disable 1.9ns rxc clock delay  *default*
+ * 1b1 enable 1.9ns rxc clock delay
+ */
+#define YT8531_CCR_RXC_DLY_EN			BIT(8)
+#define YT8531_CCR_RXC_DLY_1_900_NS		1900
+
+/* bits in struct ytphy_plat_priv->flag */
+#define TX_CLK_ADJ_ENABLED			BIT(0)
+#define AUTO_SLEEP_DISABLED			BIT(1)
+#define KEEP_PLL_ENABLED			BIT(2)
+#define TX_CLK_10_INVERTED			BIT(3)
+#define TX_CLK_100_INVERTED			BIT(4)
+#define TX_CLK_1000_INVERTED			BIT(5)
+
+struct ytphy_plat_priv {
+	u32 rx_delay_ps;
+	u32 tx_delay_ps;
+	u32 clk_out_frequency;
+	u32 flag;
+};
+
+/**
+ * struct ytphy_cfg_reg_map - map a config value to a register value
+ * @cfg: value in device configuration
+ * @reg: value in the register
+ */
+struct ytphy_cfg_reg_map {
+	u32 cfg;
+	u32 reg;
+};
+
+static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = {
+	/* for tx delay / rx delay with YT8531_CCR_RXC_DLY_EN is not set. */
+	{ 0,	YT8531_RC1R_RGMII_0_000_NS },
+	{ 150,	YT8531_RC1R_RGMII_0_150_NS },
+	{ 300,	YT8531_RC1R_RGMII_0_300_NS },
+	{ 450,	YT8531_RC1R_RGMII_0_450_NS },
+	{ 600,	YT8531_RC1R_RGMII_0_600_NS },
+	{ 750,	YT8531_RC1R_RGMII_0_750_NS },
+	{ 900,	YT8531_RC1R_RGMII_0_900_NS },
+	{ 1050,	YT8531_RC1R_RGMII_1_050_NS },
+	{ 1200,	YT8531_RC1R_RGMII_1_200_NS },
+	{ 1350,	YT8531_RC1R_RGMII_1_350_NS },
+	{ 1500,	YT8531_RC1R_RGMII_1_500_NS },
+	{ 1650,	YT8531_RC1R_RGMII_1_650_NS },
+	{ 1800,	YT8531_RC1R_RGMII_1_800_NS },
+	{ 1950,	YT8531_RC1R_RGMII_1_950_NS },	/* default tx/rx delay */
+	{ 2100,	YT8531_RC1R_RGMII_2_100_NS },
+	{ 2250,	YT8531_RC1R_RGMII_2_250_NS },
+
+	/* only for rx delay with YT8531_CCR_RXC_DLY_EN is set. */
+	{ 0    + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_0_000_NS },
+	{ 150  + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_0_150_NS },
+	{ 300  + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_0_300_NS },
+	{ 450  + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_0_450_NS },
+	{ 600  + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_0_600_NS },
+	{ 750  + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_0_750_NS },
+	{ 900  + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_0_900_NS },
+	{ 1050 + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_1_050_NS },
+	{ 1200 + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_1_200_NS },
+	{ 1350 + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_1_350_NS },
+	{ 1500 + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_1_500_NS },
+	{ 1650 + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_1_650_NS },
+	{ 1800 + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_1_800_NS },
+	{ 1950 + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_1_950_NS },
+	{ 2100 + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_2_100_NS },
+	{ 2250 + YT8531_CCR_RXC_DLY_1_900_NS,	YT8531_RC1R_RGMII_2_250_NS }
+};
+
+static u32 ytphy_get_delay_reg_value(struct phy_device *phydev,
+				     u32 val,
+				     u16 *rxc_dly_en)
+{
+	int tb_size = ARRAY_SIZE(ytphy_rgmii_delays);
+	int tb_size_half = tb_size / 2;
+	int i;
+
+	/* when rxc_dly_en is NULL, it is get the delay for tx, only half of
+	 * tb_size is valid.
+	 */
+	if (!rxc_dly_en)
+		tb_size = tb_size_half;
+
+	for (i = 0; i < tb_size; i++) {
+		if (ytphy_rgmii_delays[i].cfg == val) {
+			if (rxc_dly_en && i < tb_size_half)
+				*rxc_dly_en = 0;
+			return ytphy_rgmii_delays[i].reg;
+		}
+	}
+
+	pr_warn("Unsupported value %d, using default (%u)\n",
+		val, YT8531_RC1R_RGMII_1_950_NS);
+
+	/* when rxc_dly_en is not NULL, it is get the delay for rx.
+	 * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps,
+	 * so YT8531_CCR_RXC_DLY_EN should not be set.
+	 */
+	if (rxc_dly_en)
+		*rxc_dly_en = 0;
+
+	return YT8531_RC1R_RGMII_1_950_NS;
+}
+
+static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask,
+			    u16 set)
+{
+	int ret;
+
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_SELECT, regnum);
+	if (ret < 0)
+		return ret;
+
+	return phy_modify(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_DATA, mask, set);
+}
+
+static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev)
+{
+	struct ytphy_plat_priv	*priv = phydev->priv;
+	u16 rxc_dly_en = YT8531_CCR_RXC_DLY_EN;
+	u32 rx_reg, tx_reg;
+	u16 mask, val = 0;
+	int ret;
+
+	rx_reg = ytphy_get_delay_reg_value(phydev, priv->rx_delay_ps,
+					   &rxc_dly_en);
+	tx_reg = ytphy_get_delay_reg_value(phydev, priv->tx_delay_ps,
+					   NULL);
+
+	switch (phydev->interface) {
+	case PHY_INTERFACE_MODE_RGMII:
+		rxc_dly_en = 0;
+		break;
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+		val |= FIELD_PREP(YT8531_RC1R_RX_DELAY_MASK, rx_reg);
+		break;
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		rxc_dly_en = 0;
+		val |= FIELD_PREP(YT8531_RC1R_GE_TX_DELAY_MASK, tx_reg);
+		break;
+	case PHY_INTERFACE_MODE_RGMII_ID:
+		val |= FIELD_PREP(YT8531_RC1R_RX_DELAY_MASK, rx_reg) |
+		       FIELD_PREP(YT8531_RC1R_GE_TX_DELAY_MASK, tx_reg);
+		break;
+	default: /* do not support other modes */
+		return -EOPNOTSUPP;
+	}
+
+	ret = ytphy_modify_ext(phydev, YT8531_CHIP_CONFIG_REG,
+			       YT8531_CCR_RXC_DLY_EN, rxc_dly_en);
+	if (ret < 0)
+		return ret;
+
+	/* Generally, it is not necessary to adjust YT8531_RC1R_FE_TX_DELAY */
+	mask = YT8531_RC1R_RX_DELAY_MASK | YT8531_RC1R_GE_TX_DELAY_MASK;
+	return ytphy_modify_ext(phydev, YT8531_RGMII_CONFIG1_REG, mask, val);
+}
+
+static int yt8531_parse_status(struct phy_device *phydev)
+{
+	int val;
+	int speed, speed_mode;
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, YTPHY_SPECIFIC_STATUS_REG);
+	if (val < 0)
+		return val;
+
+	speed_mode = (val & YTPHY_SPEED_MODE_MASK) >> YTPHY_SPEED_MODE_SHIFT;
+	switch (speed_mode) {
+	case 2:
+		speed = SPEED_1000;
+		break;
+	case 1:
+		speed = SPEED_100;
+		break;
+	default:
+		speed = SPEED_10;
+		break;
+	}
+
+	phydev->speed = speed;
+	phydev->duplex = (val & YTPHY_DUPLEX_MASK) >> YTPHY_DUPLEX_SHIFT;
+
+	return 0;
+}
+
+static int yt8531_startup(struct phy_device *phydev)
+{
+	struct ytphy_plat_priv	*priv = phydev->priv;
+	u16 val = 0;
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	ret = yt8531_parse_status(phydev);
+	if (ret)
+		return ret;
+
+	if (phydev->speed < 0)
+		return -EINVAL;
+
+	if (!(priv->flag & TX_CLK_ADJ_ENABLED))
+		return 0;
+
+	switch (phydev->speed) {
+	case SPEED_1000:
+		if (priv->flag & TX_CLK_1000_INVERTED)
+			val = YT8531_RC1R_TX_CLK_SEL_INVERTED;
+		break;
+	case SPEED_100:
+		if (priv->flag & TX_CLK_100_INVERTED)
+			val = YT8531_RC1R_TX_CLK_SEL_INVERTED;
+		break;
+	case SPEED_10:
+		if (priv->flag & TX_CLK_10_INVERTED)
+			val = YT8531_RC1R_TX_CLK_SEL_INVERTED;
+		break;
+	default:
+		printf("UNKNOWN SPEED\n");
+		return -EINVAL;
+	}
+
+	ret = ytphy_modify_ext(phydev, YT8531_RGMII_CONFIG1_REG,
+			       YT8531_RC1R_TX_CLK_SEL_INVERTED, val);
+	if (ret < 0)
+		pr_warn("Modify TX_CLK_SEL err:%d\n", ret);
+
+	return 0;
+}
+
+static void ytphy_dt_parse(struct phy_device *phydev)
+{
+	struct ytphy_plat_priv	*priv = phydev->priv;
+
+	priv->clk_out_frequency = ofnode_read_u32_default(phydev->node,
+							  "motorcomm,clk-out-frequency-hz",
+							  YTPHY_DTS_OUTPUT_CLK_DIS);
+	priv->rx_delay_ps = ofnode_read_u32_default(phydev->node,
+						    "rx-internal-delay-ps",
+						    YT8531_RC1R_RGMII_1_950_NS);
+	priv->tx_delay_ps = ofnode_read_u32_default(phydev->node,
+						    "tx-internal-delay-ps",
+						    YT8531_RC1R_RGMII_1_950_NS);
+
+	if (ofnode_read_bool(phydev->node, "motorcomm,auto-sleep-disabled"))
+		priv->flag |= AUTO_SLEEP_DISABLED;
+
+	if (ofnode_read_bool(phydev->node, "motorcomm,keep-pll-enabled"))
+		priv->flag |= KEEP_PLL_ENABLED;
+
+	if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-adj-enabled"))
+		priv->flag |= TX_CLK_ADJ_ENABLED;
+
+	if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-10-inverted"))
+		priv->flag |= TX_CLK_10_INVERTED;
+
+	if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-100-inverted"))
+		priv->flag |= TX_CLK_100_INVERTED;
+
+	if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-1000-inverted"))
+		priv->flag |= TX_CLK_1000_INVERTED;
+}
+
+static int yt8531_config(struct phy_device *phydev)
+{
+	struct ytphy_plat_priv	*priv = phydev->priv;
+	u16 mask, val;
+	int ret;
+
+	ret = genphy_config_aneg(phydev);
+	if (ret < 0)
+		return ret;
+
+	ytphy_dt_parse(phydev);
+	switch (priv->clk_out_frequency) {
+	case YTPHY_DTS_OUTPUT_CLK_DIS:
+		mask = YT8531_SCR_SYNCE_ENABLE;
+		val = 0;
+		break;
+	case YTPHY_DTS_OUTPUT_CLK_25M:
+		mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
+			   YT8531_SCR_CLK_FRE_SEL_125M;
+		val = YT8531_SCR_SYNCE_ENABLE |
+			  FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
+				     YT8531_SCR_CLK_SRC_REF_25M);
+		break;
+	case YTPHY_DTS_OUTPUT_CLK_125M:
+		mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
+			   YT8531_SCR_CLK_FRE_SEL_125M;
+		val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M |
+			  FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
+				     YT8531_SCR_CLK_SRC_PLL_125M);
+		break;
+	default:
+		pr_warn("Freq err:%u\n", priv->clk_out_frequency);
+		return -EINVAL;
+	}
+
+	ret = ytphy_modify_ext(phydev, YTPHY_SYNCE_CFG_REG, mask,
+			       val);
+	if (ret < 0)
+		return ret;
+
+	ret = ytphy_rgmii_clk_delay_config(phydev);
+	if (ret < 0)
+		return ret;
+
+	if (priv->flag & AUTO_SLEEP_DISABLED) {
+		/* disable auto sleep */
+		ret = ytphy_modify_ext(phydev,
+				       YT8531_EXTREG_SLEEP_CONTROL1_REG,
+				       YT8531_ESC1R_SLEEP_SW, 0);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (priv->flag & KEEP_PLL_ENABLED) {
+		/* enable RXC clock when no wire plug */
+		ret = ytphy_modify_ext(phydev,
+				       YT8531_CLOCK_GATING_REG,
+				       YT8531_CGR_RX_CLK_EN, 0);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int yt8531_probe(struct phy_device *phydev)
+{
+	struct ytphy_plat_priv	*priv;
+
+	priv = calloc(1, sizeof(struct ytphy_plat_priv));
+	if (!priv)
+		return -ENOMEM;
+
+	phydev->priv = priv;
+
+	return 0;
+}
+
+U_BOOT_PHY_DRIVER(motorcomm8531) = {
+	.name          = "YT8531 Gigabit Ethernet",
+	.uid           = PHY_ID_YT8531,
+	.mask          = PHY_ID_MASK,
+	.features      = PHY_GBIT_FEATURES,
+	.probe	       = &yt8531_probe,
+	.config        = &yt8531_config,
+	.startup       = &yt8531_startup,
+	.shutdown      = &genphy_shutdown,
+};
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 0eeb0cb3a8..ae21acb059 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -812,8 +812,8 @@ struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask)
 	return get_phy_device_by_mask(bus, phy_mask);
 }
 
-void phy_connect_dev(struct phy_device *phydev, struct udevice *dev,
-		     phy_interface_t interface)
+static void phy_connect_dev(struct phy_device *phydev, struct udevice *dev,
+			    phy_interface_t interface)
 {
 	/* Soft Reset the PHY */
 	phy_reset(phydev);
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index c74c8a81f9..0bcd6cfd3f 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -131,7 +131,6 @@ struct ravb_priv {
 	struct mii_dev		*bus;
 	void __iomem		*iobase;
 	struct clk_bulk		clks;
-	struct gpio_desc	reset_gpio;
 };
 
 static inline void ravb_flush_dcache(u32 addr, u32 len)
@@ -312,13 +311,6 @@ static int ravb_phy_config(struct udevice *dev)
 	struct phy_device *phydev;
 	int reg;
 
-	if (dm_gpio_is_valid(&eth->reset_gpio)) {
-		dm_gpio_set_value(&eth->reset_gpio, 1);
-		mdelay(20);
-		dm_gpio_set_value(&eth->reset_gpio, 0);
-		mdelay(1);
-	}
-
 	phydev = phy_connect(eth->bus, -1, dev, pdata->phy_interface);
 	if (!phydev)
 		return -ENODEV;
@@ -503,7 +495,6 @@ static int ravb_probe(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_plat(dev);
 	struct ravb_priv *eth = dev_get_priv(dev);
-	struct ofnode_phandle_args phandle_args;
 	struct mii_dev *mdiodev;
 	void __iomem *iobase;
 	int ret;
@@ -515,17 +506,6 @@ static int ravb_probe(struct udevice *dev)
 	if (ret < 0)
 		goto err_mdio_alloc;
 
-	ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args);
-	if (!ret) {
-		gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
-					   &eth->reset_gpio, GPIOD_IS_OUT);
-	}
-
-	if (!dm_gpio_is_valid(&eth->reset_gpio)) {
-		gpio_request_by_name(dev, "reset-gpios", 0, &eth->reset_gpio,
-				     GPIOD_IS_OUT);
-	}
-
 	mdiodev = mdio_alloc();
 	if (!mdiodev) {
 		ret = -ENOMEM;
@@ -576,8 +556,6 @@ static int ravb_remove(struct udevice *dev)
 	free(eth->phydev);
 	mdio_unregister(eth->bus);
 	mdio_free(eth->bus);
-	if (dm_gpio_is_valid(&eth->reset_gpio))
-		dm_gpio_free(dev, &eth->reset_gpio);
 	unmap_physmem(eth->iobase, MAP_NOCACHE);
 
 	return 0;
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 2276a465e7..963702777c 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -96,12 +96,12 @@ static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
 #define TX_TIMEOUT  (6*HZ)
 
 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
-#define RTL_W8(reg, val8)	writeb((val8), ioaddr + (reg))
-#define RTL_W16(reg, val16)	writew((val16), ioaddr + (reg))
-#define RTL_W32(reg, val32)	writel((val32), ioaddr + (reg))
-#define RTL_R8(reg)		readb(ioaddr + (reg))
-#define RTL_R16(reg)		readw(ioaddr + (reg))
-#define RTL_R32(reg)		readl(ioaddr + (reg))
+#define RTL_W8(reg, val8)	writeb((val8), (void *)(ioaddr + (reg)))
+#define RTL_W16(reg, val16)	writew((val16), (void *)(ioaddr + (reg)))
+#define RTL_W32(reg, val32)	writel((val32), (void *)(ioaddr + (reg)))
+#define RTL_R8(reg)		readb((void *)(ioaddr + (reg)))
+#define RTL_R16(reg)		readw((void *)(ioaddr + (reg)))
+#define RTL_R32(reg)		readl((void *)(ioaddr + (reg)))
 
 #define bus_to_phys(a)	pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
 	(pci_addr_t)(unsigned long)a)
@@ -311,10 +311,12 @@ static unsigned char rxdata[RX_BUF_LEN];
  *
  * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
  * the driver to allocate descriptors from a pool of non-cached memory.
+ *
+ * Hardware maintain D-cache coherency in RISC-V architecture.
  */
 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
-	!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+	!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86) && !defined(CONFIG_RISCV)
 #warning cache-line size is larger than descriptor size
 #endif
 #endif
@@ -351,10 +353,11 @@ static const unsigned int rtl8169_rx_config =
     (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 
 static struct pci_device_id supported[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
-	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) },
 	{}
 };
 
@@ -1049,8 +1052,9 @@ static int rtl8169_eth_probe(struct udevice *dev)
 	int ret;
 
 	switch (pplat->device) {
-	case 0x8168:
 	case 0x8125:
+	case 0x8161:
+	case 0x8168:
 		region = 2;
 		break;
 	default:
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 8f162ca58f..7b1f59dc49 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -129,11 +129,11 @@ static int sh_eth_recv_start(struct sh_eth_dev *eth)
 	/* Check if the rx descriptor is ready */
 	invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 	if (port_info->rx_desc_cur->rd0 & RD_RACT)
-		return -EINVAL;
+		return -EAGAIN;
 
 	/* Check for errors */
 	if (port_info->rx_desc_cur->rd0 & RD_RFE)
-		return -EINVAL;
+		return 0;
 
 	return port_info->rx_desc_cur->rd1 & 0xffff;
 }
@@ -142,6 +142,8 @@ static void sh_eth_recv_finish(struct sh_eth_dev *eth)
 {
 	struct sh_eth_info *port_info = &eth->port_info[eth->port];
 
+	invalidate_cache(ADDR_TO_P2(port_info->rx_desc_cur->rd2), MAX_BUF_SIZE);
+
 	/* Make current descriptor available again */
 	if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 		port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
@@ -210,8 +212,6 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 		goto err;
 	}
 
-	flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
-
 	/* Make sure we use a P2 address (non-cacheable) */
 	port_info->tx_desc_base =
 		(struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
@@ -229,6 +229,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 	cur_tx_desc--;
 	cur_tx_desc->td0 |= TD_TDLE;
 
+	flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
 	/*
 	 * Point the controller to the tx descriptor list. Must use physical
 	 * addresses
@@ -264,8 +265,6 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 		goto err;
 	}
 
-	flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
-
 	/* Make sure we use a P2 address (non-cacheable) */
 	port_info->rx_desc_base =
 		(struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
@@ -299,6 +298,9 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 	cur_rx_desc--;
 	cur_rx_desc->rd0 |= RD_RDLE;
 
+	invalidate_cache(port_info->rx_buf_alloc, NUM_RX_DESC * MAX_BUF_SIZE);
+	flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
+
 	/* Point the controller to the rx descriptor list */
 	sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
@@ -530,7 +532,6 @@ struct sh_ether_priv {
 	struct mii_dev		*bus;
 	phys_addr_t		iobase;
 	struct clk		clk;
-	struct gpio_desc	reset_gpio;
 };
 
 static int sh_ether_send(struct udevice *dev, void *packet, int len)
@@ -555,15 +556,13 @@ static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
 		*packetp = packet;
 
 		return len;
-	} else {
-		len = 0;
+	}
 
-		/* Restart the receiver if disabled */
-		if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
-			sh_eth_write(port_info, EDRRR_R, EDRRR);
+	/* Restart the receiver if disabled */
+	if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
+		sh_eth_write(port_info, EDRRR_R, EDRRR);
 
-		return -EAGAIN;
-	}
+	return len;
 }
 
 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
@@ -601,14 +600,11 @@ static int sh_eth_phy_config(struct udevice *dev)
 	int ret = 0;
 	struct sh_eth_info *port_info = &eth->port_info[eth->port];
 	struct phy_device *phydev;
-	int mask = 0xffffffff;
 
-	phydev = phy_find_by_mask(priv->bus, mask);
+	phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface);
 	if (!phydev)
 		return -ENODEV;
 
-	phy_connect_dev(phydev, dev, pdata->phy_interface);
-
 	port_info->phydev = phydev;
 	phy_config(phydev);
 
@@ -653,7 +649,6 @@ static int sh_ether_probe(struct udevice *udev)
 	struct eth_pdata *pdata = dev_get_plat(udev);
 	struct sh_ether_priv *priv = dev_get_priv(udev);
 	struct sh_eth_dev *eth = &priv->shdev;
-	struct ofnode_phandle_args phandle_args;
 	struct mii_dev *mdiodev;
 	int ret;
 
@@ -664,18 +659,6 @@ static int sh_ether_probe(struct udevice *udev)
 	if (ret < 0)
 		return ret;
 #endif
-
-	ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
-	if (!ret) {
-		gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
-					   &priv->reset_gpio, GPIOD_IS_OUT);
-	}
-
-	if (!dm_gpio_is_valid(&priv->reset_gpio)) {
-		gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
-				     GPIOD_IS_OUT);
-	}
-
 	mdiodev = mdio_alloc();
 	if (!mdiodev) {
 		ret = -ENOMEM;
@@ -738,9 +721,6 @@ static int sh_ether_remove(struct udevice *udev)
 	mdio_unregister(priv->bus);
 	mdio_free(priv->bus);
 
-	if (dm_gpio_is_valid(&priv->reset_gpio))
-		dm_gpio_free(udev, &priv->reset_gpio);
-
 	return 0;
 }
 
diff --git a/drivers/net/sni_ave.c b/drivers/net/sni_ave.c
index 014b070d9e..f5a0d80af7 100644
--- a/drivers/net/sni_ave.c
+++ b/drivers/net/sni_ave.c
@@ -391,14 +391,12 @@ static int ave_mdiobus_init(struct ave_private *priv, const char *name)
 static int ave_phy_init(struct ave_private *priv, void *dev)
 {
 	struct phy_device *phydev;
-	int mask = GENMASK(31, 0), ret;
+	int ret;
 
-	phydev = phy_find_by_mask(priv->bus, mask);
+	phydev = phy_connect(priv->bus, -1, dev, priv->phy_mode);
 	if (!phydev)
 		return -ENODEV;
 
-	phy_connect_dev(phydev, dev, priv->phy_mode);
-
 	phydev->supported &= PHY_GBIT_FEATURES;
 	if (priv->max_speed) {
 		ret = phy_set_supported(phydev, priv->max_speed);
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index ad9e1abd16..4c90d4b498 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -248,10 +248,10 @@ static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 
 static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
 {
-	int ret, mask = 0xffffffff;
+	int ret, mask = -1;
 
 #ifdef CONFIG_PHY_ADDR
-	mask = 1 << CONFIG_PHY_ADDR;
+	mask = CONFIG_PHY_ADDR;
 #endif
 
 	priv->bus = mdio_alloc();
@@ -269,11 +269,10 @@ static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
 	if (ret)
 		return ret;
 
-	priv->phydev = phy_find_by_mask(priv->bus, mask);
+	priv->phydev = phy_connect(priv->bus, mask, dev, PHY_INTERFACE_MODE_MII);
 	if (!priv->phydev)
 		return -ENODEV;
 
-	phy_connect_dev(priv->phydev, dev, PHY_INTERFACE_MODE_MII);
 	phy_config(priv->phydev);
 
 	return 0;
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index e13dbc9401..02660e4fbb 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -41,8 +41,10 @@ endchoice
 config TI_AM65_CPSW_NUSS
 	bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver"
 	depends on ARCH_K3
+	imply DM_MDIO
 	imply MISC_INIT_R
 	imply MISC
+	imply SYSCON
 	select PHYLIB
 	help
 	  This driver supports TI K3 MCU CPSW Nuss Ethernet controller
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index f674b0baa3..51a8167d14 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -15,13 +15,16 @@
 #include <dm.h>
 #include <dm/device_compat.h>
 #include <dm/lists.h>
+#include <dm/pinctrl.h>
 #include <dma-uclass.h>
 #include <dm/of_access.h>
 #include <miiphy.h>
 #include <net.h>
 #include <phy.h>
 #include <power-domain.h>
+#include <regmap.h>
 #include <soc.h>
+#include <syscon.h>
 #include <linux/bitops.h>
 #include <linux/soc/ti/ti-udma.h>
 
@@ -100,8 +103,6 @@ struct am65_cpsw_common {
 	fdt_addr_t		cpsw_base;
 	fdt_addr_t		mdio_base;
 	fdt_addr_t		ale_base;
-	fdt_addr_t		gmii_sel;
-	fdt_addr_t		mac_efuse;
 
 	struct clk		fclk;
 	struct power_domain	pwrdmn;
@@ -223,23 +224,45 @@ out:
 	return phy->link;
 }
 
+#define AM65_GMII_SEL_PORT_OFFS(x)	(0x4 * ((x) - 1))
+
 #define AM65_GMII_SEL_MODE_MII		0
 #define AM65_GMII_SEL_MODE_RMII		1
 #define AM65_GMII_SEL_MODE_RGMII	2
 
 #define AM65_GMII_SEL_RGMII_IDMODE	BIT(4)
 
-static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
-				  phy_interface_t phy_mode, int slave)
+static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
+				 phy_interface_t phy_mode)
 {
-	struct am65_cpsw_common	*common = priv->cpsw_common;
-	u32 reg;
-	u32 mode = 0;
+	struct udevice *dev = priv->dev;
+	u32 offset, reg, phandle;
 	bool rgmii_id = false;
+	fdt_addr_t gmii_sel;
+	u32 mode = 0;
+	ofnode node;
+	int ret;
+
+	ret = ofnode_read_u32(dev_ofnode(dev), "phys", &phandle);
+	if (ret)
+		return ret;
+
+	ret = ofnode_read_u32_index(dev_ofnode(dev), "phys", 1, &offset);
+	if (ret)
+		return ret;
 
-	reg = readl(common->gmii_sel);
+	node = ofnode_get_by_phandle(phandle);
+	if (!ofnode_valid(node))
+		return -ENODEV;
+
+	gmii_sel = ofnode_get_addr(node);
+	if (gmii_sel == FDT_ADDR_T_NONE)
+		return -ENODEV;
 
-	dev_dbg(common->dev, "old gmii_sel: %08x\n", reg);
+	gmii_sel += AM65_GMII_SEL_PORT_OFFS(offset);
+	reg = readl(gmii_sel);
+
+	dev_dbg(dev, "old gmii_sel: %08x\n", reg);
 
 	switch (phy_mode) {
 	case PHY_INTERFACE_MODE_RMII:
@@ -258,7 +281,7 @@ static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
 		break;
 
 	default:
-		dev_warn(common->dev,
+		dev_warn(dev,
 			 "Unsupported PHY mode: %u. Defaulting to MII.\n",
 			 phy_mode);
 		/* fallthrough */
@@ -271,15 +294,19 @@ static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
 		mode |= AM65_GMII_SEL_RGMII_IDMODE;
 
 	reg = mode;
-	dev_dbg(common->dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n",
+	dev_dbg(dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n",
 		phy_mode, reg);
-	writel(reg, common->gmii_sel);
+	writel(reg, gmii_sel);
 
-	reg = readl(common->gmii_sel);
-	if (reg != mode)
-		dev_err(common->dev,
+	reg = readl(gmii_sel);
+	if (reg != mode) {
+		dev_err(dev,
 			"gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n",
 			mode, reg);
+		return 0;
+	}
+
+	return 0;
 }
 
 static int am65_cpsw_start(struct udevice *dev)
@@ -513,24 +540,45 @@ static void am65_cpsw_stop(struct udevice *dev)
 	common->started = false;
 }
 
+static int am65_cpsw_am654_get_efuse_macid(struct udevice *dev,
+					   int slave, u8 *mac_addr)
+{
+	u32 mac_lo, mac_hi, offset;
+	struct regmap *syscon;
+	int ret;
+
+	syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-efuse");
+	if (IS_ERR(syscon)) {
+		if (PTR_ERR(syscon) == -ENODEV)
+			return 0;
+		return PTR_ERR(syscon);
+	}
+
+	ret = dev_read_u32_index(dev, "ti,syscon-efuse", 1, &offset);
+	if (ret)
+		return ret;
+
+	regmap_read(syscon, offset, &mac_lo);
+	regmap_read(syscon, offset + 4, &mac_hi);
+
+	mac_addr[0] = (mac_hi >> 8) & 0xff;
+	mac_addr[1] = mac_hi & 0xff;
+	mac_addr[2] = (mac_lo >> 24) & 0xff;
+	mac_addr[3] = (mac_lo >> 16) & 0xff;
+	mac_addr[4] = (mac_lo >> 8) & 0xff;
+	mac_addr[5] = mac_lo & 0xff;
+
+	return 0;
+}
+
 static int am65_cpsw_read_rom_hwaddr(struct udevice *dev)
 {
 	struct am65_cpsw_priv *priv = dev_get_priv(dev);
-	struct am65_cpsw_common *common = priv->cpsw_common;
 	struct eth_pdata *pdata = dev_get_plat(dev);
-	u32 mac_hi, mac_lo;
 
-	if (common->mac_efuse == FDT_ADDR_T_NONE)
-		return -1;
-
-	mac_lo = readl(common->mac_efuse);
-	mac_hi = readl(common->mac_efuse + 4);
-	pdata->enetaddr[0] = (mac_hi >> 8) & 0xff;
-	pdata->enetaddr[1] = mac_hi & 0xff;
-	pdata->enetaddr[2] = (mac_lo >> 24) & 0xff;
-	pdata->enetaddr[3] = (mac_lo >> 16) & 0xff;
-	pdata->enetaddr[4] = (mac_lo >> 8) & 0xff;
-	pdata->enetaddr[5] = mac_lo & 0xff;
+	am65_cpsw_am654_get_efuse_macid(dev,
+					priv->port_id,
+					pdata->enetaddr);
 
 	return 0;
 }
@@ -558,14 +606,62 @@ static const struct soc_attr k3_mdio_soc_data[] = {
 	{ /* sentinel */ },
 };
 
+static ofnode am65_cpsw_find_mdio(ofnode parent)
+{
+	ofnode node;
+
+	ofnode_for_each_subnode(node, parent)
+		if (ofnode_device_is_compatible(node, "ti,cpsw-mdio"))
+			return node;
+
+	return ofnode_null();
+}
+
+static int am65_cpsw_mdio_setup(struct udevice *dev)
+{
+	struct am65_cpsw_priv *priv = dev_get_priv(dev);
+	struct am65_cpsw_common	*cpsw_common = priv->cpsw_common;
+	struct udevice *mdio_dev;
+	ofnode mdio;
+	int ret;
+
+	mdio = am65_cpsw_find_mdio(dev_ofnode(cpsw_common->dev));
+	if (!ofnode_valid(mdio))
+		return 0;
+
+	/*
+	 * The MDIO controller is represented in the DT binding by a
+	 * subnode of the MAC controller.
+	 *
+	 * We don't have a DM driver for the MDIO device yet, and thus any
+	 * pinctrl setting on its node will be ignored.
+	 *
+	 * However, we do need to make sure the pins states tied to the
+	 * MDIO node are configured properly. Fortunately, the core DM
+	 * does that for use when we get a device, so we can work around
+	 * that whole issue by just requesting a dummy MDIO driver to
+	 * probe, and our pins will get muxed.
+	 */
+	ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdio_dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 static int am65_cpsw_mdio_init(struct udevice *dev)
 {
 	struct am65_cpsw_priv *priv = dev_get_priv(dev);
 	struct am65_cpsw_common	*cpsw_common = priv->cpsw_common;
+	int ret;
 
 	if (!priv->has_phy || cpsw_common->bus)
 		return 0;
 
+	ret = am65_cpsw_mdio_setup(dev);
+	if (ret)
+		return ret;
+
 	cpsw_common->bus = cpsw_mdio_init(dev->name,
 					  cpsw_common->mdio_base,
 					  cpsw_common->bus_freq,
@@ -683,7 +779,9 @@ static int am65_cpsw_port_probe(struct udevice *dev)
 	if (ret)
 		goto out;
 
-	am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id);
+	ret = am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface);
+	if (ret)
+		goto out;
 
 	ret = am65_cpsw_mdio_init(dev);
 	if (ret)
@@ -707,8 +805,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
 	cpsw_common->ss_base = dev_read_addr(dev);
 	if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
 		return -EINVAL;
-	cpsw_common->mac_efuse = devfdt_get_addr_name(dev, "mac_efuse");
-	/* no err check - optional */
 
 	ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
 	if (ret) {
@@ -780,19 +876,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
 				   AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
 	}
 
-	node = dev_read_subnode(dev, "cpsw-phy-sel");
-	if (!ofnode_valid(node)) {
-		dev_err(dev, "can't find cpsw-phy-sel\n");
-		ret = -ENOENT;
-		goto out;
-	}
-
-	cpsw_common->gmii_sel = ofnode_get_addr(node);
-	if (cpsw_common->gmii_sel == FDT_ADDR_T_NONE) {
-		dev_err(dev, "failed to get gmii_sel base\n");
-		goto out;
-	}
-
 	cpsw_common->bus_freq =
 			dev_read_u32_default(dev, "bus_freq",
 					     AM65_CPSW_MDIO_BUS_FREQ_DEF);
@@ -834,3 +917,14 @@ U_BOOT_DRIVER(am65_cpsw_nuss_port) = {
 	.plat_auto	= sizeof(struct eth_pdata),
 	.flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE,
 };
+
+static const struct udevice_id am65_cpsw_mdio_ids[] = {
+	{ .compatible = "ti,cpsw-mdio" },
+	{ }
+};
+
+U_BOOT_DRIVER(am65_cpsw_mdio) = {
+	.name		= "am65_cpsw_mdio",
+	.id		= UCLASS_MDIO,
+	.of_match	= am65_cpsw_mdio_ids,
+};
diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c
index 29d2fc9b54..034877a769 100644
--- a/drivers/net/ti/davinci_emac.c
+++ b/drivers/net/ti/davinci_emac.c
@@ -833,9 +833,9 @@ static int davinci_emac_probe(struct udevice *dev)
 #endif
 	}
 
-#if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 		defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
-			!defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE))
+			!defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
 	for (i = 0; i < num_phy; i++) {
 		if (phy[i].is_phy_connected(i))
 			phy[i].auto_negotiate(i);
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 3e9919993d..39cb3cc260 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -748,7 +748,7 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
 
 	/* Wait for an incoming packet */
 	if (!isrxready(priv))
-		return -1;
+		return -EAGAIN;
 
 	debug("axiemac: RX data ready\n");
 
diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c
index 6d15386c66..410fb25dde 100644
--- a/drivers/net/xilinx_axi_mrmac.c
+++ b/drivers/net/xilinx_axi_mrmac.c
@@ -3,7 +3,7 @@
  * Xilinx Multirate Ethernet MAC(MRMAC) driver
  *
  * Author(s):   Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
- *              Michal Simek <michal.simek@xilinx.com>
+ *              Michal Simek <michal.simek@amd.com>
  *
  * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
  */
diff --git a/drivers/net/xilinx_axi_mrmac.h b/drivers/net/xilinx_axi_mrmac.h
index 4f875857cf..e2c2105450 100644
--- a/drivers/net/xilinx_axi_mrmac.h
+++ b/drivers/net/xilinx_axi_mrmac.h
@@ -3,7 +3,7 @@
  * Xilinx Multirate Ethernet MAC(MRMAC) driver
  *
  * Author(s):   Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
- *              Michal Simek <michal.simek@xilinx.com>
+ *              Michal Simek <michal.simek@amd.com>
  *
  * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
  */
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 211b2c6e55..f3cdfb0275 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -30,6 +30,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <dm/device_compat.h>
+#include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/err.h>
 #include <linux/errno.h>
@@ -67,11 +68,6 @@
 #define ZYNQ_GEM_NWCFG_FSREM		0x00020000 /* FCS removal */
 #define ZYNQ_GEM_NWCFG_SGMII_ENBL	0x08000000 /* SGMII Enable */
 #define ZYNQ_GEM_NWCFG_PCS_SEL		0x00000800 /* PCS select */
-#ifdef CONFIG_ARM64
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV	0x00100000 /* Div pclk by 64, max 160MHz */
-#else
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV	0x000c0000 /* Div pclk by 48, max 120MHz */
-#endif
 
 #ifdef CONFIG_ARM64
 # define ZYNQ_GEM_DBUS_WIDTH	(1 << 21) /* 64 bit bus */
@@ -81,8 +77,7 @@
 
 #define ZYNQ_GEM_NWCFG_INIT		(ZYNQ_GEM_DBUS_WIDTH | \
 					ZYNQ_GEM_NWCFG_FDEN | \
-					ZYNQ_GEM_NWCFG_FSREM | \
-					ZYNQ_GEM_NWCFG_MDCCLKDIV)
+					ZYNQ_GEM_NWCFG_FSREM)
 
 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK	0x00000004 /* PHY management idle */
 
@@ -141,6 +136,18 @@
 
 #define RXCLK_EN		BIT(0)
 
+/* GEM specific constants for CLK. */
+#define GEM_CLK_DIV8		0
+#define GEM_CLK_DIV16		1
+#define GEM_CLK_DIV32		2
+#define GEM_CLK_DIV48		3
+#define GEM_CLK_DIV64		4
+#define GEM_CLK_DIV96		5
+#define GEM_CLK_DIV128		6
+#define GEM_CLK_DIV224		7
+
+#define GEM_MDC_SET(val)	FIELD_PREP(GENMASK(20, 18), val)
+
 /* Device registers */
 struct zynq_gem_regs {
 	u32 nwctrl; /* 0x0 - Network Control reg */
@@ -220,6 +227,7 @@ struct zynq_gem_priv {
 	struct mii_dev *bus;
 	struct clk rx_clk;
 	struct clk tx_clk;
+	struct clk pclk;
 	u32 max_speed;
 	bool int_pcs;
 	bool dma_64bit;
@@ -352,6 +360,32 @@ static int zynq_phy_init(struct udevice *dev)
 	return phy_config(priv->phydev);
 }
 
+static u32 gem_mdc_clk_div(struct zynq_gem_priv *priv)
+{
+	u32 config;
+	unsigned long pclk_hz;
+
+	pclk_hz = clk_get_rate(&priv->pclk);
+	if (pclk_hz <= 20000000)
+		config = GEM_MDC_SET(GEM_CLK_DIV8);
+	else if (pclk_hz <= 40000000)
+		config = GEM_MDC_SET(GEM_CLK_DIV16);
+	else if (pclk_hz <= 80000000)
+		config = GEM_MDC_SET(GEM_CLK_DIV32);
+	else if (pclk_hz <= 120000000)
+		config = GEM_MDC_SET(GEM_CLK_DIV48);
+	else if (pclk_hz <= 160000000)
+		config = GEM_MDC_SET(GEM_CLK_DIV64);
+	else if (pclk_hz <= 240000000)
+		config = GEM_MDC_SET(GEM_CLK_DIV96);
+	else if (pclk_hz <= 320000000)
+		config = GEM_MDC_SET(GEM_CLK_DIV128);
+	else
+		config = GEM_MDC_SET(GEM_CLK_DIV224);
+
+	return config;
+}
+
 static int zynq_gem_init(struct udevice *dev)
 {
 	u32 i, nwconfig;
@@ -460,7 +494,8 @@ static int zynq_gem_init(struct udevice *dev)
 		return -1;
 	}
 
-	nwconfig = ZYNQ_GEM_NWCFG_INIT;
+	nwconfig = gem_mdc_clk_div(priv);
+	nwconfig |= ZYNQ_GEM_NWCFG_INIT;
 
 	/*
 	 * Set SGMII enable PCS selection only if internal PCS/PMA
@@ -828,6 +863,12 @@ static int zynq_gem_probe(struct udevice *dev)
 		}
 	}
 
+	ret = clk_get_by_name(dev, "pclk", &priv->pclk);
+	if (ret < 0) {
+		dev_err(dev, "failed to get pclk clock\n");
+		goto err2;
+	}
+
 	if (IS_ENABLED(CONFIG_DM_ETH_PHY))
 		priv->bus = eth_phy_get_mdio_bus(dev);
 
diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile
index fa7b619446..fd3e68a91d 100644
--- a/drivers/nvme/Makefile
+++ b/drivers/nvme/Makefile
@@ -4,4 +4,4 @@
 
 obj-y += nvme-uclass.o nvme.o nvme_show.o
 obj-$(CONFIG_NVME_APPLE) += nvme_apple.o
-obj-$(CONFIG_NVME_PCI) += nvme_pci.o
+obj-$(CONFIG_$(SPL_)NVME_PCI) += nvme_pci.o
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 74e7a5b011..20dc910d8a 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -578,17 +578,22 @@ static int nvme_set_queue_count(struct nvme_dev *dev, int count)
 	return min(result & 0xffff, result >> 16) + 1;
 }
 
-static void nvme_create_io_queues(struct nvme_dev *dev)
+static int nvme_create_io_queues(struct nvme_dev *dev)
 {
 	unsigned int i;
+	int ret;
 
 	for (i = dev->queue_count; i <= dev->max_qid; i++)
 		if (!nvme_alloc_queue(dev, i, dev->q_depth))
-			break;
+			return log_msg_ret("all", -ENOMEM);
 
-	for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
-		if (nvme_create_queue(dev->queues[i], i))
-			break;
+	for (i = dev->online_queues; i <= dev->queue_count - 1; i++) {
+		ret = nvme_create_queue(dev->queues[i], i);
+		if (ret)
+			return log_msg_ret("cre", ret);
+	}
+
+	return 0;
 }
 
 static int nvme_setup_io_queues(struct nvme_dev *dev)
@@ -598,14 +603,18 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
 
 	nr_io_queues = 1;
 	result = nvme_set_queue_count(dev, nr_io_queues);
-	if (result <= 0)
+	if (result <= 0) {
+		log_debug("Cannot set queue count (err=%dE)\n", result);
 		return result;
+	}
 
 	dev->max_qid = nr_io_queues;
 
 	/* Free previously allocated queues */
 	nvme_free_queues(dev, nr_io_queues + 1);
-	nvme_create_io_queues(dev);
+	result = nvme_create_io_queues(dev);
+	if (result)
+		return result;
 
 	return 0;
 }
@@ -683,8 +692,11 @@ int nvme_scan_namespace(void)
 
 	uclass_foreach_dev(dev, uc) {
 		ret = device_probe(dev);
-		if (ret)
+		if (ret) {
+			log_err("Failed to probe '%s': err=%dE\n", dev->name,
+				ret);
 			return ret;
+		}
 	}
 
 	return 0;
@@ -842,8 +854,10 @@ int nvme_init(struct udevice *udev)
 	ndev->dbs = ((void __iomem *)ndev->bar) + 4096;
 
 	ret = nvme_configure_admin_queue(ndev);
-	if (ret)
+	if (ret) {
+		log_debug("Unable to configure admin queue (err=%dE)\n", ret);
 		goto free_queue;
+	}
 
 	/* Allocate after the page size is known */
 	ndev->prp_pool = memalign(ndev->page_size, MAX_PRP_POOL);
@@ -855,8 +869,10 @@ int nvme_init(struct udevice *udev)
 	ndev->prp_entry_num = MAX_PRP_POOL >> 3;
 
 	ret = nvme_setup_io_queues(ndev);
-	if (ret)
+	if (ret) {
+		log_debug("Unable to setup I/O queues(err=%dE)\n", ret);
 		goto free_queue;
+	}
 
 	nvme_get_info_from_identify(ndev);
 
@@ -894,7 +910,7 @@ int nvme_init(struct udevice *udev)
 		if (ret)
 			goto free_id;
 
-		ret = bootdev_setup_sibling_blk(ns_udev, "nvme_bootdev");
+		ret = bootdev_setup_for_sibling_blk(ns_udev, "nvme_bootdev");
 		if (ret)
 			return log_msg_ret("bootdev", ret);
 
diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c
index 3bd011518b..3137eb2c28 100644
--- a/drivers/pch/pch9.c
+++ b/drivers/pch/pch9.c
@@ -3,6 +3,8 @@
  * Copyright (C) 2014 Google, Inc
  */
 
+#define LOG_CATEGORY	UCLASS_PCH
+
 #include <common.h>
 #include <dm.h>
 #include <log.h>
@@ -38,7 +40,7 @@ static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
 	 */
 	dm_pci_read_config32(dev, GPIO_BASE, &base);
 	if (base == 0x00000000 || base == 0xffffffff) {
-		debug("%s: unexpected BASE value\n", __func__);
+		log_debug("unexpected BASE value\n");
 		return -ENODEV;
 	}
 
@@ -59,7 +61,7 @@ static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
 
 	dm_pci_read_config32(dev, IO_BASE, &base);
 	if (base == 0x00000000 || base == 0xffffffff) {
-		debug("%s: unexpected BASE value\n", __func__);
+		log_debug("unexpected BASE value\n");
 		return -ENODEV;
 	}
 
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d2652..a0bf44d38a 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -40,6 +40,18 @@ config PCI_PNP
 	help
 	  Enable PCI memory and I/O space resource allocation and assignment.
 
+config SPL_PCI_PNP
+	bool "Enable Plug & Play support for PCI in SPL"
+	depends on SPL_PCI
+	help
+	  Enable PCI memory and I/O space resource allocation and assignment.
+
+	  This is required to auto configure the enumerated devices.
+
+	  This is normally not done in SPL, but can be enabled if devices must
+	  be set up in the SPL phase. Often it is enough to manually configure
+	  one device, so this option can be disabled.
+
 config PCI_REGION_MULTI_ENTRY
 	bool "Enable Multiple entries of region type MEMORY in ranges for PCI"
 	help
@@ -374,4 +386,24 @@ config PCIE_UNIPHIER
 	  Say Y here if you want to enable PCIe controller support on
 	  UniPhier SoCs.
 
+config PCIE_XILINX_NWL
+	bool "Xilinx NWL PCIe controller"
+	depends on ARCH_ZYNQMP
+	help
+	 Say 'Y' here if you want support for Xilinx / AMD NWL PCIe
+	 controller as Root Port.
+
+config PCIE_PLDA_COMMON
+	bool
+
+config PCIE_STARFIVE_JH7110
+	bool "Enable Starfive JH7110 PCIe driver"
+	select PCIE_PLDA_COMMON
+	imply STARFIVE_JH7110
+	imply CLK_JH7110
+	imply RESET_JH7110
+	help
+	  Say Y here if you want to enable PLDA XpressRich PCIe controller
+	  support on StarFive JH7110 SoC.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 49506e7ba5..a712a317a3 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,6 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
 obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
+obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 8d27e40338..632c1a63cf 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -13,6 +13,7 @@
 #include <log.h>
 #include <malloc.h>
 #include <pci.h>
+#include <spl.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <dm/device-internal.h>
@@ -722,6 +723,9 @@ static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor,
 	u32 vendev;
 	int index;
 
+	if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(PCI_PNP))
+		return true;
+
 	for (index = 0;
 	     !dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index,
 				 &vendev);
@@ -793,7 +797,9 @@ static int pci_find_and_bind_driver(struct udevice *parent,
 			 * space is pretty limited (ie: using Cache As RAM).
 			 */
 			if (!(gd->flags & GD_FLG_RELOC) &&
-			    !(drv->flags & DM_FLAG_PRE_RELOC))
+			    !(drv->flags & DM_FLAG_PRE_RELOC) &&
+			    (!CONFIG_IS_ENABLED(PCI_PNP) ||
+			     spl_phase() != PHASE_SPL))
 				return log_msg_ret("pre", -EPERM);
 
 			/*
@@ -918,6 +924,8 @@ int pci_bind_bus_devices(struct udevice *bus)
 			}
 			ret = pci_find_and_bind_driver(bus, &find_id, bdf,
 						       &dev);
+		} else {
+			debug("device: %s\n", dev->name);
 		}
 		if (ret == -EPERM)
 			continue;
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index f0dfe63149..438583aa01 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -26,6 +26,7 @@
 
 #include <common.h>
 #include <bios_emul.h>
+#include <bloblist.h>
 #include <bootstage.h>
 #include <dm.h>
 #include <errno.h>
@@ -34,6 +35,7 @@
 #include <malloc.h>
 #include <pci.h>
 #include <pci_rom.h>
+#include <spl.h>
 #include <vesa.h>
 #include <video.h>
 #include <acpi/acpi_s3.h>
@@ -91,6 +93,7 @@ static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
 		debug("%s: rom_address=%x\n", __func__, rom_address);
 		return -ENOENT;
 	}
+	rom_address &= PCI_ROM_ADDRESS_MASK;
 
 	/* Enable expansion ROM address decoding. */
 	dm_pci_write_config32(dev, PCI_ROM_ADDRESS,
@@ -254,14 +257,16 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
 
 	ret = pci_rom_probe(dev, &rom);
 	if (ret)
-		return ret;
+		return log_msg_ret("pro", ret);
 
 	ret = pci_rom_load(rom, &ram, &alloced);
-	if (ret)
+	if (ret) {
+		ret = log_msg_ret("ld", ret);
 		goto err;
+	}
 
 	if (!board_should_run_oprom(dev)) {
-		ret = -ENXIO;
+		ret = log_msg_ret("run", -ENXIO);
 		goto err;
 	}
 
@@ -269,7 +274,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
 		defined(CONFIG_FRAMEBUFFER_VESA_MODE)
 	vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
 #endif
-	debug("Selected vesa mode %#x\n", vesa_mode);
+	debug("Selected vesa mode 0x%x\n", vesa_mode);
 
 	if (exec_method & PCI_ROM_USE_NATIVE) {
 #ifdef CONFIG_X86
@@ -296,27 +301,31 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
 	}
 
 	if (emulate) {
-#ifdef CONFIG_BIOSEMU
-		BE_VGAInfo *info;
-
-		ret = biosemu_setup(dev, &info);
-		if (ret)
-			goto err;
-		biosemu_set_interrupt_handler(0x15, int15_handler);
-		ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
-				  true, vesa_mode, &mode_info);
-		if (ret)
-			goto err;
-#endif
+		if (CONFIG_IS_ENABLED(BIOSEMU)) {
+			BE_VGAInfo *info;
+
+			log_debug("Running video BIOS with emulator...");
+			ret = biosemu_setup(dev, &info);
+			if (ret)
+				goto err;
+			biosemu_set_interrupt_handler(0x15, int15_handler);
+			ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
+					  true, vesa_mode, &mode_info);
+			log_debug("done\n");
+			if (ret)
+				goto err;
+		}
 	} else {
 #if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL)
+		log_debug("Running video BIOS...");
 		bios_set_interrupt_handler(0x15, int15_handler);
 
 		bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
 				&mode_info);
+		log_debug("done\n");
 #endif
 	}
-	debug("Final vesa mode %#x\n", mode_info.video_mode);
+	debug("Final vesa mode %x\n", mode_info.video_mode);
 	ret = 0;
 
 err:
@@ -368,34 +377,68 @@ int vesa_setup_video(struct udevice *dev, int (*int15_handler)(void))
 		printf("Not available (previous bootloader prevents it)\n");
 		return -EPERM;
 	}
-	bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
-	ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
-					PCI_ROM_ALLOW_FALLBACK);
-	bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
-	if (ret) {
-		debug("failed to run video BIOS: %d\n", ret);
-		return ret;
-	}
 
-	ret = vesa_setup_video_priv(&mode_info.vesa,
-				    mode_info.vesa.phys_base_ptr, uc_priv,
-				    plat);
-	if (ret) {
-		if (ret == -ENFILE) {
-			/*
-			 * See video-uclass.c for how to set up reserved memory
-			 * in your video driver
-			 */
-			log_err("CONFIG_VIDEO_COPY enabled but driver '%s' set up no reserved memory\n",
-				dev->driver->name);
+	/* In U-Boot proper, collect the information added by SPL (see below) */
+	if (IS_ENABLED(CONFIG_SPL_VIDEO) && spl_phase() > PHASE_SPL &&
+	    CONFIG_IS_ENABLED(BLOBLIST)) {
+		struct video_handoff *ho;
+
+		ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho));
+		if (!ho)
+			return log_msg_ret("blf", -ENOENT);
+		plat->base = ho->fb;
+		plat->size = ho->size;
+		uc_priv->xsize = ho->xsize;
+		uc_priv->ysize = ho->ysize;
+		uc_priv->line_length = ho->line_length;
+		uc_priv->bpix = ho->bpix;
+	} else {
+		bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
+		ret = dm_pci_run_vga_bios(dev, int15_handler,
+					  PCI_ROM_USE_NATIVE |
+					  PCI_ROM_ALLOW_FALLBACK);
+		bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
+		if (ret) {
+			debug("failed to run video BIOS: %d\n", ret);
+			return ret;
 		}
 
-		debug("No video mode configured\n");
-		return ret;
+		ret = vesa_setup_video_priv(&mode_info.vesa,
+					    mode_info.vesa.phys_base_ptr,
+					    uc_priv, plat);
+		if (ret) {
+			if (ret == -ENFILE) {
+				/*
+				 * See video-uclass.c for how to set up reserved
+				 * memory in your video driver
+				 */
+				log_err("CONFIG_VIDEO_COPY enabled but driver '%s' set up no reserved memory\n",
+					dev->driver->name);
+			}
+
+			debug("No video mode configured\n");
+			return ret;
+		}
 	}
 
 	printf("Video: %dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
 	       mode_info.vesa.bits_per_pixel);
 
+	/* In SPL, store the information for use by U-Boot proper */
+	if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) {
+		struct video_handoff *ho;
+
+		ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0);
+		if (!ho)
+			return log_msg_ret("blc", -ENOMEM);
+
+		ho->fb = plat->base;
+		ho->size = plat->size;
+		ho->xsize = uc_priv->xsize;
+		ho->ysize = uc_priv->ysize;
+		ho->line_length = uc_priv->line_length;
+		ho->bpix = uc_priv->bpix;
+	}
+
 	return 0;
 }
diff --git a/drivers/pci/pcie-xilinx-nwl.c b/drivers/pci/pcie-xilinx-nwl.c
new file mode 100644
index 0000000000..7ef2bdf57b
--- /dev/null
+++ b/drivers/pci/pcie-xilinx-nwl.c
@@ -0,0 +1,352 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host bridge driver for Xilinx / AMD ZynqMP NWL PCIe Bridge
+ *
+ * Based on the Linux driver which is:
+ * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * Author: Stefan Roese <sr@denx.de>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <mapmem.h>
+#include <pci.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+
+/* Bridge core config registers */
+#define BRCFG_PCIE_RX0			0x00000000
+#define BRCFG_PCIE_RX1			0x00000004
+#define BRCFG_INTERRUPT			0x00000010
+#define BRCFG_PCIE_RX_MSG_FILTER	0x00000020
+
+/* Egress - Bridge translation registers */
+#define E_BREG_CAPABILITIES		0x00000200
+#define E_BREG_CONTROL			0x00000208
+#define E_BREG_BASE_LO			0x00000210
+#define E_BREG_BASE_HI			0x00000214
+#define E_ECAM_CAPABILITIES		0x00000220
+#define E_ECAM_CONTROL			0x00000228
+#define E_ECAM_BASE_LO			0x00000230
+#define E_ECAM_BASE_HI			0x00000234
+
+#define I_ISUB_CONTROL			0x000003E8
+#define SET_ISUB_CONTROL		BIT(0)
+/* Rxed msg fifo  - Interrupt status registers */
+#define MSGF_MISC_STATUS		0x00000400
+#define MSGF_MISC_MASK			0x00000404
+#define MSGF_LEG_STATUS			0x00000420
+#define MSGF_LEG_MASK			0x00000424
+#define MSGF_MSI_STATUS_LO		0x00000440
+#define MSGF_MSI_STATUS_HI		0x00000444
+#define MSGF_MSI_MASK_LO		0x00000448
+#define MSGF_MSI_MASK_HI		0x0000044C
+
+/* Msg filter mask bits */
+#define CFG_ENABLE_PM_MSG_FWD		BIT(1)
+#define CFG_ENABLE_INT_MSG_FWD		BIT(2)
+#define CFG_ENABLE_ERR_MSG_FWD		BIT(3)
+#define CFG_ENABLE_MSG_FILTER_MASK	(CFG_ENABLE_PM_MSG_FWD |	\
+					 CFG_ENABLE_INT_MSG_FWD |	\
+					 CFG_ENABLE_ERR_MSG_FWD)
+
+/* Misc interrupt status mask bits */
+#define MSGF_MISC_SR_RXMSG_AVAIL	BIT(0)
+#define MSGF_MISC_SR_RXMSG_OVER		BIT(1)
+#define MSGF_MISC_SR_SLAVE_ERR		BIT(4)
+#define MSGF_MISC_SR_MASTER_ERR		BIT(5)
+#define MSGF_MISC_SR_I_ADDR_ERR		BIT(6)
+#define MSGF_MISC_SR_E_ADDR_ERR		BIT(7)
+#define MSGF_MISC_SR_FATAL_AER		BIT(16)
+#define MSGF_MISC_SR_NON_FATAL_AER	BIT(17)
+#define MSGF_MISC_SR_CORR_AER		BIT(18)
+#define MSGF_MISC_SR_UR_DETECT		BIT(20)
+#define MSGF_MISC_SR_NON_FATAL_DEV	BIT(22)
+#define MSGF_MISC_SR_FATAL_DEV		BIT(23)
+#define MSGF_MISC_SR_LINK_DOWN		BIT(24)
+#define MSGF_MSIC_SR_LINK_AUTO_BWIDTH	BIT(25)
+#define MSGF_MSIC_SR_LINK_BWIDTH	BIT(26)
+
+#define MSGF_MISC_SR_MASKALL		(MSGF_MISC_SR_RXMSG_AVAIL |	\
+					 MSGF_MISC_SR_RXMSG_OVER |	\
+					 MSGF_MISC_SR_SLAVE_ERR |	\
+					 MSGF_MISC_SR_MASTER_ERR |	\
+					 MSGF_MISC_SR_I_ADDR_ERR |	\
+					 MSGF_MISC_SR_E_ADDR_ERR |	\
+					 MSGF_MISC_SR_FATAL_AER |	\
+					 MSGF_MISC_SR_NON_FATAL_AER |	\
+					 MSGF_MISC_SR_CORR_AER |	\
+					 MSGF_MISC_SR_UR_DETECT |	\
+					 MSGF_MISC_SR_NON_FATAL_DEV |	\
+					 MSGF_MISC_SR_FATAL_DEV |	\
+					 MSGF_MISC_SR_LINK_DOWN |	\
+					 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
+					 MSGF_MSIC_SR_LINK_BWIDTH)
+
+/* Legacy interrupt status mask bits */
+#define MSGF_LEG_SR_INTA		BIT(0)
+#define MSGF_LEG_SR_INTB		BIT(1)
+#define MSGF_LEG_SR_INTC		BIT(2)
+#define MSGF_LEG_SR_INTD		BIT(3)
+#define MSGF_LEG_SR_MASKALL		(MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
+					 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
+
+/* MSI interrupt status mask bits */
+#define MSGF_MSI_SR_LO_MASK		GENMASK(31, 0)
+#define MSGF_MSI_SR_HI_MASK		GENMASK(31, 0)
+
+/* Bridge config interrupt mask */
+#define BRCFG_INTERRUPT_MASK		BIT(0)
+#define BREG_PRESENT			BIT(0)
+#define BREG_ENABLE			BIT(0)
+#define BREG_ENABLE_FORCE		BIT(1)
+
+/* E_ECAM status mask bits */
+#define E_ECAM_PRESENT			BIT(0)
+#define E_ECAM_CR_ENABLE		BIT(0)
+#define E_ECAM_SIZE_LOC			GENMASK(20, 16)
+#define E_ECAM_SIZE_SHIFT		16
+#define NWL_ECAM_VALUE_DEFAULT		12
+
+#define CFG_DMA_REG_BAR			GENMASK(2, 0)
+#define CFG_PCIE_CACHE			GENMASK(7, 0)
+
+/* Readin the PS_LINKUP */
+#define PS_LINKUP_OFFSET		0x00000238
+#define PCIE_PHY_LINKUP_BIT		BIT(0)
+#define PHY_RDY_LINKUP_BIT		BIT(1)
+
+/* Parameters for the waiting for link up routine */
+#define LINK_WAIT_MAX_RETRIES          10
+#define LINK_WAIT_USLEEP_MIN           90000
+#define LINK_WAIT_USLEEP_MAX           100000
+
+struct nwl_pcie {
+	struct udevice *dev;
+	void __iomem *breg_base;
+	void __iomem *pcireg_base;
+	void __iomem *ecam_base;
+	phys_addr_t phys_breg_base;	/* Physical Bridge Register Base */
+	phys_addr_t phys_ecam_base;	/* Physical Configuration Base */
+	u32 ecam_value;
+};
+
+static int nwl_pcie_config_address(const struct udevice *bus,
+				   pci_dev_t bdf, uint offset,
+				   void **paddress)
+{
+	struct nwl_pcie *pcie = dev_get_priv(bus);
+	void *addr;
+
+	addr = pcie->ecam_base;
+	addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(bus),
+				 PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+	*paddress = addr;
+
+	return 0;
+}
+
+static int nwl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
+				uint offset, ulong *valuep,
+				enum pci_size_t size)
+{
+	return pci_generic_mmap_read_config(bus, nwl_pcie_config_address,
+					    bdf, offset, valuep, size);
+}
+
+static int nwl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
+				 uint offset, ulong value,
+				 enum pci_size_t size)
+{
+	return pci_generic_mmap_write_config(bus, nwl_pcie_config_address,
+					     bdf, offset, value, size);
+}
+
+static const struct dm_pci_ops nwl_pcie_ops = {
+	.read_config = nwl_pcie_read_config,
+	.write_config = nwl_pcie_write_config,
+};
+
+static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
+{
+	return readl(pcie->breg_base + off);
+}
+
+static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
+{
+	writel(val, pcie->breg_base + off);
+}
+
+static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
+{
+	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
+		return true;
+	return false;
+}
+
+static bool nwl_phy_link_up(struct nwl_pcie *pcie)
+{
+	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
+		return true;
+	return false;
+}
+
+static int nwl_wait_for_link(struct nwl_pcie *pcie)
+{
+	struct udevice *dev = pcie->dev;
+	int retries;
+
+	/* check if the link is up or not */
+	for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+		if (nwl_phy_link_up(pcie))
+			return 0;
+		udelay(LINK_WAIT_USLEEP_MIN);
+	}
+
+	dev_warn(dev, "PHY link never came up\n");
+	return -ETIMEDOUT;
+}
+
+static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
+{
+	struct udevice *dev = pcie->dev;
+	u32 breg_val, ecam_val;
+	int err;
+
+	breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
+	if (!breg_val) {
+		dev_err(dev, "BREG is not present\n");
+		return breg_val;
+	}
+
+	/* Write bridge_off to breg base */
+	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
+			  E_BREG_BASE_LO);
+	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
+			  E_BREG_BASE_HI);
+
+	/* Enable BREG */
+	nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
+			  E_BREG_CONTROL);
+
+	/* Disable DMA channel registers */
+	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
+			  CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
+
+	/* Enable Ingress subtractive decode translation */
+	nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
+
+	/* Enable msg filtering details */
+	nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
+			  BRCFG_PCIE_RX_MSG_FILTER);
+
+	err = nwl_wait_for_link(pcie);
+	if (err)
+		return err;
+
+	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
+	if (!ecam_val) {
+		dev_err(dev, "ECAM is not present\n");
+		return ecam_val;
+	}
+
+	/* Enable ECAM */
+	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
+			  E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
+
+	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
+			  (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
+			  E_ECAM_CONTROL);
+
+	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
+			  E_ECAM_BASE_LO);
+	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
+			  E_ECAM_BASE_HI);
+
+	if (nwl_pcie_link_up(pcie))
+		dev_info(dev, "Link is UP\n");
+	else
+		dev_info(dev, "Link is DOWN\n");
+
+	/* Disable all misc interrupts */
+	nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
+
+	/* Clear pending misc interrupts */
+	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
+			  MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
+
+	/* Disable all legacy interrupts */
+	nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
+
+	/* Clear pending legacy interrupts */
+	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
+			  MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
+
+	return 0;
+}
+
+static int nwl_pcie_parse_dt(struct nwl_pcie *pcie)
+{
+	struct udevice *dev = pcie->dev;
+	struct resource res;
+	int ret;
+
+	ret = dev_read_resource_byname(dev, "breg", &res);
+	if (ret)
+		return ret;
+	pcie->breg_base = devm_ioremap(dev, res.start, resource_size(&res));
+	if (IS_ERR(pcie->breg_base))
+		return PTR_ERR(pcie->breg_base);
+	pcie->phys_breg_base = res.start;
+
+	ret = dev_read_resource_byname(dev, "cfg", &res);
+	if (ret)
+		return ret;
+	pcie->ecam_base = devm_ioremap(dev, res.start, resource_size(&res));
+	if (IS_ERR(pcie->ecam_base))
+		return PTR_ERR(pcie->ecam_base);
+	pcie->phys_ecam_base = res.start;
+
+	return 0;
+}
+
+static int nwl_pcie_probe(struct udevice *dev)
+{
+	struct nwl_pcie *pcie = dev_get_priv(dev);
+	int err;
+
+	pcie->dev = dev;
+	pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
+
+	err = nwl_pcie_parse_dt(pcie);
+	if (err) {
+		dev_err(dev, "Parsing DT failed\n");
+		return err;
+	}
+
+	err = nwl_pcie_bridge_init(pcie);
+	if (err) {
+		dev_err(dev, "HW Initialization failed\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id nwl_pcie_of_match[] = {
+	{ .compatible = "xlnx,nwl-pcie-2.11", },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(nwl_pcie) = {
+	.name = "nwl-pcie",
+	.id = UCLASS_PCI,
+	.of_match = nwl_pcie_of_match,
+	.probe = nwl_pcie_probe,
+	.priv_auto = sizeof(struct nwl_pcie),
+	.ops = &nwl_pcie_ops,
+};
diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c
index 9f8b016d11..74fb6df412 100644
--- a/drivers/pci/pcie_dw_common.c
+++ b/drivers/pci/pcie_dw_common.c
@@ -141,9 +141,9 @@ static uintptr_t set_cfg_address(struct pcie_dw *pcie,
 
 	/*
 	 * Not accessing root port configuration space?
-	 * Region #0 is used for Outbound CFG space access.
+	 * Region #1 is used for Outbound CFG space access.
 	 * Direction = Outbound
-	 * Region Index = 0
+	 * Region Index = 1
 	 */
 	d = PCI_MASK_BUS(d);
 	d = PCI_ADD_BUS(bus, d);
@@ -328,8 +328,10 @@ void pcie_dw_setup_host(struct pcie_dw *pci)
 			pci->prefetch.bus_start = hose->regions[ret].bus_start;  /* PREFETCH_bus_addr */
 			pci->prefetch.size = hose->regions[ret].size;	    /* PREFETCH size */
 		} else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) {
-			pci->cfg_base = (void *)(pci->io.phys_start - pci->io.size);
-			pci->cfg_size = pci->io.size;
+			if (!pci->cfg_base) {
+				pci->cfg_base = (void *)(pci->io.phys_start - pci->io.size);
+				pci->cfg_size = pci->io.size;
+			}
 		} else {
 			dev_err(pci->dev, "invalid flags type!\n");
 		}
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 6da618055c..1a35fae5c3 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -61,8 +61,7 @@ struct rk_pcie {
 #define PCIE_CLIENT_DBG_TRANSITION_DATA	0xffff0000
 #define PCIE_CLIENT_DBF_EN		0xffff0003
 
-/* Parameters for the waiting for #perst signal */
-#define MACRO_US			1000
+#define PCIE_TYPE0_HDR_DBI2_OFFSET	0x100000
 
 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
 {
@@ -161,6 +160,12 @@ static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
 {
 	dw_pcie_dbi_write_enable(&pci->dw, true);
 
+	/* Disable BAR 0 and BAR 1 */
+	writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET +
+	       PCI_BASE_ADDRESS_0);
+	writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET +
+	       PCI_BASE_ADDRESS_1);
+
 	clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
 			TARGET_LINK_SPEED_MASK, cap_speed);
 
@@ -242,43 +247,46 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
 	/* DW pre link configurations */
 	rk_pcie_configure(priv, cap_speed);
 
-	/* Rest the device */
-	if (dm_gpio_is_valid(&priv->rst_gpio)) {
-		dm_gpio_set_value(&priv->rst_gpio, 0);
-		/*
-		 * Minimal is 100ms from spec but we see
-		 * some wired devices need much more, such as 600ms.
-		 * Add a enough delay to cover all cases.
-		 */
-		udelay(MACRO_US * 1000);
-		dm_gpio_set_value(&priv->rst_gpio, 1);
-	}
-
 	rk_pcie_disable_ltssm(priv);
 	rk_pcie_link_status_clear(priv);
 	rk_pcie_enable_debug(priv);
 
+	/* Reset the device */
+	if (dm_gpio_is_valid(&priv->rst_gpio))
+		dm_gpio_set_value(&priv->rst_gpio, 0);
+
 	/* Enable LTSSM */
 	rk_pcie_enable_ltssm(priv);
 
-	for (retries = 0; retries < 5; retries++) {
-		if (is_link_up(priv)) {
-			dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
-				 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
-			rk_pcie_debug_dump(priv);
-			return 0;
-		}
-
-		dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
-			 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
-		rk_pcie_debug_dump(priv);
-		udelay(MACRO_US * 1000);
+	/*
+	 * PCIe requires the refclk to be stable for 100ms prior to releasing
+	 * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
+	 * Express Card Electromechanical Specification, 1.1. However, we don't
+	 * know if the refclk is coming from RC's PHY or external OSC. If it's
+	 * from RC, so enabling LTSSM is the just right place to release #PERST.
+	 */
+	mdelay(100);
+	if (dm_gpio_is_valid(&priv->rst_gpio))
+		dm_gpio_set_value(&priv->rst_gpio, 1);
+
+	/* Check if the link is up or not */
+	for (retries = 0; retries < 10; retries++) {
+		if (is_link_up(priv))
+			break;
+
+		mdelay(100);
+	}
+
+	if (retries >= 10) {
+		dev_err(priv->dw.dev, "PCIe-%d Link Fail\n",
+			dev_seq(priv->dw.dev));
+		return -EIO;
 	}
 
-	dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
-	/* Link maybe in Gen switch recovery but we need to wait more 1s */
-	udelay(MACRO_US * 1000);
-	return -EIO;
+	dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
+		 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
+	rk_pcie_debug_dump(priv);
+	return 0;
 }
 
 static int rockchip_pcie_init_port(struct udevice *dev)
@@ -287,22 +295,23 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 	u32 val;
 	struct rk_pcie *priv = dev_get_priv(dev);
 
-	/* Set power and maybe external ref clk input */
-	if (priv->vpcie3v3) {
-		ret = regulator_set_value(priv->vpcie3v3, 3300000);
-		if (ret) {
-			dev_err(priv->dw.dev, "failed to enable vpcie3v3 (ret=%d)\n",
-				ret);
-			return ret;
-		}
+	ret = reset_assert_bulk(&priv->rsts);
+	if (ret) {
+		dev_err(dev, "failed to assert resets (ret=%d)\n", ret);
+		return ret;
 	}
 
-	udelay(MACRO_US * 1000);
+	/* Set power and maybe external ref clk input */
+	ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
+	if (ret && ret != -ENOSYS) {
+		dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret);
+		return ret;
+	}
 
 	ret = generic_phy_init(&priv->phy);
 	if (ret) {
 		dev_err(dev, "failed to init phy (ret=%d)\n", ret);
-		return ret;
+		goto err_disable_regulator;
 	}
 
 	ret = generic_phy_power_on(&priv->phy);
@@ -345,6 +354,8 @@ err_power_off_phy:
 	generic_phy_power_off(&priv->phy);
 err_exit_phy:
 	generic_phy_exit(&priv->phy);
+err_disable_regulator:
+	regulator_set_enable_if_allowed(priv->vpcie3v3, false);
 
 	return ret;
 }
@@ -366,6 +377,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
 
 	dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
 
+	priv->dw.cfg_base = dev_read_addr_size_index_ptr(dev, 2,
+							 &priv->dw.cfg_size);
+	if (!priv->dw.cfg_base)
+		return -EINVAL;
+
+	dev_dbg(dev, "CFG address is 0x%p\n", priv->dw.cfg_base);
+
 	ret = gpio_request_by_name(dev, "reset-gpios", 0,
 				   &priv->rst_gpio, GPIOD_IS_OUT);
 	if (ret) {
diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c
new file mode 100644
index 0000000000..cd74bb4711
--- /dev/null
+++ b/drivers/pci/pcie_plda_common.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PLDA XpressRich PCIe host controller common functions.
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include "pcie_plda_common.h"
+
+static bool plda_pcie_addr_valid(struct pcie_plda *plda, pci_dev_t bdf)
+{
+	/*
+	 * Single device limitation.
+	 * PCIe controller contain HW issue that secondary bus of
+	 * host bridge emumerate duplicate devices.
+	 * Only can access device 0 in secondary bus.
+	 */
+	if (PCI_BUS(bdf) == plda->sec_busno && PCI_DEV(bdf) > 0)
+		return false;
+
+	return true;
+}
+
+static int plda_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf,
+				  uint offset, void **paddr)
+{
+	struct pcie_plda *priv = dev_get_priv(udev);
+	int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(udev),
+				     PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+
+	if (!plda_pcie_addr_valid(priv, bdf))
+		return -ENODEV;
+
+	*paddr = (void *)(priv->cfg_base + where);
+	return 0;
+}
+
+int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
+			  uint offset, ulong *valuep,
+			  enum pci_size_t size)
+{
+	return pci_generic_mmap_read_config(udev, plda_pcie_conf_address,
+					    bdf, offset, valuep, size);
+}
+
+int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
+			   uint offset, ulong value,
+			   enum pci_size_t size)
+{
+	struct pcie_plda *priv = dev_get_priv(udev);
+	int ret;
+
+	ret = pci_generic_mmap_write_config(udev, plda_pcie_conf_address,
+					    bdf, offset, value, size);
+
+	/* record secondary bus number */
+	if (!ret && PCI_BUS(bdf) == dev_seq(udev) &&
+	    PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+	    (offset == PCI_SECONDARY_BUS ||
+	    (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
+		priv->sec_busno =
+			((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 0xff;
+		priv->sec_busno += dev_seq(udev);
+		debug("Secondary bus number was changed to %d\n",
+		      priv->sec_busno);
+	}
+	return ret;
+}
+
+int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
+			    phys_addr_t trsl_addr, phys_size_t window_size,
+			    int trsl_param)
+{
+	void __iomem *base =
+		plda->reg_base + XR3PCI_ATR_AXI4_SLV0;
+
+	/* Support AXI4 Slave 0 Address Translation Tables 0-7. */
+	if (plda->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM) {
+		dev_err(plda->dev, "ATR table number %d exceeds max num\n",
+			plda->atr_table_num);
+		return -EINVAL;
+	}
+	base +=  XR3PCI_ATR_TABLE_OFFSET * plda->atr_table_num;
+	plda->atr_table_num++;
+
+	/*
+	 * X3PCI_ATR_SRC_ADDR_LOW:
+	 *   - bit 0: enable entry,
+	 *   - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
+	 *   - bits 7-11: reserved
+	 *   - bits 12-31: start of source address
+	 */
+	writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) |
+			(fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1,
+			base + XR3PCI_ATR_SRC_ADDR_LOW);
+	writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH);
+	writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK),
+	       base + XR3PCI_ATR_TRSL_ADDR_LOW);
+	writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
+	writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
+
+	dev_dbg(plda->dev, "ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n",
+		src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->",
+		trsl_addr, (u64)window_size, trsl_param);
+	return 0;
+}
diff --git a/drivers/pci/pcie_plda_common.h b/drivers/pci/pcie_plda_common.h
new file mode 100644
index 0000000000..409949f534
--- /dev/null
+++ b/drivers/pci/pcie_plda_common.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ *
+ */
+
+#ifndef PCIE_PLDA_COMMON_H
+#define PCIE_PLDA_COMMON_H
+
+#define GEN_SETTINGS			0x80
+#define PCIE_PCI_IDS			0x9C
+#define PCIE_WINROM			0xFC
+#define PMSG_SUPPORT_RX			0x3F0
+#define PCI_MISC			0xB4
+
+#define PLDA_EP_ENABLE			0
+#define PLDA_RP_ENABLE			1
+
+#define IDS_CLASS_CODE_SHIFT		8
+
+#define PREF_MEM_WIN_64_SUPPORT		BIT(3)
+#define PMSG_LTR_SUPPORT		BIT(2)
+#define PLDA_FUNCTION_DIS		BIT(15)
+#define PLDA_FUNC_NUM			4
+#define PLDA_PHY_FUNC_SHIFT		9
+
+#define XR3PCI_ATR_AXI4_SLV0		0x800
+#define XR3PCI_ATR_SRC_ADDR_LOW		0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH	0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW	0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH	0xc
+#define XR3PCI_ATR_TRSL_PARAM		0x10
+#define XR3PCI_ATR_TABLE_OFFSET		0x20
+#define XR3PCI_ATR_MAX_TABLE_NUM	8
+
+#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT	1
+#define XR3PCI_ATR_SRC_ADDR_MASK	GENMASK(31, 12)
+#define XR3PCI_ATR_TRSL_ADDR_MASK	GENMASK(31, 12)
+#define XR3PCI_ATR_TRSL_DIR		BIT(22)
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY	0x0
+#define XR3PCI_ATR_TRSLID_PCIE_CONFIG	0x1
+
+/**
+ * struct pcie_plda - PLDA PCIe controller state
+ *
+ * @reg_base: The base address of controller register space
+ * @cfg_base: The base address of configuration space
+ * @cfg_size: The size of configuration space
+ * @sec_busno: Secondary bus number.
+ * @atr_table_num: Total ATR table numbers.
+ */
+struct pcie_plda {
+	struct udevice	*dev;
+	void __iomem *reg_base;
+	void __iomem *cfg_base;
+	phys_size_t cfg_size;
+	int sec_busno;
+	int atr_table_num;
+};
+
+int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
+			  uint offset, ulong *valuep,
+			  enum pci_size_t size);
+int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
+			   uint offset, ulong value,
+			   enum pci_size_t size);
+int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
+			    phys_addr_t trsl_addr, phys_size_t window_size,
+			    int trsl_param);
+
+static inline void plda_pcie_enable_root_port(struct pcie_plda *plda)
+{
+	u32 value;
+
+	value = readl(plda->reg_base + GEN_SETTINGS);
+	value |= PLDA_RP_ENABLE;
+	writel(value, plda->reg_base + GEN_SETTINGS);
+}
+
+static inline void plda_pcie_set_standard_class(struct pcie_plda *plda)
+{
+	u32 value;
+
+	value = readl(plda->reg_base + PCIE_PCI_IDS);
+	value &= 0xff;
+	value |= (PCI_CLASS_BRIDGE_PCI_NORMAL << IDS_CLASS_CODE_SHIFT);
+	writel(value, plda->reg_base + PCIE_PCI_IDS);
+}
+
+static inline void plda_pcie_set_pref_win_64bit(struct pcie_plda *plda)
+{
+	u32 value;
+
+	value = readl(plda->reg_base + PCIE_WINROM);
+	value |= PREF_MEM_WIN_64_SUPPORT;
+	writel(value, plda->reg_base + PCIE_WINROM);
+}
+
+static inline void plda_pcie_disable_ltr(struct pcie_plda *plda)
+{
+	u32 value;
+
+	value = readl(plda->reg_base + PMSG_SUPPORT_RX);
+	value &= ~PMSG_LTR_SUPPORT;
+	writel(value, plda->reg_base + PMSG_SUPPORT_RX);
+}
+
+static inline void plda_pcie_disable_func(struct pcie_plda *plda)
+{
+	u32 value;
+
+	value = readl(plda->reg_base + PCI_MISC);
+	value |= PLDA_FUNCTION_DIS;
+	writel(value, plda->reg_base + PCI_MISC);
+}
+#endif
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 72b41398f2..624841e9d8 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -12,23 +12,15 @@
  */
 
 #include <common.h>
-#include <clk.h>
 #include <dm.h>
-#include <asm/global_data.h>
 #include <dm/device_compat.h>
 #include <generic-phy.h>
 #include <pci.h>
-#include <power-domain.h>
 #include <power/regulator.h>
 #include <reset.h>
-#include <syscon.h>
-#include <asm/io.h>
 #include <asm-generic/gpio.h>
-#include <asm/arch-rockchip/clock.h>
 #include <linux/iopoll.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define HIWORD_UPDATE(mask, val)        (((mask) << 16) | (val))
 #define HIWORD_UPDATE_BIT(val)          HIWORD_UPDATE(val, val)
 
@@ -383,41 +375,38 @@ static int rockchip_pcie_set_vpcie(struct udevice *dev)
 	struct rockchip_pcie *priv = dev_get_priv(dev);
 	int ret;
 
-	if (priv->vpcie3v3) {
-		ret = regulator_set_enable(priv->vpcie3v3, true);
-		if (ret) {
-			dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",
-				ret);
-			return ret;
-		}
+	ret = regulator_set_enable_if_allowed(priv->vpcie12v, true);
+	if (ret && ret != -ENOSYS) {
+		dev_err(dev, "failed to enable vpcie12v (ret=%d)\n", ret);
+		return ret;
 	}
 
-	if (priv->vpcie1v8) {
-		ret = regulator_set_enable(priv->vpcie1v8, true);
-		if (ret) {
-			dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n",
-				ret);
-			goto err_disable_3v3;
-		}
+	ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
+	if (ret && ret != -ENOSYS) {
+		dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret);
+		goto err_disable_12v;
 	}
 
-	if (priv->vpcie0v9) {
-		ret = regulator_set_enable(priv->vpcie0v9, true);
-		if (ret) {
-			dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n",
-				ret);
-			goto err_disable_1v8;
-		}
+	ret = regulator_set_enable_if_allowed(priv->vpcie1v8, true);
+	if (ret && ret != -ENOSYS) {
+		dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", ret);
+		goto err_disable_3v3;
+	}
+
+	ret = regulator_set_enable_if_allowed(priv->vpcie0v9, true);
+	if (ret && ret != -ENOSYS) {
+		dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", ret);
+		goto err_disable_1v8;
 	}
 
 	return 0;
 
 err_disable_1v8:
-	if (priv->vpcie1v8)
-		regulator_set_enable(priv->vpcie1v8, false);
+	regulator_set_enable_if_allowed(priv->vpcie1v8, false);
 err_disable_3v3:
-	if (priv->vpcie3v3)
-		regulator_set_enable(priv->vpcie3v3, false);
+	regulator_set_enable_if_allowed(priv->vpcie3v3, false);
+err_disable_12v:
+	regulator_set_enable_if_allowed(priv->vpcie12v, false);
 	return ret;
 }
 
@@ -427,19 +416,12 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
 	int ret;
 
 	priv->axi_base = dev_read_addr_name(dev, "axi-base");
-	if (!priv->axi_base)
-		return -ENODEV;
+	if (priv->axi_base == FDT_ADDR_T_NONE)
+		return -EINVAL;
 
 	priv->apb_base = dev_read_addr_name(dev, "apb-base");
-	if (!priv->axi_base)
-		return -ENODEV;
-
-	ret = gpio_request_by_name(dev, "ep-gpios", 0,
-				   &priv->ep_gpio, GPIOD_IS_OUT);
-	if (ret) {
-		dev_err(dev, "failed to find ep-gpios property\n");
-		return ret;
-	}
+	if (priv->apb_base == FDT_ADDR_T_NONE)
+		return -EINVAL;
 
 	ret = reset_get_by_name(dev, "core", &priv->core_rst);
 	if (ret) {
@@ -483,6 +465,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
 		return ret;
 	}
 
+	ret = device_get_supply_regulator(dev, "vpcie12v-supply",
+					  &priv->vpcie12v);
+	if (ret && ret != -ENOENT) {
+		dev_err(dev, "failed to get vpcie12v supply (ret=%d)\n", ret);
+		return ret;
+	}
+
 	ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
 					  &priv->vpcie3v3);
 	if (ret && ret != -ENOENT) {
@@ -510,6 +499,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
 		return ret;
 	}
 
+	ret = gpio_request_by_name(dev, "ep-gpios", 0,
+				   &priv->ep_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "failed to find ep-gpios property\n");
+		return ret;
+	}
+
 	return 0;
 }
 
@@ -529,16 +525,26 @@ static int rockchip_pcie_probe(struct udevice *dev)
 
 	ret = rockchip_pcie_set_vpcie(dev);
 	if (ret)
-		return ret;
+		goto err_gpio_free;
 
 	ret = rockchip_pcie_init_port(dev);
 	if (ret)
-		return ret;
+		goto err_disable_vpcie;
 
 	dev_info(dev, "PCIE-%d: Link up (Bus%d)\n",
 		 dev_seq(dev), hose->first_busno);
 
 	return 0;
+
+err_disable_vpcie:
+	regulator_set_enable_if_allowed(priv->vpcie0v9, false);
+	regulator_set_enable_if_allowed(priv->vpcie1v8, false);
+	regulator_set_enable_if_allowed(priv->vpcie3v3, false);
+	regulator_set_enable_if_allowed(priv->vpcie12v, false);
+err_gpio_free:
+	if (dm_gpio_is_valid(&priv->ep_gpio))
+		dm_gpio_free(dev, &priv->ep_gpio);
+	return ret;
 }
 
 static const struct dm_pci_ops rockchip_pcie_ops = {
@@ -552,10 +558,10 @@ static const struct udevice_id rockchip_pcie_ids[] = {
 };
 
 U_BOOT_DRIVER(rockchip_pcie) = {
-	.name			= "rockchip_pcie",
-	.id			= UCLASS_PCI,
-	.of_match		= rockchip_pcie_ids,
-	.ops			= &rockchip_pcie_ops,
-	.probe			= rockchip_pcie_probe,
+	.name		= "rockchip_pcie",
+	.id		= UCLASS_PCI,
+	.of_match	= rockchip_pcie_ids,
+	.ops		= &rockchip_pcie_ops,
+	.probe		= rockchip_pcie_probe,
 	.priv_auto	= sizeof(struct rockchip_pcie),
 };
diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c
new file mode 100644
index 0000000000..903a544d37
--- /dev/null
+++ b/drivers/pci/pcie_starfive_jh7110.c
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive PLDA PCIe host controller driver
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Mason Huo <mason.huo@starfivetech.com>
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <power-domain.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include "pcie_plda_common.h"
+
+/* system control */
+#define STG_SYSCON_K_RP_NEP_MASK               BIT(8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK       GENMASK(22, 8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT      8
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK       GENMASK(14, 0)
+#define STG_SYSCON_CLKREQ_MASK                 BIT(22)
+#define STG_SYSCON_CKREF_SRC_SHIFT             18
+#define STG_SYSCON_CKREF_SRC_MASK              GENMASK(19, 18)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct starfive_pcie {
+	struct pcie_plda plda;
+	struct clk_bulk	clks;
+	struct reset_ctl_bulk	rsts;
+	struct gpio_desc	reset_gpio;
+	struct regmap *regmap;
+	u32 stg_arfun;
+	u32 stg_awfun;
+	u32 stg_rp_nep;
+};
+
+static int starfive_pcie_atr_init(struct starfive_pcie *priv)
+{
+	struct udevice *ctlr = pci_get_controller(priv->plda.dev);
+	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+	int i, ret;
+
+	/*
+	 * As the two host bridges in JH7110 soc have the same default
+	 * address translation table, this cause the second root port can't
+	 * access it's host bridge config space correctly.
+	 * To workaround, config the ATR of host bridge config space by SW.
+	 */
+
+	ret = plda_pcie_set_atr_entry(&priv->plda,
+				      (phys_addr_t)priv->plda.cfg_base, 0,
+				      priv->plda.cfg_size,
+				      XR3PCI_ATR_TRSLID_PCIE_CONFIG);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < hose->region_count; i++) {
+		if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
+			continue;
+
+		/* Only support identity mappings. */
+		if (hose->regions[i].bus_start !=
+		    hose->regions[i].phys_start)
+			return -EINVAL;
+
+		ret = plda_pcie_set_atr_entry(&priv->plda,
+					      hose->regions[i].phys_start,
+					      hose->regions[i].bus_start,
+					      hose->regions[i].size,
+					      XR3PCI_ATR_TRSLID_PCIE_MEMORY);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int starfive_pcie_get_syscon(struct udevice *dev)
+{
+	struct starfive_pcie *priv = dev_get_priv(dev);
+	struct udevice *syscon;
+	struct ofnode_phandle_args syscfg_phandle;
+	u32 cells[4];
+	int ret;
+
+	/* get corresponding syscon phandle */
+	ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 0, 0,
+					 &syscfg_phandle);
+
+	if (ret < 0) {
+		dev_err(dev, "Can't get syscfg phandle: %d\n", ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, syscfg_phandle.node,
+					  &syscon);
+	if (ret) {
+		dev_err(dev, "Unable to find syscon device (%d)\n", ret);
+		return ret;
+	}
+
+	priv->regmap = syscon_get_regmap(syscon);
+	if (!priv->regmap) {
+		dev_err(dev, "Unable to find regmap\n");
+		return -ENODEV;
+	}
+
+	/* get syscon register offset */
+	ret = dev_read_u32_array(dev, "starfive,stg-syscon",
+				 cells, ARRAY_SIZE(cells));
+	if (ret) {
+		dev_err(dev, "Get syscon register err %d\n", ret);
+		return -EINVAL;
+	}
+
+	dev_dbg(dev, "Get syscon values: %x, %x, %x\n",
+		cells[1], cells[2], cells[3]);
+	priv->stg_arfun = cells[1];
+	priv->stg_awfun = cells[2];
+	priv->stg_rp_nep = cells[3];
+
+	return 0;
+}
+
+static int starfive_pcie_parse_dt(struct udevice *dev)
+{
+	struct starfive_pcie *priv = dev_get_priv(dev);
+	int ret;
+
+	priv->plda.reg_base = (void *)dev_read_addr_name(dev, "reg");
+	if (priv->plda.reg_base == (void __iomem *)FDT_ADDR_T_NONE) {
+		dev_err(dev, "Missing required reg address range\n");
+		return -EINVAL;
+	}
+
+	priv->plda.cfg_base =
+		(void *)dev_read_addr_size_name(dev,
+						"config",
+						&priv->plda.cfg_size);
+	if (priv->plda.cfg_base == (void __iomem *)FDT_ADDR_T_NONE) {
+		dev_err(dev, "Missing required config address range");
+		return -EINVAL;
+	}
+
+	ret = starfive_pcie_get_syscon(dev);
+	if (ret) {
+		dev_err(dev, "Can't get syscon: %d\n", ret);
+		return ret;
+	}
+
+	ret = reset_get_bulk(dev, &priv->rsts);
+	if (ret) {
+		dev_err(dev, "Can't get reset: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_get_bulk(dev, &priv->clks);
+	if (ret) {
+		dev_err(dev, "Can't get clock: %d\n", ret);
+		return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
+				   GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "Can't get reset-gpio: %d\n", ret);
+		return ret;
+	}
+
+	if (!dm_gpio_is_valid(&priv->reset_gpio)) {
+		dev_err(dev, "reset-gpio is not valid\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int starfive_pcie_init_port(struct udevice *dev)
+{
+	int ret, i;
+	struct starfive_pcie *priv = dev_get_priv(dev);
+	struct pcie_plda *plda = &priv->plda;
+
+	ret = clk_enable_bulk(&priv->clks);
+	if (ret) {
+		dev_err(dev, "Failed to enable clks (ret=%d)\n", ret);
+		return ret;
+	}
+
+	ret = reset_deassert_bulk(&priv->rsts);
+	if (ret) {
+		dev_err(dev, "Failed to deassert resets (ret=%d)\n", ret);
+		goto err_deassert_clk;
+	}
+
+	dm_gpio_set_value(&priv->reset_gpio, 1);
+	/* Disable physical functions except #0 */
+	for (i = 1; i < PLDA_FUNC_NUM; i++) {
+		regmap_update_bits(priv->regmap,
+				   priv->stg_arfun,
+				   STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
+				   (i << PLDA_PHY_FUNC_SHIFT) <<
+				   STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
+		regmap_update_bits(priv->regmap,
+				   priv->stg_awfun,
+				   STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
+				   i << PLDA_PHY_FUNC_SHIFT);
+
+		plda_pcie_disable_func(plda);
+	}
+
+	/* Disable physical functions */
+	regmap_update_bits(priv->regmap,
+			   priv->stg_arfun,
+			   STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
+			   0);
+	regmap_update_bits(priv->regmap,
+			   priv->stg_awfun,
+			   STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
+			   0);
+
+	plda_pcie_enable_root_port(plda);
+
+	/* PCIe PCI Standard Configuration Identification Settings. */
+	plda_pcie_set_standard_class(plda);
+
+	/*
+	 * The LTR message forwarding of PCIe Message Reception was set by core
+	 * as default, but the forward id & addr are also need to be reset.
+	 * If we do not disable LTR message forwarding here, or set a legal
+	 * forwarding address, the kernel will get stuck after this driver probe.
+	 * To workaround, disable the LTR message forwarding support on
+	 * PCIe Message Reception.
+	 */
+	plda_pcie_disable_ltr(plda);
+
+	/* Prefetchable memory window 64-bit addressing support */
+	plda_pcie_set_pref_win_64bit(plda);
+	starfive_pcie_atr_init(priv);
+
+	dm_gpio_set_value(&priv->reset_gpio, 0);
+	/* Ensure that PERST in default at least 300 ms */
+	mdelay(300);
+
+	return 0;
+
+err_deassert_clk:
+	clk_disable_bulk(&priv->clks);
+	return ret;
+}
+
+static int starfive_pcie_probe(struct udevice *dev)
+{
+	struct starfive_pcie *priv = dev_get_priv(dev);
+	int ret;
+
+	priv->plda.atr_table_num = 0;
+	priv->plda.dev = dev;
+
+	ret = starfive_pcie_parse_dt(dev);
+	if (ret)
+		return ret;
+
+	regmap_update_bits(priv->regmap,
+			   priv->stg_rp_nep,
+			   STG_SYSCON_K_RP_NEP_MASK,
+			   STG_SYSCON_K_RP_NEP_MASK);
+
+	regmap_update_bits(priv->regmap,
+			   priv->stg_awfun,
+			   STG_SYSCON_CKREF_SRC_MASK,
+			   2 << STG_SYSCON_CKREF_SRC_SHIFT);
+
+	regmap_update_bits(priv->regmap,
+			   priv->stg_awfun,
+			   STG_SYSCON_CLKREQ_MASK,
+			   STG_SYSCON_CLKREQ_MASK);
+
+	ret = starfive_pcie_init_port(dev);
+	if (ret)
+		return ret;
+
+	dev_err(dev, "Starfive PCIe bus probed.\n");
+
+	return 0;
+}
+
+static const struct dm_pci_ops starfive_pcie_ops = {
+	.read_config	= plda_pcie_config_read,
+	.write_config	= plda_pcie_config_write,
+};
+
+static const struct udevice_id starfive_pcie_ids[] = {
+	{ .compatible = "starfive,jh7110-pcie" },
+	{ }
+};
+
+U_BOOT_DRIVER(starfive_pcie_drv) = {
+	.name			= "starfive_7110_pcie",
+	.id			= UCLASS_PCI,
+	.of_match		= starfive_pcie_ids,
+	.ops			= &starfive_pcie_ops,
+	.probe			= starfive_pcie_probe,
+	.priv_auto	= sizeof(struct starfive_pcie),
+};
diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
index f8f1e99c4f..bb0bd8d5f8 100644
--- a/drivers/phy/allwinner/Kconfig
+++ b/drivers/phy/allwinner/Kconfig
@@ -4,6 +4,9 @@
 config PHY_SUN4I_USB
 	bool "Allwinner Sun4I USB PHY driver"
 	depends on ARCH_SUNXI
+	depends on !MACH_SUN9I
+	default n if MACH_SUN8I_V3S
+	default y
 	select DM_REGULATOR
 	select PHY
 	help
@@ -11,7 +14,7 @@ config PHY_SUN4I_USB
 	  sunxi SoCs.
 
 	  This driver controls the entire USB PHY block, both the USB OTG
-	  parts, as well as the 2 regular USB 2 host PHYs.
+	  parts, as well as the regular USB HCI host PHYs.
 
 config INITIAL_USB_SCAN_DELAY
 	int "Delay initial USB scan by x ms to allow builtin devices to init"
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 6428163c18..77dffcad88 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -73,26 +73,16 @@
 
 #define MAX_PHYS			4
 
-enum sun4i_usb_phy_type {
-	sun4i_a10_phy,
-	sun6i_a31_phy,
-	sun8i_a33_phy,
-	sun8i_a83t_phy,
-	sun8i_h3_phy,
-	sun8i_r40_phy,
-	sun8i_v3s_phy,
-	sun50i_a64_phy,
-	sun50i_h6_phy,
-};
-
 struct sun4i_usb_phy_cfg {
 	int num_phys;
-	enum sun4i_usb_phy_type type;
+	int hsic_index;
 	u32 disc_thresh;
 	u32 hci_phy_ctl_clear;
 	u8 phyctl_offset;
 	bool dedicated_clocks;
 	bool phy0_dual_route;
+	bool siddq_in_base;
+	bool needs_phy2_siddq;
 	int missing_phys;
 };
 
@@ -129,6 +119,7 @@ struct sun4i_usb_phy_plat {
 	struct gpio_desc gpio_vbus_det;
 	struct gpio_desc gpio_id_det;
 	struct clk clocks;
+	struct clk clk2;
 	struct reset_ctl resets;
 	int id;
 };
@@ -200,7 +191,7 @@ static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
 		SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 
 	/* A83T USB2 is HSIC */
-	if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
+	if (data->cfg->hsic_index && usb_phy->id == data->cfg->hsic_index)
 		bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
 			SUNXI_HSIC;
 
@@ -283,14 +274,48 @@ static int sun4i_usb_phy_init(struct phy *phy)
 		return ret;
 	}
 
+	/* Some PHYs on some SoCs (the H616) need the help of PHY2 to work. */
+	if (data->cfg->needs_phy2_siddq && phy->id != 2) {
+		struct sun4i_usb_phy_plat *phy2 = &data->usb_phy[2];
+
+		ret = clk_enable(&phy2->clocks);
+		if (ret) {
+			dev_err(phy->dev, "failed to enable aux clock\n");
+			return ret;
+		}
+
+		ret = reset_deassert(&phy2->resets);
+		if (ret) {
+			dev_err(phy->dev, "failed to deassert aux reset\n");
+			return ret;
+		}
+
+		/*
+		 * This extra clock is just needed to access the
+		 * REG_HCI_PHY_CTL PMU register for PHY2.
+		 */
+		ret = clk_enable(&phy2->clk2);
+		if (ret) {
+			dev_err(phy->dev, "failed to enable PHY2 clock\n");
+			return ret;
+		}
+
+		if (phy2->pmu && data->cfg->hci_phy_ctl_clear) {
+			val = readl(phy2->pmu + REG_HCI_PHY_CTL);
+			val &= ~data->cfg->hci_phy_ctl_clear;
+			writel(val, phy2->pmu + REG_HCI_PHY_CTL);
+		}
+
+		clk_disable(&phy2->clk2);
+	}
+
 	if (usb_phy->pmu && data->cfg->hci_phy_ctl_clear) {
 		val = readl(usb_phy->pmu + REG_HCI_PHY_CTL);
 		val &= ~data->cfg->hci_phy_ctl_clear;
 		writel(val, usb_phy->pmu + REG_HCI_PHY_CTL);
 	}
 
-	if (data->cfg->type == sun8i_a83t_phy ||
-	    data->cfg->type == sun50i_h6_phy) {
+	if (data->cfg->siddq_in_base) {
 		if (phy->id == 0) {
 			val = readl(data->base + data->cfg->phyctl_offset);
 			val |= PHY_CTL_VBUSVLDEXT;
@@ -339,8 +364,7 @@ static int sun4i_usb_phy_exit(struct phy *phy)
 	int ret;
 
 	if (phy->id == 0) {
-		if (data->cfg->type == sun8i_a83t_phy ||
-		    data->cfg->type == sun50i_h6_phy) {
+		if (data->cfg->siddq_in_base) {
 			void __iomem *phyctl = data->base +
 				data->cfg->phyctl_offset;
 
@@ -372,7 +396,10 @@ static int sun4i_usb_phy_xlate(struct phy *phy,
 {
 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 
-	if (args->args_count >= data->cfg->num_phys)
+	if (args->args_count != 1)
+		return -EINVAL;
+
+	if (args->args[0] >= data->cfg->num_phys)
 		return -EINVAL;
 
 	if (data->cfg->missing_phys & BIT(args->args[0]))
@@ -510,6 +537,15 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 			return ret;
 		}
 
+		/* Helper clock from PHY2 for the H616 PHY quirk */
+		snprintf(name, sizeof(name), "pmu%d_clk", i);
+		ret = clk_get_by_name_optional(dev, name, &phy->clk2);
+		if (ret) {
+			dev_err(dev, "failed to get pmu%d_clk clock phandle\n",
+				i);
+			return ret;
+		}
+
 		snprintf(name, sizeof(name), "usb%d_reset", i);
 		ret = reset_get_by_name(dev, name, &phy->resets);
 		if (ret) {
@@ -533,7 +569,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 
 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 	.num_phys = 3,
-	.type = sun4i_a10_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = false,
@@ -541,7 +576,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 
 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 	.num_phys = 2,
-	.type = sun4i_a10_phy,
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = false,
@@ -549,7 +583,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 
 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 	.num_phys = 3,
-	.type = sun6i_a31_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = true,
@@ -557,7 +590,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 
 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 	.num_phys = 3,
-	.type = sun4i_a10_phy,
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = false,
@@ -565,7 +597,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 
 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 	.num_phys = 2,
-	.type = sun4i_a10_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = true,
@@ -573,7 +604,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 
 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 	.num_phys = 2,
-	.type = sun8i_a33_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
@@ -581,14 +611,14 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 
 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 	.num_phys = 3,
-	.type = sun8i_a83t_phy,
+	.hsic_index = 2,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
+	.siddq_in_base = true,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.num_phys = 4,
-	.type = sun8i_h3_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
@@ -598,7 +628,6 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 
 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
 	.num_phys = 3,
-	.type = sun8i_r40_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
@@ -608,7 +637,6 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
 
 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 	.num_phys = 1,
-	.type = sun8i_v3s_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
@@ -618,16 +646,15 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 
 static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
 	.num_phys = 2,
-	.type = sun50i_h6_phy,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
 	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
 	.phy0_dual_route = true,
+	.siddq_in_base = true,
 };
 
 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.num_phys = 2,
-	.type = sun50i_a64_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
@@ -637,14 +664,32 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 
 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
 	.num_phys = 4,
-	.type = sun50i_h6_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
 	.phy0_dual_route = true,
+	.siddq_in_base = true,
 	.missing_phys = BIT(1) | BIT(2),
 };
 
+static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
+	.num_phys = 4,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
+	.phy0_dual_route = true,
+	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
+	.needs_phy2_siddq = true,
+	.siddq_in_base = true,
+};
+
+static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
+	.num_phys = 1,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = true,
+};
+
 static const struct udevice_id sun4i_usb_phy_ids[] = {
 	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
 	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
@@ -659,6 +704,8 @@ static const struct udevice_id sun4i_usb_phy_ids[] = {
 	{ .compatible = "allwinner,sun20i-d1-usb-phy", .data = (ulong)&sun20i_d1_cfg },
 	{ .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg},
+	{ .compatible = "allwinner,sun50i-h616-usb-phy", .data = (ulong)&sun50i_h616_cfg },
+	{ .compatible = "allwinner,suniv-f1c100s-usb-phy", .data = (ulong)&suniv_f1c100s_cfg },
 	{ }
 };
 
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index e063b51c6d..a7e0099045 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MV_SIP_COMPHY_PLL_LOCK	0x82000003
 #define MV_SIP_COMPHY_XFI_TRAIN	0x82000004
 
-/* Used to distinguish between different possible callers (U-boot/Linux) */
+/* Used to distinguish between different possible callers (U-Boot/Linux) */
 #define COMPHY_CALLER_UBOOT			(0x1 << 21)
 
 #define COMPHY_FW_MODE_FORMAT(mode)		((mode) << 12)
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index f87ca8c310..0247d93ab4 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -41,6 +41,13 @@ config PHY_ROCKCHIP_SNPS_PCIE3
 	  It could support PCIe Gen3 single root complex, and could
 	  also be able splited into multiple combinations of lanes.
 
+config PHY_ROCKCHIP_USBDP
+	tristate "Rockchip USBDP COMBO PHY Driver"
+	depends on ARCH_ROCKCHIP
+	select PHY
+	help
+	  Enable this to support the Rockchip USB3.0/DP
+	  combo PHY with Samsung IP block.
 
 config PHY_ROCKCHIP_TYPEC
 	bool "Rockchip TYPEC PHY Driver"
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 25a803a8a8..7fdbd10797 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
 obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3)	+= phy-rockchip-snps-pcie3.o
 obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
+obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index e43a5ba9b5..70e61eccb7 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -259,7 +259,7 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
 	}
 
 	/* support address_cells=2 */
-	if (reg == 0) {
+	if (dev_read_addr_cells(dev) == 2 && reg == 0) {
 		if (ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, &reg)) {
 			dev_err(dev, "%s must have reg[1]\n",
 				ofnode_get_name(dev_ofnode(dev)));
@@ -345,6 +345,36 @@ bind_fail:
 	return ret;
 }
 
+static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = {
+	{
+		.reg = 0x100,
+		.clkout_ctl	= { 0x108, 4, 4, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x0100, 15, 0, 0, 0x1d1 },
+				.bvalid_det_en	= { 0x0110, 3, 2, 0, 3 },
+				.bvalid_det_st	= { 0x0114, 3, 2, 0, 3 },
+				.bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
+				.ls_det_en	= { 0x0110, 0, 0, 0, 1 },
+				.ls_det_st	= { 0x0114, 0, 0, 0, 1 },
+				.ls_det_clr	= { 0x0118, 0, 0, 0, 1 },
+				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
+				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
+				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0x104, 15, 0, 0, 0x1d1 },
+				.ls_det_en	= { 0x110, 1, 1, 0, 1 },
+				.ls_det_st	= { 0x114, 1, 1, 0, 1 },
+				.ls_det_clr	= { 0x118, 1, 1, 0, 1 },
+				.utmi_ls	= { 0x120, 17, 16, 0, 1 },
+				.utmi_hstdet	= { 0x120, 19, 19, 0, 1 }
+			}
+		},
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
 	{
 		.reg		= 0xe450,
@@ -499,6 +529,10 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
 
 static const struct udevice_id rockchip_usb2phy_ids[] = {
 	{
+		.compatible = "rockchip,rk3328-usb2phy",
+		.data = (ulong)&rk3328_usb2phy_cfgs,
+	},
+	{
 		.compatible = "rockchip,rk3399-usb2phy",
 		.data = (ulong)&rk3399_usb2phy_cfgs,
 	},
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
new file mode 100644
index 0000000000..baf9252934
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -0,0 +1,880 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Rockchip USBDP Combo PHY with Samsung IP block driver
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <dm/lists.h>
+#include <dm/of.h>
+#include <dm/of_access.h>
+#include <generic-phy.h>
+#include <linux/bitfield.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/otg.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+#include <linux/usb/phy-rockchip-usbdp.h>
+
+#define BIT_WRITEABLE_SHIFT	16
+
+enum {
+	UDPHY_MODE_NONE		= 0,
+	UDPHY_MODE_USB		= BIT(0),
+	UDPHY_MODE_DP		= BIT(1),
+	UDPHY_MODE_DP_USB	= BIT(1) | BIT(0),
+};
+
+struct udphy_grf_reg {
+	unsigned int	offset;
+	unsigned int	bitend;
+	unsigned int	bitstart;
+	unsigned int	disable;
+	unsigned int	enable;
+};
+
+/**
+ * struct reg_sequence - An individual write from a sequence of writes.
+ *
+ * @reg: Register address.
+ * @def: Register value.
+ * @delay_us: Delay to be applied after the register write in microseconds
+ *
+ * Register/value pairs for sequences of writes with an optional delay in
+ * microseconds to be applied after each write.
+ */
+struct reg_sequence {
+	unsigned int reg;
+	unsigned int def;
+	unsigned int delay_us;
+};
+
+struct udphy_grf_cfg {
+	/* u2phy-grf */
+	struct udphy_grf_reg	bvalid_phy_con;
+	struct udphy_grf_reg	bvalid_grf_con;
+
+	/* usb-grf */
+	struct udphy_grf_reg	usb3otg0_cfg;
+	struct udphy_grf_reg	usb3otg1_cfg;
+
+	/* usbdpphy-grf */
+	struct udphy_grf_reg	low_pwrn;
+	struct udphy_grf_reg	rx_lfps;
+};
+
+struct rockchip_udphy;
+
+struct rockchip_udphy_cfg {
+	/* resets to be requested */
+	const char * const *rst_list;
+	int num_rsts;
+
+	struct udphy_grf_cfg grfcfg;
+	int (*combophy_init)(struct rockchip_udphy *udphy);
+};
+
+struct rockchip_udphy {
+	struct udevice *dev;
+	struct regmap *pma_regmap;
+	struct regmap *u2phygrf;
+	struct regmap *udphygrf;
+	struct regmap *usbgrf;
+	struct regmap *vogrf;
+
+	/* clocks and rests */
+	struct reset_ctl *rsts;
+
+	/* PHY status management */
+	bool flip;
+	bool mode_change;
+	u8 mode;
+	u8 status;
+
+	/* utilized for USB */
+	bool hs; /* flag for high-speed */
+
+	/* utilized for DP */
+	struct gpio_desc *sbu1_dc_gpio;
+	struct gpio_desc *sbu2_dc_gpio;
+	u32 lane_mux_sel[4];
+	u32 dp_lane_sel[4];
+	u32 dp_aux_dout_sel;
+	u32 dp_aux_din_sel;
+	int id;
+
+	/* PHY const config */
+	const struct rockchip_udphy_cfg *cfgs;
+};
+
+static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = {
+	{0x0090, 0x68}, {0x0094, 0x68},
+	{0x0128, 0x24}, {0x012c, 0x44},
+	{0x0130, 0x3f}, {0x0134, 0x44},
+	{0x015c, 0xa9}, {0x0160, 0x71},
+	{0x0164, 0x71}, {0x0168, 0xa9},
+	{0x0174, 0xa9}, {0x0178, 0x71},
+	{0x017c, 0x71}, {0x0180, 0xa9},
+	{0x018c, 0x41}, {0x0190, 0x00},
+	{0x0194, 0x05}, {0x01ac, 0x2a},
+	{0x01b0, 0x17}, {0x01b4, 0x17},
+	{0x01b8, 0x2a}, {0x01c8, 0x04},
+	{0x01cc, 0x08}, {0x01d0, 0x08},
+	{0x01d4, 0x04}, {0x01d8, 0x20},
+	{0x01dc, 0x01}, {0x01e0, 0x09},
+	{0x01e4, 0x03}, {0x01f0, 0x29},
+	{0x01f4, 0x02}, {0x01f8, 0x02},
+	{0x01fc, 0x29}, {0x0208, 0x2a},
+	{0x020c, 0x17}, {0x0210, 0x17},
+	{0x0214, 0x2a}, {0x0224, 0x20},
+	{0x03f0, 0x0d}, {0x03f4, 0x09},
+	{0x03f8, 0x09}, {0x03fc, 0x0d},
+	{0x0404, 0x0e}, {0x0408, 0x14},
+	{0x040c, 0x14}, {0x0410, 0x3b},
+	{0x0ce0, 0x68}, {0x0ce8, 0xd0},
+	{0x0cf0, 0x87}, {0x0cf8, 0x70},
+	{0x0d00, 0x70}, {0x0d08, 0xa9},
+	{0x1ce0, 0x68}, {0x1ce8, 0xd0},
+	{0x1cf0, 0x87}, {0x1cf8, 0x70},
+	{0x1d00, 0x70}, {0x1d08, 0xa9},
+	{0x0a3c, 0xd0}, {0x0a44, 0xd0},
+	{0x0a48, 0x01}, {0x0a4c, 0x0d},
+	{0x0a54, 0xe0}, {0x0a5c, 0xe0},
+	{0x0a64, 0xa8}, {0x1a3c, 0xd0},
+	{0x1a44, 0xd0}, {0x1a48, 0x01},
+	{0x1a4c, 0x0d}, {0x1a54, 0xe0},
+	{0x1a5c, 0xe0}, {0x1a64, 0xa8}
+};
+
+static const struct reg_sequence rk3588_udphy_init_sequence[] = {
+	{0x0104, 0x44}, {0x0234, 0xE8},
+	{0x0248, 0x44}, {0x028C, 0x18},
+	{0x081C, 0xE5}, {0x0878, 0x00},
+	{0x0994, 0x1C}, {0x0AF0, 0x00},
+	{0x181C, 0xE5}, {0x1878, 0x00},
+	{0x1994, 0x1C}, {0x1AF0, 0x00},
+	{0x0428, 0x60}, {0x0D58, 0x33},
+	{0x1D58, 0x33}, {0x0990, 0x74},
+	{0x0D64, 0x17}, {0x08C8, 0x13},
+	{0x1990, 0x74}, {0x1D64, 0x17},
+	{0x18C8, 0x13}, {0x0D90, 0x40},
+	{0x0DA8, 0x40}, {0x0DC0, 0x40},
+	{0x0DD8, 0x40}, {0x1D90, 0x40},
+	{0x1DA8, 0x40}, {0x1DC0, 0x40},
+	{0x1DD8, 0x40}, {0x03C0, 0x30},
+	{0x03C4, 0x06}, {0x0E10, 0x00},
+	{0x1E10, 0x00}, {0x043C, 0x0F},
+	{0x0D2C, 0xFF}, {0x1D2C, 0xFF},
+	{0x0D34, 0x0F}, {0x1D34, 0x0F},
+	{0x08FC, 0x2A}, {0x0914, 0x28},
+	{0x0A30, 0x03}, {0x0E38, 0x05},
+	{0x0ECC, 0x27}, {0x0ED0, 0x22},
+	{0x0ED4, 0x26}, {0x18FC, 0x2A},
+	{0x1914, 0x28}, {0x1A30, 0x03},
+	{0x1E38, 0x05}, {0x1ECC, 0x27},
+	{0x1ED0, 0x22}, {0x1ED4, 0x26},
+	{0x0048, 0x0F}, {0x0060, 0x3C},
+	{0x0064, 0xF7}, {0x006C, 0x20},
+	{0x0070, 0x7D}, {0x0074, 0x68},
+	{0x0AF4, 0x1A}, {0x1AF4, 0x1A},
+	{0x0440, 0x3F}, {0x10D4, 0x08},
+	{0x20D4, 0x08}, {0x00D4, 0x30},
+	{0x0024, 0x6e},
+};
+
+static inline int grfreg_write(struct regmap *base,
+			       const struct udphy_grf_reg *reg, bool en)
+{
+	u32 val, mask, tmp;
+
+	tmp = en ? reg->enable : reg->disable;
+	mask = GENMASK(reg->bitend, reg->bitstart);
+	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+	return regmap_write(base, reg->offset, val);
+}
+
+static int __regmap_multi_reg_write(struct regmap *map,
+				    const struct reg_sequence *regs,
+				    int num_regs)
+{
+	int i, ret = 0;
+
+	for (i = 0; i < num_regs; i++) {
+		ret = regmap_write(map, regs[i].reg, regs[i].def);
+
+		if (regs[i].delay_us)
+			udelay(regs[i].delay_us);
+	}
+
+	return ret;
+}
+
+static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev)
+{
+	return 0;
+}
+
+static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev)
+{
+	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+	int idx;
+	int ret;
+
+	udphy->rsts = devm_kcalloc(dev, cfg->num_rsts,
+				   sizeof(*udphy->rsts), GFP_KERNEL);
+	if (!udphy->rsts)
+		return -ENOMEM;
+
+	for (idx = 0; idx < cfg->num_rsts; idx++) {
+		const char *name = cfg->rst_list[idx];
+
+		ret = reset_get_by_name(dev, name, &udphy->rsts[idx]);
+		if (ret) {
+			dev_err(dev, "failed to get %s reset\n", name);
+			goto err;
+		}
+
+		reset_assert(&udphy->rsts[idx]);
+	}
+
+	return 0;
+
+err:
+	devm_kfree(dev, udphy->rsts);
+	return ret;
+}
+
+static int udphy_get_rst_idx(const char * const *list, int num, char *name)
+{
+	int idx;
+
+	for (idx = 0; idx < num; idx++) {
+		if (!strcmp(list[idx], name))
+			return idx;
+	}
+
+	return -EINVAL;
+}
+
+static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name)
+{
+	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+	int idx;
+
+	idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
+	if (idx < 0)
+		return idx;
+
+	return reset_assert(&udphy->rsts[idx]);
+}
+
+static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name)
+{
+	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+	int idx;
+
+	idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
+	if (idx < 0)
+		return idx;
+
+	return reset_deassert(&udphy->rsts[idx]);
+}
+
+static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)
+{
+	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+	const struct udphy_grf_reg *preg;
+
+	preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
+	grfreg_write(udphy->usbgrf, preg, disable);
+}
+
+__maybe_unused
+static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)
+{
+	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+
+	grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
+	grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
+}
+
+/*
+ * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
+ *
+ * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
+ * ---------------------------------------------------------------------------
+ * Type-C Pin   B11-B10       A2-A3       A11-A10       B2-B3
+ * PHY Pad      ln0(tx/rx)    ln1(tx)     ln2(tx/rx)    ln3(tx)
+ * C/E(Normal)  dpln3         dpln2       dpln0         dpln1
+ * C/E(Flip  )  dpln0         dpln1       dpln3         dpln2
+ * D/F(Normal)  usbrx         usbtx       dpln0         dpln1
+ * D/F(Flip  )  dpln0         dpln1       usbrx         usbtx
+ * A(Normal  )  dpln3         dpln1       dpln2         dpln0
+ * A(Flip    )  dpln2         dpln0       dpln3         dpln1
+ * B(Normal  )  usbrx         usbtx       dpln1         dpln0
+ * B(Flip    )  dpln1         dpln0       usbrx         usbtx
+ * ---------------------------------------------------------------------------
+ *
+ * 2 Mapping the lanes in dtsi
+ * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
+ * sample as follow:
+ * ---------------------------------------------------------------------------
+ *                        B11-B10       A2-A3       A11-A10       B2-B3
+ * rockchip,dp-lane-mux   ln0(tx/rx)    ln1(tx)     ln2(tx/rx)    ln3(tx)
+ * <0 1 2 3>              dpln0         dpln1       dpln2         dpln3
+ * <2 3 0 1>              dpln2         dpln3       dpln0         dpln1
+ * ---------------------------------------------------------------------------
+ * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
+ * sample as follow:
+ * ---------------------------------------------------------------------------
+ *                        B11-B10       A2-A3       A11-A10       B2-B3
+ * rockchip,dp-lane-mux   ln0(tx/rx)    ln1(tx)     ln2(tx/rx)    ln3(tx)
+ * <0 1>                  dpln0         dpln1       usbrx         usbtx
+ * <2 3>                  usbrx         usbtx       dpln0         dpln1
+ * ---------------------------------------------------------------------------
+ */
+
+__maybe_unused
+static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy)
+{
+	if (udphy->flip) {
+		udphy->dp_lane_sel[0] = 0;
+		udphy->dp_lane_sel[1] = 1;
+		udphy->dp_lane_sel[2] = 3;
+		udphy->dp_lane_sel[3] = 2;
+		udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
+		udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
+		udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
+		udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
+		udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
+		udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
+	} else {
+		udphy->dp_lane_sel[0] = 2;
+		udphy->dp_lane_sel[1] = 3;
+		udphy->dp_lane_sel[2] = 1;
+		udphy->dp_lane_sel[3] = 0;
+		udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
+		udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
+		udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
+		udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
+		udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
+		udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
+	}
+
+	udphy->mode = UDPHY_MODE_DP_USB;
+
+	return 0;
+}
+
+static int udphy_setup(struct rockchip_udphy *udphy)
+{
+	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+	int ret = 0;
+
+	if (cfg->combophy_init) {
+		ret = cfg->combophy_init(udphy);
+		if (ret)
+			dev_err(udphy->dev, "failed to init usbdp combophy\n");
+	}
+
+	return ret;
+}
+
+static int udphy_disable(struct rockchip_udphy *udphy)
+{
+	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+	int i;
+
+	for (i = 0; i < cfg->num_rsts; i++)
+		reset_assert(&udphy->rsts[i]);
+
+	return 0;
+}
+
+static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy,
+				     const struct device_node *np)
+{
+	struct property *prop;
+	int ret, i, len, num_lanes;
+
+	prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
+	if (!prop) {
+		dev_dbg(udphy->dev,
+			"failed to find dp lane mux, following dp alt mode\n");
+		udphy->mode = UDPHY_MODE_USB;
+		return 0;
+	}
+
+	num_lanes = len / sizeof(u32);
+
+	if (num_lanes != 2 && num_lanes != 4) {
+		dev_err(udphy->dev, "invalid number of lane mux\n");
+		return -EINVAL;
+	}
+
+	ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel,
+				num_lanes);
+	if (ret) {
+		dev_err(udphy->dev, "get dp lane mux failed\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < num_lanes; i++) {
+		int j;
+
+		if (udphy->dp_lane_sel[i] > 3) {
+			dev_err(udphy->dev,
+				"lane mux between 0 and 3, exceeding the range\n");
+			return -EINVAL;
+		}
+
+		udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
+
+		for (j = i + 1; j < num_lanes; j++) {
+			if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
+				dev_err(udphy->dev,
+					"set repeat lane mux value\n");
+				return -EINVAL;
+			}
+		}
+	}
+
+	udphy->mode = UDPHY_MODE_DP;
+	if (num_lanes == 2)
+		udphy->mode |= UDPHY_MODE_USB;
+
+	return 0;
+}
+
+static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)
+{
+	const struct device_node *np = ofnode_to_np(dev_ofnode(dev));
+	enum usb_device_speed maximum_speed;
+	int ret;
+
+	udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev,
+							  "rockchip,u2phy-grf");
+	if (IS_ERR(udphy->u2phygrf)) {
+		if (PTR_ERR(udphy->u2phygrf) == -ENODEV) {
+			dev_warn(dev, "missing u2phy-grf dt node\n");
+			udphy->u2phygrf = NULL;
+		} else {
+			return PTR_ERR(udphy->u2phygrf);
+		}
+	}
+
+	udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev,
+							  "rockchip,usbdpphy-grf");
+	if (IS_ERR(udphy->udphygrf)) {
+		if (PTR_ERR(udphy->udphygrf) == -ENODEV) {
+			dev_warn(dev, "missing usbdpphy-grf dt node\n");
+			udphy->udphygrf = NULL;
+		} else {
+			return PTR_ERR(udphy->udphygrf);
+		}
+	}
+
+	udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev,
+							"rockchip,usb-grf");
+	if (IS_ERR(udphy->usbgrf)) {
+		if (PTR_ERR(udphy->usbgrf) == -ENODEV) {
+			dev_warn(dev, "missing usb-grf dt node\n");
+			udphy->usbgrf = NULL;
+		} else {
+			return PTR_ERR(udphy->usbgrf);
+		}
+	}
+
+	udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf");
+	if (IS_ERR(udphy->vogrf)) {
+		if (PTR_ERR(udphy->vogrf) == -ENODEV) {
+			dev_warn(dev, "missing vo-grf dt node\n");
+			udphy->vogrf = NULL;
+		} else {
+			return PTR_ERR(udphy->vogrf);
+		}
+	}
+
+	ret = udphy_parse_lane_mux_data(udphy, np);
+	if (ret)
+		return ret;
+
+	if (dev_read_prop(dev, "maximum-speed", NULL)) {
+		maximum_speed = usb_get_maximum_speed(dev_ofnode(dev));
+		udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;
+	}
+
+	ret = udphy_clk_init(udphy, dev);
+	if (ret)
+		return ret;
+
+	ret = udphy_reset_init(udphy, dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
+{
+	int ret;
+
+	if (!(udphy->mode & mode)) {
+		dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
+		return 0;
+	}
+
+	if (udphy->status == UDPHY_MODE_NONE) {
+		udphy->mode_change = false;
+		ret = udphy_setup(udphy);
+		if (ret)
+			return ret;
+
+		if (udphy->mode & UDPHY_MODE_USB)
+			udphy_u3_port_disable(udphy, false);
+	} else if (udphy->mode_change) {
+		udphy->mode_change = false;
+		udphy->status = UDPHY_MODE_NONE;
+		if (udphy->mode == UDPHY_MODE_DP)
+			udphy_u3_port_disable(udphy, true);
+
+		ret = udphy_disable(udphy);
+		if (ret)
+			return ret;
+		ret = udphy_setup(udphy);
+		if (ret)
+			return ret;
+	}
+
+	udphy->status |= mode;
+
+	return 0;
+}
+
+static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
+{
+	int ret;
+
+	if (!(udphy->mode & mode)) {
+		dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode);
+		return 0;
+	}
+
+	if (!udphy->status)
+		return 0;
+
+	udphy->status &= ~mode;
+
+	if (udphy->status == UDPHY_MODE_NONE) {
+		ret = udphy_disable(udphy);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_u3phy_init(struct phy *phy)
+{
+	struct udevice *parent = phy->dev->parent;
+	struct rockchip_udphy *udphy = dev_get_priv(parent);
+
+	/* DP only or high-speed, disable U3 port */
+	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
+		udphy_u3_port_disable(udphy, true);
+		return 0;
+	}
+
+	return udphy_power_on(udphy, UDPHY_MODE_USB);
+}
+
+static int rockchip_u3phy_exit(struct phy *phy)
+{
+	struct udevice *parent = phy->dev->parent;
+	struct rockchip_udphy *udphy = dev_get_priv(parent);
+
+	/* DP only or high-speed */
+	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
+		return 0;
+
+	return udphy_power_off(udphy, UDPHY_MODE_USB);
+}
+
+static const struct phy_ops rockchip_u3phy_ops = {
+	.init		= rockchip_u3phy_init,
+	.exit		= rockchip_u3phy_exit,
+};
+
+int rockchip_u3phy_uboot_init(void)
+{
+	struct udevice *udev;
+	struct rockchip_udphy *udphy;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_PHY,
+					  DM_DRIVER_GET(rockchip_udphy_u3_port),
+					  &udev);
+	if (ret) {
+		pr_err("%s: get u3-port failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	/* DP only or high-speed, disable U3 port */
+	udphy = dev_get_priv(udev->parent);
+	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
+		udphy_u3_port_disable(udphy, true);
+		return 0;
+	}
+
+	return udphy_power_on(udphy, UDPHY_MODE_USB);
+}
+
+static int rockchip_udphy_probe(struct udevice *dev)
+{
+	const struct device_node *np = ofnode_to_np(dev_ofnode(dev));
+	struct rockchip_udphy *udphy = dev_get_priv(dev);
+	const struct rockchip_udphy_cfg *phy_cfgs;
+	int id, ret;
+
+	udphy->dev = dev;
+
+	id = of_alias_get_id(np, "usbdp");
+	if (id < 0)
+		id = 0;
+	udphy->id = id;
+
+	phy_cfgs = (const struct rockchip_udphy_cfg *)dev_get_driver_data(dev);
+	if (!phy_cfgs) {
+		dev_err(dev, "unable to get phy_cfgs\n");
+		return -EINVAL;
+	}
+	udphy->cfgs = phy_cfgs;
+
+	ret = regmap_init_mem(dev_ofnode(dev), &udphy->pma_regmap);
+	if (ret)
+		return ret;
+	udphy->pma_regmap->ranges[0].start += UDPHY_PMA;
+
+	ret = udphy_parse_dt(udphy, dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int rockchip_udphy_bind(struct udevice *parent)
+{
+	struct udevice *child;
+	ofnode subnode;
+	const char *node_name;
+	int ret;
+
+	dev_for_each_subnode(subnode, parent) {
+		if (!ofnode_valid(subnode)) {
+			printf("%s: no subnode for %s", __func__, parent->name);
+			return -ENXIO;
+		}
+
+		node_name = ofnode_get_name(subnode);
+		debug("%s: subnode %s\n", __func__, node_name);
+
+		/* if there is no match, continue */
+		if (strcasecmp(node_name, "usb3-port"))
+			continue;
+
+		/* node name is usb3-port */
+		ret = device_bind_driver_to_node(parent,
+						 "rockchip_udphy_u3_port",
+						 node_name, subnode, &child);
+		if (ret) {
+			printf("%s: '%s' cannot bind its driver\n",
+			       __func__, node_name);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
+{
+	/* configure phy reference clock */
+	return __regmap_multi_reg_write(udphy->pma_regmap,
+					rk3588_udphy_24m_refclk_cfg,
+					ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg));
+}
+
+static int rk3588_udphy_status_check(struct rockchip_udphy *udphy)
+{
+	unsigned int val;
+	int ret;
+
+	if (!(udphy->mode & UDPHY_MODE_USB))
+		return 0;
+
+	/* LCPLL check */
+	ret = regmap_read_poll_timeout(udphy->pma_regmap,
+				       CMN_ANA_LCPLL_DONE_OFFSET,
+				       val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
+				       (val & CMN_ANA_LCPLL_LOCK_DONE),
+				       200, 100);
+	if (ret) {
+		dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
+		return ret;
+	}
+
+	if (!udphy->flip) {
+		ret = regmap_read_poll_timeout(udphy->pma_regmap,
+					       TRSV_LN0_MON_RX_CDR_DONE_OFFSET,
+					       val,
+					       val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
+					       200, 100);
+		if (ret)
+			dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
+	} else {
+		ret = regmap_read_poll_timeout(udphy->pma_regmap,
+					       TRSV_LN2_MON_RX_CDR_DONE_OFFSET,
+					       val,
+					       val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
+					       200, 100);
+		if (ret)
+			dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
+	}
+
+	return 0;
+}
+
+static int rk3588_udphy_init(struct rockchip_udphy *udphy)
+{
+	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+	int ret;
+
+	/* enable rx lfps for usb */
+	if (udphy->mode & UDPHY_MODE_USB)
+		grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
+
+	/* Step 1: power on pma and deassert apb rstn */
+	grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
+
+	udphy_reset_deassert(udphy, "pma_apb");
+	udphy_reset_deassert(udphy, "pcs_apb");
+
+	/* Step 2: set init sequence and phy refclk */
+	ret = __regmap_multi_reg_write(udphy->pma_regmap,
+				       rk3588_udphy_init_sequence,
+				       ARRAY_SIZE(rk3588_udphy_init_sequence));
+	if (ret) {
+		dev_err(udphy->dev, "init sequence set error %d\n", ret);
+		goto assert_apb;
+	}
+
+	ret = rk3588_udphy_refclk_set(udphy);
+	if (ret) {
+		dev_err(udphy->dev, "refclk set error %d\n", ret);
+		goto assert_apb;
+	}
+
+	/* Step 3: configure lane mux */
+	regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
+			   CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
+			   FIELD_PREP(CMN_DP_LANE_MUX_N(3),
+				      udphy->lane_mux_sel[3]) |
+			   FIELD_PREP(CMN_DP_LANE_MUX_N(2),
+				      udphy->lane_mux_sel[2]) |
+			   FIELD_PREP(CMN_DP_LANE_MUX_N(1),
+				      udphy->lane_mux_sel[1]) |
+			   FIELD_PREP(CMN_DP_LANE_MUX_N(0),
+				      udphy->lane_mux_sel[0]) |
+			   FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
+
+	/* Step 4: deassert init rstn and wait for 200ns from datasheet */
+	if (udphy->mode & UDPHY_MODE_USB)
+		udphy_reset_deassert(udphy, "init");
+
+	if (udphy->mode & UDPHY_MODE_DP) {
+		regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
+				   CMN_DP_INIT_RSTN,
+				   FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
+	}
+
+	udelay(1);
+
+	/*  Step 5: deassert cmn/lane rstn */
+	if (udphy->mode & UDPHY_MODE_USB) {
+		udphy_reset_deassert(udphy, "cmn");
+		udphy_reset_deassert(udphy, "lane");
+	}
+
+	/*  Step 6: wait for lock done of pll */
+	ret = rk3588_udphy_status_check(udphy);
+	if (ret)
+		goto assert_phy;
+
+	return 0;
+
+assert_phy:
+	udphy_reset_assert(udphy, "init");
+	udphy_reset_assert(udphy, "cmn");
+	udphy_reset_assert(udphy, "lane");
+
+assert_apb:
+	udphy_reset_assert(udphy, "pma_apb");
+	udphy_reset_assert(udphy, "pcs_apb");
+
+	return ret;
+}
+
+static const char * const rk3588_udphy_rst_l[] = {
+	"init", "cmn", "lane", "pcs_apb", "pma_apb"
+};
+
+static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
+	.num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
+	.rst_list = rk3588_udphy_rst_l,
+	.grfcfg	= {
+		/* u2phy-grf */
+		.bvalid_phy_con		= { 0x0008, 1, 0, 0x2, 0x3 },
+		.bvalid_grf_con		= { 0x0010, 3, 2, 0x2, 0x3 },
+
+		/* usb-grf */
+		.usb3otg0_cfg		= { 0x001c, 15, 0, 0x1100, 0x0188 },
+		.usb3otg1_cfg		= { 0x0034, 15, 0, 0x1100, 0x0188 },
+
+		/* usbdpphy-grf */
+		.low_pwrn		= { 0x0004, 13, 13, 0, 1 },
+		.rx_lfps		= { 0x0004, 14, 14, 0, 1 },
+	},
+	.combophy_init = rk3588_udphy_init,
+};
+
+static const struct udevice_id rockchip_udphy_dt_match[] = {
+	{
+		.compatible = "rockchip,rk3588-usbdp-phy",
+		.data = (ulong)&rk3588_udphy_cfgs
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(rockchip_udphy_u3_port) = {
+	.name		= "rockchip_udphy_u3_port",
+	.id		= UCLASS_PHY,
+	.ops		= &rockchip_u3phy_ops,
+};
+
+U_BOOT_DRIVER(rockchip_udphy) = {
+	.name		= "rockchip_udphy",
+	.id		= UCLASS_PHY,
+	.of_match	= rockchip_udphy_dt_match,
+	.probe		= rockchip_udphy_probe,
+	.bind		= rockchip_udphy_bind,
+	.priv_auto	= sizeof(struct rockchip_udphy),
+};
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 23397175d3..34314d0bd1 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -256,6 +256,7 @@ enum wiz_type {
 	J721E_WIZ_10G,
 	AM64_WIZ_10G,
 	J784S4_WIZ_10G,
+	J721S2_WIZ_10G,
 };
 
 struct wiz_data {
@@ -307,6 +308,15 @@ static struct wiz_data j784s4_wiz_10g = {
 	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
 };
 
+static struct wiz_data j721s2_10g_data = {
+	.type = J721S2_WIZ_10G,
+	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
+	.refclk_dig_sel = &refclk_dig_sel_10g,
+	.clk_mux_sel = clk_mux_sel_10g,
+	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN	100	/* ms */
 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX	1000
 
@@ -1037,8 +1047,14 @@ static int j721e_wiz_bind_of_clocks(struct wiz *wiz)
 	ofnode node;
 	int i, rc;
 
-	if (type == AM64_WIZ_10G || type == J784S4_WIZ_10G)
+	switch (type) {
+	case AM64_WIZ_10G:
+	case J784S4_WIZ_10G:
+	case J721S2_WIZ_10G:
 		return j721e_wiz_bind_clocks(wiz);
+	default:
+		break;
+	};
 
 	div_clk_drv = lists_driver_lookup_name("wiz_div_clk");
 	if (!div_clk_drv) {
@@ -1282,6 +1298,9 @@ static const struct udevice_id j721e_wiz_ids[] = {
 	{
 		.compatible = "ti,j784s4-wiz-10g", .data = (ulong)&j784s4_wiz_10g,
 	},
+	{
+		.compatible = "ti,j721s2-wiz-10g", .data = (ulong)&j721s2_10g_data,
+	},
 	{}
 };
 
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.h b/drivers/pinctrl/exynos/pinctrl-exynos.h
index a7788b76d9..cbc5174b48 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.h
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.h
@@ -6,7 +6,7 @@
  */
 
 #ifndef __PINCTRL_EXYNOS_H_
-#define __PINCTRL_EXYNOS__H_
+#define __PINCTRL_EXYNOS_H_
 
 #define PIN_CON		0x00	/* Offset of pin function register */
 #define PIN_DAT		0x04	/* Offset of pin data register */
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 27e8998e59..34d23cece5 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -24,6 +24,10 @@ config PINCTRL_MT7986
 	bool "MT7986 SoC pinctrl driver"
 	select PINCTRL_MTK
 
+config PINCTRL_MT7988
+	bool "MT7988 SoC pinctrl driver"
+	select PINCTRL_MTK
+
 config PINCTRL_MT8512
 	bool "MT8512 SoC pinctrl driver"
 	select PINCTRL_MTK
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 6e733759f5..de39d1ea43 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
 obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
 obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
 obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
 obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o
 obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
 obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
index bf4e9a28e9..114f2602b2 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
@@ -233,283 +233,285 @@ static const struct mtk_pin_desc mt7622_pins[] = {
  */
 
 /* EMMC */
-static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
-static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+static const int mt7622_emmc_pins[] = {
+	40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
+static const int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
 
-static int mt7622_emmc_rst_pins[] = { 37, };
-static int mt7622_emmc_rst_funcs[] = { 1, };
+static const int mt7622_emmc_rst_pins[] = { 37, };
+static const int mt7622_emmc_rst_funcs[] = { 1, };
 
 /* LED for EPHY */
-static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
-static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
-static int mt7622_ephy0_led_pins[] = { 86, };
-static int mt7622_ephy0_led_funcs[] = { 0, };
-static int mt7622_ephy1_led_pins[] = { 91, };
-static int mt7622_ephy1_led_funcs[] = { 2, };
-static int mt7622_ephy2_led_pins[] = { 92, };
-static int mt7622_ephy2_led_funcs[] = { 2, };
-static int mt7622_ephy3_led_pins[] = { 93, };
-static int mt7622_ephy3_led_funcs[] = { 2, };
-static int mt7622_ephy4_led_pins[] = { 94, };
-static int mt7622_ephy4_led_funcs[] = { 2, };
+static const int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
+static const int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
+static const int mt7622_ephy0_led_pins[] = { 86, };
+static const int mt7622_ephy0_led_funcs[] = { 0, };
+static const int mt7622_ephy1_led_pins[] = { 91, };
+static const int mt7622_ephy1_led_funcs[] = { 2, };
+static const int mt7622_ephy2_led_pins[] = { 92, };
+static const int mt7622_ephy2_led_funcs[] = { 2, };
+static const int mt7622_ephy3_led_pins[] = { 93, };
+static const int mt7622_ephy3_led_funcs[] = { 2, };
+static const int mt7622_ephy4_led_pins[] = { 94, };
+static const int mt7622_ephy4_led_funcs[] = { 2, };
 
 /* Embedded Switch */
-static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
-				 62, 63, 64, 65, 66, 67, 68, 69, 70, };
-static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-				  0, 0, 0, 0, 0, 0, 0, 0, 0, };
-static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
-static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
-static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
-					  68, 69, 70, };
-static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
-					   0, 0, 0, };
+static const int mt7622_esw_pins[] = {
+	51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
+	69, 70, };
+static const int mt7622_esw_funcs[] = {
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static const int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
+static const int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static const int mt7622_esw_p2_p3_p4_pins[] = {
+	59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, };
+static const int mt7622_esw_p2_p3_p4_funcs[] = {
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
 /* RGMII via ESW */
-static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
-					   67, 68, 69, 70, };
-static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-					    0, };
+static const int mt7622_rgmii_via_esw_pins[] = {
+	59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, };
+static const int mt7622_rgmii_via_esw_funcs[] = {
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
 
 /* RGMII via GMAC1 */
-static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
-					     67, 68, 69, 70, };
-static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-					      2, };
+static const int mt7622_rgmii_via_gmac1_pins[] = {
+	59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, };
+static const int mt7622_rgmii_via_gmac1_funcs[] = {
+	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
 
 /* RGMII via GMAC2 */
-static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
-					     33, 34, 35, 36, };
-static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-					      0, };
+static const int mt7622_rgmii_via_gmac2_pins[] = {
+	25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, };
+static const int mt7622_rgmii_via_gmac2_funcs[] = {
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
 
 /* I2C */
-static int mt7622_i2c0_pins[] = { 14, 15, };
-static int mt7622_i2c0_funcs[] = { 0, 0, };
-static int mt7622_i2c1_0_pins[] = { 55, 56, };
-static int mt7622_i2c1_0_funcs[] = { 0, 0, };
-static int mt7622_i2c1_1_pins[] = { 73, 74, };
-static int mt7622_i2c1_1_funcs[] = { 3, 3, };
-static int mt7622_i2c1_2_pins[] = { 87, 88, };
-static int mt7622_i2c1_2_funcs[] = { 0, 0, };
-static int mt7622_i2c2_0_pins[] = { 57, 58, };
-static int mt7622_i2c2_0_funcs[] = { 0, 0, };
-static int mt7622_i2c2_1_pins[] = { 75, 76, };
-static int mt7622_i2c2_1_funcs[] = { 3, 3, };
-static int mt7622_i2c2_2_pins[] = { 89, 90, };
-static int mt7622_i2c2_2_funcs[] = { 0, 0, };
+static const int mt7622_i2c0_pins[] = { 14, 15, };
+static const int mt7622_i2c0_funcs[] = { 0, 0, };
+static const int mt7622_i2c1_0_pins[] = { 55, 56, };
+static const int mt7622_i2c1_0_funcs[] = { 0, 0, };
+static const int mt7622_i2c1_1_pins[] = { 73, 74, };
+static const int mt7622_i2c1_1_funcs[] = { 3, 3, };
+static const int mt7622_i2c1_2_pins[] = { 87, 88, };
+static const int mt7622_i2c1_2_funcs[] = { 0, 0, };
+static const int mt7622_i2c2_0_pins[] = { 57, 58, };
+static const int mt7622_i2c2_0_funcs[] = { 0, 0, };
+static const int mt7622_i2c2_1_pins[] = { 75, 76, };
+static const int mt7622_i2c2_1_funcs[] = { 3, 3, };
+static const int mt7622_i2c2_2_pins[] = { 89, 90, };
+static const int mt7622_i2c2_2_funcs[] = { 0, 0, };
 
 /* I2S */
-static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
-static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
-static int mt7622_i2s1_in_data_pins[] = { 1, };
-static int mt7622_i2s1_in_data_funcs[] = { 0, };
-static int mt7622_i2s2_in_data_pins[] = { 16, };
-static int mt7622_i2s2_in_data_funcs[] = { 0, };
-static int mt7622_i2s3_in_data_pins[] = { 17, };
-static int mt7622_i2s3_in_data_funcs[] = { 0, };
-static int mt7622_i2s4_in_data_pins[] = { 18, };
-static int mt7622_i2s4_in_data_funcs[] = { 0, };
-static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
-static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
-static int mt7622_i2s1_out_data_pins[] = { 2, };
-static int mt7622_i2s1_out_data_funcs[] = { 0, };
-static int mt7622_i2s2_out_data_pins[] = { 19, };
-static int mt7622_i2s2_out_data_funcs[] = { 0, };
-static int mt7622_i2s3_out_data_pins[] = { 20, };
-static int mt7622_i2s3_out_data_funcs[] = { 0, };
-static int mt7622_i2s4_out_data_pins[] = { 21, };
-static int mt7622_i2s4_out_data_funcs[] = { 0, };
+static const int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
+static const int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
+static const int mt7622_i2s1_in_data_pins[] = { 1, };
+static const int mt7622_i2s1_in_data_funcs[] = { 0, };
+static const int mt7622_i2s2_in_data_pins[] = { 16, };
+static const int mt7622_i2s2_in_data_funcs[] = { 0, };
+static const int mt7622_i2s3_in_data_pins[] = { 17, };
+static const int mt7622_i2s3_in_data_funcs[] = { 0, };
+static const int mt7622_i2s4_in_data_pins[] = { 18, };
+static const int mt7622_i2s4_in_data_funcs[] = { 0, };
+static const int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
+static const int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
+static const int mt7622_i2s1_out_data_pins[] = { 2, };
+static const int mt7622_i2s1_out_data_funcs[] = { 0, };
+static const int mt7622_i2s2_out_data_pins[] = { 19, };
+static const int mt7622_i2s2_out_data_funcs[] = { 0, };
+static const int mt7622_i2s3_out_data_pins[] = { 20, };
+static const int mt7622_i2s3_out_data_funcs[] = { 0, };
+static const int mt7622_i2s4_out_data_pins[] = { 21, };
+static const int mt7622_i2s4_out_data_funcs[] = { 0, };
 
 /* IR */
-static int mt7622_ir_0_tx_pins[] = { 16, };
-static int mt7622_ir_0_tx_funcs[] = { 4, };
-static int mt7622_ir_1_tx_pins[] = { 59, };
-static int mt7622_ir_1_tx_funcs[] = { 5, };
-static int mt7622_ir_2_tx_pins[] = { 99, };
-static int mt7622_ir_2_tx_funcs[] = { 3, };
-static int mt7622_ir_0_rx_pins[] = { 17, };
-static int mt7622_ir_0_rx_funcs[] = { 4, };
-static int mt7622_ir_1_rx_pins[] = { 60, };
-static int mt7622_ir_1_rx_funcs[] = { 5, };
-static int mt7622_ir_2_rx_pins[] = { 100, };
-static int mt7622_ir_2_rx_funcs[] = { 3, };
+static const int mt7622_ir_0_tx_pins[] = { 16, };
+static const int mt7622_ir_0_tx_funcs[] = { 4, };
+static const int mt7622_ir_1_tx_pins[] = { 59, };
+static const int mt7622_ir_1_tx_funcs[] = { 5, };
+static const int mt7622_ir_2_tx_pins[] = { 99, };
+static const int mt7622_ir_2_tx_funcs[] = { 3, };
+static const int mt7622_ir_0_rx_pins[] = { 17, };
+static const int mt7622_ir_0_rx_funcs[] = { 4, };
+static const int mt7622_ir_1_rx_pins[] = { 60, };
+static const int mt7622_ir_1_rx_funcs[] = { 5, };
+static const int mt7622_ir_2_rx_pins[] = { 100, };
+static const int mt7622_ir_2_rx_funcs[] = { 3, };
 
 /* MDIO */
-static int mt7622_mdc_mdio_pins[] = { 23, 24, };
-static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
+static const int mt7622_mdc_mdio_pins[] = { 23, 24, };
+static const int mt7622_mdc_mdio_funcs[] = { 0, 0, };
 
 /* PCIE */
-static int mt7622_pcie0_0_waken_pins[] = { 14, };
-static int mt7622_pcie0_0_waken_funcs[] = { 2, };
-static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
-static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
-static int mt7622_pcie0_1_waken_pins[] = { 79, };
-static int mt7622_pcie0_1_waken_funcs[] = { 4, };
-static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
-static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
-static int mt7622_pcie1_0_waken_pins[] = { 14, };
-static int mt7622_pcie1_0_waken_funcs[] = { 3, };
-static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
-static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
-
-static int mt7622_pcie0_pad_perst_pins[] = { 83, };
-static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
-static int mt7622_pcie1_pad_perst_pins[] = { 84, };
-static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
+static const int mt7622_pcie0_0_waken_pins[] = { 14, };
+static const int mt7622_pcie0_0_waken_funcs[] = { 2, };
+static const int mt7622_pcie0_0_clkreq_pins[] = { 15, };
+static const int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
+static const int mt7622_pcie0_1_waken_pins[] = { 79, };
+static const int mt7622_pcie0_1_waken_funcs[] = { 4, };
+static const int mt7622_pcie0_1_clkreq_pins[] = { 80, };
+static const int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
+static const int mt7622_pcie1_0_waken_pins[] = { 14, };
+static const int mt7622_pcie1_0_waken_funcs[] = { 3, };
+static const int mt7622_pcie1_0_clkreq_pins[] = { 15, };
+static const int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
+
+static const int mt7622_pcie0_pad_perst_pins[] = { 83, };
+static const int mt7622_pcie0_pad_perst_funcs[] = { 0, };
+static const int mt7622_pcie1_pad_perst_pins[] = { 84, };
+static const int mt7622_pcie1_pad_perst_funcs[] = { 0, };
 
 /* PMIC bus */
-static int mt7622_pmic_bus_pins[] = { 71, 72, };
-static int mt7622_pmic_bus_funcs[] = { 0, 0, };
+static const int mt7622_pmic_bus_pins[] = { 71, 72, };
+static const int mt7622_pmic_bus_funcs[] = { 0, 0, };
 
 /* Parallel NAND */
-static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
-				   48, 49, 50, };
-static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-				    0, };
+static const int mt7622_pnand_pins[] = {
+	37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, };
+static const int mt7622_pnand_funcs[] = {
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
 
 /* PWM */
-static int mt7622_pwm_ch1_0_pins[] = { 51, };
-static int mt7622_pwm_ch1_0_funcs[] = { 3, };
-static int mt7622_pwm_ch1_1_pins[] = { 73, };
-static int mt7622_pwm_ch1_1_funcs[] = { 4, };
-static int mt7622_pwm_ch1_2_pins[] = { 95, };
-static int mt7622_pwm_ch1_2_funcs[] = { 0, };
-static int mt7622_pwm_ch2_0_pins[] = { 52, };
-static int mt7622_pwm_ch2_0_funcs[] = { 3, };
-static int mt7622_pwm_ch2_1_pins[] = { 74, };
-static int mt7622_pwm_ch2_1_funcs[] = { 4, };
-static int mt7622_pwm_ch2_2_pins[] = { 96, };
-static int mt7622_pwm_ch2_2_funcs[] = { 0, };
-static int mt7622_pwm_ch3_0_pins[] = { 53, };
-static int mt7622_pwm_ch3_0_funcs[] = { 3, };
-static int mt7622_pwm_ch3_1_pins[] = { 75, };
-static int mt7622_pwm_ch3_1_funcs[] = { 4, };
-static int mt7622_pwm_ch3_2_pins[] = { 97, };
-static int mt7622_pwm_ch3_2_funcs[] = { 0, };
-static int mt7622_pwm_ch4_0_pins[] = { 54, };
-static int mt7622_pwm_ch4_0_funcs[] = { 3, };
-static int mt7622_pwm_ch4_1_pins[] = { 67, };
-static int mt7622_pwm_ch4_1_funcs[] = { 3, };
-static int mt7622_pwm_ch4_2_pins[] = { 76, };
-static int mt7622_pwm_ch4_2_funcs[] = { 4, };
-static int mt7622_pwm_ch4_3_pins[] = { 98, };
-static int mt7622_pwm_ch4_3_funcs[] = { 0, };
-static int mt7622_pwm_ch5_0_pins[] = { 68, };
-static int mt7622_pwm_ch5_0_funcs[] = { 3, };
-static int mt7622_pwm_ch5_1_pins[] = { 77, };
-static int mt7622_pwm_ch5_1_funcs[] = { 4, };
-static int mt7622_pwm_ch5_2_pins[] = { 99, };
-static int mt7622_pwm_ch5_2_funcs[] = { 0, };
-static int mt7622_pwm_ch6_0_pins[] = { 69, };
-static int mt7622_pwm_ch6_0_funcs[] = { 3, };
-static int mt7622_pwm_ch6_1_pins[] = { 78, };
-static int mt7622_pwm_ch6_1_funcs[] = { 4, };
-static int mt7622_pwm_ch6_2_pins[] = { 81, };
-static int mt7622_pwm_ch6_2_funcs[] = { 4, };
-static int mt7622_pwm_ch6_3_pins[] = { 100, };
-static int mt7622_pwm_ch6_3_funcs[] = { 0, };
-static int mt7622_pwm_ch7_0_pins[] = { 70, };
-static int mt7622_pwm_ch7_0_funcs[] = { 3, };
-static int mt7622_pwm_ch7_1_pins[] = { 82, };
-static int mt7622_pwm_ch7_1_funcs[] = { 4, };
-static int mt7622_pwm_ch7_2_pins[] = { 101, };
-static int mt7622_pwm_ch7_2_funcs[] = { 0, };
+static const int mt7622_pwm_ch1_0_pins[] = { 51, };
+static const int mt7622_pwm_ch1_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch1_1_pins[] = { 73, };
+static const int mt7622_pwm_ch1_1_funcs[] = { 4, };
+static const int mt7622_pwm_ch1_2_pins[] = { 95, };
+static const int mt7622_pwm_ch1_2_funcs[] = { 0, };
+static const int mt7622_pwm_ch2_0_pins[] = { 52, };
+static const int mt7622_pwm_ch2_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch2_1_pins[] = { 74, };
+static const int mt7622_pwm_ch2_1_funcs[] = { 4, };
+static const int mt7622_pwm_ch2_2_pins[] = { 96, };
+static const int mt7622_pwm_ch2_2_funcs[] = { 0, };
+static const int mt7622_pwm_ch3_0_pins[] = { 53, };
+static const int mt7622_pwm_ch3_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch3_1_pins[] = { 75, };
+static const int mt7622_pwm_ch3_1_funcs[] = { 4, };
+static const int mt7622_pwm_ch3_2_pins[] = { 97, };
+static const int mt7622_pwm_ch3_2_funcs[] = { 0, };
+static const int mt7622_pwm_ch4_0_pins[] = { 54, };
+static const int mt7622_pwm_ch4_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch4_1_pins[] = { 67, };
+static const int mt7622_pwm_ch4_1_funcs[] = { 3, };
+static const int mt7622_pwm_ch4_2_pins[] = { 76, };
+static const int mt7622_pwm_ch4_2_funcs[] = { 4, };
+static const int mt7622_pwm_ch4_3_pins[] = { 98, };
+static const int mt7622_pwm_ch4_3_funcs[] = { 0, };
+static const int mt7622_pwm_ch5_0_pins[] = { 68, };
+static const int mt7622_pwm_ch5_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch5_1_pins[] = { 77, };
+static const int mt7622_pwm_ch5_1_funcs[] = { 4, };
+static const int mt7622_pwm_ch5_2_pins[] = { 99, };
+static const int mt7622_pwm_ch5_2_funcs[] = { 0, };
+static const int mt7622_pwm_ch6_0_pins[] = { 69, };
+static const int mt7622_pwm_ch6_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch6_1_pins[] = { 78, };
+static const int mt7622_pwm_ch6_1_funcs[] = { 4, };
+static const int mt7622_pwm_ch6_2_pins[] = { 81, };
+static const int mt7622_pwm_ch6_2_funcs[] = { 4, };
+static const int mt7622_pwm_ch6_3_pins[] = { 100, };
+static const int mt7622_pwm_ch6_3_funcs[] = { 0, };
+static const int mt7622_pwm_ch7_0_pins[] = { 70, };
+static const int mt7622_pwm_ch7_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch7_1_pins[] = { 82, };
+static const int mt7622_pwm_ch7_1_funcs[] = { 4, };
+static const int mt7622_pwm_ch7_2_pins[] = { 101, };
+static const int mt7622_pwm_ch7_2_funcs[] = { 0, };
 
 /* SD */
-static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
-static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
-static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
-static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
+static const int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
+static const int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
+static const int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
+static const int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
 
 /* Serial NAND */
-static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
-static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
+static const int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
+static const int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
 
 /* SPI NOR */
-static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
-static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
+static const int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
+static const int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
 
 /* SPIC */
-static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
-static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
-static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
-static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
-static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
-static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
-static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
-static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
-static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
-static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
-static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
-static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
+static const int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
+static const int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
+static const int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
+static const int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
+static const int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
+static const int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
+static const int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
+static const int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
+static const int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
+static const int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
+static const int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
+static const int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
 
 /* TDM */
-static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
-static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
-static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-static int mt7622_tdm_0_out_data_pins[] = { 20, };
-static int mt7622_tdm_0_out_data_funcs[] = { 3, };
-static int mt7622_tdm_0_in_data_pins[] = { 21, };
-static int mt7622_tdm_0_in_data_funcs[] = { 3, };
-static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
-static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
-static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-static int mt7622_tdm_1_out_data_pins[] = { 55, };
-static int mt7622_tdm_1_out_data_funcs[] = { 3, };
-static int mt7622_tdm_1_in_data_pins[] = { 56, };
-static int mt7622_tdm_1_in_data_funcs[] = { 3, };
+static const int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
+static const int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static const int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
+static const int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static const int mt7622_tdm_0_out_data_pins[] = { 20, };
+static const int mt7622_tdm_0_out_data_funcs[] = { 3, };
+static const int mt7622_tdm_0_in_data_pins[] = { 21, };
+static const int mt7622_tdm_0_in_data_funcs[] = { 3, };
+static const int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
+static const int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static const int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
+static const int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static const int mt7622_tdm_1_out_data_pins[] = { 55, };
+static const int mt7622_tdm_1_out_data_funcs[] = { 3, };
+static const int mt7622_tdm_1_in_data_pins[] = { 56, };
+static const int mt7622_tdm_1_in_data_funcs[] = { 3, };
 
 /* UART */
-static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
-static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
-static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
-static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
-static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
-static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
-static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
-static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
-static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
-static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
-static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
-static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
-static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
-static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
-static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
-static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
-static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
-static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
-static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
-static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
-static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
-static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
-static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
-static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
-static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
-static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
-static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
-static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
-static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
-static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
-static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
-static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
-static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
-static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
-static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
-static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
-static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
-static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
-static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
-static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
+static const int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
+static const int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
+static const int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
+static const int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
+static const int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
+static const int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
+static const int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
+static const int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
+static const int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
+static const int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
+static const int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
+static const int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
+static const int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
+static const int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
+static const int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
+static const int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
+static const int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
+static const int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
+static const int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
+static const int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
+static const int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
+static const int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
+static const int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
+static const int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
+static const int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
+static const int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
+static const int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
+static const int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
+static const int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
+static const int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
+static const int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
+static const int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
+static const int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
+static const int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
+static const int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
+static const int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
+static const int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
+static const int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
+static const int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
+static const int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
 
 /* Watchdog */
-static int mt7622_watchdog_pins[] = { 78, };
-static int mt7622_watchdog_funcs[] = { 0, };
+static const int mt7622_watchdog_pins[] = { 78, };
+static const int mt7622_watchdog_funcs[] = { 0, };
 
 /* WLAN LED */
-static int mt7622_wled_pins[] = { 85, };
-static int mt7622_wled_funcs[] = { 0, };
+static const int mt7622_wled_pins[] = { 85, };
+static const int mt7622_wled_funcs[] = { 0, };
 
 static const struct mtk_group_desc mt7622_groups[] = {
 	PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
@@ -719,7 +721,7 @@ static const struct mtk_function_desc mt7622_functions[] = {
 	{"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
 };
 
-static struct mtk_pinctrl_soc mt7622_data = {
+static const struct mtk_pinctrl_soc mt7622_data = {
 	.name = "mt7622_pinctrl",
 	.reg_cal = mt7622_reg_cals,
 	.pins = mt7622_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
index 2e3ae34b8b..2703e6f754 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
@@ -692,377 +692,377 @@ static const struct mtk_pin_desc mt7623_pins[] = {
  */
 
 /* AUDIO EXT CLK */
-static int mt7623_aud_ext_clk0_pins[] = { 208, };
-static int mt7623_aud_ext_clk0_funcs[] = { 1, };
-static int mt7623_aud_ext_clk1_pins[] = { 209, };
-static int mt7623_aud_ext_clk1_funcs[] = { 1, };
+static const int mt7623_aud_ext_clk0_pins[] = { 208, };
+static const int mt7623_aud_ext_clk0_funcs[] = { 1, };
+static const int mt7623_aud_ext_clk1_pins[] = { 209, };
+static const int mt7623_aud_ext_clk1_funcs[] = { 1, };
 
 /* DISP PWM */
-static int mt7623_disp_pwm_0_pins[] = { 72, };
-static int mt7623_disp_pwm_0_funcs[] = { 5, };
-static int mt7623_disp_pwm_1_pins[] = { 203, };
-static int mt7623_disp_pwm_1_funcs[] = { 2, };
-static int mt7623_disp_pwm_2_pins[] = { 208, };
-static int mt7623_disp_pwm_2_funcs[] = { 5, };
+static const int mt7623_disp_pwm_0_pins[] = { 72, };
+static const int mt7623_disp_pwm_0_funcs[] = { 5, };
+static const int mt7623_disp_pwm_1_pins[] = { 203, };
+static const int mt7623_disp_pwm_1_funcs[] = { 2, };
+static const int mt7623_disp_pwm_2_pins[] = { 208, };
+static const int mt7623_disp_pwm_2_funcs[] = { 5, };
 
 /* ESW */
-static int mt7623_esw_int_pins[] = { 273, };
-static int mt7623_esw_int_funcs[] = { 1, };
-static int mt7623_esw_rst_pins[] = { 277, };
-static int mt7623_esw_rst_funcs[] = { 1, };
+static const int mt7623_esw_int_pins[] = { 273, };
+static const int mt7623_esw_int_funcs[] = { 1, };
+static const int mt7623_esw_rst_pins[] = { 277, };
+static const int mt7623_esw_rst_funcs[] = { 1, };
 
 /* EPHY */
-static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
-				  269, 270, 271, 272, 274, };
-static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
+					269, 270, 271, 272, 274, };
+static const int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
 
 /* EXT_SDIO */
-static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
-static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
+static const int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
+static const int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
 
 /* HDMI RX */
-static int mt7623_hdmi_rx_pins[] = { 247, 248, };
-static int mt7623_hdmi_rx_funcs[] = { 1, 1 };
-static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
-static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
+static const int mt7623_hdmi_rx_pins[] = { 247, 248, };
+static const int mt7623_hdmi_rx_funcs[] = { 1, 1 };
+static const int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
+static const int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
 
 /* HDMI TX */
-static int mt7623_hdmi_cec_pins[] = { 122, };
-static int mt7623_hdmi_cec_funcs[] = { 1, };
-static int mt7623_hdmi_htplg_pins[] = { 123, };
-static int mt7623_hdmi_htplg_funcs[] = { 1, };
-static int mt7623_hdmi_i2c_pins[] = { 124, 125, };
-static int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
+static const int mt7623_hdmi_cec_pins[] = { 122, };
+static const int mt7623_hdmi_cec_funcs[] = { 1, };
+static const int mt7623_hdmi_htplg_pins[] = { 123, };
+static const int mt7623_hdmi_htplg_funcs[] = { 1, };
+static const int mt7623_hdmi_i2c_pins[] = { 124, 125, };
+static const int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
 
 /* I2C */
-static int mt7623_i2c0_pins[] = { 75, 76, };
-static int mt7623_i2c0_funcs[] = { 1, 1, };
-static int mt7623_i2c1_0_pins[] = { 57, 58, };
-static int mt7623_i2c1_0_funcs[] = { 1, 1, };
-static int mt7623_i2c1_1_pins[] = { 242, 243, };
-static int mt7623_i2c1_1_funcs[] = { 4, 4, };
-static int mt7623_i2c1_2_pins[] = { 85, 86, };
-static int mt7623_i2c1_2_funcs[] = { 3, 3, };
-static int mt7623_i2c1_3_pins[] = { 105, 106, };
-static int mt7623_i2c1_3_funcs[] = { 3, 3, };
-static int mt7623_i2c1_4_pins[] = { 124, 125, };
-static int mt7623_i2c1_4_funcs[] = { 4, 4, };
-static int mt7623_i2c2_0_pins[] = { 77, 78, };
-static int mt7623_i2c2_0_funcs[] = { 1, 1, };
-static int mt7623_i2c2_1_pins[] = { 89, 90, };
-static int mt7623_i2c2_1_funcs[] = { 3, 3, };
-static int mt7623_i2c2_2_pins[] = { 109, 110, };
-static int mt7623_i2c2_2_funcs[] = { 3, 3, };
-static int mt7623_i2c2_3_pins[] = { 122, 123, };
-static int mt7623_i2c2_3_funcs[] = { 4, 4, };
+static const int mt7623_i2c0_pins[] = { 75, 76, };
+static const int mt7623_i2c0_funcs[] = { 1, 1, };
+static const int mt7623_i2c1_0_pins[] = { 57, 58, };
+static const int mt7623_i2c1_0_funcs[] = { 1, 1, };
+static const int mt7623_i2c1_1_pins[] = { 242, 243, };
+static const int mt7623_i2c1_1_funcs[] = { 4, 4, };
+static const int mt7623_i2c1_2_pins[] = { 85, 86, };
+static const int mt7623_i2c1_2_funcs[] = { 3, 3, };
+static const int mt7623_i2c1_3_pins[] = { 105, 106, };
+static const int mt7623_i2c1_3_funcs[] = { 3, 3, };
+static const int mt7623_i2c1_4_pins[] = { 124, 125, };
+static const int mt7623_i2c1_4_funcs[] = { 4, 4, };
+static const int mt7623_i2c2_0_pins[] = { 77, 78, };
+static const int mt7623_i2c2_0_funcs[] = { 1, 1, };
+static const int mt7623_i2c2_1_pins[] = { 89, 90, };
+static const int mt7623_i2c2_1_funcs[] = { 3, 3, };
+static const int mt7623_i2c2_2_pins[] = { 109, 110, };
+static const int mt7623_i2c2_2_funcs[] = { 3, 3, };
+static const int mt7623_i2c2_3_pins[] = { 122, 123, };
+static const int mt7623_i2c2_3_funcs[] = { 4, 4, };
 
 /* I2S */
-static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
-static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
-static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
-static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
-static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
-static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
-static int mt7623_i2s2_data_in_pins[] = { 51, };
-static int mt7623_i2s2_data_in_funcs[] = { 1, };
-static int mt7623_i2s2_data_0_pins[] = { 203, };
-static int mt7623_i2s2_data_0_funcs[] = { 9, };
-static int mt7623_i2s2_data_1_pins[] = { 38,  };
-static int mt7623_i2s2_data_1_funcs[] = { 4, };
-static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
-static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
-static int mt7623_i2s3_data_in_pins[] = { 190, };
-static int mt7623_i2s3_data_in_funcs[] = { 1, };
-static int mt7623_i2s3_data_0_pins[] = { 204, };
-static int mt7623_i2s3_data_0_funcs[] = { 9, };
-static int mt7623_i2s3_data_1_pins[] = { 2, };
-static int mt7623_i2s3_data_1_funcs[] = { 0, };
-static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
-static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
-static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
-static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
+static const int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
+static const int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
+static const int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
+static const int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
+static const int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
+static const int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
+static const int mt7623_i2s2_data_in_pins[] = { 51, };
+static const int mt7623_i2s2_data_in_funcs[] = { 1, };
+static const int mt7623_i2s2_data_0_pins[] = { 203, };
+static const int mt7623_i2s2_data_0_funcs[] = { 9, };
+static const int mt7623_i2s2_data_1_pins[] = { 38,  };
+static const int mt7623_i2s2_data_1_funcs[] = { 4, };
+static const int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
+static const int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
+static const int mt7623_i2s3_data_in_pins[] = { 190, };
+static const int mt7623_i2s3_data_in_funcs[] = { 1, };
+static const int mt7623_i2s3_data_0_pins[] = { 204, };
+static const int mt7623_i2s3_data_0_funcs[] = { 9, };
+static const int mt7623_i2s3_data_1_pins[] = { 2, };
+static const int mt7623_i2s3_data_1_funcs[] = { 0, };
+static const int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
+static const int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
+static const int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
+static const int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
 
 /* IR */
-static int mt7623_ir_pins[] = { 46, };
-static int mt7623_ir_funcs[] = { 1, };
+static const int mt7623_ir_pins[] = { 46, };
+static const int mt7623_ir_funcs[] = { 1, };
 
 /* LCD */
-static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
-				     99, 100, };
-static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-static int mt7623_dsi_te_pins[] = { 84, };
-static int mt7623_dsi_te_funcs[] = { 1, };
-static int mt7623_lcm_rst_pins[] = { 83, };
-static int mt7623_lcm_rst_funcs[] = { 1, };
+static const int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
+					   99, 100, };
+static const int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7623_dsi_te_pins[] = { 84, };
+static const int mt7623_dsi_te_funcs[] = { 1, };
+static const int mt7623_lcm_rst_pins[] = { 83, };
+static const int mt7623_lcm_rst_funcs[] = { 1, };
 
 /* MDC/MDIO */
-static int mt7623_mdc_mdio_pins[] = { 275, 276, };
-static int mt7623_mdc_mdio_funcs[] = { 1, 1, };
+static const int mt7623_mdc_mdio_pins[] = { 275, 276, };
+static const int mt7623_mdc_mdio_funcs[] = { 1, 1, };
 
 /* MSDC */
-static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
-				   119, 120, 121, };
-static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
-static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
-static int mt7623_msdc1_ins_pins[] = { 261, };
-static int mt7623_msdc1_ins_funcs[] = { 1, };
-static int mt7623_msdc1_wp_0_pins[] = { 29, };
-static int mt7623_msdc1_wp_0_funcs[] = { 1, };
-static int mt7623_msdc1_wp_1_pins[] = { 55, };
-static int mt7623_msdc1_wp_1_funcs[] = { 3, };
-static int mt7623_msdc1_wp_2_pins[] = { 209, };
-static int mt7623_msdc1_wp_2_funcs[] = { 2, };
-static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
-static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
-static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
-				   257, 258, 259, 260, };
-static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
+					 119, 120, 121, };
+static const int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
+static const int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
+static const int mt7623_msdc1_ins_pins[] = { 261, };
+static const int mt7623_msdc1_ins_funcs[] = { 1, };
+static const int mt7623_msdc1_wp_0_pins[] = { 29, };
+static const int mt7623_msdc1_wp_0_funcs[] = { 1, };
+static const int mt7623_msdc1_wp_1_pins[] = { 55, };
+static const int mt7623_msdc1_wp_1_funcs[] = { 3, };
+static const int mt7623_msdc1_wp_2_pins[] = { 209, };
+static const int mt7623_msdc1_wp_2_funcs[] = { 2, };
+static const int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
+static const int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
+static const int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
+					 257, 258, 259, 260, };
+static const int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
 
 /* NAND */
-static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
-				   116, 117, 118, 119, 120, 121, };
-static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
-				   4, 4, };
-static int mt7623_nandc_ceb0_pins[] = { 45, };
-static int mt7623_nandc_ceb0_funcs[] = { 1, };
-static int mt7623_nandc_ceb1_pins[] = { 44, };
-static int mt7623_nandc_ceb1_funcs[] = { 1, };
+static const int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
+					 116, 117, 118, 119, 120, 121, };
+static const int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+					  4, 4, };
+static const int mt7623_nandc_ceb0_pins[] = { 45, };
+static const int mt7623_nandc_ceb0_funcs[] = { 1, };
+static const int mt7623_nandc_ceb1_pins[] = { 44, };
+static const int mt7623_nandc_ceb1_funcs[] = { 1, };
 
 /* RTC */
-static int mt7623_rtc_pins[] = { 10, };
-static int mt7623_rtc_funcs[] = { 1, };
+static const int mt7623_rtc_pins[] = { 10, };
+static const int mt7623_rtc_funcs[] = { 1, };
 
 /* OTG */
-static int mt7623_otg_iddig0_0_pins[] = { 29, };
-static int mt7623_otg_iddig0_0_funcs[] = { 1, };
-static int mt7623_otg_iddig0_1_pins[] = { 44, };
-static int mt7623_otg_iddig0_1_funcs[] = { 2, };
-static int mt7623_otg_iddig0_2_pins[] = { 236, };
-static int mt7623_otg_iddig0_2_funcs[] = { 2, };
-static int mt7623_otg_iddig1_0_pins[] = { 27, };
-static int mt7623_otg_iddig1_0_funcs[] = { 2, };
-static int mt7623_otg_iddig1_1_pins[] = { 47, };
-static int mt7623_otg_iddig1_1_funcs[] = { 2, };
-static int mt7623_otg_iddig1_2_pins[] = { 238, };
-static int mt7623_otg_iddig1_2_funcs[] = { 2, };
-static int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
-static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
-static int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
-static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
-static int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
-static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
-static int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
-static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
-static int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
-static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
-static int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
-static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
+static const int mt7623_otg_iddig0_0_pins[] = { 29, };
+static const int mt7623_otg_iddig0_0_funcs[] = { 1, };
+static const int mt7623_otg_iddig0_1_pins[] = { 44, };
+static const int mt7623_otg_iddig0_1_funcs[] = { 2, };
+static const int mt7623_otg_iddig0_2_pins[] = { 236, };
+static const int mt7623_otg_iddig0_2_funcs[] = { 2, };
+static const int mt7623_otg_iddig1_0_pins[] = { 27, };
+static const int mt7623_otg_iddig1_0_funcs[] = { 2, };
+static const int mt7623_otg_iddig1_1_pins[] = { 47, };
+static const int mt7623_otg_iddig1_1_funcs[] = { 2, };
+static const int mt7623_otg_iddig1_2_pins[] = { 238, };
+static const int mt7623_otg_iddig1_2_funcs[] = { 2, };
+static const int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
+static const int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
+static const int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
+static const int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
+static const int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
+static const int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
+static const int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
+static const int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
+static const int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
+static const int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
+static const int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
+static const int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
 
 /* PCIE */
-static int mt7623_pcie0_0_perst_pins[] = { 208, };
-static int mt7623_pcie0_0_perst_funcs[] = { 3, };
-static int mt7623_pcie0_1_perst_pins[] = { 22, };
-static int mt7623_pcie0_1_perst_funcs[] = { 2, };
-static int mt7623_pcie1_0_perst_pins[] = { 209, };
-static int mt7623_pcie1_0_perst_funcs[] = { 3, };
-static int mt7623_pcie1_1_perst_pins[] = { 23, };
-static int mt7623_pcie1_1_perst_funcs[] = { 2, };
-static int mt7623_pcie2_0_perst_pins[] = { 24, };
-static int mt7623_pcie2_0_perst_funcs[] = { 2, };
-static int mt7623_pcie2_1_perst_pins[] = { 29, };
-static int mt7623_pcie2_1_perst_funcs[] = { 6, };
-static int mt7623_pcie0_0_wake_pins[] = { 28, };
-static int mt7623_pcie0_0_wake_funcs[] = { 6, };
-static int mt7623_pcie0_1_wake_pins[] = { 251, };
-static int mt7623_pcie0_1_wake_funcs[] = { 6, };
-static int mt7623_pcie1_0_wake_pins[] = { 27, };
-static int mt7623_pcie1_0_wake_funcs[] = { 6, };
-static int mt7623_pcie1_1_wake_pins[] = { 253, };
-static int mt7623_pcie1_1_wake_funcs[] = { 6, };
-static int mt7623_pcie2_0_wake_pins[] = { 26, };
-static int mt7623_pcie2_0_wake_funcs[] = { 6, };
-static int mt7623_pcie2_1_wake_pins[] = { 255, };
-static int mt7623_pcie2_1_wake_funcs[] = { 6, };
-static int mt7623_pcie0_clkreq_pins[] = { 250, };
-static int mt7623_pcie0_clkreq_funcs[] = { 6, };
-static int mt7623_pcie1_clkreq_pins[] = { 252, };
-static int mt7623_pcie1_clkreq_funcs[] = { 6, };
-static int mt7623_pcie2_clkreq_pins[] = { 254, };
-static int mt7623_pcie2_clkreq_funcs[] = { 6, };
+static const int mt7623_pcie0_0_perst_pins[] = { 208, };
+static const int mt7623_pcie0_0_perst_funcs[] = { 3, };
+static const int mt7623_pcie0_1_perst_pins[] = { 22, };
+static const int mt7623_pcie0_1_perst_funcs[] = { 2, };
+static const int mt7623_pcie1_0_perst_pins[] = { 209, };
+static const int mt7623_pcie1_0_perst_funcs[] = { 3, };
+static const int mt7623_pcie1_1_perst_pins[] = { 23, };
+static const int mt7623_pcie1_1_perst_funcs[] = { 2, };
+static const int mt7623_pcie2_0_perst_pins[] = { 24, };
+static const int mt7623_pcie2_0_perst_funcs[] = { 2, };
+static const int mt7623_pcie2_1_perst_pins[] = { 29, };
+static const int mt7623_pcie2_1_perst_funcs[] = { 6, };
+static const int mt7623_pcie0_0_wake_pins[] = { 28, };
+static const int mt7623_pcie0_0_wake_funcs[] = { 6, };
+static const int mt7623_pcie0_1_wake_pins[] = { 251, };
+static const int mt7623_pcie0_1_wake_funcs[] = { 6, };
+static const int mt7623_pcie1_0_wake_pins[] = { 27, };
+static const int mt7623_pcie1_0_wake_funcs[] = { 6, };
+static const int mt7623_pcie1_1_wake_pins[] = { 253, };
+static const int mt7623_pcie1_1_wake_funcs[] = { 6, };
+static const int mt7623_pcie2_0_wake_pins[] = { 26, };
+static const int mt7623_pcie2_0_wake_funcs[] = { 6, };
+static const int mt7623_pcie2_1_wake_pins[] = { 255, };
+static const int mt7623_pcie2_1_wake_funcs[] = { 6, };
+static const int mt7623_pcie0_clkreq_pins[] = { 250, };
+static const int mt7623_pcie0_clkreq_funcs[] = { 6, };
+static const int mt7623_pcie1_clkreq_pins[] = { 252, };
+static const int mt7623_pcie1_clkreq_funcs[] = { 6, };
+static const int mt7623_pcie2_clkreq_pins[] = { 254, };
+static const int mt7623_pcie2_clkreq_funcs[] = { 6, };
 /* the pcie_*_rev are only used for MT7623 */
-static int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
-static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
-static int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
-static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
-static int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
-static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
-static int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
-static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
-static int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
-static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
-static int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
-static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
+static const int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
+static const int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
+static const int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
+static const int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
+static const int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
+static const int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
+static const int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
+static const int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
+static const int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
+static const int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
+static const int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
+static const int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
 
 /* PCM */
-static int mt7623_pcm_clk_0_pins[] = { 18, };
-static int mt7623_pcm_clk_0_funcs[] = { 1, };
-static int mt7623_pcm_clk_1_pins[] = { 17, };
-static int mt7623_pcm_clk_1_funcs[] = { 3, };
-static int mt7623_pcm_clk_2_pins[] = { 35, };
-static int mt7623_pcm_clk_2_funcs[] = { 3, };
-static int mt7623_pcm_clk_3_pins[] = { 50, };
-static int mt7623_pcm_clk_3_funcs[] = { 3, };
-static int mt7623_pcm_clk_4_pins[] = { 74, };
-static int mt7623_pcm_clk_4_funcs[] = { 3, };
-static int mt7623_pcm_clk_5_pins[] = { 191, };
-static int mt7623_pcm_clk_5_funcs[] = { 3, };
-static int mt7623_pcm_clk_6_pins[] = { 196, };
-static int mt7623_pcm_clk_6_funcs[] = { 3, };
-static int mt7623_pcm_sync_0_pins[] = { 19, };
-static int mt7623_pcm_sync_0_funcs[] = { 1, };
-static int mt7623_pcm_sync_1_pins[] = { 30, };
-static int mt7623_pcm_sync_1_funcs[] = { 3, };
-static int mt7623_pcm_sync_2_pins[] = { 36, };
-static int mt7623_pcm_sync_2_funcs[] = { 3, };
-static int mt7623_pcm_sync_3_pins[] = { 52, };
-static int mt7623_pcm_sync_3_funcs[] = { 31, };
-static int mt7623_pcm_sync_4_pins[] = { 73, };
-static int mt7623_pcm_sync_4_funcs[] = { 3, };
-static int mt7623_pcm_sync_5_pins[] = { 192, };
-static int mt7623_pcm_sync_5_funcs[] = { 3, };
-static int mt7623_pcm_sync_6_pins[] = { 197, };
-static int mt7623_pcm_sync_6_funcs[] = { 3, };
-static int mt7623_pcm_rx_0_pins[] = { 20, };
-static int mt7623_pcm_rx_0_funcs[] = { 1, };
-static int mt7623_pcm_rx_1_pins[] = { 16, };
-static int mt7623_pcm_rx_1_funcs[] = { 3, };
-static int mt7623_pcm_rx_2_pins[] = { 34, };
-static int mt7623_pcm_rx_2_funcs[] = { 3, };
-static int mt7623_pcm_rx_3_pins[] = { 51, };
-static int mt7623_pcm_rx_3_funcs[] = { 3, };
-static int mt7623_pcm_rx_4_pins[] = { 72, };
-static int mt7623_pcm_rx_4_funcs[] = { 3, };
-static int mt7623_pcm_rx_5_pins[] = { 190, };
-static int mt7623_pcm_rx_5_funcs[] = { 3, };
-static int mt7623_pcm_rx_6_pins[] = { 195, };
-static int mt7623_pcm_rx_6_funcs[] = { 3, };
-static int mt7623_pcm_tx_0_pins[] = { 21, };
-static int mt7623_pcm_tx_0_funcs[] = { 1, };
-static int mt7623_pcm_tx_1_pins[] = { 32, };
-static int mt7623_pcm_tx_1_funcs[] = { 3, };
-static int mt7623_pcm_tx_2_pins[] = { 33, };
-static int mt7623_pcm_tx_2_funcs[] = { 3, };
-static int mt7623_pcm_tx_3_pins[] = { 38, };
-static int mt7623_pcm_tx_3_funcs[] = { 3, };
-static int mt7623_pcm_tx_4_pins[] = { 49, };
-static int mt7623_pcm_tx_4_funcs[] = { 3, };
-static int mt7623_pcm_tx_5_pins[] = { 189, };
-static int mt7623_pcm_tx_5_funcs[] = { 3, };
-static int mt7623_pcm_tx_6_pins[] = { 194, };
-static int mt7623_pcm_tx_6_funcs[] = { 3, };
+static const int mt7623_pcm_clk_0_pins[] = { 18, };
+static const int mt7623_pcm_clk_0_funcs[] = { 1, };
+static const int mt7623_pcm_clk_1_pins[] = { 17, };
+static const int mt7623_pcm_clk_1_funcs[] = { 3, };
+static const int mt7623_pcm_clk_2_pins[] = { 35, };
+static const int mt7623_pcm_clk_2_funcs[] = { 3, };
+static const int mt7623_pcm_clk_3_pins[] = { 50, };
+static const int mt7623_pcm_clk_3_funcs[] = { 3, };
+static const int mt7623_pcm_clk_4_pins[] = { 74, };
+static const int mt7623_pcm_clk_4_funcs[] = { 3, };
+static const int mt7623_pcm_clk_5_pins[] = { 191, };
+static const int mt7623_pcm_clk_5_funcs[] = { 3, };
+static const int mt7623_pcm_clk_6_pins[] = { 196, };
+static const int mt7623_pcm_clk_6_funcs[] = { 3, };
+static const int mt7623_pcm_sync_0_pins[] = { 19, };
+static const int mt7623_pcm_sync_0_funcs[] = { 1, };
+static const int mt7623_pcm_sync_1_pins[] = { 30, };
+static const int mt7623_pcm_sync_1_funcs[] = { 3, };
+static const int mt7623_pcm_sync_2_pins[] = { 36, };
+static const int mt7623_pcm_sync_2_funcs[] = { 3, };
+static const int mt7623_pcm_sync_3_pins[] = { 52, };
+static const int mt7623_pcm_sync_3_funcs[] = { 31, };
+static const int mt7623_pcm_sync_4_pins[] = { 73, };
+static const int mt7623_pcm_sync_4_funcs[] = { 3, };
+static const int mt7623_pcm_sync_5_pins[] = { 192, };
+static const int mt7623_pcm_sync_5_funcs[] = { 3, };
+static const int mt7623_pcm_sync_6_pins[] = { 197, };
+static const int mt7623_pcm_sync_6_funcs[] = { 3, };
+static const int mt7623_pcm_rx_0_pins[] = { 20, };
+static const int mt7623_pcm_rx_0_funcs[] = { 1, };
+static const int mt7623_pcm_rx_1_pins[] = { 16, };
+static const int mt7623_pcm_rx_1_funcs[] = { 3, };
+static const int mt7623_pcm_rx_2_pins[] = { 34, };
+static const int mt7623_pcm_rx_2_funcs[] = { 3, };
+static const int mt7623_pcm_rx_3_pins[] = { 51, };
+static const int mt7623_pcm_rx_3_funcs[] = { 3, };
+static const int mt7623_pcm_rx_4_pins[] = { 72, };
+static const int mt7623_pcm_rx_4_funcs[] = { 3, };
+static const int mt7623_pcm_rx_5_pins[] = { 190, };
+static const int mt7623_pcm_rx_5_funcs[] = { 3, };
+static const int mt7623_pcm_rx_6_pins[] = { 195, };
+static const int mt7623_pcm_rx_6_funcs[] = { 3, };
+static const int mt7623_pcm_tx_0_pins[] = { 21, };
+static const int mt7623_pcm_tx_0_funcs[] = { 1, };
+static const int mt7623_pcm_tx_1_pins[] = { 32, };
+static const int mt7623_pcm_tx_1_funcs[] = { 3, };
+static const int mt7623_pcm_tx_2_pins[] = { 33, };
+static const int mt7623_pcm_tx_2_funcs[] = { 3, };
+static const int mt7623_pcm_tx_3_pins[] = { 38, };
+static const int mt7623_pcm_tx_3_funcs[] = { 3, };
+static const int mt7623_pcm_tx_4_pins[] = { 49, };
+static const int mt7623_pcm_tx_4_funcs[] = { 3, };
+static const int mt7623_pcm_tx_5_pins[] = { 189, };
+static const int mt7623_pcm_tx_5_funcs[] = { 3, };
+static const int mt7623_pcm_tx_6_pins[] = { 194, };
+static const int mt7623_pcm_tx_6_funcs[] = { 3, };
 
 /* PWM */
-static int mt7623_pwm_ch1_0_pins[] = { 203, };
-static int mt7623_pwm_ch1_0_funcs[] = { 1, };
-static int mt7623_pwm_ch1_1_pins[] = { 208, };
-static int mt7623_pwm_ch1_1_funcs[] = { 2, };
-static int mt7623_pwm_ch1_2_pins[] = { 72, };
-static int mt7623_pwm_ch1_2_funcs[] = { 4, };
-static int mt7623_pwm_ch1_3_pins[] = { 88, };
-static int mt7623_pwm_ch1_3_funcs[] = { 3, };
-static int mt7623_pwm_ch1_4_pins[] = { 108, };
-static int mt7623_pwm_ch1_4_funcs[] = { 3, };
-static int mt7623_pwm_ch2_0_pins[] = { 204, };
-static int mt7623_pwm_ch2_0_funcs[] = { 1, };
-static int mt7623_pwm_ch2_1_pins[] = { 53, };
-static int mt7623_pwm_ch2_1_funcs[] = { 5, };
-static int mt7623_pwm_ch2_2_pins[] = { 88, };
-static int mt7623_pwm_ch2_2_funcs[] = { 6, };
-static int mt7623_pwm_ch2_3_pins[] = { 108, };
-static int mt7623_pwm_ch2_3_funcs[] = { 6, };
-static int mt7623_pwm_ch2_4_pins[] = { 209, };
-static int mt7623_pwm_ch2_4_funcs[] = { 5, };
-static int mt7623_pwm_ch3_0_pins[] = { 205, };
-static int mt7623_pwm_ch3_0_funcs[] = { 1, };
-static int mt7623_pwm_ch3_1_pins[] = { 55, };
-static int mt7623_pwm_ch3_1_funcs[] = { 5, };
-static int mt7623_pwm_ch3_2_pins[] = { 89, };
-static int mt7623_pwm_ch3_2_funcs[] = { 6, };
-static int mt7623_pwm_ch3_3_pins[] = { 109, };
-static int mt7623_pwm_ch3_3_funcs[] = { 6, };
-static int mt7623_pwm_ch4_0_pins[] = { 206, };
-static int mt7623_pwm_ch4_0_funcs[] = { 1, };
-static int mt7623_pwm_ch4_1_pins[] = { 90, };
-static int mt7623_pwm_ch4_1_funcs[] = { 6, };
-static int mt7623_pwm_ch4_2_pins[] = { 110, };
-static int mt7623_pwm_ch4_2_funcs[] = { 6, };
-static int mt7623_pwm_ch4_3_pins[] = { 124, };
-static int mt7623_pwm_ch4_3_funcs[] = { 5, };
-static int mt7623_pwm_ch5_0_pins[] = { 207, };
-static int mt7623_pwm_ch5_0_funcs[] = { 1, };
-static int mt7623_pwm_ch5_1_pins[] = { 125, };
-static int mt7623_pwm_ch5_1_funcs[] = { 5, };
+static const int mt7623_pwm_ch1_0_pins[] = { 203, };
+static const int mt7623_pwm_ch1_0_funcs[] = { 1, };
+static const int mt7623_pwm_ch1_1_pins[] = { 208, };
+static const int mt7623_pwm_ch1_1_funcs[] = { 2, };
+static const int mt7623_pwm_ch1_2_pins[] = { 72, };
+static const int mt7623_pwm_ch1_2_funcs[] = { 4, };
+static const int mt7623_pwm_ch1_3_pins[] = { 88, };
+static const int mt7623_pwm_ch1_3_funcs[] = { 3, };
+static const int mt7623_pwm_ch1_4_pins[] = { 108, };
+static const int mt7623_pwm_ch1_4_funcs[] = { 3, };
+static const int mt7623_pwm_ch2_0_pins[] = { 204, };
+static const int mt7623_pwm_ch2_0_funcs[] = { 1, };
+static const int mt7623_pwm_ch2_1_pins[] = { 53, };
+static const int mt7623_pwm_ch2_1_funcs[] = { 5, };
+static const int mt7623_pwm_ch2_2_pins[] = { 88, };
+static const int mt7623_pwm_ch2_2_funcs[] = { 6, };
+static const int mt7623_pwm_ch2_3_pins[] = { 108, };
+static const int mt7623_pwm_ch2_3_funcs[] = { 6, };
+static const int mt7623_pwm_ch2_4_pins[] = { 209, };
+static const int mt7623_pwm_ch2_4_funcs[] = { 5, };
+static const int mt7623_pwm_ch3_0_pins[] = { 205, };
+static const int mt7623_pwm_ch3_0_funcs[] = { 1, };
+static const int mt7623_pwm_ch3_1_pins[] = { 55, };
+static const int mt7623_pwm_ch3_1_funcs[] = { 5, };
+static const int mt7623_pwm_ch3_2_pins[] = { 89, };
+static const int mt7623_pwm_ch3_2_funcs[] = { 6, };
+static const int mt7623_pwm_ch3_3_pins[] = { 109, };
+static const int mt7623_pwm_ch3_3_funcs[] = { 6, };
+static const int mt7623_pwm_ch4_0_pins[] = { 206, };
+static const int mt7623_pwm_ch4_0_funcs[] = { 1, };
+static const int mt7623_pwm_ch4_1_pins[] = { 90, };
+static const int mt7623_pwm_ch4_1_funcs[] = { 6, };
+static const int mt7623_pwm_ch4_2_pins[] = { 110, };
+static const int mt7623_pwm_ch4_2_funcs[] = { 6, };
+static const int mt7623_pwm_ch4_3_pins[] = { 124, };
+static const int mt7623_pwm_ch4_3_funcs[] = { 5, };
+static const int mt7623_pwm_ch5_0_pins[] = { 207, };
+static const int mt7623_pwm_ch5_0_funcs[] = { 1, };
+static const int mt7623_pwm_ch5_1_pins[] = { 125, };
+static const int mt7623_pwm_ch5_1_funcs[] = { 5, };
 
 /* PWRAP */
-static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
-static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
+static const int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
 
 /* SPDIF */
-static int mt7623_spdif_in0_0_pins[] = { 56, };
-static int mt7623_spdif_in0_0_funcs[] = { 3, };
-static int mt7623_spdif_in0_1_pins[] = { 201, };
-static int mt7623_spdif_in0_1_funcs[] = { 1, };
-static int mt7623_spdif_in1_0_pins[] = { 54, };
-static int mt7623_spdif_in1_0_funcs[] = { 3, };
-static int mt7623_spdif_in1_1_pins[] = { 202, };
-static int mt7623_spdif_in1_1_funcs[] = { 1, };
-static int mt7623_spdif_out_pins[] = { 202, };
-static int mt7623_spdif_out_funcs[] = { 1, };
+static const int mt7623_spdif_in0_0_pins[] = { 56, };
+static const int mt7623_spdif_in0_0_funcs[] = { 3, };
+static const int mt7623_spdif_in0_1_pins[] = { 201, };
+static const int mt7623_spdif_in0_1_funcs[] = { 1, };
+static const int mt7623_spdif_in1_0_pins[] = { 54, };
+static const int mt7623_spdif_in1_0_funcs[] = { 3, };
+static const int mt7623_spdif_in1_1_pins[] = { 202, };
+static const int mt7623_spdif_in1_1_funcs[] = { 1, };
+static const int mt7623_spdif_out_pins[] = { 202, };
+static const int mt7623_spdif_out_funcs[] = { 1, };
 
 /* SPI */
-static int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
-static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
-static int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
-static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
-static int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
-static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
+static const int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
+static const int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
+static const int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
+static const int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
+static const int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
+static const int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
 
 /* UART */
-static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
-static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
-static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
-static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
-static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
-static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
-static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
-static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
-static int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
-static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
-static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
-static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
-static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
-static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
-static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
-static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
-static int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
-static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
-static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
-static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
-static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
-static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
-static int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
-static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
-static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
-static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
-static int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
-static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
+static const int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
+static const int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
+static const int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
+static const int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
+static const int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
+static const int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
+static const int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
+static const int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
+static const int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
+static const int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
+static const int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
+static const int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
+static const int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
+static const int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
+static const int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
+static const int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
+static const int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
+static const int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
+static const int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
+static const int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
+static const int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
+static const int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
+static const int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
+static const int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
+static const int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
+static const int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
+static const int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
+static const int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
 
 /* Watchdog */
-static int mt7623_watchdog_0_pins[] = { 11, };
-static int mt7623_watchdog_0_funcs[] = { 1, };
-static int mt7623_watchdog_1_pins[] = { 121, };
-static int mt7623_watchdog_1_funcs[] = { 5, };
+static const int mt7623_watchdog_0_pins[] = { 11, };
+static const int mt7623_watchdog_0_funcs[] = { 1, };
+static const int mt7623_watchdog_1_pins[] = { 121, };
+static const int mt7623_watchdog_1_funcs[] = { 5, };
 
 static const struct mtk_group_desc mt7623_groups[] = {
 	PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0),
@@ -1362,7 +1362,7 @@ static const struct mtk_function_desc mt7623_functions[] = {
 	{"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)},
 };
 
-static struct mtk_pinctrl_soc mt7623_data = {
+static const struct mtk_pinctrl_soc mt7623_data = {
 	.name = "mt7623_pinctrl",
 	.reg_cal = mt7623_reg_cals,
 	.pins = mt7623_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
index 5d4bec2234..45d4def316 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
@@ -180,118 +180,118 @@ static const struct mtk_pin_desc mt7629_pins[] = {
  */
 
 /* WF 5G */
-static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
-static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
+static const int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
 
 /* LED for EPHY */
-static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
-static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
-static int mt7629_ephy_led0_pins[] = { 12, };
-static int mt7629_ephy_led0_funcs[] = { 1, };
-static int mt7629_ephy_led1_pins[] = { 13, };
-static int mt7629_ephy_led1_funcs[] = { 1, };
-static int mt7629_ephy_led2_pins[] = { 14, };
-static int mt7629_ephy_led2_funcs[] = { 1, };
-static int mt7629_ephy_led3_pins[] = { 15, };
-static int mt7629_ephy_led3_funcs[] = { 1, };
-static int mt7629_ephy_led4_pins[] = { 16, };
-static int mt7629_ephy_led4_funcs[] = { 1, };
-static int mt7629_wf2g_led_pins[] = { 17, };
-static int mt7629_wf2g_led_funcs[] = { 1, };
-static int mt7629_wf5g_led_pins[] = { 18, };
-static int mt7629_wf5g_led_funcs[] = { 1, };
+static const int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
+static const int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7629_ephy_led0_pins[] = { 12, };
+static const int mt7629_ephy_led0_funcs[] = { 1, };
+static const int mt7629_ephy_led1_pins[] = { 13, };
+static const int mt7629_ephy_led1_funcs[] = { 1, };
+static const int mt7629_ephy_led2_pins[] = { 14, };
+static const int mt7629_ephy_led2_funcs[] = { 1, };
+static const int mt7629_ephy_led3_pins[] = { 15, };
+static const int mt7629_ephy_led3_funcs[] = { 1, };
+static const int mt7629_ephy_led4_pins[] = { 16, };
+static const int mt7629_ephy_led4_funcs[] = { 1, };
+static const int mt7629_wf2g_led_pins[] = { 17, };
+static const int mt7629_wf2g_led_funcs[] = { 1, };
+static const int mt7629_wf5g_led_pins[] = { 18, };
+static const int mt7629_wf5g_led_funcs[] = { 1, };
 
 /* LED for EPHY used as JTAG */
-static int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, };
-static int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, };
+static const int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, };
+static const int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, };
 
 /* Watchdog */
-static int mt7629_watchdog_pins[] = { 11, };
-static int mt7629_watchdog_funcs[] = { 1, };
+static const int mt7629_watchdog_pins[] = { 11, };
+static const int mt7629_watchdog_funcs[] = { 1, };
 
 /* LED for GPHY */
-static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
-static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
-static int mt7629_gphy_led1_0_pins[] = { 21, };
-static int mt7629_gphy_led1_0_funcs[] = { 2, };
-static int mt7629_gphy_led2_0_pins[] = { 22, };
-static int mt7629_gphy_led2_0_funcs[] = { 2, };
-static int mt7629_gphy_led3_0_pins[] = { 23, };
-static int mt7629_gphy_led3_0_funcs[] = { 2, };
-static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
-static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
-static int mt7629_gphy_led1_1_pins[] = { 57, };
-static int mt7629_gphy_led1_1_funcs[] = { 1, };
-static int mt7629_gphy_led2_1_pins[] = { 58, };
-static int mt7629_gphy_led2_1_funcs[] = { 1, };
-static int mt7629_gphy_led3_1_pins[] = { 59, };
-static int mt7629_gphy_led3_1_funcs[] = { 1, };
+static const int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
+static const int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
+static const int mt7629_gphy_led1_0_pins[] = { 21, };
+static const int mt7629_gphy_led1_0_funcs[] = { 2, };
+static const int mt7629_gphy_led2_0_pins[] = { 22, };
+static const int mt7629_gphy_led2_0_funcs[] = { 2, };
+static const int mt7629_gphy_led3_0_pins[] = { 23, };
+static const int mt7629_gphy_led3_0_funcs[] = { 2, };
+static const int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
+static const int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
+static const int mt7629_gphy_led1_1_pins[] = { 57, };
+static const int mt7629_gphy_led1_1_funcs[] = { 1, };
+static const int mt7629_gphy_led2_1_pins[] = { 58, };
+static const int mt7629_gphy_led2_1_funcs[] = { 1, };
+static const int mt7629_gphy_led3_1_pins[] = { 59, };
+static const int mt7629_gphy_led3_1_funcs[] = { 1, };
 
 /* I2C */
-static int mt7629_i2c_0_pins[] = { 19, 20, };
-static int mt7629_i2c_0_funcs[] = { 1, 1, };
-static int mt7629_i2c_1_pins[] = { 53, 54, };
-static int mt7629_i2c_1_funcs[] = { 1, 1, };
+static const int mt7629_i2c_0_pins[] = { 19, 20, };
+static const int mt7629_i2c_0_funcs[] = { 1, 1, };
+static const int mt7629_i2c_1_pins[] = { 53, 54, };
+static const int mt7629_i2c_1_funcs[] = { 1, 1, };
 
 /* SPI */
-static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
-static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
-static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
-static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
-static int mt7629_spi_wp_pins[] = { 66, };
-static int mt7629_spi_wp_funcs[] = { 1, };
-static int mt7629_spi_hold_pins[] = { 67, };
-static int mt7629_spi_hold_funcs[] = { 1, };
+static const int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
+static const int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
+static const int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
+static const int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
+static const int mt7629_spi_wp_pins[] = { 66, };
+static const int mt7629_spi_wp_funcs[] = { 1, };
+static const int mt7629_spi_hold_pins[] = { 67, };
+static const int mt7629_spi_hold_funcs[] = { 1, };
 
 /* UART */
-static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
-static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
-static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
-static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
-static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
-static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
-static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
-static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
-static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
-static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
-static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
-static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
-static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
-static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
-static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
-static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
-static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
-static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
+static const int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
+static const int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
+static const int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
+static const int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
+static const int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
+static const int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
+static const int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
+static const int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
+static const int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
+static const int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
+static const int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
+static const int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
+static const int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
+static const int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
+static const int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
+static const int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
+static const int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
+static const int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
 
 /* MDC/MDIO */
-static int mt7629_mdc_mdio_pins[] = { 49, 50, };
-static int mt7629_mdc_mdio_funcs[] = { 1, 1, };
+static const int mt7629_mdc_mdio_pins[] = { 49, 50, };
+static const int mt7629_mdc_mdio_funcs[] = { 1, 1, };
 
 /* PCIE */
-static int mt7629_pcie_pereset_pins[] = { 51, };
-static int mt7629_pcie_pereset_funcs[] = { 1, };
-static int mt7629_pcie_wake_pins[] = { 55, };
-static int mt7629_pcie_wake_funcs[] = { 1, };
-static int mt7629_pcie_clkreq_pins[] = { 56, };
-static int mt7629_pcie_clkreq_funcs[] = { 1, };
+static const int mt7629_pcie_pereset_pins[] = { 51, };
+static const int mt7629_pcie_pereset_funcs[] = { 1, };
+static const int mt7629_pcie_wake_pins[] = { 55, };
+static const int mt7629_pcie_wake_funcs[] = { 1, };
+static const int mt7629_pcie_clkreq_pins[] = { 56, };
+static const int mt7629_pcie_clkreq_funcs[] = { 1, };
 
 /* PWM */
-static int mt7629_pwm_0_pins[] = { 52, };
-static int mt7629_pwm_0_funcs[] = { 1, };
-static int mt7629_pwm_1_pins[] = { 61, };
-static int mt7629_pwm_1_funcs[] = { 2, };
+static const int mt7629_pwm_0_pins[] = { 52, };
+static const int mt7629_pwm_0_funcs[] = { 1, };
+static const int mt7629_pwm_1_pins[] = { 61, };
+static const int mt7629_pwm_1_funcs[] = { 2, };
 
 /* WF 2G */
-static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
-static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
+static const int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
 
 /* SNFI */
-static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
-static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
+static const int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
+static const int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
 
 /* SPI NOR */
-static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
-static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
+static const int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
+static const int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
 
 static const struct mtk_group_desc mt7629_groups[] = {
 	PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g),
@@ -385,7 +385,7 @@ static const struct mtk_function_desc mt7629_functions[] = {
 	{"jtag", mt7629_jtag_groups, ARRAY_SIZE(mt7629_jtag_groups)},
 };
 
-static struct mtk_pinctrl_soc mt7629_data = {
+static const struct mtk_pinctrl_soc mt7629_data = {
 	.name = "mt7629_pinctrl",
 	.reg_cal = mt7629_reg_cals,
 	.pins = mt7629_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
index d8875241cb..3fa198ed79 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
@@ -570,242 +570,246 @@ static const struct mtk_pin_desc mt7981_pins[] = {
 };
 
 /* WA_AICE */
-static int mt7981_wa_aice1_pins[] = { 0, 1, };
-static int mt7981_wa_aice1_funcs[] = { 2, 2, };
+static const int mt7981_wa_aice1_pins[] = { 0, 1, };
+static const int mt7981_wa_aice1_funcs[] = { 2, 2, };
 
-static int mt7981_wa_aice2_pins[] = { 0, 1, };
-static int mt7981_wa_aice2_funcs[] = { 3, 3, };
+static const int mt7981_wa_aice2_pins[] = { 0, 1, };
+static const int mt7981_wa_aice2_funcs[] = { 3, 3, };
 
-static int mt7981_wa_aice3_pins[] = { 28, 29, };
-static int mt7981_wa_aice3_funcs[] = { 3, 3, };
+static const int mt7981_wa_aice3_pins[] = { 28, 29, };
+static const int mt7981_wa_aice3_funcs[] = { 3, 3, };
 
-static int mt7981_wm_aice1_pins[] = { 9, 10, };
-static int mt7981_wm_aice1_funcs[] = { 2, 2, };
+static const int mt7981_wm_aice1_pins[] = { 9, 10, };
+static const int mt7981_wm_aice1_funcs[] = { 2, 2, };
 
-static int mt7981_wm_aice2_pins[] = { 30, 31, };
-static int mt7981_wm_aice2_funcs[] = { 5, 5, };
+static const int mt7981_wm_aice2_pins[] = { 30, 31, };
+static const int mt7981_wm_aice2_funcs[] = { 5, 5, };
 
 /* WM_UART */
-static int mt7981_wm_uart_0_pins[] = { 0, 1, };
-static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
+static const int mt7981_wm_uart_0_pins[] = { 0, 1, };
+static const int mt7981_wm_uart_0_funcs[] = { 5, 5, };
 
-static int mt7981_wm_uart_1_pins[] = { 20, 21, };
-static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
+static const int mt7981_wm_uart_1_pins[] = { 20, 21, };
+static const int mt7981_wm_uart_1_funcs[] = { 4, 4, };
 
-static int mt7981_wm_uart_2_pins[] = { 30, 31, };
-static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
+static const int mt7981_wm_uart_2_pins[] = { 30, 31, };
+static const int mt7981_wm_uart_2_funcs[] = { 3, 3, };
 
 /* DFD */
-static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
-static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
+static const int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
+static const int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
 
 /* SYS_WATCHDOG */
-static int mt7981_watchdog_pins[] = { 2, };
-static int mt7981_watchdog_funcs[] = { 1, };
+static const int mt7981_watchdog_pins[] = { 2, };
+static const int mt7981_watchdog_funcs[] = { 1, };
 
-static int mt7981_watchdog1_pins[] = { 13, };
-static int mt7981_watchdog1_funcs[] = { 5, };
+static const int mt7981_watchdog1_pins[] = { 13, };
+static const int mt7981_watchdog1_funcs[] = { 5, };
 
 /* PCIE_PERESET_N */
-static int mt7981_pcie_pereset_pins[] = { 3, };
-static int mt7981_pcie_pereset_funcs[] = { 1, };
+static const int mt7981_pcie_pereset_pins[] = { 3, };
+static const int mt7981_pcie_pereset_funcs[] = { 1, };
 
 /* JTAG */
-static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
+static const int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
+static const int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
 
 /* WM_JTAG */
-static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
+static const int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
+static const int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
 
-static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
-static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
+static const int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
+static const int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
 
 /* WO0_JTAG */
-static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
+static const int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
+static const int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
 
-static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
-static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
+static const int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
+static const int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
 
 /* UART2 */
-static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
+static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
+static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
 
 /* GBE_LED0 */
-static int mt7981_gbe_led0_pins[] = { 8, };
-static int mt7981_gbe_led0_funcs[] = { 3, };
+static const int mt7981_gbe_led0_pins[] = { 8, };
+static const int mt7981_gbe_led0_funcs[] = { 3, };
 
 /* PTA_EXT */
-static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
-static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
+static const int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
+static const int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
 
-static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
-static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
+static const int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
+static const int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
 
 /* PWM2 */
-static int mt7981_pwm2_pins[] = { 7, };
-static int mt7981_pwm2_funcs[] = { 4, };
+static const int mt7981_pwm2_pins[] = { 7, };
+static const int mt7981_pwm2_funcs[] = { 4, };
 
 /* NET_WO0_UART_TXD */
-static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
-static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
+static const int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
+static const int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
 
-static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
-static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
+static const int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
+static const int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
 
-static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
-static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
+static const int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
+static const int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
 
 /* SPI1 */
-static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
+static const int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
+static const int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
 
 /* I2C */
-static int mt7981_i2c0_0_pins[] = { 6, 7, };
-static int mt7981_i2c0_0_funcs[] = { 6, 6, };
+static const int mt7981_i2c0_0_pins[] = { 6, 7, };
+static const int mt7981_i2c0_0_funcs[] = { 6, 6, };
 
-static int mt7981_i2c0_1_pins[] = { 30, 31, };
-static int mt7981_i2c0_1_funcs[] = { 4, 4, };
+static const int mt7981_i2c0_1_pins[] = { 30, 31, };
+static const int mt7981_i2c0_1_funcs[] = { 4, 4, };
 
-static int mt7981_i2c0_2_pins[] = { 36, 37, };
-static int mt7981_i2c0_2_funcs[] = { 2, 2, };
+static const int mt7981_i2c0_2_pins[] = { 36, 37, };
+static const int mt7981_i2c0_2_funcs[] = { 2, 2, };
 
-static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
-static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
+static const int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
+static const int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
 
-static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
+static const int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
+static const int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
 
-static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
+static const int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
+static const int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
 
-static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
+static const int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
+static const int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
 
 /* DFD_NTRST */
-static int mt7981_dfd_ntrst_pins[] = { 8, };
-static int mt7981_dfd_ntrst_funcs[] = { 6, };
+static const int mt7981_dfd_ntrst_pins[] = { 8, };
+static const int mt7981_dfd_ntrst_funcs[] = { 6, };
 
 /* PWM0 */
-static int mt7981_pwm0_0_pins[] = { 13, };
-static int mt7981_pwm0_0_funcs[] = { 2, };
+static const int mt7981_pwm0_0_pins[] = { 13, };
+static const int mt7981_pwm0_0_funcs[] = { 2, };
 
-static int mt7981_pwm0_1_pins[] = { 15, };
-static int mt7981_pwm0_1_funcs[] = { 1, };
+static const int mt7981_pwm0_1_pins[] = { 15, };
+static const int mt7981_pwm0_1_funcs[] = { 1, };
 
 /* PWM1 */
-static int mt7981_pwm1_0_pins[] = { 14, };
-static int mt7981_pwm1_0_funcs[] = { 2, };
+static const int mt7981_pwm1_0_pins[] = { 14, };
+static const int mt7981_pwm1_0_funcs[] = { 2, };
 
-static int mt7981_pwm1_1_pins[] = { 15, };
-static int mt7981_pwm1_1_funcs[] = { 3, };
+static const int mt7981_pwm1_1_pins[] = { 15, };
+static const int mt7981_pwm1_1_funcs[] = { 3, };
 
 /* GBE_LED1 */
-static int mt7981_gbe_led1_pins[] = { 13, };
-static int mt7981_gbe_led1_funcs[] = { 3, };
+static const int mt7981_gbe_led1_pins[] = { 13, };
+static const int mt7981_gbe_led1_funcs[] = { 3, };
 
 /* PCM */
-static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
-static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
+static const int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
+static const int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
 
 /* UDI */
-static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
+static const int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
+static const int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
 
 /* DRV_VBUS */
-static int mt7981_drv_vbus_pins[] = { 14, };
-static int mt7981_drv_vbus_funcs[] = { 1, };
+static const int mt7981_drv_vbus_pins[] = { 14, };
+static const int mt7981_drv_vbus_funcs[] = { 1, };
 
 /* EMMC */
-static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+static const int mt7981_emmc_45_pins[] = {
+	15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
+static const int mt7981_emmc_45_funcs[] = {
+	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
 
 /* SNFI */
-static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
-static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
+static const int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
+static const int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
 
 /* SPI0 */
-static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
+static const int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
+static const int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
 
 /* SPI0 */
-static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
-static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
+static const int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
+static const int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
 
 /* SPI1 */
-static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
+static const int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
+static const int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
 
 /* SPI2 */
-static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
-static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
+static const int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
+static const int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
 
 /* SPI2 */
-static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
-static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
+static const int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
+static const int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
 
 /* UART1 */
-static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
+static const int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
+static const int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
 
-static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
-static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
+static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
+static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
 
 /* UART2 */
-static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
+static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
+static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
 
 /* UART0 */
-static int mt7981_uart0_pins[] = { 32, 33, };
-static int mt7981_uart0_funcs[] = { 1, 1, };
+static const int mt7981_uart0_pins[] = { 32, 33, };
+static const int mt7981_uart0_funcs[] = { 1, 1, };
 
 /* PCIE_CLK_REQ */
-static int mt7981_pcie_clk_pins[] = { 34, };
-static int mt7981_pcie_clk_funcs[] = { 2, };
+static const int mt7981_pcie_clk_pins[] = { 34, };
+static const int mt7981_pcie_clk_funcs[] = { 2, };
 
 /* PCIE_WAKE_N */
-static int mt7981_pcie_wake_pins[] = { 35, };
-static int mt7981_pcie_wake_funcs[] = { 2, };
+static const int mt7981_pcie_wake_pins[] = { 35, };
+static const int mt7981_pcie_wake_funcs[] = { 2, };
 
 /* MDC_MDIO */
-static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
+static const int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
+static const int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
 
-static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
+static const int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
+static const int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
 
 /* WF0_MODE1 */
-static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
-				       50, 51, 52, 53, 54, 55, 56 };
-static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-					1, 1, 1, 1 };
+static const int mt7981_wf0_mode1_pins[] = {
+	40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
+static const int mt7981_wf0_mode1_funcs[] = {
+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 
 /* WF0_MODE3 */
-static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
-static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
+static const int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
+static const int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
 
 /* WF2G_LED */
-static int mt7981_wf2g_led0_pins[] = { 30, };
-static int mt7981_wf2g_led0_funcs[] = { 2, };
+static const int mt7981_wf2g_led0_pins[] = { 30, };
+static const int mt7981_wf2g_led0_funcs[] = { 2, };
 
-static int mt7981_wf2g_led1_pins[] = { 34, };
-static int mt7981_wf2g_led1_funcs[] = { 1, };
+static const int mt7981_wf2g_led1_pins[] = { 34, };
+static const int mt7981_wf2g_led1_funcs[] = { 1, };
 
 /* WF5G_LED */
-static int mt7981_wf5g_led0_pins[] = { 31, };
-static int mt7981_wf5g_led0_funcs[] = { 2, };
+static const int mt7981_wf5g_led0_pins[] = { 31, };
+static const int mt7981_wf5g_led0_funcs[] = { 2, };
 
-static int mt7981_wf5g_led1_pins[] = { 35, };
-static int mt7981_wf5g_led1_funcs[] = { 1, };
+static const int mt7981_wf5g_led1_pins[] = { 35, };
+static const int mt7981_wf5g_led1_funcs[] = { 1, };
 
 /* MT7531_INT */
-static int mt7981_mt7531_int_pins[] = { 38, };
-static int mt7981_mt7531_int_funcs[] = { 1, };
+static const int mt7981_mt7531_int_pins[] = { 38, };
+static const int mt7981_mt7531_int_funcs[] = { 1, };
 
 /* ANT_SEL */
-static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
-static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
+static const int mt7981_ant_sel_pins[] = {
+	14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
+static const int mt7981_ant_sel_funcs[] = {
+	6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
 
 static const struct mtk_group_desc mt7981_groups[] = {
 	/* @GPIO(0,1): WA_AICE(2) */
@@ -1012,7 +1016,7 @@ static const char *const mt7981_pinctrl_register_base_names[] = {
 	"iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base",
 };
 
-static struct mtk_pinctrl_soc mt7981_data = {
+static const struct mtk_pinctrl_soc mt7981_data = {
 	.name = "mt7981_pinctrl",
 	.reg_cal = mt7981_reg_cals,
 	.pins = mt7981_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
index 449e5adcd9..819d64488f 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
@@ -554,114 +554,117 @@ static const struct mtk_io_type_desc mt7986_io_type_desc[] = {
  * The hardware probably has multiple combinations of these pinouts.
  */
 
-static int mt7986_watchdog_pins[] = { 0, };
-static int mt7986_watchdog_funcs[] = { 1, };
+static const int mt7986_watchdog_pins[] = { 0, };
+static const int mt7986_watchdog_funcs[] = { 1, };
 
-static int mt7986_wifi_led_pins[] = { 1, 2, };
-static int mt7986_wifi_led_funcs[] = { 1, 1, };
+static const int mt7986_wifi_led_pins[] = { 1, 2, };
+static const int mt7986_wifi_led_funcs[] = { 1, 1, };
 
-static int mt7986_i2c_pins[] = { 3, 4, };
-static int mt7986_i2c_funcs[] = { 1, 1, };
+static const int mt7986_i2c_pins[] = { 3, 4, };
+static const int mt7986_i2c_funcs[] = { 1, 1, };
 
-static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
-static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
+static const int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
+static const int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
 
-static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
-static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
+static const int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
+static const int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
 
-static int mt7986_pwm1_1_pins[] = { 20, };
-static int mt7986_pwm1_1_funcs[] = { 2, };
+static const int mt7986_pwm1_1_pins[] = { 20, };
+static const int mt7986_pwm1_1_funcs[] = { 2, };
 
-static int mt7986_pwm0_pins[] = { 21, };
-static int mt7986_pwm0_funcs[] = { 1, };
+static const int mt7986_pwm0_pins[] = { 21, };
+static const int mt7986_pwm0_funcs[] = { 1, };
 
-static int mt7986_pwm1_0_pins[] = { 22, };
-static int mt7986_pwm1_0_funcs[] = { 1, };
+static const int mt7986_pwm1_0_pins[] = { 22, };
+static const int mt7986_pwm1_0_funcs[] = { 1, };
 
-static int mt7986_emmc_45_pins[] = {
+static const int mt7986_emmc_45_pins[] = {
 	22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
-static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+static const int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
 
-static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
-static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
+static const int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
+static const int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
 
-static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
+static const int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
+static const int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
 
-static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
+static const int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
+static const int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
 
-static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
-static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
+static const int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
+static const int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
 
-static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
-static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
+static const int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
+static const int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
 
-static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
-static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
+static const int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
+static const int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
 
-static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
+static const int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
+static const int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
 
-static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
-static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
+static const int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
+static const int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
 
-static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
-static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
+static const int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
+static const int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
 
-static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
-static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
+static const int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
+static const int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
 
-static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
-static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
+static const int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
+static const int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
 
-static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
+static const int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
+static const int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
 
-static int mt7986_uart0_pins[] = { 39, 40, };
-static int mt7986_uart0_funcs[] = { 1, 1, };
+static const int mt7986_uart0_pins[] = { 39, 40, };
+static const int mt7986_uart0_funcs[] = { 1, 1, };
 
-static int mt7986_pcie_reset_pins[] = { 41, };
-static int mt7986_pcie_reset_funcs[] = { 1, };
+static const int mt7986_pcie_reset_pins[] = { 41, };
+static const int mt7986_pcie_reset_funcs[] = { 1, };
 
-static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
-static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
+static const int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
+static const int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
 
-static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
-static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
+static const int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
+static const int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
 
-static int mt7986_emmc_51_pins[] = {
+static const int mt7986_emmc_51_pins[] = {
 	50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
-static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7986_emmc_51_funcs[] = {
+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
 
-static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
-static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
+static const int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
+static const int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
 
-static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
-static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
+static const int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
+static const int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
 
-static int mt7986_switch_int_pins[] = { 66, };
-static int mt7986_switch_int_funcs[] = { 1, };
+static const int mt7986_switch_int_pins[] = { 66, };
+static const int mt7986_switch_int_funcs[] = { 1, };
 
-static int mt7986_mdc_mdio_pins[] = { 67, 68, };
-static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
+static const int mt7986_mdc_mdio_pins[] = { 67, 68, };
+static const int mt7986_mdc_mdio_funcs[] = { 1, 1, };
 
-static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
-static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7986_wf_2g_pins[] = {
+	74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
+static const int mt7986_wf_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
 
-static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
-static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7986_wf_5g_pins[] = {
+	91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
+static const int mt7986_wf_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
 
-static int mt7986_wf_dbdc_pins[] = {
+static const int mt7986_wf_dbdc_pins[] = {
 	74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
-static int mt7986_wf_dbdc_funcs[] = {
+static const int mt7986_wf_dbdc_funcs[] = {
 	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
 
-static int mt7986_pcie_clk_pins[] = { 9, };
-static int mt7986_pcie_clk_funcs[] = { 1, };
+static const int mt7986_pcie_clk_pins[] = { 9, };
+static const int mt7986_pcie_clk_funcs[] = { 1, };
 
-static int mt7986_pcie_wake_pins[] = { 10, };
-static int mt7986_pcie_wake_funcs[] = { 1, };
+static const int mt7986_pcie_wake_pins[] = { 10, };
+static const int mt7986_pcie_wake_funcs[] = { 1, };
 
 static const struct mtk_group_desc mt7986_groups[] = {
 	PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
@@ -738,7 +741,7 @@ static const struct mtk_function_desc mt7986_functions[] = {
 	{"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
 };
 
-static struct mtk_pinctrl_soc mt7986_data = {
+static const struct mtk_pinctrl_soc mt7986_data = {
 	.name = "mt7986_pinctrl",
 	.reg_cal = mt7986_reg_cals,
 	.pins = mt7986_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c
new file mode 100644
index 0000000000..03a38e83df
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c
@@ -0,0 +1,1274 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dm.h>
+#include "pinctrl-mtk-common.h"
+
+enum MT7988_PINCTRL_REG_PAGE {
+	GPIO_BASE,
+	IOCFG_TR_BASE,
+	IOCFG_BR_BASE,
+	IOCFG_RB_BASE,
+	IOCFG_LB_BASE,
+	IOCFG_TL_BASE,
+};
+
+#define MT7988_TYPE0_PIN(_number, _name)                                       \
+	MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
+
+#define MT7988_TYPE1_PIN(_number, _name)                                       \
+	MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
+
+#define MT7988_TYPE2_PIN(_number, _name)                                       \
+	MTK_TYPED_PIN(_number, _name, DRV_FIXED, IO_TYPE_GRP2)
+
+#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)     \
+	PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs,      \
+			    _s_bit, _x_bits, 32, 0)
+
+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
+		       _x_bits)                                                \
+	PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs,        \
+			    _s_bit, _x_bits, 32, 0)
+
+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,    \
+			_x_bits)                                               \
+	PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs,        \
+			    _s_bit, _x_bits, 32, 1)
+
+static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
+	PIN_FIELD_GPIO(0, 83, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
+	PIN_FIELD_GPIO(0, 83, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
+	PIN_FIELD_GPIO(0, 83, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
+	PIN_FIELD_GPIO(0, 83, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x30, 0x10, 13, 1),
+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x30, 0x10, 11, 1),
+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 9, 1),
+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 10, 1),
+
+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x30, 0x10, 8, 1),
+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x30, 0x10, 6, 1),
+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x30, 0x10, 5, 1),
+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x30, 0x10, 3, 1),
+
+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x40, 0x10, 21, 1),
+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
+
+	PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x30, 0x10, 7, 1),
+	PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
+	PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x30, 0x10, 3, 1),
+	PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
+
+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x30, 0x10, 7, 1),
+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x30, 0x10, 4, 1),
+
+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x50, 0x10, 17, 1),
+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x50, 0x10, 23, 1),
+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x50, 0x10, 20, 1),
+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x50, 0x10, 19, 1),
+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x50, 0x10, 21, 1),
+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x50, 0x10, 22, 1),
+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x50, 0x10, 18, 1),
+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x50, 0x10, 25, 1),
+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x50, 0x10, 26, 1),
+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x50, 0x10, 27, 1),
+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x50, 0x10, 24, 1),
+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x50, 0x10, 28, 1),
+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x50, 0x10, 31, 1),
+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x50, 0x10, 29, 1),
+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x50, 0x10, 30, 1),
+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x60, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x50, 0x10, 11, 1),
+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x50, 0x10, 10, 1),
+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x50, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x50, 0x10, 1, 1),
+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x50, 0x10, 9, 1),
+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x50, 0x10, 8, 1),
+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x50, 0x10, 7, 1),
+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x50, 0x10, 6, 1),
+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x50, 0x10, 5, 1),
+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x50, 0x10, 4, 1),
+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x50, 0x10, 3, 1),
+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x50, 0x10, 2, 1),
+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x50, 0x10, 15, 1),
+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x50, 0x10, 12, 1),
+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x50, 0x10, 13, 1),
+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x50, 0x10, 14, 1),
+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x50, 0x10, 16, 1),
+
+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x40, 0x10, 15, 1),
+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x40, 0x10, 13, 1),
+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x40, 0x10, 3, 1),
+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x40, 0x10, 7, 1),
+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x40, 0x10, 20, 1),
+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x40, 0x10, 8, 1),
+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x40, 0x10, 10, 1),
+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x40, 0x10, 11, 1),
+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x40, 0x10, 12, 1),
+
+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
+	PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x30, 0x10, 5, 1),
+	PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x30, 0x10, 6, 1),
+
+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x30, 0x10, 10, 1),
+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x30, 0x10, 1, 1),
+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x30, 0x10, 11, 1),
+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x30, 0x10, 9, 1),
+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x30, 0x10, 2, 1),
+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x30, 0x10, 0, 1),
+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x30, 0x10, 12, 1),
+
+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x40, 0x10, 18, 1),
+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x40, 0x10, 19, 1),
+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x40, 0x10, 17, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0xc0, 0x10, 13, 1),
+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0xc0, 0x10, 14, 1),
+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0xc0, 0x10, 11, 1),
+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0xc0, 0x10, 12, 1),
+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0xc0, 0x10, 0, 1),
+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0xc0, 0x10, 9, 1),
+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0xc0, 0x10, 10, 1),
+
+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0xb0, 0x10, 8, 1),
+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0xb0, 0x10, 6, 1),
+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0xb0, 0x10, 5, 1),
+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0xb0, 0x10, 3, 1),
+
+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0xe0, 0x10, 0, 1),
+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0xe0, 0x10, 21, 1),
+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0xe0, 0x10, 1, 1),
+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0xe0, 0x10, 2, 1),
+
+	PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0xc0, 0x10, 7, 1),
+	PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0xc0, 0x10, 8, 1),
+	PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0xc0, 0x10, 3, 1),
+	PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0xc0, 0x10, 4, 1),
+
+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0xb0, 0x10, 7, 1),
+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0xb0, 0x10, 4, 1),
+
+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x140, 0x10, 17, 1),
+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x140, 0x10, 23, 1),
+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x140, 0x10, 20, 1),
+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x140, 0x10, 19, 1),
+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x140, 0x10, 21, 1),
+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x140, 0x10, 22, 1),
+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x140, 0x10, 18, 1),
+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x140, 0x10, 25, 1),
+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x140, 0x10, 26, 1),
+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x140, 0x10, 27, 1),
+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x140, 0x10, 24, 1),
+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x140, 0x10, 28, 1),
+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x150, 0x10, 0, 1),
+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x140, 0x10, 31, 1),
+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x140, 0x10, 29, 1),
+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x140, 0x10, 30, 1),
+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x150, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x140, 0x10, 11, 1),
+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x140, 0x10, 10, 1),
+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x140, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x140, 0x10, 1, 1),
+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x140, 0x10, 9, 1),
+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x140, 0x10, 8, 1),
+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x140, 0x10, 7, 1),
+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x140, 0x10, 6, 1),
+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x140, 0x10, 5, 1),
+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x140, 0x10, 4, 1),
+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x140, 0x10, 3, 1),
+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x140, 0x10, 2, 1),
+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x140, 0x10, 15, 1),
+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x140, 0x10, 12, 1),
+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x140, 0x10, 13, 1),
+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x140, 0x10, 14, 1),
+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x140, 0x10, 16, 1),
+
+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0xe0, 0x10, 14, 1),
+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0xe0, 0x10, 15, 1),
+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0xe0, 0x10, 13, 1),
+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0xe0, 0x10, 4, 1),
+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0xe0, 0x10, 5, 1),
+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0xe0, 0x10, 6, 1),
+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0xe0, 0x10, 3, 1),
+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0xe0, 0x10, 7, 1),
+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0xe0, 0x10, 20, 1),
+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0xe0, 0x10, 8, 1),
+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0xe0, 0x10, 9, 1),
+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0xe0, 0x10, 10, 1),
+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0xe0, 0x10, 11, 1),
+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0xe0, 0x10, 12, 1),
+
+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0xc0, 0x10, 1, 1),
+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0xc0, 0x10, 2, 1),
+	PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0xc0, 0x10, 5, 1),
+	PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0xc0, 0x10, 6, 1),
+
+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0xb0, 0x10, 10, 1),
+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0xb0, 0x10, 1, 1),
+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0xb0, 0x10, 11, 1),
+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0xb0, 0x10, 9, 1),
+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0xb0, 0x10, 2, 1),
+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0xb0, 0x10, 0, 1),
+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0xb0, 0x10, 12, 1),
+
+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0xe0, 0x10, 18, 1),
+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0xe0, 0x10, 19, 1),
+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0xe0, 0x10, 16, 1),
+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0xe0, 0x10, 17, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x60, 0x10, 5, 1),
+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x60, 0x10, 4, 1),
+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x60, 0x10, 3, 1),
+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
+
+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x70, 0x10, 0, 1),
+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x70, 0x10, 1, 1),
+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x70, 0x10, 2, 1),
+
+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x60, 0x10, 7, 1),
+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x60, 0x10, 6, 1),
+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x60, 0x10, 1, 1),
+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x60, 0x10, 8, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x40, 0x10, 5, 1),
+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x40, 0x10, 4, 1),
+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x40, 0x10, 3, 1),
+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
+
+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
+
+	PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
+	PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x40, 0x10, 5, 1),
+	PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
+	PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
+
+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
+	PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
+	PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x40, 0x10, 3, 1),
+
+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x40, 0x10, 7, 1),
+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x40, 0x10, 6, 1),
+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x40, 0x10, 1, 1),
+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x40, 0x10, 8, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x00, 0x10, 21, 3),
+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x00, 0x10, 15, 3),
+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x00, 0x10, 18, 3),
+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x00, 0x10, 9, 3),
+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
+
+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x00, 0x10, 24, 3),
+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x00, 0x10, 28, 3),
+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x00, 0x10, 15, 3),
+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x00, 0x10, 9, 3),
+
+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x20, 0x10, 3, 3),
+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
+
+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x00, 0x10, 21, 3),
+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x00, 0x10, 12, 3),
+
+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x20, 0x10, 6, 3),
+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x10, 0x10, 24, 3),
+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x20, 0x10, 18, 3),
+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x20, 0x10, 12, 3),
+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x20, 0x10, 24, 3),
+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x30, 0x10, 6, 3),
+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x30, 0x10, 3, 3),
+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x20, 0x10, 27, 3),
+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x30, 0x10, 0, 3),
+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x30, 0x10, 9, 3),
+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x10, 0x10, 3, 3),
+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x00, 0x10, 27, 3),
+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x00, 0x10, 18, 3),
+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x00, 0x10, 15, 3),
+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x00, 0x10, 12, 3),
+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x00, 0x10, 9, 3),
+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x00, 0x10, 6, 3),
+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
+
+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x10, 0x10, 15, 3),
+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x10, 0x10, 9, 3),
+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x00, 0x10, 18, 3),
+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x00, 0x10, 9, 3),
+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x00, 0x10, 21, 3),
+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x20, 0x10, 0, 3),
+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x00, 0x10, 24, 3),
+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x10, 0x10, 3, 3),
+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x10, 0x10, 6, 3),
+
+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
+
+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x10, 0x10, 0, 3),
+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x00, 0x10, 3, 3),
+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x10, 0x10, 3, 3),
+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x00, 0x10, 27, 3),
+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x00, 0x10, 6, 3),
+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x00, 0x10, 0, 3),
+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x10, 0x10, 6, 3),
+
+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x10, 0x10, 24, 3),
+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 27, 3),
+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 21, 3),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x50, 0x10, 7, 1),
+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x50, 0x10, 5, 1),
+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 6, 1),
+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1),
+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
+
+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x60, 0x10, 0, 1),
+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x60, 0x10, 18, 1),
+
+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x50, 0x10, 1, 1),
+
+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x70, 0x10, 20, 1),
+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x70, 0x10, 19, 1),
+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x70, 0x10, 22, 1),
+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x70, 0x10, 26, 1),
+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x70, 0x10, 24, 1),
+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x70, 0x10, 28, 1),
+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x70, 0x10, 31, 1),
+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x70, 0x10, 29, 1),
+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x70, 0x10, 30, 1),
+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x80, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x70, 0x10, 11, 1),
+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 10, 1),
+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 1, 1),
+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x70, 0x10, 9, 1),
+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x70, 0x10, 7, 1),
+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x70, 0x10, 6, 1),
+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x70, 0x10, 5, 1),
+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x70, 0x10, 4, 1),
+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x70, 0x10, 3, 1),
+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
+
+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x60, 0x10, 12, 1),
+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x60, 0x10, 13, 1),
+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x60, 0x10, 11, 1),
+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x60, 0x10, 2, 1),
+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x60, 0x10, 3, 1),
+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x60, 0x10, 4, 1),
+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x60, 0x10, 1, 1),
+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x60, 0x10, 5, 1),
+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x60, 0x10, 6, 1),
+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x60, 0x10, 7, 1),
+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x60, 0x10, 8, 1),
+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x60, 0x10, 9, 1),
+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x60, 0x10, 10, 1),
+
+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
+
+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x50, 0x10, 3, 1),
+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
+
+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x60, 0x10, 16, 1),
+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x60, 0x10, 17, 1),
+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x60, 0x10, 14, 1),
+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x60, 0x10, 15, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x60, 0x10, 7, 1),
+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x60, 0x10, 8, 1),
+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x60, 0x10, 5, 1),
+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x60, 0x10, 6, 1),
+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x60, 0x10, 0, 1),
+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x60, 0x10, 3, 1),
+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x60, 0x10, 4, 1),
+
+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x80, 0x10, 18, 1),
+
+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x70, 0x10, 2, 1),
+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x70, 0x10, 1, 1),
+
+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x90, 0x10, 17, 1),
+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x90, 0x10, 23, 1),
+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x90, 0x10, 20, 1),
+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x90, 0x10, 19, 1),
+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x90, 0x10, 21, 1),
+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x90, 0x10, 22, 1),
+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x90, 0x10, 18, 1),
+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x90, 0x10, 25, 1),
+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x90, 0x10, 26, 1),
+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x90, 0x10, 27, 1),
+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x90, 0x10, 24, 1),
+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x90, 0x10, 28, 1),
+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xa0, 0x10, 0, 1),
+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x90, 0x10, 31, 1),
+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x90, 0x10, 29, 1),
+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x90, 0x10, 30, 1),
+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xa0, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x90, 0x10, 11, 1),
+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x90, 0x10, 10, 1),
+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x90, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x90, 0x10, 1, 1),
+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x90, 0x10, 9, 1),
+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x90, 0x10, 8, 1),
+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x90, 0x10, 7, 1),
+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x90, 0x10, 6, 1),
+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x90, 0x10, 5, 1),
+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x90, 0x10, 4, 1),
+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x90, 0x10, 3, 1),
+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x90, 0x10, 2, 1),
+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x90, 0x10, 15, 1),
+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x90, 0x10, 12, 1),
+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x90, 0x10, 13, 1),
+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x90, 0x10, 14, 1),
+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x90, 0x10, 16, 1),
+
+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x80, 0x10, 12, 1),
+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x80, 0x10, 13, 1),
+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x80, 0x10, 11, 1),
+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x80, 0x10, 3, 1),
+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x80, 0x10, 7, 1),
+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x80, 0x10, 8, 1),
+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x80, 0x10, 10, 1),
+
+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x60, 0x10, 1, 1),
+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x60, 0x10, 2, 1),
+
+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x70, 0x10, 3, 1),
+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x70, 0x10, 0, 1),
+
+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 17, 1),
+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 15, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x70, 0x10, 7, 1),
+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x70, 0x10, 5, 1),
+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x70, 0x10, 6, 1),
+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x70, 0x10, 3, 1),
+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
+
+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x90, 0x10, 0, 1),
+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x90, 0x10, 18, 1),
+
+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x80, 0x10, 2, 1),
+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x80, 0x10, 1, 1),
+
+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0xb0, 0x10, 17, 1),
+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0xb0, 0x10, 23, 1),
+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0xb0, 0x10, 20, 1),
+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0xb0, 0x10, 19, 1),
+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0xb0, 0x10, 21, 1),
+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0xb0, 0x10, 22, 1),
+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0xb0, 0x10, 18, 1),
+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0xb0, 0x10, 25, 1),
+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0xb0, 0x10, 26, 1),
+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0xb0, 0x10, 27, 1),
+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0xb0, 0x10, 24, 1),
+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0xb0, 0x10, 28, 1),
+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xc0, 0x10, 0, 1),
+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0xb0, 0x10, 31, 1),
+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0xb0, 0x10, 29, 1),
+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0xb0, 0x10, 30, 1),
+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xc0, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0xb0, 0x10, 11, 1),
+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xb0, 0x10, 10, 1),
+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xb0, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xb0, 0x10, 1, 1),
+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0xb0, 0x10, 9, 1),
+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0xb0, 0x10, 8, 1),
+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0xb0, 0x10, 7, 1),
+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0xb0, 0x10, 6, 1),
+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0xb0, 0x10, 5, 1),
+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0xb0, 0x10, 4, 1),
+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0xb0, 0x10, 3, 1),
+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0xb0, 0x10, 2, 1),
+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0xb0, 0x10, 15, 1),
+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0xb0, 0x10, 12, 1),
+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0xb0, 0x10, 13, 1),
+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0xb0, 0x10, 14, 1),
+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0xb0, 0x10, 16, 1),
+
+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x90, 0x10, 12, 1),
+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x90, 0x10, 13, 1),
+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x90, 0x10, 11, 1),
+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x90, 0x10, 2, 1),
+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x90, 0x10, 3, 1),
+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x90, 0x10, 4, 1),
+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x90, 0x10, 1, 1),
+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x90, 0x10, 5, 1),
+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x90, 0x10, 6, 1),
+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x90, 0x10, 7, 1),
+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x90, 0x10, 8, 1),
+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x90, 0x10, 9, 1),
+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x90, 0x10, 10, 1),
+
+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
+
+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x80, 0x10, 3, 1),
+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x80, 0x10, 0, 1),
+
+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x90, 0x10, 16, 1),
+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x90, 0x10, 17, 1),
+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x90, 0x10, 14, 1),
+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x90, 0x10, 15, 1),
+};
+
+static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
+	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
+	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
+	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
+	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
+	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
+	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
+	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
+	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
+	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
+	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
+	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
+	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
+};
+
+static const struct mtk_pin_desc mt7988_pins[] = {
+	MT7988_TYPE0_PIN(0, "UART2_RXD"),
+	MT7988_TYPE0_PIN(1, "UART2_TXD"),
+	MT7988_TYPE0_PIN(2, "UART2_CTS"),
+	MT7988_TYPE0_PIN(3, "UART2_RTS"),
+	MT7988_TYPE0_PIN(4, "GPIO_A"),
+	MT7988_TYPE0_PIN(5, "SMI_0_MDC"),
+	MT7988_TYPE0_PIN(6, "SMI_0_MDIO"),
+	MT7988_TYPE1_PIN(7, "PCIE30_2L_0_WAKE_N"),
+	MT7988_TYPE1_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
+	MT7988_TYPE1_PIN(9, "PCIE30_1L_1_WAKE_N"),
+	MT7988_TYPE1_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
+	MT7988_TYPE0_PIN(11, "GPIO_P"),
+	MT7988_TYPE0_PIN(12, "WATCHDOG"),
+	MT7988_TYPE1_PIN(13, "GPIO_RESET"),
+	MT7988_TYPE1_PIN(14, "GPIO_WPS"),
+	MT7988_TYPE2_PIN(15, "PMIC_I2C_SCL"),
+	MT7988_TYPE2_PIN(16, "PMIC_I2C_SDA"),
+	MT7988_TYPE2_PIN(17, "I2C_1_SCL"),
+	MT7988_TYPE2_PIN(18, "I2C_1_SDA"),
+	MT7988_TYPE0_PIN(19, "PCIE30_2L_0_PRESET_N"),
+	MT7988_TYPE0_PIN(20, "PCIE30_1L_1_PRESET_N"),
+	MT7988_TYPE0_PIN(21, "PWMD1"),
+	MT7988_TYPE0_PIN(22, "SPI0_WP"),
+	MT7988_TYPE0_PIN(23, "SPI0_HOLD"),
+	MT7988_TYPE0_PIN(24, "SPI0_CSB"),
+	MT7988_TYPE0_PIN(25, "SPI0_MISO"),
+	MT7988_TYPE0_PIN(26, "SPI0_MOSI"),
+	MT7988_TYPE0_PIN(27, "SPI0_CLK"),
+	MT7988_TYPE0_PIN(28, "SPI1_CSB"),
+	MT7988_TYPE0_PIN(29, "SPI1_MISO"),
+	MT7988_TYPE0_PIN(30, "SPI1_MOSI"),
+	MT7988_TYPE0_PIN(31, "SPI1_CLK"),
+	MT7988_TYPE0_PIN(32, "SPI2_CLK"),
+	MT7988_TYPE0_PIN(33, "SPI2_MOSI"),
+	MT7988_TYPE0_PIN(34, "SPI2_MISO"),
+	MT7988_TYPE0_PIN(35, "SPI2_CSB"),
+	MT7988_TYPE0_PIN(36, "SPI2_HOLD"),
+	MT7988_TYPE0_PIN(37, "SPI2_WP"),
+	MT7988_TYPE0_PIN(38, "EMMC_RSTB"),
+	MT7988_TYPE0_PIN(39, "EMMC_DSL"),
+	MT7988_TYPE0_PIN(40, "EMMC_CK"),
+	MT7988_TYPE0_PIN(41, "EMMC_CMD"),
+	MT7988_TYPE0_PIN(42, "EMMC_DATA_7"),
+	MT7988_TYPE0_PIN(43, "EMMC_DATA_6"),
+	MT7988_TYPE0_PIN(44, "EMMC_DATA_5"),
+	MT7988_TYPE0_PIN(45, "EMMC_DATA_4"),
+	MT7988_TYPE0_PIN(46, "EMMC_DATA_3"),
+	MT7988_TYPE0_PIN(47, "EMMC_DATA_2"),
+	MT7988_TYPE0_PIN(48, "EMMC_DATA_1"),
+	MT7988_TYPE0_PIN(49, "EMMC_DATA_0"),
+	MT7988_TYPE0_PIN(50, "PCM_FS_I2S_LRCK"),
+	MT7988_TYPE0_PIN(51, "PCM_CLK_I2S_BCLK"),
+	MT7988_TYPE0_PIN(52, "PCM_DRX_I2S_DIN"),
+	MT7988_TYPE0_PIN(53, "PCM_DTX_I2S_DOUT"),
+	MT7988_TYPE0_PIN(54, "PCM_MCK_I2S_MCLK"),
+	MT7988_TYPE0_PIN(55, "UART0_RXD"),
+	MT7988_TYPE0_PIN(56, "UART0_TXD"),
+	MT7988_TYPE0_PIN(57, "PWMD0"),
+	MT7988_TYPE0_PIN(58, "JTAG_JTDI"),
+	MT7988_TYPE0_PIN(59, "JTAG_JTDO"),
+	MT7988_TYPE0_PIN(60, "JTAG_JTMS"),
+	MT7988_TYPE0_PIN(61, "JTAG_JTCLK"),
+	MT7988_TYPE0_PIN(62, "JTAG_JTRST_N"),
+	MT7988_TYPE1_PIN(63, "USB_DRV_VBUS_P1"),
+	MT7988_TYPE0_PIN(64, "LED_A"),
+	MT7988_TYPE0_PIN(65, "LED_B"),
+	MT7988_TYPE0_PIN(66, "LED_C"),
+	MT7988_TYPE0_PIN(67, "LED_D"),
+	MT7988_TYPE0_PIN(68, "LED_E"),
+	MT7988_TYPE0_PIN(69, "GPIO_B"),
+	MT7988_TYPE0_PIN(70, "GPIO_C"),
+	MT7988_TYPE2_PIN(71, "I2C_2_SCL"),
+	MT7988_TYPE2_PIN(72, "I2C_2_SDA"),
+	MT7988_TYPE0_PIN(73, "PCIE30_2L_1_PRESET_N"),
+	MT7988_TYPE0_PIN(74, "PCIE30_1L_0_PRESET_N"),
+	MT7988_TYPE1_PIN(75, "PCIE30_2L_1_WAKE_N"),
+	MT7988_TYPE1_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
+	MT7988_TYPE1_PIN(77, "PCIE30_1L_0_WAKE_N"),
+	MT7988_TYPE1_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
+	MT7988_TYPE1_PIN(79, "USB_DRV_VBUS_P0"),
+	MT7988_TYPE0_PIN(80, "UART1_RXD"),
+	MT7988_TYPE0_PIN(81, "UART1_TXD"),
+	MT7988_TYPE0_PIN(82, "UART1_CTS"),
+	MT7988_TYPE0_PIN(83, "UART1_RTS"),
+};
+
+/* jtag */
+static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
+static const int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
+
+static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
+static const int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
+
+static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
+static const int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
+
+static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
+static const int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
+
+static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
+static const int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
+
+static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
+static const int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
+
+/* int_usxgmii */
+static const int mt7988_int_usxgmii_pins[] = { 2, 3 };
+static const int mt7988_int_usxgmii_funcs[] = { 3, 3 };
+
+/* pwm */
+static const int mt7988_pwm0_pins[] = { 57 };
+static const int mt7988_pwm0_funcs[] = { 1 };
+
+static const int mt7988_pwm1_pins[] = { 21 };
+static const int mt7988_pwm1_funcs[] = { 1 };
+
+static const int mt7988_pwm2_pins[] = { 80 };
+static const int mt7988_pwm2_funcs[] = { 2 };
+
+static const int mt7988_pwm3_pins[] = { 81 };
+static const int mt7988_pwm3_funcs[] = { 2 };
+
+static const int mt7988_pwm4_pins[] = { 82 };
+static const int mt7988_pwm4_funcs[] = { 2 };
+
+static const int mt7988_pwm5_pins[] = { 83 };
+static const int mt7988_pwm5_funcs[] = { 2 };
+
+static const int mt7988_pwm6_pins[] = { 69 };
+static const int mt7988_pwm6_funcs[] = { 3 };
+
+static const int mt7988_pwm7_pins[] = { 70 };
+static const int mt7988_pwm7_funcs[] = { 3 };
+
+/* dfd */
+static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
+static const int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
+
+/* i2c */
+static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
+static const int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
+
+static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
+static const int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
+
+static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
+static const int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
+
+static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
+static const int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
+
+static const int mt7988_i2c0_0_pins[] = { 5, 6 };
+static const int mt7988_i2c0_0_funcs[] = { 2, 2 };
+
+static const int mt7988_i2c1_sfp_pins[] = { 5, 6 };
+static const int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
+
+static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
+static const int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
+
+static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
+static const int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
+
+static const int mt7988_i2c0_1_pins[] = { 15, 16 };
+static const int mt7988_i2c0_1_funcs[] = { 1, 1 };
+
+static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
+static const int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
+
+static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
+static const int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
+
+static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
+static const int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
+
+static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
+static const int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
+
+static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
+static const int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
+
+static const int mt7988_i2c1_0_pins[] = { 17, 18 };
+static const int mt7988_i2c1_0_funcs[] = { 1, 1 };
+
+static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
+static const int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
+
+static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
+static const int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
+
+static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
+static const int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
+
+static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
+static const int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
+
+static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
+static const int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
+
+static const int mt7988_i2c1_2_pins[] = { 69, 70 };
+static const int mt7988_i2c1_2_funcs[] = { 2, 2 };
+
+static const int mt7988_i2c2_0_pins[] = { 69, 70 };
+static const int mt7988_i2c2_0_funcs[] = { 4, 4 };
+
+static const int mt7988_i2c2_1_pins[] = { 71, 72 };
+static const int mt7988_i2c2_1_funcs[] = { 1, 1 };
+
+/* eth */
+static const int mt7988_mdc_mdio0_pins[] = { 5, 6 };
+static const int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
+
+static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
+static const int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
+
+static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
+static const int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
+
+static const int mt7988_mdc_mdio1_pins[] = { 69, 70 };
+static const int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
+
+/* pcie */
+static const int mt7988_pcie_wake_n0_0_pins[] = { 7 };
+static const int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
+
+static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
+static const int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
+
+static const int mt7988_pcie_wake_n3_0_pins[] = { 9 };
+static const int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
+
+static const int mt7988_pcie_clk_req_n3_pins[] = { 10 };
+static const int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
+
+static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
+static const int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
+
+static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
+static const int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
+
+static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
+static const int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
+
+static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
+static const int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
+
+static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
+static const int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
+
+static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
+static const int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
+
+static const int mt7988_pcie_wake_n0_1_pins[] = { 13 };
+static const int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
+
+static const int mt7988_pcie_wake_n3_1_pins[] = { 14 };
+static const int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
+
+static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
+static const int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
+
+static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
+static const int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
+
+static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
+static const int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
+
+static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
+static const int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
+
+static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
+static const int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
+
+static const int mt7988_pcie_wake_n1_0_pins[] = { 75 };
+static const int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
+
+static const int mt7988_pcie_clk_req_n1_pins[] = { 76 };
+static const int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
+
+static const int mt7988_pcie_wake_n2_0_pins[] = { 77 };
+static const int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
+
+static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
+static const int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
+
+static const int mt7988_pcie_wake_n2_1_pins[] = { 79 };
+static const int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
+
+/* pmic */
+static const int mt7988_pmic_pins[] = { 11 };
+static const int mt7988_pmic_funcs[] = { 1 };
+
+/* watchdog */
+static const int mt7988_watchdog_pins[] = { 12 };
+static const int mt7988_watchdog_funcs[] = { 1 };
+
+/* spi */
+static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
+static const int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
+
+static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
+static const int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
+
+static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
+static const int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
+
+static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
+static const int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
+
+static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
+static const int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
+
+/* flash */
+static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
+static const int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
+
+static const int mt7988_emmc_45_pins[] = {
+	21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 };
+static const int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
+
+static const int mt7988_emmc_51_pins[] = {
+	38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 };
+static const int mt7988_emmc_51_funcs[] = {
+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
+
+/* uart */
+static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
+static const int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
+
+static const int mt7988_tops_uart0_0_pins[] = { 22, 23 };
+static const int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
+
+static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
+static const int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
+
+static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
+static const int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
+
+static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
+static const int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
+
+static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
+static const int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
+
+static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
+static const int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
+
+static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
+static const int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
+
+static const int mt7988_tops_uart1_0_pins[] = { 28, 29 };
+static const int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
+
+static const int mt7988_tops_uart0_1_pins[] = { 30, 31 };
+static const int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
+
+static const int mt7988_tops_uart1_1_pins[] = { 36, 37 };
+static const int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
+
+static const int mt7988_uart0_pins[] = { 55, 56 };
+static const int mt7988_uart0_funcs[] = { 1, 1 };
+
+static const int mt7988_tops_uart0_2_pins[] = { 55, 56 };
+static const int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
+
+static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
+static const int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
+
+static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
+static const int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
+
+static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
+static const int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
+
+static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
+static const int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
+
+static const int mt7988_tops_uart1_2_pins[] = { 80, 81 };
+static const int mt7988_tops_uart1_2_funcs[] = { 4, 4, };
+
+static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
+static const int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
+
+static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
+static const int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
+
+static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
+static const int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
+
+/* udi */
+static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
+static const int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
+
+/* pcm */
+static const int mt7988_pcm_pins[] = { 50, 51, 52, 53, 54 };
+static const int mt7988_pcm_funcs[] = { 1, 1, 1, 1, 1 };
+
+/* led */
+static const int mt7988_gbe_led1_pins[] = { 58, 59, 60, 61 };
+static const int mt7988_gbe_led1_funcs[] = { 6, 6, 6, 6 };
+
+static const int mt7988_2p5gbe_led1_pins[] = { 62 };
+static const int mt7988_2p5gbe_led1_funcs[] = { 6 };
+
+static const int mt7988_gbe_led0_pins[] = { 64, 65, 66, 67 };
+static const int mt7988_gbe_led0_funcs[] = { 1, 1, 1, 1 };
+
+static const int mt7988_2p5gbe_led0_pins[] = { 68 };
+static const int mt7988_2p5gbe_led0_funcs[] = { 1 };
+
+/* usb */
+static const int mt7988_drv_vbus_p1_pins[] = { 63 };
+static const int mt7988_drv_vbus_p1_funcs[] = { 1 };
+
+static const int mt7988_drv_vbus_pins[] = { 79 };
+static const int mt7988_drv_vbus_funcs[] = { 1 };
+
+static const struct mtk_group_desc mt7988_groups[] = {
+	PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
+	PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
+	PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
+	PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
+	PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
+	PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
+	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
+	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
+	PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
+	PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
+	PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
+	PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
+	PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
+	PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
+	PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
+	PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
+	PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
+	PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
+	PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
+	PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
+	PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
+	PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
+	PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
+	PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
+	PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
+	PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
+	PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
+	PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
+	PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
+	PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
+	PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
+	PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
+	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
+	PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
+	PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
+	PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
+	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
+	PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
+	PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
+	PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
+	PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
+	PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
+	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
+	PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
+	PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
+	PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
+	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
+	PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
+	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
+	PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
+	PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
+	PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
+	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
+	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
+	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
+	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
+	PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
+	PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
+	PINCTRL_PIN_GROUP("udi", mt7988_udi),
+	PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
+	PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
+	PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
+	PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
+	PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
+	PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
+	PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
+	PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
+	PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
+	PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
+	PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
+	PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
+	PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
+	PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
+	PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
+	PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
+	PINCTRL_PIN_GROUP("gbe_led1", mt7988_gbe_led1),
+	PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
+	PINCTRL_PIN_GROUP("gbe_led0", mt7988_gbe_led0),
+	PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
+	PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
+	PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
+	PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
+	PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
+	PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
+	PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
+	PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
+	PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
+	PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
+	PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
+	PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
+	PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
+	PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
+	PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
+	PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
+	PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
+	PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
+	PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
+	PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
+	PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
+	PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
+	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
+	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
+	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
+	PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
+	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
+	PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
+	PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
+};
+
+static const struct mtk_io_type_desc mt7988_io_type_desc[] = {
+	[IO_TYPE_GRP0] = {
+		.name = "18OD33",
+		.bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
+		.drive_set = mtk_pinconf_drive_set_v1,
+		.input_enable = mtk_pinconf_input_enable_v1,
+	},
+	[IO_TYPE_GRP1] = {
+		.name = "18A01",
+		.bias_set = mtk_pinconf_bias_set_pu_pd,
+		.drive_set = mtk_pinconf_drive_set_v1,
+		.input_enable = mtk_pinconf_input_enable_v1,
+	},
+	[IO_TYPE_GRP2] = {
+		.name = "I2C",
+		.input_enable = mtk_pinconf_input_enable_v1,
+	},
+};
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *const mt7988_jtag_groups[] = { "tops_jtag0_0", "wo0_jtag",
+	"wo1_jtag", "wo2_jtag", "jtag", "tops_jtag0_1", };
+static const char *const mt7988_int_usxgmii_groups[] = { "int_usxgmii", };
+static const char *const mt7988_pwm_groups[] = { "pwm0", "pwm1", "pwm2", "pwm3",
+	"pwm4", "pwm5", "pwm6", "pwm7" };
+static const char *const mt7988_dfd_groups[] = { "dfd", };
+static const char *const mt7988_i2c_groups[] = { "xfi_phy0_i2c0",
+	"xfi_phy1_i2c0", "xfi_phy_pll_i2c0", "xfi_phy_pll_i2c1", "i2c0_0",
+	"i2c1_sfp", "xfi_pextp_phy0_i2c", "xfi_pextp_phy1_i2c", "i2c0_1",
+	"u30_phy_i2c0", "u32_phy_i2c0", "xfi_phy0_i2c1", "xfi_phy1_i2c1",
+	"xfi_phy_pll_i2c2", "i2c1_0", "u30_phy_i2c1", "u32_phy_i2c1",
+	"xfi_phy_pll_i2c3", "sgmii0_i2c", "sgmii1_i2c", "i2c1_2", "i2c2_0",
+	"i2c2_1", };
+static const char *const mt7988_ethernet_groups[] = { "mdc_mdio0",
+	"2p5g_ext_mdio", "gbe_ext_mdio", "mdc_mdio1", };
+static const char *const mt7988_pcie_groups[] = { "pcie_wake_n0_0",
+	"pcie_clk_req_n0_0", "pcie_wake_n3_0", "pcie_clk_req_n3",
+	"pcie_p0_phy_i2c", "pcie_p1_phy_i2c", "pcie_p3_phy_i2",
+	"pcie_p2_phy_i2c", "ckm_phy_i2c", "pcie_wake_n0_1", "pcie_wake_n3_1",
+	"pcie_2l_0_pereset", "pcie_1l_1_pereset", "pcie_clk_req_n2_1",
+	"pcie_2l_1_perese", "pcie_1l_0_pereset", "pcie_wake_n1_0",
+	"cie_clk_req_n1", "pcie_wake_n2_0", "pcie_wake_n2_1", };
+static const char *const mt7988_pmic_groups[] = { "pmic", };
+static const char *const mt7988_wdt_groups[] = { "watchdog", };
+static const char *const mt7988_spi_groups[] = { "spi0", "spi0_wp_hold",
+	"spi1", "spi2", "spi2_wp_hold", };
+static const char *const mt7988_flash_groups[] = { "emmc_45", "snfi",
+	"emmc_51" };
+static const char *const mt7988_uart_groups[] = { "uart2", "tops_uart0_0",
+	"uart2_0", "uart1_0", "uart2_1",
+	"net_wo0_uart_txd_0", "net_wo1_uart_txd_0", "net_wo2_uart_txd_0",
+	"tops_uart1_0", "ops_uart0_1", "ops_uart1_1",
+	"uart0", "tops_uart0_2", "uart1_1",
+	"uart2_3", "uart1_2", "tops_uart1_2",
+	"net_wo0_uart_txd_1", "net_wo1_uart_txd_1", "net_wo2_uart_txd_1", };
+static const char *const mt7988_udi_groups[] = { "udi", };
+static const char *const mt7988_pcm_groups[] = { "pcm", };
+static const char *const mt7988_led_groups[] = { "gbe_led1", "2p5gbe_led1",
+	"gbe_led0", "2p5gbe_led0", "wf5g_led0", "wf5g_led1", };
+static const char *const mt7988_usb_groups[] = { "drv_vbus", "drv_vbus_p1", };
+
+static const struct mtk_function_desc mt7988_functions[] = {
+	{"jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups)},
+	{"int_usxgmii", mt7988_int_usxgmii_groups,
+			ARRAY_SIZE(mt7988_int_usxgmii_groups)},
+	{"pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups)},
+	{"dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups)},
+	{"i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups)},
+	{"eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups)},
+	{"pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups)},
+	{"pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups)},
+	{"watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups)},
+	{"spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups)},
+	{"flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups)},
+	{"uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups)},
+	{"udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups)},
+	{"pcm", mt7988_pcm_groups, ARRAY_SIZE(mt7988_pcm_groups)},
+	{"usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups)},
+	{"led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups)},
+};
+
+static const char *const mt7988_pinctrl_register_base_names[] = {
+	"gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base",
+	"iocfg_lb_base", "iocfg_tl_base",
+};
+
+static const struct mtk_pinctrl_soc mt7988_data = {
+	.name = "mt7988_pinctrl",
+	.reg_cal = mt7988_reg_cals,
+	.pins = mt7988_pins,
+	.npins = ARRAY_SIZE(mt7988_pins),
+	.grps = mt7988_groups,
+	.ngrps = ARRAY_SIZE(mt7988_groups),
+	.funcs = mt7988_functions,
+	.nfuncs = ARRAY_SIZE(mt7988_functions),
+	.io_type = mt7988_io_type_desc,
+	.ntype = ARRAY_SIZE(mt7988_io_type_desc),
+	.gpio_mode = 0,
+	.base_names = mt7988_pinctrl_register_base_names,
+	.nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
+	.base_calc = 1,
+};
+
+static int mtk_pinctrl_mt7988_probe(struct udevice *dev)
+{
+	return mtk_pinctrl_common_probe(dev, &mt7988_data);
+}
+
+static const struct udevice_id mt7988_pctrl_match[] = {
+	{.compatible = "mediatek,mt7988-pinctrl"},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt7988_pinctrl) = {
+	.name = "mt7988_pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = mt7988_pctrl_match,
+	.ops = &mtk_pinctrl_ops,
+	.probe = mtk_pinctrl_mt7988_probe,
+	.priv_auto = sizeof(struct mtk_pinctrl_priv),
+};
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8512.c b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
index 3d9c0abe36..bc5fb83ac6 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8512.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
@@ -315,12 +315,12 @@ static const struct mtk_pin_desc mt8512_pins[] = {
  */
 
 /* UART */
-static int mt8512_uart0_0_rxd_txd_pins[]		= { 52, 53, };
-static int mt8512_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
-static int mt8512_uart1_0_rxd_txd_pins[]		= { 54, 55, };
-static int mt8512_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
-static int mt8512_uart2_0_rxd_txd_pins[]		= { 28, 29, };
-static int mt8512_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
+static const int mt8512_uart0_0_rxd_txd_pins[]		= { 52, 53, };
+static const int mt8512_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
+static const int mt8512_uart1_0_rxd_txd_pins[]		= { 54, 55, };
+static const int mt8512_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
+static const int mt8512_uart2_0_rxd_txd_pins[]		= { 28, 29, };
+static const int mt8512_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
 
 /* Joint those groups owning the same capability in user point of view which
  * allows that people tend to use through the device tree.
@@ -330,13 +330,13 @@ static const char *const mt8512_uart_groups[] = { "uart0_0_rxd_txd",
 						"uart2_0_rxd_txd", };
 
 /* SNAND */
-static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, };
-static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
+static const int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, };
+static const int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
 
 /* MMC0 */
-static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84,
-				   85, 86, };
-static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84,
+					 85, 86, };
+static const int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
 
 static const struct mtk_group_desc mt8512_groups[] = {
 	PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd),
@@ -356,7 +356,7 @@ static const struct mtk_function_desc mt8512_functions[] = {
 	{"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)},
 };
 
-static struct mtk_pinctrl_soc mt8512_data = {
+static const struct mtk_pinctrl_soc mt8512_data = {
 	.name = "mt8512_pinctrl",
 	.reg_cal = mt8512_reg_cals,
 	.pins = mt8512_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
index 6f94f762d9..7487d6f060 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
@@ -326,12 +326,12 @@ static const struct mtk_pin_desc mt8516_pins[] = {
  */
 
 /* UART */
-static int mt8516_uart0_0_rxd_txd_pins[]		= { 62, 63, };
-static int mt8516_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
-static int mt8516_uart1_0_rxd_txd_pins[]		= { 64, 65, };
-static int mt8516_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
-static int mt8516_uart2_0_rxd_txd_pins[]		= { 34, 35, };
-static int mt8516_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
+static const int mt8516_uart0_0_rxd_txd_pins[]		= { 62, 63, };
+static const int mt8516_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
+static const int mt8516_uart1_0_rxd_txd_pins[]		= { 64, 65, };
+static const int mt8516_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
+static const int mt8516_uart2_0_rxd_txd_pins[]		= { 34, 35, };
+static const int mt8516_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
 
 /* Joint those groups owning the same capability in user point of view which
  * allows that people tend to use through the device tree.
@@ -341,9 +341,9 @@ static const char *const mt8516_uart_groups[] = { "uart0_0_rxd_txd",
 						"uart2_0_rxd_txd", };
 
 /* MMC0 */
-static int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, 118,
-				   119, 120, };
-static int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117,
+					 118, 119, 120, };
+static const int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
 
 static const struct mtk_group_desc mt8516_groups[] = {
 	PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8516_uart0_0_rxd_txd),
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8518.c b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
index ed51bd3bbc..66fcfdff14 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8518.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
@@ -346,12 +346,12 @@ static const struct mtk_pin_desc mt8518_pins[] = {
  */
 
 /* UART */
-static int mt8518_uart0_0_rxd_txd_pins[]		= { 104, 105, };
-static int mt8518_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
-static int mt8518_uart1_0_rxd_txd_pins[]		= { 52, 53, };
-static int mt8518_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
-static int mt8518_uart2_0_rxd_txd_pins[]		= { 106, 107, };
-static int mt8518_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
+static const int mt8518_uart0_0_rxd_txd_pins[]		= { 104, 105, };
+static const int mt8518_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
+static const int mt8518_uart1_0_rxd_txd_pins[]		= { 52, 53, };
+static const int mt8518_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
+static const int mt8518_uart2_0_rxd_txd_pins[]		= { 106, 107, };
+static const int mt8518_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
 
 /* Joint those groups owning the same capability in user point of view which
  * allows that people tend to use through the device tree.
@@ -361,9 +361,9 @@ static const char *const mt8518_uart_groups[] = { "uart0_0_rxd_txd",
 						"uart2_0_rxd_txd", };
 
 /* MMC0 */
-static int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11,
-				   12, 13, };
-static int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11,
+					 12, 13, };
+static const int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
 
 static const struct mtk_group_desc mt8518_groups[] = {
 	PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8518_uart0_0_rxd_txd),
@@ -380,7 +380,7 @@ static const struct mtk_function_desc mt8518_functions[] = {
 	{"msdc", mt8518_msdc_groups, ARRAY_SIZE(mt8518_msdc_groups)},
 };
 
-static struct mtk_pinctrl_soc mt8518_data = {
+static const struct mtk_pinctrl_soc mt8518_data = {
 	.name = "mt8518_pinctrl",
 	.reg_cal = mt8518_reg_cals,
 	.pins = mt8518_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 5a4d58b327..0baef57c1c 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -304,6 +304,19 @@ static const char *mtk_get_function_name(struct udevice *dev,
 	return priv->soc->funcs[selector].name;
 }
 
+static int mtk_pinmux_set(struct udevice *dev, unsigned int pin_selector,
+			  unsigned int func_selector)
+{
+	int err;
+
+	err = mtk_hw_set_value(dev, pin_selector, PINCTRL_PIN_REG_MODE,
+			       func_selector);
+	if (err)
+		return err;
+
+	return 0;
+}
+
 static int mtk_pinmux_group_set(struct udevice *dev,
 				unsigned int group_selector,
 				unsigned int func_selector)
@@ -314,7 +327,7 @@ static int mtk_pinmux_group_set(struct udevice *dev,
 	int i;
 
 	for (i = 0; i < grp->num_pins; i++) {
-		int *pin_modes = grp->data;
+		const int *pin_modes = grp->data;
 
 		mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE,
 				 pin_modes[i]);
@@ -513,7 +526,7 @@ int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg)
 			return err;
 	}
 
-	return 0;
+	return err;
 }
 
 int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
@@ -531,7 +544,7 @@ int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
 			return err;
 	}
 
-	return 0;
+	return err;
 }
 
 int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
@@ -647,6 +660,7 @@ const struct pinctrl_ops mtk_pinctrl_ops = {
 	.get_group_name = mtk_get_group_name,
 	.get_functions_count = mtk_get_functions_count,
 	.get_function_name = mtk_get_function_name,
+	.pinmux_set = mtk_pinmux_set,
 	.pinmux_group_set = mtk_pinmux_group_set,
 #if CONFIG_IS_ENABLED(PINCONF)
 	.pinconf_num_params = ARRAY_SIZE(mtk_conf_params),
@@ -769,7 +783,7 @@ static int mtk_gpiochip_register(struct udevice *parent)
 #endif
 
 int mtk_pinctrl_common_probe(struct udevice *dev,
-			     struct mtk_pinctrl_soc *soc)
+			     const struct mtk_pinctrl_soc *soc)
 {
 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
 	int ret = 0;
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 0d9596fa72..c948b80843 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -174,9 +174,9 @@ struct mtk_pin_desc {
  */
 struct mtk_group_desc {
 	const char *name;
-	int *pins;
+	const int *pins;
 	int num_pins;
-	void *data;
+	const void *data;
 };
 
 /**
@@ -233,7 +233,7 @@ struct mtk_pinctrl_soc {
  */
 struct mtk_pinctrl_priv {
 	void __iomem *base[MAX_BASE_CALC];
-	struct mtk_pinctrl_soc *soc;
+	const struct mtk_pinctrl_soc *soc;
 };
 
 extern const struct pinctrl_ops mtk_pinctrl_ops;
@@ -242,7 +242,7 @@ extern const struct pinctrl_ops mtk_pinctrl_ops;
 void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set);
 void mtk_i_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set);
 int mtk_pinctrl_common_probe(struct udevice *dev,
-			     struct mtk_pinctrl_soc *soc);
+			     const struct mtk_pinctrl_soc *soc);
 
 #if CONFIG_IS_ENABLED(PINCONF)
 
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index ef02087ed2..97e574330f 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -29,4 +29,8 @@ config PINCTRL_MESON_G12A
 	bool "Amlogic Meson G12a SoC pinctrl driver"
 	select PINCTRL_MESON_AXG_PMX
 
+config PINCTRL_MESON_A1
+	bool "Amlogic Meson A1 SoC pinctrl driver"
+	select PINCTRL_MESON_AXG_PMX
+
 endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 80dba65e1b..8d10d027ac 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB)	+= pinctrl-meson-gxbb.o
 obj-$(CONFIG_PINCTRL_MESON_GXL)		+= pinctrl-meson-gxl.o
 obj-$(CONFIG_PINCTRL_MESON_AXG)		+= pinctrl-meson-axg.o
 obj-$(CONFIG_PINCTRL_MESON_G12A)	+= pinctrl-meson-g12a.o
+obj-$(CONFIG_PINCTRL_MESON_A1)		+= pinctrl-meson-a1.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-a1.c b/drivers/pinctrl/meson/pinctrl-meson-a1.c
new file mode 100644
index 0000000000..30cf3bc0be
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-a1.c
@@ -0,0 +1,867 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Qianggui Song <qianggui.song@amlogic.com>
+ * Copyright (C) 2023 SberDevices, Inc.
+ * Author: Igor Prusov <ivprusov@sberdevices.ru>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/gpio/meson-a1-gpio.h>
+
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg.h"
+
+/* psram */
+static const unsigned int psram_clkn_pins[]		= { GPIOP_0 };
+static const unsigned int psram_clkp_pins[]		= { GPIOP_1 };
+static const unsigned int psram_ce_n_pins[]		= { GPIOP_2 };
+static const unsigned int psram_rst_n_pins[]		= { GPIOP_3 };
+static const unsigned int psram_adq0_pins[]		= { GPIOP_4 };
+static const unsigned int psram_adq1_pins[]		= { GPIOP_5 };
+static const unsigned int psram_adq2_pins[]		= { GPIOP_6 };
+static const unsigned int psram_adq3_pins[]		= { GPIOP_7 };
+static const unsigned int psram_adq4_pins[]		= { GPIOP_8 };
+static const unsigned int psram_adq5_pins[]		= { GPIOP_9 };
+static const unsigned int psram_adq6_pins[]		= { GPIOP_10 };
+static const unsigned int psram_adq7_pins[]		= { GPIOP_11 };
+static const unsigned int psram_dqs_dm_pins[]		= { GPIOP_12 };
+
+/* sdcard */
+static const unsigned int sdcard_d0_b_pins[]		= { GPIOB_0 };
+static const unsigned int sdcard_d1_b_pins[]		= { GPIOB_1 };
+static const unsigned int sdcard_d2_b_pins[]		= { GPIOB_2 };
+static const unsigned int sdcard_d3_b_pins[]		= { GPIOB_3 };
+static const unsigned int sdcard_clk_b_pins[]		= { GPIOB_4 };
+static const unsigned int sdcard_cmd_b_pins[]		= { GPIOB_5 };
+
+static const unsigned int sdcard_d0_x_pins[]		= { GPIOX_0 };
+static const unsigned int sdcard_d1_x_pins[]		= { GPIOX_1 };
+static const unsigned int sdcard_d2_x_pins[]		= { GPIOX_2 };
+static const unsigned int sdcard_d3_x_pins[]		= { GPIOX_3 };
+static const unsigned int sdcard_clk_x_pins[]		= { GPIOX_4 };
+static const unsigned int sdcard_cmd_x_pins[]		= { GPIOX_5 };
+
+/* spif */
+static const unsigned int spif_mo_pins[]		= { GPIOB_0 };
+static const unsigned int spif_mi_pins[]		= { GPIOB_1 };
+static const unsigned int spif_wp_n_pins[]		= { GPIOB_2 };
+static const unsigned int spif_hold_n_pins[]		= { GPIOB_3 };
+static const unsigned int spif_clk_pins[]		= { GPIOB_4 };
+static const unsigned int spif_cs_pins[]		= { GPIOB_5 };
+
+/* i2c0 */
+static const unsigned int i2c0_sck_f9_pins[]		= { GPIOF_9 };
+static const unsigned int i2c0_sda_f10_pins[]		= { GPIOF_10 };
+static const unsigned int i2c0_sck_f11_pins[]		= { GPIOF_11 };
+static const unsigned int i2c0_sda_f12_pins[]		= { GPIOF_12 };
+
+/* i2c1 */
+static const unsigned int i2c1_sda_x_pins[]		= { GPIOX_9 };
+static const unsigned int i2c1_sck_x_pins[]		= { GPIOX_10 };
+static const unsigned int i2c1_sda_a_pins[]		= { GPIOA_10 };
+static const unsigned int i2c1_sck_a_pins[]		= { GPIOA_11 };
+
+/* i2c2 */
+static const unsigned int i2c2_sck_x0_pins[]		= { GPIOX_0 };
+static const unsigned int i2c2_sda_x1_pins[]		= { GPIOX_1 };
+static const unsigned int i2c2_sck_x15_pins[]		= { GPIOX_15 };
+static const unsigned int i2c2_sda_x16_pins[]		= { GPIOX_16 };
+static const unsigned int i2c2_sck_a4_pins[]		= { GPIOA_4 };
+static const unsigned int i2c2_sda_a5_pins[]		= { GPIOA_5 };
+static const unsigned int i2c2_sck_a8_pins[]		= { GPIOA_8 };
+static const unsigned int i2c2_sda_a9_pins[]		= { GPIOA_9 };
+
+/* i2c3 */
+static const unsigned int i2c3_sck_f_pins[]		= { GPIOF_4 };
+static const unsigned int i2c3_sda_f_pins[]		= { GPIOF_5 };
+static const unsigned int i2c3_sck_x_pins[]		= { GPIOX_11 };
+static const unsigned int i2c3_sda_x_pins[]		= { GPIOX_12 };
+
+/* i2c slave */
+static const unsigned int i2c_slave_sck_a_pins[]	= { GPIOA_10 };
+static const unsigned int i2c_slave_sda_a_pins[]	= { GPIOA_11 };
+static const unsigned int i2c_slave_sck_f_pins[]	= { GPIOF_11 };
+static const unsigned int i2c_slave_sda_f_pins[]	= { GPIOF_12 };
+
+/* uart_a */
+static const unsigned int uart_a_tx_pins[]		= { GPIOX_11 };
+static const unsigned int uart_a_rx_pins[]		= { GPIOX_12 };
+static const unsigned int uart_a_cts_pins[]		= { GPIOX_13 };
+static const unsigned int uart_a_rts_pins[]		= { GPIOX_14 };
+
+/* uart_b */
+static const unsigned int uart_b_tx_x_pins[]		= { GPIOX_7 };
+static const unsigned int uart_b_rx_x_pins[]		= { GPIOX_8 };
+static const unsigned int uart_b_tx_f_pins[]		= { GPIOF_0 };
+static const unsigned int uart_b_rx_f_pins[]		= { GPIOF_1 };
+
+/* uart_c */
+static const unsigned int uart_c_tx_x0_pins[]		= { GPIOX_0 };
+static const unsigned int uart_c_rx_x1_pins[]		= { GPIOX_1 };
+static const unsigned int uart_c_cts_pins[]		= { GPIOX_2 };
+static const unsigned int uart_c_rts_pins[]		= { GPIOX_3 };
+static const unsigned int uart_c_tx_x15_pins[]		= { GPIOX_15 };
+static const unsigned int uart_c_rx_x16_pins[]		= { GPIOX_16 };
+
+/* pmw_a */
+static const unsigned int pwm_a_x6_pins[]		= { GPIOX_6 };
+static const unsigned int pwm_a_x7_pins[]		= { GPIOX_7 };
+static const unsigned int pwm_a_f6_pins[]		= { GPIOF_6 };
+static const unsigned int pwm_a_f10_pins[]		= { GPIOF_10 };
+static const unsigned int pwm_a_a_pins[]		= { GPIOA_5 };
+
+/* pmw_b */
+static const unsigned int pwm_b_x_pins[]		= { GPIOX_8 };
+static const unsigned int pwm_b_f_pins[]		= { GPIOF_7 };
+static const unsigned int pwm_b_a_pins[]		= { GPIOA_11 };
+
+/* pmw_c */
+static const unsigned int pwm_c_x_pins[]		= { GPIOX_9 };
+static const unsigned int pwm_c_f3_pins[]		= { GPIOF_3 };
+static const unsigned int pwm_c_f8_pins[]		= { GPIOF_8 };
+static const unsigned int pwm_c_a_pins[]		= { GPIOA_10 };
+
+/* pwm_d */
+static const unsigned int pwm_d_x10_pins[]		= { GPIOX_10 };
+static const unsigned int pwm_d_x13_pins[]		= { GPIOX_13 };
+static const unsigned int pwm_d_x15_pins[]		= { GPIOX_15 };
+static const unsigned int pwm_d_f_pins[]		= { GPIOF_11 };
+
+/* pwm_e */
+static const unsigned int pwm_e_p_pins[]		= { GPIOP_3 };
+static const unsigned int pwm_e_x2_pins[]		= { GPIOX_2 };
+static const unsigned int pwm_e_x14_pins[]		= { GPIOX_14 };
+static const unsigned int pwm_e_x16_pins[]		= { GPIOX_16 };
+static const unsigned int pwm_e_f_pins[]		= { GPIOF_3 };
+static const unsigned int pwm_e_a_pins[]		= { GPIOA_0 };
+
+/* pwm_f */
+static const unsigned int pwm_f_b_pins[]		= { GPIOB_6 };
+static const unsigned int pwm_f_x_pins[]		= { GPIOX_3 };
+static const unsigned int pwm_f_f4_pins[]		= { GPIOF_4 };
+static const unsigned int pwm_f_f12_pins[]		= { GPIOF_12 };
+
+/* pwm_a_hiz */
+static const unsigned int pwm_a_hiz_f8_pins[]		= { GPIOF_8 };
+static const unsigned int pwm_a_hiz_f10_pins[]		= { GPIOF_10 };
+static const unsigned int pmw_a_hiz_f6_pins[]		= { GPIOF_6 };
+
+/* pwm_b_hiz */
+static const unsigned int pwm_b_hiz_pins[]		= { GPIOF_7 };
+
+/* pmw_c_hiz */
+static const unsigned int pwm_c_hiz_pins[]		= { GPIOF_8 };
+
+/* tdm_a */
+static const unsigned int tdm_a_dout1_pins[]		= { GPIOX_7 };
+static const unsigned int tdm_a_dout0_pins[]		= { GPIOX_8 };
+static const unsigned int tdm_a_fs_pins[]		= { GPIOX_9 };
+static const unsigned int tdm_a_sclk_pins[]		= { GPIOX_10 };
+static const unsigned int tdm_a_din1_pins[]		= { GPIOX_7 };
+static const unsigned int tdm_a_din0_pins[]		= { GPIOX_8 };
+static const unsigned int tdm_a_slv_fs_pins[]		= { GPIOX_9 };
+static const unsigned int tdm_a_slv_sclk_pins[]		= { GPIOX_10 };
+
+/* spi_a */
+static const unsigned int spi_a_mosi_x2_pins[]		= { GPIOX_2 };
+static const unsigned int spi_a_ss0_x3_pins[]		= { GPIOX_3 };
+static const unsigned int spi_a_sclk_x4_pins[]		= { GPIOX_4 };
+static const unsigned int spi_a_miso_x5_pins[]		= { GPIOX_5 };
+static const unsigned int spi_a_mosi_x7_pins[]		= { GPIOX_7 };
+static const unsigned int spi_a_miso_x8_pins[]		= { GPIOX_8 };
+static const unsigned int spi_a_ss0_x9_pins[]		= { GPIOX_9 };
+static const unsigned int spi_a_sclk_x10_pins[]		= { GPIOX_10 };
+
+static const unsigned int spi_a_mosi_a_pins[]		= { GPIOA_6 };
+static const unsigned int spi_a_miso_a_pins[]		= { GPIOA_7 };
+static const unsigned int spi_a_ss0_a_pins[]		= { GPIOA_8 };
+static const unsigned int spi_a_sclk_a_pins[]		= { GPIOA_9 };
+
+/* pdm */
+static const unsigned int pdm_din0_x_pins[]		= { GPIOX_7 };
+static const unsigned int pdm_din1_x_pins[]		= { GPIOX_8 };
+static const unsigned int pdm_din2_x_pins[]		= { GPIOX_9 };
+static const unsigned int pdm_dclk_x_pins[]		= { GPIOX_10 };
+
+static const unsigned int pdm_din2_a_pins[]		= { GPIOA_6 };
+static const unsigned int pdm_din1_a_pins[]		= { GPIOA_7 };
+static const unsigned int pdm_din0_a_pins[]		= { GPIOA_8 };
+static const unsigned int pdm_dclk_pins[]		= { GPIOA_9 };
+
+/* gen_clk */
+static const unsigned int gen_clk_x_pins[]		= { GPIOX_7 };
+static const unsigned int gen_clk_f8_pins[]		= { GPIOF_8 };
+static const unsigned int gen_clk_f10_pins[]		= { GPIOF_10 };
+static const unsigned int gen_clk_a_pins[]		= { GPIOA_11 };
+
+/* jtag_a */
+static const unsigned int jtag_a_clk_pins[]		= { GPIOF_4 };
+static const unsigned int jtag_a_tms_pins[]		= { GPIOF_5 };
+static const unsigned int jtag_a_tdi_pins[]		= { GPIOF_6 };
+static const unsigned int jtag_a_tdo_pins[]		= { GPIOF_7 };
+
+/* clk_32_in */
+static const unsigned int clk_32k_in_pins[]		= { GPIOF_2 };
+
+/* ir in */
+static const unsigned int remote_input_f_pins[]		= { GPIOF_3 };
+static const unsigned int remote_input_a_pins[]		= { GPIOA_11 };
+
+/* ir out */
+static const unsigned int remote_out_pins[]		= { GPIOF_5 };
+
+/* spdif */
+static const unsigned int spdif_in_f6_pins[]		= { GPIOF_6 };
+static const unsigned int spdif_in_f7_pins[]		= { GPIOF_7 };
+
+/* sw */
+static const unsigned int swclk_pins[]			= { GPIOF_4 };
+static const unsigned int swdio_pins[]			= { GPIOF_5 };
+
+/* clk_25 */
+static const unsigned int clk25_pins[]			= { GPIOF_10 };
+
+/* cec_a */
+static const unsigned int cec_a_pins[]			= { GPIOF_2 };
+
+/* cec_b */
+static const unsigned int cec_b_pins[]			= { GPIOF_2 };
+
+/* clk12_24 */
+static const unsigned int clk12_24_pins[]		= { GPIOF_10 };
+
+/* mclk_0 */
+static const unsigned int mclk_0_pins[]			= { GPIOA_0 };
+
+/* tdm_b */
+static const unsigned int tdm_b_sclk_pins[]		= { GPIOA_1 };
+static const unsigned int tdm_b_fs_pins[]		= { GPIOA_2 };
+static const unsigned int tdm_b_dout0_pins[]		= { GPIOA_3 };
+static const unsigned int tdm_b_dout1_pins[]		= { GPIOA_4 };
+static const unsigned int tdm_b_dout2_pins[]		= { GPIOA_5 };
+static const unsigned int tdm_b_dout3_pins[]		= { GPIOA_6 };
+static const unsigned int tdm_b_dout4_pins[]		= { GPIOA_7 };
+static const unsigned int tdm_b_dout5_pins[]		= { GPIOA_8 };
+static const unsigned int tdm_b_slv_sclk_pins[]		= { GPIOA_5 };
+static const unsigned int tdm_b_slv_fs_pins[]		= { GPIOA_6 };
+static const unsigned int tdm_b_din0_pins[]		= { GPIOA_7 };
+static const unsigned int tdm_b_din1_pins[]		= { GPIOA_8 };
+static const unsigned int tdm_b_din2_pins[]		= { GPIOA_9 };
+
+/* mclk_vad */
+static const unsigned int mclk_vad_pins[]		= { GPIOA_0 };
+
+/* tdm_vad */
+static const unsigned int tdm_vad_sclk_a1_pins[]	= { GPIOA_1 };
+static const unsigned int tdm_vad_fs_a2_pins[]		= { GPIOA_2 };
+static const unsigned int tdm_vad_sclk_a5_pins[]	= { GPIOA_5 };
+static const unsigned int tdm_vad_fs_a6_pins[]		= { GPIOA_6 };
+
+/* tst_out */
+static const unsigned int tst_out0_pins[]		= { GPIOA_0 };
+static const unsigned int tst_out1_pins[]		= { GPIOA_1 };
+static const unsigned int tst_out2_pins[]		= { GPIOA_2 };
+static const unsigned int tst_out3_pins[]		= { GPIOA_3 };
+static const unsigned int tst_out4_pins[]		= { GPIOA_4 };
+static const unsigned int tst_out5_pins[]		= { GPIOA_5 };
+static const unsigned int tst_out6_pins[]		= { GPIOA_6 };
+static const unsigned int tst_out7_pins[]		= { GPIOA_7 };
+static const unsigned int tst_out8_pins[]		= { GPIOA_8 };
+static const unsigned int tst_out9_pins[]		= { GPIOA_9 };
+static const unsigned int tst_out10_pins[]		= { GPIOA_10 };
+static const unsigned int tst_out11_pins[]		= { GPIOA_11 };
+
+/* mute */
+static const unsigned int mute_key_pins[]		= { GPIOA_4 };
+static const unsigned int mute_en_pins[]		= { GPIOA_5 };
+
+static struct meson_pmx_group meson_a1_periphs_groups[] = {
+	GPIO_GROUP(GPIOP_0, 0),
+	GPIO_GROUP(GPIOP_1, 0),
+	GPIO_GROUP(GPIOP_2, 0),
+	GPIO_GROUP(GPIOP_3, 0),
+	GPIO_GROUP(GPIOP_4, 0),
+	GPIO_GROUP(GPIOP_5, 0),
+	GPIO_GROUP(GPIOP_6, 0),
+	GPIO_GROUP(GPIOP_7, 0),
+	GPIO_GROUP(GPIOP_8, 0),
+	GPIO_GROUP(GPIOP_9, 0),
+	GPIO_GROUP(GPIOP_10, 0),
+	GPIO_GROUP(GPIOP_11, 0),
+	GPIO_GROUP(GPIOP_12, 0),
+	GPIO_GROUP(GPIOB_0, 0),
+	GPIO_GROUP(GPIOB_1, 0),
+	GPIO_GROUP(GPIOB_2, 0),
+	GPIO_GROUP(GPIOB_3, 0),
+	GPIO_GROUP(GPIOB_4, 0),
+	GPIO_GROUP(GPIOB_5, 0),
+	GPIO_GROUP(GPIOB_6, 0),
+	GPIO_GROUP(GPIOX_0, 0),
+	GPIO_GROUP(GPIOX_1, 0),
+	GPIO_GROUP(GPIOX_2, 0),
+	GPIO_GROUP(GPIOX_3, 0),
+	GPIO_GROUP(GPIOX_4, 0),
+	GPIO_GROUP(GPIOX_5, 0),
+	GPIO_GROUP(GPIOX_6, 0),
+	GPIO_GROUP(GPIOX_7, 0),
+	GPIO_GROUP(GPIOX_8, 0),
+	GPIO_GROUP(GPIOX_9, 0),
+	GPIO_GROUP(GPIOX_10, 0),
+	GPIO_GROUP(GPIOX_11, 0),
+	GPIO_GROUP(GPIOX_12, 0),
+	GPIO_GROUP(GPIOX_13, 0),
+	GPIO_GROUP(GPIOX_14, 0),
+	GPIO_GROUP(GPIOX_15, 0),
+	GPIO_GROUP(GPIOX_16, 0),
+	GPIO_GROUP(GPIOF_0, 0),
+	GPIO_GROUP(GPIOF_1, 0),
+	GPIO_GROUP(GPIOF_2, 0),
+	GPIO_GROUP(GPIOF_3, 0),
+	GPIO_GROUP(GPIOF_4, 0),
+	GPIO_GROUP(GPIOF_5, 0),
+	GPIO_GROUP(GPIOF_6, 0),
+	GPIO_GROUP(GPIOF_7, 0),
+	GPIO_GROUP(GPIOF_8, 0),
+	GPIO_GROUP(GPIOF_9, 0),
+	GPIO_GROUP(GPIOF_10, 0),
+	GPIO_GROUP(GPIOF_11, 0),
+	GPIO_GROUP(GPIOF_12, 0),
+	GPIO_GROUP(GPIOA_0, 0),
+	GPIO_GROUP(GPIOA_1, 0),
+	GPIO_GROUP(GPIOA_2, 0),
+	GPIO_GROUP(GPIOA_3, 0),
+	GPIO_GROUP(GPIOA_4, 0),
+	GPIO_GROUP(GPIOA_5, 0),
+	GPIO_GROUP(GPIOA_6, 0),
+	GPIO_GROUP(GPIOA_7, 0),
+	GPIO_GROUP(GPIOA_8, 0),
+	GPIO_GROUP(GPIOA_9, 0),
+	GPIO_GROUP(GPIOA_10, 0),
+	GPIO_GROUP(GPIOA_11, 0),
+
+	/* bank P func1 */
+	GROUP(psram_clkn,		1),
+	GROUP(psram_clkp,		1),
+	GROUP(psram_ce_n,		1),
+	GROUP(psram_rst_n,		1),
+	GROUP(psram_adq0,		1),
+	GROUP(psram_adq1,		1),
+	GROUP(psram_adq2,		1),
+	GROUP(psram_adq3,		1),
+	GROUP(psram_adq4,		1),
+	GROUP(psram_adq5,		1),
+	GROUP(psram_adq6,		1),
+	GROUP(psram_adq7,		1),
+	GROUP(psram_dqs_dm,		1),
+
+	/* bank P func2 */
+	GROUP(pwm_e_p,			2),
+
+	/* bank B func1 */
+	GROUP(spif_mo,			1),
+	GROUP(spif_mi,			1),
+	GROUP(spif_wp_n,		1),
+	GROUP(spif_hold_n,		1),
+	GROUP(spif_clk,			1),
+	GROUP(spif_cs,			1),
+	GROUP(pwm_f_b,			1),
+
+	/* bank B func2 */
+	GROUP(sdcard_d0_b,		2),
+	GROUP(sdcard_d1_b,		2),
+	GROUP(sdcard_d2_b,		2),
+	GROUP(sdcard_d3_b,		2),
+	GROUP(sdcard_clk_b,		2),
+	GROUP(sdcard_cmd_b,		2),
+
+	/* bank X func1 */
+	GROUP(sdcard_d0_x,		1),
+	GROUP(sdcard_d1_x,		1),
+	GROUP(sdcard_d2_x,		1),
+	GROUP(sdcard_d3_x,		1),
+	GROUP(sdcard_clk_x,		1),
+	GROUP(sdcard_cmd_x,		1),
+	GROUP(pwm_a_x6,			1),
+	GROUP(tdm_a_dout1,		1),
+	GROUP(tdm_a_dout0,		1),
+	GROUP(tdm_a_fs,			1),
+	GROUP(tdm_a_sclk,		1),
+	GROUP(uart_a_tx,		1),
+	GROUP(uart_a_rx,		1),
+	GROUP(uart_a_cts,		1),
+	GROUP(uart_a_rts,		1),
+	GROUP(pwm_d_x15,		1),
+	GROUP(pwm_e_x16,		1),
+
+	/* bank X func2 */
+	GROUP(i2c2_sck_x0,		2),
+	GROUP(i2c2_sda_x1,		2),
+	GROUP(spi_a_mosi_x2,		2),
+	GROUP(spi_a_ss0_x3,		2),
+	GROUP(spi_a_sclk_x4,		2),
+	GROUP(spi_a_miso_x5,		2),
+	GROUP(tdm_a_din1,		2),
+	GROUP(tdm_a_din0,		2),
+	GROUP(tdm_a_slv_fs,		2),
+	GROUP(tdm_a_slv_sclk,		2),
+	GROUP(i2c3_sck_x,		2),
+	GROUP(i2c3_sda_x,		2),
+	GROUP(pwm_d_x13,		2),
+	GROUP(pwm_e_x14,		2),
+	GROUP(i2c2_sck_x15,		2),
+	GROUP(i2c2_sda_x16,		2),
+
+	/* bank X func3 */
+	GROUP(uart_c_tx_x0,		3),
+	GROUP(uart_c_rx_x1,		3),
+	GROUP(uart_c_cts,		3),
+	GROUP(uart_c_rts,		3),
+	GROUP(pdm_din0_x,		3),
+	GROUP(pdm_din1_x,		3),
+	GROUP(pdm_din2_x,		3),
+	GROUP(pdm_dclk_x,		3),
+	GROUP(uart_c_tx_x15,		3),
+	GROUP(uart_c_rx_x16,		3),
+
+	/* bank X func4 */
+	GROUP(pwm_e_x2,			4),
+	GROUP(pwm_f_x,			4),
+	GROUP(spi_a_mosi_x7,		4),
+	GROUP(spi_a_miso_x8,		4),
+	GROUP(spi_a_ss0_x9,		4),
+	GROUP(spi_a_sclk_x10,		4),
+
+	/* bank X func5 */
+	GROUP(uart_b_tx_x,		5),
+	GROUP(uart_b_rx_x,		5),
+	GROUP(i2c1_sda_x,		5),
+	GROUP(i2c1_sck_x,		5),
+
+	/* bank X func6 */
+	GROUP(pwm_a_x7,			6),
+	GROUP(pwm_b_x,			6),
+	GROUP(pwm_c_x,			6),
+	GROUP(pwm_d_x10,		6),
+
+	/* bank X func7 */
+	GROUP(gen_clk_x,		7),
+
+	/* bank F func1 */
+	GROUP(uart_b_tx_f,		1),
+	GROUP(uart_b_rx_f,		1),
+	GROUP(remote_input_f,		1),
+	GROUP(jtag_a_clk,		1),
+	GROUP(jtag_a_tms,		1),
+	GROUP(jtag_a_tdi,		1),
+	GROUP(jtag_a_tdo,		1),
+	GROUP(gen_clk_f8,		1),
+	GROUP(pwm_a_f10,		1),
+	GROUP(i2c0_sck_f11,		1),
+	GROUP(i2c0_sda_f12,		1),
+
+	/* bank F func2 */
+	GROUP(clk_32k_in,		2),
+	GROUP(pwm_e_f,			2),
+	GROUP(pwm_f_f4,			2),
+	GROUP(remote_out,		2),
+	GROUP(spdif_in_f6,		2),
+	GROUP(spdif_in_f7,		2),
+	GROUP(pwm_a_hiz_f8,		2),
+	GROUP(pwm_a_hiz_f10,		2),
+	GROUP(pwm_d_f,			2),
+	GROUP(pwm_f_f12,		2),
+
+	/* bank F func3 */
+	GROUP(pwm_c_f3,			3),
+	GROUP(swclk,			3),
+	GROUP(swdio,			3),
+	GROUP(pwm_a_f6,			3),
+	GROUP(pwm_b_f,			3),
+	GROUP(pwm_c_f8,			3),
+	GROUP(clk25,			3),
+	GROUP(i2c_slave_sck_f,		3),
+	GROUP(i2c_slave_sda_f,		3),
+
+	/* bank F func4 */
+	GROUP(cec_a,			4),
+	GROUP(i2c3_sck_f,		4),
+	GROUP(i2c3_sda_f,		4),
+	GROUP(pmw_a_hiz_f6,		4),
+	GROUP(pwm_b_hiz,		4),
+	GROUP(pwm_c_hiz,		4),
+	GROUP(i2c0_sck_f9,		4),
+	GROUP(i2c0_sda_f10,		4),
+
+	/* bank F func5 */
+	GROUP(cec_b,			5),
+	GROUP(clk12_24,			5),
+
+	/* bank F func7 */
+	GROUP(gen_clk_f10,		7),
+
+	/* bank A func1 */
+	GROUP(mclk_0,			1),
+	GROUP(tdm_b_sclk,		1),
+	GROUP(tdm_b_fs,			1),
+	GROUP(tdm_b_dout0,		1),
+	GROUP(tdm_b_dout1,		1),
+	GROUP(tdm_b_dout2,		1),
+	GROUP(tdm_b_dout3,		1),
+	GROUP(tdm_b_dout4,		1),
+	GROUP(tdm_b_dout5,		1),
+	GROUP(remote_input_a,		1),
+
+	/* bank A func2 */
+	GROUP(pwm_e_a,			2),
+	GROUP(tdm_b_slv_sclk,		2),
+	GROUP(tdm_b_slv_fs,		2),
+	GROUP(tdm_b_din0,		2),
+	GROUP(tdm_b_din1,		2),
+	GROUP(tdm_b_din2,		2),
+	GROUP(i2c1_sda_a,		2),
+	GROUP(i2c1_sck_a,		2),
+
+	/* bank A func3 */
+	GROUP(i2c2_sck_a4,		3),
+	GROUP(i2c2_sda_a5,		3),
+	GROUP(pdm_din2_a,		3),
+	GROUP(pdm_din1_a,		3),
+	GROUP(pdm_din0_a,		3),
+	GROUP(pdm_dclk,			3),
+	GROUP(pwm_c_a,			3),
+	GROUP(pwm_b_a,			3),
+
+	/* bank A func4 */
+	GROUP(pwm_a_a,			4),
+	GROUP(spi_a_mosi_a,		4),
+	GROUP(spi_a_miso_a,		4),
+	GROUP(spi_a_ss0_a,		4),
+	GROUP(spi_a_sclk_a,		4),
+	GROUP(i2c_slave_sck_a,		4),
+	GROUP(i2c_slave_sda_a,		4),
+
+	/* bank A func5 */
+	GROUP(mclk_vad,			5),
+	GROUP(tdm_vad_sclk_a1,		5),
+	GROUP(tdm_vad_fs_a2,		5),
+	GROUP(tdm_vad_sclk_a5,		5),
+	GROUP(tdm_vad_fs_a6,		5),
+	GROUP(i2c2_sck_a8,		5),
+	GROUP(i2c2_sda_a9,		5),
+
+	/* bank A func6 */
+	GROUP(tst_out0,			6),
+	GROUP(tst_out1,			6),
+	GROUP(tst_out2,			6),
+	GROUP(tst_out3,			6),
+	GROUP(tst_out4,			6),
+	GROUP(tst_out5,			6),
+	GROUP(tst_out6,			6),
+	GROUP(tst_out7,			6),
+	GROUP(tst_out8,			6),
+	GROUP(tst_out9,			6),
+	GROUP(tst_out10,		6),
+	GROUP(tst_out11,		6),
+
+	/* bank A func7 */
+	GROUP(mute_key,			7),
+	GROUP(mute_en,			7),
+	GROUP(gen_clk_a,		7),
+};
+
+static const char * const gpio_periphs_groups[] = {
+	"GPIOP_0", "GPIOP_1", "GPIOP_2", "GPIOP_3", "GPIOP_4",
+	"GPIOP_5", "GPIOP_6", "GPIOP_7", "GPIOP_8", "GPIOP_9",
+	"GPIOP_10", "GPIOP_11", "GPIOP_12",
+
+	"GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4",
+	"GPIOB_5", "GPIOB_6",
+
+	"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+	"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+	"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
+	"GPIOX_15", "GPIOX_16",
+
+	"GPIOF_0", "GPIOF_1", "GPIOF_2", "GPIOF_3", "GPIOF_4",
+	"GPIOF_5", "GPIOF_6", "GPIOF_7", "GPIOF_8", "GPIOF_9",
+	"GPIOF_10", "GPIOF_11", "GPIOF_12",
+
+	"GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
+	"GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
+	"GPIOA_10", "GPIOA_11",
+};
+
+static const char * const psram_groups[] = {
+	"psram_clkn", "psram_clkp", "psram_ce_n", "psram_rst_n", "psram_adq0",
+	"psram_adq1", "psram_adq2", "psram_adq3", "psram_adq4", "psram_adq5",
+	"psram_adq6", "psram_adq7", "psram_dqs_dm",
+};
+
+static const char * const pwm_a_groups[] = {
+	"pwm_a_x6", "pwm_a_x7", "pwm_a_f10", "pwm_a_f6", "pwm_a_a",
+};
+
+static const char * const pwm_b_groups[] = {
+	"pwm_b_x", "pwm_b_f", "pwm_b_a",
+};
+
+static const char * const pwm_c_groups[] = {
+	"pwm_c_x", "pwm_c_f3", "pwm_c_f8", "pwm_c_a",
+};
+
+static const char * const pwm_d_groups[] = {
+	"pwm_d_x15", "pwm_d_x13", "pwm_d_x10", "pwm_d_f",
+};
+
+static const char * const pwm_e_groups[] = {
+	"pwm_e_p", "pwm_e_x16", "pwm_e_x14", "pwm_e_x2", "pwm_e_f",
+	"pwm_e_a",
+};
+
+static const char * const pwm_f_groups[] = {
+	"pwm_f_b", "pwm_f_x", "pwm_f_f4", "pwm_f_f12",
+};
+
+static const char * const pwm_a_hiz_groups[] = {
+	"pwm_a_hiz_f8", "pwm_a_hiz_f10", "pwm_a_hiz_f6",
+};
+
+static const char * const pwm_b_hiz_groups[] = {
+	"pwm_b_hiz",
+};
+
+static const char * const pwm_c_hiz_groups[] = {
+	"pwm_c_hiz",
+};
+
+static const char * const spif_groups[] = {
+	"spif_mo", "spif_mi", "spif_wp_n", "spif_hold_n", "spif_clk",
+	"spif_cs",
+};
+
+static const char * const sdcard_groups[] = {
+	"sdcard_d0_b", "sdcard_d1_b", "sdcard_d2_b", "sdcard_d3_b",
+	"sdcard_clk_b", "sdcard_cmd_b",
+
+	"sdcard_d0_x", "sdcard_d1_x", "sdcard_d2_x", "sdcard_d3_x",
+	"sdcard_clk_x", "sdcard_cmd_x",
+};
+
+static const char * const tdm_a_groups[] = {
+	"tdm_a_din0", "tdm_a_din1",  "tdm_a_fs", "tdm_a_sclk",
+	"tdm_a_slv_fs", "tdm_a_slv_sclk", "tdm_a_dout0", "tdm_a_dout1",
+};
+
+static const char * const uart_a_groups[] = {
+	"uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts",
+};
+
+static const char * const uart_b_groups[] = {
+	"uart_b_tx_x", "uart_b_rx_x", "uart_b_tx_f", "uart_b_rx_f",
+};
+
+static const char * const uart_c_groups[] = {
+	"uart_c_tx_x0", "uart_c_rx_x1", "uart_c_cts", "uart_c_rts",
+	"uart_c_tx_x15", "uart_c_rx_x16",
+};
+
+static const char * const i2c0_groups[] = {
+	"i2c0_sck_f11", "i2c0_sda_f12", "i2c0_sck_f9", "i2c0_sda_f10",
+};
+
+static const char * const i2c1_groups[] = {
+	"i2c1_sda_x", "i2c1_sck_x", "i2c1_sda_a", "i2c1_sck_a",
+};
+
+static const char * const i2c2_groups[] = {
+	"i2c2_sck_x0", "i2c2_sda_x1", "i2c2_sck_x15", "i2c2_sda_x16",
+	"i2c2_sck_a4", "i2c2_sda_a5", "i2c2_sck_a8", "i2c2_sda_a9",
+};
+
+static const char * const i2c3_groups[] = {
+	"i2c3_sck_x", "i2c3_sda_x", "i2c3_sck_f", "i2c3_sda_f",
+};
+
+static const char * const spi_a_groups[] = {
+	"spi_a_mosi_x2", "spi_a_ss0_x3", "spi_a_sclk_x4", "spi_a_miso_x5",
+	"spi_a_mosi_x7", "spi_a_miso_x8", "spi_a_ss0_x9", "spi_a_sclk_x10",
+
+	"spi_a_mosi_a", "spi_a_miso_a", "spi_a_ss0_a", "spi_a_sclk_a",
+};
+
+static const char * const pdm_groups[] = {
+	"pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_dclk_x", "pdm_din2_a",
+	"pdm_din1_a", "pdm_din0_a", "pdm_dclk",
+};
+
+static const char * const gen_clk_groups[] = {
+	"gen_clk_x", "gen_clk_f8", "gen_clk_f10", "gen_clk_a",
+};
+
+static const char * const remote_input_groups[] = {
+	"remote_input_f",
+	"remote_input_a",
+};
+
+static const char * const jtag_a_groups[] = {
+	"jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo",
+};
+
+static const char * const clk_32k_in_groups[] = {
+	"clk_32k_in",
+};
+
+static const char * const remote_out_groups[] = {
+	"remote_out",
+};
+
+static const char * const spdif_in_groups[] = {
+	"spdif_in_f6", "spdif_in_f7",
+};
+
+static const char * const sw_groups[] = {
+	"swclk", "swdio",
+};
+
+static const char * const clk25_groups[] = {
+	"clk_25",
+};
+
+static const char * const cec_a_groups[] = {
+	"cec_a",
+};
+
+static const char * const cec_b_groups[] = {
+	"cec_b",
+};
+
+static const char * const clk12_24_groups[] = {
+	"clk12_24",
+};
+
+static const char * const mclk_0_groups[] = {
+	"mclk_0",
+};
+
+static const char * const tdm_b_groups[] = {
+	"tdm_b_din0", "tdm_b_din1", "tdm_b_din2",
+	"tdm_b_sclk", "tdm_b_fs", "tdm_b_dout0", "tdm_b_dout1",
+	"tdm_b_dout2", "tdm_b_dout3", "tdm_b_dout4", "tdm_b_dout5",
+	"tdm_b_slv_sclk", "tdm_b_slv_fs",
+};
+
+static const char * const mclk_vad_groups[] = {
+	"mclk_vad",
+};
+
+static const char * const tdm_vad_groups[] = {
+	"tdm_vad_sclk_a1", "tdm_vad_fs_a2", "tdm_vad_sclk_a5", "tdm_vad_fs_a6",
+};
+
+static const char * const tst_out_groups[] = {
+	"tst_out0", "tst_out1", "tst_out2", "tst_out3",
+	"tst_out4", "tst_out5", "tst_out6", "tst_out7",
+	"tst_out8", "tst_out9", "tst_out10", "tst_out11",
+};
+
+static const char * const mute_groups[] = {
+	"mute_key", "mute_en",
+};
+
+static struct meson_pmx_func meson_a1_periphs_functions[] = {
+	FUNCTION(gpio_periphs),
+	FUNCTION(psram),
+	FUNCTION(pwm_a),
+	FUNCTION(pwm_b),
+	FUNCTION(pwm_c),
+	FUNCTION(pwm_d),
+	FUNCTION(pwm_e),
+	FUNCTION(pwm_f),
+	FUNCTION(pwm_a_hiz),
+	FUNCTION(pwm_b_hiz),
+	FUNCTION(pwm_c_hiz),
+	FUNCTION(spif),
+	FUNCTION(sdcard),
+	FUNCTION(tdm_a),
+	FUNCTION(uart_a),
+	FUNCTION(uart_b),
+	FUNCTION(uart_c),
+	FUNCTION(i2c0),
+	FUNCTION(i2c1),
+	FUNCTION(i2c2),
+	FUNCTION(i2c3),
+	FUNCTION(spi_a),
+	FUNCTION(pdm),
+	FUNCTION(gen_clk),
+	FUNCTION(remote_input),
+	FUNCTION(jtag_a),
+	FUNCTION(clk_32k_in),
+	FUNCTION(remote_out),
+	FUNCTION(spdif_in),
+	FUNCTION(sw),
+	FUNCTION(clk25),
+	FUNCTION(cec_a),
+	FUNCTION(cec_b),
+	FUNCTION(clk12_24),
+	FUNCTION(mclk_0),
+	FUNCTION(tdm_b),
+	FUNCTION(mclk_vad),
+	FUNCTION(tdm_vad),
+	FUNCTION(tst_out),
+	FUNCTION(mute),
+};
+
+static struct meson_bank meson_a1_periphs_banks[] = {
+	/* name      first    last       pullen    pull      dir       out       in        ds */
+	BANK_DS("P", GPIOP_0, GPIOP_12,  0x3,  0,  0x4,  0,  0x2,  0,  0x1,  0,  0x0,  0,  0x5,  0),
+	BANK_DS("B", GPIOB_0, GPIOB_6,   0x13, 0,  0x14, 0,  0x12, 0,  0x11, 0,  0x10, 0,  0x15, 0),
+	BANK_DS("X", GPIOX_0, GPIOX_16,  0x23, 0,  0x24, 0,  0x22, 0,  0x21, 0,  0x20, 0,  0x25, 0),
+	BANK_DS("F", GPIOF_0, GPIOF_12,  0x33, 0,  0x34, 0,  0x32, 0,  0x31, 0,  0x30, 0,  0x35, 0),
+	BANK_DS("A", GPIOA_0, GPIOA_11,  0x43, 0,  0x44, 0,  0x42, 0,  0x41, 0,  0x40, 0,  0x45, 0),
+};
+
+static struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = {
+	/*  name	 first	  last      reg	 offset  */
+	BANK_PMX("P",    GPIOP_0, GPIOP_12, 0x0, 0),
+	BANK_PMX("B",    GPIOB_0, GPIOB_6,  0x2, 0),
+	BANK_PMX("X",    GPIOX_0, GPIOX_16, 0x3, 0),
+	BANK_PMX("F",    GPIOF_0, GPIOF_12, 0x6, 0),
+	BANK_PMX("A",    GPIOA_0, GPIOA_11, 0x8, 0),
+};
+
+static struct meson_axg_pmx_data meson_a1_periphs_pmx_banks_data = {
+	.pmx_banks	= meson_a1_periphs_pmx_banks,
+	.num_pmx_banks	= ARRAY_SIZE(meson_a1_periphs_pmx_banks),
+};
+
+static struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = {
+	.name		= "periphs-banks",
+	.groups		= meson_a1_periphs_groups,
+	.funcs		= meson_a1_periphs_functions,
+	.banks		= meson_a1_periphs_banks,
+	.num_pins	= 62,
+	.num_groups	= ARRAY_SIZE(meson_a1_periphs_groups),
+	.num_funcs	= ARRAY_SIZE(meson_a1_periphs_functions),
+	.num_banks	= ARRAY_SIZE(meson_a1_periphs_banks),
+	.pmx_data	= &meson_a1_periphs_pmx_banks_data,
+};
+
+static const struct udevice_id meson_a1_pinctrl_match[] = {
+	{
+		.compatible = "amlogic,meson-a1-periphs-pinctrl",
+		.data = (ulong)&meson_a1_periphs_pinctrl_data,
+	},
+	{ },
+};
+
+U_BOOT_DRIVER(meson_a1_pinctrl) = {
+	.name	= "meson-a1-pinctrl",
+	.id	= UCLASS_PINCTRL,
+	.of_match = of_match_ptr(meson_a1_pinctrl_match),
+	.probe = meson_pinctrl_probe,
+	.priv_auto = sizeof(struct meson_pinctrl),
+	.ops = &meson_axg_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
index 1ad8bfbd88..92513822e7 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -1552,12 +1552,12 @@ static int npcm7xx_pinconf_set(struct udevice *dev, unsigned int pin,
 		setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
 	case PIN_CONFIG_OUTPUT:
 		dev_dbg(dev, "set pin %d output %d\n", pin, arg);
-		clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
-		setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
 		if (arg)
 			setbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio));
 		else
 			clrbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio));
+		clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
+		setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
 		break;
 	case PIN_CONFIG_DRIVE_PUSH_PULL:
 		dev_dbg(dev, "set pin %d push pull\n", pin);
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
index 0ec47e9577..7976e3b3ed 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -808,6 +808,9 @@ static bool is_gpio_persist(struct udevice *dev, uint bank)
 	status = npcm_get_reset_status();
 	dev_dbg(dev, "reset status: 0x%x\n", status);
 
+	if (status & PORST)
+		return false;
+
 	if (status & CORST)
 		regmap_read(priv->rst_regmap, CORSTC, &val);
 	else if (status & WD0RST)
@@ -900,12 +903,12 @@ static int npcm8xx_pinconf_set(struct udevice *dev, unsigned int selector,
 		setbits_le32(base + GPIO_OES, BIT(gpio));
 	case PIN_CONFIG_OUTPUT:
 		dev_dbg(dev, "set pin %d output %d\n", pin, arg);
-		clrbits_le32(base + GPIO_IEM, BIT(gpio));
-		setbits_le32(base + GPIO_OES, BIT(gpio));
 		if (arg)
 			setbits_le32(base + GPIO_DOUT, BIT(gpio));
 		else
 			clrbits_le32(base + GPIO_DOUT, BIT(gpio));
+		clrbits_le32(base + GPIO_IEM, BIT(gpio));
+		setbits_le32(base + GPIO_OES, BIT(gpio));
 		break;
 	case PIN_CONFIG_DRIVE_PUSH_PULL:
 		dev_dbg(dev, "set pin %d push pull\n", pin);
diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c
index ee6529b3c2..02626a7561 100644
--- a/drivers/pinctrl/pinctrl-zynqmp.c
+++ b/drivers/pinctrl/pinctrl-zynqmp.c
@@ -3,7 +3,7 @@
  * Xilinx pinctrl driver for ZynqMP
  *
  * Author(s):   Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
- *              Michal Simek <michal.simek@xilinx.com>
+ *              Michal Simek <michal.simek@amd.com>
  *
  * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
  */
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
index 314edb5a60..1d43919826 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
@@ -113,11 +113,9 @@ static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 	struct rockchip_pinctrl_priv *priv = bank->priv;
 	int iomux_num = (pin / 8);
 	struct regmap *regmap;
-	int reg, ret, mask;
+	int reg, mask;
 	u8 bit;
-	u32 data;
-
-	debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+	u32 data, rmask;
 
 	if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 		regmap = priv->regmap_pmu;
@@ -131,10 +129,10 @@ static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 	mask = 0xf;
 
 	data = (mask << (bit + 16));
+	rmask = data | (data >> 16);
 	data |= (mux & mask) << bit;
-	ret = regmap_write(regmap, reg, data);
 
-	return ret;
+	return regmap_update_bits(regmap, reg, rmask, data);
 }
 
 #define RK3568_PULL_PMU_OFFSET		0x20
@@ -225,7 +223,7 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank,
 	struct regmap *regmap;
 	int reg, ret;
 	u8 bit, type;
-	u32 data;
+	u32 data, rmask;
 
 	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
 		return -ENOTSUPP;
@@ -249,52 +247,59 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank,
 
 	/* enable the write to the equivalent lower bits */
 	data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
-
+	rmask = data | (data >> 16);
 	data |= (ret << bit);
-	ret = regmap_write(regmap, reg, data);
 
-	return ret;
+	return regmap_update_bits(regmap, reg, rmask, data);
 }
 
+#define GRF_GPIO1C5_DS		0x0840
+#define GRF_GPIO2A2_DS		0x0844
+#define GRF_GPIO2B0_DS		0x0848
+#define GRF_GPIO3A0_DS		0x084c
+#define GRF_GPIO3A6_DS		0x0850
+#define GRF_GPIO4A0_DS		0x0854
+
 static int rk3568_set_drive(struct rockchip_pin_bank *bank,
 			    int pin_num, int strength)
 {
 	struct regmap *regmap;
-	int reg;
-	u32 data;
+	int reg, ret;
+	u32 data, rmask;
 	u8 bit;
 	int drv = (1 << (strength + 1)) - 1;
-	int ret = 0;
 
 	rk3568_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 
 	/* enable the write to the equivalent lower bits */
 	data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+	rmask = data | (data >> 16);
 	data |= (drv << bit);
 
-	ret = regmap_write(regmap, reg, data);
+	ret = regmap_update_bits(regmap, reg, rmask, data);
 	if (ret)
 		return ret;
 
 	if (bank->bank_num == 1 && pin_num == 21)
-		reg = 0x0840;
+		reg = GRF_GPIO1C5_DS;
 	else if (bank->bank_num == 2 && pin_num == 2)
-		reg = 0x0844;
+		reg = GRF_GPIO2A2_DS;
 	else if (bank->bank_num == 2 && pin_num == 8)
-		reg = 0x0848;
+		reg = GRF_GPIO2B0_DS;
 	else if (bank->bank_num == 3 && pin_num == 0)
-		reg = 0x084c;
+		reg = GRF_GPIO3A0_DS;
 	else if (bank->bank_num == 3 && pin_num == 6)
-		reg = 0x0850;
+		reg = GRF_GPIO3A6_DS;
 	else if (bank->bank_num == 4 && pin_num == 0)
-		reg = 0x0854;
+		reg = GRF_GPIO4A0_DS;
 	else
 		return 0;
 
 	data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
-	data |= drv;
+	rmask = data | (data >> 16);
+	data |= drv >> 6;
 
-	return regmap_write(regmap, reg, data);
+	return regmap_update_bits(regmap, reg, rmask, data);
 }
 
 static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
@@ -302,16 +307,17 @@ static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
 {
 	struct regmap *regmap;
 	int reg;
-	u32 data;
+	u32 data, rmask;
 	u8 bit;
 
 	rk3568_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 
 	/* enable the write to the equivalent lower bits */
 	data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
-	data |= (enable << bit);
+	rmask = data | (data >> 16);
+	data |= ((enable ? 0x2 : 0x1) << bit);
 
-	return regmap_write(regmap, reg, data);
+	return regmap_update_bits(regmap, reg, rmask, data);
 }
 
 static struct rockchip_pin_bank rk3568_pin_banks[] = {
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index d9d61fdb72..8ef089994f 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -12,7 +12,6 @@
 #include <fdtdec.h>
 #include <linux/bitops.h>
 #include <linux/libfdt.h>
-#include <asm/global_data.h>
 
 #include "pinctrl-rockchip.h"
 
@@ -433,13 +432,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
 	int prop_len, param;
 	const u32 *data;
 	ofnode node;
-#ifdef CONFIG_OF_LIVE
-	const struct device_node *np;
-	struct property *pp;
-#else
-	int property_offset, pcfg_node;
-	const void *blob = gd->fdt_blob;
-#endif
+	struct ofprop prop;
 	data = dev_read_prop(config, "rockchip,pins", &count);
 	if (count < 0) {
 		debug("%s: bad array size %d\n", __func__, count);
@@ -473,24 +466,15 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
 		node = ofnode_get_by_phandle(conf);
 		if (!ofnode_valid(node))
 			return -ENODEV;
-#ifdef CONFIG_OF_LIVE
-		np = ofnode_to_np(node);
-		for (pp = np->properties; pp; pp = pp->next) {
-			prop_name = pp->name;
-			prop_len = pp->length;
-			value = pp->value;
-#else
-		pcfg_node = ofnode_to_offset(node);
-		fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
-			value = fdt_getprop_by_offset(blob, property_offset,
-						      &prop_name, &prop_len);
+		ofnode_for_each_prop(prop, node) {
+			value = ofprop_get_property(&prop, &prop_name, &prop_len);
 			if (!value)
-				return -ENOENT;
-#endif
+				continue;
+
 			param = rockchip_pinconf_prop_name_to_param(prop_name,
 								    &default_val);
 			if (param < 0)
-				break;
+				continue;
 
 			if (prop_len >= sizeof(fdt32_t))
 				arg = fdt32_to_cpu(*(fdt32_t *)value);
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 7e1b8c072f..411c210756 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -68,6 +68,13 @@ config MESON_EE_POWER_DOMAIN
 	  Enable support for manipulating Amlogic Meson Everything-Else power
 	  domains.
 
+config MESON_SECURE_POWER_DOMAIN
+	bool "Enable Amlogic Secure power domain driver"
+	depends on POWER_DOMAIN && ARCH_MESON && MESON_A1
+	help
+	  Enable support for manipulating Amlogic Meson Secure power domains.
+	  Support for Amlogic A1 series.
+
 config SANDBOX_POWER_DOMAIN
 	bool "Enable the sandbox power domain test driver"
 	depends on POWER_DOMAIN && SANDBOX
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index e624477621..aa5a4ba57c 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_IMX8MP_HSIOMIX_BLKCTRL) += imx8mp-hsiomix.o
 obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
 obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
 obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o
+obj-$(CONFIG_MESON_SECURE_POWER_DOMAIN) += meson-secure-pwrc.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
 obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c
index 37b0f95aba..c8ca266575 100644
--- a/drivers/power/domain/imx8-power-domain-legacy.c
+++ b/drivers/power/domain/imx8-power-domain-legacy.c
@@ -89,7 +89,6 @@ static int imx8_power_domain_on(struct power_domain *power_domain)
 	struct udevice *dev = power_domain->dev;
 	struct imx8_power_domain_plat *pdata;
 	struct imx8_power_domain_priv *ppriv;
-	sc_err_t ret;
 	int err;
 
 	struct power_domain parent_domain;
@@ -117,11 +116,11 @@ static int imx8_power_domain_on(struct power_domain *power_domain)
 		if (!sc_rm_is_resource_owned(-1, pdata->resource_id))
 			printf("%s [%d] not owned by curr partition\n", dev->name, pdata->resource_id);
 
-		ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id,
+		err = sc_pm_set_resource_power_mode(-1, pdata->resource_id,
 						    SC_PM_PW_MODE_ON);
-		if (ret) {
+		if (err) {
 			printf("Error: %s Power up failed! (error = %d)\n",
-			       dev->name, ret);
+			       dev->name, err);
 			return -EIO;
 		}
 	}
@@ -139,7 +138,7 @@ static int imx8_power_domain_off_node(struct power_domain *power_domain)
 	struct imx8_power_domain_priv *ppriv;
 	struct imx8_power_domain_priv *child_ppriv;
 	struct imx8_power_domain_plat *pdata;
-	sc_err_t ret;
+	int ret;
 
 	ppriv = dev_get_priv(dev);
 	pdata = dev_get_plat(dev);
diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c
index 145f6ec0cd..df5d7d6956 100644
--- a/drivers/power/domain/imx8m-power-domain.c
+++ b/drivers/power/domain/imx8m-power-domain.c
@@ -338,6 +338,9 @@ static int imx8m_power_domain_on(struct power_domain *power_domain)
 		}
 	}
 
+	/* delay for reset to propagate */
+	udelay(5);
+
 	if (domain->bits.pxx) {
 		/* request the domain to power up */
 		setbits_le32(base + regs->pup, domain->bits.pxx);
diff --git a/drivers/power/domain/meson-secure-pwrc.c b/drivers/power/domain/meson-secure-pwrc.c
new file mode 100644
index 0000000000..f70f8e0242
--- /dev/null
+++ b/drivers/power/domain/meson-secure-pwrc.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 SberDevices, Inc.
+ * Author: Alexey Romanov <avromanov@sberdevices.ru>
+ */
+
+#include <dm.h>
+#include <asm/arch/sm.h>
+#include <power-domain.h>
+#include <power-domain-uclass.h>
+#include <dt-bindings/power/meson-a1-power.h>
+
+struct meson_secure_pwrc_domain_desc {
+	char *name;
+	size_t index;
+};
+
+struct meson_secure_pwrc_domain_data {
+	unsigned int count;
+	struct meson_secure_pwrc_domain_desc *domains;
+};
+
+struct meson_secure_pwrc_priv {
+	const struct meson_secure_pwrc_domain_data *data;
+};
+
+static int meson_secure_pwrc_on(struct power_domain *power_domain)
+{
+	struct meson_secure_pwrc_priv *priv = dev_get_priv(power_domain->dev);
+	struct meson_secure_pwrc_domain_desc *pwrc_domain;
+	int err;
+
+	pwrc_domain = &priv->data->domains[power_domain->id];
+
+	err = meson_sm_pwrdm_on(pwrc_domain->index);
+	if (err) {
+		pr_err("meson_sm_pwrdm_on() failed (%d)\n", err);
+		return err;
+	}
+
+	pr_debug("enable %s power domain\n", pwrc_domain->name);
+
+	return 0;
+}
+
+static int meson_secure_pwrc_off(struct power_domain *power_domain)
+{
+	struct meson_secure_pwrc_priv *priv = dev_get_priv(power_domain->dev);
+	struct meson_secure_pwrc_domain_desc *pwrc_domain;
+	int err;
+
+	pwrc_domain = &priv->data->domains[power_domain->id];
+
+	err = meson_sm_pwrdm_off(pwrc_domain->index);
+	if (err) {
+		pr_err("meson_sm_pwrdm_off() failed (%d)\n", err);
+		return err;
+	}
+
+	pr_debug("disable %s power domain\n", pwrc_domain->name);
+
+	return 0;
+}
+
+static int meson_secure_pwrc_of_xlate(struct power_domain *power_domain,
+				  struct ofnode_phandle_args *args)
+{
+	struct meson_secure_pwrc_priv *priv = dev_get_priv(power_domain->dev);
+	struct meson_secure_pwrc_domain_desc *pwrc_domain;
+
+	if (args->args_count < 1) {
+		pr_err("invalid args count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	power_domain->id = args->args[0];
+
+	if (power_domain->id >= priv->data->count) {
+		pr_err("domain with ID=%lu is invalid\n", power_domain->id);
+		return -EINVAL;
+	}
+
+	pwrc_domain = &priv->data->domains[power_domain->id];
+
+	if (!pwrc_domain->name) {
+		pr_err("domain with ID=%lu is invalid\n", power_domain->id);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+#define SEC_PD(__name)			\
+[PWRC_##__name##_ID] =			\
+{					\
+	.name = #__name,		\
+	.index = PWRC_##__name##_ID,	\
+}
+
+static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = {
+	SEC_PD(DSPA),
+	SEC_PD(DSPB),
+	SEC_PD(UART),
+	SEC_PD(DMC),
+	SEC_PD(I2C),
+	SEC_PD(PSRAM),
+	SEC_PD(ACODEC),
+	SEC_PD(AUDIO),
+	SEC_PD(OTP),
+	SEC_PD(DMA),
+	SEC_PD(SD_EMMC),
+	SEC_PD(RAMA),
+	SEC_PD(RAMB),
+	SEC_PD(IR),
+	SEC_PD(SPICC),
+	SEC_PD(SPIFC),
+	SEC_PD(USB),
+	SEC_PD(NIC),
+	SEC_PD(PDMIN),
+	SEC_PD(RSA),
+};
+
+struct power_domain_ops meson_secure_pwrc_ops = {
+	.on = meson_secure_pwrc_on,
+	.off = meson_secure_pwrc_off,
+	.of_xlate = meson_secure_pwrc_of_xlate,
+};
+
+static struct meson_secure_pwrc_domain_data meson_secure_a1_pwrc_data = {
+	.count = ARRAY_SIZE(a1_pwrc_domains),
+	.domains = a1_pwrc_domains,
+};
+
+static const struct udevice_id meson_secure_pwrc_ids[] = {
+	{
+		.compatible = "amlogic,meson-a1-pwrc",
+		.data = (unsigned long)&meson_secure_a1_pwrc_data,
+	},
+	{ }
+};
+
+static int meson_secure_pwrc_probe(struct udevice *dev)
+{
+	struct meson_secure_pwrc_priv *priv = dev_get_priv(dev);
+
+	priv->data = (void *)dev_get_driver_data(dev);
+	if (!priv->data)
+		return -EINVAL;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(meson_secure_pwrc) = {
+	.name = "meson_secure_pwrc",
+	.id = UCLASS_POWER_DOMAIN,
+	.of_match = meson_secure_pwrc_ids,
+	.probe = meson_secure_pwrc_probe,
+	.ops = &meson_secure_pwrc_ops,
+	.priv_auto = sizeof(struct meson_secure_pwrc_priv),
+};
diff --git a/drivers/power/domain/zynqmp-power-domain.c b/drivers/power/domain/zynqmp-power-domain.c
index adbbb5fdd9..5ee9e020fb 100644
--- a/drivers/power/domain/zynqmp-power-domain.c
+++ b/drivers/power/domain/zynqmp-power-domain.c
@@ -23,12 +23,17 @@ static int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 
 static int zynqmp_power_domain_request(struct power_domain *power_domain)
 {
+	int ret = 0;
+
 	dev_dbg(power_domain->dev, "Request for id: %ld\n", power_domain->id);
 
-	if (IS_ENABLED(CONFIG_ARCH_ZYNQMP))
-		return zynqmp_pmufw_node(power_domain->id);
+	if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) {
+		ret = zynqmp_pmufw_node(power_domain->id);
+		if (ret == -ENODEV)
+			ret = 0;
+	}
 
-	return 0;
+	return ret;
 }
 
 static int zynqmp_power_domain_free(struct power_domain *power_domain)
diff --git a/drivers/power/pmic/stpmic1.c b/drivers/power/pmic/stpmic1.c
index 2c85410b1b..8701d4f971 100644
--- a/drivers/power/pmic/stpmic1.c
+++ b/drivers/power/pmic/stpmic1.c
@@ -34,7 +34,9 @@ static const struct pmic_child_info stpmic1_children_info[] = {
 	{ .prefix = "ldo", .driver = "stpmic1_ldo" },
 	{ .prefix = "buck", .driver = "stpmic1_buck" },
 	{ .prefix = "vref_ddr", .driver = "stpmic1_vref_ddr" },
+	{ .prefix = "vref-ddr", .driver = "stpmic1_vref_ddr" },
 	{ .prefix = "pwr_sw", .driver = "stpmic1_pwr_sw" },
+	{ .prefix = "pwr-sw", .driver = "stpmic1_pwr_sw" },
 	{ .prefix = "boost", .driver = "stpmic1_boost" },
 	{ },
 };
diff --git a/drivers/power/regulator/fan53555.c b/drivers/power/regulator/fan53555.c
index 5681206bba..815f96beef 100644
--- a/drivers/power/regulator/fan53555.c
+++ b/drivers/power/regulator/fan53555.c
@@ -101,7 +101,7 @@ struct fan53555_priv {
 
 static int fan53555_regulator_of_to_plat(struct udevice *dev)
 {
-	struct fan53555_plat *dev_pdata = dev_get_plat(dev);
+	struct fan53555_plat *plat = dev_get_plat(dev);
 	struct dm_regulator_uclass_plat *uc_pdata =
 		dev_get_uclass_plat(dev);
 	u32 sleep_vsel;
@@ -118,12 +118,12 @@ static int fan53555_regulator_of_to_plat(struct udevice *dev)
 	 */
 	switch (sleep_vsel) {
 	case FAN53555_VSEL0:
-		dev_pdata->sleep_reg = FAN53555_VSEL0;
-		dev_pdata->vol_reg = FAN53555_VSEL1;
+		plat->sleep_reg = FAN53555_VSEL0;
+		plat->vol_reg = FAN53555_VSEL1;
 		break;
 	case FAN53555_VSEL1:
-		dev_pdata->sleep_reg = FAN53555_VSEL1;
-		dev_pdata->vol_reg = FAN53555_VSEL0;
+		plat->sleep_reg = FAN53555_VSEL1;
+		plat->vol_reg = FAN53555_VSEL0;
 		break;
 	default:
 		pr_err("%s: invalid vsel id %d\n", dev->name, sleep_vsel);
diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c
index 90004d1601..f7ddba8b45 100644
--- a/drivers/power/regulator/fixed.c
+++ b/drivers/power/regulator/fixed.c
@@ -24,16 +24,18 @@ struct fixed_clock_regulator_plat {
 static int fixed_regulator_of_to_plat(struct udevice *dev)
 {
 	struct dm_regulator_uclass_plat *uc_pdata;
-	struct regulator_common_plat *dev_pdata;
+	struct regulator_common_plat *plat;
+	bool gpios;
 
-	dev_pdata = dev_get_plat(dev);
+	plat = dev_get_plat(dev);
 	uc_pdata = dev_get_uclass_plat(dev);
 	if (!uc_pdata)
 		return -ENXIO;
 
 	uc_pdata->type = REGULATOR_TYPE_FIXED;
 
-	return regulator_common_of_to_plat(dev, dev_pdata, "gpio");
+	gpios = dev_read_bool(dev, "gpios");
+	return regulator_common_of_to_plat(dev, plat, gpios ? "gpios" : "gpio");
 }
 
 static int fixed_regulator_get_value(struct udevice *dev)
@@ -88,7 +90,7 @@ static int fixed_clock_regulator_get_enable(struct udevice *dev)
 static int fixed_clock_regulator_set_enable(struct udevice *dev, bool enable)
 {
 	struct fixed_clock_regulator_plat *priv = dev_get_priv(dev);
-	struct regulator_common_plat *dev_pdata = dev_get_plat(dev);
+	struct regulator_common_plat *plat = dev_get_plat(dev);
 	int ret = 0;
 
 	if (enable) {
@@ -101,11 +103,11 @@ static int fixed_clock_regulator_set_enable(struct udevice *dev, bool enable)
 	if (ret)
 		return ret;
 
-	if (enable && dev_pdata->startup_delay_us)
-		udelay(dev_pdata->startup_delay_us);
+	if (enable && plat->startup_delay_us)
+		udelay(plat->startup_delay_us);
 
-	if (!enable && dev_pdata->off_on_delay_us)
-		udelay(dev_pdata->off_on_delay_us);
+	if (!enable && plat->off_on_delay_us)
+		udelay(plat->off_on_delay_us);
 
 	return ret;
 }
diff --git a/drivers/power/regulator/gpio-regulator.c b/drivers/power/regulator/gpio-regulator.c
index 9c0a68aa5a..ded7be059b 100644
--- a/drivers/power/regulator/gpio-regulator.c
+++ b/drivers/power/regulator/gpio-regulator.c
@@ -27,12 +27,12 @@ struct gpio_regulator_plat {
 static int gpio_regulator_of_to_plat(struct udevice *dev)
 {
 	struct dm_regulator_uclass_plat *uc_pdata;
-	struct gpio_regulator_plat *dev_pdata;
+	struct gpio_regulator_plat *plat;
 	struct gpio_desc *gpio;
 	int ret, count, i, j;
 	u32 states_array[GPIO_REGULATOR_MAX_STATES * 2];
 
-	dev_pdata = dev_get_plat(dev);
+	plat = dev_get_plat(dev);
 	uc_pdata = dev_get_uclass_plat(dev);
 	if (!uc_pdata)
 		return -ENXIO;
@@ -47,7 +47,7 @@ static int gpio_regulator_of_to_plat(struct udevice *dev)
 	 * per gpio-regulator. As of now no instance with multiple
 	 * gpios is presnt
 	 */
-	gpio = &dev_pdata->gpio;
+	gpio = &plat->gpio;
 	ret = gpio_request_by_name(dev, "gpios", 0, gpio, GPIOD_IS_OUT);
 	if (ret)
 		debug("regulator gpio - not found! Error: %d", ret);
@@ -68,21 +68,21 @@ static int gpio_regulator_of_to_plat(struct udevice *dev)
 		return ret;
 
 	for (i = 0, j = 0; i < count; i += 2) {
-		dev_pdata->voltages[j] = states_array[i];
-		dev_pdata->states[j] = states_array[i + 1];
+		plat->voltages[j] = states_array[i];
+		plat->states[j] = states_array[i + 1];
 		j++;
 	}
 
-	return regulator_common_of_to_plat(dev, &dev_pdata->common, "enable-gpios");
+	return regulator_common_of_to_plat(dev, &plat->common, "enable-gpios");
 }
 
 static int gpio_regulator_get_value(struct udevice *dev)
 {
 	struct dm_regulator_uclass_plat *uc_pdata;
-	struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev);
+	struct gpio_regulator_plat *plat = dev_get_plat(dev);
 	int enable;
 
-	if (!dev_pdata->gpio.dev)
+	if (!plat->gpio.dev)
 		return -ENOSYS;
 
 	uc_pdata = dev_get_uclass_plat(dev);
@@ -91,30 +91,30 @@ static int gpio_regulator_get_value(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	enable = dm_gpio_get_value(&dev_pdata->gpio);
-	if (enable == dev_pdata->states[0])
-		return dev_pdata->voltages[0];
+	enable = dm_gpio_get_value(&plat->gpio);
+	if (enable == plat->states[0])
+		return plat->voltages[0];
 	else
-		return dev_pdata->voltages[1];
+		return plat->voltages[1];
 }
 
 static int gpio_regulator_set_value(struct udevice *dev, int uV)
 {
-	struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev);
+	struct gpio_regulator_plat *plat = dev_get_plat(dev);
 	int ret;
 	bool enable;
 
-	if (!dev_pdata->gpio.dev)
+	if (!plat->gpio.dev)
 		return -ENOSYS;
 
-	if (uV == dev_pdata->voltages[0])
-		enable = dev_pdata->states[0];
-	else if (uV == dev_pdata->voltages[1])
-		enable = dev_pdata->states[1];
+	if (uV == plat->voltages[0])
+		enable = plat->states[0];
+	else if (uV == plat->voltages[1])
+		enable = plat->states[1];
 	else
 		return -EINVAL;
 
-	ret = dm_gpio_set_value(&dev_pdata->gpio, enable);
+	ret = dm_gpio_set_value(&plat->gpio, enable);
 	if (ret) {
 		pr_err("Can't set regulator : %s gpio to: %d\n", dev->name,
 		      enable);
@@ -126,14 +126,14 @@ static int gpio_regulator_set_value(struct udevice *dev, int uV)
 
 static int gpio_regulator_get_enable(struct udevice *dev)
 {
-	struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev);
-	return regulator_common_get_enable(dev, &dev_pdata->common);
+	struct gpio_regulator_plat *plat = dev_get_plat(dev);
+	return regulator_common_get_enable(dev, &plat->common);
 }
 
 static int gpio_regulator_set_enable(struct udevice *dev, bool enable)
 {
-	struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev);
-	return regulator_common_set_enable(dev, &dev_pdata->common, enable);
+	struct gpio_regulator_plat *plat = dev_get_plat(dev);
+	return regulator_common_set_enable(dev, &plat->common, enable);
 }
 
 static const struct dm_regulator_ops gpio_regulator_ops = {
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index d608f7c236..3a6ba69f6d 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -197,6 +197,12 @@ int regulator_set_enable_if_allowed(struct udevice *dev, bool enable)
 	ret = regulator_set_enable(dev, enable);
 	if (ret == -ENOSYS || ret == -EACCES)
 		return 0;
+	/* if we want to disable but it's in use by someone else */
+	if (!enable && ret == -EBUSY)
+		return 0;
+	/* if it's already enabled/disabled */
+	if (ret == -EALREADY)
+		return 0;
 
 	return ret;
 }
diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c
index 93d8196b38..e26f5ebec3 100644
--- a/drivers/power/regulator/regulator_common.c
+++ b/drivers/power/regulator/regulator_common.c
@@ -13,7 +13,7 @@
 #include "regulator_common.h"
 
 int regulator_common_of_to_plat(struct udevice *dev,
-				struct regulator_common_plat *dev_pdata,
+				struct regulator_common_plat *plat,
 				const char *enable_gpio_name)
 {
 	struct gpio_desc *gpio;
@@ -26,7 +26,7 @@ int regulator_common_of_to_plat(struct udevice *dev,
 		flags |= GPIOD_IS_OUT_ACTIVE;
 
 	/* Get optional enable GPIO desc */
-	gpio = &dev_pdata->gpio;
+	gpio = &plat->gpio;
 	ret = gpio_request_by_name(dev, enable_gpio_name, 0, gpio, flags);
 	if (ret) {
 		debug("Regulator '%s' optional enable GPIO - not found! Error: %d\n",
@@ -36,12 +36,11 @@ int regulator_common_of_to_plat(struct udevice *dev,
 	}
 
 	/* Get optional ramp up delay */
-	dev_pdata->startup_delay_us = dev_read_u32_default(dev,
-							"startup-delay-us", 0);
-	dev_pdata->off_on_delay_us =
-		dev_read_u32_default(dev, "off-on-delay-us", 0);
-	if (!dev_pdata->off_on_delay_us) {
-		dev_pdata->off_on_delay_us =
+	plat->startup_delay_us = dev_read_u32_default(dev,
+						      "startup-delay-us", 0);
+	plat->off_on_delay_us = dev_read_u32_default(dev, "off-on-delay-us", 0);
+	if (!plat->off_on_delay_us) {
+		plat->off_on_delay_us =
 			dev_read_u32_default(dev, "u-boot,off-on-delay-us", 0);
 	}
 
@@ -49,43 +48,65 @@ int regulator_common_of_to_plat(struct udevice *dev,
 }
 
 int regulator_common_get_enable(const struct udevice *dev,
-	struct regulator_common_plat *dev_pdata)
+	struct regulator_common_plat *plat)
 {
 	/* Enable GPIO is optional */
-	if (!dev_pdata->gpio.dev)
+	if (!plat->gpio.dev)
 		return true;
 
-	return dm_gpio_get_value(&dev_pdata->gpio);
+	return dm_gpio_get_value(&plat->gpio);
 }
 
 int regulator_common_set_enable(const struct udevice *dev,
-	struct regulator_common_plat *dev_pdata, bool enable)
+	struct regulator_common_plat *plat, bool enable)
 {
 	int ret;
 
 	debug("%s: dev='%s', enable=%d, delay=%d, has_gpio=%d\n", __func__,
-	      dev->name, enable, dev_pdata->startup_delay_us,
-	      dm_gpio_is_valid(&dev_pdata->gpio));
+	      dev->name, enable, plat->startup_delay_us,
+	      dm_gpio_is_valid(&plat->gpio));
 	/* Enable GPIO is optional */
-	if (!dm_gpio_is_valid(&dev_pdata->gpio)) {
+	if (!dm_gpio_is_valid(&plat->gpio)) {
 		if (!enable)
 			return -ENOSYS;
 		return 0;
 	}
 
-	ret = dm_gpio_set_value(&dev_pdata->gpio, enable);
+	/* If previously enabled, increase count */
+	if (enable && plat->enable_count > 0) {
+		plat->enable_count++;
+		return -EALREADY;
+	}
+
+	if (!enable) {
+		if (plat->enable_count > 1) {
+			/* If enabled multiple times, decrease count */
+			plat->enable_count--;
+			return -EBUSY;
+		} else if (!plat->enable_count) {
+			/* If already disabled, do nothing */
+			return -EALREADY;
+		}
+	}
+
+	ret = dm_gpio_set_value(&plat->gpio, enable);
 	if (ret) {
 		pr_err("Can't set regulator : %s gpio to: %d\n", dev->name,
 		      enable);
 		return ret;
 	}
 
-	if (enable && dev_pdata->startup_delay_us)
-		udelay(dev_pdata->startup_delay_us);
+	if (enable && plat->startup_delay_us)
+		udelay(plat->startup_delay_us);
 	debug("%s: done\n", __func__);
 
-	if (!enable && dev_pdata->off_on_delay_us)
-		udelay(dev_pdata->off_on_delay_us);
+	if (!enable && plat->off_on_delay_us)
+		udelay(plat->off_on_delay_us);
+
+	if (enable)
+		plat->enable_count++;
+	else
+		plat->enable_count--;
 
 	return 0;
 }
diff --git a/drivers/power/regulator/regulator_common.h b/drivers/power/regulator/regulator_common.h
index c10492f016..d4962899d8 100644
--- a/drivers/power/regulator/regulator_common.h
+++ b/drivers/power/regulator/regulator_common.h
@@ -13,14 +13,35 @@ struct regulator_common_plat {
 	struct gpio_desc gpio; /* GPIO for regulator enable control */
 	unsigned int startup_delay_us;
 	unsigned int off_on_delay_us;
+	unsigned int enable_count;
 };
 
 int regulator_common_of_to_plat(struct udevice *dev,
-				struct regulator_common_plat *dev_pdata, const
+				struct regulator_common_plat *plat, const
 				char *enable_gpio_name);
 int regulator_common_get_enable(const struct udevice *dev,
-	struct regulator_common_plat *dev_pdata);
+	struct regulator_common_plat *plat);
+/*
+ * Enable or Disable a regulator
+ *
+ * This is a reentrant function and subsequent calls that enable will
+ * increase an internal counter, and disable calls will decrease the counter.
+ * The actual resource will be enabled when the counter gets to 1 coming from 0,
+ * and disabled when it reaches 0 coming from 1.
+ *
+ * @dev: regulator device
+ * @plat: Platform data
+ * @enable: bool indicating whether to enable or disable the regulator
+ * @return:
+ * 0 on Success
+ * -EBUSY if the regulator cannot be disabled because it's requested by
+ *        another device
+ * -EALREADY if the regulator has already been enabled or has already been
+ *        disabled
+ * -EACCES if there is no possibility to enable/disable the regulator
+ * -ve on different error situation
+ */
 int regulator_common_set_enable(const struct udevice *dev,
-	struct regulator_common_plat *dev_pdata, bool enable);
+	struct regulator_common_plat *plat, bool enable);
 
 #endif /* _REGULATOR_COMMON_H */
diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c
index 0ee07ad299..e95640a39b 100644
--- a/drivers/power/regulator/rk8xx.c
+++ b/drivers/power/regulator/rk8xx.c
@@ -12,6 +12,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <log.h>
+#include <linux/delay.h>
 #include <power/rk8xx_pmic.h>
 #include <power/pmic.h>
 #include <power/regulator.h>
@@ -616,6 +617,9 @@ static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable)
 		break;
 	}
 
+	if (enable)
+		udelay(500);
+
 	return ret;
 }
 
diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c
index 605142eab0..11e7444019 100644
--- a/drivers/pwm/pwm-mtk.c
+++ b/drivers/pwm/pwm-mtk.c
@@ -205,12 +205,19 @@ static const struct mtk_pwm_soc mt7986_data = {
 	.reg_ver = PWM_REG_V1,
 };
 
+static const struct mtk_pwm_soc mt7988_data = {
+	.num_pwms = 8,
+	.pwm45_fixup = false,
+	.reg_ver = PWM_REG_V2,
+};
+
 static const struct udevice_id mtk_pwm_ids[] = {
 	{ .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
 	{ .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
 	{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
 	{ .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
 	{ .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
+	{ .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data },
 	{ }
 };
 
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 7e445d2b73..b54557f02c 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -138,6 +138,7 @@ struct k3_ddrss_desc {
 	u32 ddr_freq1;
 	u32 ddr_freq2;
 	u32 ddr_fhs_cnt;
+	u32 dram_class;
 	struct udevice *vtt_supply;
 	u32 instance;
 	lpddr4_obj *driverdt;
@@ -243,14 +244,11 @@ static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
 
 static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
 {
-	u32 dram_class;
 	struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
 
 	debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
 
-	dram_class = k3_lpddr4_read_ddr_type(pd);
-
-	switch (dram_class) {
+	switch (ddrss->dram_class) {
 	case DENALI_CTL_0_DRAM_CLASS_DDR4:
 		break;
 	case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
@@ -263,13 +261,12 @@ static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
 
 static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
 {
-	u32 dram_class;
 	int ret;
 	lpddr4_privatedata *pd = &ddrss->pd;
 
-	dram_class = k3_lpddr4_read_ddr_type(pd);
+	ddrss->dram_class = k3_lpddr4_read_ddr_type(pd);
 
-	switch (dram_class) {
+	switch (ddrss->dram_class) {
 	case DENALI_CTL_0_DRAM_CLASS_DDR4:
 		/* Set to ddr_freq1 from DT for DDR4 */
 		ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c
index 1737fdac97..f65fcf179c 100644
--- a/drivers/ram/mediatek/ddr3-mt7629.c
+++ b/drivers/ram/mediatek/ddr3-mt7629.c
@@ -14,6 +14,7 @@
 #include <asm/io.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
+#include <linux/sizes.h>
 
 /* EMI */
 #define EMI_CONA			0x000
diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c
index 553f2ce6f4..a0a3d6b33d 100644
--- a/drivers/ram/starfive/starfive_ddr.c
+++ b/drivers/ram/starfive/starfive_ddr.c
@@ -72,8 +72,6 @@ static int starfive_ddr_probe(struct udevice *dev)
 	u64 rate;
 	int ret;
 
-	/* Read memory base and size from DT */
-	fdtdec_setup_mem_size_base();
 	priv->info.base = gd->ram_base;
 	priv->info.size = gd->ram_size;
 
diff --git a/drivers/reset/reset-mediatek.c b/drivers/reset/reset-mediatek.c
index 8b62d91777..97ed221f73 100644
--- a/drivers/reset/reset-mediatek.c
+++ b/drivers/reset/reset-mediatek.c
@@ -79,6 +79,9 @@ int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs)
 		return ret;
 
 	priv = malloc(sizeof(struct mediatek_reset_priv));
+	if (!priv)
+		return -ENOMEM;
+
 	priv->regofs = regofs;
 	priv->nr_resets = num_regs * 32;
 	dev_set_priv(rst_dev, priv);
diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c
index 2ebe3382f7..6cabaa10a3 100644
--- a/drivers/reset/reset-rockchip.c
+++ b/drivers/reset/reset-rockchip.c
@@ -97,7 +97,7 @@ static int rockchip_reset_probe(struct udevice *dev)
 	fdt_addr_t addr;
 	fdt_size_t size;
 
-	addr = dev_read_addr_size(dev, "reg", &size);
+	addr = dev_read_addr_size(dev, &size);
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
diff --git a/drivers/rtc/max313xx.c b/drivers/rtc/max313xx.c
index 748f3c42c3..60400235dd 100644
--- a/drivers/rtc/max313xx.c
+++ b/drivers/rtc/max313xx.c
@@ -326,10 +326,22 @@ static int max313xx_reset(struct udevice *dev)
 	return ret;
 }
 
+static int max313xx_read8(struct udevice *dev, unsigned int reg)
+{
+	return  dm_i2c_reg_read(dev, reg);
+}
+
+static int max313xx_write8(struct udevice *dev, unsigned int reg, int val)
+{
+	return dm_i2c_reg_write(dev, reg, val);
+}
+
 static const struct rtc_ops max3133x_rtc_ops = {
 	.get	= max313xx_read_time,
 	.set	= max313xx_set_time,
 	.reset  = max313xx_reset,
+	.read8	= max313xx_read8,
+	.write8	= max313xx_write8,
 };
 
 static int max313xx_init(struct udevice *dev)
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 6caeb3fcdd..0a3420b7fb 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -607,7 +607,7 @@ static int do_scsi_scan_one(struct udevice *dev, int id, int lun, bool verbose)
 		/* TODO: undo create */
 		return log_msg_ret("pro", ret);
 
-	ret = bootdev_setup_sibling_blk(bdev, "scsi_bootdev");
+	ret = bootdev_setup_for_sibling_blk(bdev, "scsi_bootdev");
 	if (ret)
 		return log_msg_ret("bd", ret);
 
diff --git a/drivers/scsi/scsi_bootdev.c b/drivers/scsi/scsi_bootdev.c
index 991013fe1e..218221fa30 100644
--- a/drivers/scsi/scsi_bootdev.c
+++ b/drivers/scsi/scsi_bootdev.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Bootdevice for USB
+ * Bootdev for SCSI
  *
  * Copyright 2021 Google LLC
  * Written by Simon Glass <sjg@chromium.org>
diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c
index ded7346a13..2dffa14ea7 100644
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
@@ -439,6 +439,7 @@ static inline void _debug_uart_init(void)
 {
 	struct mtk_serial_priv priv;
 
+	memset(&priv, 0, sizeof(struct mtk_serial_priv));
 	priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
 	priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK;
 
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index f5468353e1..428a4d210d 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -291,8 +291,16 @@ int pl01x_serial_probe(struct udevice *dev)
 	struct pl01x_serial_plat *plat = dev_get_plat(dev);
 	struct pl01x_priv *priv = dev_get_priv(dev);
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_serial_pl01x *dtplat = &plat->dtplat;
+
+	priv->regs = (struct pl01x_regs *)dtplat->reg[0];
+	plat->type = dtplat->type;
+#else
 	priv->regs = (struct pl01x_regs *)plat->base;
+#endif
 	priv->type = plat->type;
+
 	if (!plat->skip_init)
 		return pl01x_generic_serial_init(priv->regs, priv->type);
 	else
@@ -321,7 +329,7 @@ int pl01x_serial_pending(struct udevice *dev, bool input)
 	if (input)
 		return pl01x_tstc(priv->regs);
 	else
-		return fr & UART_PL01x_FR_TXFF ? 0 : 1;
+		return fr & UART_PL01x_FR_TXFE ? 0 : 1;
 }
 
 static const struct dm_serial_ops pl01x_serial_ops = {
@@ -331,7 +339,7 @@ static const struct dm_serial_ops pl01x_serial_ops = {
 	.setbrg = pl01x_serial_setbrg,
 };
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_REAL)
 static const struct udevice_id pl01x_serial_id[] ={
 	{.compatible = "arm,pl011", .data = TYPE_PL011},
 	{.compatible = "arm,pl010", .data = TYPE_PL010},
@@ -380,8 +388,10 @@ int pl01x_serial_of_to_plat(struct udevice *dev)
 U_BOOT_DRIVER(serial_pl01x) = {
 	.name	= "serial_pl01x",
 	.id	= UCLASS_SERIAL,
+#if CONFIG_IS_ENABLED(OF_REAL)
 	.of_match = of_match_ptr(pl01x_serial_id),
 	.of_to_plat = of_match_ptr(pl01x_serial_of_to_plat),
+#endif
 	.plat_auto	= sizeof(struct pl01x_serial_plat),
 	.probe = pl01x_serial_probe,
 	.ops	= &pl01x_serial_ops,
@@ -389,6 +399,8 @@ U_BOOT_DRIVER(serial_pl01x) = {
 	.priv_auto	= sizeof(struct pl01x_priv),
 };
 
+DM_DRIVER_ALIAS(serial_pl01x, arm_pl011)
+DM_DRIVER_ALIAS(serial_pl01x, arm_pl010)
 #endif
 
 #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index 2ba92bf9c4..23d476fba2 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -18,9 +18,18 @@
 #include <dm/device_compat.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
+#include <linux/iopoll.h>
 #include "serial_stm32.h"
 #include <dm/device_compat.h>
 
+/*
+ * At 115200 bits/s
+ * 1 bit = 1 / 115200 = 8,68 us
+ * 8 bits = 69,444 us
+ * 10 bits are needed for worst case (8 bits + 1 start + 1 stop) = 86.806 us
+ */
+#define ONE_BYTE_B115200_US		87
+
 static void _stm32_serial_setbrg(fdt_addr_t base,
 				 struct stm32_uart_info *uart_info,
 				 u32 clock_rate,
@@ -28,6 +37,10 @@ static void _stm32_serial_setbrg(fdt_addr_t base,
 {
 	bool stm32f4 = uart_info->stm32f4;
 	u32 int_div, mantissa, fraction, oversampling;
+	u8 uart_enable_bit = uart_info->uart_enable_bit;
+
+	/* BRR register must be set when uart is disabled */
+	clrbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit));
 
 	int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
 
@@ -43,6 +56,8 @@ static void _stm32_serial_setbrg(fdt_addr_t base,
 	fraction = int_div % oversampling;
 
 	writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
+
+	setbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit));
 }
 
 static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
@@ -181,9 +196,12 @@ static int stm32_serial_probe(struct udevice *dev)
 	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
 	struct clk clk;
 	struct reset_ctl reset;
+	u32 isr;
 	int ret;
+	bool stm32f4;
 
 	plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
+	stm32f4 = plat->uart_info->stm32f4;
 
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret < 0)
@@ -195,6 +213,15 @@ static int stm32_serial_probe(struct udevice *dev)
 		return ret;
 	}
 
+	/*
+	 * before uart initialization, wait for TC bit (Transmission Complete)
+	 * in case there is still chars from previous bootstage to transmit
+	 */
+	ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 50,
+				16 * ONE_BYTE_B115200_US, plat->base + ISR_OFFSET(stm32f4));
+	if (ret)
+		dev_dbg(dev, "FIFO not empty, some character can be lost (%d)\n", ret);
+
 	ret = reset_get_by_index(dev, 0, &reset);
 	if (!ret) {
 		reset_assert(&reset);
diff --git a/drivers/serial/serial_stm32.h b/drivers/serial/serial_stm32.h
index 5bee68fa9c..b7e7a90b93 100644
--- a/drivers/serial/serial_stm32.h
+++ b/drivers/serial/serial_stm32.h
@@ -66,6 +66,7 @@ struct stm32x7_serial_plat {
 #define USART_CR3_OVRDIS		BIT(12)
 
 #define USART_ISR_TXE			BIT(7)
+#define USART_ISR_TC			BIT(6)
 #define USART_ISR_RXNE			BIT(5)
 #define USART_ISR_ORE			BIT(3)
 #define USART_ISR_FE			BIT(1)
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index afa277f604..d9a5944965 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -3,7 +3,7 @@
  * Xilinx ZynqMP SOC driver
  *
  * Copyright (C) 2021 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  *
  * Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG
  * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4f435fd268..854b8b88da 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -101,12 +101,21 @@ config ATMEL_SPI
 
 config BCM63XX_HSSPI
 	bool "BCM63XX HSSPI driver"
-	depends on (ARCH_BMIPS || BCM6856 || BCM6858 || BCM63158)
+	depends on (ARCH_BMIPS || ARCH_BCMBCA)
 	help
-	  Enable the BCM6328 HSSPI driver. This driver can be used to
+	  Enable the BCM63XX HSSPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Broadcom
 	  SPI core.
 
+config BCMBCA_HSSPI
+	bool "BCMBCA HSSPI driver"
+	depends on ARCH_BCMBCA && HAVE_SPI_CS_CTRL
+	help
+	  This enables support for the High Speed SPI controller present on
+	  newer Broadcom BCMBCA SoCs. These SoCs include an updated SPI controller
+	  that adds the capability to allow the driver to control chip select
+	  explicitly.
+
 config BCM63XX_SPI
 	bool "BCM6348 SPI driver"
 	depends on ARCH_BMIPS
@@ -382,7 +391,7 @@ config SPI_QUP
 config RENESAS_RPC_SPI
 	bool "Renesas RPC SPI driver"
 	depends on RCAR_64 || RZA1
-	imply SPI_FLASH_BAR
+	imply SPI_FLASH_SFDP_SUPPORT
 	help
 	  Enable the Renesas RPC SPI driver, used to access SPI NOR flash
 	  on Renesas RCar Gen3 SoCs. This uses driver model and requires a
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 95dba9ac45..c27b3327c3 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
+obj-$(CONFIG_BCMBCA_HSSPI) += bcmbca_hsspi.o
 obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
 obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 4d714adc4a..a24bb430cb 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -20,7 +20,13 @@
 
 #define HSSPI_PP			0
 
-#define SPI_MAX_SYNC_CLOCK		30000000
+/*
+ * The maximum frequency for SPI synchronous mode is 30MHz for some chips and
+ * 25MHz for some others. This depends on the chip layout and SPI signals
+ * distance to the pad. We use the lower of these values to cover all relevant
+ * chips.
+ */
+#define SPI_MAX_SYNC_CLOCK		25000000
 
 /* SPI Control register */
 #define SPI_CTL_REG			0x000
@@ -72,12 +78,16 @@
 #define SPI_PFL_MODE_REG(x)		(0x100 + (0x20 * (x)) + 0x08)
 #define SPI_PFL_MODE_FILL_SHIFT		0
 #define SPI_PFL_MODE_FILL_MASK		(0xff << SPI_PFL_MODE_FILL_SHIFT)
+#define SPI_PFL_MODE_MDRDST_SHIFT	8
+#define SPI_PFL_MODE_MDWRST_SHIFT	12
 #define SPI_PFL_MODE_MDRDSZ_SHIFT	16
 #define SPI_PFL_MODE_MDRDSZ_MASK	(1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
 #define SPI_PFL_MODE_MDWRSZ_SHIFT	18
 #define SPI_PFL_MODE_MDWRSZ_MASK	(1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
 #define SPI_PFL_MODE_3WIRE_SHIFT	20
 #define SPI_PFL_MODE_3WIRE_MASK		(1 << SPI_PFL_MODE_3WIRE_SHIFT)
+#define SPI_PFL_MODE_PREPCNT_SHIFT	24
+#define SPI_PFL_MODE_PREPCNT_MASK	(4 << SPI_PFL_MODE_PREPCNT_SHIFT)
 
 /* SPI Ping-Pong FIFO registers */
 #define HSSPI_FIFO_SIZE			0x200
@@ -96,12 +106,21 @@
 #define HSSPI_FIFO_OP_CODE_W		(2 << HSSPI_FIFO_OP_CODE_SHIFT)
 #define HSSPI_FIFO_OP_CODE_R		(3 << HSSPI_FIFO_OP_CODE_SHIFT)
 
+#define HSSPI_MAX_DATA_SIZE			(HSSPI_FIFO_SIZE - HSSPI_FIFO_OP_SIZE)
+#define HSSPI_MAX_PREPEND_SIZE		15
+
+#define HSSPI_XFER_MODE_PREPEND		0
+#define HSSPI_XFER_MODE_DUMMYCS		1
+
 struct bcm63xx_hsspi_priv {
 	void __iomem *regs;
 	ulong clk_rate;
 	uint8_t num_cs;
 	uint8_t cs_pols;
 	uint speed;
+	uint xfer_mode;
+	uint32_t prepend_cnt;
+	uint8_t prepend_buf[HSSPI_MAX_PREPEND_SIZE];
 };
 
 static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
@@ -143,9 +162,16 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
 				   struct dm_spi_slave_plat *plat)
 {
 	uint32_t clr, set;
+	uint speed = priv->speed;
+
+	if (priv->xfer_mode == HSSPI_XFER_MODE_DUMMYCS &&
+	    speed > SPI_MAX_SYNC_CLOCK) {
+		speed = SPI_MAX_SYNC_CLOCK;
+		debug("Force to dummy cs mode. Reduce the speed to %dHz\n", speed);
+	}
 
 	/* profile clock */
-	set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
+	set = DIV_ROUND_UP(priv->clk_rate, speed);
 	set = DIV_ROUND_UP(2048, set);
 	set &= SPI_PFL_CLK_FREQ_MASK;
 	set |= SPI_PFL_CLK_RSTLOOP_MASK;
@@ -164,7 +190,7 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
 		set |= SPI_PFL_SIG_LATCHRIS_MASK;
 
 	/* async clk */
-	if (priv->speed > SPI_MAX_SYNC_CLOCK)
+	if (speed > SPI_MAX_SYNC_CLOCK)
 		set |= SPI_PFL_SIG_ASYNCIN_MASK;
 
 	clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
@@ -173,17 +199,24 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
 	set = 0;
 	clr = 0;
 
-	/* invert cs polarity */
-	if (priv->cs_pols & BIT(plat->cs))
-		clr |= BIT(plat->cs);
-	else
-		set |= BIT(plat->cs);
-
-	/* invert dummy cs polarity */
-	if (priv->cs_pols & BIT(!plat->cs))
-		clr |= BIT(!plat->cs);
-	else
-		set |= BIT(!plat->cs);
+	if (priv->xfer_mode == HSSPI_XFER_MODE_PREPEND) {
+		if (priv->cs_pols & BIT(plat->cs))
+			set |= BIT(plat->cs);
+		else
+			clr |= BIT(plat->cs);
+	} else {
+		/* invert cs polarity */
+		if (priv->cs_pols & BIT(plat->cs))
+			clr |= BIT(plat->cs);
+		else
+			set |= BIT(plat->cs);
+
+		/* invert dummy cs polarity */
+		if (priv->cs_pols & BIT(!plat->cs))
+			clr |= BIT(!plat->cs);
+		else
+			set |= BIT(!plat->cs);
+	}
 
 	clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set);
 }
@@ -212,16 +245,21 @@ static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv)
  * all the time. This hack is also used in the upstream linux driver and
  * allows keeping CS active between transfers even if the HW doesn't give
  * this possibility.
+ *
+ * This workaround only works when the dummy CS (usually CS1 when the actual
+ * CS is 0) pinmuxed to SPI chip select function if SPI clock is faster than
+ * SPI_MAX_SYNC_CLOCK. In old broadcom chip, CS1 pin is default to chip select
+ * function. But this is not the case for new chips. To make this function
+ * always work, it should be called with maximum clock of SPI_MAX_SYNC_CLOCK.
  */
-static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
-		const void *dout, void *din, unsigned long flags)
+static int bcm63xx_hsspi_xfer_dummy_cs(struct udevice *dev, unsigned int data_bytes,
+				       const void *dout, void *din, unsigned long flags)
 {
 	struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
 	struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
-	size_t data_bytes = bitlen / 8;
 	size_t step_size = HSSPI_FIFO_SIZE;
 	uint16_t opcode = 0;
-	uint32_t val;
+	uint32_t val = SPI_PFL_MODE_FILL_MASK;
 	const uint8_t *tx = dout;
 	uint8_t *rx = din;
 
@@ -240,14 +278,17 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
 		step_size -= HSSPI_FIFO_OP_SIZE;
 
 	/* dual mode */
-	if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
-	    (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
+	if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||
+	    (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {
 		opcode |= HSSPI_FIFO_OP_MBIT_MASK;
 
-	/* profile mode */
-	val = SPI_PFL_MODE_FILL_MASK |
-	      SPI_PFL_MODE_MDRDSZ_MASK |
-	      SPI_PFL_MODE_MDWRSZ_MASK;
+		/* profile mode */
+		if (plat->mode & SPI_RX_DUAL)
+			val |= SPI_PFL_MODE_MDRDSZ_MASK;
+		if (plat->mode & SPI_TX_DUAL)
+			val |= SPI_PFL_MODE_MDWRSZ_MASK;
+	}
+
 	if (plat->mode & SPI_3WIRE)
 		val |= SPI_PFL_MODE_3WIRE_MASK;
 	writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
@@ -301,6 +342,182 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
 	return 0;
 }
 
+static int bcm63xx_prepare_prepend_transfer(struct bcm63xx_hsspi_priv *priv,
+					    unsigned int data_bytes, const void *dout, void *din,
+					    unsigned long flags)
+{
+	/*
+	 * only support multiple half duplex write transfer + optional
+	 * full duplex read/write at the end.
+	 */
+	if (flags & SPI_XFER_BEGIN) {
+		/* clear prepends */
+		priv->prepend_cnt = 0;
+	}
+
+	if (din) {
+		/* buffering reads not possible for prepend mode */
+		if (!(flags & SPI_XFER_END)) {
+			debug("unable to buffer reads\n");
+			return HSSPI_XFER_MODE_DUMMYCS;
+		}
+
+		/* check rx size */
+		if (data_bytes > HSSPI_MAX_DATA_SIZE) {
+			debug("max rx bytes exceeded\n");
+			return HSSPI_XFER_MODE_DUMMYCS;
+		}
+	}
+
+	if (dout) {
+		/* check tx size */
+		if (flags & SPI_XFER_END) {
+			if (priv->prepend_cnt + data_bytes > HSSPI_MAX_DATA_SIZE) {
+				debug("max tx bytes exceeded\n");
+				return HSSPI_XFER_MODE_DUMMYCS;
+			}
+		} else {
+			if (priv->prepend_cnt + data_bytes > HSSPI_MAX_PREPEND_SIZE) {
+				debug("max prepend bytes exceeded\n");
+				return HSSPI_XFER_MODE_DUMMYCS;
+			}
+
+			/*
+			 * buffer transfer data in the prepend buf in case we have to fall
+			 * back to dummy cs mode.
+			 */
+			memcpy(&priv->prepend_buf[priv->prepend_cnt], dout, data_bytes);
+			priv->prepend_cnt += data_bytes;
+		}
+	}
+
+	return	HSSPI_XFER_MODE_PREPEND;
+}
+
+static int bcm63xx_hsspi_xfer_prepend(struct udevice *dev, unsigned int data_bytes,
+				      const void *dout, void *din, unsigned long flags)
+{
+	struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
+	struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
+	uint16_t opcode = 0;
+	uint32_t val, offset;
+	int ret;
+
+	if (flags & SPI_XFER_END) {
+		offset = HSSPI_FIFO_BASE + HSSPI_FIFO_OP_SIZE;
+		if (priv->prepend_cnt) {
+			/* copy prepend data */
+			memcpy_toio(priv->regs + offset,
+				    priv->prepend_buf, priv->prepend_cnt);
+		}
+
+		if (dout && data_bytes) {
+			/* copy tx data */
+			offset += priv->prepend_cnt;
+			memcpy_toio(priv->regs + offset, dout, data_bytes);
+		}
+
+		bcm63xx_hsspi_activate_cs(priv, plat);
+		if (dout && !din) {
+			/* all half-duplex write. merge to single write */
+			data_bytes += priv->prepend_cnt;
+			opcode = HSSPI_FIFO_OP_CODE_W;
+			priv->prepend_cnt = 0;
+		} else if (!dout && din) {
+			/* half-duplex read with prepend write */
+			opcode = HSSPI_FIFO_OP_CODE_R;
+		} else {
+			/* full duplex read/write */
+			opcode = HSSPI_FIFO_OP_READ_WRITE;
+		}
+
+		/* profile mode */
+		val = SPI_PFL_MODE_FILL_MASK;
+		if (plat->mode & SPI_3WIRE)
+			val |= SPI_PFL_MODE_3WIRE_MASK;
+
+		/* dual mode */
+		if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||
+		    (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {
+			opcode |= HSSPI_FIFO_OP_MBIT_MASK;
+
+			if (plat->mode & SPI_RX_DUAL) {
+				val |= SPI_PFL_MODE_MDRDSZ_MASK;
+				val |= priv->prepend_cnt << SPI_PFL_MODE_MDRDST_SHIFT;
+			}
+			if (plat->mode & SPI_TX_DUAL) {
+				val |= SPI_PFL_MODE_MDWRSZ_MASK;
+				val |= priv->prepend_cnt << SPI_PFL_MODE_MDWRST_SHIFT;
+			}
+		}
+		val |= (priv->prepend_cnt << SPI_PFL_MODE_PREPCNT_SHIFT);
+		writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
+
+		/* set fifo operation */
+		val = opcode | (data_bytes & HSSPI_FIFO_OP_BYTES_MASK);
+		writew(cpu_to_be16(val),
+		       priv->regs + HSSPI_FIFO_OP_REG);
+
+		/* issue the transfer */
+		val = SPI_CMD_OP_START;
+		val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
+		       SPI_CMD_PFL_MASK;
+		val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) &
+		       SPI_CMD_SLAVE_MASK;
+		writel(val, priv->regs + SPI_CMD_REG);
+
+		/* wait for completion */
+		ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,
+				      SPI_STAT_SRCBUSY_MASK, false,
+				      1000, false);
+		if (ret) {
+			bcm63xx_hsspi_deactivate_cs(priv);
+			printf("spi polling timeout\n");
+			return ret;
+		}
+
+		/* copy rx data */
+		if (din)
+			memcpy_fromio(din, priv->regs + HSSPI_FIFO_BASE,
+				      data_bytes);
+		bcm63xx_hsspi_deactivate_cs(priv);
+	}
+
+	return 0;
+}
+
+static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
+			      const void *dout, void *din, unsigned long flags)
+{
+	struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
+	int ret;
+	u32 data_bytes = bitlen >> 3;
+
+	if (priv->xfer_mode == HSSPI_XFER_MODE_PREPEND) {
+		priv->xfer_mode =
+			bcm63xx_prepare_prepend_transfer(priv, data_bytes, dout, din, flags);
+	}
+
+	/* if not prependable, fall back to dummy cs mode with safe clock */
+	if (priv->xfer_mode == HSSPI_XFER_MODE_DUMMYCS) {
+		/* For pending prepend data from previous transfers, send it first */
+		if (priv->prepend_cnt) {
+			bcm63xx_hsspi_xfer_dummy_cs(dev, priv->prepend_cnt,
+						    priv->prepend_buf, NULL,
+						    (flags & ~SPI_XFER_END) | SPI_XFER_BEGIN);
+			priv->prepend_cnt = 0;
+		}
+		ret = bcm63xx_hsspi_xfer_dummy_cs(dev, data_bytes, dout, din, flags);
+	} else {
+		ret = bcm63xx_hsspi_xfer_prepend(dev, data_bytes, dout, din, flags);
+	}
+
+	if (flags & SPI_XFER_END)
+		priv->xfer_mode = HSSPI_XFER_MODE_PREPEND;
+
+	return ret;
+}
+
 static const struct dm_spi_ops bcm63xx_hsspi_ops = {
 	.cs_info = bcm63xx_hsspi_cs_info,
 	.set_mode = bcm63xx_hsspi_set_mode,
@@ -310,6 +527,7 @@ static const struct dm_spi_ops bcm63xx_hsspi_ops = {
 
 static const struct udevice_id bcm63xx_hsspi_ids[] = {
 	{ .compatible = "brcm,bcm6328-hsspi", },
+	{ .compatible = "brcm,bcmbca-hsspi-v1.0", },
 	{ /* sentinel */ }
 };
 
@@ -317,6 +535,7 @@ static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
 {
 	struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
 	struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
+	struct spi_slave *slave = dev_get_parent_priv(dev);
 
 	/* check cs */
 	if (plat->cs >= priv->num_cs) {
@@ -330,6 +549,13 @@ static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
 	else
 		priv->cs_pols &= ~BIT(plat->cs);
 
+	/*
+	 * set the max read/write size to make sure each xfer are within the
+	 * prepend limit
+	 */
+	slave->max_read_size = HSSPI_MAX_DATA_SIZE;
+	slave->max_write_size = HSSPI_MAX_DATA_SIZE;
+
 	return 0;
 }
 
@@ -391,6 +617,9 @@ static int bcm63xx_hsspi_probe(struct udevice *dev)
 	priv->cs_pols = readl(priv->regs + SPI_CTL_REG) &
 			SPI_CTL_CS_POL_MASK;
 
+	/* default in prepend mode */
+	priv->xfer_mode = HSSPI_XFER_MODE_PREPEND;
+
 	return 0;
 }
 
diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c
new file mode 100644
index 0000000000..fbe315a7d4
--- /dev/null
+++ b/drivers/spi/bcmbca_hsspi.c
@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
+ *	Copyright (C) 2000-2010 Broadcom Corporation
+ *	Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
+ *	Copyright (C) 2021 Broadcom Ltd
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <spi.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+
+#define HSSPI_PP			0
+
+#define SPI_MAX_SYNC_CLOCK		30000000
+
+/* SPI Control register */
+#define SPI_CTL_REG			0x000
+#define SPI_CTL_CS_POL_SHIFT		0
+#define SPI_CTL_CS_POL_MASK		(0xff << SPI_CTL_CS_POL_SHIFT)
+#define SPI_CTL_CLK_GATE_SHIFT		16
+#define SPI_CTL_CLK_GATE_MASK		BIT(SPI_CTL_CLK_GATE_SHIFT)
+#define SPI_CTL_CLK_POL_SHIFT		17
+#define SPI_CTL_CLK_POL_MASK		BIT(SPI_CTL_CLK_POL_SHIFT)
+
+/* SPI Interrupts registers */
+#define SPI_IR_STAT_REG			0x008
+#define SPI_IR_ST_MASK_REG		0x00c
+#define SPI_IR_MASK_REG			0x010
+
+#define SPI_IR_CLEAR_ALL		0xff001f1f
+
+/* SPI Ping-Pong Command registers */
+#define SPI_CMD_REG			(0x080 + (0x40 * (HSSPI_PP)) + 0x00)
+#define SPI_CMD_OP_SHIFT		0
+#define SPI_CMD_OP_START		BIT(SPI_CMD_OP_SHIFT)
+#define SPI_CMD_PFL_SHIFT		8
+#define SPI_CMD_PFL_MASK		(0x7 << SPI_CMD_PFL_SHIFT)
+#define SPI_CMD_SLAVE_SHIFT		12
+#define SPI_CMD_SLAVE_MASK		(0x7 << SPI_CMD_SLAVE_SHIFT)
+
+/* SPI Ping-Pong Status registers */
+#define SPI_STAT_REG			(0x080 + (0x40 * (HSSPI_PP)) + 0x04)
+#define SPI_STAT_SRCBUSY_SHIFT		1
+#define SPI_STAT_SRCBUSY_MASK		BIT(SPI_STAT_SRCBUSY_SHIFT)
+
+/* SPI Profile Clock registers */
+#define SPI_PFL_CLK_REG(x)		(0x100 + (0x20 * (x)) + 0x00)
+#define SPI_PFL_CLK_FREQ_SHIFT		0
+#define SPI_PFL_CLK_FREQ_MASK		(0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
+#define SPI_PFL_CLK_RSTLOOP_SHIFT	15
+#define SPI_PFL_CLK_RSTLOOP_MASK	BIT(SPI_PFL_CLK_RSTLOOP_SHIFT)
+
+/* SPI Profile Signal registers */
+#define SPI_PFL_SIG_REG(x)		(0x100 + (0x20 * (x)) + 0x04)
+#define SPI_PFL_SIG_LATCHRIS_SHIFT	12
+#define SPI_PFL_SIG_LATCHRIS_MASK	BIT(SPI_PFL_SIG_LATCHRIS_SHIFT)
+#define SPI_PFL_SIG_LAUNCHRIS_SHIFT	13
+#define SPI_PFL_SIG_LAUNCHRIS_MASK	BIT(SPI_PFL_SIG_LAUNCHRIS_SHIFT)
+#define SPI_PFL_SIG_ASYNCIN_SHIFT	16
+#define SPI_PFL_SIG_ASYNCIN_MASK	BIT(SPI_PFL_SIG_ASYNCIN_SHIFT)
+
+/* SPI Profile Mode registers */
+#define SPI_PFL_MODE_REG(x)		(0x100 + (0x20 * (x)) + 0x08)
+#define SPI_PFL_MODE_FILL_SHIFT		0
+#define SPI_PFL_MODE_FILL_MASK		(0xff << SPI_PFL_MODE_FILL_SHIFT)
+#define SPI_PFL_MODE_MDRDSZ_SHIFT	16
+#define SPI_PFL_MODE_MDRDSZ_MASK	BIT(SPI_PFL_MODE_MDRDSZ_SHIFT)
+#define SPI_PFL_MODE_MDWRSZ_SHIFT	18
+#define SPI_PFL_MODE_MDWRSZ_MASK	BIT(SPI_PFL_MODE_MDWRSZ_SHIFT)
+#define SPI_PFL_MODE_3WIRE_SHIFT	20
+#define SPI_PFL_MODE_3WIRE_MASK		BIT(SPI_PFL_MODE_3WIRE_SHIFT)
+
+/* SPI Ping-Pong FIFO registers */
+#define HSSPI_FIFO_SIZE			0x200
+#define HSSPI_FIFO_BASE			(0x200 + \
+					 (HSSPI_FIFO_SIZE * HSSPI_PP))
+
+/* SPI Ping-Pong FIFO OP register */
+#define HSSPI_FIFO_OP_SIZE		0x2
+#define HSSPI_FIFO_OP_REG		(HSSPI_FIFO_BASE + 0x00)
+#define HSSPI_FIFO_OP_BYTES_SHIFT	0
+#define HSSPI_FIFO_OP_BYTES_MASK	(0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT)
+#define HSSPI_FIFO_OP_MBIT_SHIFT	11
+#define HSSPI_FIFO_OP_MBIT_MASK		BIT(HSSPI_FIFO_OP_MBIT_SHIFT)
+#define HSSPI_FIFO_OP_CODE_SHIFT	13
+#define HSSPI_FIFO_OP_READ_WRITE	(1 << HSSPI_FIFO_OP_CODE_SHIFT)
+#define HSSPI_FIFO_OP_CODE_W		(2 << HSSPI_FIFO_OP_CODE_SHIFT)
+#define HSSPI_FIFO_OP_CODE_R		(3 << HSSPI_FIFO_OP_CODE_SHIFT)
+
+#define HSSPI_MAX_DATA_SIZE		(HSSPI_FIFO_SIZE - HSSPI_FIFO_OP_SIZE)
+
+#define SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT		0
+#define SPIM_CTRL_CS_OVERRIDE_SEL_MASK		0xff
+#define SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT		8
+#define SPIM_CTRL_CS_OVERRIDE_VAL_MASK		0xff
+
+struct bcmbca_hsspi_priv {
+	void __iomem *regs;
+	void __iomem *spim_ctrl;
+	u32 clk_rate;
+	u8 num_cs;
+	u8 cs_pols;
+	u32 speed;
+};
+
+static int bcmbca_hsspi_cs_info(struct udevice *bus, uint cs,
+				struct spi_cs_info *info)
+{
+	struct bcmbca_hsspi_priv *priv = dev_get_priv(bus);
+
+	if (cs >= priv->num_cs) {
+		dev_err(bus, "no cs %u\n", cs);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int bcmbca_hsspi_set_mode(struct udevice *bus, uint mode)
+{
+	struct bcmbca_hsspi_priv *priv = dev_get_priv(bus);
+
+	/* clock polarity */
+	if (mode & SPI_CPOL)
+		setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
+	else
+		clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
+
+	return 0;
+}
+
+static int bcmbca_hsspi_set_speed(struct udevice *bus, uint speed)
+{
+	struct bcmbca_hsspi_priv *priv = dev_get_priv(bus);
+
+	priv->speed = speed;
+
+	return 0;
+}
+
+static void bcmbca_hsspi_setup_clock(struct bcmbca_hsspi_priv *priv,
+				     struct dm_spi_slave_plat *plat)
+{
+	u32 clr, set;
+
+	/* profile clock */
+	set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
+	set = DIV_ROUND_UP(2048, set);
+	set &= SPI_PFL_CLK_FREQ_MASK;
+	set |= SPI_PFL_CLK_RSTLOOP_MASK;
+	writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
+
+	/* profile signal */
+	set = 0;
+	clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
+	      SPI_PFL_SIG_LATCHRIS_MASK |
+	      SPI_PFL_SIG_ASYNCIN_MASK;
+
+	/* latch/launch config */
+	if (plat->mode & SPI_CPHA)
+		set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
+	else
+		set |= SPI_PFL_SIG_LATCHRIS_MASK;
+
+	/* async clk */
+	if (priv->speed > SPI_MAX_SYNC_CLOCK)
+		set |= SPI_PFL_SIG_ASYNCIN_MASK;
+
+	clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
+
+	/* global control */
+	set = 0;
+	clr = 0;
+
+	if (priv->cs_pols & BIT(plat->cs))
+		set |= BIT(plat->cs);
+	else
+		clr |= BIT(plat->cs);
+
+	clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set);
+}
+
+static void bcmbca_hsspi_activate_cs(struct bcmbca_hsspi_priv *priv,
+				     struct dm_spi_slave_plat *plat)
+{
+	u32 val;
+
+	/* set the override bit */
+	val = readl(priv->spim_ctrl);
+	val |= BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT);
+	writel(val, priv->spim_ctrl);
+}
+
+static void bcmbca_hsspi_deactivate_cs(struct bcmbca_hsspi_priv *priv,
+				       struct dm_spi_slave_plat *plat)
+{
+	u32 val;
+
+	/* clear the cs override bit */
+	val = readl(priv->spim_ctrl);
+	val &= ~BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT);
+	writel(val, priv->spim_ctrl);
+}
+
+static int bcmbca_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
+			     const void *dout, void *din, unsigned long flags)
+{
+	struct bcmbca_hsspi_priv *priv = dev_get_priv(dev->parent);
+	struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
+	size_t data_bytes = bitlen / 8;
+	size_t step_size = HSSPI_FIFO_SIZE;
+	u16 opcode = 0;
+	u32 val = SPI_PFL_MODE_FILL_MASK;
+	const u8 *tx = dout;
+	u8 *rx = din;
+	u32 cs_act = 0;
+
+	if (flags & SPI_XFER_BEGIN)
+		bcmbca_hsspi_setup_clock(priv, plat);
+
+	/* fifo operation */
+	if (tx && rx)
+		opcode = HSSPI_FIFO_OP_READ_WRITE;
+	else if (rx)
+		opcode = HSSPI_FIFO_OP_CODE_R;
+	else if (tx)
+		opcode = HSSPI_FIFO_OP_CODE_W;
+
+	if (opcode != HSSPI_FIFO_OP_CODE_R)
+		step_size -= HSSPI_FIFO_OP_SIZE;
+
+	/* dual mode */
+	if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||
+	    (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {
+		opcode |= HSSPI_FIFO_OP_MBIT_MASK;
+
+		/* profile mode */
+		if (plat->mode & SPI_RX_DUAL)
+			val |= SPI_PFL_MODE_MDRDSZ_MASK;
+		if (plat->mode & SPI_TX_DUAL)
+			val |= SPI_PFL_MODE_MDWRSZ_MASK;
+	}
+
+	if (plat->mode & SPI_3WIRE)
+		val |= SPI_PFL_MODE_3WIRE_MASK;
+	writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
+
+	/* transfer loop */
+	while (data_bytes > 0) {
+		size_t curr_step = min(step_size, data_bytes);
+		int ret;
+
+		/* copy tx data */
+		if (tx) {
+			memcpy_toio(priv->regs + HSSPI_FIFO_BASE +
+				    HSSPI_FIFO_OP_SIZE, tx, curr_step);
+			tx += curr_step;
+		}
+
+		/* set fifo operation */
+		writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),
+		       priv->regs + HSSPI_FIFO_OP_REG);
+
+		/* make sure we keep cs active until spi transfer is done */
+		if (!cs_act) {
+			bcmbca_hsspi_activate_cs(priv, plat);
+			cs_act = 1;
+		}
+
+		/* issue the transfer */
+		val = SPI_CMD_OP_START;
+		val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
+			  SPI_CMD_PFL_MASK;
+		val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) &
+			  SPI_CMD_SLAVE_MASK;
+		writel(val, priv->regs + SPI_CMD_REG);
+
+		/* wait for completion */
+		ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,
+				      SPI_STAT_SRCBUSY_MASK, false,
+				      1000, false);
+		if (ret) {
+			bcmbca_hsspi_deactivate_cs(priv, plat);
+			dev_err(dev, "interrupt timeout\n");
+			return ret;
+		}
+
+		data_bytes -= curr_step;
+		if ((flags & SPI_XFER_END) && !data_bytes)
+			bcmbca_hsspi_deactivate_cs(priv, plat);
+
+		/* copy rx data */
+		if (rx) {
+			memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,
+				      curr_step);
+			rx += curr_step;
+		}
+	}
+
+	return 0;
+}
+
+static const struct dm_spi_ops bcmbca_hsspi_ops = {
+	.cs_info = bcmbca_hsspi_cs_info,
+	.set_mode = bcmbca_hsspi_set_mode,
+	.set_speed = bcmbca_hsspi_set_speed,
+	.xfer = bcmbca_hsspi_xfer,
+};
+
+static const struct udevice_id bcmbca_hsspi_ids[] = {
+	{ .compatible = "brcm,bcmbca-hsspi-v1.1", },
+	{ /* sentinel */ }
+};
+
+static int bcmbca_hsspi_child_pre_probe(struct udevice *dev)
+{
+	struct bcmbca_hsspi_priv *priv = dev_get_priv(dev->parent);
+	struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
+	u32 val;
+
+	/* check cs */
+	if (plat->cs >= priv->num_cs) {
+		dev_err(dev, "no cs %u\n", plat->cs);
+		return -EINVAL;
+	}
+
+	/* cs polarity */
+	if (plat->mode & SPI_CS_HIGH)
+		priv->cs_pols |= BIT(plat->cs);
+	else
+		priv->cs_pols &= ~BIT(plat->cs);
+
+	/* set the polarity to spim cs register */
+	val = readl(priv->spim_ctrl);
+	val &= ~BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
+	if (priv->cs_pols & BIT(plat->cs))
+		val |= BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
+	writel(val, priv->spim_ctrl);
+
+	return 0;
+}
+
+static int bcmbca_hsspi_probe(struct udevice *dev)
+{
+	struct bcmbca_hsspi_priv *priv = dev_get_priv(dev);
+	struct clk clk;
+	int ret;
+
+	priv->regs = dev_remap_addr_name(dev, "hsspi");
+	if (!priv->regs)
+		return -EINVAL;
+
+	priv->spim_ctrl = dev_remap_addr_name(dev, "spim-ctrl");
+	if (!priv->spim_ctrl) {
+		dev_err(dev, "misc spim ctrl register not defined in dts!\n");
+		return -EINVAL;
+	}
+
+	priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);
+
+	/* enable clock */
+	ret = clk_get_by_name(dev, "hsspi", &clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_enable(&clk);
+	if (ret < 0 && ret != -ENOSYS)
+		return ret;
+
+	clk_free(&clk);
+
+	/* get clock rate */
+	ret = clk_get_by_name(dev, "pll", &clk);
+	if (ret < 0 && ret != -ENOSYS)
+		return ret;
+
+	priv->clk_rate = clk_get_rate(&clk);
+
+	clk_free(&clk);
+
+	/* initialize hardware */
+	writel(0, priv->regs + SPI_IR_MASK_REG);
+
+	/* clear pending interrupts */
+	writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
+
+	/* enable clk gate */
+	setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
+
+	/* read default cs polarities */
+	priv->cs_pols = readl(priv->regs + SPI_CTL_REG) &
+			SPI_CTL_CS_POL_MASK;
+
+	dev_info(dev, "Broadcom BCMBCA HS SPI bus driver\n");
+	return 0;
+}
+
+U_BOOT_DRIVER(bcmbca_hsspi) = {
+	.name = "bcmbca_hsspi",
+	.id = UCLASS_SPI,
+	.of_match = bcmbca_hsspi_ids,
+	.ops = &bcmbca_hsspi_ops,
+	.priv_auto = sizeof(struct bcmbca_hsspi_priv),
+	.child_pre_probe = bcmbca_hsspi_child_pre_probe,
+	.probe = bcmbca_hsspi_probe,
+};
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index 434c6038f3..a7685a2f51 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -130,7 +130,6 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv)
 #if defined(CONFIG_DM_GPIO)
 int cadence_qspi_versal_flash_reset(struct udevice *dev)
 {
-#ifndef CONFIG_ARCH_VERSAL_NET
 	struct gpio_desc gpio;
 	u32 reset_gpio;
 	int ret;
@@ -166,7 +165,7 @@ int cadence_qspi_versal_flash_reset(struct udevice *dev)
 	/* Set value 1 to pin */
 	dm_gpio_set_value(&gpio, 1);
 	udelay(1);
-#endif
+
 	return 0;
 }
 #else
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 2d715e478c..cc3a54f295 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -249,17 +249,14 @@ static int cadence_spi_probe(struct udevice *bus)
 
 	priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
 
-	if (IS_ENABLED(CONFIG_ARCH_VERSAL)) {
-		/* Versal platform uses spi calibration to set read delay */
+	/* Versal and Versal-NET use spi calibration to set read delay */
+	if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
+	    CONFIG_IS_ENABLED(ARCH_VERSAL_NET))
 		if (priv->read_delay >= 0)
 			priv->read_delay = -1;
-		/* Reset ospi flash device */
-		ret = cadence_qspi_versal_flash_reset(bus);
-		if (ret)
-			return ret;
-	}
 
-	return 0;
+	/* Reset ospi flash device */
+	return cadence_qspi_versal_flash_reset(bus);
 }
 
 static int cadence_spi_remove(struct udevice *dev)
diff --git a/drivers/spi/mtk_spim.c b/drivers/spi/mtk_spim.c
index ebb8ee8ef4..418e586b91 100644
--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
@@ -137,6 +137,8 @@ struct mtk_spim_capability {
  * @state:		Controller state
  * @sel_clk:		Pad clock
  * @spi_clk:		Core clock
+ * @pll_clk_rate:	Controller's PLL source clock rate, which is different
+ *			from SPI bus clock rate
  * @xfer_len:		Current length of data for transfer
  * @hw_cap:		Controller capabilities
  * @tick_dly:		Used to postpone SPI sampling time
@@ -149,6 +151,7 @@ struct mtk_spim_priv {
 	void __iomem *base;
 	u32 state;
 	struct clk sel_clk, spi_clk;
+	u32 pll_clk_rate;
 	u32 xfer_len;
 	struct mtk_spim_capability hw_cap;
 	u32 tick_dly;
@@ -239,6 +242,9 @@ static int mtk_spim_hw_init(struct spi_slave *slave)
 			reg_val &= ~SPI_CMD_SAMPLE_SEL;
 	}
 
+	/* Disable interrupt enable for pause mode & normal mode */
+	reg_val &= ~(SPI_CMD_PAUSE_IE | SPI_CMD_FINISH_IE);
+
 	/* disable dma mode */
 	reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
 
@@ -253,11 +259,10 @@ static int mtk_spim_hw_init(struct spi_slave *slave)
 static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv,
 				      u32 speed_hz)
 {
-	u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
+	u32 div, sck_time, cs_time, reg_val;
 
-	spi_clk_hz = clk_get_rate(&priv->spi_clk);
-	if (speed_hz <= spi_clk_hz / 4)
-		div = DIV_ROUND_UP(spi_clk_hz, speed_hz);
+	if (speed_hz <= priv->pll_clk_rate / 4)
+		div = DIV_ROUND_UP(priv->pll_clk_rate, speed_hz);
 	else
 		div = 4;
 
@@ -404,7 +409,7 @@ static int mtk_spim_transfer_wait(struct spi_slave *slave,
 {
 	struct udevice *bus = dev_get_parent(slave->dev);
 	struct mtk_spim_priv *priv = dev_get_priv(bus);
-	u32 sck_l, sck_h, spi_bus_clk, clk_count, reg;
+	u32 sck_l, sck_h, clk_count, reg;
 	ulong us = 1;
 	int ret = 0;
 
@@ -413,12 +418,11 @@ static int mtk_spim_transfer_wait(struct spi_slave *slave,
 	else
 		clk_count = op->data.nbytes;
 
-	spi_bus_clk = clk_get_rate(&priv->spi_clk);
 	sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
 	sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
-	do_div(spi_bus_clk, sck_l + sck_h + 2);
+	do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
 
-	us = CLK_TO_US(spi_bus_clk, clk_count * 8);
+	us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
 	us += 1000 * 1000; /* 1s tolerance */
 
 	if (us > UINT_MAX)
@@ -662,6 +666,10 @@ static int mtk_spim_probe(struct udevice *dev)
 	clk_enable(&priv->sel_clk);
 	clk_enable(&priv->spi_clk);
 
+	priv->pll_clk_rate = clk_get_rate(&priv->spi_clk);
+	if (priv->pll_clk_rate == 0)
+		return -EINVAL;
+
 	return 0;
 }
 
diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c
index bd9ac65411..37bab70967 100644
--- a/drivers/spi/npcm_pspi.c
+++ b/drivers/spi/npcm_pspi.c
@@ -40,7 +40,7 @@ static inline void spi_cs_activate(struct udevice *dev)
 	struct udevice *bus = dev->parent;
 	struct npcm_pspi_priv *priv = dev_get_priv(bus);
 
-	dm_gpio_set_value(&priv->cs_gpio, 0);
+	dm_gpio_set_value(&priv->cs_gpio, 1);
 }
 
 static inline void spi_cs_deactivate(struct udevice *dev)
@@ -48,7 +48,7 @@ static inline void spi_cs_deactivate(struct udevice *dev)
 	struct udevice *bus = dev->parent;
 	struct npcm_pspi_priv *priv = dev_get_priv(bus);
 
-	dm_gpio_set_value(&priv->cs_gpio, 1);
+	dm_gpio_set_value(&priv->cs_gpio, 0);
 }
 
 static inline void npcm_pspi_enable(struct npcm_pspi_priv *priv)
@@ -122,6 +122,9 @@ static int npcm_pspi_xfer(struct udevice *dev, unsigned int bitlen,
 	if (flags & SPI_XFER_END)
 		spi_cs_deactivate(dev);
 
+	debug("npcm_pspi_xfer: slave %s:%s dout %08X din %08X bitlen %u\n",
+	      dev->parent->name, dev->name, *(uint *)tx, *(uint *)rx, bitlen);
+
 	npcm_pspi_disable(priv);
 
 	return ret;
@@ -183,6 +186,7 @@ static int npcm_pspi_set_mode(struct udevice *bus, uint mode)
 	val |= pspi_mode;
 	writew(val, priv->base + PSPI_CTL1);
 
+	debug("%s: mode=%u\n", __func__, mode);
 	return 0;
 }
 
@@ -197,9 +201,9 @@ static int npcm_pspi_probe(struct udevice *bus)
 		return ret;
 
 	priv->base = dev_read_addr_ptr(bus);
-	priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
+	priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 1000000);
 	gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0,
-				   &priv->cs_gpio, GPIOD_IS_OUT);
+				   &priv->cs_gpio, GPIOD_IS_OUT| GPIOD_ACTIVE_LOW);
 
 	return 0;
 }
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 1cbb5d46fd..ff7b55f870 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -347,20 +347,28 @@ static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv)
 	omap3_spi_write_chconf(priv, confr);
 }
 
-static void spi_reset(struct mcspi *regs)
+static void spi_reset(struct omap3_spi_priv *priv)
 {
 	unsigned int tmp;
 
-	writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &regs->sysconfig);
+	writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &priv->regs->sysconfig);
 	do {
-		tmp = readl(&regs->sysstatus);
+		tmp = readl(&priv->regs->sysstatus);
 	} while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
 
 	writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
 	       OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
-	       OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &regs->sysconfig);
+	       OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &priv->regs->sysconfig);
 
-	writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &regs->wakeupenable);
+	writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &priv->regs->wakeupenable);
+
+	/*
+	 * Set the same default mode for each channel, especially CS polarity
+	 * which must be common for all SPI slaves before any transfer.
+	 */
+	for (priv->cs = 0 ; priv->cs < OMAP4_MCSPI_CHAN_NB ; priv->cs++)
+		_omap3_spi_set_mode(priv);
+	priv->cs = 0;
 }
 
 static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
@@ -430,7 +438,7 @@ static int omap3_spi_probe(struct udevice *dev)
 	priv->pin_dir = plat->pin_dir;
 	priv->wordlen = SPI_DEFAULT_WORDLEN;
 
-	spi_reset(priv->regs);
+	spi_reset(priv);
 
 	return 0;
 }
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
index 828eab3d34..fc7388b379 100644
--- a/drivers/spi/pl022_spi.c
+++ b/drivers/spi/pl022_spi.c
@@ -12,9 +12,11 @@
 #include <clk.h>
 #include <common.h>
 #include <dm.h>
-#include <dm/platform_data/spi_pl022.h>
+#include <dm/device_compat.h>
+#include <fdtdec.h>
 #include <linux/io.h>
 #include <asm/global_data.h>
+#include <asm/gpio.h>
 #include <spi.h>
 
 #define SSP_CR0		0x000
@@ -66,6 +68,15 @@
 #define SSP_SR_MASK_RFF		(0x1 << 3) /* Receive FIFO full */
 #define SSP_SR_MASK_BSY		(0x1 << 4) /* Busy Flag */
 
+struct pl022_spi_pdata {
+	fdt_addr_t addr;
+	fdt_size_t size;
+	unsigned int freq;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+	struct gpio_desc cs_gpio;
+#endif
+};
+
 struct pl022_spi_slave {
 	void *base;
 	unsigned int freq;
@@ -107,7 +118,7 @@ static int pl022_spi_probe(struct udevice *bus)
 	return 0;
 }
 
-static void flush(struct pl022_spi_slave *ps)
+static void pl022_spi_flush(struct pl022_spi_slave *ps)
 {
 	do {
 		while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)
@@ -126,7 +137,7 @@ static int pl022_spi_claim_bus(struct udevice *dev)
 	reg |= SSP_CR1_MASK_SSE;
 	writew(reg, ps->base + SSP_CR1);
 
-	flush(ps);
+	pl022_spi_flush(ps);
 
 	return 0;
 }
@@ -137,7 +148,7 @@ static int pl022_spi_release_bus(struct udevice *dev)
 	struct pl022_spi_slave *ps = dev_get_priv(bus);
 	u16 reg;
 
-	flush(ps);
+	pl022_spi_flush(ps);
 
 	/* Disable the SPI hardware */
 	reg = readw(ps->base + SSP_CR1);
@@ -147,6 +158,17 @@ static int pl022_spi_release_bus(struct udevice *dev)
 	return 0;
 }
 
+static void pl022_spi_set_cs(struct udevice *dev, bool on)
+{
+#if CONFIG_IS_ENABLED(DM_GPIO)
+	struct udevice *bus = dev->parent;
+	struct pl022_spi_pdata *plat = dev_get_plat(bus);
+
+	if (dm_gpio_is_valid(&plat->cs_gpio))
+		dm_gpio_set_value(&plat->cs_gpio, on ? 1 : 0);
+#endif
+}
+
 static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
 			  const void *dout, void *din, unsigned long flags)
 {
@@ -159,7 +181,7 @@ static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
 
 	if (bitlen == 0)
 		/* Finish any previously submitted transfers */
-		return 0;
+		goto done;
 
 	/*
 	 * TODO: The controller can do non-multiple-of-8 bit
@@ -172,9 +194,13 @@ static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	if (bitlen % 8) {
 		/* Errors always terminate an ongoing transfer */
 		flags |= SPI_XFER_END;
-		return -1;
+		ret = -1;
+		goto done;
 	}
 
+	if (flags & SPI_XFER_BEGIN)
+		pl022_spi_set_cs(dev, true);
+
 	len = bitlen / 8;
 
 	while (len_tx < len) {
@@ -201,6 +227,10 @@ static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		}
 	}
 
+done:
+	if (flags & SPI_XFER_END)
+		pl022_spi_set_cs(dev, false);
+
 	return ret;
 }
 
@@ -303,11 +333,18 @@ static int pl022_spi_of_to_plat(struct udevice *bus)
 
 	plat->freq = clk_get_rate(&clkdev);
 
+#if CONFIG_IS_ENABLED(DM_GPIO)
+	ret = gpio_request_by_name(bus, "cs-gpios", 0, &plat->cs_gpio,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret < 0 && ret != -ENOENT)
+		return ret;
+#endif
+
 	return 0;
 }
 
 static const struct udevice_id pl022_spi_ids[] = {
-	{ .compatible = "arm,pl022-spi" },
+	{ .compatible = "arm,pl022" },
 	{ }
 };
 #endif
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index cb2b8fb64d..51c37d72eb 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -17,6 +17,7 @@
 #include <linux/bug.h>
 #include <linux/errno.h>
 #include <spi.h>
+#include <spi-mem.h>
 #include <wait_bit.h>
 
 #define RPC_CMNCR		0x0000	/* R/W */
@@ -140,6 +141,7 @@
 #define PRC_PHYCNT_EXDS		BIT(21)
 #define RPC_PHYCNT_OCT		BIT(20)
 #define RPC_PHYCNT_STRTIM(v)	(((v) & 0x7) << 15)
+#define RPC_PHYCNT_STRTIM2(v)	((((v) & 0x7) << 15) | (((v) & 0x8) << 24))
 #define RPC_PHYCNT_WBUF2	BIT(4)
 #define RPC_PHYCNT_WBUF		BIT(2)
 #define RPC_PHYCNT_MEM(v)	(((v) & 0x3) << 0)
@@ -167,10 +169,6 @@ struct rpc_spi_priv {
 	fdt_addr_t	regs;
 	fdt_addr_t	extr;
 	struct clk	clk;
-
-	u8		cmdcopy[8];
-	u32		cmdlen;
-	bool		cmdstarted;
 };
 
 static int rpc_spi_wait_sslf(struct udevice *dev)
@@ -202,18 +200,35 @@ static void rpc_spi_flush_read_cache(struct udevice *dev)
 
 }
 
+static u32 rpc_spi_get_strobe_delay(void)
+{
+#ifndef CONFIG_RZA1
+	u32 cpu_type = rmobile_get_cpu_type();
+
+	/*
+	 * NOTE: RPC_PHYCNT_STRTIM value:
+	 *       0: On H3 ES1.x (not supported in mainline U-Boot)
+	 *       6: On M3 ES1.x
+	 *       7: On other R-Car Gen3
+	 *      15: On R-Car Gen4
+	 */
+	if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && rmobile_get_cpu_rev_integer() == 1)
+		return RPC_PHYCNT_STRTIM(6);
+	else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 ||
+		 cpu_type == RMOBILE_CPU_TYPE_R8A779G0)
+		return RPC_PHYCNT_STRTIM2(15);
+	else
+#endif
+		return RPC_PHYCNT_STRTIM(7);
+}
+
 static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
 {
 	struct udevice *bus = dev->parent;
 	struct rpc_spi_priv *priv = dev_get_priv(bus);
 
-	/*
-	 * NOTE: The 0x260 are undocumented bits, but they must be set.
-	 * NOTE: On H3 ES1.x (not supported in mainline U-Boot), the
-	 *       RPC_PHYCNT_STRTIM shall be 0, while on newer parts, the
-	 *       RPC_PHYCNT_STRTIM shall be 6.
-	 */
-	writel(RPC_PHYCNT_CAL | RPC_PHYCNT_STRTIM(6) | 0x260,
+	/* NOTE: The 0x260 are undocumented bits, but they must be set. */
+	writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260,
 	       priv->regs + RPC_PHYCNT);
 	writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE |
 		 RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0),
@@ -233,79 +248,91 @@ static int rpc_spi_release_bus(struct udevice *dev)
 	struct rpc_spi_priv *priv = dev_get_priv(bus);
 
 	/* NOTE: The 0x260 are undocumented bits, but they must be set. */
-	writel(RPC_PHYCNT_STRTIM(6) | 0x260, priv->regs + RPC_PHYCNT);
+	writel(rpc_spi_get_strobe_delay() | 0x260, priv->regs + RPC_PHYCNT);
 
 	rpc_spi_flush_read_cache(dev);
 
 	return 0;
 }
 
-static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen,
-			const void *dout, void *din, unsigned long flags)
+static int rpc_spi_mem_exec_op(struct spi_slave *spi,
+			       const struct spi_mem_op *op)
 {
-	struct udevice *bus = dev->parent;
+	struct udevice *bus = spi->dev->parent;
 	struct rpc_spi_priv *priv = dev_get_priv(bus);
-	u32 wlen = dout ? (bitlen / 8) : 0;
-	u32 rlen = din ? (bitlen / 8) : 0;
-	u32 wloop = DIV_ROUND_UP(wlen, 4);
-	u32 smenr, smcr, offset;
+	const void *dout = op->data.buf.out ? op->data.buf.out : NULL;
+	void *din = op->data.buf.in ? op->data.buf.in : NULL;
 	int ret = 0;
-
-	if (!priv->cmdstarted) {
-		if (!wlen || rlen)
-			BUG();
-
-		memcpy(priv->cmdcopy, dout, wlen);
-		priv->cmdlen = wlen;
-
-		/* Command transfer start */
-		priv->cmdstarted = true;
-		if (!(flags & SPI_XFER_END))
-			return 0;
-	}
-
-	offset = (priv->cmdcopy[1] << 16) | (priv->cmdcopy[2] << 8) |
-		 (priv->cmdcopy[3] << 0);
+	u32 offset = 0;
+	u32 smenr, smcr;
 
 	smenr = 0;
+	offset = op->addr.val;
+
+	switch (op->data.dir) {
+	case SPI_MEM_DATA_IN:
+		rpc_spi_claim_bus(spi->dev, false);
+
+		writel(0, priv->regs + RPC_DRCMR);
+		writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR);
+		smenr |= RPC_DRENR_CDE;
+
+		writel(0, priv->regs + RPC_DREAR);
+		if (op->addr.nbytes == 4) {
+			writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1),
+			       priv->regs + RPC_DREAR);
+			smenr |= RPC_DRENR_ADE(0xF);
+		} else if (op->addr.nbytes == 3) {
+			smenr |= RPC_DRENR_ADE(0x7);
+		} else {
+			smenr |= RPC_DRENR_ADE(0);
+		}
 
-	if (wlen || (!rlen && !wlen) || flags == SPI_XFER_ONCE) {
-		if (wlen && flags == SPI_XFER_END)
-			smenr = RPC_SMENR_SPIDE(0xf);
+		writel(0, priv->regs + RPC_DRDMCR);
+		if (op->dummy.nbytes) {
+			writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR);
+			smenr |= RPC_DRENR_DME;
+		}
 
-		rpc_spi_claim_bus(dev, true);
+		writel(0, priv->regs + RPC_DROPR);
+		writel(smenr, priv->regs + RPC_DRENR);
 
-		writel(0, priv->regs + RPC_SMCR);
+		memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes);
 
-		if (priv->cmdlen >= 1) {	/* Command(1) */
-			writel(RPC_SMCMR_CMD(priv->cmdcopy[0]),
-			       priv->regs + RPC_SMCMR);
-			smenr |= RPC_SMENR_CDE;
-		} else {
-			writel(0, priv->regs + RPC_SMCMR);
-		}
+		rpc_spi_release_bus(spi->dev);
+		break;
+	case SPI_MEM_DATA_OUT:
+	case SPI_MEM_NO_DATA:
+		rpc_spi_claim_bus(spi->dev, true);
 
-		if (priv->cmdlen >= 4) {	/* Address(3) */
-			writel(offset, priv->regs + RPC_SMADR);
-			smenr |= RPC_SMENR_ADE(7);
-		} else {
-			writel(0, priv->regs + RPC_SMADR);
-		}
+		writel(0, priv->regs + RPC_SMCR);
+		writel(0, priv->regs + RPC_SMCMR);
+		writel(RPC_SMCMR_CMD(op->cmd.opcode), priv->regs + RPC_SMCMR);
+		smenr |= RPC_SMENR_CDE;
+
+		writel(0, priv->regs + RPC_SMADR);
+		if (op->addr.nbytes == 4)
+			smenr |= RPC_SMENR_ADE(0xF);
+		else if (op->addr.nbytes == 3)
+			smenr |= RPC_SMENR_ADE(0x7);
+		else
+			smenr |= RPC_SMENR_ADE(0);
+		writel(offset, priv->regs + RPC_SMADR);
 
-		if (priv->cmdlen >= 5) {	/* Dummy(n) */
-			writel(8 * (priv->cmdlen - 4) - 1,
-			       priv->regs + RPC_SMDMCR);
+		writel(0, priv->regs + RPC_SMDMCR);
+		if (op->dummy.nbytes) {
+			writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_SMDMCR);
 			smenr |= RPC_SMENR_DME;
-		} else {
-			writel(0, priv->regs + RPC_SMDMCR);
 		}
 
 		writel(0, priv->regs + RPC_SMOPR);
-
 		writel(0, priv->regs + RPC_SMDRENR);
 
-		if (wlen && flags == SPI_XFER_END) {
+		if (dout && op->data.nbytes) {
 			u32 *datout = (u32 *)dout;
+			u32 wloop = DIV_ROUND_UP(op->data.nbytes, 4);
+
+			smenr |= RPC_SMENR_SPIDE(0xF);
 
 			while (wloop--) {
 				smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE;
@@ -314,57 +341,28 @@ static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen,
 				writel(smenr, priv->regs + RPC_SMENR);
 				writel(*datout, priv->regs + RPC_SMWDR0);
 				writel(smcr, priv->regs + RPC_SMCR);
-				ret = rpc_spi_wait_tend(dev);
-				if (ret)
-					goto err;
+				ret = rpc_spi_wait_tend(spi->dev);
+				if (ret) {
+					rpc_spi_release_bus(spi->dev);
+					return ret;
+				}
 				datout++;
-				smenr = RPC_SMENR_SPIDE(0xf);
+				smenr &= (~RPC_SMENR_CDE & ~RPC_SMENR_ADE(0xF));
 			}
 
-			ret = rpc_spi_wait_sslf(dev);
-
+			ret = rpc_spi_wait_sslf(spi->dev);
 		} else {
 			writel(smenr, priv->regs + RPC_SMENR);
 			writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR);
-			ret = rpc_spi_wait_tend(dev);
-		}
-	} else {	/* Read data only, using DRx ext access */
-		rpc_spi_claim_bus(dev, false);
-
-		if (priv->cmdlen >= 1) {	/* Command(1) */
-			writel(RPC_DRCMR_CMD(priv->cmdcopy[0]),
-			       priv->regs + RPC_DRCMR);
-			smenr |= RPC_DRENR_CDE;
-		} else {
-			writel(0, priv->regs + RPC_DRCMR);
-		}
-
-		if (priv->cmdlen >= 4)		/* Address(3) */
-			smenr |= RPC_DRENR_ADE(7);
-
-		if (priv->cmdlen >= 5) {	/* Dummy(n) */
-			writel(8 * (priv->cmdlen - 4) - 1,
-			       priv->regs + RPC_DRDMCR);
-			smenr |= RPC_DRENR_DME;
-		} else {
-			writel(0, priv->regs + RPC_DRDMCR);
+			ret = rpc_spi_wait_tend(spi->dev);
 		}
 
-		writel(0, priv->regs + RPC_DROPR);
-
-		writel(smenr, priv->regs + RPC_DRENR);
-
-		if (rlen)
-			memcpy_fromio(din, (void *)(priv->extr + offset), rlen);
-		else
-			readl(priv->extr);	/* Dummy read */
+		rpc_spi_release_bus(spi->dev);
+		break;
+	default:
+		break;
 	}
 
-err:
-	priv->cmdstarted = false;
-
-	rpc_spi_release_bus(dev);
-
 	return ret;
 }
 
@@ -380,6 +378,10 @@ static int rpc_spi_set_mode(struct udevice *bus, uint mode)
 	return 0;
 }
 
+static const struct spi_controller_mem_ops rpc_spi_mem_ops = {
+	.exec_op	= rpc_spi_mem_exec_op
+};
+
 static int rpc_spi_bind(struct udevice *parent)
 {
 	const void *fdt = gd->fdt_blob;
@@ -443,9 +445,9 @@ static int rpc_spi_of_to_plat(struct udevice *bus)
 }
 
 static const struct dm_spi_ops rpc_spi_ops = {
-	.xfer		= rpc_spi_xfer,
 	.set_speed	= rpc_spi_set_speed,
 	.set_mode	= rpc_spi_set_mode,
+	.mem_ops        = &rpc_spi_mem_ops
 };
 
 static const struct udevice_id rpc_spi_ids[] = {
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index f3602a25ba..0fa14339bd 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -248,20 +248,33 @@ static int soft_spi_probe(struct udevice *dev)
 	cs_flags = (slave && slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
 	clk_flags = (slave && slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
 
-	if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs,
-				 GPIOD_IS_OUT | cs_flags) ||
-	    gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk,
-				 GPIOD_IS_OUT | clk_flags))
+	ret = gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs,
+				   GPIOD_IS_OUT | cs_flags);
+	if (ret)
+		return -EINVAL;
+
+	ret = gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk,
+				   GPIOD_IS_OUT | clk_flags);
+	if (ret)
+		ret = gpio_request_by_name(dev, "sck-gpios", 0, &plat->sclk,
+					   GPIOD_IS_OUT | clk_flags);
+	if (ret)
 		return -EINVAL;
 
 	ret = gpio_request_by_name(dev, "gpio-mosi", 0, &plat->mosi,
 				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 	if (ret)
+		ret = gpio_request_by_name(dev, "mosi-gpios", 0, &plat->mosi,
+					   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret)
 		plat->flags |= SPI_MASTER_NO_TX;
 
 	ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso,
 				   GPIOD_IS_IN);
 	if (ret)
+		ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso,
+					   GPIOD_IS_IN);
+	if (ret)
 		plat->flags |= SPI_MASTER_NO_RX;
 
 	if ((plat->flags & (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX)) ==
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 7b64532e50..572cef1694 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -9,7 +9,7 @@
  * Author: Robert Marko <robert.marko@sartura.hr>
  * Author: Luka Kovacic <luka.kovacic@sartura.hr>
  *
- * Based on stock U-boot and Linux drivers
+ * Based on stock U-Boot and Linux drivers
  */
 
 #include <asm/gpio.h>
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
index 0f5d0a30c3..553f9687e3 100644
--- a/drivers/spi/spi-synquacer.c
+++ b/drivers/spi/spi-synquacer.c
@@ -186,7 +186,7 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx)
 	struct udevice *bus = dev->parent;
 	struct synquacer_spi_priv *priv = dev_get_priv(bus);
 	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
-	u32 val, div, bus_width = 1;
+	u32 val, div, bus_width;
 	int rwflag;
 
 	rwflag = (rx ? 1 : 0) | (tx ? 2 : 0);
@@ -203,16 +203,14 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx)
 	priv->mode = slave_plat->mode;
 	priv->speed = slave_plat->max_hz;
 
-	if (priv->mode & SPI_TX_BYTE)
-		bus_width = 1;
-	else if (priv->mode & SPI_TX_DUAL)
+	if (priv->mode & SPI_TX_DUAL)
 		bus_width = 2;
 	else if (priv->mode & SPI_TX_QUAD)
 		bus_width = 4;
 	else if (priv->mode & SPI_TX_OCTAL)
 		bus_width = 8;
 	else
-		log_warning("SPI mode not configured, setting to byte mode\n");
+		bus_width = 1; /* default is single bit mode */
 
 	div = DIV_ROUND_UP(125000000, priv->speed);
 
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 33575fe757..b58a3f632a 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -363,8 +363,8 @@ static int xilinx_qspi_check_buswidth(struct spi_slave *slave, u8 width)
 	return -EOPNOTSUPP;
 }
 
-bool xilinx_qspi_mem_exec_op(struct spi_slave *slave,
-			     const struct spi_mem_op *op)
+static bool xilinx_qspi_mem_exec_op(struct spi_slave *slave,
+				    const struct spi_mem_op *op)
 {
 	if (xilinx_qspi_check_buswidth(slave, op->cmd.buswidth))
 		return false;
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index d1d4048966..cb52c0f307 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -747,8 +747,8 @@ static int zynq_qspi_check_buswidth(struct spi_slave *slave, u8 width)
 	return -EOPNOTSUPP;
 }
 
-bool zynq_qspi_mem_exec_op(struct spi_slave *slave,
-			   const struct spi_mem_op *op)
+static bool zynq_qspi_mem_exec_op(struct spi_slave *slave,
+				  const struct spi_mem_op *op)
 {
 	if (zynq_qspi_check_buswidth(slave, op->cmd.buswidth))
 		return false;
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 03f7fdd597..bdbe2a9536 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -61,14 +61,14 @@ endif
 
 config POWEROFF_GPIO
 	bool "Enable support for GPIO poweroff driver"
-	select DM_GPIO
+	depends on DM_GPIO
 	help
 	  Support for system poweroff using a GPIO pin. This can be used
 	  for systems having a single GPIO to trigger a system poweroff.
 
 config SYSRESET_GPIO
 	bool "Enable support for GPIO reset driver"
-	select DM_GPIO
+	depends on DM_GPIO
 	help
 	  Reset support via GPIO pin connected reset logic. This is used for
 	  example on Microblaze where reset logic can be controlled via GPIO
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index cdc20f5e94..1ca74805fd 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
 obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
 obj-$(CONFIG_SANDBOX_TIMER)	+= sandbox_timer.o
 obj-$(CONFIG_SP804_TIMER)	+= sp804_timer.o
-obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o
+obj-$(CONFIG_$(SPL_)RISCV_ACLINT) += riscv_aclint_timer.o
 obj-$(CONFIG_ARM_GLOBAL_TIMER)	+= arm_global_timer.o
 obj-$(CONFIG_STM32_TIMER)	+= stm32_timer.o
 obj-$(CONFIG_TEGRA_TIMER)	+= tegra-timer.o
diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c
index aa2e4360c1..9b6d97dae6 100644
--- a/drivers/timer/omap-timer.c
+++ b/drivers/timer/omap-timer.c
@@ -114,6 +114,7 @@ static const struct udevice_id omap_timer_ids[] = {
 	{ .compatible = "ti,am335x-timer" },
 	{ .compatible = "ti,am4372-timer" },
 	{ .compatible = "ti,omap5430-timer" },
+	{ .compatible = "ti,am654-timer" },
 	{}
 };
 
diff --git a/drivers/timer/riscv_aclint_timer.c b/drivers/timer/riscv_aclint_timer.c
new file mode 100644
index 0000000000..e29d527c8d
--- /dev/null
+++ b/drivers/timer/riscv_aclint_timer.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <dm/device-internal.h>
+#include <linux/err.h>
+
+#define CLINT_MTIME_OFFSET		0xbff8
+#define ACLINT_MTIME_OFFSET		0
+
+/* mtime register */
+#define MTIME_REG(base, offset)		((ulong)(base) + (offset))
+
+static u64 notrace riscv_aclint_timer_get_count(struct udevice *dev)
+{
+	return readq((void __iomem *)MTIME_REG(dev_get_priv(dev),
+					       dev_get_driver_data(dev)));
+}
+
+#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+	return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+	return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE,
+					       RISCV_MMODE_TIMEROFF));
+}
+#endif
+
+static const struct timer_ops riscv_aclint_timer_ops = {
+	.get_count = riscv_aclint_timer_get_count,
+};
+
+static int riscv_aclint_timer_probe(struct udevice *dev)
+{
+	dev_set_priv(dev, dev_read_addr_ptr(dev));
+	if (!dev_get_priv(dev))
+		return -EINVAL;
+
+	return timer_timebase_fallback(dev);
+}
+
+static const struct udevice_id riscv_aclint_timer_ids[] = {
+	{ .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET },
+	{ .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET },
+	{ .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET },
+	{ }
+};
+
+U_BOOT_DRIVER(riscv_aclint_timer) = {
+	.name		= "riscv_aclint_timer",
+	.id		= UCLASS_TIMER,
+	.of_match	= riscv_aclint_timer_ids,
+	.probe		= riscv_aclint_timer_probe,
+	.ops		= &riscv_aclint_timer_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c
deleted file mode 100644
index 939b99d937..0000000000
--- a/drivers/timer/sifive_clint_timer.c
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
- * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <timer.h>
-#include <asm/io.h>
-#include <dm/device-internal.h>
-#include <linux/err.h>
-
-/* mtime register */
-#define MTIME_REG(base)			((ulong)(base) + 0xbff8)
-
-static u64 notrace sifive_clint_get_count(struct udevice *dev)
-{
-	return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
-}
-
-#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
-/**
- * timer_early_get_rate() - Get the timer rate before driver model
- */
-unsigned long notrace timer_early_get_rate(void)
-{
-	return RISCV_MMODE_TIMER_FREQ;
-}
-
-/**
- * timer_early_get_count() - Get the timer count before driver model
- *
- */
-u64 notrace timer_early_get_count(void)
-{
-	return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
-}
-#endif
-
-static const struct timer_ops sifive_clint_ops = {
-	.get_count = sifive_clint_get_count,
-};
-
-static int sifive_clint_probe(struct udevice *dev)
-{
-	dev_set_priv(dev, dev_read_addr_ptr(dev));
-	if (!dev_get_priv(dev))
-		return -EINVAL;
-
-	return timer_timebase_fallback(dev);
-}
-
-static const struct udevice_id sifive_clint_ids[] = {
-	{ .compatible = "riscv,clint0" },
-	{ .compatible = "sifive,clint0" },
-	{ }
-};
-
-U_BOOT_DRIVER(sifive_clint) = {
-	.name		= "sifive_clint",
-	.id		= UCLASS_TIMER,
-	.of_match	= sifive_clint_ids,
-	.probe		= sifive_clint_probe,
-	.ops		= &sifive_clint_ops,
-	.flags		= DM_FLAG_PRE_RELOC,
-};
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index 8dd29edd3d..3bf1a95e7f 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -775,7 +775,7 @@ static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba)
 
 	/* command descriptor fields */
 	ucd_req_ptr->header.dword_0 =
-			UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, 0x1f);
+			UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, TASK_TAG);
 	/* clear rest of the fields of basic header */
 	ucd_req_ptr->header.dword_1 = 0;
 	ucd_req_ptr->header.dword_2 = 0;
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 94fb32d107..a972d87c7a 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -126,6 +126,28 @@ config USB_HUB_DEBOUNCE_TIMEOUT
 	  value = 1s because some usb device needs around 1.5s to be initialized
 	  and a 2s value should solve detection issue on problematic USB keys.
 
+if SPL_USB_HOST
+
+comment "USB peripherals in SPL"
+
+config SPL_USB_STORAGE
+	bool "Support loading from USB"
+	help
+	  Enable support for USB devices in SPL. This allows use of USB
+	  devices such as hard drives and flash drivers for loading U-Boot.
+	  The actual drivers are enabled separately using the normal U-Boot
+	  config options. This enables loading from USB using a configured
+	  device.
+
+config SYS_USB_FAT_BOOT_PARTITION
+	int "Partition on USB to use to load U-Boot from"
+	depends on SPL_USB_STORAGE
+	default 1
+	help
+	  Partition on the USB storage device to load U-Boot from.
+
+endif
+
 if USB_KEYBOARD
 
 config USB_KEYBOARD_FN_KEYS
diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index fcaeab9cc1..cae570cf59 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -82,6 +82,9 @@ static int __cdns3_gadget_ep_queue(struct usb_ep *ep,
 				   struct usb_request *request,
 				   gfp_t gfp_flags);
 
+static void cdns3_gadget_udc_set_speed(struct usb_gadget *gadget,
+				       enum usb_device_speed speed);
+
 /**
  * cdns3_set_register_bit - set bit in given register.
  * @ptr: address of device controller register to be read and changed
@@ -2341,6 +2344,7 @@ static int cdns3_gadget_udc_start(struct usb_gadget *gadget,
 
 	spin_lock_irqsave(&priv_dev->lock, flags);
 	priv_dev->gadget_driver = driver;
+	cdns3_gadget_udc_set_speed(gadget, gadget->max_speed);
 	cdns3_gadget_config(priv_dev);
 	spin_unlock_irqrestore(&priv_dev->lock, flags);
 	return 0;
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 66da5a8d6f..b3ed728fd8 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -105,7 +105,7 @@ static int dwc3_generic_probe(struct udevice *dev,
 	if (CONFIG_IS_ENABLED(DM_GPIO) &&
 	    device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3")) {
 		priv->ulpi_reset = devm_gpiod_get_optional(dev->parent, "reset",
-								GPIOD_ACTIVE_LOW);
+							   GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
 		/* property is optional, don't return error! */
 		if (priv->ulpi_reset) {
 			/* Toggle ulpi to reset the phy. */
@@ -226,8 +226,7 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {
 };
 #endif
 
-#if defined(CONFIG_SPL_USB_HOST) || \
-	!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST)
+#if CONFIG_IS_ENABLED(USB_HOST)
 static int dwc3_generic_host_probe(struct udevice *dev)
 {
 	struct xhci_hcor *hcor;
@@ -406,10 +405,23 @@ struct dwc3_glue_ops ti_ops = {
 	.glue_configure = dwc3_ti_glue_configure,
 };
 
+static int dwc3_rk_glue_get_ctrl_dev(struct udevice *dev, ofnode *node)
+{
+	*node = dev_ofnode(dev);
+	if (!ofnode_valid(*node))
+		return -EINVAL;
+
+	return 0;
+}
+
+struct dwc3_glue_ops rk_ops = {
+	.glue_get_ctrl_dev = dwc3_rk_glue_get_ctrl_dev,
+};
+
 static int dwc3_glue_bind_common(struct udevice *parent, ofnode node)
 {
 	const char *name = ofnode_get_name(node);
-	const char *driver = NULL;
+	const char *driver;
 	enum usb_dr_mode dr_mode;
 	struct udevice *dev;
 	int ret;
@@ -421,27 +433,17 @@ static int dwc3_glue_bind_common(struct udevice *parent, ofnode node)
 	if (!dr_mode)
 		dr_mode = usb_get_dr_mode(node);
 
-	switch (dr_mode) {
-	case USB_DR_MODE_PERIPHERAL:
-	case USB_DR_MODE_OTG:
-#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+	if (CONFIG_IS_ENABLED(DM_USB_GADGET) &&
+	    (dr_mode == USB_DR_MODE_PERIPHERAL || dr_mode == USB_DR_MODE_OTG)) {
 		debug("%s: dr_mode: OTG or Peripheral\n", __func__);
 		driver = "dwc3-generic-peripheral";
-#endif
-		break;
-#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD)
-	case USB_DR_MODE_HOST:
+	} else if (CONFIG_IS_ENABLED(USB_HOST) && dr_mode == USB_DR_MODE_HOST) {
 		debug("%s: dr_mode: HOST\n", __func__);
 		driver = "dwc3-generic-host";
-		break;
-#endif
-	default:
-		debug("%s: unsupported dr_mode\n", __func__);
+	} else {
+		debug("%s: unsupported dr_mode %d\n", __func__, dr_mode);
 		return -ENODEV;
-	};
-
-	if (!driver)
-		return -ENXIO;
+	}
 
 	ret = device_bind_driver_to_node(parent, driver, name,
 					 node, &dev);
@@ -558,9 +560,9 @@ int dwc3_glue_probe(struct udevice *dev)
 			return ret;
 	}
 
-	ret = device_find_first_child(dev, &child);
-	if (ret)
-		return ret;
+	device_find_first_child(dev, &child);
+	if (!child)
+		return 0;
 
 	if (glue->clks.count == 0) {
 		ret = dwc3_glue_clk_init(child, glue);
@@ -605,8 +607,9 @@ static const struct udevice_id dwc3_glue_ids[] = {
 	{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
 	{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
 	{ .compatible = "ti,am654-dwc3" },
-	{ .compatible = "rockchip,rk3328-dwc3" },
+	{ .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops },
 	{ .compatible = "rockchip,rk3399-dwc3" },
+	{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
 	{ .compatible = "qcom,dwc3" },
 	{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
 	{ .compatible = "fsl,imx8mq-dwc3" },
diff --git a/drivers/usb/eth/lan78xx.c b/drivers/usb/eth/lan78xx.c
index 37912a1d04..1d8267c80b 100644
--- a/drivers/usb/eth/lan78xx.c
+++ b/drivers/usb/eth/lan78xx.c
@@ -146,11 +146,9 @@ static int lan78xx_read_otp(struct usb_device *udev, u32 offset,
 	ret = lan78xx_read_raw_otp(udev, 0, 1, &sig);
 
 	if (!ret) {
-		if (sig == LAN78XX_OTP_INDICATOR_1)
-			offset = offset;
-		else if (sig == LAN78XX_OTP_INDICATOR_2)
+		if (sig == LAN78XX_OTP_INDICATOR_2)
 			offset += 0x100;
-		else
+		else if (sig != LAN78XX_OTP_INDICATOR_1)
 			return -EINVAL;
 		ret = lan78xx_read_raw_otp(udev, offset, length, data);
 		if (ret)
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 941f97c96d..1cfe602284 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -36,6 +36,12 @@ menuconfig USB_GADGET
 	   peripheral/device side bus controller, and a "gadget driver" for
 	   your peripheral protocol.
 
+config SPL_USB_GADGET
+	bool "USB Gadget Support in SPL"
+	help
+	  Enable USB Gadget API which allows to enable USB device functions
+	  in SPL.
+
 if USB_GADGET
 
 config USB_GADGET_MANUFACTURER
@@ -265,3 +271,85 @@ config USBNET_HOST_ADDR
 endif # USB_ETHER
 
 endif # USB_GADGET
+
+if SPL_USB_GADGET
+
+config SPL_USB_ETHER
+	bool "Support USB Ethernet drivers in SPL"
+	depends on SPL_NET
+	help
+	  Enable access to the USB network subsystem and associated
+	  drivers in SPL. This permits SPL to load U-Boot over a
+	  USB-connected Ethernet link (such as a USB Ethernet dongle) rather
+	  than from an onboard peripheral. Environment support is required
+	  since the network stack uses a number of environment variables.
+	  See also SPL_NET and SPL_ETH.
+
+if SPL_USB_ETHER
+
+choice
+	prompt "USB Ethernet Gadget Model in SPL"
+	default SPL_USB_ETH_RNDIS
+	help
+	  There is several models (protocols) to implement Ethernet over USB
+	  devices. The main ones are Microsoft's RNDIS and USB's CDC-Ethernet
+	  (also called CDC-ECM). RNDIS is obviously compatible with Windows,
+	  while CDC-ECM is not. Most other operating systems support both, so
+	  if inter-operability is a concern, RNDIS is to be preferred.
+
+config SPL_USB_ETH_RNDIS
+	bool "RNDIS Protocol"
+	help
+	  The RNDIS (Remote Network Driver Interface Specification) is a
+	  Microsoft proprietary protocol to create an Ethernet device over USB.
+	  Windows obviously supports it, as well as all the major operating
+	  systems, so it's the best option for compatibility.
+
+endchoice
+
+endif # SPL_USB_ETHER
+
+config SPL_DFU
+	bool "Support DFU (Device Firmware Upgrade) in SPL"
+	select SPL_HASH
+	select SPL_DFU_NO_RESET
+	depends on SPL_RAM_SUPPORT
+	help
+	  This feature enables the DFU (Device Firmware Upgrade) in SPL with
+	  RAM memory device support. The ROM code will load and execute
+	  the SPL built with dfu. The user can load binaries (u-boot/kernel) to
+	  selected device partition from host-pc using dfu-utils.
+	  This feature is useful to flash the binaries to factory or bare-metal
+	  boards using USB interface.
+
+choice
+	bool "DFU device selection in SPL"
+	depends on SPL_DFU
+
+config SPL_DFU_RAM
+	bool "RAM device"
+	depends on SPL_DFU && SPL_RAM_SUPPORT
+	help
+	 select RAM/DDR memory device for loading binary images
+	 (u-boot/kernel) to the selected device partition using
+	 DFU and execute the u-boot/kernel from RAM.
+
+endchoice
+
+config SPL_USB_SDP_SUPPORT
+	bool "Support SDP (Serial Download Protocol) in SPL"
+	depends on SPL_SERIAL
+	help
+	  Enable Serial Download Protocol (SDP) device support in SPL. This
+	  allows to download images into memory and execute (jump to) them
+	  using the same protocol as implemented by the i.MX family's boot ROM.
+
+config SPL_SDP_USB_DEV
+	int "SDP USB controller index in SPL"
+	default 0
+	depends on SPL_USB_SDP_SUPPORT
+	help
+	  Some boards have USB controller other than 0. Define this option
+	  so it can be used in compiled environment.
+
+endif # SPL_USB_GADGET
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 6cfe0f3a04..6abcce0d9c 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -3,8 +3,9 @@
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
-obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o
-obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o
+obj-$(CONFIG_$(SPL_TPL_)USB_GADGET) += epautoconf.o config.o usbstring.o
+obj-$(CONFIG_$(SPL_TPL_)USB_ETHER) += epautoconf.o config.o usbstring.o ether.o
+obj-$(CONFIG_$(SPL_TPL_)USB_ETH_RNDIS) += rndis.o
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_USB_GADGET) += g_dnl.o
@@ -34,9 +35,6 @@ endif
 
 obj-$(CONFIG_CI_UDC) += ci_udc.o
 
-obj-$(CONFIG_USB_ETHER) += ether.o
-obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o
-
 # Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE
 # This is really only N900 and USBTTY now.
 obj-$(CONFIG_USB_DEVICE) += core.o ep0.o
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 85c971e4c4..5ff06d3814 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -2273,56 +2273,16 @@ fail:
 }
 
 /*-------------------------------------------------------------------------*/
-static void _usb_eth_halt(struct ether_priv *priv);
+static void usb_eth_stop(struct udevice *dev);
 
-static int _usb_eth_init(struct ether_priv *priv)
+static int usb_eth_start(struct udevice *udev)
 {
+	struct ether_priv *priv = dev_get_priv(udev);
 	struct eth_dev *dev = &priv->ethdev;
 	struct usb_gadget *gadget;
 	unsigned long ts;
-	int ret;
 	unsigned long timeout = USB_CONNECT_TIMEOUT;
 
-	ret = usb_gadget_initialize(0);
-	if (ret)
-		return ret;
-
-	/* Configure default mac-addresses for the USB ethernet device */
-#ifdef CONFIG_USBNET_DEV_ADDR
-	strlcpy(dev_addr, CONFIG_USBNET_DEV_ADDR, sizeof(dev_addr));
-#endif
-#ifdef CONFIG_USBNET_HOST_ADDR
-	strlcpy(host_addr, CONFIG_USBNET_HOST_ADDR, sizeof(host_addr));
-#endif
-	/* Check if the user overruled the MAC addresses */
-	if (env_get("usbnet_devaddr"))
-		strlcpy(dev_addr, env_get("usbnet_devaddr"),
-			sizeof(dev_addr));
-
-	if (env_get("usbnet_hostaddr"))
-		strlcpy(host_addr, env_get("usbnet_hostaddr"),
-			sizeof(host_addr));
-
-	if (!is_eth_addr_valid(dev_addr)) {
-		pr_err("Need valid 'usbnet_devaddr' to be set");
-		goto fail;
-	}
-	if (!is_eth_addr_valid(host_addr)) {
-		pr_err("Need valid 'usbnet_hostaddr' to be set");
-		goto fail;
-	}
-
-	priv->eth_driver.speed		= DEVSPEED;
-	priv->eth_driver.bind		= eth_bind;
-	priv->eth_driver.unbind		= eth_unbind;
-	priv->eth_driver.setup		= eth_setup;
-	priv->eth_driver.reset		= eth_disconnect;
-	priv->eth_driver.disconnect	= eth_disconnect;
-	priv->eth_driver.suspend	= eth_suspend;
-	priv->eth_driver.resume		= eth_resume;
-	if (usb_gadget_register_driver(&priv->eth_driver) < 0)
-		goto fail;
-
 	dev->network_started = 0;
 
 	packet_received = 0;
@@ -2347,12 +2307,13 @@ static int _usb_eth_init(struct ether_priv *priv)
 	rx_submit(dev, dev->rx_req, 0);
 	return 0;
 fail:
-	_usb_eth_halt(priv);
+	usb_eth_stop(udev);
 	return -1;
 }
 
-static int _usb_eth_send(struct ether_priv *priv, void *packet, int length)
+static int usb_eth_send(struct udevice *udev, void *packet, int length)
 {
+	struct ether_priv *priv = dev_get_priv(udev);
 	int			retval;
 	void			*rndis_pkt = NULL;
 	struct eth_dev		*dev = &priv->ethdev;
@@ -2419,15 +2380,9 @@ drop:
 	return -ENOMEM;
 }
 
-static int _usb_eth_recv(struct ether_priv *priv)
-{
-	usb_gadget_handle_interrupts(0);
-
-	return 0;
-}
-
-static void _usb_eth_halt(struct ether_priv *priv)
+static void usb_eth_stop(struct udevice *udev)
 {
+	struct ether_priv *priv = dev_get_priv(udev);
 	struct eth_dev *dev = &priv->ethdev;
 
 	/* If the gadget not registered, simple return */
@@ -2454,36 +2409,14 @@ static void _usb_eth_halt(struct ether_priv *priv)
 		usb_gadget_handle_interrupts(0);
 		dev->network_started = 0;
 	}
-
-	usb_gadget_unregister_driver(&priv->eth_driver);
-	usb_gadget_release(0);
-}
-
-static int usb_eth_start(struct udevice *dev)
-{
-	struct ether_priv *priv = dev_get_priv(dev);
-
-	return _usb_eth_init(priv);
-}
-
-static int usb_eth_send(struct udevice *dev, void *packet, int length)
-{
-	struct ether_priv *priv = dev_get_priv(dev);
-
-	return _usb_eth_send(priv, packet, length);
 }
 
 static int usb_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 {
 	struct ether_priv *priv = dev_get_priv(dev);
 	struct eth_dev *ethdev = &priv->ethdev;
-	int ret;
 
-	ret = _usb_eth_recv(priv);
-	if (ret) {
-		pr_err("error packet receive\n");
-		return ret;
-	}
+	usb_gadget_handle_interrupts(0);
 
 	if (packet_received) {
 		if (ethdev->rx_req) {
@@ -2509,27 +2442,6 @@ static int usb_eth_free_pkt(struct udevice *dev, uchar *packet,
 	return rx_submit(ethdev, ethdev->rx_req, 0);
 }
 
-static void usb_eth_stop(struct udevice *dev)
-{
-	struct ether_priv *priv = dev_get_priv(dev);
-
-	_usb_eth_halt(priv);
-}
-
-static int usb_eth_probe(struct udevice *dev)
-{
-	struct ether_priv *priv = dev_get_priv(dev);
-	struct eth_pdata *pdata = dev_get_plat(dev);
-
-	priv->netdev = dev;
-	l_priv = priv;
-
-	get_ether_addr(CONFIG_USBNET_DEV_ADDR, pdata->enetaddr);
-	eth_env_set_enetaddr("usbnet_devaddr", pdata->enetaddr);
-
-	return 0;
-}
-
 static const struct eth_ops usb_eth_ops = {
 	.start		= usb_eth_start,
 	.send		= usb_eth_send,
@@ -2555,6 +2467,69 @@ int usb_ether_init(void)
 		return ret;
 	}
 
+	return usb_gadget_initialize(0);
+}
+
+static int usb_eth_probe(struct udevice *dev)
+{
+	struct ether_priv *priv = dev_get_priv(dev);
+	struct eth_pdata *pdata = dev_get_plat(dev);
+
+	priv->netdev = dev;
+	l_priv = priv;
+
+	get_ether_addr(CONFIG_USBNET_DEV_ADDR, pdata->enetaddr);
+	eth_env_set_enetaddr("usbnet_devaddr", pdata->enetaddr);
+
+	/* Configure default mac-addresses for the USB ethernet device */
+#ifdef CONFIG_USBNET_DEV_ADDR
+	strlcpy(dev_addr, CONFIG_USBNET_DEV_ADDR, sizeof(dev_addr));
+#endif
+#ifdef CONFIG_USBNET_HOST_ADDR
+	strlcpy(host_addr, CONFIG_USBNET_HOST_ADDR, sizeof(host_addr));
+#endif
+	/* Check if the user overruled the MAC addresses */
+	if (env_get("usbnet_devaddr"))
+		strlcpy(dev_addr, env_get("usbnet_devaddr"),
+			sizeof(dev_addr));
+
+	if (env_get("usbnet_hostaddr"))
+		strlcpy(host_addr, env_get("usbnet_hostaddr"),
+			sizeof(host_addr));
+
+	if (!is_eth_addr_valid(dev_addr)) {
+		pr_err("Need valid 'usbnet_devaddr' to be set");
+		return -EINVAL;
+	}
+	if (!is_eth_addr_valid(host_addr)) {
+		pr_err("Need valid 'usbnet_hostaddr' to be set");
+		return -EINVAL;
+	}
+
+	priv->eth_driver.speed		= DEVSPEED;
+	priv->eth_driver.bind		= eth_bind;
+	priv->eth_driver.unbind		= eth_unbind;
+	priv->eth_driver.setup		= eth_setup;
+	priv->eth_driver.reset		= eth_disconnect;
+	priv->eth_driver.disconnect	= eth_disconnect;
+	priv->eth_driver.suspend	= eth_suspend;
+	priv->eth_driver.resume		= eth_resume;
+	return usb_gadget_register_driver(&priv->eth_driver);
+}
+
+static int usb_eth_remove(struct udevice *dev)
+{
+	struct ether_priv *priv = dev_get_priv(dev);
+
+	usb_gadget_unregister_driver(&priv->eth_driver);
+
+	return 0;
+}
+
+static int usb_eth_unbind(struct udevice *dev)
+{
+	usb_gadget_release(0);
+
 	return 0;
 }
 
@@ -2562,6 +2537,8 @@ U_BOOT_DRIVER(eth_usb) = {
 	.name	= "usb_ether",
 	.id	= UCLASS_ETH,
 	.probe	= usb_eth_probe,
+	.remove	= usb_eth_remove,
+	.unbind	= usb_eth_unbind,
 	.ops	= &usb_eth_ops,
 	.priv_auto	= sizeof(struct ether_priv),
 	.plat_auto	= sizeof(struct eth_pdata),
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 6213b3c95f..1a883babf4 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -6,6 +6,19 @@ comment "USB Host Controller Drivers"
 config USB_HOST
 	bool
 	select DM_USB
+	help
+	  Enable access to USB (Universal Serial Bus) host devices so that
+	  SPL can load U-Boot from a connected USB peripheral, such as a USB
+	  flash stick. While USB takes a little longer to start up than most
+	  buses, it is very flexible since many different types of storage
+	  device can be attached.
+
+config SPL_USB_HOST
+	bool "Support USB host drivers"
+	depends on SPL
+	help
+	  For detailed help see USB_HOST Kconfig symbol. This option enables
+	  the drivers in drivers/usb/host as part of an SPL build.
 
 config USB_XHCI_HCD
 	bool "xHCI HCD (USB 3.0) support"
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index fae20838c6..a9ed5e7a0d 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -709,18 +709,6 @@ static int ehci_usb_probe(struct udevice *dev)
 		goto err_regulator;
 #endif
 
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
-	if (priv->vbus_supply) {
-		ret = regulator_set_enable(priv->vbus_supply,
-					   (type == USB_INIT_DEVICE) ?
-					   false : true);
-		if (ret && ret != -ENOSYS) {
-			printf("Error enabling VBUS supply (ret=%i)\n", ret);
-			goto err_clk;
-		}
-	}
-#endif
-
 	if (priv->init_type == USB_INIT_HOST) {
 		setbits_le32(&ehci->usbmode, CM_HOST);
 		writel(mx6_portsc(priv->phy_type), &ehci->portsc);
@@ -744,10 +732,6 @@ err_phy:
 	generic_shutdown_phy(&priv->phy);
 err_regulator:
 #endif
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
-	if (priv->vbus_supply)
-		regulator_set_enable(priv->vbus_supply, false);
-#endif
 err_clk:
 #if CONFIG_IS_ENABLED(CLK)
 	clk_disable(&priv->clk);
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index 02c0138a20..7a03435ba7 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -346,7 +346,7 @@ int usb_init(void)
 	if (controllers_initialized == 0)
 		printf("No working controllers found\n");
 
-	return usb_started ? 0 : -1;
+	return usb_started ? 0 : -ENOENT;
 }
 
 int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp)
diff --git a/drivers/usb/host/usb_bootdev.c b/drivers/usb/host/usb_bootdev.c
index 06e8f61aa1..7fa1c601df 100644
--- a/drivers/usb/host/usb_bootdev.c
+++ b/drivers/usb/host/usb_bootdev.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Bootdevice for USB
+ * Bootdev for USB
  *
  * Copyright 2021 Google LLC
  * Written by Simon Glass <sjg@chromium.org>
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 9e33c5d855..5cacf0769e 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -1418,7 +1418,6 @@ int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
 
 	return 0;
 err:
-	free(ctrl);
 	debug("%s: failed, ret=%d\n", __func__, ret);
 	return ret;
 }
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 51f876cd71..c52afd41a7 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -68,6 +68,7 @@ config USB_MUSB_PIC32
 config USB_MUSB_SUNXI
 	bool "Enable sunxi OTG / DRC USB controller"
 	depends on ARCH_SUNXI
+	depends on PHY_SUN4I_USB
 	select USB_MUSB_PIO_ONLY
 	default y
 	---help---
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1e2f4e6de4..69f4809cf4 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -64,8 +64,9 @@ config BACKLIGHT
 
 config VIDEO_PCI_DEFAULT_FB_SIZE
 	hex "Default framebuffer size to use if no drivers request it"
-	default 0x1000000 if X86 && PCI
-	default 0 if !(X86 && PCI)
+	default 0x1000000 if X86
+	default 0x800000 if !X86 && VIDEO_BOCHS
+	default 0 if !X86 && !VIDEO_BOCHS
 	help
 	  Generally, video drivers request the amount of memory they need for
 	  the frame buffer when they are bound, by setting the size field in
@@ -77,7 +78,7 @@ config VIDEO_PCI_DEFAULT_FB_SIZE
 	  devices to have a framebuffer allocated by U-Boot.
 
 	  Note: the framebuffer needs to be large enough to store all pixels at
-	  maximum resolution. For example, at 1920 x 1200 with 32 bits per
+	  maximum resolution. For example, at 2560 x 1600 with 32 bits per
 	  pixel, 2560 * 1600 * 32 / 8 = 0xfa0000 bytes are needed.
 
 config VIDEO_COPY
@@ -278,6 +279,35 @@ config VIDCONSOLE_AS_NAME
 	  possible to update the environment, the breakage may be confusing for
 	  users. This option will be removed around the end of 2020.
 
+config VIDEO_BOCHS
+	bool "Enable Bochs video emulation for QEMU"
+	help
+	  Enable this to use the Bochs video support provided in the QEMU
+	  emulator. This appears as a PCI device which U-Boot can set up to
+	  provide a frame buffer.
+
+if VIDEO_BOCHS
+
+config VIDEO_BOCHS_SIZE_X
+	int "Width of display (X resolution)"
+	default 1280
+	help
+	  Sets the width of the display.
+
+	  These two options control the size of the display set up by QEMU.
+	  Typical sizes are 1024 x 768 or 1280 x 1024.
+
+config VIDEO_BOCHS_SIZE_Y
+	int "High of display (Y resolution)"
+	default 1024
+	help
+	  Sets the height of the display.
+
+	  These two options control the size of the display set up by QEMU.
+	  Typical sizes are 1024 x 768 or 1280 x 1024.
+
+endif
+
 config VIDEO_COREBOOT
 	bool "Enable coreboot framebuffer driver support"
 	depends on X86
@@ -477,6 +507,14 @@ config VIDEO_LCD_ENDEAVORU
 	  using the same DSI command sequence. The panel has a 720x1280
 	  resolution and uses 24 bit RGB per pixel.
 
+config VIDEO_LCD_HIMAX_HX8394
+	bool "Himax HX8394 DSI LCD panel support"
+	depends on PANEL && BACKLIGHT
+	select VIDEO_MIPI_DSI
+	help
+	Say Y here if you want to enable support for Himax HX8394
+	dsi 4dl panel.
+
 config VIDEO_LCD_ORISETECH_OTM8009A
 	bool "OTM8009A DSI LCD panel support"
 	select VIDEO_MIPI_DSI
@@ -740,14 +778,7 @@ config VIDEO_SEPS525
 	  Enable support for the Syncoam PM-OLED display driver (RGB 160x128).
 	  Currently driver is supporting only SPI interface.
 
-config VIDEO_ZYNQMP_DPSUB
-	bool "Enable video support for ZynqMP Display Port"
-	depends on ZYNQMP_POWER_DOMAIN
-	help
-	  Enable support for Xilinx ZynqMP Display Port. Currently this file
-	  is used as placeholder for driver. The main reason is to record
-	  compatible string and calling power domain driver.
-
+source "drivers/video/zynqmp/Kconfig"
 source "drivers/video/nexell/Kconfig"
 
 config CONSOLE_SCROLL_LINES
@@ -840,6 +871,12 @@ config IHS_VIDEO_OUT
 	  out On-screen Display (OSD) used on gdsys FPGAs to control dynamic
 	  textual overlays of the display outputs.
 
+config VIDEO_REMOVE
+	bool "Remove video driver"
+	help
+	  Use this option to specify if user wants to call remove method of
+	  video driver in u-boot proper stage.
+
 config SPLASH_SCREEN
 	bool "Show a splash-screen image"
 	help
@@ -974,6 +1011,16 @@ config SPL_VIDEO
 if SPL_VIDEO
 source "drivers/video/tidss/Kconfig"
 
+config SPL_VIDEO_HANDOFF
+	bool "Pass the video frame-buffer through to U-Boot proper"
+	depends on SPL_BLOBLIST
+	default y if !X86
+	help
+	  Enable this to set up video-handoff information in SPL which can be
+	  picked up in U-Boot proper. This includes the frame buffer and
+	  various other pieces of information. With this enabled, SPL can set
+	  up video and avoid re-initing it later.
+
 config SPL_VIDEO_LOGO
 	bool "Show the U-Boot logo on the display at SPL"
 	default y if !SPL_SPLASH_SCREEN
@@ -1000,8 +1047,9 @@ config SPL_SYS_WHITE_ON_BLACK
 
 config SPL_VIDEO_PCI_DEFAULT_FB_SIZE
 	hex "Default framebuffer size to use if no drivers request it at SPL"
-	default 0x1000000 if X86 && PCI
-	default 0 if !(X86 && PCI)
+	default 0x1000000 if X86
+	default 0x800000 if !X86 && VIDEO_BOCHS
+	default 0 if !X86 && !VIDEO_BOCHS
 	help
 	  Generally, video drivers request the amount of memory they need for
 	  the frame buffer when they are bound, by setting the size field in
@@ -1013,7 +1061,7 @@ config SPL_VIDEO_PCI_DEFAULT_FB_SIZE
 	  devices to have a framebuffer allocated by U-Boot.
 
 	  Note: the framebuffer needs to be large enough to store all pixels at
-	  maximum resolution. For example, at 1920 x 1200 with 32 bits per
+	  maximum resolution. For example, at 2560 x 1600 with 32 bits per
 	  pixel, 2560 * 1600 * 32 / 8 = 0xfa0000 bytes are needed.
 
 config SPL_CONSOLE_SCROLL_LINES
@@ -1063,6 +1111,12 @@ config SPL_SYS_WHITE_ON_BLACK
 	 This can be better in low-light situations or to reduce eye strain in
 	 some cases.
 
+config SPL_VIDEO_REMOVE
+	bool "Remove video driver after SPL stage"
+	help
+	  if this  option is enabled video driver will be removed at the end of
+	  SPL stage, before loading the next stage.
+
 if SPL_SPLASH_SCREEN
 
 config SPL_SPLASH_SCREEN_ALIGN
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 9a53cd1418..d13af9f3b1 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_OSD) += video_osd-uclass.o
 obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o
 obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o
 obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
+obj-$(CONFIG_VIDEO_BOCHS) += bochs.o
 obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
 obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
@@ -54,6 +55,7 @@ obj-$(CONFIG_VIDEO_IPUV3) += imx/
 obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o
+obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
 obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
@@ -73,7 +75,7 @@ obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-$(CONFIG_VIDEO_VESA) += vesa.o
 obj-$(CONFIG_VIDEO_SEPS525) += seps525.o
-obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp_dpsub.o
+obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp/
 
 obj-y += bridge/
 obj-y += sunxi/
diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c
index c2962932c9..14942526f1 100644
--- a/drivers/video/bcm2835.c
+++ b/drivers/video/bcm2835.c
@@ -54,6 +54,9 @@ static const struct udevice_id bcm2835_video_ids[] = {
 	{ .compatible = "brcm,bcm2835-hdmi" },
 	{ .compatible = "brcm,bcm2711-hdmi0" },
 	{ .compatible = "brcm,bcm2708-fb" },
+#if !IS_ENABLED(CONFIG_VIDEO_DT_SIMPLEFB)
+	{ .compatible = "simple-framebuffer" },
+#endif
 	{ }
 };
 
diff --git a/drivers/video/bochs.c b/drivers/video/bochs.c
new file mode 100644
index 0000000000..022ea38d4c
--- /dev/null
+++ b/drivers/video/bochs.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Modified from coreboot bochs.c
+ */
+
+#define LOG_CATEGORY	UCLASS_VIDEO
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <pci.h>
+#include <video.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include "bochs.h"
+
+static int xsize = CONFIG_VIDEO_BOCHS_SIZE_X;
+static int ysize = CONFIG_VIDEO_BOCHS_SIZE_Y;
+
+static void bochs_write(void *mmio, int index, int val)
+{
+	writew(val, mmio + MMIO_BASE + index * 2);
+}
+
+static int bochs_read(void *mmio, int index)
+{
+	return readw(mmio + MMIO_BASE + index * 2);
+}
+
+static void bochs_vga_write(void *mmio, int index, uint8_t val)
+{
+	writeb(val, mmio + VGA_BASE + index);
+}
+
+static int bochs_init_fb(struct udevice *dev)
+{
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	ulong fb;
+	void *mmio;
+	int id, mem;
+
+	log_debug("probing %s at PCI %x\n", dev->name, dm_pci_get_bdf(dev));
+	fb = dm_pci_read_bar32(dev, 0);
+	if (!fb)
+		return log_msg_ret("fb", -EIO);
+
+	/* MMIO bar supported since qemu 3.0+ */
+	mmio = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_TYPE,
+			      PCI_REGION_MEM);
+
+	if (!mmio)
+		return log_msg_ret("map", -EIO);
+
+	/* bochs dispi detection */
+	id = bochs_read(mmio, INDEX_ID);
+	if ((id & 0xfff0) != ID0) {
+		log_debug("ID mismatch\n");
+		return -EPROTONOSUPPORT;
+	}
+	mem = bochs_read(mmio, INDEX_VIDEO_MEMORY_64K) * SZ_64K;
+	log_debug("QEMU VGA: bochs @ %p: %d MiB FB at %lx\n", mmio, mem / SZ_1M,
+		  fb);
+
+	uc_priv->xsize = xsize;
+	uc_priv->ysize = ysize;
+	uc_priv->bpix = VIDEO_BPP32;
+
+	/* setup video mode */
+	bochs_write(mmio, INDEX_ENABLE,  0);
+	bochs_write(mmio, INDEX_BANK,  0);
+	bochs_write(mmio, INDEX_BPP, VNBITS(uc_priv->bpix));
+	bochs_write(mmio, INDEX_XRES, xsize);
+	bochs_write(mmio, INDEX_YRES, ysize);
+	bochs_write(mmio, INDEX_VIRT_WIDTH, xsize);
+	bochs_write(mmio, INDEX_VIRT_HEIGHT, ysize);
+	bochs_write(mmio, INDEX_X_OFFSET, 0);
+	bochs_write(mmio, INDEX_Y_OFFSET, 0);
+	bochs_write(mmio, INDEX_ENABLE, ENABLED | LFB_ENABLED);
+
+	/* disable blanking */
+	bochs_vga_write(mmio, VGA_ATT_W - VGA_INDEX, VGA_AR_ENABLE_DISPLAY);
+
+	plat->base = fb;
+
+	return 0;
+}
+
+static int bochs_video_probe(struct udevice *dev)
+{
+	int ret;
+
+	ret = bochs_init_fb(dev);
+	if (ret)
+		return log_ret(ret);
+
+	return 0;
+}
+
+static int bochs_video_bind(struct udevice *dev)
+{
+	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+
+	/* Set the frame buffer size per configuration */
+	uc_plat->size = xsize * ysize * 32 / 8;
+	log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(bochs_video) = {
+	.name	= "bochs_video",
+	.id	= UCLASS_VIDEO,
+	.bind	= bochs_video_bind,
+	.probe	= bochs_video_probe,
+};
+
+static struct pci_device_id bochs_video_supported[] = {
+	{ PCI_DEVICE(0x1234, 0x1111) },
+	{ },
+};
+
+U_BOOT_PCI_DEVICE(bochs_video, bochs_video_supported);
diff --git a/drivers/video/bochs.h b/drivers/video/bochs.h
new file mode 100644
index 0000000000..3facf690e5
--- /dev/null
+++ b/drivers/video/bochs.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Modified from coreboot bochs.c
+ */
+
+#ifndef __BOCHS_H
+#define __BOCHS_H
+
+#define VGA_INDEX		0x3c0
+
+#define VGA_ATT_W		0x3c0
+#define VGA_AR_ENABLE_DISPLAY	0x20
+
+enum {
+	INDEX_ID,
+	INDEX_XRES,
+	INDEX_YRES,
+	INDEX_BPP,
+	INDEX_ENABLE,
+	INDEX_BANK,
+	INDEX_VIRT_WIDTH,
+	INDEX_VIRT_HEIGHT,
+	INDEX_X_OFFSET,
+	INDEX_Y_OFFSET,
+	INDEX_VIDEO_MEMORY_64K
+};
+
+#define ID0		0xb0c0
+
+#define ENABLED		BIT(0)
+#define LFB_ENABLED	BIT(6)
+#define NOCLEARMEM	BIT(7)
+
+#define VGA_BASE	0x400
+#define MMIO_BASE	0x500
+
+#endif
diff --git a/drivers/video/broadwell_igd.c b/drivers/video/broadwell_igd.c
index 6aa4e27071..83b6c908a8 100644
--- a/drivers/video/broadwell_igd.c
+++ b/drivers/video/broadwell_igd.c
@@ -693,13 +693,9 @@ static int broadwell_igd_probe(struct udevice *dev)
 
 	/* Use write-combining for the graphics memory, 256MB */
 	fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base;
-	ret = mtrr_add_request(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
-	if (!ret)
-		ret = mtrr_commit(true);
-	if (ret && ret != -ENOSYS) {
-		printf("Failed to add MTRR: Display will be slow (err %d)\n",
-		       ret);
-	}
+	ret = mtrr_set_next_var(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
+	if (ret)
+		printf("Failed to add MTRR: Display will be slow (err %d)\n", ret);
 
 	debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base,
 	      plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c
index 1f93b1b85f..b5d0e3dcec 100644
--- a/drivers/video/console_core.c
+++ b/drivers/video/console_core.c
@@ -201,6 +201,12 @@ int console_simple_select_font(struct udevice *dev, const char *name, uint size)
 {
 	struct video_fontdata *font;
 
+	if (!name) {
+		if (fonts->name)
+			console_set_font(dev, fonts);
+		return 0;
+	}
+
 	for (font = fonts; font->name; font++) {
 		if (!strcmp(name, font->name)) {
 			console_set_font(dev, font);
diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c
index 6b5390136a..0f9bb49e44 100644
--- a/drivers/video/console_truetype.c
+++ b/drivers/video/console_truetype.c
@@ -62,10 +62,43 @@ static double tt_sqrt(double value)
 	return lo;
 }
 
+static double tt_fmod(double x, double y)
+{
+	double rem;
+
+	if (y == 0.0)
+		return 0.0;
+	rem = x - (x / y) * y;
+
+	return rem;
+}
+
+/* dummy implementation */
+static double tt_pow(double x, double y)
+{
+	return 0;
+}
+
+/* dummy implementation */
+static double tt_cos(double val)
+{
+	return 0;
+}
+
+/* dummy implementation */
+static double tt_acos(double val)
+{
+	return 0;
+}
+
 #define STBTT_ifloor		tt_floor
 #define STBTT_iceil		tt_ceil
 #define STBTT_fabs		tt_fabs
 #define STBTT_sqrt		tt_sqrt
+#define STBTT_pow		tt_pow
+#define STBTT_fmod		tt_fmod
+#define STBTT_cos		tt_cos
+#define STBTT_acos		tt_acos
 #define STBTT_malloc(size, u)	((void)(u), malloc(size))
 #define STBTT_free(size, u)	((void)(u), free(size))
 #define STBTT_assert(x)
@@ -154,33 +187,33 @@ static int console_truetype_set_row(struct udevice *dev, uint row, int clr)
 	end = line + met->font_size * vid_priv->line_length;
 
 	switch (vid_priv->bpix) {
-#ifdef CONFIG_VIDEO_BPP8
 	case VIDEO_BPP8: {
 		u8 *dst;
 
-		for (dst = line; dst < (u8 *)end; ++dst)
-			*dst = clr;
+		if (IS_ENABLED(CONFIG_VIDEO_BPP8)) {
+			for (dst = line; dst < (u8 *)end; ++dst)
+				*dst = clr;
+		}
 		break;
 	}
-#endif
-#ifdef CONFIG_VIDEO_BPP16
 	case VIDEO_BPP16: {
 		u16 *dst = line;
 
-		for (dst = line; dst < (u16 *)end; ++dst)
-			*dst = clr;
+		if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+			for (dst = line; dst < (u16 *)end; ++dst)
+				*dst = clr;
+		}
 		break;
 	}
-#endif
-#ifdef CONFIG_VIDEO_BPP32
 	case VIDEO_BPP32: {
 		u32 *dst = line;
 
-		for (dst = line; dst < (u32 *)end; ++dst)
-			*dst = clr;
+		if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+			for (dst = line; dst < (u32 *)end; ++dst)
+				*dst = clr;
+		}
 		break;
 	}
-#endif
 	default:
 		return -ENOSYS;
 	}
@@ -256,7 +289,7 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y,
 	 */
 	x_shift = xpos - (double)tt_floor(xpos);
 	xpos += advance * met->scale;
-	width_frac = (int)VID_TO_POS(xpos);
+	width_frac = (int)VID_TO_POS(advance * met->scale);
 	if (x + width_frac >= vc_priv->xsize_frac)
 		return -EAGAIN;
 
@@ -317,52 +350,52 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y,
 				end = dst;
 			}
 			break;
-#ifdef CONFIG_VIDEO_BPP16
 		case VIDEO_BPP16: {
 			uint16_t *dst = (uint16_t *)line + xoff;
 			int i;
 
-			for (i = 0; i < width; i++) {
-				int val = *bits;
-				int out;
-
-				if (vid_priv->colour_bg)
-					val = 255 - val;
-				out = val >> 3 |
-					(val >> 2) << 5 |
-					(val >> 3) << 11;
-				if (vid_priv->colour_fg)
-					*dst++ |= out;
-				else
-					*dst++ &= out;
-				bits++;
+			if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+				for (i = 0; i < width; i++) {
+					int val = *bits;
+					int out;
+
+					if (vid_priv->colour_bg)
+						val = 255 - val;
+					out = val >> 3 |
+						(val >> 2) << 5 |
+						(val >> 3) << 11;
+					if (vid_priv->colour_fg)
+						*dst++ |= out;
+					else
+						*dst++ &= out;
+					bits++;
+				}
+				end = dst;
 			}
-			end = dst;
 			break;
 		}
-#endif
-#ifdef CONFIG_VIDEO_BPP32
 		case VIDEO_BPP32: {
 			u32 *dst = (u32 *)line + xoff;
 			int i;
 
-			for (i = 0; i < width; i++) {
-				int val = *bits;
-				int out;
-
-				if (vid_priv->colour_bg)
-					val = 255 - val;
-				out = val | val << 8 | val << 16;
-				if (vid_priv->colour_fg)
-					*dst++ |= out;
-				else
-					*dst++ &= out;
-				bits++;
+			if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+				for (i = 0; i < width; i++) {
+					int val = *bits;
+					int out;
+
+					if (vid_priv->colour_bg)
+						val = 255 - val;
+					out = val | val << 8 | val << 16;
+					if (vid_priv->colour_fg)
+						*dst++ |= out;
+					else
+						*dst++ &= out;
+					bits++;
+				}
+				end = dst;
 			}
-			end = dst;
 			break;
 		}
-#endif
 		default:
 			free(data);
 			return -ENOSYS;
@@ -379,72 +412,6 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y,
 }
 
 /**
- * console_truetype_erase() - Erase a character
- *
- * This is used for backspace. We erase a square of the display within the
- * given bounds.
- *
- * @dev:	Device to update
- * @xstart:	X start position in pixels from the left
- * @ystart:	Y start position in pixels from the top
- * @xend:	X end position in pixels from the left
- * @yend:	Y end position  in pixels from the top
- * @clr:	Value to write
- * Return: 0 if OK, -ENOSYS if the display depth is not supported
- */
-static int console_truetype_erase(struct udevice *dev, int xstart, int ystart,
-				  int xend, int yend, int clr)
-{
-	struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
-	void *start, *line;
-	int pixels = xend - xstart;
-	int row, i, ret;
-
-	start = vid_priv->fb + ystart * vid_priv->line_length;
-	start += xstart * VNBYTES(vid_priv->bpix);
-	line = start;
-	for (row = ystart; row < yend; row++) {
-		switch (vid_priv->bpix) {
-#ifdef CONFIG_VIDEO_BPP8
-		case VIDEO_BPP8: {
-			uint8_t *dst = line;
-
-			for (i = 0; i < pixels; i++)
-				*dst++ = clr;
-			break;
-		}
-#endif
-#ifdef CONFIG_VIDEO_BPP16
-		case VIDEO_BPP16: {
-			uint16_t *dst = line;
-
-			for (i = 0; i < pixels; i++)
-				*dst++ = clr;
-			break;
-		}
-#endif
-#ifdef CONFIG_VIDEO_BPP32
-		case VIDEO_BPP32: {
-			uint32_t *dst = line;
-
-			for (i = 0; i < pixels; i++)
-				*dst++ = clr;
-			break;
-		}
-#endif
-		default:
-			return -ENOSYS;
-		}
-		line += vid_priv->line_length;
-	}
-	ret = vidconsole_sync_copy(dev, start, line);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-/**
  * console_truetype_backspace() - Handle a backspace operation
  *
  * This clears the previous character so that the console looks as if it had
@@ -482,9 +449,9 @@ static int console_truetype_backspace(struct udevice *dev)
 	else
 		xend = vid_priv->xsize;
 
-	console_truetype_erase(dev, VID_TO_PIXEL(pos->xpos_frac), pos->ypos,
-			       xend, pos->ypos + vc_priv->y_charsize,
-			       vid_priv->colour_bg);
+	video_fill_part(vid_dev, VID_TO_PIXEL(pos->xpos_frac), pos->ypos,
+			xend, pos->ypos + vc_priv->y_charsize,
+			vid_priv->colour_bg);
 
 	/* Move the cursor back to where it was when we pushed this record */
 	vc_priv->xcur_frac = pos->xpos_frac;
@@ -680,8 +647,8 @@ static void select_metrics(struct udevice *dev, struct console_tt_metrics *met)
 	vc_priv->tab_width_frac = VID_TO_POS(met->font_size) * 8 / 2;
 }
 
-static int truetype_select_font(struct udevice *dev, const char *name,
-				uint size)
+static int get_metrics(struct udevice *dev, const char *name, uint size,
+		       struct console_tt_metrics **metp)
 {
 	struct console_tt_priv *priv = dev_get_priv(dev);
 	struct console_tt_metrics *met;
@@ -719,11 +686,70 @@ static int truetype_select_font(struct udevice *dev, const char *name,
 		met = priv->metrics;
 	}
 
+	*metp = met;
+
+	return 0;
+}
+
+static int truetype_select_font(struct udevice *dev, const char *name,
+				uint size)
+{
+	struct console_tt_metrics *met;
+	int ret;
+
+	ret = get_metrics(dev, name, size, &met);
+	if (ret)
+		return log_msg_ret("sel", ret);
+
 	select_metrics(dev, met);
 
 	return 0;
 }
 
+int truetype_measure(struct udevice *dev, const char *name, uint size,
+		     const char *text, struct vidconsole_bbox *bbox)
+{
+	struct console_tt_metrics *met;
+	stbtt_fontinfo *font;
+	int lsb, advance;
+	const char *s;
+	int width;
+	int last;
+	int ret;
+
+	ret = get_metrics(dev, name, size, &met);
+	if (ret)
+		return log_msg_ret("sel", ret);
+
+	bbox->valid = false;
+	if (!*text)
+		return 0;
+
+	font = &met->font;
+	width = 0;
+	for (last = 0, s = text; *s; s++) {
+		int ch = *s;
+
+		/* Used kerning to fine-tune the position of this character */
+		if (last)
+			width += stbtt_GetCodepointKernAdvance(font, last, ch);
+
+		/* First get some basic metrics about this character */
+		stbtt_GetCodepointHMetrics(font, ch, &advance, &lsb);
+
+		width += advance;
+		last = ch;
+	}
+
+	bbox->valid = true;
+	bbox->x0 = 0;
+	bbox->y0 = 0;
+	bbox->x1 = tt_ceil((double)width * met->scale);
+	bbox->y1 = met->font_size;
+
+	return 0;
+}
+
 const char *console_truetype_get_font_size(struct udevice *dev, uint *sizep)
 {
 	struct console_tt_priv *priv = dev_get_priv(dev);
@@ -775,6 +801,7 @@ struct vidconsole_ops console_truetype_ops = {
 	.get_font	= console_truetype_get_font,
 	.get_font_size	= console_truetype_get_font_size,
 	.select_font	= truetype_select_font,
+	.measure	= truetype_measure,
 };
 
 U_BOOT_DRIVER(vidconsole_truetype) = {
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
index 92e388ac1e..22fef7e882 100644
--- a/drivers/video/dw_mipi_dsi.c
+++ b/drivers/video/dw_mipi_dsi.c
@@ -538,9 +538,9 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 		break;
 	}
 
-	if (device->mode_flags & DISPLAY_FLAGS_VSYNC_HIGH)
+	if (timings->flags & DISPLAY_FLAGS_VSYNC_LOW)
 		val |= VSYNC_ACTIVE_LOW;
-	if (device->mode_flags & DISPLAY_FLAGS_HSYNC_HIGH)
+	if (timings->flags & DISPLAY_FLAGS_HSYNC_LOW)
 		val |= HSYNC_ACTIVE_LOW;
 
 	dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
diff --git a/drivers/video/himax-hx8394.c b/drivers/video/himax-hx8394.c
new file mode 100644
index 0000000000..63637b4db0
--- /dev/null
+++ b/drivers/video/himax-hx8394.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Ondrej Jirman <megi@xff.cz>
+ */
+#include <common.h>
+#include <backlight.h>
+#include <dm.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <asm/gpio.h>
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+
+struct hx8394_panel_priv {
+	struct udevice *reg_vcc;
+	struct udevice *reg_iovcc;
+	struct gpio_desc reset;
+	struct udevice *backlight;
+};
+
+static const struct display_timing default_timing = {
+	.pixelclock.typ		= 74250000,
+	.hactive.typ		= 720,
+	.hfront_porch.typ	= 40,
+	.hback_porch.typ	= 40,
+	.hsync_len.typ		= 46,
+	.vactive.typ		= 1440,
+	.vfront_porch.typ	= 7,
+	.vback_porch.typ	= 9,
+	.vsync_len.typ		= 7,
+	.flags			= DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
+};
+
+#define dsi_dcs_write_seq(device, seq...) do {					\
+		static const u8 d[] = { seq };					\
+		int ret;							\
+		ret = mipi_dsi_dcs_write_buffer(device, d, ARRAY_SIZE(d));	\
+		if (ret < 0)							\
+			return ret;						\
+	} while (0)
+
+static int hx8394_init_sequence(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *device = plat->device;
+	int ret;
+
+	dsi_dcs_write_seq(device, 0xb9, 0xff, 0x83, 0x94);
+	dsi_dcs_write_seq(device, 0xb1, 0x48, 0x11, 0x71, 0x09, 0x32, 0x24,
+			  0x71, 0x31, 0x55, 0x30);
+	dsi_dcs_write_seq(device, 0xba, 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
+	dsi_dcs_write_seq(device, 0xb2, 0x00, 0x80, 0x78, 0x0c, 0x07);
+	dsi_dcs_write_seq(device, 0xb4, 0x12, 0x63, 0x12, 0x63, 0x12, 0x63,
+			  0x01, 0x0c, 0x7c, 0x55, 0x00, 0x3f, 0x12, 0x6b, 0x12,
+			  0x6b, 0x12, 0x6b, 0x01, 0x0c, 0x7c);
+	dsi_dcs_write_seq(device, 0xd3, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x1c,
+			  0x00, 0x00, 0x32, 0x10, 0x09, 0x00, 0x09, 0x32, 0x15,
+			  0xad, 0x05, 0xad, 0x32, 0x00, 0x00, 0x00, 0x00, 0x37,
+			  0x03, 0x0b, 0x0b, 0x37, 0x00, 0x00, 0x00, 0x0c, 0x40);
+	dsi_dcs_write_seq(device, 0xd5, 0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b,
+			  0x1a, 0x1a, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
+			  0x07, 0x20, 0x21, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+			  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x24, 0x25, 0x18,
+			  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+			  0x18, 0x18);
+	dsi_dcs_write_seq(device, 0xd6, 0x18, 0x18, 0x19, 0x19, 0x1b, 0x1b,
+			  0x1a, 0x1a, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
+			  0x00, 0x25, 0x24, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+			  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x18,
+			  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+			  0x18, 0x18);
+	dsi_dcs_write_seq(device, 0xe0, 0x00, 0x04, 0x0c, 0x12, 0x14, 0x18,
+			  0x1a, 0x18, 0x31, 0x3f, 0x4d, 0x4c, 0x54, 0x65, 0x6b,
+			  0x70, 0x7f, 0x82, 0x7e, 0x8a, 0x99, 0x4a, 0x48, 0x49,
+			  0x4b, 0x4a, 0x4c, 0x4b, 0x7f, 0x00, 0x04, 0x0c, 0x11,
+			  0x13, 0x17, 0x1a, 0x18, 0x31, 0x3f, 0x4d, 0x4c, 0x54,
+			  0x65, 0x6b, 0x70, 0x7f, 0x82, 0x7e, 0x8a, 0x99, 0x4a,
+			  0x48, 0x49, 0x4b, 0x4a, 0x4c, 0x4b, 0x7f);
+	dsi_dcs_write_seq(device, 0xcc, 0x0b);
+	dsi_dcs_write_seq(device, 0xc0, 0x1f, 0x31);
+	dsi_dcs_write_seq(device, 0xb6, 0x7d, 0x7d);
+	dsi_dcs_write_seq(device, 0xd4, 0x02);
+	dsi_dcs_write_seq(device, 0xbd, 0x01);
+	dsi_dcs_write_seq(device, 0xb1, 0x00);
+	dsi_dcs_write_seq(device, 0xbd, 0x00);
+	dsi_dcs_write_seq(device, 0xc6, 0xed);
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(device);
+	if (ret)
+		return ret;
+
+	/* Panel is operational 120 msec after reset */
+	mdelay(120);
+
+	ret = mipi_dsi_dcs_set_display_on(device);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int hx8394_panel_enable_backlight(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *device = plat->device;
+	struct hx8394_panel_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = mipi_dsi_attach(device);
+	if (ret < 0) {
+		printf("mipi_dsi_attach failed %d\n", ret);
+		return ret;
+	}
+
+	ret = hx8394_init_sequence(dev);
+	if (ret) {
+		printf("hx8394_init_sequence failed %d\n", ret);
+		return ret;
+	}
+
+	if (priv->backlight) {
+		ret = backlight_enable(priv->backlight);
+		if (ret) {
+			printf("backlight enabled failed %d\n", ret);
+			return ret;
+		}
+
+		backlight_set_brightness(priv->backlight, 60);
+	}
+
+	mdelay(10);
+
+	return 0;
+}
+
+static int hx8394_panel_get_display_timing(struct udevice *dev,
+					   struct display_timing *timings)
+{
+	memcpy(timings, &default_timing, sizeof(*timings));
+
+	return 0;
+}
+
+static int hx8394_panel_of_to_plat(struct udevice *dev)
+{
+	struct hx8394_panel_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
+		ret =  device_get_supply_regulator(dev, "vcc-supply",
+						   &priv->reg_vcc);
+		if (ret && ret != -ENOENT) {
+			dev_err(dev, "Warning: cannot get vcc supply\n");
+			return ret;
+		}
+
+		ret =  device_get_supply_regulator(dev, "iovcc-supply",
+						   &priv->reg_iovcc);
+		if (ret && ret != -ENOENT) {
+			dev_err(dev, "Warning: cannot get iovcc supply\n");
+			return ret;
+		}
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+					   "backlight", &priv->backlight);
+	if (ret)
+		dev_warn(dev, "failed to get backlight\n");
+
+	ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
+				   GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "warning: cannot get reset GPIO (%d)\n", ret);
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int hx8394_panel_probe(struct udevice *dev)
+{
+	struct hx8394_panel_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	int ret;
+
+	dm_gpio_set_value(&priv->reset, true);
+
+	if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
+		dev_dbg(dev, "enable vcc '%s'\n", priv->reg_vcc->name);
+		ret = regulator_set_enable(priv->reg_vcc, true);
+		if (ret)
+			return ret;
+
+		dev_dbg(dev, "enable iovcc '%s'\n", priv->reg_iovcc->name);
+		ret = regulator_set_enable(priv->reg_iovcc, true);
+		if (ret) {
+			regulator_set_enable(priv->reg_vcc, false);
+			return ret;
+		}
+	}
+
+	mdelay(5);
+	dm_gpio_set_value(&priv->reset, false);
+
+	mdelay(180);
+
+	/* fill characteristics of DSI data link */
+	plat->lanes = 4;
+	plat->format = MIPI_DSI_FMT_RGB888;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO |
+			   MIPI_DSI_MODE_VIDEO_BURST;
+
+	return 0;
+}
+
+static const struct panel_ops hx8394_panel_ops = {
+	.enable_backlight = hx8394_panel_enable_backlight,
+	.get_display_timing = hx8394_panel_get_display_timing,
+};
+
+static const struct udevice_id hx8394_panel_ids[] = {
+	{ .compatible = "hannstar,hsd060bhw4" },
+	{ }
+};
+
+U_BOOT_DRIVER(hx8394_panel) = {
+	.name		= "hx8394_panel",
+	.id		= UCLASS_PANEL,
+	.of_match	= hx8394_panel_ids,
+	.ops		= &hx8394_panel_ops,
+	.of_to_plat	= hx8394_panel_of_to_plat,
+	.probe		= hx8394_panel_probe,
+	.plat_auto	= sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto	= sizeof(struct hx8394_panel_priv),
+};
diff --git a/drivers/video/ivybridge_igd.c b/drivers/video/ivybridge_igd.c
index 9264dd6770..c2cc976618 100644
--- a/drivers/video/ivybridge_igd.c
+++ b/drivers/video/ivybridge_igd.c
@@ -774,8 +774,7 @@ static int bd82x6x_video_probe(struct udevice *dev)
 
 	/* Use write-combining for the graphics memory, 256MB */
 	fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base;
-	mtrr_add_request(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
-	mtrr_commit(true);
+	mtrr_set_next_var(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
 
 	return 0;
 }
diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index d7c096923b..aa0e292866 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -14,6 +14,7 @@
 #include <pwm.h>
 #include <asm/gpio.h>
 #include <linux/delay.h>
+#include <linux/math64.h>
 #include <power/regulator.h>
 
 /**
@@ -59,12 +60,14 @@ struct pwm_backlight_priv {
 
 static int set_pwm(struct pwm_backlight_priv *priv)
 {
+	u64 width;
 	uint duty_cycle;
 	int ret;
 
 	if (priv->period_ns) {
-		duty_cycle = priv->period_ns * (priv->cur_level - priv->min_level) /
-			(priv->max_level - priv->min_level);
+		width = priv->period_ns * (priv->cur_level - priv->min_level);
+		duty_cycle = div_u64(width,
+				     (priv->max_level - priv->min_level));
 		ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns,
 				     duty_cycle);
 	} else {
diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index ca548a60b7..0852b53ebe 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -18,6 +18,7 @@
 #include <panel.h>
 #include <phy-mipi-dphy.h>
 #include <reset.h>
+#include <syscon.h>
 #include <video_bridge.h>
 #include <dm/device_compat.h>
 #include <dm/lists.h>
@@ -30,6 +31,9 @@
 #include <dm/device-internal.h>
 #include <linux/bitops.h>
 
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
+
 #define USEC_PER_SEC	1000000L
 
 /*
@@ -130,6 +134,32 @@
 #define HS_RX_CONTROL_OF_LANE_2				0x84
 #define HS_RX_CONTROL_OF_LANE_3				0x94
 
+#define DW_MIPI_NEEDS_PHY_CFG_CLK	BIT(0)
+#define DW_MIPI_NEEDS_GRF_CLK		BIT(1)
+
+#define RK3399_GRF_SOC_CON20		0x6250
+#define RK3399_DSI0_LCDC_SEL		BIT(0)
+#define RK3399_DSI1_LCDC_SEL		BIT(4)
+
+#define RK3399_GRF_SOC_CON22		0x6258
+#define RK3399_DSI0_TURNREQUEST		(0xf << 12)
+#define RK3399_DSI0_TURNDISABLE		(0xf << 8)
+#define RK3399_DSI0_FORCETXSTOPMODE	(0xf << 4)
+#define RK3399_DSI0_FORCERXMODE		(0xf << 0)
+
+#define RK3399_GRF_SOC_CON23		0x625c
+#define RK3399_DSI1_TURNDISABLE		(0xf << 12)
+#define RK3399_DSI1_FORCETXSTOPMODE	(0xf << 8)
+#define RK3399_DSI1_FORCERXMODE		(0xf << 4)
+#define RK3399_DSI1_ENABLE		(0xf << 0)
+
+#define RK3399_GRF_SOC_CON24		0x6260
+#define RK3399_TXRX_MASTERSLAVEZ	BIT(7)
+#define RK3399_TXRX_ENABLECLK		BIT(6)
+#define RK3399_TXRX_BASEDIR		BIT(5)
+#define RK3399_TXRX_SRC_SEL_ISP0	BIT(4)
+#define RK3399_TXRX_TURNREQUEST		GENMASK(3, 0)
+
 #define RK3568_GRF_VO_CON2		0x0368
 #define RK3568_DSI0_SKEWCALHS		(0x1f << 11)
 #define RK3568_DSI0_FORCETXSTOPMODE	(0xf << 4)
@@ -197,6 +227,7 @@ struct dw_rockchip_dsi_priv {
 	struct mipi_dsi_device device;
 	void __iomem *base;
 	struct udevice *panel;
+	void __iomem *grf;
 
 	/* Optional external dphy */
 	struct phy phy;
@@ -204,6 +235,8 @@ struct dw_rockchip_dsi_priv {
 
 	struct clk *pclk;
 	struct clk *ref;
+	struct clk *grf_clk;
+	struct clk *phy_cfg_clk;
 	struct reset_ctl *rst;
 	unsigned int lane_mbps; /* per lane */
 	u16 input_div;
@@ -344,7 +377,7 @@ static int dsi_phy_init(void *priv_data)
 	struct dw_rockchip_dsi_priv *dsi = dev_get_priv(dev);
 	int ret, i, vco;
 
-	if (&dsi->phy) {
+	if (dsi->phy.dev) {
 		ret = generic_phy_configure(&dsi->phy, &dsi->phy_opts);
 		if (ret) {
 			dev_err(dsi->dsi_host,
@@ -460,7 +493,7 @@ static int dsi_phy_init(void *priv_data)
 	dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
 			      BIT(5) | ns2bc(dsi, 100));
 
-	return ret;
+	return 0;
 }
 
 static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags)
@@ -505,7 +538,6 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
 	unsigned int _prediv, best_prediv;
 	unsigned long _fbdiv, best_fbdiv;
 	unsigned long min_delta = ULONG_MAX;
-	unsigned int pllref_clk;
 
 	bpp = mipi_dsi_pixel_format_to_bpp(format);
 	if (bpp < 0) {
@@ -527,7 +559,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
 	}
 
 	/* for external phy only the mipi_dphy_config is necessary */
-	if (&dsi->phy) {
+	if (dsi->phy.dev) {
 		phy_mipi_dphy_get_default_config(timings->pixelclock.typ  * 10 / 8,
 						 bpp, lanes,
 						 &dsi->phy_opts);
@@ -537,7 +569,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
 		return 0;
 	}
 
-	pllref_clk = clk_get_rate(dsi->ref);
+	fin = clk_get_rate(dsi->ref);
 	fout = target_mbps * USEC_PER_SEC;
 
 	/* constraint: 5Mhz <= Fref / N <= 40MHz */
@@ -753,16 +785,13 @@ static int dw_mipi_dsi_rockchip_set_bl(struct udevice *dev, int percent)
 static void dw_mipi_dsi_rockchip_config(struct dw_rockchip_dsi_priv *dsi)
 {
 	if (dsi->cdata->lanecfg1_grf_reg)
-		dsi_write(dsi, dsi->cdata->lanecfg1_grf_reg,
-			  dsi->cdata->lanecfg1);
+		rk_setreg(dsi->grf + dsi->cdata->lanecfg1_grf_reg, dsi->cdata->lanecfg1);
 
 	if (dsi->cdata->lanecfg2_grf_reg)
-		dsi_write(dsi, dsi->cdata->lanecfg2_grf_reg,
-			  dsi->cdata->lanecfg2);
+		rk_setreg(dsi->grf + dsi->cdata->lanecfg2_grf_reg, dsi->cdata->lanecfg2);
 
 	if (dsi->cdata->enable_grf_reg)
-		dsi_write(dsi, dsi->cdata->enable_grf_reg,
-			  dsi->cdata->enable);
+		rk_setreg(dsi->grf + dsi->cdata->enable_grf_reg, dsi->cdata->enable);
 }
 
 static int dw_mipi_dsi_rockchip_bind(struct udevice *dev)
@@ -795,6 +824,8 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev)
 		return -EINVAL;
 	}
 
+	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
 	i = 0;
 	while (cdata[i].reg) {
 		if (cdata[i].reg == (fdt_addr_t)priv->base) {
@@ -815,33 +846,58 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev)
 	 * NULL if it's not initialized.
 	 */
 	ret = generic_phy_get_by_name(dev, "dphy", &priv->phy);
-	if ((ret) && (ret != -ENODEV)) {
+	if (ret && ret != -ENODATA) {
 		dev_err(dev, "failed to get mipi dphy: %d\n", ret);
-		return -EINVAL;
+		return ret;
 	}
 
 	priv->pclk = devm_clk_get(dev, "pclk");
 	if (IS_ERR(priv->pclk)) {
+		ret = PTR_ERR(priv->pclk);
 		dev_err(dev, "peripheral clock get error %d\n", ret);
 		return ret;
 	}
 
 	/* Get a ref clock only if not using an external phy. */
-	if (&priv->phy) {
+	if (priv->phy.dev) {
 		dev_dbg(dev, "setting priv->ref to NULL\n");
 		priv->ref = NULL;
 
 	} else {
 		priv->ref = devm_clk_get(dev, "ref");
-		if (ret) {
+		if (IS_ERR(priv->ref)) {
+			ret = PTR_ERR(priv->ref);
 			dev_err(dev, "pll reference clock get error %d\n", ret);
 			return ret;
 		}
 	}
 
+	if (cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
+		priv->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
+		if (IS_ERR(priv->phy_cfg_clk)) {
+			ret = PTR_ERR(priv->phy_cfg_clk);
+			dev_err(dev, "phy_cfg_clk clock get error %d\n", ret);
+			return ret;
+		}
+
+		clk_enable(priv->phy_cfg_clk);
+	}
+
+	if (cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
+		priv->grf_clk = devm_clk_get(dev, "grf");
+		if (IS_ERR(priv->grf_clk)) {
+			ret = PTR_ERR(priv->grf_clk);
+			dev_err(dev, "grf_clk clock get error %d\n", ret);
+			return ret;
+		}
+
+		clk_enable(priv->grf_clk);
+	}
+
 	priv->rst = devm_reset_control_get_by_index(device->dev, 0);
 	if (IS_ERR(priv->rst)) {
-		dev_err(dev, "missing dsi hardware reset\n");
+		ret = PTR_ERR(priv->rst);
+		dev_err(dev, "missing dsi hardware reset %d\n", ret);
 		return ret;
 	}
 
@@ -858,6 +914,52 @@ struct video_bridge_ops dw_mipi_dsi_rockchip_ops = {
 	.set_backlight = dw_mipi_dsi_rockchip_set_bl,
 };
 
+static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
+	{
+		.reg = 0xff960000,
+		.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
+		.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
+		.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
+					    RK3399_DSI0_LCDC_SEL),
+
+		.lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
+		.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
+					     RK3399_DSI0_TURNDISABLE |
+					     RK3399_DSI0_FORCETXSTOPMODE |
+					     RK3399_DSI0_FORCERXMODE),
+
+		.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
+		.max_data_lanes = 4,
+	},
+	{
+		.reg = 0xff968000,
+		.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
+		.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
+		.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
+					    RK3399_DSI1_LCDC_SEL),
+
+		.lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
+		.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
+					     RK3399_DSI1_FORCETXSTOPMODE |
+					     RK3399_DSI1_FORCERXMODE |
+					     RK3399_DSI1_ENABLE),
+
+		.lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
+		.lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
+					  RK3399_TXRX_ENABLECLK,
+					  RK3399_TXRX_MASTERSLAVEZ |
+					  RK3399_TXRX_ENABLECLK |
+					  RK3399_TXRX_BASEDIR),
+
+		.enable_grf_reg = RK3399_GRF_SOC_CON23,
+		.enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
+
+		.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
+		.max_data_lanes = 4,
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
 	{
 		.reg = 0xfe060000,
@@ -881,6 +983,9 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
 };
 
 static const struct udevice_id dw_mipi_dsi_rockchip_dt_ids[] = {
+	{ .compatible = "rockchip,rk3399-mipi-dsi",
+	  .data = (long)&rk3399_chip_data,
+	},
 	{ .compatible = "rockchip,rk3568-mipi-dsi",
 	  .data = (long)&rk3568_chip_data,
 	},
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index dab9902fda..c514e2a0e4 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -432,7 +432,7 @@ int rk_vop_probe(struct udevice *dev)
 	ret = reset_assert(&ahb_rst);
 	if (ret) {
 		dev_err(dev, "failed to assert ahb reset (ret=%d)\n", ret);
-	return ret;
+		return ret;
 	}
 	udelay(20);
 
diff --git a/drivers/video/stb_truetype.h b/drivers/video/stb_truetype.h
index 438bfce468..c6973bb353 100644
--- a/drivers/video/stb_truetype.h
+++ b/drivers/video/stb_truetype.h
@@ -1,11 +1,21 @@
-// stb_truetype.h - v1.08 - public domain
-// authored from 2009-2015 by Sean Barrett / RAD Game Tools
+// stb_truetype.h - v1.26 - public domain
+// authored from 2009-2021 by Sean Barrett / RAD Game Tools
+//
+// =======================================================================
+//
+//    NO SECURITY GUARANTEE -- DO NOT USE THIS ON UNTRUSTED FONT FILES
+//
+// This library does no range checking of the offsets found in the file,
+// meaning an attacker can use it to read arbitrary memory.
+//
+// =======================================================================
 //
 //   This library processes TrueType files:
 //        parse files
 //        extract glyph metrics
 //        extract glyph shapes
 //        render glyphs to one-channel bitmaps with antialiasing (box filter)
+//        render glyphs to one-channel SDF bitmaps (signed-distance field/function)
 //
 //   Todo:
 //        non-MS cmaps
@@ -20,58 +30,68 @@
 //
 //   Mikko Mononen: compound shape support, more cmap formats
 //   Tor Andersson: kerning, subpixel rendering
-//
-//   Bug/warning reports/fixes:
-//       "Zer" on mollyrocket (with fix)
-//       Cass Everitt
-//       stoiko (Haemimont Games)
-//       Brian Hook 
-//       Walter van Niftrik
-//       David Gow
-//       David Given
-//       Ivan-Assen Ivanov
-//       Anthony Pesch
-//       Johan Duparc
-//       Hou Qiming
-//       Fabian "ryg" Giesen
-//       Martins Mozeiko
-//       Cap Petschulat
-//       Omar Cornut
-//       github:aloucks
-//       Peter LaValle
-//       Sergey Popov
-//       Giumo X. Clanjor
-//       Higor Euripedes
+//   Dougall Johnson: OpenType / Type 2 font handling
+//   Daniel Ribeiro Maciel: basic GPOS-based kerning
 //
 //   Misc other:
 //       Ryan Gordon
+//       Simon Glass
+//       github:IntellectualKitty
+//       Imanol Celaya
+//       Daniel Ribeiro Maciel
+//
+//   Bug/warning reports/fixes:
+//       "Zer" on mollyrocket       Fabian "ryg" Giesen   github:NiLuJe
+//       Cass Everitt               Martins Mozeiko       github:aloucks
+//       stoiko (Haemimont Games)   Cap Petschulat        github:oyvindjam
+//       Brian Hook                 Omar Cornut           github:vassvik
+//       Walter van Niftrik         Ryan Griege
+//       David Gow                  Peter LaValle
+//       David Given                Sergey Popov
+//       Ivan-Assen Ivanov          Giumo X. Clanjor
+//       Anthony Pesch              Higor Euripedes
+//       Johan Duparc               Thomas Fields
+//       Hou Qiming                 Derek Vinyard
+//       Rob Loach                  Cort Stratton
+//       Kenney Phillis Jr.         Brian Costabile
+//       Ken Voskuil (kaesve)
 //
 // VERSION HISTORY
 //
+//   1.26 (2021-08-28) fix broken rasterizer
+//   1.25 (2021-07-11) many fixes
+//   1.24 (2020-02-05) fix warning
+//   1.23 (2020-02-02) query SVG data for glyphs; query whole kerning table (but only kern not GPOS)
+//   1.22 (2019-08-11) minimize missing-glyph duplication; fix kerning if both 'GPOS' and 'kern' are defined
+//   1.21 (2019-02-25) fix warning
+//   1.20 (2019-02-07) PackFontRange skips missing codepoints; GetScaleFontVMetrics()
+//   1.19 (2018-02-11) GPOS kerning, STBTT_fmod
+//   1.18 (2018-01-29) add missing function
+//   1.17 (2017-07-23) make more arguments const; doc fix
+//   1.16 (2017-07-12) SDF support
+//   1.15 (2017-03-03) make more arguments const
+//   1.14 (2017-01-16) num-fonts-in-TTC function
+//   1.13 (2017-01-02) support OpenType fonts, certain Apple fonts
+//   1.12 (2016-10-25) suppress warnings about casting away const with -Wcast-qual
+//   1.11 (2016-04-02) fix unused-variable warning
+//   1.10 (2016-04-02) user-defined fabs(); rare memory leak; remove duplicate typedef
+//   1.09 (2016-01-16) warning fix; avoid crash on outofmem; use allocation userdata properly
 //   1.08 (2015-09-13) document stbtt_Rasterize(); fixes for vertical & horizontal edges
 //   1.07 (2015-08-01) allow PackFontRanges to accept arrays of sparse codepoints;
 //                     variant PackFontRanges to pack and render in separate phases;
 //                     fix stbtt_GetFontOFfsetForIndex (never worked for non-0 input?);
 //                     fixed an assert() bug in the new rasterizer
 //                     replace assert() with STBTT_assert() in new rasterizer
-//   1.06 (2015-07-14) performance improvements (~35% faster on x86 and x64 on test machine)
-//                     also more precise AA rasterizer, except if shapes overlap
-//                     remove need for STBTT_sort
-//   1.05 (2015-04-15) fix misplaced definitions for STBTT_STATIC
-//   1.04 (2015-04-15) typo in example
-//   1.03 (2015-04-12) STBTT_STATIC, fix memory leak in new packing, various fixes
 //
 //   Full history can be found at the end of this file.
 //
 // LICENSE
 //
-//   This software is in the public domain. Where that dedication is not
-//   recognized, you are granted a perpetual, irrevocable license to copy,
-//   distribute, and modify this file as you see fit.
+//   See end of file for license information.
 //
 // USAGE
 //
-//   Include this file in whatever places neeed to refer to it. In ONE C/C++
+//   Include this file in whatever places need to refer to it. In ONE C/C++
 //   file, write:
 //      #define STB_TRUETYPE_IMPLEMENTATION
 //   before the #include of this file. This expands out the actual
@@ -87,14 +107,15 @@
 //   Improved 3D API (more shippable):
 //           #include "stb_rect_pack.h"           -- optional, but you really want it
 //           stbtt_PackBegin()
-//           stbtt_PackSetOversample()            -- for improved quality on small fonts
+//           stbtt_PackSetOversampling()          -- for improved quality on small fonts
 //           stbtt_PackFontRanges()               -- pack and renders
 //           stbtt_PackEnd()
 //           stbtt_GetPackedQuad()
 //
 //   "Load" a font file from a memory buffer (you have to keep the buffer loaded)
 //           stbtt_InitFont()
-//           stbtt_GetFontOffsetForIndex()        -- use for TTC font collections
+//           stbtt_GetFontOffsetForIndex()        -- indexing for TTC font collections
+//           stbtt_GetNumberOfFonts()             -- number of fonts for TTC font collections
 //
 //   Render a unicode codepoint to a bitmap
 //           stbtt_GetCodepointBitmap()           -- allocates and returns a bitmap
@@ -104,6 +125,7 @@
 //   Character advance/positioning
 //           stbtt_GetCodepointHMetrics()
 //           stbtt_GetFontVMetrics()
+//           stbtt_GetFontVMetricsOS2()
 //           stbtt_GetCodepointKernAdvance()
 //
 //   Starting with version 1.06, the rasterizer was replaced with a new,
@@ -159,7 +181,7 @@
 //         measurement for describing font size, defined as 72 points per inch.
 //         stb_truetype provides a point API for compatibility. However, true
 //         "per inch" conventions don't make much sense on computer displays
-//         since they different monitors have different number of pixels per
+//         since different monitors have different number of pixels per
 //         inch. For example, Windows traditionally uses a convention that
 //         there are 96 pixels per inch, thus making 'inch' measurements have
 //         nothing to do with inches, and thus effectively defining a point to
@@ -169,6 +191,39 @@
 //         for non-commercial fonts, thus making fonts scaled in points
 //         according to the TrueType spec incoherently sized in practice.
 //
+// DETAILED USAGE:
+//
+//  Scale:
+//    Select how high you want the font to be, in points or pixels.
+//    Call ScaleForPixelHeight or ScaleForMappingEmToPixels to compute
+//    a scale factor SF that will be used by all other functions.
+//
+//  Baseline:
+//    You need to select a y-coordinate that is the baseline of where
+//    your text will appear. Call GetFontBoundingBox to get the baseline-relative
+//    bounding box for all characters. SF*-y0 will be the distance in pixels
+//    that the worst-case character could extend above the baseline, so if
+//    you want the top edge of characters to appear at the top of the
+//    screen where y=0, then you would set the baseline to SF*-y0.
+//
+//  Current point:
+//    Set the current point where the first character will appear. The
+//    first character could extend left of the current point; this is font
+//    dependent. You can either choose a current point that is the leftmost
+//    point and hope, or add some padding, or check the bounding box or
+//    left-side-bearing of the first character to be displayed and set
+//    the current point based on that.
+//
+//  Displaying a character:
+//    Compute the bounding box of the character. It will contain signed values
+//    relative to <current_point, baseline>. I.e. if it returns x0,y0,x1,y1,
+//    then the character should be displayed in the rectangle from
+//    <current_point+SF*x0, baseline+SF*y0> to <current_point+SF*x1,baseline+SF*y1).
+//
+//  Advancing for the next character:
+//    Call GlyphHMetrics, and compute 'current_point += SF * advance'.
+//
+//
 // ADVANCED USAGE
 //
 //   Quality:
@@ -203,19 +258,6 @@
 //   recommend it.
 //
 //
-// SOURCE STATISTICS (based on v0.6c, 2050 LOC)
-//
-//   Documentation & header file        520 LOC  \___ 660 LOC documentation
-//   Sample code                        140 LOC  /
-//   Truetype parsing                   620 LOC  ---- 620 LOC TrueType
-//   Software rasterization             240 LOC  \                           .
-//   Curve tesselation                  120 LOC   \__ 550 LOC Bitmap creation
-//   Bitmap management                  100 LOC   /
-//   Baked bitmap interface              70 LOC  /
-//   Font name matching & access        150 LOC  ---- 150 
-//   C runtime library abstraction       60 LOC  ----  60
-//
-//
 // PERFORMANCE MEASUREMENTS FOR 1.06:
 //
 //                      32-bit     64-bit
@@ -230,8 +272,8 @@
 ////  SAMPLE PROGRAMS
 ////
 //
-//  Incomplete text-in-3d-api example, which draws quads properly aligned to be lossless
-//
+//  Incomplete text-in-3d-api example, which draws quads properly aligned to be lossless.
+//  See "tests/truetype_demo_win32.c" for a complete version.
 #if 0
 #define STB_TRUETYPE_IMPLEMENTATION  // force following include to generate implementation
 #include "stb_truetype.h"
@@ -257,6 +299,8 @@ void my_stbtt_initfont(void)
 void my_stbtt_print(float x, float y, char *text)
 {
    // assume orthographic projection with units = screen pixels, origin at top left
+   glEnable(GL_BLEND);
+   glBlendFunc(GL_SRC_ALPHA, GL_ONE_MINUS_SRC_ALPHA);
    glEnable(GL_TEXTURE_2D);
    glBindTexture(GL_TEXTURE_2D, ftex);
    glBegin(GL_QUADS);
@@ -264,10 +308,10 @@ void my_stbtt_print(float x, float y, char *text)
       if (*text >= 32 && *text < 128) {
          stbtt_aligned_quad q;
          stbtt_GetBakedQuad(cdata, 512,512, *text-32, &x,&y,&q,1);//1=opengl & d3d10+,0=d3d9
-         glTexCoord2f(q.s0,q.t1); glVertex2f(q.x0,q.y0);
-         glTexCoord2f(q.s1,q.t1); glVertex2f(q.x1,q.y0);
-         glTexCoord2f(q.s1,q.t0); glVertex2f(q.x1,q.y1);
-         glTexCoord2f(q.s0,q.t0); glVertex2f(q.x0,q.y1);
+         glTexCoord2f(q.s0,q.t0); glVertex2f(q.x0,q.y0);
+         glTexCoord2f(q.s1,q.t0); glVertex2f(q.x1,q.y0);
+         glTexCoord2f(q.s1,q.t1); glVertex2f(q.x1,q.y1);
+         glTexCoord2f(q.s0,q.t1); glVertex2f(q.x0,q.y1);
       }
       ++text;
    }
@@ -305,7 +349,7 @@ int main(int argc, char **argv)
    }
    return 0;
 }
-#endif 
+#endif
 //
 // Output:
 //
@@ -319,9 +363,9 @@ int main(int argc, char **argv)
 //  :@@.  M@M
 //   @@@o@@@@
 //   :M@@V:@@.
-//  
+//
 //////////////////////////////////////////////////////////////////////////////
-// 
+//
 // Complete program: print "Hello World!" banner, with bugs
 //
 #if 0
@@ -375,7 +419,8 @@ int main(int arg, char **argv)
 ////   INTEGRATION WITH YOUR CODEBASE
 ////
 ////   The following sections allow you to supply alternate definitions
-////   of C library functions used by stb_truetype.
+////   of C library functions used by stb_truetype, e.g. if you don't
+////   link with the C runtime library.
 
 #ifdef STB_TRUETYPE_IMPLEMENTATION
    // #define your own (u)stbtt_int8/16/32 before including to override this
@@ -391,7 +436,7 @@ int main(int arg, char **argv)
    typedef char stbtt__check_size32[sizeof(stbtt_int32)==4 ? 1 : -1];
    typedef char stbtt__check_size16[sizeof(stbtt_int16)==2 ? 1 : -1];
 
-   // #define your own STBTT_ifloor/STBTT_iceil() to avoid math.h
+   // e.g. #define your own STBTT_ifloor/STBTT_iceil() to avoid math.h
    #ifndef STBTT_ifloor
    #include <math.h>
    #define STBTT_ifloor(x)   ((int) floor(x))
@@ -401,6 +446,18 @@ int main(int arg, char **argv)
    #ifndef STBTT_sqrt
    #include <math.h>
    #define STBTT_sqrt(x)      sqrt(x)
+   #define STBTT_pow(x,y)     pow(x,y)
+   #endif
+
+   #ifndef STBTT_fmod
+   #include <math.h>
+   #define STBTT_fmod(x,y)    fmod(x,y)
+   #endif
+
+   #ifndef STBTT_cos
+   #include <math.h>
+   #define STBTT_cos(x)       cos(x)
+   #define STBTT_acos(x)      acos(x)
    #endif
 
    #ifndef STBTT_fabs
@@ -452,6 +509,14 @@ int main(int arg, char **argv)
 extern "C" {
 #endif
 
+// private structure
+typedef struct
+{
+   unsigned char *data;
+   int cursor;
+   int size;
+} stbtt__buf;
+
 //////////////////////////////////////////////////////////////////////////////
 //
 // TEXTURE BAKING API
@@ -481,7 +546,7 @@ typedef struct
    float x1,y1,s1,t1; // bottom-right
 } stbtt_aligned_quad;
 
-STBTT_DEF void stbtt_GetBakedQuad(stbtt_bakedchar *chardata, int pw, int ph,  // same data as above
+STBTT_DEF void stbtt_GetBakedQuad(const stbtt_bakedchar *chardata, int pw, int ph,  // same data as above
                                int char_index,             // character to display
                                float *xpos, float *ypos,   // pointers to current position in screen pixel space
                                stbtt_aligned_quad *q,      // output: quad to draw
@@ -496,6 +561,9 @@ STBTT_DEF void stbtt_GetBakedQuad(stbtt_bakedchar *chardata, int pw, int ph,  //
 //
 // It's inefficient; you might want to c&p it and optimize it.
 
+STBTT_DEF void stbtt_GetScaledFontVMetrics(const unsigned char *fontdata, int index, float size, float *ascent, float *descent, float *lineGap);
+// Query the font vertical metrics without having to create a font first.
+
 
 //////////////////////////////////////////////////////////////////////////////
 //
@@ -520,7 +588,7 @@ typedef struct stbrp_rect stbrp_rect;
 STBTT_DEF int  stbtt_PackBegin(stbtt_pack_context *spc, unsigned char *pixels, int width, int height, int stride_in_bytes, int padding, void *alloc_context);
 // Initializes a packing context stored in the passed-in stbtt_pack_context.
 // Future calls using this context will pack characters into the bitmap passed
-// in here: a 1-channel bitmap that is weight x height. stride_in_bytes is
+// in here: a 1-channel bitmap that is width * height. stride_in_bytes is
 // the distance from one row to the next (or 0 to mean they are packed tightly
 // together). "padding" is the amount of padding to leave between each
 // character (normally you want '1' for bitmaps you'll use as textures with
@@ -533,7 +601,7 @@ STBTT_DEF void stbtt_PackEnd  (stbtt_pack_context *spc);
 
 #define STBTT_POINT_SIZE(x)   (-(x))
 
-STBTT_DEF int  stbtt_PackFontRange(stbtt_pack_context *spc, unsigned char *fontdata, int font_index, float font_size,
+STBTT_DEF int  stbtt_PackFontRange(stbtt_pack_context *spc, const unsigned char *fontdata, int font_index, float font_size,
                                 int first_unicode_char_in_range, int num_chars_in_range, stbtt_packedchar *chardata_for_range);
 // Creates character bitmaps from the font_index'th font found in fontdata (use
 // font_index=0 if you don't know what that is). It creates num_chars_in_range
@@ -558,7 +626,7 @@ typedef struct
    unsigned char h_oversample, v_oversample; // don't set these, they're used internally
 } stbtt_pack_range;
 
-STBTT_DEF int  stbtt_PackFontRanges(stbtt_pack_context *spc, unsigned char *fontdata, int font_index, stbtt_pack_range *ranges, int num_ranges);
+STBTT_DEF int  stbtt_PackFontRanges(stbtt_pack_context *spc, const unsigned char *fontdata, int font_index, stbtt_pack_range *ranges, int num_ranges);
 // Creates character bitmaps from multiple ranges of characters stored in
 // ranges. This will usually create a better-packed bitmap than multiple
 // calls to stbtt_PackFontRange. Note that you can call this multiple
@@ -580,19 +648,25 @@ STBTT_DEF void stbtt_PackSetOversampling(stbtt_pack_context *spc, unsigned int h
 // To use with PackFontRangesGather etc., you must set it before calls
 // call to PackFontRangesGatherRects.
 
-STBTT_DEF void stbtt_GetPackedQuad(stbtt_packedchar *chardata, int pw, int ph,  // same data as above
+STBTT_DEF void stbtt_PackSetSkipMissingCodepoints(stbtt_pack_context *spc, int skip);
+// If skip != 0, this tells stb_truetype to skip any codepoints for which
+// there is no corresponding glyph. If skip=0, which is the default, then
+// codepoints without a glyph recived the font's "missing character" glyph,
+// typically an empty box by convention.
+
+STBTT_DEF void stbtt_GetPackedQuad(const stbtt_packedchar *chardata, int pw, int ph,  // same data as above
                                int char_index,             // character to display
                                float *xpos, float *ypos,   // pointers to current position in screen pixel space
                                stbtt_aligned_quad *q,      // output: quad to draw
                                int align_to_integer);
 
-STBTT_DEF int  stbtt_PackFontRangesGatherRects(stbtt_pack_context *spc, stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects);
+STBTT_DEF int  stbtt_PackFontRangesGatherRects(stbtt_pack_context *spc, const stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects);
 STBTT_DEF void stbtt_PackFontRangesPackRects(stbtt_pack_context *spc, stbrp_rect *rects, int num_rects);
-STBTT_DEF int  stbtt_PackFontRangesRenderIntoRects(stbtt_pack_context *spc, stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects);
+STBTT_DEF int  stbtt_PackFontRangesRenderIntoRects(stbtt_pack_context *spc, const stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects);
 // Calling these functions in sequence is roughly equivalent to calling
 // stbtt_PackFontRanges(). If you more control over the packing of multiple
 // fonts, or if you want to pack custom data into a font texture, take a look
-// at the source to of stbtt_PackFontRanges() and create a custom version 
+// at the source to of stbtt_PackFontRanges() and create a custom version
 // using these functions, e.g. call GatherRects multiple times,
 // building up a single array of rects, then call PackRects once,
 // then call RenderIntoRects repeatedly. This may result in a
@@ -608,6 +682,7 @@ struct stbtt_pack_context {
    int   height;
    int   stride_in_bytes;
    int   padding;
+   int   skip_missing;
    unsigned int   h_oversample, v_oversample;
    unsigned char *pixels;
    void  *nodes;
@@ -619,18 +694,23 @@ struct stbtt_pack_context {
 //
 //
 
+STBTT_DEF int stbtt_GetNumberOfFonts(const unsigned char *data);
+// This function will determine the number of fonts in a font file.  TrueType
+// collection (.ttc) files may contain multiple fonts, while TrueType font
+// (.ttf) files only contain one font. The number of fonts can be used for
+// indexing with the previous function where the index is between zero and one
+// less than the total fonts. If an error occurs, -1 is returned.
+
 STBTT_DEF int stbtt_GetFontOffsetForIndex(const unsigned char *data, int index);
 // Each .ttf/.ttc file may have more than one font. Each font has a sequential
 // index number starting from 0. Call this function to get the font offset for
 // a given index; it returns -1 if the index is out of range. A regular .ttf
 // file will only define one font and it always be at offset 0, so it will
-// return '0' for index 0, and -1 for all other indices. You can just skip
-// this step if you know it's that kind of font.
+// return '0' for index 0, and -1 for all other indices.
 
-
-// The following structure is defined publically so you can declare one on
+// The following structure is defined publicly so you can declare one on
 // the stack or as a global or etc, but you should treat it as opaque.
-typedef struct stbtt_fontinfo
+struct stbtt_fontinfo
 {
    void           * userdata;
    unsigned char  * data;              // pointer to .ttf file
@@ -638,10 +718,17 @@ typedef struct stbtt_fontinfo
 
    int numGlyphs;                     // number of glyphs, needed for range checking
 
-   int loca,head,glyf,hhea,hmtx,kern; // table locations as offset from start of .ttf
+   int loca,head,glyf,hhea,hmtx,kern,gpos,svg; // table locations as offset from start of .ttf
    int index_map;                     // a cmap mapping for our chosen character encoding
    int indexToLocFormat;              // format needed to map from glyph index to glyph
-} stbtt_fontinfo;
+
+   stbtt__buf cff;                    // cff font data
+   stbtt__buf charstrings;            // the charstring index
+   stbtt__buf gsubrs;                 // global charstring subroutines index
+   stbtt__buf subrs;                  // private charstring subroutines index
+   stbtt__buf fontdicts;              // array of font dicts
+   stbtt__buf fdselect;               // map from glyph to fontdict
+};
 
 STBTT_DEF int stbtt_InitFont(stbtt_fontinfo *info, const unsigned char *data, int offset);
 // Given an offset into the file that defines a font, this function builds
@@ -660,6 +747,7 @@ STBTT_DEF int stbtt_FindGlyphIndex(const stbtt_fontinfo *info, int unicode_codep
 // and you want a speed-up, call this function with the character you're
 // going to process, then use glyph-based functions instead of the
 // codepoint-based functions.
+// Returns 0 if the character codepoint is not defined in the font.
 
 
 //////////////////////////////////////////////////////////////////////////////
@@ -688,6 +776,12 @@ STBTT_DEF void stbtt_GetFontVMetrics(const stbtt_fontinfo *info, int *ascent, in
 //   these are expressed in unscaled coordinates, so you must multiply by
 //   the scale factor for a given size
 
+STBTT_DEF int  stbtt_GetFontVMetricsOS2(const stbtt_fontinfo *info, int *typoAscent, int *typoDescent, int *typoLineGap);
+// analogous to GetFontVMetrics, but returns the "typographic" values from the OS/2
+// table (specific to MS/Windows TTF files).
+//
+// Returns 1 on success (table present), 0 on failure.
+
 STBTT_DEF void stbtt_GetFontBoundingBox(const stbtt_fontinfo *info, int *x0, int *y0, int *x1, int *y1);
 // the bounding box around all possible characters
 
@@ -707,6 +801,18 @@ STBTT_DEF int  stbtt_GetGlyphKernAdvance(const stbtt_fontinfo *info, int glyph1,
 STBTT_DEF int  stbtt_GetGlyphBox(const stbtt_fontinfo *info, int glyph_index, int *x0, int *y0, int *x1, int *y1);
 // as above, but takes one or more glyph indices for greater efficiency
 
+typedef struct stbtt_kerningentry
+{
+   int glyph1; // use stbtt_FindGlyphIndex
+   int glyph2;
+   int advance;
+} stbtt_kerningentry;
+
+STBTT_DEF int  stbtt_GetKerningTableLength(const stbtt_fontinfo *info);
+STBTT_DEF int  stbtt_GetKerningTable(const stbtt_fontinfo *info, stbtt_kerningentry* table, int table_length);
+// Retrieves a complete list of all of the kerning pairs provided by the font
+// stbtt_GetKerningTable never writes more than table_length entries and returns how many entries it did write.
+// The table will be sorted by (a.glyph1 == b.glyph1)?(a.glyph2 < b.glyph2):(a.glyph1 < b.glyph1)
 
 //////////////////////////////////////////////////////////////////////////////
 //
@@ -718,7 +824,8 @@ STBTT_DEF int  stbtt_GetGlyphBox(const stbtt_fontinfo *info, int glyph_index, in
    enum {
       STBTT_vmove=1,
       STBTT_vline,
-      STBTT_vcurve
+      STBTT_vcurve,
+      STBTT_vcubic
    };
 #endif
 
@@ -727,7 +834,7 @@ STBTT_DEF int  stbtt_GetGlyphBox(const stbtt_fontinfo *info, int glyph_index, in
    #define stbtt_vertex_type short // can't use stbtt_int16 because that's not visible in the header file
    typedef struct
    {
-      stbtt_vertex_type x,y,cx,cy;
+      stbtt_vertex_type x,y,cx,cy,cx1,cy1;
       unsigned char type,padding;
    } stbtt_vertex;
 #endif
@@ -740,7 +847,7 @@ STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, s
 // returns # of vertices and fills *vertices with the pointer to them
 //   these are expressed in "unscaled" coordinates
 //
-// The shape is a series of countours. Each one starts with
+// The shape is a series of contours. Each one starts with
 // a STBTT_moveto, then consists of a series of mixed
 // STBTT_lineto and STBTT_curveto segments. A lineto
 // draws a line from previous endpoint to its x,y; a curveto
@@ -750,6 +857,12 @@ STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, s
 STBTT_DEF void stbtt_FreeShape(const stbtt_fontinfo *info, stbtt_vertex *vertices);
 // frees the data allocated above
 
+STBTT_DEF unsigned char *stbtt_FindSVGDoc(const stbtt_fontinfo *info, int gl);
+STBTT_DEF int stbtt_GetCodepointSVG(const stbtt_fontinfo *info, int unicode_codepoint, const char **svg);
+STBTT_DEF int stbtt_GetGlyphSVG(const stbtt_fontinfo *info, int gl, const char **svg);
+// fills svg with the character's SVG data.
+// returns data size or 0 if SVG not found.
+
 //////////////////////////////////////////////////////////////////////////////
 //
 // BITMAP RENDERING
@@ -781,6 +894,10 @@ STBTT_DEF void stbtt_MakeCodepointBitmapSubpixel(const stbtt_fontinfo *info, uns
 // same as stbtt_MakeCodepointBitmap, but you can specify a subpixel
 // shift for the character
 
+STBTT_DEF void stbtt_MakeCodepointBitmapSubpixelPrefilter(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int oversample_x, int oversample_y, float *sub_x, float *sub_y, int codepoint);
+// same as stbtt_MakeCodepointBitmapSubpixel, but prefiltering
+// is performed (see stbtt_PackSetOversampling)
+
 STBTT_DEF void stbtt_GetCodepointBitmapBox(const stbtt_fontinfo *font, int codepoint, float scale_x, float scale_y, int *ix0, int *iy0, int *ix1, int *iy1);
 // get the bbox of the bitmap centered around the glyph origin; so the
 // bitmap width is ix1-ix0, height is iy1-iy0, and location to place
@@ -798,6 +915,7 @@ STBTT_DEF unsigned char *stbtt_GetGlyphBitmap(const stbtt_fontinfo *info, float
 STBTT_DEF unsigned char *stbtt_GetGlyphBitmapSubpixel(const stbtt_fontinfo *info, float scale_x, float scale_y, float shift_x, float shift_y, int glyph, int *width, int *height, int *xoff, int *yoff);
 STBTT_DEF void stbtt_MakeGlyphBitmap(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, int glyph);
 STBTT_DEF void stbtt_MakeGlyphBitmapSubpixel(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int glyph);
+STBTT_DEF void stbtt_MakeGlyphBitmapSubpixelPrefilter(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int oversample_x, int oversample_y, float *sub_x, float *sub_y, int glyph);
 STBTT_DEF void stbtt_GetGlyphBitmapBox(const stbtt_fontinfo *font, int glyph, float scale_x, float scale_y, int *ix0, int *iy0, int *ix1, int *iy1);
 STBTT_DEF void stbtt_GetGlyphBitmapBoxSubpixel(const stbtt_fontinfo *font, int glyph, float scale_x, float scale_y,float shift_x, float shift_y, int *ix0, int *iy0, int *ix1, int *iy1);
 
@@ -822,6 +940,64 @@ STBTT_DEF void stbtt_Rasterize(stbtt__bitmap *result,        // 1-channel bitmap
 
 //////////////////////////////////////////////////////////////////////////////
 //
+// Signed Distance Function (or Field) rendering
+
+STBTT_DEF void stbtt_FreeSDF(unsigned char *bitmap, void *userdata);
+// frees the SDF bitmap allocated below
+
+STBTT_DEF unsigned char * stbtt_GetGlyphSDF(const stbtt_fontinfo *info, float scale, int glyph, int padding, unsigned char onedge_value, float pixel_dist_scale, int *width, int *height, int *xoff, int *yoff);
+STBTT_DEF unsigned char * stbtt_GetCodepointSDF(const stbtt_fontinfo *info, float scale, int codepoint, int padding, unsigned char onedge_value, float pixel_dist_scale, int *width, int *height, int *xoff, int *yoff);
+// These functions compute a discretized SDF field for a single character, suitable for storing
+// in a single-channel texture, sampling with bilinear filtering, and testing against
+// larger than some threshold to produce scalable fonts.
+//        info              --  the font
+//        scale             --  controls the size of the resulting SDF bitmap, same as it would be creating a regular bitmap
+//        glyph/codepoint   --  the character to generate the SDF for
+//        padding           --  extra "pixels" around the character which are filled with the distance to the character (not 0),
+//                                 which allows effects like bit outlines
+//        onedge_value      --  value 0-255 to test the SDF against to reconstruct the character (i.e. the isocontour of the character)
+//        pixel_dist_scale  --  what value the SDF should increase by when moving one SDF "pixel" away from the edge (on the 0..255 scale)
+//                                 if positive, > onedge_value is inside; if negative, < onedge_value is inside
+//        width,height      --  output height & width of the SDF bitmap (including padding)
+//        xoff,yoff         --  output origin of the character
+//        return value      --  a 2D array of bytes 0..255, width*height in size
+//
+// pixel_dist_scale & onedge_value are a scale & bias that allows you to make
+// optimal use of the limited 0..255 for your application, trading off precision
+// and special effects. SDF values outside the range 0..255 are clamped to 0..255.
+//
+// Example:
+//      scale = stbtt_ScaleForPixelHeight(22)
+//      padding = 5
+//      onedge_value = 180
+//      pixel_dist_scale = 180/5.0 = 36.0
+//
+//      This will create an SDF bitmap in which the character is about 22 pixels
+//      high but the whole bitmap is about 22+5+5=32 pixels high. To produce a filled
+//      shape, sample the SDF at each pixel and fill the pixel if the SDF value
+//      is greater than or equal to 180/255. (You'll actually want to antialias,
+//      which is beyond the scope of this example.) Additionally, you can compute
+//      offset outlines (e.g. to stroke the character border inside & outside,
+//      or only outside). For example, to fill outside the character up to 3 SDF
+//      pixels, you would compare against (180-36.0*3)/255 = 72/255. The above
+//      choice of variables maps a range from 5 pixels outside the shape to
+//      2 pixels inside the shape to 0..255; this is intended primarily for apply
+//      outside effects only (the interior range is needed to allow proper
+//      antialiasing of the font at *smaller* sizes)
+//
+// The function computes the SDF analytically at each SDF pixel, not by e.g.
+// building a higher-res bitmap and approximating it. In theory the quality
+// should be as high as possible for an SDF of this size & representation, but
+// unclear if this is true in practice (perhaps building a higher-res bitmap
+// and computing from that can allow drop-out prevention).
+//
+// The algorithm has not been optimized at all, so expect it to be slow
+// if computing lots of characters or very large sizes.
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+//
 // Finding the right font...
 //
 // You should really just solve this offline, keep your own tables
@@ -943,6 +1119,158 @@ typedef int stbtt__test_oversample_pow2[(STBTT_MAX_OVERSAMPLE & (STBTT_MAX_OVERS
 #define STBTT_RASTERIZER_VERSION 2
 #endif
 
+#ifdef _MSC_VER
+#define STBTT__NOTUSED(v)  (void)(v)
+#else
+#define STBTT__NOTUSED(v)  (void)sizeof(v)
+#endif
+
+//////////////////////////////////////////////////////////////////////////
+//
+// stbtt__buf helpers to parse data from file
+//
+
+static stbtt_uint8 stbtt__buf_get8(stbtt__buf *b)
+{
+   if (b->cursor >= b->size)
+      return 0;
+   return b->data[b->cursor++];
+}
+
+static stbtt_uint8 stbtt__buf_peek8(stbtt__buf *b)
+{
+   if (b->cursor >= b->size)
+      return 0;
+   return b->data[b->cursor];
+}
+
+static void stbtt__buf_seek(stbtt__buf *b, int o)
+{
+   STBTT_assert(!(o > b->size || o < 0));
+   b->cursor = (o > b->size || o < 0) ? b->size : o;
+}
+
+static void stbtt__buf_skip(stbtt__buf *b, int o)
+{
+   stbtt__buf_seek(b, b->cursor + o);
+}
+
+static stbtt_uint32 stbtt__buf_get(stbtt__buf *b, int n)
+{
+   stbtt_uint32 v = 0;
+   int i;
+   STBTT_assert(n >= 1 && n <= 4);
+   for (i = 0; i < n; i++)
+      v = (v << 8) | stbtt__buf_get8(b);
+   return v;
+}
+
+static stbtt__buf stbtt__new_buf(const void *p, size_t size)
+{
+   stbtt__buf r;
+   STBTT_assert(size < 0x40000000);
+   r.data = (stbtt_uint8*) p;
+   r.size = (int) size;
+   r.cursor = 0;
+   return r;
+}
+
+#define stbtt__buf_get16(b)  stbtt__buf_get((b), 2)
+#define stbtt__buf_get32(b)  stbtt__buf_get((b), 4)
+
+static stbtt__buf stbtt__buf_range(const stbtt__buf *b, int o, int s)
+{
+   stbtt__buf r = stbtt__new_buf(NULL, 0);
+   if (o < 0 || s < 0 || o > b->size || s > b->size - o) return r;
+   r.data = b->data + o;
+   r.size = s;
+   return r;
+}
+
+static stbtt__buf stbtt__cff_get_index(stbtt__buf *b)
+{
+   int count, start, offsize;
+   start = b->cursor;
+   count = stbtt__buf_get16(b);
+   if (count) {
+      offsize = stbtt__buf_get8(b);
+      STBTT_assert(offsize >= 1 && offsize <= 4);
+      stbtt__buf_skip(b, offsize * count);
+      stbtt__buf_skip(b, stbtt__buf_get(b, offsize) - 1);
+   }
+   return stbtt__buf_range(b, start, b->cursor - start);
+}
+
+static stbtt_uint32 stbtt__cff_int(stbtt__buf *b)
+{
+   int b0 = stbtt__buf_get8(b);
+   if (b0 >= 32 && b0 <= 246)       return b0 - 139;
+   else if (b0 >= 247 && b0 <= 250) return (b0 - 247)*256 + stbtt__buf_get8(b) + 108;
+   else if (b0 >= 251 && b0 <= 254) return -(b0 - 251)*256 - stbtt__buf_get8(b) - 108;
+   else if (b0 == 28)               return stbtt__buf_get16(b);
+   else if (b0 == 29)               return stbtt__buf_get32(b);
+   STBTT_assert(0);
+   return 0;
+}
+
+static void stbtt__cff_skip_operand(stbtt__buf *b) {
+   int v, b0 = stbtt__buf_peek8(b);
+   STBTT_assert(b0 >= 28);
+   if (b0 == 30) {
+      stbtt__buf_skip(b, 1);
+      while (b->cursor < b->size) {
+         v = stbtt__buf_get8(b);
+         if ((v & 0xF) == 0xF || (v >> 4) == 0xF)
+            break;
+      }
+   } else {
+      stbtt__cff_int(b);
+   }
+}
+
+static stbtt__buf stbtt__dict_get(stbtt__buf *b, int key)
+{
+   stbtt__buf_seek(b, 0);
+   while (b->cursor < b->size) {
+      int start = b->cursor, end, op;
+      while (stbtt__buf_peek8(b) >= 28)
+         stbtt__cff_skip_operand(b);
+      end = b->cursor;
+      op = stbtt__buf_get8(b);
+      if (op == 12)  op = stbtt__buf_get8(b) | 0x100;
+      if (op == key) return stbtt__buf_range(b, start, end-start);
+   }
+   return stbtt__buf_range(b, 0, 0);
+}
+
+static void stbtt__dict_get_ints(stbtt__buf *b, int key, int outcount, stbtt_uint32 *out)
+{
+   int i;
+   stbtt__buf operands = stbtt__dict_get(b, key);
+   for (i = 0; i < outcount && operands.cursor < operands.size; i++)
+      out[i] = stbtt__cff_int(&operands);
+}
+
+static int stbtt__cff_index_count(stbtt__buf *b)
+{
+   stbtt__buf_seek(b, 0);
+   return stbtt__buf_get16(b);
+}
+
+static stbtt__buf stbtt__cff_index_get(stbtt__buf b, int i)
+{
+   int count, offsize, start, end;
+   stbtt__buf_seek(&b, 0);
+   count = stbtt__buf_get16(&b);
+   offsize = stbtt__buf_get8(&b);
+   STBTT_assert(i >= 0 && i < count);
+   STBTT_assert(offsize >= 1 && offsize <= 4);
+   stbtt__buf_skip(&b, i*offsize);
+   start = stbtt__buf_get(&b, offsize);
+   end = stbtt__buf_get(&b, offsize);
+   return stbtt__buf_range(&b, 2+(count+1)*offsize+start, end - start);
+}
+
 //////////////////////////////////////////////////////////////////////////
 //
 // accessors to parse data from file
@@ -955,32 +1283,22 @@ typedef int stbtt__test_oversample_pow2[(STBTT_MAX_OVERSAMPLE & (STBTT_MAX_OVERS
 #define ttCHAR(p)     (* (stbtt_int8 *) (p))
 #define ttFixed(p)    ttLONG(p)
 
-#if defined(STB_TRUETYPE_BIGENDIAN) && !defined(ALLOW_UNALIGNED_TRUETYPE)
-
-   #define ttUSHORT(p)   (* (stbtt_uint16 *) (p))
-   #define ttSHORT(p)    (* (stbtt_int16 *) (p))
-   #define ttULONG(p)    (* (stbtt_uint32 *) (p))
-   #define ttLONG(p)     (* (stbtt_int32 *) (p))
-
-#else
-
-   static stbtt_uint16 ttUSHORT(const stbtt_uint8 *p) { return p[0]*256 + p[1]; }
-   static stbtt_int16 ttSHORT(const stbtt_uint8 *p)   { return p[0]*256 + p[1]; }
-   static stbtt_uint32 ttULONG(const stbtt_uint8 *p)  { return (p[0]<<24) + (p[1]<<16) + (p[2]<<8) + p[3]; }
-   static stbtt_int32 ttLONG(const stbtt_uint8 *p)    { return (p[0]<<24) + (p[1]<<16) + (p[2]<<8) + p[3]; }
-
-#endif
+static stbtt_uint16 ttUSHORT(stbtt_uint8 *p) { return p[0]*256 + p[1]; }
+static stbtt_int16 ttSHORT(stbtt_uint8 *p)   { return p[0]*256 + p[1]; }
+static stbtt_uint32 ttULONG(stbtt_uint8 *p)  { return (p[0]<<24) + (p[1]<<16) + (p[2]<<8) + p[3]; }
+static stbtt_int32 ttLONG(stbtt_uint8 *p)    { return (p[0]<<24) + (p[1]<<16) + (p[2]<<8) + p[3]; }
 
 #define stbtt_tag4(p,c0,c1,c2,c3) ((p)[0] == (c0) && (p)[1] == (c1) && (p)[2] == (c2) && (p)[3] == (c3))
 #define stbtt_tag(p,str)           stbtt_tag4(p,str[0],str[1],str[2],str[3])
 
-static int stbtt__isfont(const stbtt_uint8 *font)
+static int stbtt__isfont(stbtt_uint8 *font)
 {
    // check the version number
    if (stbtt_tag4(font, '1',0,0,0))  return 1; // TrueType 1
    if (stbtt_tag(font, "typ1"))   return 1; // TrueType with type 1 font -- we don't support this!
    if (stbtt_tag(font, "OTTO"))   return 1; // OpenType with CFF
    if (stbtt_tag4(font, 0,1,0,0)) return 1; // OpenType 1.0
+   if (stbtt_tag(font, "true"))   return 1; // Apple specification for TrueType fonts
    return 0;
 }
 
@@ -998,7 +1316,7 @@ static stbtt_uint32 stbtt__find_table(stbtt_uint8 *data, stbtt_uint32 fontstart,
    return 0;
 }
 
-STBTT_DEF int stbtt_GetFontOffsetForIndex(const unsigned char *font_collection, int index)
+static int stbtt_GetFontOffsetForIndex_internal(unsigned char *font_collection, int index)
 {
    // if it's just a font, there's only one valid index
    if (stbtt__isfont(font_collection))
@@ -1017,14 +1335,59 @@ STBTT_DEF int stbtt_GetFontOffsetForIndex(const unsigned char *font_collection,
    return -1;
 }
 
-STBTT_DEF int stbtt_InitFont(stbtt_fontinfo *info, const unsigned char *data2, int fontstart)
+static int stbtt_GetNumberOfFonts_internal(unsigned char *font_collection)
+{
+   // if it's just a font, there's only one valid font
+   if (stbtt__isfont(font_collection))
+      return 1;
+
+   // check if it's a TTC
+   if (stbtt_tag(font_collection, "ttcf")) {
+      // version 1?
+      if (ttULONG(font_collection+4) == 0x00010000 || ttULONG(font_collection+4) == 0x00020000) {
+         return ttLONG(font_collection+8);
+      }
+   }
+   return 0;
+}
+
+static stbtt__buf stbtt__get_subrs(stbtt__buf cff, stbtt__buf fontdict)
+{
+   stbtt_uint32 subrsoff = 0, private_loc[2] = { 0, 0 };
+   stbtt__buf pdict;
+   stbtt__dict_get_ints(&fontdict, 18, 2, private_loc);
+   if (!private_loc[1] || !private_loc[0]) return stbtt__new_buf(NULL, 0);
+   pdict = stbtt__buf_range(&cff, private_loc[1], private_loc[0]);
+   stbtt__dict_get_ints(&pdict, 19, 1, &subrsoff);
+   if (!subrsoff) return stbtt__new_buf(NULL, 0);
+   stbtt__buf_seek(&cff, private_loc[1]+subrsoff);
+   return stbtt__cff_get_index(&cff);
+}
+
+// since most people won't use this, find this table the first time it's needed
+static int stbtt__get_svg(stbtt_fontinfo *info)
+{
+   stbtt_uint32 t;
+   if (info->svg < 0) {
+      t = stbtt__find_table(info->data, info->fontstart, "SVG ");
+      if (t) {
+         stbtt_uint32 offset = ttULONG(info->data + t + 2);
+         info->svg = t + offset;
+      } else {
+         info->svg = 0;
+      }
+   }
+   return info->svg;
+}
+
+static int stbtt_InitFont_internal(stbtt_fontinfo *info, unsigned char *data, int fontstart)
 {
-   stbtt_uint8 *data = (stbtt_uint8 *) data2;
    stbtt_uint32 cmap, t;
    stbtt_int32 i,numTables;
 
    info->data = data;
    info->fontstart = fontstart;
+   info->cff = stbtt__new_buf(NULL, 0);
 
    cmap = stbtt__find_table(data, fontstart, "cmap");       // required
    info->loca = stbtt__find_table(data, fontstart, "loca"); // required
@@ -1033,8 +1396,62 @@ STBTT_DEF int stbtt_InitFont(stbtt_fontinfo *info, const unsigned char *data2, i
    info->hhea = stbtt__find_table(data, fontstart, "hhea"); // required
    info->hmtx = stbtt__find_table(data, fontstart, "hmtx"); // required
    info->kern = stbtt__find_table(data, fontstart, "kern"); // not required
-   if (!cmap || !info->loca || !info->head || !info->glyf || !info->hhea || !info->hmtx)
+   info->gpos = stbtt__find_table(data, fontstart, "GPOS"); // not required
+
+   if (!cmap || !info->head || !info->hhea || !info->hmtx)
       return 0;
+   if (info->glyf) {
+      // required for truetype
+      if (!info->loca) return 0;
+   } else {
+      // initialization for CFF / Type2 fonts (OTF)
+      stbtt__buf b, topdict, topdictidx;
+      stbtt_uint32 cstype = 2, charstrings = 0, fdarrayoff = 0, fdselectoff = 0;
+      stbtt_uint32 cff;
+
+      cff = stbtt__find_table(data, fontstart, "CFF ");
+      if (!cff) return 0;
+
+      info->fontdicts = stbtt__new_buf(NULL, 0);
+      info->fdselect = stbtt__new_buf(NULL, 0);
+
+      // @TODO this should use size from table (not 512MB)
+      info->cff = stbtt__new_buf(data+cff, 512*1024*1024);
+      b = info->cff;
+
+      // read the header
+      stbtt__buf_skip(&b, 2);
+      stbtt__buf_seek(&b, stbtt__buf_get8(&b)); // hdrsize
+
+      // @TODO the name INDEX could list multiple fonts,
+      // but we just use the first one.
+      stbtt__cff_get_index(&b);  // name INDEX
+      topdictidx = stbtt__cff_get_index(&b);
+      topdict = stbtt__cff_index_get(topdictidx, 0);
+      stbtt__cff_get_index(&b);  // string INDEX
+      info->gsubrs = stbtt__cff_get_index(&b);
+
+      stbtt__dict_get_ints(&topdict, 17, 1, &charstrings);
+      stbtt__dict_get_ints(&topdict, 0x100 | 6, 1, &cstype);
+      stbtt__dict_get_ints(&topdict, 0x100 | 36, 1, &fdarrayoff);
+      stbtt__dict_get_ints(&topdict, 0x100 | 37, 1, &fdselectoff);
+      info->subrs = stbtt__get_subrs(b, topdict);
+
+      // we only support Type 2 charstrings
+      if (cstype != 2) return 0;
+      if (charstrings == 0) return 0;
+
+      if (fdarrayoff) {
+         // looks like a CID font
+         if (!fdselectoff) return 0;
+         stbtt__buf_seek(&b, fdarrayoff);
+         info->fontdicts = stbtt__cff_get_index(&b);
+         info->fdselect = stbtt__buf_range(&b, fdselectoff, b.size-fdselectoff);
+      }
+
+      stbtt__buf_seek(&b, charstrings);
+      info->charstrings = stbtt__cff_get_index(&b);
+   }
 
    t = stbtt__find_table(data, fontstart, "maxp");
    if (t)
@@ -1042,6 +1459,8 @@ STBTT_DEF int stbtt_InitFont(stbtt_fontinfo *info, const unsigned char *data2, i
    else
       info->numGlyphs = 0xffff;
 
+   info->svg = -1;
+
    // find a cmap encoding table we understand *now* to avoid searching
    // later. (todo: could make this installable)
    // the same regardless of glyph.
@@ -1125,12 +1544,12 @@ STBTT_DEF int stbtt_FindGlyphIndex(const stbtt_fontinfo *info, int unicode_codep
       search += 2;
 
       {
-         stbtt_uint16 offset, start;
+         stbtt_uint16 offset, start, last;
          stbtt_uint16 item = (stbtt_uint16) ((search - endCount) >> 1);
 
-         STBTT_assert(unicode_codepoint <= ttUSHORT(data + endCount + 2*item));
          start = ttUSHORT(data + index_map + 14 + segcount*2 + 2 + 2*item);
-         if (unicode_codepoint < start)
+         last = ttUSHORT(data + endCount + 2*item);
+         if (unicode_codepoint < start || unicode_codepoint > last)
             return 0;
 
          offset = ttUSHORT(data + index_map + 14 + segcount*6 + 2 + 2*item);
@@ -1185,6 +1604,8 @@ static int stbtt__GetGlyfOffset(const stbtt_fontinfo *info, int glyph_index)
 {
    int g1,g2;
 
+   STBTT_assert(!info->cff.size);
+
    if (glyph_index >= info->numGlyphs) return -1; // glyph index out of range
    if (info->indexToLocFormat >= 2)    return -1; // unknown index->glyph map format
 
@@ -1199,15 +1620,21 @@ static int stbtt__GetGlyfOffset(const stbtt_fontinfo *info, int glyph_index)
    return g1==g2 ? -1 : g1; // if length is 0, return -1
 }
 
+static int stbtt__GetGlyphInfoT2(const stbtt_fontinfo *info, int glyph_index, int *x0, int *y0, int *x1, int *y1);
+
 STBTT_DEF int stbtt_GetGlyphBox(const stbtt_fontinfo *info, int glyph_index, int *x0, int *y0, int *x1, int *y1)
 {
-   int g = stbtt__GetGlyfOffset(info, glyph_index);
-   if (g < 0) return 0;
+   if (info->cff.size) {
+      stbtt__GetGlyphInfoT2(info, glyph_index, x0, y0, x1, y1);
+   } else {
+      int g = stbtt__GetGlyfOffset(info, glyph_index);
+      if (g < 0) return 0;
 
-   if (x0) *x0 = ttSHORT(info->data + g + 2);
-   if (y0) *y0 = ttSHORT(info->data + g + 4);
-   if (x1) *x1 = ttSHORT(info->data + g + 6);
-   if (y1) *y1 = ttSHORT(info->data + g + 8);
+      if (x0) *x0 = ttSHORT(info->data + g + 2);
+      if (y0) *y0 = ttSHORT(info->data + g + 4);
+      if (x1) *x1 = ttSHORT(info->data + g + 6);
+      if (y1) *y1 = ttSHORT(info->data + g + 8);
+   }
    return 1;
 }
 
@@ -1219,7 +1646,10 @@ STBTT_DEF int stbtt_GetCodepointBox(const stbtt_fontinfo *info, int codepoint, i
 STBTT_DEF int stbtt_IsGlyphEmpty(const stbtt_fontinfo *info, int glyph_index)
 {
    stbtt_int16 numberOfContours;
-   int g = stbtt__GetGlyfOffset(info, glyph_index);
+   int g;
+   if (info->cff.size)
+      return stbtt__GetGlyphInfoT2(info, glyph_index, NULL, NULL, NULL, NULL) == 0;
+   g = stbtt__GetGlyfOffset(info, glyph_index);
    if (g < 0) return 1;
    numberOfContours = ttSHORT(info->data + g);
    return numberOfContours == 0;
@@ -1241,7 +1671,7 @@ static int stbtt__close_shape(stbtt_vertex *vertices, int num_vertices, int was_
    return num_vertices;
 }
 
-STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, stbtt_vertex **pvertices)
+static int stbtt__GetGlyphShapeTT(const stbtt_fontinfo *info, int glyph_index, stbtt_vertex **pvertices)
 {
    stbtt_int16 numberOfContours;
    stbtt_uint8 *endPtsOfContours;
@@ -1337,7 +1767,7 @@ STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, s
             if (i != 0)
                num_vertices = stbtt__close_shape(vertices, num_vertices, was_off, start_off, sx,sy,scx,scy,cx,cy);
 
-            // now start the new one               
+            // now start the new one
             start_off = !(flags & 1);
             if (start_off) {
                // if we start off with an off-curve point, then when we need to find a point on the curve
@@ -1379,7 +1809,7 @@ STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, s
          }
       }
       num_vertices = stbtt__close_shape(vertices, num_vertices, was_off, start_off, sx,sy,scx,scy,cx,cy);
-   } else if (numberOfContours == -1) {
+   } else if (numberOfContours < 0) {
       // Compound shapes.
       int more = 1;
       stbtt_uint8 *comp = data + g + 10;
@@ -1390,7 +1820,7 @@ STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, s
          int comp_num_verts = 0, i;
          stbtt_vertex *comp_verts = 0, *tmp = 0;
          float mtx[6] = {1,0,0,1,0,0}, m, n;
-         
+
          flags = ttSHORT(comp); comp+=2;
          gidx = ttSHORT(comp); comp+=2;
 
@@ -1420,7 +1850,7 @@ STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, s
             mtx[2] = ttSHORT(comp)/16384.0f; comp+=2;
             mtx[3] = ttSHORT(comp)/16384.0f; comp+=2;
          }
-         
+
          // Find transformation scales.
          m = (float) STBTT_sqrt(mtx[0]*mtx[0] + mtx[1]*mtx[1]);
          n = (float) STBTT_sqrt(mtx[2]*mtx[2] + mtx[3]*mtx[3]);
@@ -1446,7 +1876,7 @@ STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, s
                if (comp_verts) STBTT_free(comp_verts, info->userdata);
                return 0;
             }
-            if (num_vertices > 0) STBTT_memcpy(tmp, vertices, num_vertices*sizeof(stbtt_vertex));
+            if (num_vertices > 0 && vertices) STBTT_memcpy(tmp, vertices, num_vertices*sizeof(stbtt_vertex));
             STBTT_memcpy(tmp+num_vertices, comp_verts, comp_num_verts*sizeof(stbtt_vertex));
             if (vertices) STBTT_free(vertices, info->userdata);
             vertices = tmp;
@@ -1456,9 +1886,6 @@ STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, s
          // More components ?
          more = flags & (1<<5);
       }
-   } else if (numberOfContours < 0) {
-      // @TODO other compound variations?
-      STBTT_assert(0);
    } else {
       // numberOfCounters == 0, do nothing
    }
@@ -1467,6 +1894,414 @@ STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, s
    return num_vertices;
 }
 
+typedef struct
+{
+   int bounds;
+   int started;
+   float first_x, first_y;
+   float x, y;
+   stbtt_int32 min_x, max_x, min_y, max_y;
+
+   stbtt_vertex *pvertices;
+   int num_vertices;
+} stbtt__csctx;
+
+#define STBTT__CSCTX_INIT(bounds) {bounds,0, 0,0, 0,0, 0,0,0,0, NULL, 0}
+
+static void stbtt__track_vertex(stbtt__csctx *c, stbtt_int32 x, stbtt_int32 y)
+{
+   if (x > c->max_x || !c->started) c->max_x = x;
+   if (y > c->max_y || !c->started) c->max_y = y;
+   if (x < c->min_x || !c->started) c->min_x = x;
+   if (y < c->min_y || !c->started) c->min_y = y;
+   c->started = 1;
+}
+
+static void stbtt__csctx_v(stbtt__csctx *c, stbtt_uint8 type, stbtt_int32 x, stbtt_int32 y, stbtt_int32 cx, stbtt_int32 cy, stbtt_int32 cx1, stbtt_int32 cy1)
+{
+   if (c->bounds) {
+      stbtt__track_vertex(c, x, y);
+      if (type == STBTT_vcubic) {
+         stbtt__track_vertex(c, cx, cy);
+         stbtt__track_vertex(c, cx1, cy1);
+      }
+   } else {
+      stbtt_setvertex(&c->pvertices[c->num_vertices], type, x, y, cx, cy);
+      c->pvertices[c->num_vertices].cx1 = (stbtt_int16) cx1;
+      c->pvertices[c->num_vertices].cy1 = (stbtt_int16) cy1;
+   }
+   c->num_vertices++;
+}
+
+static void stbtt__csctx_close_shape(stbtt__csctx *ctx)
+{
+   if (ctx->first_x != ctx->x || ctx->first_y != ctx->y)
+      stbtt__csctx_v(ctx, STBTT_vline, (int)ctx->first_x, (int)ctx->first_y, 0, 0, 0, 0);
+}
+
+static void stbtt__csctx_rmove_to(stbtt__csctx *ctx, float dx, float dy)
+{
+   stbtt__csctx_close_shape(ctx);
+   ctx->first_x = ctx->x = ctx->x + dx;
+   ctx->first_y = ctx->y = ctx->y + dy;
+   stbtt__csctx_v(ctx, STBTT_vmove, (int)ctx->x, (int)ctx->y, 0, 0, 0, 0);
+}
+
+static void stbtt__csctx_rline_to(stbtt__csctx *ctx, float dx, float dy)
+{
+   ctx->x += dx;
+   ctx->y += dy;
+   stbtt__csctx_v(ctx, STBTT_vline, (int)ctx->x, (int)ctx->y, 0, 0, 0, 0);
+}
+
+static void stbtt__csctx_rccurve_to(stbtt__csctx *ctx, float dx1, float dy1, float dx2, float dy2, float dx3, float dy3)
+{
+   float cx1 = ctx->x + dx1;
+   float cy1 = ctx->y + dy1;
+   float cx2 = cx1 + dx2;
+   float cy2 = cy1 + dy2;
+   ctx->x = cx2 + dx3;
+   ctx->y = cy2 + dy3;
+   stbtt__csctx_v(ctx, STBTT_vcubic, (int)ctx->x, (int)ctx->y, (int)cx1, (int)cy1, (int)cx2, (int)cy2);
+}
+
+static stbtt__buf stbtt__get_subr(stbtt__buf idx, int n)
+{
+   int count = stbtt__cff_index_count(&idx);
+   int bias = 107;
+   if (count >= 33900)
+      bias = 32768;
+   else if (count >= 1240)
+      bias = 1131;
+   n += bias;
+   if (n < 0 || n >= count)
+      return stbtt__new_buf(NULL, 0);
+   return stbtt__cff_index_get(idx, n);
+}
+
+static stbtt__buf stbtt__cid_get_glyph_subrs(const stbtt_fontinfo *info, int glyph_index)
+{
+   stbtt__buf fdselect = info->fdselect;
+   int nranges, start, end, v, fmt, fdselector = -1, i;
+
+   stbtt__buf_seek(&fdselect, 0);
+   fmt = stbtt__buf_get8(&fdselect);
+   if (fmt == 0) {
+      // untested
+      stbtt__buf_skip(&fdselect, glyph_index);
+      fdselector = stbtt__buf_get8(&fdselect);
+   } else if (fmt == 3) {
+      nranges = stbtt__buf_get16(&fdselect);
+      start = stbtt__buf_get16(&fdselect);
+      for (i = 0; i < nranges; i++) {
+         v = stbtt__buf_get8(&fdselect);
+         end = stbtt__buf_get16(&fdselect);
+         if (glyph_index >= start && glyph_index < end) {
+            fdselector = v;
+            break;
+         }
+         start = end;
+      }
+   }
+   if (fdselector == -1) stbtt__new_buf(NULL, 0);
+   return stbtt__get_subrs(info->cff, stbtt__cff_index_get(info->fontdicts, fdselector));
+}
+
+static int stbtt__run_charstring(const stbtt_fontinfo *info, int glyph_index, stbtt__csctx *c)
+{
+   int in_header = 1, maskbits = 0, subr_stack_height = 0, sp = 0, v, i, b0;
+   int has_subrs = 0, clear_stack;
+   float s[48];
+   stbtt__buf subr_stack[10], subrs = info->subrs, b;
+   float f;
+
+#define STBTT__CSERR(s) (0)
+
+   // this currently ignores the initial width value, which isn't needed if we have hmtx
+   b = stbtt__cff_index_get(info->charstrings, glyph_index);
+   while (b.cursor < b.size) {
+      i = 0;
+      clear_stack = 1;
+      b0 = stbtt__buf_get8(&b);
+      switch (b0) {
+      // @TODO implement hinting
+      case 0x13: // hintmask
+      case 0x14: // cntrmask
+         if (in_header)
+            maskbits += (sp / 2); // implicit "vstem"
+         in_header = 0;
+         stbtt__buf_skip(&b, (maskbits + 7) / 8);
+         break;
+
+      case 0x01: // hstem
+      case 0x03: // vstem
+      case 0x12: // hstemhm
+      case 0x17: // vstemhm
+         maskbits += (sp / 2);
+         break;
+
+      case 0x15: // rmoveto
+         in_header = 0;
+         if (sp < 2) return STBTT__CSERR("rmoveto stack");
+         stbtt__csctx_rmove_to(c, s[sp-2], s[sp-1]);
+         break;
+      case 0x04: // vmoveto
+         in_header = 0;
+         if (sp < 1) return STBTT__CSERR("vmoveto stack");
+         stbtt__csctx_rmove_to(c, 0, s[sp-1]);
+         break;
+      case 0x16: // hmoveto
+         in_header = 0;
+         if (sp < 1) return STBTT__CSERR("hmoveto stack");
+         stbtt__csctx_rmove_to(c, s[sp-1], 0);
+         break;
+
+      case 0x05: // rlineto
+         if (sp < 2) return STBTT__CSERR("rlineto stack");
+         for (; i + 1 < sp; i += 2)
+            stbtt__csctx_rline_to(c, s[i], s[i+1]);
+         break;
+
+      // hlineto/vlineto and vhcurveto/hvcurveto alternate horizontal and vertical
+      // starting from a different place.
+
+      case 0x07: // vlineto
+         if (sp < 1) return STBTT__CSERR("vlineto stack");
+         goto vlineto;
+      case 0x06: // hlineto
+         if (sp < 1) return STBTT__CSERR("hlineto stack");
+         for (;;) {
+            if (i >= sp) break;
+            stbtt__csctx_rline_to(c, s[i], 0);
+            i++;
+      vlineto:
+            if (i >= sp) break;
+            stbtt__csctx_rline_to(c, 0, s[i]);
+            i++;
+         }
+         break;
+
+      case 0x1F: // hvcurveto
+         if (sp < 4) return STBTT__CSERR("hvcurveto stack");
+         goto hvcurveto;
+      case 0x1E: // vhcurveto
+         if (sp < 4) return STBTT__CSERR("vhcurveto stack");
+         for (;;) {
+            if (i + 3 >= sp) break;
+            stbtt__csctx_rccurve_to(c, 0, s[i], s[i+1], s[i+2], s[i+3], (sp - i == 5) ? s[i + 4] : 0.0f);
+            i += 4;
+      hvcurveto:
+            if (i + 3 >= sp) break;
+            stbtt__csctx_rccurve_to(c, s[i], 0, s[i+1], s[i+2], (sp - i == 5) ? s[i+4] : 0.0f, s[i+3]);
+            i += 4;
+         }
+         break;
+
+      case 0x08: // rrcurveto
+         if (sp < 6) return STBTT__CSERR("rcurveline stack");
+         for (; i + 5 < sp; i += 6)
+            stbtt__csctx_rccurve_to(c, s[i], s[i+1], s[i+2], s[i+3], s[i+4], s[i+5]);
+         break;
+
+      case 0x18: // rcurveline
+         if (sp < 8) return STBTT__CSERR("rcurveline stack");
+         for (; i + 5 < sp - 2; i += 6)
+            stbtt__csctx_rccurve_to(c, s[i], s[i+1], s[i+2], s[i+3], s[i+4], s[i+5]);
+         if (i + 1 >= sp) return STBTT__CSERR("rcurveline stack");
+         stbtt__csctx_rline_to(c, s[i], s[i+1]);
+         break;
+
+      case 0x19: // rlinecurve
+         if (sp < 8) return STBTT__CSERR("rlinecurve stack");
+         for (; i + 1 < sp - 6; i += 2)
+            stbtt__csctx_rline_to(c, s[i], s[i+1]);
+         if (i + 5 >= sp) return STBTT__CSERR("rlinecurve stack");
+         stbtt__csctx_rccurve_to(c, s[i], s[i+1], s[i+2], s[i+3], s[i+4], s[i+5]);
+         break;
+
+      case 0x1A: // vvcurveto
+      case 0x1B: // hhcurveto
+         if (sp < 4) return STBTT__CSERR("(vv|hh)curveto stack");
+         f = 0.0;
+         if (sp & 1) { f = s[i]; i++; }
+         for (; i + 3 < sp; i += 4) {
+            if (b0 == 0x1B)
+               stbtt__csctx_rccurve_to(c, s[i], f, s[i+1], s[i+2], s[i+3], 0.0);
+            else
+               stbtt__csctx_rccurve_to(c, f, s[i], s[i+1], s[i+2], 0.0, s[i+3]);
+            f = 0.0;
+         }
+         break;
+
+      case 0x0A: // callsubr
+         if (!has_subrs) {
+            if (info->fdselect.size)
+               subrs = stbtt__cid_get_glyph_subrs(info, glyph_index);
+            has_subrs = 1;
+         }
+         // FALLTHROUGH
+      case 0x1D: // callgsubr
+         if (sp < 1) return STBTT__CSERR("call(g|)subr stack");
+         v = (int) s[--sp];
+         if (subr_stack_height >= 10) return STBTT__CSERR("recursion limit");
+         subr_stack[subr_stack_height++] = b;
+         b = stbtt__get_subr(b0 == 0x0A ? subrs : info->gsubrs, v);
+         if (b.size == 0) return STBTT__CSERR("subr not found");
+         b.cursor = 0;
+         clear_stack = 0;
+         break;
+
+      case 0x0B: // return
+         if (subr_stack_height <= 0) return STBTT__CSERR("return outside subr");
+         b = subr_stack[--subr_stack_height];
+         clear_stack = 0;
+         break;
+
+      case 0x0E: // endchar
+         stbtt__csctx_close_shape(c);
+         return 1;
+
+      case 0x0C: { // two-byte escape
+         float dx1, dx2, dx3, dx4, dx5, dx6, dy1, dy2, dy3, dy4, dy5, dy6;
+         float dx, dy;
+         int b1 = stbtt__buf_get8(&b);
+         switch (b1) {
+         // @TODO These "flex" implementations ignore the flex-depth and resolution,
+         // and always draw beziers.
+         case 0x22: // hflex
+            if (sp < 7) return STBTT__CSERR("hflex stack");
+            dx1 = s[0];
+            dx2 = s[1];
+            dy2 = s[2];
+            dx3 = s[3];
+            dx4 = s[4];
+            dx5 = s[5];
+            dx6 = s[6];
+            stbtt__csctx_rccurve_to(c, dx1, 0, dx2, dy2, dx3, 0);
+            stbtt__csctx_rccurve_to(c, dx4, 0, dx5, -dy2, dx6, 0);
+            break;
+
+         case 0x23: // flex
+            if (sp < 13) return STBTT__CSERR("flex stack");
+            dx1 = s[0];
+            dy1 = s[1];
+            dx2 = s[2];
+            dy2 = s[3];
+            dx3 = s[4];
+            dy3 = s[5];
+            dx4 = s[6];
+            dy4 = s[7];
+            dx5 = s[8];
+            dy5 = s[9];
+            dx6 = s[10];
+            dy6 = s[11];
+            //fd is s[12]
+            stbtt__csctx_rccurve_to(c, dx1, dy1, dx2, dy2, dx3, dy3);
+            stbtt__csctx_rccurve_to(c, dx4, dy4, dx5, dy5, dx6, dy6);
+            break;
+
+         case 0x24: // hflex1
+            if (sp < 9) return STBTT__CSERR("hflex1 stack");
+            dx1 = s[0];
+            dy1 = s[1];
+            dx2 = s[2];
+            dy2 = s[3];
+            dx3 = s[4];
+            dx4 = s[5];
+            dx5 = s[6];
+            dy5 = s[7];
+            dx6 = s[8];
+            stbtt__csctx_rccurve_to(c, dx1, dy1, dx2, dy2, dx3, 0);
+            stbtt__csctx_rccurve_to(c, dx4, 0, dx5, dy5, dx6, -(dy1+dy2+dy5));
+            break;
+
+         case 0x25: // flex1
+            if (sp < 11) return STBTT__CSERR("flex1 stack");
+            dx1 = s[0];
+            dy1 = s[1];
+            dx2 = s[2];
+            dy2 = s[3];
+            dx3 = s[4];
+            dy3 = s[5];
+            dx4 = s[6];
+            dy4 = s[7];
+            dx5 = s[8];
+            dy5 = s[9];
+            dx6 = dy6 = s[10];
+            dx = dx1+dx2+dx3+dx4+dx5;
+            dy = dy1+dy2+dy3+dy4+dy5;
+            if (STBTT_fabs(dx) > STBTT_fabs(dy))
+               dy6 = -dy;
+            else
+               dx6 = -dx;
+            stbtt__csctx_rccurve_to(c, dx1, dy1, dx2, dy2, dx3, dy3);
+            stbtt__csctx_rccurve_to(c, dx4, dy4, dx5, dy5, dx6, dy6);
+            break;
+
+         default:
+            return STBTT__CSERR("unimplemented");
+         }
+      } break;
+
+      default:
+         if (b0 != 255 && b0 != 28 && b0 < 32)
+            return STBTT__CSERR("reserved operator");
+
+         // push immediate
+         if (b0 == 255) {
+            f = (float)(stbtt_int32)stbtt__buf_get32(&b) / 0x10000;
+         } else {
+            stbtt__buf_skip(&b, -1);
+            f = (float)(stbtt_int16)stbtt__cff_int(&b);
+         }
+         if (sp >= 48) return STBTT__CSERR("push stack overflow");
+         s[sp++] = f;
+         clear_stack = 0;
+         break;
+      }
+      if (clear_stack) sp = 0;
+   }
+   return STBTT__CSERR("no endchar");
+
+#undef STBTT__CSERR
+}
+
+static int stbtt__GetGlyphShapeT2(const stbtt_fontinfo *info, int glyph_index, stbtt_vertex **pvertices)
+{
+   // runs the charstring twice, once to count and once to output (to avoid realloc)
+   stbtt__csctx count_ctx = STBTT__CSCTX_INIT(1);
+   stbtt__csctx output_ctx = STBTT__CSCTX_INIT(0);
+   if (stbtt__run_charstring(info, glyph_index, &count_ctx)) {
+      *pvertices = (stbtt_vertex*)STBTT_malloc(count_ctx.num_vertices*sizeof(stbtt_vertex), info->userdata);
+      output_ctx.pvertices = *pvertices;
+      if (stbtt__run_charstring(info, glyph_index, &output_ctx)) {
+         STBTT_assert(output_ctx.num_vertices == count_ctx.num_vertices);
+         return output_ctx.num_vertices;
+      }
+   }
+   *pvertices = NULL;
+   return 0;
+}
+
+static int stbtt__GetGlyphInfoT2(const stbtt_fontinfo *info, int glyph_index, int *x0, int *y0, int *x1, int *y1)
+{
+   stbtt__csctx c = STBTT__CSCTX_INIT(1);
+   int r = stbtt__run_charstring(info, glyph_index, &c);
+   if (x0)  *x0 = r ? c.min_x : 0;
+   if (y0)  *y0 = r ? c.min_y : 0;
+   if (x1)  *x1 = r ? c.max_x : 0;
+   if (y1)  *y1 = r ? c.max_y : 0;
+   return r ? c.num_vertices : 0;
+}
+
+STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, stbtt_vertex **pvertices)
+{
+   if (!info->cff.size)
+      return stbtt__GetGlyphShapeTT(info, glyph_index, pvertices);
+   else
+      return stbtt__GetGlyphShapeT2(info, glyph_index, pvertices);
+}
+
 STBTT_DEF void stbtt_GetGlyphHMetrics(const stbtt_fontinfo *info, int glyph_index, int *advanceWidth, int *leftSideBearing)
 {
    stbtt_uint16 numOfLongHorMetrics = ttUSHORT(info->data+info->hhea + 34);
@@ -1479,7 +2314,49 @@ STBTT_DEF void stbtt_GetGlyphHMetrics(const stbtt_fontinfo *info, int glyph_inde
    }
 }
 
-STBTT_DEF int  stbtt_GetGlyphKernAdvance(const stbtt_fontinfo *info, int glyph1, int glyph2)
+STBTT_DEF int  stbtt_GetKerningTableLength(const stbtt_fontinfo *info)
+{
+   stbtt_uint8 *data = info->data + info->kern;
+
+   // we only look at the first table. it must be 'horizontal' and format 0.
+   if (!info->kern)
+      return 0;
+   if (ttUSHORT(data+2) < 1) // number of tables, need at least 1
+      return 0;
+   if (ttUSHORT(data+8) != 1) // horizontal flag must be set in format
+      return 0;
+
+   return ttUSHORT(data+10);
+}
+
+STBTT_DEF int stbtt_GetKerningTable(const stbtt_fontinfo *info, stbtt_kerningentry* table, int table_length)
+{
+   stbtt_uint8 *data = info->data + info->kern;
+   int k, length;
+
+   // we only look at the first table. it must be 'horizontal' and format 0.
+   if (!info->kern)
+      return 0;
+   if (ttUSHORT(data+2) < 1) // number of tables, need at least 1
+      return 0;
+   if (ttUSHORT(data+8) != 1) // horizontal flag must be set in format
+      return 0;
+
+   length = ttUSHORT(data+10);
+   if (table_length < length)
+      length = table_length;
+
+   for (k = 0; k < length; k++)
+   {
+      table[k].glyph1 = ttUSHORT(data+18+(k*6));
+      table[k].glyph2 = ttUSHORT(data+20+(k*6));
+      table[k].advance = ttSHORT(data+22+(k*6));
+   }
+
+   return length;
+}
+
+static int stbtt__GetGlyphKernInfoAdvance(const stbtt_fontinfo *info, int glyph1, int glyph2)
 {
    stbtt_uint8 *data = info->data + info->kern;
    stbtt_uint32 needle, straw;
@@ -1509,9 +2386,242 @@ STBTT_DEF int  stbtt_GetGlyphKernAdvance(const stbtt_fontinfo *info, int glyph1,
    return 0;
 }
 
+static stbtt_int32 stbtt__GetCoverageIndex(stbtt_uint8 *coverageTable, int glyph)
+{
+   stbtt_uint16 coverageFormat = ttUSHORT(coverageTable);
+   switch (coverageFormat) {
+      case 1: {
+         stbtt_uint16 glyphCount = ttUSHORT(coverageTable + 2);
+
+         // Binary search.
+         stbtt_int32 l=0, r=glyphCount-1, m;
+         int straw, needle=glyph;
+         while (l <= r) {
+            stbtt_uint8 *glyphArray = coverageTable + 4;
+            stbtt_uint16 glyphID;
+            m = (l + r) >> 1;
+            glyphID = ttUSHORT(glyphArray + 2 * m);
+            straw = glyphID;
+            if (needle < straw)
+               r = m - 1;
+            else if (needle > straw)
+               l = m + 1;
+            else {
+               return m;
+            }
+         }
+         break;
+      }
+
+      case 2: {
+         stbtt_uint16 rangeCount = ttUSHORT(coverageTable + 2);
+         stbtt_uint8 *rangeArray = coverageTable + 4;
+
+         // Binary search.
+         stbtt_int32 l=0, r=rangeCount-1, m;
+         int strawStart, strawEnd, needle=glyph;
+         while (l <= r) {
+            stbtt_uint8 *rangeRecord;
+            m = (l + r) >> 1;
+            rangeRecord = rangeArray + 6 * m;
+            strawStart = ttUSHORT(rangeRecord);
+            strawEnd = ttUSHORT(rangeRecord + 2);
+            if (needle < strawStart)
+               r = m - 1;
+            else if (needle > strawEnd)
+               l = m + 1;
+            else {
+               stbtt_uint16 startCoverageIndex = ttUSHORT(rangeRecord + 4);
+               return startCoverageIndex + glyph - strawStart;
+            }
+         }
+         break;
+      }
+
+      default: return -1; // unsupported
+   }
+
+   return -1;
+}
+
+static stbtt_int32  stbtt__GetGlyphClass(stbtt_uint8 *classDefTable, int glyph)
+{
+   stbtt_uint16 classDefFormat = ttUSHORT(classDefTable);
+   switch (classDefFormat)
+   {
+      case 1: {
+         stbtt_uint16 startGlyphID = ttUSHORT(classDefTable + 2);
+         stbtt_uint16 glyphCount = ttUSHORT(classDefTable + 4);
+         stbtt_uint8 *classDef1ValueArray = classDefTable + 6;
+
+         if (glyph >= startGlyphID && glyph < startGlyphID + glyphCount)
+            return (stbtt_int32)ttUSHORT(classDef1ValueArray + 2 * (glyph - startGlyphID));
+         break;
+      }
+
+      case 2: {
+         stbtt_uint16 classRangeCount = ttUSHORT(classDefTable + 2);
+         stbtt_uint8 *classRangeRecords = classDefTable + 4;
+
+         // Binary search.
+         stbtt_int32 l=0, r=classRangeCount-1, m;
+         int strawStart, strawEnd, needle=glyph;
+         while (l <= r) {
+            stbtt_uint8 *classRangeRecord;
+            m = (l + r) >> 1;
+            classRangeRecord = classRangeRecords + 6 * m;
+            strawStart = ttUSHORT(classRangeRecord);
+            strawEnd = ttUSHORT(classRangeRecord + 2);
+            if (needle < strawStart)
+               r = m - 1;
+            else if (needle > strawEnd)
+               l = m + 1;
+            else
+               return (stbtt_int32)ttUSHORT(classRangeRecord + 4);
+         }
+         break;
+      }
+
+      default:
+         return -1; // Unsupported definition type, return an error.
+   }
+
+   // "All glyphs not assigned to a class fall into class 0". (OpenType spec)
+   return 0;
+}
+
+// Define to STBTT_assert(x) if you want to break on unimplemented formats.
+#define STBTT_GPOS_TODO_assert(x)
+
+static stbtt_int32 stbtt__GetGlyphGPOSInfoAdvance(const stbtt_fontinfo *info, int glyph1, int glyph2)
+{
+   stbtt_uint16 lookupListOffset;
+   stbtt_uint8 *lookupList;
+   stbtt_uint16 lookupCount;
+   stbtt_uint8 *data;
+   stbtt_int32 i, sti;
+
+   if (!info->gpos) return 0;
+
+   data = info->data + info->gpos;
+
+   if (ttUSHORT(data+0) != 1) return 0; // Major version 1
+   if (ttUSHORT(data+2) != 0) return 0; // Minor version 0
+
+   lookupListOffset = ttUSHORT(data+8);
+   lookupList = data + lookupListOffset;
+   lookupCount = ttUSHORT(lookupList);
+
+   for (i=0; i<lookupCount; ++i) {
+      stbtt_uint16 lookupOffset = ttUSHORT(lookupList + 2 + 2 * i);
+      stbtt_uint8 *lookupTable = lookupList + lookupOffset;
+
+      stbtt_uint16 lookupType = ttUSHORT(lookupTable);
+      stbtt_uint16 subTableCount = ttUSHORT(lookupTable + 4);
+      stbtt_uint8 *subTableOffsets = lookupTable + 6;
+      if (lookupType != 2) // Pair Adjustment Positioning Subtable
+         continue;
+
+      for (sti=0; sti<subTableCount; sti++) {
+         stbtt_uint16 subtableOffset = ttUSHORT(subTableOffsets + 2 * sti);
+         stbtt_uint8 *table = lookupTable + subtableOffset;
+         stbtt_uint16 posFormat = ttUSHORT(table);
+         stbtt_uint16 coverageOffset = ttUSHORT(table + 2);
+         stbtt_int32 coverageIndex = stbtt__GetCoverageIndex(table + coverageOffset, glyph1);
+         if (coverageIndex == -1) continue;
+
+         switch (posFormat) {
+            case 1: {
+               stbtt_int32 l, r, m;
+               int straw, needle;
+               stbtt_uint16 valueFormat1 = ttUSHORT(table + 4);
+               stbtt_uint16 valueFormat2 = ttUSHORT(table + 6);
+               if (valueFormat1 == 4 && valueFormat2 == 0) { // Support more formats?
+                  stbtt_int32 valueRecordPairSizeInBytes = 2;
+                  stbtt_uint16 pairSetCount = ttUSHORT(table + 8);
+                  stbtt_uint16 pairPosOffset = ttUSHORT(table + 10 + 2 * coverageIndex);
+                  stbtt_uint8 *pairValueTable = table + pairPosOffset;
+                  stbtt_uint16 pairValueCount = ttUSHORT(pairValueTable);
+                  stbtt_uint8 *pairValueArray = pairValueTable + 2;
+
+                  if (coverageIndex >= pairSetCount) return 0;
+
+                  needle=glyph2;
+                  r=pairValueCount-1;
+                  l=0;
+
+                  // Binary search.
+                  while (l <= r) {
+                     stbtt_uint16 secondGlyph;
+                     stbtt_uint8 *pairValue;
+                     m = (l + r) >> 1;
+                     pairValue = pairValueArray + (2 + valueRecordPairSizeInBytes) * m;
+                     secondGlyph = ttUSHORT(pairValue);
+                     straw = secondGlyph;
+                     if (needle < straw)
+                        r = m - 1;
+                     else if (needle > straw)
+                        l = m + 1;
+                     else {
+                        stbtt_int16 xAdvance = ttSHORT(pairValue + 2);
+                        return xAdvance;
+                     }
+                  }
+               } else
+                  return 0;
+               break;
+            }
+
+            case 2: {
+               stbtt_uint16 valueFormat1 = ttUSHORT(table + 4);
+               stbtt_uint16 valueFormat2 = ttUSHORT(table + 6);
+               if (valueFormat1 == 4 && valueFormat2 == 0) { // Support more formats?
+                  stbtt_uint16 classDef1Offset = ttUSHORT(table + 8);
+                  stbtt_uint16 classDef2Offset = ttUSHORT(table + 10);
+                  int glyph1class = stbtt__GetGlyphClass(table + classDef1Offset, glyph1);
+                  int glyph2class = stbtt__GetGlyphClass(table + classDef2Offset, glyph2);
+
+                  stbtt_uint16 class1Count = ttUSHORT(table + 12);
+                  stbtt_uint16 class2Count = ttUSHORT(table + 14);
+                  stbtt_uint8 *class1Records, *class2Records;
+                  stbtt_int16 xAdvance;
+
+                  if (glyph1class < 0 || glyph1class >= class1Count) return 0; // malformed
+                  if (glyph2class < 0 || glyph2class >= class2Count) return 0; // malformed
+
+                  class1Records = table + 16;
+                  class2Records = class1Records + 2 * (glyph1class * class2Count);
+                  xAdvance = ttSHORT(class2Records + 2 * glyph2class);
+                  return xAdvance;
+               } else
+                  return 0;
+               break;
+            }
+
+            default:
+               return 0; // Unsupported position format
+         }
+      }
+   }
+
+   return 0;
+}
+
+STBTT_DEF int  stbtt_GetGlyphKernAdvance(const stbtt_fontinfo *info, int g1, int g2)
+{
+   int xAdvance = 0;
+
+   if (info->gpos)
+      xAdvance += stbtt__GetGlyphGPOSInfoAdvance(info, g1, g2);
+   else if (info->kern)
+      xAdvance += stbtt__GetGlyphKernInfoAdvance(info, g1, g2);
+
+   return xAdvance;
+}
+
 STBTT_DEF int  stbtt_GetCodepointKernAdvance(const stbtt_fontinfo *info, int ch1, int ch2)
 {
-   if (!info->kern) // if no kerning table, don't waste time looking up both codepoint->glyphs
+   if (!info->kern && !info->gpos) // if no kerning table, don't waste time looking up both codepoint->glyphs
       return 0;
    return stbtt_GetGlyphKernAdvance(info, stbtt_FindGlyphIndex(info,ch1), stbtt_FindGlyphIndex(info,ch2));
 }
@@ -1528,6 +2638,17 @@ STBTT_DEF void stbtt_GetFontVMetrics(const stbtt_fontinfo *info, int *ascent, in
    if (lineGap) *lineGap = ttSHORT(info->data+info->hhea + 8);
 }
 
+STBTT_DEF int  stbtt_GetFontVMetricsOS2(const stbtt_fontinfo *info, int *typoAscent, int *typoDescent, int *typoLineGap)
+{
+   int tab = stbtt__find_table(info->data, info->fontstart, "OS/2");
+   if (!tab)
+      return 0;
+   if (typoAscent ) *typoAscent  = ttSHORT(info->data+tab + 68);
+   if (typoDescent) *typoDescent = ttSHORT(info->data+tab + 70);
+   if (typoLineGap) *typoLineGap = ttSHORT(info->data+tab + 72);
+   return 1;
+}
+
 STBTT_DEF void stbtt_GetFontBoundingBox(const stbtt_fontinfo *info, int *x0, int *y0, int *x1, int *y1)
 {
    *x0 = ttSHORT(info->data + info->head + 36);
@@ -1553,6 +2674,45 @@ STBTT_DEF void stbtt_FreeShape(const stbtt_fontinfo *info, stbtt_vertex *v)
    STBTT_free(v, info->userdata);
 }
 
+STBTT_DEF stbtt_uint8 *stbtt_FindSVGDoc(const stbtt_fontinfo *info, int gl)
+{
+   int i;
+   stbtt_uint8 *data = info->data;
+   stbtt_uint8 *svg_doc_list = data + stbtt__get_svg((stbtt_fontinfo *) info);
+
+   int numEntries = ttUSHORT(svg_doc_list);
+   stbtt_uint8 *svg_docs = svg_doc_list + 2;
+
+   for(i=0; i<numEntries; i++) {
+      stbtt_uint8 *svg_doc = svg_docs + (12 * i);
+      if ((gl >= ttUSHORT(svg_doc)) && (gl <= ttUSHORT(svg_doc + 2)))
+         return svg_doc;
+   }
+   return 0;
+}
+
+STBTT_DEF int stbtt_GetGlyphSVG(const stbtt_fontinfo *info, int gl, const char **svg)
+{
+   stbtt_uint8 *data = info->data;
+   stbtt_uint8 *svg_doc;
+
+   if (info->svg == 0)
+      return 0;
+
+   svg_doc = stbtt_FindSVGDoc(info, gl);
+   if (svg_doc != NULL) {
+      *svg = (char *) data + info->svg + ttULONG(svg_doc + 4);
+      return ttULONG(svg_doc + 8);
+   } else {
+      return 0;
+   }
+}
+
+STBTT_DEF int stbtt_GetCodepointSVG(const stbtt_fontinfo *info, int unicode_codepoint, const char **svg)
+{
+   return stbtt_GetGlyphSVG(info, stbtt_FindGlyphIndex(info, unicode_codepoint), svg);
+}
+
 //////////////////////////////////////////////////////////////////////////////
 //
 // antialiasing software rasterizer
@@ -1560,7 +2720,7 @@ STBTT_DEF void stbtt_FreeShape(const stbtt_fontinfo *info, stbtt_vertex *v)
 
 STBTT_DEF void stbtt_GetGlyphBitmapBoxSubpixel(const stbtt_fontinfo *font, int glyph, float scale_x, float scale_y,float shift_x, float shift_y, int *ix0, int *iy0, int *ix1, int *iy1)
 {
-   int x0,y0,x1,y1;
+   int x0=0,y0=0,x1,y1; // =0 suppresses compiler warning
    if (!stbtt_GetGlyphBox(font, glyph, &x0,&y0,&x1,&y1)) {
       // e.g. space character
       if (ix0) *ix0 = 0;
@@ -1624,7 +2784,7 @@ static void *stbtt__hheap_alloc(stbtt__hheap *hh, size_t size, void *userdata)
          hh->num_remaining_in_head_chunk = count;
       }
       --hh->num_remaining_in_head_chunk;
-      return (char *) (hh->head) + size * hh->num_remaining_in_head_chunk;
+      return (char *) (hh->head) + sizeof(stbtt__hheap_chunk) + size * hh->num_remaining_in_head_chunk;
    }
 }
 
@@ -1676,8 +2836,9 @@ static stbtt__active_edge *stbtt__new_active(stbtt__hheap *hh, stbtt__edge *e, i
 {
    stbtt__active_edge *z = (stbtt__active_edge *) stbtt__hheap_alloc(hh, sizeof(*z), userdata);
    float dxdy = (e->x1 - e->x0) / (e->y1 - e->y0);
+   STBTT_assert(z != NULL);
    if (!z) return z;
-   
+
    // round dx down to avoid overshooting
    if (dxdy < 0)
       z->dx = -STBTT_ifloor(STBTT_FIX * -dxdy);
@@ -1697,6 +2858,7 @@ static stbtt__active_edge *stbtt__new_active(stbtt__hheap *hh, stbtt__edge *e, i
 {
    stbtt__active_edge *z = (stbtt__active_edge *) stbtt__hheap_alloc(hh, sizeof(*z), userdata);
    float dxdy = (e->x1 - e->x0) / (e->y1 - e->y0);
+   STBTT_assert(z != NULL);
    //STBTT_assert(e->y0 <= start_point);
    if (!z) return z;
    z->fdx = dxdy;
@@ -1754,7 +2916,7 @@ static void stbtt__fill_active_edges(unsigned char *scanline, int len, stbtt__ac
             }
          }
       }
-      
+
       e = e->next;
    }
 }
@@ -1768,13 +2930,10 @@ static void stbtt__rasterize_sorted_edges(stbtt__bitmap *result, stbtt__edge *e,
    int s; // vertical subsample index
    unsigned char scanline_data[512], *scanline;
 
-   if (result->w > 512) {
+   if (result->w > 512)
       scanline = (unsigned char *) STBTT_malloc(result->w, userdata);
-      if (!scanline)
-         return;
-   } else {
+   else
       scanline = scanline_data;
-   }
 
    y = off_y * vsubsample;
    e[n].y0 = (off_y + result->h) * (float) vsubsample + 1;
@@ -1824,23 +2983,23 @@ static void stbtt__rasterize_sorted_edges(stbtt__bitmap *result, stbtt__edge *e,
          while (e->y0 <= scan_y) {
             if (e->y1 > scan_y) {
                stbtt__active_edge *z = stbtt__new_active(&hh, e, off_x, scan_y, userdata);
-               if (!z)
-                  return;
-               // find insertion point
-               if (active == NULL)
-                  active = z;
-               else if (z->x < active->x) {
-                  // insert at front
-                  z->next = active;
-                  active = z;
-               } else {
-                  // find thing to insert AFTER
-                  stbtt__active_edge *p = active;
-                  while (p->next && p->next->x < z->x)
-                     p = p->next;
-                  // at this point, p->next->x is NOT < z->x
-                  z->next = p->next;
-                  p->next = z;
+               if (z != NULL) {
+                  // find insertion point
+                  if (active == NULL)
+                     active = z;
+                  else if (z->x < active->x) {
+                     // insert at front
+                     z->next = active;
+                     active = z;
+                  } else {
+                     // find thing to insert AFTER
+                     stbtt__active_edge *p = active;
+                     while (p->next && p->next->x < z->x)
+                        p = p->next;
+                     // at this point, p->next->x is NOT < z->x
+                     z->next = p->next;
+                     p->next = z;
+                  }
                }
             }
             ++e;
@@ -1903,6 +3062,23 @@ static void stbtt__handle_clipped_edge(float *scanline, int x, stbtt__active_edg
    }
 }
 
+static float stbtt__sized_trapezoid_area(float height, float top_width, float bottom_width)
+{
+   STBTT_assert(top_width >= 0);
+   STBTT_assert(bottom_width >= 0);
+   return (top_width + bottom_width) / 2.0f * height;
+}
+
+static float stbtt__position_trapezoid_area(float height, float tx0, float tx1, float bx0, float bx1)
+{
+   return stbtt__sized_trapezoid_area(height, tx1 - tx0, bx1 - bx0);
+}
+
+static float stbtt__sized_triangle_area(float height, float width)
+{
+   return height * width / 2;
+}
+
 static void stbtt__fill_active_edges_new(float *scanline, float *scanline_fill, int len, stbtt__active_edge *e, float y_top)
 {
    float y_bottom = y_top+1;
@@ -1957,13 +3133,13 @@ static void stbtt__fill_active_edges_new(float *scanline, float *scanline_fill,
                float height;
                // simple case, only spans one pixel
                int x = (int) x_top;
-               height = sy1 - sy0;
+               height = (sy1 - sy0) * e->direction;
                STBTT_assert(x >= 0 && x < len);
-               scanline[x] += e->direction * (1-((x_top - x) + (x_bottom-x))/2)  * height;
-               scanline_fill[x] += e->direction * height; // everything right of this pixel is filled
+               scanline[x]      += stbtt__position_trapezoid_area(height, x_top, x+1.0f, x_bottom, x+1.0f);
+               scanline_fill[x] += height; // everything right of this pixel is filled
             } else {
                int x,x1,x2;
-               float y_crossing, step, sign, area;
+               float y_crossing, y_final, step, sign, area;
                // covers 2+ pixels
                if (x_top > x_bottom) {
                   // flip scanline vertically; signed area is the same
@@ -1976,29 +3152,79 @@ static void stbtt__fill_active_edges_new(float *scanline, float *scanline_fill,
                   dy = -dy;
                   t = x0, x0 = xb, xb = t;
                }
+               STBTT_assert(dy >= 0);
+               STBTT_assert(dx >= 0);
 
                x1 = (int) x_top;
                x2 = (int) x_bottom;
                // compute intersection with y axis at x1+1
-               y_crossing = (x1+1 - x0) * dy + y_top;
+               y_crossing = y_top + dy * (x1+1 - x0);
+
+               // compute intersection with y axis at x2
+               y_final = y_top + dy * (x2 - x0);
+
+               //           x1    x_top                            x2    x_bottom
+               //     y_top  +------|-----+------------+------------+--------|---+------------+
+               //            |            |            |            |            |            |
+               //            |            |            |            |            |            |
+               //       sy0  |      Txxxxx|............|............|............|............|
+               // y_crossing |            *xxxxx.......|............|............|............|
+               //            |            |     xxxxx..|............|............|............|
+               //            |            |     /-   xx*xxxx........|............|............|
+               //            |            | dy <       |    xxxxxx..|............|............|
+               //   y_final  |            |     \-     |          xx*xxx.........|............|
+               //       sy1  |            |            |            |   xxxxxB...|............|
+               //            |            |            |            |            |            |
+               //            |            |            |            |            |            |
+               //  y_bottom  +------------+------------+------------+------------+------------+
+               //
+               // goal is to measure the area covered by '.' in each pixel
+
+               // if x2 is right at the right edge of x1, y_crossing can blow up, github #1057
+               // @TODO: maybe test against sy1 rather than y_bottom?
+               if (y_crossing > y_bottom)
+                  y_crossing = y_bottom;
 
                sign = e->direction;
-               // area of the rectangle covered from y0..y_crossing
+
+               // area of the rectangle covered from sy0..y_crossing
                area = sign * (y_crossing-sy0);
-               // area of the triangle (x_top,y0), (x+1,y0), (x+1,y_crossing)
-               scanline[x1] += area * (1-((x_top - x1)+(x1+1-x1))/2);
 
-               step = sign * dy;
+               // area of the triangle (x_top,sy0), (x1+1,sy0), (x1+1,y_crossing)
+               scanline[x1] += stbtt__sized_triangle_area(area, x1+1 - x_top);
+
+               // check if final y_crossing is blown up; no test case for this
+               if (y_final > y_bottom) {
+                  y_final = y_bottom;
+                  dy = (y_final - y_crossing ) / (x2 - (x1+1)); // if denom=0, y_final = y_crossing, so y_final <= y_bottom
+               }
+
+               // in second pixel, area covered by line segment found in first pixel
+               // is always a rectangle 1 wide * the height of that line segment; this
+               // is exactly what the variable 'area' stores. it also gets a contribution
+               // from the line segment within it. the THIRD pixel will get the first
+               // pixel's rectangle contribution, the second pixel's rectangle contribution,
+               // and its own contribution. the 'own contribution' is the same in every pixel except
+               // the leftmost and rightmost, a trapezoid that slides down in each pixel.
+               // the second pixel's contribution to the third pixel will be the
+               // rectangle 1 wide times the height change in the second pixel, which is dy.
+
+               step = sign * dy * 1; // dy is dy/dx, change in y for every 1 change in x,
+               // which multiplied by 1-pixel-width is how much pixel area changes for each step in x
+               // so the area advances by 'step' every time
+
                for (x = x1+1; x < x2; ++x) {
-                  scanline[x] += area + step/2;
+                  scanline[x] += area + step/2; // area of trapezoid is 1*step/2
                   area += step;
                }
-               y_crossing += dy * (x2 - (x1+1));
+               STBTT_assert(STBTT_fabs(area) <= 1.01f); // accumulated error from area += step unless we round step down
+               STBTT_assert(sy1 > y_final-0.01f);
 
-               STBTT_assert(fabs(area) <= 1.01f);
-
-               scanline[x2] += area + sign * (1-(x_bottom-x2)/2) * (sy1-y_crossing);
+               // area covered in the last pixel is the rectangle from all the pixels to the left,
+               // plus the trapezoid filled by the line segment in this pixel all the way to the right edge
+               scanline[x2] += area + sign * stbtt__position_trapezoid_area(sy1-y_final, (float) x2, x2+1.0f, x_bottom, x2+1.0f);
 
+               // the rest of the line is filled based on the total height of the line segment in this pixel
                scanline_fill[x2] += sign * (sy1-sy0);
             }
          } else {
@@ -2006,6 +3232,9 @@ static void stbtt__fill_active_edges_new(float *scanline, float *scanline_fill,
             // clipping logic. since this does not match the intended use
             // of this library, we use a different, very slow brute
             // force implementation
+            // note though that this does happen some of the time because
+            // x_top and x_bottom can be extrapolated at the top & bottom of
+            // the shape and actually lie outside the bounding box
             int x;
             for (x=0; x < len; ++x) {
                // cases:
@@ -2021,19 +3250,18 @@ static void stbtt__fill_active_edges_new(float *scanline, float *scanline_fill,
                // from the other y segment, and it might ignored as an empty segment. to avoid
                // that, we need to explicitly produce segments based on x positions.
 
-               // rename variables to clear pairs
+               // rename variables to clearly-defined pairs
                float y0 = y_top;
                float x1 = (float) (x);
                float x2 = (float) (x+1);
                float x3 = xb;
                float y3 = y_bottom;
-               float y1,y2;
 
                // x = e->x + e->dx * (y-y_top)
                // (y-y_top) = (x - e->x) / e->dx
                // y = (x - e->x) / e->dx + y_top
-               y1 = (x - x0) / dx + y_top;
-               y2 = (x+1 - x0) / dx + y_top;
+               float y1 = (x - x0) / dx + y_top;
+               float y2 = (x+1 - x0) / dx + y_top;
 
                if (x0 < x1 && x3 > x2) {         // three segments descending down-right
                   stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x1,y1);
@@ -2073,13 +3301,12 @@ static void stbtt__rasterize_sorted_edges(stbtt__bitmap *result, stbtt__edge *e,
    int y,j=0, i;
    float scanline_data[129], *scanline, *scanline2;
 
-   if (result->w > 64) {
+   STBTT__NOTUSED(vsubsample);
+
+   if (result->w > 64)
       scanline = (float *) STBTT_malloc((result->w*2+1) * sizeof(float), userdata);
-      if (!scanline)
-         return;
-   } else {
+   else
       scanline = scanline_data;
-   }
 
    scanline2 = scanline + result->w;
 
@@ -2113,12 +3340,18 @@ static void stbtt__rasterize_sorted_edges(stbtt__bitmap *result, stbtt__edge *e,
       while (e->y0 <= scan_y_bottom) {
          if (e->y0 != e->y1) {
             stbtt__active_edge *z = stbtt__new_active(&hh, e, off_x, scan_y_top, userdata);
-            if (!z)
-               return;
-            STBTT_assert(z->ey >= scan_y_top);
-            // insert at front
-            z->next = active;
-            active = z;
+            if (z != NULL) {
+               if (j == 0 && off_y != 0) {
+                  if (z->ey < scan_y_top) {
+                     // this can happen due to subpixel positioning and some kind of fp rounding error i think
+                     z->ey = scan_y_top;
+                  }
+               }
+               STBTT_assert(z->ey >= scan_y_top); // if we get really unlucky a tiny bit of an edge can be out of bounds
+               // insert at front
+               z->next = active;
+               active = z;
+            }
          }
          ++e;
       }
@@ -2183,7 +3416,7 @@ static void stbtt__sort_edges_ins_sort(stbtt__edge *p, int n)
 
 static void stbtt__sort_edges_quicksort(stbtt__edge *p, int n)
 {
-   /* threshhold for transitioning to insertion sort */
+   /* threshold for transitioning to insertion sort */
    while (n > 12) {
       stbtt__edge t;
       int c01,c12,c,m,i,j;
@@ -2318,7 +3551,7 @@ static void stbtt__add_point(stbtt__point *points, int n, float x, float y)
    points[n].y = y;
 }
 
-// tesselate until threshhold p is happy... @TODO warped to compensate for non-linear stretching
+// tessellate until threshold p is happy... @TODO warped to compensate for non-linear stretching
 static int stbtt__tesselate_curve(stbtt__point *points, int *num_points, float x0, float y0, float x1, float y1, float x2, float y2, float objspace_flatness_squared, int n)
 {
    // midpoint
@@ -2339,6 +3572,48 @@ static int stbtt__tesselate_curve(stbtt__point *points, int *num_points, float x
    return 1;
 }
 
+static void stbtt__tesselate_cubic(stbtt__point *points, int *num_points, float x0, float y0, float x1, float y1, float x2, float y2, float x3, float y3, float objspace_flatness_squared, int n)
+{
+   // @TODO this "flatness" calculation is just made-up nonsense that seems to work well enough
+   float dx0 = x1-x0;
+   float dy0 = y1-y0;
+   float dx1 = x2-x1;
+   float dy1 = y2-y1;
+   float dx2 = x3-x2;
+   float dy2 = y3-y2;
+   float dx = x3-x0;
+   float dy = y3-y0;
+   float longlen = (float) (STBTT_sqrt(dx0*dx0+dy0*dy0)+STBTT_sqrt(dx1*dx1+dy1*dy1)+STBTT_sqrt(dx2*dx2+dy2*dy2));
+   float shortlen = (float) STBTT_sqrt(dx*dx+dy*dy);
+   float flatness_squared = longlen*longlen-shortlen*shortlen;
+
+   if (n > 16) // 65536 segments on one curve better be enough!
+      return;
+
+   if (flatness_squared > objspace_flatness_squared) {
+      float x01 = (x0+x1)/2;
+      float y01 = (y0+y1)/2;
+      float x12 = (x1+x2)/2;
+      float y12 = (y1+y2)/2;
+      float x23 = (x2+x3)/2;
+      float y23 = (y2+y3)/2;
+
+      float xa = (x01+x12)/2;
+      float ya = (y01+y12)/2;
+      float xb = (x12+x23)/2;
+      float yb = (y12+y23)/2;
+
+      float mx = (xa+xb)/2;
+      float my = (ya+yb)/2;
+
+      stbtt__tesselate_cubic(points, num_points, x0,y0, x01,y01, xa,ya, mx,my, objspace_flatness_squared,n+1);
+      stbtt__tesselate_cubic(points, num_points, mx,my, xb,yb, x23,y23, x3,y3, objspace_flatness_squared,n+1);
+   } else {
+      stbtt__add_point(points, *num_points,x3,y3);
+      *num_points = *num_points+1;
+   }
+}
+
 // returns number of contours
 static stbtt__point *stbtt_FlattenCurves(stbtt_vertex *vertices, int num_verts, float objspace_flatness, int **contour_lengths, int *num_contours, void *userdata)
 {
@@ -2395,6 +3670,14 @@ static stbtt__point *stbtt_FlattenCurves(stbtt_vertex *vertices, int num_verts,
                                         objspace_flatness_squared, 0);
                x = vertices[i].x, y = vertices[i].y;
                break;
+            case STBTT_vcubic:
+               stbtt__tesselate_cubic(points, &num_points, x,y,
+                                        vertices[i].cx, vertices[i].cy,
+                                        vertices[i].cx1, vertices[i].cy1,
+                                        vertices[i].x,  vertices[i].y,
+                                        objspace_flatness_squared, 0);
+               x = vertices[i].x, y = vertices[i].y;
+               break;
          }
       }
       (*contour_lengths)[n] = num_points - start;
@@ -2411,8 +3694,9 @@ error:
 
 STBTT_DEF void stbtt_Rasterize(stbtt__bitmap *result, float flatness_in_pixels, stbtt_vertex *vertices, int num_verts, float scale_x, float scale_y, float shift_x, float shift_y, int x_off, int y_off, int invert, void *userdata)
 {
-   float scale = scale_x > scale_y ? scale_y : scale_x;
-   int winding_count, *winding_lengths;
+   float scale            = scale_x > scale_y ? scale_y : scale_x;
+   int winding_count      = 0;
+   int *winding_lengths   = NULL;
    stbtt__point *windings = stbtt_FlattenCurves(vertices, num_verts, flatness_in_pixels / scale, &winding_lengths, &winding_count, userdata);
    if (windings) {
       stbtt__rasterize(result, windings, winding_lengths, winding_count, scale_x, scale_y, shift_x, shift_y, x_off, y_off, invert, userdata);
@@ -2430,7 +3714,7 @@ STBTT_DEF unsigned char *stbtt_GetGlyphBitmapSubpixel(const stbtt_fontinfo *info
 {
    int ix0,iy0,ix1,iy1;
    stbtt__bitmap gbm;
-   stbtt_vertex *vertices;   
+   stbtt_vertex *vertices;
    int num_verts = stbtt_GetGlyphShape(info, glyph, &vertices);
 
    if (scale_x == 0) scale_x = scale_y;
@@ -2453,7 +3737,7 @@ STBTT_DEF unsigned char *stbtt_GetGlyphBitmapSubpixel(const stbtt_fontinfo *info
    if (height) *height = gbm.h;
    if (xoff  ) *xoff   = ix0;
    if (yoff  ) *yoff   = iy0;
-   
+
    if (gbm.w && gbm.h) {
       gbm.pixels = (unsigned char *) STBTT_malloc(gbm.w * gbm.h, info->userdata);
       if (gbm.pixels) {
@@ -2464,7 +3748,7 @@ STBTT_DEF unsigned char *stbtt_GetGlyphBitmapSubpixel(const stbtt_fontinfo *info
    }
    STBTT_free(vertices, info->userdata);
    return gbm.pixels;
-}   
+}
 
 STBTT_DEF unsigned char *stbtt_GetGlyphBitmap(const stbtt_fontinfo *info, float scale_x, float scale_y, int glyph, int *width, int *height, int *xoff, int *yoff)
 {
@@ -2476,7 +3760,7 @@ STBTT_DEF void stbtt_MakeGlyphBitmapSubpixel(const stbtt_fontinfo *info, unsigne
    int ix0,iy0;
    stbtt_vertex *vertices;
    int num_verts = stbtt_GetGlyphShape(info, glyph, &vertices);
-   stbtt__bitmap gbm;   
+   stbtt__bitmap gbm;
 
    stbtt_GetGlyphBitmapBoxSubpixel(info, glyph, scale_x, scale_y, shift_x, shift_y, &ix0,&iy0,0,0);
    gbm.pixels = output;
@@ -2498,7 +3782,12 @@ STBTT_DEF void stbtt_MakeGlyphBitmap(const stbtt_fontinfo *info, unsigned char *
 STBTT_DEF unsigned char *stbtt_GetCodepointBitmapSubpixel(const stbtt_fontinfo *info, float scale_x, float scale_y, float shift_x, float shift_y, int codepoint, int *width, int *height, int *xoff, int *yoff)
 {
    return stbtt_GetGlyphBitmapSubpixel(info, scale_x, scale_y,shift_x,shift_y, stbtt_FindGlyphIndex(info,codepoint), width,height,xoff,yoff);
-}   
+}
+
+STBTT_DEF void stbtt_MakeCodepointBitmapSubpixelPrefilter(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int oversample_x, int oversample_y, float *sub_x, float *sub_y, int codepoint)
+{
+   stbtt_MakeGlyphBitmapSubpixelPrefilter(info, output, out_w, out_h, out_stride, scale_x, scale_y, shift_x, shift_y, oversample_x, oversample_y, sub_x, sub_y, stbtt_FindGlyphIndex(info,codepoint));
+}
 
 STBTT_DEF void stbtt_MakeCodepointBitmapSubpixel(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int codepoint)
 {
@@ -2508,7 +3797,7 @@ STBTT_DEF void stbtt_MakeCodepointBitmapSubpixel(const stbtt_fontinfo *info, uns
 STBTT_DEF unsigned char *stbtt_GetCodepointBitmap(const stbtt_fontinfo *info, float scale_x, float scale_y, int codepoint, int *width, int *height, int *xoff, int *yoff)
 {
    return stbtt_GetCodepointBitmapSubpixel(info, scale_x, scale_y, 0.0f,0.0f, codepoint, width,height,xoff,yoff);
-}   
+}
 
 STBTT_DEF void stbtt_MakeCodepointBitmap(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, int codepoint)
 {
@@ -2521,7 +3810,7 @@ STBTT_DEF void stbtt_MakeCodepointBitmap(const stbtt_fontinfo *info, unsigned ch
 //
 // This is SUPER-CRAPPY packing to keep source code small
 
-STBTT_DEF int stbtt_BakeFontBitmap(const unsigned char *data, int offset,  // font location (use offset=0 for plain .ttf)
+static int stbtt_BakeFontBitmap_internal(unsigned char *data, int offset,  // font location (use offset=0 for plain .ttf)
                                 float pixel_height,                     // height of font in pixels
                                 unsigned char *pixels, int pw, int ph,  // bitmap to be filled in
                                 int first_char, int num_chars,          // characters to bake
@@ -2530,6 +3819,7 @@ STBTT_DEF int stbtt_BakeFontBitmap(const unsigned char *data, int offset,  // fo
    float scale;
    int x,y,bottom_y, i;
    stbtt_fontinfo f;
+   f.userdata = NULL;
    if (!stbtt_InitFont(&f, data, offset))
       return -1;
    STBTT_memset(pixels, 0, pw*ph); // background of 0 around pixels
@@ -2566,11 +3856,11 @@ STBTT_DEF int stbtt_BakeFontBitmap(const unsigned char *data, int offset,  // fo
    return bottom_y;
 }
 
-STBTT_DEF void stbtt_GetBakedQuad(stbtt_bakedchar *chardata, int pw, int ph, int char_index, float *xpos, float *ypos, stbtt_aligned_quad *q, int opengl_fillrule)
+STBTT_DEF void stbtt_GetBakedQuad(const stbtt_bakedchar *chardata, int pw, int ph, int char_index, float *xpos, float *ypos, stbtt_aligned_quad *q, int opengl_fillrule)
 {
    float d3d_bias = opengl_fillrule ? 0 : -0.5f;
    float ipw = 1.0f / pw, iph = 1.0f / ph;
-   stbtt_bakedchar *b = chardata + char_index;
+   const stbtt_bakedchar *b = chardata + char_index;
    int round_x = STBTT_ifloor((*xpos + b->xoff) + 0.5f);
    int round_y = STBTT_ifloor((*ypos + b->yoff) + 0.5f);
 
@@ -2593,11 +3883,6 @@ STBTT_DEF void stbtt_GetBakedQuad(stbtt_bakedchar *chardata, int pw, int ph, int
 //
 
 #ifndef STB_RECT_PACK_VERSION
-#ifdef _MSC_VER
-#define STBTT__NOTUSED(v)  (void)(v)
-#else
-#define STBTT__NOTUSED(v)  (void)sizeof(v)
-#endif
 
 typedef int stbrp_coord;
 
@@ -2637,7 +3922,7 @@ static void stbrp_init_target(stbrp_context *con, int pw, int ph, stbrp_node *no
    con->y = 0;
    con->bottom_y = 0;
    STBTT__NOTUSED(nodes);
-   STBTT__NOTUSED(num_nodes);   
+   STBTT__NOTUSED(num_nodes);
 }
 
 static void stbrp_pack_rects(stbrp_context *con, stbrp_rect *rects, int num_rects)
@@ -2691,6 +3976,7 @@ STBTT_DEF int stbtt_PackBegin(stbtt_pack_context *spc, unsigned char *pixels, in
    spc->stride_in_bytes = stride_in_bytes != 0 ? stride_in_bytes : pw;
    spc->h_oversample = 1;
    spc->v_oversample = 1;
+   spc->skip_missing = 0;
 
    stbrp_init_target(context, pw-padding, ph-padding, nodes, num_nodes);
 
@@ -2716,6 +4002,11 @@ STBTT_DEF void stbtt_PackSetOversampling(stbtt_pack_context *spc, unsigned int h
       spc->v_oversample = v_oversample;
 }
 
+STBTT_DEF void stbtt_PackSetSkipMissingCodepoints(stbtt_pack_context *spc, int skip)
+{
+   spc->skip_missing = skip;
+}
+
 #define STBTT__OVER_MASK  (STBTT_MAX_OVERSAMPLE-1)
 
 static void stbtt__h_prefilter(unsigned char *pixels, int w, int h, int stride_in_bytes, unsigned int kernel_width)
@@ -2723,6 +4014,7 @@ static void stbtt__h_prefilter(unsigned char *pixels, int w, int h, int stride_i
    unsigned char buffer[STBTT_MAX_OVERSAMPLE];
    int safe_w = w - kernel_width;
    int j;
+   STBTT_memset(buffer, 0, STBTT_MAX_OVERSAMPLE); // suppress bogus warning from VS2013 -analyze
    for (j=0; j < h; ++j) {
       int i;
       unsigned int total;
@@ -2784,6 +4076,7 @@ static void stbtt__v_prefilter(unsigned char *pixels, int w, int h, int stride_i
    unsigned char buffer[STBTT_MAX_OVERSAMPLE];
    int safe_h = h - kernel_width;
    int j;
+   STBTT_memset(buffer, 0, STBTT_MAX_OVERSAMPLE); // suppress bogus warning from VS2013 -analyze
    for (j=0; j < w; ++j) {
       int i;
       unsigned int total;
@@ -2853,9 +4146,10 @@ static float stbtt__oversample_shift(int oversample)
 }
 
 // rects array must be big enough to accommodate all characters in the given ranges
-STBTT_DEF int stbtt_PackFontRangesGatherRects(stbtt_pack_context *spc, stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects)
+STBTT_DEF int stbtt_PackFontRangesGatherRects(stbtt_pack_context *spc, const stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects)
 {
    int i,j,k;
+   int missing_glyph_added = 0;
 
    k=0;
    for (i=0; i < num_ranges; ++i) {
@@ -2867,13 +4161,19 @@ STBTT_DEF int stbtt_PackFontRangesGatherRects(stbtt_pack_context *spc, stbtt_fon
          int x0,y0,x1,y1;
          int codepoint = ranges[i].array_of_unicode_codepoints == NULL ? ranges[i].first_unicode_codepoint_in_range + j : ranges[i].array_of_unicode_codepoints[j];
          int glyph = stbtt_FindGlyphIndex(info, codepoint);
-         stbtt_GetGlyphBitmapBoxSubpixel(info,glyph,
-                                         scale * spc->h_oversample,
-                                         scale * spc->v_oversample,
-                                         0,0,
-                                         &x0,&y0,&x1,&y1);
-         rects[k].w = (stbrp_coord) (x1-x0 + spc->padding + spc->h_oversample-1);
-         rects[k].h = (stbrp_coord) (y1-y0 + spc->padding + spc->v_oversample-1);
+         if (glyph == 0 && (spc->skip_missing || missing_glyph_added)) {
+            rects[k].w = rects[k].h = 0;
+         } else {
+            stbtt_GetGlyphBitmapBoxSubpixel(info,glyph,
+                                            scale * spc->h_oversample,
+                                            scale * spc->v_oversample,
+                                            0,0,
+                                            &x0,&y0,&x1,&y1);
+            rects[k].w = (stbrp_coord) (x1-x0 + spc->padding + spc->h_oversample-1);
+            rects[k].h = (stbrp_coord) (y1-y0 + spc->padding + spc->v_oversample-1);
+            if (glyph == 0)
+               missing_glyph_added = 1;
+         }
          ++k;
       }
    }
@@ -2881,10 +4181,33 @@ STBTT_DEF int stbtt_PackFontRangesGatherRects(stbtt_pack_context *spc, stbtt_fon
    return k;
 }
 
+STBTT_DEF void stbtt_MakeGlyphBitmapSubpixelPrefilter(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int prefilter_x, int prefilter_y, float *sub_x, float *sub_y, int glyph)
+{
+   stbtt_MakeGlyphBitmapSubpixel(info,
+                                 output,
+                                 out_w - (prefilter_x - 1),
+                                 out_h - (prefilter_y - 1),
+                                 out_stride,
+                                 scale_x,
+                                 scale_y,
+                                 shift_x,
+                                 shift_y,
+                                 glyph);
+
+   if (prefilter_x > 1)
+      stbtt__h_prefilter(output, out_w, out_h, out_stride, prefilter_x);
+
+   if (prefilter_y > 1)
+      stbtt__v_prefilter(output, out_w, out_h, out_stride, prefilter_y);
+
+   *sub_x = stbtt__oversample_shift(prefilter_x);
+   *sub_y = stbtt__oversample_shift(prefilter_y);
+}
+
 // rects array must be big enough to accommodate all characters in the given ranges
-STBTT_DEF int stbtt_PackFontRangesRenderIntoRects(stbtt_pack_context *spc, stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects)
+STBTT_DEF int stbtt_PackFontRangesRenderIntoRects(stbtt_pack_context *spc, const stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects)
 {
-   int i,j,k, return_value = 1;
+   int i,j,k, missing_glyph = -1, return_value = 1;
 
    // save current values
    int old_h_over = spc->h_oversample;
@@ -2903,7 +4226,7 @@ STBTT_DEF int stbtt_PackFontRangesRenderIntoRects(stbtt_pack_context *spc, stbtt
       sub_y = stbtt__oversample_shift(spc->v_oversample);
       for (j=0; j < ranges[i].num_chars; ++j) {
          stbrp_rect *r = &rects[k];
-         if (r->was_packed) {
+         if (r->was_packed && r->w != 0 && r->h != 0) {
             stbtt_packedchar *bc = &ranges[i].chardata_for_range[j];
             int advance, lsb, x0,y0,x1,y1;
             int codepoint = ranges[i].array_of_unicode_codepoints == NULL ? ranges[i].first_unicode_codepoint_in_range + j : ranges[i].array_of_unicode_codepoints[j];
@@ -2949,6 +4272,13 @@ STBTT_DEF int stbtt_PackFontRangesRenderIntoRects(stbtt_pack_context *spc, stbtt
             bc->yoff     =       (float)  y0 * recip_v + sub_y;
             bc->xoff2    =                (x0 + r->w) * recip_h + sub_x;
             bc->yoff2    =                (y0 + r->h) * recip_v + sub_y;
+
+            if (glyph == 0)
+               missing_glyph = j;
+         } else if (spc->skip_missing) {
+            return_value = 0;
+         } else if (r->was_packed && r->w == 0 && r->h == 0 && missing_glyph >= 0) {
+            ranges[i].chardata_for_range[j] = ranges[i].chardata_for_range[missing_glyph];
          } else {
             return_value = 0; // if any fail, report failure
          }
@@ -2969,7 +4299,7 @@ STBTT_DEF void stbtt_PackFontRangesPackRects(stbtt_pack_context *spc, stbrp_rect
    stbrp_pack_rects((stbrp_context *) spc->pack_info, rects, num_rects);
 }
 
-STBTT_DEF int stbtt_PackFontRanges(stbtt_pack_context *spc, unsigned char *fontdata, int font_index, stbtt_pack_range *ranges, int num_ranges)
+STBTT_DEF int stbtt_PackFontRanges(stbtt_pack_context *spc, const unsigned char *fontdata, int font_index, stbtt_pack_range *ranges, int num_ranges)
 {
    stbtt_fontinfo info;
    int i,j,n, return_value = 1;
@@ -2987,24 +4317,25 @@ STBTT_DEF int stbtt_PackFontRanges(stbtt_pack_context *spc, unsigned char *fontd
    n = 0;
    for (i=0; i < num_ranges; ++i)
       n += ranges[i].num_chars;
-         
+
    rects = (stbrp_rect *) STBTT_malloc(sizeof(*rects) * n, spc->user_allocator_context);
    if (rects == NULL)
       return 0;
 
+   info.userdata = spc->user_allocator_context;
    stbtt_InitFont(&info, fontdata, stbtt_GetFontOffsetForIndex(fontdata,font_index));
 
    n = stbtt_PackFontRangesGatherRects(spc, &info, ranges, num_ranges, rects);
 
    stbtt_PackFontRangesPackRects(spc, rects, n);
-  
+
    return_value = stbtt_PackFontRangesRenderIntoRects(spc, &info, ranges, num_ranges, rects);
 
    STBTT_free(rects, spc->user_allocator_context);
    return return_value;
 }
 
-STBTT_DEF int stbtt_PackFontRange(stbtt_pack_context *spc, unsigned char *fontdata, int font_index, float font_size,
+STBTT_DEF int stbtt_PackFontRange(stbtt_pack_context *spc, const unsigned char *fontdata, int font_index, float font_size,
             int first_unicode_codepoint_in_range, int num_chars_in_range, stbtt_packedchar *chardata_for_range)
 {
    stbtt_pack_range range;
@@ -3016,10 +4347,23 @@ STBTT_DEF int stbtt_PackFontRange(stbtt_pack_context *spc, unsigned char *fontda
    return stbtt_PackFontRanges(spc, fontdata, font_index, &range, 1);
 }
 
-STBTT_DEF void stbtt_GetPackedQuad(stbtt_packedchar *chardata, int pw, int ph, int char_index, float *xpos, float *ypos, stbtt_aligned_quad *q, int align_to_integer)
+STBTT_DEF void stbtt_GetScaledFontVMetrics(const unsigned char *fontdata, int index, float size, float *ascent, float *descent, float *lineGap)
+{
+   int i_ascent, i_descent, i_lineGap;
+   float scale;
+   stbtt_fontinfo info;
+   stbtt_InitFont(&info, fontdata, stbtt_GetFontOffsetForIndex(fontdata, index));
+   scale = size > 0 ? stbtt_ScaleForPixelHeight(&info, size) : stbtt_ScaleForMappingEmToPixels(&info, -size);
+   stbtt_GetFontVMetrics(&info, &i_ascent, &i_descent, &i_lineGap);
+   *ascent  = (float) i_ascent  * scale;
+   *descent = (float) i_descent * scale;
+   *lineGap = (float) i_lineGap * scale;
+}
+
+STBTT_DEF void stbtt_GetPackedQuad(const stbtt_packedchar *chardata, int pw, int ph, int char_index, float *xpos, float *ypos, stbtt_aligned_quad *q, int align_to_integer)
 {
    float ipw = 1.0f / pw, iph = 1.0f / ph;
-   stbtt_packedchar *b = chardata + char_index;
+   const stbtt_packedchar *b = chardata + char_index;
 
    if (align_to_integer) {
       float x = (float) STBTT_ifloor((*xpos + b->xoff) + 0.5f);
@@ -3043,6 +4387,385 @@ STBTT_DEF void stbtt_GetPackedQuad(stbtt_packedchar *chardata, int pw, int ph, i
    *xpos += b->xadvance;
 }
 
+//////////////////////////////////////////////////////////////////////////////
+//
+// sdf computation
+//
+
+#define STBTT_min(a,b)  ((a) < (b) ? (a) : (b))
+#define STBTT_max(a,b)  ((a) < (b) ? (b) : (a))
+
+static int stbtt__ray_intersect_bezier(float orig[2], float ray[2], float q0[2], float q1[2], float q2[2], float hits[2][2])
+{
+   float q0perp = q0[1]*ray[0] - q0[0]*ray[1];
+   float q1perp = q1[1]*ray[0] - q1[0]*ray[1];
+   float q2perp = q2[1]*ray[0] - q2[0]*ray[1];
+   float roperp = orig[1]*ray[0] - orig[0]*ray[1];
+
+   float a = q0perp - 2*q1perp + q2perp;
+   float b = q1perp - q0perp;
+   float c = q0perp - roperp;
+
+   float s0 = 0., s1 = 0.;
+   int num_s = 0;
+
+   if (a != 0.0) {
+      float discr = b*b - a*c;
+      if (discr > 0.0) {
+         float rcpna = -1 / a;
+         float d = (float) STBTT_sqrt(discr);
+         s0 = (b+d) * rcpna;
+         s1 = (b-d) * rcpna;
+         if (s0 >= 0.0 && s0 <= 1.0)
+            num_s = 1;
+         if (d > 0.0 && s1 >= 0.0 && s1 <= 1.0) {
+            if (num_s == 0) s0 = s1;
+            ++num_s;
+         }
+      }
+   } else {
+      // 2*b*s + c = 0
+      // s = -c / (2*b)
+      s0 = c / (-2 * b);
+      if (s0 >= 0.0 && s0 <= 1.0)
+         num_s = 1;
+   }
+
+   if (num_s == 0)
+      return 0;
+   else {
+      float rcp_len2 = 1 / (ray[0]*ray[0] + ray[1]*ray[1]);
+      float rayn_x = ray[0] * rcp_len2, rayn_y = ray[1] * rcp_len2;
+
+      float q0d =   q0[0]*rayn_x +   q0[1]*rayn_y;
+      float q1d =   q1[0]*rayn_x +   q1[1]*rayn_y;
+      float q2d =   q2[0]*rayn_x +   q2[1]*rayn_y;
+      float rod = orig[0]*rayn_x + orig[1]*rayn_y;
+
+      float q10d = q1d - q0d;
+      float q20d = q2d - q0d;
+      float q0rd = q0d - rod;
+
+      hits[0][0] = q0rd + s0*(2.0f - 2.0f*s0)*q10d + s0*s0*q20d;
+      hits[0][1] = a*s0+b;
+
+      if (num_s > 1) {
+         hits[1][0] = q0rd + s1*(2.0f - 2.0f*s1)*q10d + s1*s1*q20d;
+         hits[1][1] = a*s1+b;
+         return 2;
+      } else {
+         return 1;
+      }
+   }
+}
+
+static int equal(float *a, float *b)
+{
+   return (a[0] == b[0] && a[1] == b[1]);
+}
+
+static int stbtt__compute_crossings_x(float x, float y, int nverts, stbtt_vertex *verts)
+{
+   int i;
+   float orig[2], ray[2] = { 1, 0 };
+   float y_frac;
+   int winding = 0;
+
+   // make sure y never passes through a vertex of the shape
+   y_frac = (float) STBTT_fmod(y, 1.0f);
+   if (y_frac < 0.01f)
+      y += 0.01f;
+   else if (y_frac > 0.99f)
+      y -= 0.01f;
+
+   orig[0] = x;
+   orig[1] = y;
+
+   // test a ray from (-infinity,y) to (x,y)
+   for (i=0; i < nverts; ++i) {
+      if (verts[i].type == STBTT_vline) {
+         int x0 = (int) verts[i-1].x, y0 = (int) verts[i-1].y;
+         int x1 = (int) verts[i  ].x, y1 = (int) verts[i  ].y;
+         if (y > STBTT_min(y0,y1) && y < STBTT_max(y0,y1) && x > STBTT_min(x0,x1)) {
+            float x_inter = (y - y0) / (y1 - y0) * (x1-x0) + x0;
+            if (x_inter < x)
+               winding += (y0 < y1) ? 1 : -1;
+         }
+      }
+      if (verts[i].type == STBTT_vcurve) {
+         int x0 = (int) verts[i-1].x , y0 = (int) verts[i-1].y ;
+         int x1 = (int) verts[i  ].cx, y1 = (int) verts[i  ].cy;
+         int x2 = (int) verts[i  ].x , y2 = (int) verts[i  ].y ;
+         int ax = STBTT_min(x0,STBTT_min(x1,x2)), ay = STBTT_min(y0,STBTT_min(y1,y2));
+         int by = STBTT_max(y0,STBTT_max(y1,y2));
+         if (y > ay && y < by && x > ax) {
+            float q0[2],q1[2],q2[2];
+            float hits[2][2];
+            q0[0] = (float)x0;
+            q0[1] = (float)y0;
+            q1[0] = (float)x1;
+            q1[1] = (float)y1;
+            q2[0] = (float)x2;
+            q2[1] = (float)y2;
+            if (equal(q0,q1) || equal(q1,q2)) {
+               x0 = (int)verts[i-1].x;
+               y0 = (int)verts[i-1].y;
+               x1 = (int)verts[i  ].x;
+               y1 = (int)verts[i  ].y;
+               if (y > STBTT_min(y0,y1) && y < STBTT_max(y0,y1) && x > STBTT_min(x0,x1)) {
+                  float x_inter = (y - y0) / (y1 - y0) * (x1-x0) + x0;
+                  if (x_inter < x)
+                     winding += (y0 < y1) ? 1 : -1;
+               }
+            } else {
+               int num_hits = stbtt__ray_intersect_bezier(orig, ray, q0, q1, q2, hits);
+               if (num_hits >= 1)
+                  if (hits[0][0] < 0)
+                     winding += (hits[0][1] < 0 ? -1 : 1);
+               if (num_hits >= 2)
+                  if (hits[1][0] < 0)
+                     winding += (hits[1][1] < 0 ? -1 : 1);
+            }
+         }
+      }
+   }
+   return winding;
+}
+
+static float stbtt__cuberoot( float x )
+{
+   if (x<0)
+      return -(float) STBTT_pow(-x,1.0f/3.0f);
+   else
+      return  (float) STBTT_pow( x,1.0f/3.0f);
+}
+
+// x^3 + a*x^2 + b*x + c = 0
+static int stbtt__solve_cubic(float a, float b, float c, float* r)
+{
+   float s = -a / 3;
+   float p = b - a*a / 3;
+   float q = a * (2*a*a - 9*b) / 27 + c;
+   float p3 = p*p*p;
+   float d = q*q + 4*p3 / 27;
+   if (d >= 0) {
+      float z = (float) STBTT_sqrt(d);
+      float u = (-q + z) / 2;
+      float v = (-q - z) / 2;
+      u = stbtt__cuberoot(u);
+      v = stbtt__cuberoot(v);
+      r[0] = s + u + v;
+      return 1;
+   } else {
+      float u = (float) STBTT_sqrt(-p/3);
+      float v = (float) STBTT_acos(-STBTT_sqrt(-27/p3) * q / 2) / 3; // p3 must be negative, since d is negative
+      float m = (float) STBTT_cos(v);
+      float n = (float) STBTT_cos(v-3.141592/2)*1.732050808f;
+      r[0] = s + u * 2 * m;
+      r[1] = s - u * (m + n);
+      r[2] = s - u * (m - n);
+
+      //STBTT_assert( STBTT_fabs(((r[0]+a)*r[0]+b)*r[0]+c) < 0.05f);  // these asserts may not be safe at all scales, though they're in bezier t parameter units so maybe?
+      //STBTT_assert( STBTT_fabs(((r[1]+a)*r[1]+b)*r[1]+c) < 0.05f);
+      //STBTT_assert( STBTT_fabs(((r[2]+a)*r[2]+b)*r[2]+c) < 0.05f);
+      return 3;
+   }
+}
+
+STBTT_DEF unsigned char * stbtt_GetGlyphSDF(const stbtt_fontinfo *info, float scale, int glyph, int padding, unsigned char onedge_value, float pixel_dist_scale, int *width, int *height, int *xoff, int *yoff)
+{
+   float scale_x = scale, scale_y = scale;
+   int ix0,iy0,ix1,iy1;
+   int w,h;
+   unsigned char *data;
+
+   if (scale == 0) return NULL;
+
+   stbtt_GetGlyphBitmapBoxSubpixel(info, glyph, scale, scale, 0.0f,0.0f, &ix0,&iy0,&ix1,&iy1);
+
+   // if empty, return NULL
+   if (ix0 == ix1 || iy0 == iy1)
+      return NULL;
+
+   ix0 -= padding;
+   iy0 -= padding;
+   ix1 += padding;
+   iy1 += padding;
+
+   w = (ix1 - ix0);
+   h = (iy1 - iy0);
+
+   if (width ) *width  = w;
+   if (height) *height = h;
+   if (xoff  ) *xoff   = ix0;
+   if (yoff  ) *yoff   = iy0;
+
+   // invert for y-downwards bitmaps
+   scale_y = -scale_y;
+
+   {
+      int x,y,i,j;
+      float *precompute;
+      stbtt_vertex *verts;
+      int num_verts = stbtt_GetGlyphShape(info, glyph, &verts);
+      data = (unsigned char *) STBTT_malloc(w * h, info->userdata);
+      precompute = (float *) STBTT_malloc(num_verts * sizeof(float), info->userdata);
+
+      for (i=0,j=num_verts-1; i < num_verts; j=i++) {
+         if (verts[i].type == STBTT_vline) {
+            float x0 = verts[i].x*scale_x, y0 = verts[i].y*scale_y;
+            float x1 = verts[j].x*scale_x, y1 = verts[j].y*scale_y;
+            float dist = (float) STBTT_sqrt((x1-x0)*(x1-x0) + (y1-y0)*(y1-y0));
+            precompute[i] = (dist == 0) ? 0.0f : 1.0f / dist;
+         } else if (verts[i].type == STBTT_vcurve) {
+            float x2 = verts[j].x *scale_x, y2 = verts[j].y *scale_y;
+            float x1 = verts[i].cx*scale_x, y1 = verts[i].cy*scale_y;
+            float x0 = verts[i].x *scale_x, y0 = verts[i].y *scale_y;
+            float bx = x0 - 2*x1 + x2, by = y0 - 2*y1 + y2;
+            float len2 = bx*bx + by*by;
+            if (len2 != 0.0f)
+               precompute[i] = 1.0f / (bx*bx + by*by);
+            else
+               precompute[i] = 0.0f;
+         } else
+            precompute[i] = 0.0f;
+      }
+
+      for (y=iy0; y < iy1; ++y) {
+         for (x=ix0; x < ix1; ++x) {
+            float val;
+            float min_dist = 999999.0f;
+            float sx = (float) x + 0.5f;
+            float sy = (float) y + 0.5f;
+            float x_gspace = (sx / scale_x);
+            float y_gspace = (sy / scale_y);
+
+            int winding = stbtt__compute_crossings_x(x_gspace, y_gspace, num_verts, verts); // @OPTIMIZE: this could just be a rasterization, but needs to be line vs. non-tesselated curves so a new path
+
+            for (i=0; i < num_verts; ++i) {
+               float x0 = verts[i].x*scale_x, y0 = verts[i].y*scale_y;
+
+               if (verts[i].type == STBTT_vline && precompute[i] != 0.0f) {
+                  float x1 = verts[i-1].x*scale_x, y1 = verts[i-1].y*scale_y;
+
+                  float dist,dist2 = (x0-sx)*(x0-sx) + (y0-sy)*(y0-sy);
+                  if (dist2 < min_dist*min_dist)
+                     min_dist = (float) STBTT_sqrt(dist2);
+
+                  // coarse culling against bbox
+                  //if (sx > STBTT_min(x0,x1)-min_dist && sx < STBTT_max(x0,x1)+min_dist &&
+                  //    sy > STBTT_min(y0,y1)-min_dist && sy < STBTT_max(y0,y1)+min_dist)
+                  dist = (float) STBTT_fabs((x1-x0)*(y0-sy) - (y1-y0)*(x0-sx)) * precompute[i];
+                  STBTT_assert(i != 0);
+                  if (dist < min_dist) {
+                     // check position along line
+                     // x' = x0 + t*(x1-x0), y' = y0 + t*(y1-y0)
+                     // minimize (x'-sx)*(x'-sx)+(y'-sy)*(y'-sy)
+                     float dx = x1-x0, dy = y1-y0;
+                     float px = x0-sx, py = y0-sy;
+                     // minimize (px+t*dx)^2 + (py+t*dy)^2 = px*px + 2*px*dx*t + t^2*dx*dx + py*py + 2*py*dy*t + t^2*dy*dy
+                     // derivative: 2*px*dx + 2*py*dy + (2*dx*dx+2*dy*dy)*t, set to 0 and solve
+                     float t = -(px*dx + py*dy) / (dx*dx + dy*dy);
+                     if (t >= 0.0f && t <= 1.0f)
+                        min_dist = dist;
+                  }
+               } else if (verts[i].type == STBTT_vcurve) {
+                  float x2 = verts[i-1].x *scale_x, y2 = verts[i-1].y *scale_y;
+                  float x1 = verts[i  ].cx*scale_x, y1 = verts[i  ].cy*scale_y;
+                  float box_x0 = STBTT_min(STBTT_min(x0,x1),x2);
+                  float box_y0 = STBTT_min(STBTT_min(y0,y1),y2);
+                  float box_x1 = STBTT_max(STBTT_max(x0,x1),x2);
+                  float box_y1 = STBTT_max(STBTT_max(y0,y1),y2);
+                  // coarse culling against bbox to avoid computing cubic unnecessarily
+                  if (sx > box_x0-min_dist && sx < box_x1+min_dist && sy > box_y0-min_dist && sy < box_y1+min_dist) {
+                     int num=0;
+                     float ax = x1-x0, ay = y1-y0;
+                     float bx = x0 - 2*x1 + x2, by = y0 - 2*y1 + y2;
+                     float mx = x0 - sx, my = y0 - sy;
+                     float res[3] = {0.f,0.f,0.f};
+                     float px,py,t,it,dist2;
+                     float a_inv = precompute[i];
+                     if (a_inv == 0.0) { // if a_inv is 0, it's 2nd degree so use quadratic formula
+                        float a = 3*(ax*bx + ay*by);
+                        float b = 2*(ax*ax + ay*ay) + (mx*bx+my*by);
+                        float c = mx*ax+my*ay;
+                        if (a == 0.0) { // if a is 0, it's linear
+                           if (b != 0.0) {
+                              res[num++] = -c/b;
+                           }
+                        } else {
+                           float discriminant = b*b - 4*a*c;
+                           if (discriminant < 0)
+                              num = 0;
+                           else {
+                              float root = (float) STBTT_sqrt(discriminant);
+                              res[0] = (-b - root)/(2*a);
+                              res[1] = (-b + root)/(2*a);
+                              num = 2; // don't bother distinguishing 1-solution case, as code below will still work
+                           }
+                        }
+                     } else {
+                        float b = 3*(ax*bx + ay*by) * a_inv; // could precompute this as it doesn't depend on sample point
+                        float c = (2*(ax*ax + ay*ay) + (mx*bx+my*by)) * a_inv;
+                        float d = (mx*ax+my*ay) * a_inv;
+                        num = stbtt__solve_cubic(b, c, d, res);
+                     }
+                     dist2 = (x0-sx)*(x0-sx) + (y0-sy)*(y0-sy);
+                     if (dist2 < min_dist*min_dist)
+                        min_dist = (float) STBTT_sqrt(dist2);
+
+                     if (num >= 1 && res[0] >= 0.0f && res[0] <= 1.0f) {
+                        t = res[0], it = 1.0f - t;
+                        px = it*it*x0 + 2*t*it*x1 + t*t*x2;
+                        py = it*it*y0 + 2*t*it*y1 + t*t*y2;
+                        dist2 = (px-sx)*(px-sx) + (py-sy)*(py-sy);
+                        if (dist2 < min_dist * min_dist)
+                           min_dist = (float) STBTT_sqrt(dist2);
+                     }
+                     if (num >= 2 && res[1] >= 0.0f && res[1] <= 1.0f) {
+                        t = res[1], it = 1.0f - t;
+                        px = it*it*x0 + 2*t*it*x1 + t*t*x2;
+                        py = it*it*y0 + 2*t*it*y1 + t*t*y2;
+                        dist2 = (px-sx)*(px-sx) + (py-sy)*(py-sy);
+                        if (dist2 < min_dist * min_dist)
+                           min_dist = (float) STBTT_sqrt(dist2);
+                     }
+                     if (num >= 3 && res[2] >= 0.0f && res[2] <= 1.0f) {
+                        t = res[2], it = 1.0f - t;
+                        px = it*it*x0 + 2*t*it*x1 + t*t*x2;
+                        py = it*it*y0 + 2*t*it*y1 + t*t*y2;
+                        dist2 = (px-sx)*(px-sx) + (py-sy)*(py-sy);
+                        if (dist2 < min_dist * min_dist)
+                           min_dist = (float) STBTT_sqrt(dist2);
+                     }
+                  }
+               }
+            }
+            if (winding == 0)
+               min_dist = -min_dist;  // if outside the shape, value is negative
+            val = onedge_value + pixel_dist_scale * min_dist;
+            if (val < 0)
+               val = 0;
+            else if (val > 255)
+               val = 255;
+            data[(y-iy0)*w+(x-ix0)] = (unsigned char) val;
+         }
+      }
+      STBTT_free(precompute, info->userdata);
+      STBTT_free(verts, info->userdata);
+   }
+   return data;
+}
+
+STBTT_DEF unsigned char * stbtt_GetCodepointSDF(const stbtt_fontinfo *info, float scale, int codepoint, int padding, unsigned char onedge_value, float pixel_dist_scale, int *width, int *height, int *xoff, int *yoff)
+{
+   return stbtt_GetGlyphSDF(info, scale, stbtt_FindGlyphIndex(info, codepoint), padding, onedge_value, pixel_dist_scale, width, height, xoff, yoff);
+}
+
+STBTT_DEF void stbtt_FreeSDF(unsigned char *bitmap, void *userdata)
+{
+   STBTT_free(bitmap, userdata);
+}
 
 //////////////////////////////////////////////////////////////////////////////
 //
@@ -3050,7 +4773,7 @@ STBTT_DEF void stbtt_GetPackedQuad(stbtt_packedchar *chardata, int pw, int ph, i
 //
 
 // check if a utf8 string contains a prefix which is the utf16 string; if so return length of matching utf8 string
-static stbtt_int32 stbtt__CompareUTF8toUTF16_bigendian_prefix(const stbtt_uint8 *s1, stbtt_int32 len1, const stbtt_uint8 *s2, stbtt_int32 len2) 
+static stbtt_int32 stbtt__CompareUTF8toUTF16_bigendian_prefix(stbtt_uint8 *s1, stbtt_int32 len1, stbtt_uint8 *s2, stbtt_int32 len2)
 {
    stbtt_int32 i=0;
 
@@ -3089,9 +4812,9 @@ static stbtt_int32 stbtt__CompareUTF8toUTF16_bigendian_prefix(const stbtt_uint8
    return i;
 }
 
-STBTT_DEF int stbtt_CompareUTF8toUTF16_bigendian(const char *s1, int len1, const char *s2, int len2) 
+static int stbtt_CompareUTF8toUTF16_bigendian_internal(char *s1, int len1, char *s2, int len2)
 {
-   return len1 == stbtt__CompareUTF8toUTF16_bigendian_prefix((const stbtt_uint8*) s1, len1, (const stbtt_uint8*) s2, len2);
+   return len1 == stbtt__CompareUTF8toUTF16_bigendian_prefix((stbtt_uint8*) s1, len1, (stbtt_uint8*) s2, len2);
 }
 
 // returns results in whatever encoding you request... but note that 2-byte encodings
@@ -3147,7 +4870,7 @@ static int stbtt__matchpair(stbtt_uint8 *fc, stbtt_uint32 nm, stbtt_uint8 *name,
                         return 1;
                   } else if (matchlen < nlen && name[matchlen] == ' ') {
                      ++matchlen;
-                     if (stbtt_CompareUTF8toUTF16_bigendian((char*) (name+matchlen), nlen-matchlen, (char*)(fc+stringOffset+off),slen))
+                     if (stbtt_CompareUTF8toUTF16_bigendian_internal((char*) (name+matchlen), nlen-matchlen, (char*)(fc+stringOffset+off),slen))
                         return 1;
                   }
                } else {
@@ -3193,7 +4916,7 @@ static int stbtt__matches(stbtt_uint8 *fc, stbtt_uint32 offset, stbtt_uint8 *nam
    return 0;
 }
 
-STBTT_DEF int stbtt_FindMatchingFont(const unsigned char *font_collection, const char *name_utf8, stbtt_int32 flags)
+static int stbtt_FindMatchingFont_internal(unsigned char *font_collection, char *name_utf8, stbtt_int32 flags)
 {
    stbtt_int32 i;
    for (i=0;;++i) {
@@ -3204,11 +4927,71 @@ STBTT_DEF int stbtt_FindMatchingFont(const unsigned char *font_collection, const
    }
 }
 
+#if defined(__GNUC__) || defined(__clang__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#endif
+
+STBTT_DEF int stbtt_BakeFontBitmap(const unsigned char *data, int offset,
+                                float pixel_height, unsigned char *pixels, int pw, int ph,
+                                int first_char, int num_chars, stbtt_bakedchar *chardata)
+{
+   return stbtt_BakeFontBitmap_internal((unsigned char *) data, offset, pixel_height, pixels, pw, ph, first_char, num_chars, chardata);
+}
+
+STBTT_DEF int stbtt_GetFontOffsetForIndex(const unsigned char *data, int index)
+{
+   return stbtt_GetFontOffsetForIndex_internal((unsigned char *) data, index);
+}
+
+STBTT_DEF int stbtt_GetNumberOfFonts(const unsigned char *data)
+{
+   return stbtt_GetNumberOfFonts_internal((unsigned char *) data);
+}
+
+STBTT_DEF int stbtt_InitFont(stbtt_fontinfo *info, const unsigned char *data, int offset)
+{
+   return stbtt_InitFont_internal(info, (unsigned char *) data, offset);
+}
+
+STBTT_DEF int stbtt_FindMatchingFont(const unsigned char *fontdata, const char *name, int flags)
+{
+   return stbtt_FindMatchingFont_internal((unsigned char *) fontdata, (char *) name, flags);
+}
+
+STBTT_DEF int stbtt_CompareUTF8toUTF16_bigendian(const char *s1, int len1, const char *s2, int len2)
+{
+   return stbtt_CompareUTF8toUTF16_bigendian_internal((char *) s1, len1, (char *) s2, len2);
+}
+
+#if defined(__GNUC__) || defined(__clang__)
+#pragma GCC diagnostic pop
+#endif
+
 #endif // STB_TRUETYPE_IMPLEMENTATION
 
 
 // FULL VERSION HISTORY
 //
+//   1.25 (2021-07-11) many fixes
+//   1.24 (2020-02-05) fix warning
+//   1.23 (2020-02-02) query SVG data for glyphs; query whole kerning table (but only kern not GPOS)
+//   1.22 (2019-08-11) minimize missing-glyph duplication; fix kerning if both 'GPOS' and 'kern' are defined
+//   1.21 (2019-02-25) fix warning
+//   1.20 (2019-02-07) PackFontRange skips missing codepoints; GetScaleFontVMetrics()
+//   1.19 (2018-02-11) OpenType GPOS kerning (horizontal only), STBTT_fmod
+//   1.18 (2018-01-29) add missing function
+//   1.17 (2017-07-23) make more arguments const; doc fix
+//   1.16 (2017-07-12) SDF support
+//   1.15 (2017-03-03) make more arguments const
+//   1.14 (2017-01-16) num-fonts-in-TTC function
+//   1.13 (2017-01-02) support OpenType fonts, certain Apple fonts
+//   1.12 (2016-10-25) suppress warnings about casting away const with -Wcast-qual
+//   1.11 (2016-04-02) fix unused-variable warning
+//   1.10 (2016-04-02) allow user-defined fabs() replacement
+//                     fix memory leak if fontsize=0.0
+//                     fix warning from duplicate typedef
+//   1.09 (2016-01-16) warning fix; avoid crash on outofmem; use alloc userdata for PackFontRanges
 //   1.08 (2015-09-13) document stbtt_Rasterize(); fixes for vertical & horizontal edges
 //   1.07 (2015-08-01) allow PackFontRanges to accept arrays of sparse codepoints;
 //                     allow PackFontRanges to pack and render in separate phases;
@@ -3250,3 +5033,45 @@ STBTT_DEF int stbtt_FindMatchingFont(const unsigned char *font_collection, const
 //   0.2  (2009-03-11) Fix unsigned/signed char warnings
 //   0.1  (2009-03-09) First public release
 //
+
+/*
+------------------------------------------------------------------------------
+This software is available under 2 licenses -- choose whichever you prefer.
+------------------------------------------------------------------------------
+ALTERNATIVE A - MIT License
+Copyright (c) 2017 Sean Barrett
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+------------------------------------------------------------------------------
+ALTERNATIVE B - Public Domain (www.unlicense.org)
+This is free and unencumbered software released into the public domain.
+Anyone is free to copy, modify, publish, use, compile, sell, or distribute this
+software, either in source code form or as a compiled binary, for any purpose,
+commercial or non-commercial, and by any means.
+In jurisdictions that recognize copyright laws, the author or authors of this
+software dedicate any and all copyright interest in the software to the public
+domain. We make this dedication for the benefit of the public at large and to
+the detriment of our heirs and successors. We intend this dedication to be an
+overt act of relinquishment in perpetuity of all present and future rights to
+this software under copyright law.
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+------------------------------------------------------------------------------
+*/
diff --git a/drivers/video/tidss/tidss_drv.c b/drivers/video/tidss/tidss_drv.c
index 078e3e82e3..e285f255d7 100644
--- a/drivers/video/tidss/tidss_drv.c
+++ b/drivers/video/tidss/tidss_drv.c
@@ -901,18 +901,10 @@ static int tidss_drv_probe(struct udevice *dev)
 
 static int tidss_drv_remove(struct udevice *dev)
 {
-	u32 val;
-	int ret;
-	struct tidss_drv_priv *priv = dev_get_priv(dev);
+	if (CONFIG_IS_ENABLED(VIDEO_REMOVE)) {
+		struct tidss_drv_priv *priv = dev_get_priv(dev);
 
-	priv->base_common = dev_remap_addr_index(dev, 0);
-	REG_FLD_MOD(priv, DSS_SYSCONFIG, 1, 1, 1);
-	/* Wait for reset to complete */
-	ret = readl_poll_timeout(priv->base_common + DSS_SYSSTATUS,
-				 val, val & 1, 5000);
-	if (ret) {
-		dev_warn(priv->dev, "failed to reset priv\n");
-		return ret;
+		VP_REG_FLD_MOD(priv, 0, DSS_VP_CONTROL, 0, 0, 0);
 	}
 	return 0;
 }
@@ -939,5 +931,9 @@ U_BOOT_DRIVER(tidss_drv) = {
 	.probe = tidss_drv_probe,
 	.remove = tidss_drv_remove,
 	.priv_auto = sizeof(struct tidss_drv_priv),
+#if CONFIG_IS_ENABLED(VIDEO_REMOVE)
 	.flags = DM_FLAG_OS_PREPARE,
+#else
+	.flags = DM_FLAG_OS_PREPARE | DM_FLAG_LEAVE_PD_ON,
+#endif
 };
diff --git a/drivers/video/vesa.c b/drivers/video/vesa.c
index cac3bb0c33..50912c5c8b 100644
--- a/drivers/video/vesa.c
+++ b/drivers/video/vesa.c
@@ -23,8 +23,7 @@ static int vesa_video_probe(struct udevice *dev)
 
 	/* Use write-combining for the graphics memory, 256MB */
 	fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base;
-	mtrr_add_request(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
-	mtrr_commit(true);
+	mtrr_set_next_var(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
 
 	return 0;
 }
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index a21fde0e1d..b5b3b66259 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -596,6 +596,48 @@ int vidconsole_select_font(struct udevice *dev, const char *name, uint size)
 	return ops->select_font(dev, name, size);
 }
 
+int vidconsole_measure(struct udevice *dev, const char *name, uint size,
+		       const char *text, struct vidconsole_bbox *bbox)
+{
+	struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
+	struct vidconsole_ops *ops = vidconsole_get_ops(dev);
+	int ret;
+
+	if (ops->measure) {
+		ret = ops->measure(dev, name, size, text, bbox);
+		if (ret != -ENOSYS)
+			return ret;
+	}
+
+	bbox->valid = true;
+	bbox->x0 = 0;
+	bbox->y0 = 0;
+	bbox->x1 = priv->x_charsize * strlen(text);
+	bbox->y1 = priv->y_charsize;
+
+	return 0;
+}
+
+void vidconsole_push_colour(struct udevice *dev, enum colour_idx fg,
+			    enum colour_idx bg, struct vidconsole_colour *old)
+{
+	struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
+
+	old->colour_fg = vid_priv->colour_fg;
+	old->colour_bg = vid_priv->colour_bg;
+
+	vid_priv->colour_fg = video_index_to_colour(vid_priv, fg);
+	vid_priv->colour_bg = video_index_to_colour(vid_priv, bg);
+}
+
+void vidconsole_pop_colour(struct udevice *dev, struct vidconsole_colour *old)
+{
+	struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
+
+	vid_priv->colour_fg = old->colour_fg;
+	vid_priv->colour_bg = old->colour_bg;
+}
+
 /* Set up the number of rows and colours (rotated drivers override this) */
 static int vidconsole_pre_probe(struct udevice *dev)
 {
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 8396bdfb11..f743ed74c8 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -6,12 +6,14 @@
 #define LOG_CATEGORY UCLASS_VIDEO
 
 #include <common.h>
+#include <bloblist.h>
 #include <console.h>
 #include <cpu_func.h>
 #include <dm.h>
 #include <log.h>
 #include <malloc.h>
 #include <mapmem.h>
+#include <spl.h>
 #include <stdio_dev.h>
 #include <video.h>
 #include <video_console.h>
@@ -139,6 +141,79 @@ int video_reserve(ulong *addrp)
 	debug("Video frame buffers from %lx to %lx\n", gd->video_bottom,
 	      gd->video_top);
 
+	if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(VIDEO_HANDOFF)) {
+		struct video_handoff *ho;
+
+		ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0);
+		if (!ho)
+			return log_msg_ret("blf", -ENOENT);
+		ho->fb = *addrp;
+		ho->size = size;
+	}
+
+	return 0;
+}
+
+int video_fill_part(struct udevice *dev, int xstart, int ystart, int xend,
+		    int yend, u32 colour)
+{
+	struct video_priv *priv = dev_get_uclass_priv(dev);
+	void *start, *line;
+	int pixels = xend - xstart;
+	int row, i, ret;
+
+	start = priv->fb + ystart * priv->line_length;
+	start += xstart * VNBYTES(priv->bpix);
+	line = start;
+	for (row = ystart; row < yend; row++) {
+		switch (priv->bpix) {
+		case VIDEO_BPP8: {
+			u8 *dst = line;
+
+			if (IS_ENABLED(CONFIG_VIDEO_BPP8)) {
+				for (i = 0; i < pixels; i++)
+					*dst++ = colour;
+			}
+			break;
+		}
+		case VIDEO_BPP16: {
+			u16 *dst = line;
+
+			if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+				for (i = 0; i < pixels; i++)
+					*dst++ = colour;
+			}
+			break;
+		}
+		case VIDEO_BPP32: {
+			u32 *dst = line;
+
+			if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+				for (i = 0; i < pixels; i++)
+					*dst++ = colour;
+			}
+			break;
+		}
+		default:
+			return -ENOSYS;
+		}
+		line += priv->line_length;
+	}
+	ret = video_sync_copy(dev, start, line);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int video_reserve_from_bloblist(struct video_handoff *ho)
+{
+	gd->video_bottom = ho->fb;
+	gd->fb_base = ho->fb;
+	gd->video_top = ho->fb + ho->size;
+	debug("Reserving %luk for video using blob at: %08x\n",
+	      ((unsigned long)ho->size) >> 10, (u32)ho->fb);
+
 	return 0;
 }
 
@@ -208,7 +283,7 @@ static const struct vid_rgb colours[VID_COLOUR_COUNT] = {
 	{ 0xff, 0xff, 0xff },  /* white */
 };
 
-u32 video_index_to_colour(struct video_priv *priv, unsigned int idx)
+u32 video_index_to_colour(struct video_priv *priv, enum colour_idx idx)
 {
 	switch (priv->bpix) {
 	case VIDEO_BPP16:
@@ -220,14 +295,20 @@ u32 video_index_to_colour(struct video_priv *priv, unsigned int idx)
 		break;
 	case VIDEO_BPP32:
 		if (CONFIG_IS_ENABLED(VIDEO_BPP32)) {
-			if (priv->format == VIDEO_X2R10G10B10)
+			switch (priv->format) {
+			case VIDEO_X2R10G10B10:
 				return (colours[idx].r << 22) |
 				       (colours[idx].g << 12) |
 				       (colours[idx].b <<  2);
-			else
+			case VIDEO_RGBA8888:
+				return (colours[idx].r << 24) |
+				       (colours[idx].g << 16) |
+				       (colours[idx].b << 8) | 0xff;
+			default:
 				return (colours[idx].r << 16) |
 				       (colours[idx].g <<  8) |
 				       (colours[idx].b <<  0);
+			}
 		}
 		break;
 	default:
@@ -545,10 +626,12 @@ static int video_post_bind(struct udevice *dev)
 	addr = uc_priv->video_ptr;
 	size = alloc_fb(dev, &addr);
 	if (addr < gd->video_bottom) {
-		/* Device tree node may need the 'bootph-all' or
+		/*
+		 * Device tree node may need the 'bootph-all' or
 		 * 'bootph-some-ram' tag
 		 */
-		printf("Video device '%s' cannot allocate frame buffer memory -ensure the device is set up before relocation\n",
+		printf("Video device '%s' cannot allocate frame buffer memory "
+		       "- ensure the device is set up before relocation\n",
 		       dev->name);
 		return -ENOSPC;
 	}
diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c
index 47e52c4f69..45f003c825 100644
--- a/drivers/video/video_bmp.c
+++ b/drivers/video/video_bmp.c
@@ -43,6 +43,18 @@ static u32 get_bmp_col_x2r10g10b10(struct bmp_color_table_entry *cte)
 }
 
 /**
+ * get_bmp_col_rgba8888() - Convert a colour-table entry into a rgba8888 pixel value
+ *
+ * Return: value to write to the rgba8888 frame buffer for this palette entry
+ */
+static u32 get_bmp_col_rgba8888(struct bmp_color_table_entry *cte)
+{
+	return ((cte->red) |
+		(cte->green << 8U) |
+		(cte->blue << 16U) | 0xff << 24U);
+}
+
+/**
  * write_pix8() - Write a pixel from a BMP image into the framebuffer
  *
  * This handles frame buffers with 8, 16, 24 or 32 bits per pixel
@@ -71,6 +83,8 @@ static void write_pix8(u8 *fb, uint bpix, enum video_format eformat,
 			*fb++ = cte->blue;
 		} else if (eformat == VIDEO_X2R10G10B10) {
 			*(u32 *)fb = get_bmp_col_x2r10g10b10(cte);
+		} else if (eformat == VIDEO_RGBA8888) {
+			*(u32 *)fb = get_bmp_col_rgba8888(cte);
 		} else {
 			*fb++ = cte->blue;
 			*fb++ = cte->green;
@@ -382,6 +396,17 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
 						*fb++ = (pix >> 8) & 0xff;
 						*fb++ = (pix >> 16) & 0xff;
 						*fb++ = pix >> 24;
+					} else if (eformat == VIDEO_RGBA8888) {
+						u32 pix;
+
+						pix = *bmap++ << 8U; /* blue */
+						pix |= *bmap++ << 16U; /* green */
+						pix |= *bmap++ << 24U; /* red */
+
+						*fb++ = (pix >> 24) & 0xff;
+						*fb++ = (pix >> 16) & 0xff;
+						*fb++ = (pix >> 8) & 0xff;
+						*fb++ = 0xff;
 					} else {
 						*fb++ = *bmap++;
 						*fb++ = *bmap++;
@@ -409,6 +434,17 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
 						*fb++ = (pix >> 8) & 0xff;
 						*fb++ = (pix >> 16) & 0xff;
 						*fb++ = pix >> 24;
+					} else if (eformat == VIDEO_RGBA8888) {
+						u32 pix;
+
+						pix = *bmap++ << 8U; /* blue */
+						pix |= *bmap++ << 16U; /* green */
+						pix |= *bmap++ << 24U; /* red */
+						bmap++;
+						*fb++ = (pix >> 24) & 0xff;
+						*fb++ = (pix >> 16) & 0xff;
+						*fb++ = (pix >> 8) & 0xff;
+						*fb++ = 0xff; /* opacity */
 					} else {
 						*fb++ = *bmap++;
 						*fb++ = *bmap++;
diff --git a/drivers/video/zynqmp/Kconfig b/drivers/video/zynqmp/Kconfig
new file mode 100644
index 0000000000..b35cd1fb34
--- /dev/null
+++ b/drivers/video/zynqmp/Kconfig
@@ -0,0 +1,8 @@
+
+config VIDEO_ZYNQMP_DPSUB
+	bool "Enable video support for ZynqMP Display Port"
+	depends on ZYNQMP_POWER_DOMAIN
+	help
+	Enable support for Xilinx ZynqMP Display Port. Currently this file
+	is used as placeholder for driver. The main reason is to record
+	compatible string and calling power domain driver.
diff --git a/drivers/video/zynqmp/Makefile b/drivers/video/zynqmp/Makefile
new file mode 100644
index 0000000000..cc057f5356
--- /dev/null
+++ b/drivers/video/zynqmp/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2023, Advanced Micro Devices, Inc.
+
+obj-y += zynqmp_dpsub.o
diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c
new file mode 100644
index 0000000000..def4dcf626
--- /dev/null
+++ b/drivers/video/zynqmp/zynqmp_dpsub.c
@@ -0,0 +1,2225 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 - 2022, Xilinx Inc.
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Xilinx displayport(DP) Tx Subsytem driver
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <stdlib.h>
+#include <video.h>
+#include <wait_bit.h>
+#include <dm/device_compat.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <dm/device_compat.h>
+#include <asm/global_data.h>
+
+#include "zynqmp_dpsub.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Maximum supported resolution */
+#define WIDTH				1024
+#define HEIGHT				768
+
+static struct dp_dma dp_dma;
+static struct dp_dma_descriptor cur_desc __aligned(256);
+
+static void dma_init_video_descriptor(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	struct dp_dma_frame_buffer *frame_buffer = &dp_sub->frame_buffer;
+
+	cur_desc.control = DPDMA_DESC_PREAMBLE | DPDMA_DESC_IGNR_DONE |
+			   DPDMA_DESC_LAST_FRAME;
+	cur_desc.dscr_id = 0;
+	cur_desc.xfer_size = frame_buffer->size;
+	cur_desc.line_size_stride = ((frame_buffer->stride >> 4) <<
+				     DPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT) |
+				     (frame_buffer->line_size);
+	cur_desc.addr_ext = (((u32)(frame_buffer->address >>
+			     DPDMA_DESCRIPTOR_SRC_ADDR_WIDTH) <<
+			     DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) |
+			     (upper_32_bits((u64)&cur_desc)));
+	cur_desc.next_desr = lower_32_bits((u64)&cur_desc);
+	cur_desc.src_addr = lower_32_bits((u64)gd->fb_base);
+}
+
+static void dma_set_descriptor_address(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	flush_dcache_range((u64)&cur_desc,
+			   ALIGN(((u64)&cur_desc + sizeof(cur_desc)),
+				 CONFIG_SYS_CACHELINE_SIZE));
+	writel(upper_32_bits((u64)&cur_desc), dp_sub->dp_dma->base_addr +
+	       DPDMA_CH3_DSCR_STRT_ADDRE);
+	writel(lower_32_bits((u64)&cur_desc), dp_sub->dp_dma->base_addr +
+	       DPDMA_CH3_DSCR_STRT_ADDR);
+}
+
+static void dma_setup_channel(struct udevice *dev)
+{
+	dma_init_video_descriptor(dev);
+	dma_set_descriptor_address(dev);
+}
+
+static void dma_set_channel_state(struct udevice *dev)
+{
+	u32 mask = 0, regval = 0;
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	mask = DPDMA_CH_CNTL_EN_MASK | DPDMA_CH_CNTL_PAUSE_MASK;
+	regval = DPDMA_CH_CNTL_EN_MASK;
+
+	clrsetbits_le32(dp_sub->dp_dma->base_addr + DPDMA_CH3_CNTL,
+			mask, regval);
+}
+
+static void dma_trigger(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 trigger;
+
+	trigger = DPDMA_GBL_TRG_CH3_MASK;
+	dp_sub->dp_dma->gfx.trigger_status = DPDMA_TRIGGER_DONE;
+	writel(trigger, dp_sub->dp_dma->base_addr + DPDMA_GBL);
+}
+
+static void dma_vsync_intr_handler(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	dma_setup_channel(dev);
+	dma_set_channel_state(dev);
+	dma_trigger(dev);
+
+	/* Clear VSync Interrupt */
+	writel(DPDMA_ISR_VSYNC_INT_MASK, dp_sub->dp_dma->base_addr + DPDMA_ISR);
+}
+
+/**
+ * wait_phy_ready() - Wait for the DisplayPort PHY to come out of reset
+ * @dev:  The DP device
+ *
+ * Return: 0 if wait succeeded, -ve if error occurred
+ */
+static int wait_phy_ready(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 timeout = 100, phy_status;
+	u8 phy_ready_mask =  DP_PHY_STATUS_RESET_LANE_0_DONE_MASK |
+			     DP_PHY_STATUS_GT_PLL_LOCK_MASK;
+
+	/* Wait until the PHY is ready. */
+	do {
+		udelay(20);
+		phy_status = readl(dp_sub->base_addr + DP_PHY_STATUS);
+		phy_status &= phy_ready_mask;
+		/* Protect against an infinite loop. */
+		if (!timeout--)
+			return -ETIMEDOUT;
+	} while (phy_status != phy_ready_mask);
+
+	return 0;
+}
+
+static int init_dp_tx(struct udevice *dev)
+{
+	u32 status, phyval, regval, rate;
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	phyval = readl(dp_sub->base_addr + DP_PHY_CONFIG);
+	writel(DP_SOFT_RESET_EN, dp_sub->base_addr + DP_SOFT_RESET);
+	status = readl(dp_sub->base_addr + DP_SOFT_RESET);
+	writel(DP_DISABLE, dp_sub->base_addr + DP_ENABLE);
+
+	regval = (readl(dp_sub->base_addr + DP_AUX_CLK_DIVIDER) &
+		  ~DP_AUX_CLK_DIVIDER_VAL_MASK) |
+		  (60 << 8) |
+		  (dp_sub->clock / 1000000);
+	writel(regval, dp_sub->base_addr + DP_AUX_CLK_DIVIDER);
+
+	writel(DP_PHY_CLOCK_SELECT_540GBPS, dp_sub->base_addr + DP_PHY_CLOCK_SELECT);
+
+	regval = phyval & ~DP_PHY_CONFIG_GT_ALL_RESET_MASK;
+	writel(regval, dp_sub->base_addr + DP_PHY_CONFIG);
+	status = wait_phy_ready(dev);
+	if (status)
+		return -EINVAL;
+
+	writel(DP_ENABLE, dp_sub->base_addr + DP_ENABLE);
+
+	rate = ~DP_INTR_HPD_PULSE_DETECTED_MASK & ~DP_INTR_HPD_EVENT_MASK
+		& ~DP_INTR_HPD_IRQ_MASK;
+	writel(rate, dp_sub->base_addr + DP_INTR_MASK);
+	return 0;
+}
+
+static int set_nonlive_gfx_format(struct udevice *dev, enum av_buf_video_format format)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	struct av_buf_vid_attribute *ptr = (struct av_buf_vid_attribute *)avbuf_supported_formats;
+
+	while (1) {
+		dev_dbg(dev, "Format %d\n", ptr->video_format);
+
+		if (!ptr->video_format)
+			return -EINVAL;
+
+		if (ptr->video_format == format) {
+			dp_sub->non_live_graphics = ptr;
+			break;
+		}
+		ptr++;
+	}
+	dev_dbg(dev, "Video format found. BPP %d\n", dp_sub->non_live_graphics->bpp);
+	return 0;
+}
+
+/* DP dma setup */
+static void set_qos(struct udevice *dev, u8 qos)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u8 index;
+	u32 regval = 0, mask;
+
+	regval = (((u32)qos << DPDMA_CH_CNTL_QOS_DATA_RD_SHIFT) |
+		 ((u32)qos << DPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT) |
+		 ((u32)qos << DPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT));
+
+	mask = DPDMA_CH_CNTL_QOS_DATA_RD_MASK |
+	       DPDMA_CH_CNTL_QOS_DSCR_RD_MASK |
+	       DPDMA_CH_CNTL_QOS_DSCR_WR_MASK;
+	for (index = 0; index <= DPDMA_AUDIO_CHANNEL1; index++) {
+		clrsetbits_le32(dp_sub->dp_dma->base_addr +
+				DPDMA_CH0_CNTL +
+				(DPDMA_CH_OFFSET * (u32)index),
+				mask, regval);
+	}
+}
+
+static void enable_gfx_buffers(struct udevice *dev, u8 enable)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 regval = 0;
+
+	regval = (0xF << AVBUF_CHBUF3_BURST_LEN_SHIFT) |
+			 AVBUF_CHBUF3_FLUSH_MASK;
+	writel(regval, dp_sub->base_addr + AVBUF_CHBUF3);
+	if (enable) {
+		regval = (0xF << AVBUF_CHBUF3_BURST_LEN_SHIFT) |
+				 AVBUF_CHBUF0_EN_MASK;
+		writel(regval, dp_sub->base_addr + AVBUF_CHBUF3);
+	}
+}
+
+static void avbuf_video_select(struct udevice *dev, enum av_buf_video_stream vid_stream,
+			       enum av_buf_gfx_stream gfx_stream)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	dp_sub->av_mode.video_src = vid_stream;
+	dp_sub->av_mode.gfx_src = gfx_stream;
+
+	clrsetbits_le32(dp_sub->base_addr +
+			AVBUF_BUF_OUTPUT_AUD_VID_SELECT,
+			AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK |
+			AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK,
+			vid_stream | gfx_stream);
+}
+
+static void config_gfx_pipeline(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u16 *csc_matrix, *offset_matrix;
+	u32 regval = 0, index = 0, *scaling_factors = NULL;
+	u16 rgb_coeffs[] = { 0x1000, 0x0000, 0x0000,
+			     0x0000, 0x1000, 0x0000,
+			     0x0000, 0x0000, 0x1000 };
+	u16 rgb_offset[] = { 0x0000, 0x0000, 0x0000 };
+	struct av_buf_vid_attribute *video = dp_sub->non_live_graphics;
+
+	scaling_factors = video->sf;
+
+	clrsetbits_le32(dp_sub->base_addr + AVBUF_BUF_FORMAT,
+			AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK,
+			(video->value) << AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT);
+
+	for (index = 0; index < 3; index++) {
+		writel(scaling_factors[index], dp_sub->base_addr +
+		       AVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR + (index * 4));
+	}
+	regval = (video->is_rgb << AVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT) |
+								video->sampling_en;
+	writel(regval, dp_sub->base_addr + AVBUF_V_BLEND_LAYER1_CONTROL);
+
+	if (video->is_rgb) {
+		csc_matrix = rgb_coeffs;
+		offset_matrix = rgb_offset;
+	}
+	/* Program Colorspace conversion coefficients */
+	for (index = 9; index < 12; index++) {
+		writel(offset_matrix[index - 9], dp_sub->base_addr +
+		       AVBUF_V_BLEND_IN2CSC_COEFF0 + (index * 4));
+	}
+
+	/* Program Colorspace conversion matrix */
+	for (index = 0; index < 9; index++) {
+		writel(csc_matrix[index], dp_sub->base_addr +
+		       AVBUF_V_BLEND_IN2CSC_COEFF0 + (index * 4));
+	}
+}
+
+static void set_blender_alpha(struct udevice *dev, u8 alpha, u8 enable)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 regval;
+
+	regval = enable;
+	regval |= alpha << AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT;
+	writel(regval, dp_sub->base_addr +
+	       AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG);
+}
+
+static void config_output_video(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 regval = 0, index;
+	u16 rgb_coeffs[] = { 0x1000, 0x0000, 0x0000,
+			     0x0000, 0x1000, 0x0000,
+			     0x0000, 0x0000, 0x1000 };
+	u16 rgb_offset[] = { 0x0000, 0x0000, 0x0000 };
+	u16 *matrix_coeff = rgb_coeffs, *matrix_offset = rgb_offset;
+
+	struct av_buf_vid_attribute *output_video = dp_sub->non_live_graphics;
+
+	regval |= output_video->sampling_en <<
+		  AVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT;
+	regval |= output_video->value;
+	writel(regval, dp_sub->base_addr + AVBUF_V_BLEND_OUTPUT_VID_FORMAT);
+
+	for (index = 0; index < 9; index++) {
+		writel(matrix_coeff[index], dp_sub->base_addr +
+		       AVBUF_V_BLEND_RGB2YCBCR_COEFF0 + (index * 4));
+	}
+
+	for (index = 0; index < 3; index++) {
+		writel((matrix_offset[index] <<
+			AVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT),
+			dp_sub->base_addr +
+			AVBUF_V_BLEND_LUMA_OUTCSC_OFFSET
+			+ (index * 4));
+	}
+
+	set_blender_alpha(dev, 0, 0);
+}
+
+static void config_msa_sync_clk_mode(struct udevice *dev, u8 enable)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	struct main_stream_attributes *msa_config;
+
+	msa_config = &dp_sub->msa_config;
+	msa_config->synchronous_clock_mode = enable;
+
+	if (enable == 1) {
+		msa_config->misc0 |= (1 <<
+				     DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT);
+	} else {
+		msa_config->misc0 &= ~(1 <<
+				      DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT);
+	}
+}
+
+static void av_buf_soft_reset(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	writel(AVBUF_BUF_SRST_REG_VID_RST_MASK,
+	       dp_sub->base_addr + AVBUF_BUF_SRST_REG);
+	writel(0, dp_sub->base_addr + AVBUF_BUF_SRST_REG);
+}
+
+static void set_video_clk_source(struct udevice *dev, u8 video_clk, u8 audio_clk)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 regval = 0;
+
+	if (dp_sub->av_mode.video_src != AVBUF_VIDSTREAM1_LIVE &&
+	    dp_sub->av_mode.gfx_src != AVBUF_VIDSTREAM2_LIVE_GFX) {
+		regval = 1 << AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT;
+	} else if (dp_sub->av_mode.video_src == AVBUF_VIDSTREAM1_LIVE ||
+		   dp_sub->av_mode.gfx_src == AVBUF_VIDSTREAM2_LIVE_GFX) {
+		video_clk = AVBUF_PL_CLK;
+	}
+
+	regval |= (video_clk << AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT) |
+		  (audio_clk << AVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT);
+	writel(regval, dp_sub->base_addr + AVBUF_BUF_AUD_VID_CLK_SOURCE);
+
+	av_buf_soft_reset(dev);
+}
+
+static int init_dpdma_subsys(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	dp_sub->dp_dma->base_addr = DPDMA_BASE_ADDRESS;
+	dp_sub->dp_dma->gfx.channel.cur = NULL;
+	dp_sub->dp_dma->gfx.trigger_status = DPDMA_TRIGGER_DONE;
+
+	set_qos(dev, 11);
+	return 0;
+}
+
+/**
+ * is_dp_connected() - Check if there is a connected RX device
+ * @dev: The DP device
+ *
+ *
+ * Return: true if a connected RX device was detected, false otherwise
+ */
+static bool is_dp_connected(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 status;
+	u8 retries = 0;
+
+	do {
+		status = readl(dp_sub->base_addr +
+				DP_INTERRUPT_SIG_STATE)
+				& DP_INTERRUPT_SIG_STATE_HPD_STATE_MASK;
+
+		if (retries > DP_IS_CONNECTED_MAX_TIMEOUT_COUNT)
+			return 0;
+
+		retries++;
+		udelay(1000);
+	} while (status == 0);
+
+	return 1;
+}
+
+/**
+ * aux_wait_ready() -  Wait until another request is no longer in progress
+ * @dev: The DP device
+ *
+ * Return: 0 if wait succeeded, -ve if error occurred
+ */
+static int aux_wait_ready(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 status, timeout = 100;
+
+	do {
+		status = readl(dp_sub->base_addr +
+			       DP_INTERRUPT_SIG_STATE);
+		if (!timeout--)
+			return -ETIMEDOUT;
+
+		udelay(20);
+	} while (status & DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK);
+
+	return 0;
+}
+
+/**
+ * aux_wait_reply() - Wait for reply on AUX channel
+ * @dev: The DP device
+ *
+ * Wait for a reply indicating that the most recent AUX request
+ * has been received by the RX device.
+ *
+ * Return: 0 if wait succeeded, -ve if error occurred
+ */
+static int aux_wait_reply(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 timeout = DP_AUX_MAX_WAIT, status;
+
+	while (timeout > 0) {
+		status = readl(dp_sub->base_addr + DP_REPLY_STATUS);
+		if (status & DP_REPLY_STATUS_REPLY_ERROR_MASK)
+			return -ETIMEDOUT;
+
+		if ((status & DP_REPLY_STATUS_REPLY_RECEIVED_MASK) &&
+		    !(status & DP_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) &&
+		    !(status & DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK)) {
+			return 0;
+		}
+		timeout--;
+		udelay(20);
+	}
+	return -ETIMEDOUT;
+}
+
+/**
+ * aux_request_send() - Send request on the AUX channel
+ * @dev:     The DP device
+ * @request: The request to send
+ *
+ * Submit the supplied AUX request to the RX device over the AUX
+ * channel by writing the command, the destination address, (the write buffer
+ * for write commands), and the data size to the DisplayPort TX core.
+ *
+ * This is the lower-level sending routine, which is called by aux_request().
+ *
+ * Return: 0 if request was sent successfully, -ve on error
+ */
+static int aux_request_send(struct udevice *dev, struct aux_transaction *request)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 timeout_count = 0, status;
+	u8 index;
+
+	do {
+		status = readl(dp_sub->base_addr +
+			       DP_REPLY_STATUS);
+
+		udelay(20);
+		timeout_count++;
+		if (timeout_count >= DP_AUX_MAX_TIMEOUT_COUNT)
+			return -ETIMEDOUT;
+
+	} while ((status & DP_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) ||
+		(status & DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK));
+	/* Set the address for the request. */
+	writel(request->address, dp_sub->base_addr + DP_AUX_ADDRESS);
+
+	if (request->cmd_code == DP_AUX_CMD_WRITE ||
+	    request->cmd_code == DP_AUX_CMD_I2C_WRITE ||
+	    request->cmd_code == DP_AUX_CMD_I2C_WRITE_MOT) {
+		/* Feed write data into the DisplayPort TX core's write FIFO. */
+		for (index = 0; index < request->num_bytes; index++) {
+			writel(request->data[index],
+			       dp_sub->base_addr +
+			       DP_AUX_WRITE_FIFO);
+		}
+	}
+
+	status = ((request->cmd_code << DP_AUX_CMD_SHIFT) |
+		 ((request->num_bytes - 1) &
+		 DP_AUX_CMD_NBYTES_TRANSFER_MASK));
+
+	/* Submit the command and the data size. */
+	writel(((request->cmd_code << DP_AUX_CMD_SHIFT) |
+		((request->num_bytes - 1) & DP_AUX_CMD_NBYTES_TRANSFER_MASK)),
+		dp_sub->base_addr + DP_AUX_CMD);
+
+	/* Check for a reply from the RX device to the submitted request. */
+	status = aux_wait_reply(dev);
+	if (status)
+		/* Waiting for a reply timed out. */
+		return -ETIMEDOUT;
+
+	/* Analyze the reply. */
+	status = readl(dp_sub->base_addr + DP_AUX_REPLY_CODE);
+	if (status == DP_AUX_REPLY_CODE_DEFER ||
+	    status == DP_AUX_REPLY_CODE_I2C_DEFER) {
+		/* The request was deferred. */
+		return -EAGAIN;
+	} else if (status == DP_AUX_REPLY_CODE_NACK ||
+		   status == DP_AUX_REPLY_CODE_I2C_NACK) {
+		/* The request was not acknowledged. */
+		return -EIO;
+	}
+
+	/* The request was acknowledged. */
+	if (request->cmd_code == DP_AUX_CMD_READ ||
+	    request->cmd_code == DP_AUX_CMD_I2C_READ ||
+	    request->cmd_code == DP_AUX_CMD_I2C_READ_MOT) {
+		/* Wait until all data has been received. */
+		timeout_count = 0;
+		do {
+			status = readl(dp_sub->base_addr +
+				       DP_REPLY_DATA_COUNT);
+			udelay(100);
+			timeout_count++;
+			if (timeout_count >= DP_AUX_MAX_TIMEOUT_COUNT)
+				return -ETIMEDOUT;
+		} while (status != request->num_bytes);
+
+		/* Obtain the read data from the reply FIFO. */
+		for (index = 0; index < request->num_bytes; index++) {
+			request->data[index] = readl(dp_sub->base_addr +
+						     DP_AUX_REPLY_DATA);
+		}
+	}
+	return 0;
+}
+
+/**
+ * aux_request() - Submit request on the AUX channel
+ * @dev:     The DP device
+ * @request: The request to submit
+ *
+ * Submit the supplied AUX request to the RX device over the AUX
+ * channel. If waiting for a reply times out, or if the DisplayPort TX core
+ * indicates that the request was deferred, the request is sent again (up to a
+ * maximum specified by DP_AUX_MAX_DEFER_COUNT|DP_AUX_MAX_TIMEOUT_COUNT).
+ *
+ * Return: 0 if request was submitted successfully, -ve on error
+ */
+static int aux_request(struct udevice *dev, struct aux_transaction *request)
+{
+	u32 status, defer_count = 0, timeout_count = 0;
+
+	do {
+		status = aux_wait_ready(dev);
+		if (status) {
+			/* The RX device isn't ready yet. */
+			timeout_count++;
+			continue;
+		}
+		/* Send the request. */
+		status = aux_request_send(dev, request);
+		if (status == -EAGAIN) {
+			/* The request was deferred. */
+			defer_count++;
+		} else if (status == -ETIMEDOUT) {
+			/* Waiting for a reply timed out. */
+			timeout_count++;
+		} else {
+			return status;
+		}
+
+		udelay(100);
+	} while ((defer_count < DP_AUX_MAX_DEFER_COUNT) &&
+		(timeout_count < DP_AUX_MAX_TIMEOUT_COUNT));
+
+	/* The request was not successfully received by the RX device. */
+	return -ETIMEDOUT;
+}
+
+/**
+ * aux_common() - Common (read/write) AUX communication transmission
+ * @dev:       The DP device
+ * @cmd_type:  Command code of the transaction
+ * @address:   The DPCD address of the transaction
+ * @num_bytes: Number of bytes in the payload data
+ * @data:      The payload data of the AUX command
+ *
+ * Common sequence of submitting an AUX command for AUX read, AUX write,
+ * I2C-over-AUX read, and I2C-over-AUX write transactions. If required, the
+ * reads and writes are split into multiple requests, each acting on a maximum
+ * of 16 bytes.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+static int aux_common(struct udevice *dev, u32 cmd_type, u32 address,
+		      u32 num_bytes, u8 *data)
+{
+	u32 status, bytes_left;
+	struct aux_transaction request;
+
+	if (!is_dp_connected(dev))
+		return -ENODEV;
+
+	/*
+	 * Set the start address for AUX transactions. For I2C transactions,
+	 * this is the address of the I2C bus.
+	 */
+	request.address = address;
+	bytes_left = num_bytes;
+	while (bytes_left > 0) {
+		request.cmd_code = cmd_type;
+
+		if (cmd_type == DP_AUX_CMD_READ ||
+		    cmd_type == DP_AUX_CMD_WRITE) {
+			/* Increment address for normal AUX transactions. */
+			request.address = address + (num_bytes - bytes_left);
+		}
+
+		/* Increment the pointer to the supplied data buffer. */
+		request.data = &data[num_bytes - bytes_left];
+
+		if (bytes_left > 16)
+			request.num_bytes = 16;
+		else
+			request.num_bytes = bytes_left;
+
+		bytes_left -= request.num_bytes;
+
+		if (cmd_type == DP_AUX_CMD_I2C_READ && bytes_left > 0) {
+			/*
+			 * Middle of a transaction I2C read request. Override
+			 * the command code that was set to CmdType.
+			 */
+			request.cmd_code = DP_AUX_CMD_I2C_READ_MOT;
+		} else if (cmd_type == DP_AUX_CMD_I2C_WRITE && bytes_left > 0) {
+			/*
+			 * Middle of a transaction I2C write request. Override
+			 * the command code that was set to CmdType.
+			 */
+			request.cmd_code = DP_AUX_CMD_I2C_WRITE_MOT;
+		}
+
+		status = aux_request(dev, &request);
+		if (status)
+			return status;
+	}
+	return 0;
+}
+
+/**
+ * aux_write() - Issue AUX write request
+ * @dev:            The DP device
+ * @dpcd_address:   The DPCD address to write to
+ * @bytes_to_write: Number of bytes to write
+ * @write_data:     Buffer containig data to be written
+ *
+ * Issue a write request over the AUX channel that will write to
+ * the RX device's DisplayPort Configuration data (DPCD) address space. The
+ * write message will be divided into multiple transactions which write a
+ * maximum of 16 bytes each.
+ *
+ * Return: 0 if write operation was successful, -ve on error
+ */
+static int aux_write(struct udevice *dev, u32 dpcd_address, u32 bytes_to_write,
+		     void *write_data)
+{
+	return aux_common(dev, DP_AUX_CMD_WRITE, dpcd_address,
+			  bytes_to_write, (u8 *)write_data);
+}
+
+/**
+ * aux_read() - Issue AUX read request
+ * @dev:           The DP device
+ * @dpcd_address:  The DPCD address to read from
+ * @bytes_to_read: Number of bytes to read
+ * @read_data:     Buffer to receive the read data
+ *
+ * Issue a read request over the AUX channel that will read from the RX
+ * device's DisplayPort Configuration data (DPCD) address space. The read
+ * message will be divided into multiple transactions which read a maximum of
+ * 16 bytes each.
+ *
+ * Return: 0 if read operation was successful, -ve on error
+ */
+static int aux_read(struct udevice *dev, u32 dpcd_address, u32 bytes_to_read, void *read_data)
+{
+	return aux_common(dev, DP_AUX_CMD_READ, dpcd_address,
+			  bytes_to_read, (u8 *)read_data);
+}
+
+static int dp_tx_wakeup(struct udevice *dev)
+{
+	u32 status;
+	u8 aux_data;
+
+	aux_data = 0x1;
+	status = aux_write(dev, DP_DPCD_SET_POWER_DP_PWR_VOLTAGE, 1, &aux_data);
+	if (status)
+		debug("! 1st power wake-up - AUX write failed.\n");
+	status = aux_write(dev, DP_DPCD_SET_POWER_DP_PWR_VOLTAGE, 1, &aux_data);
+	if (status)
+		debug("! 2nd power wake-up - AUX write failed.\n");
+
+	return status;
+}
+
+/**
+ * enable_main_link() - Switch on main link for a device
+ * @dev: The DP device
+ */
+static void enable_main_link(struct udevice *dev, u8 enable)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	/* Reset the scrambler. */
+	writel(1, dp_sub->base_addr + DP_FORCE_SCRAMBLER_RESET);
+	/* Enable the main stream. */
+	writel(enable, dp_sub->base_addr + DP_ENABLE_MAIN_STREAM);
+}
+
+/**
+ * get_rx_capabilities() - Check if capabilities of RX device are valid for TX
+ *                         device
+ * @dev: The DP device
+ *
+ * Return: 0 if the capabilities of the RX device are valid for the TX device,
+ *         -ve if not, of an error occurred during capability determination
+ */
+static int get_rx_capabilities(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u8 rx_max_link_rate, rx_max_lane_count, *dpcd = NULL;
+	u32 status;
+	struct link_config *link_config = NULL;
+
+	dpcd = dp_sub->dpcd_rx_caps;
+	link_config = &dp_sub->link_config;
+
+	status = aux_read(dev, DP_DPCD_RECEIVER_CAP_FIELD_START, 16, dpcd);
+	if (status)
+		return status;
+
+	rx_max_link_rate = dpcd[DP_DPCD_MAX_LINK_RATE];
+	rx_max_lane_count = dpcd[DP_DPCD_MAX_LANE_COUNT] & DP_DPCD_MAX_LANE_COUNT_MASK;
+	link_config->max_link_rate = (rx_max_link_rate > DP_0_LINK_RATE) ?
+				      DP_0_LINK_RATE : rx_max_link_rate;
+	link_config->max_lane_count = (rx_max_lane_count > DP_0_LANE_COUNT) ?
+				       DP_0_LANE_COUNT : rx_max_lane_count;
+	link_config->support_enhanced_framing_mode = dpcd[DP_DPCD_MAX_LANE_COUNT] &
+						     DP_DPCD_ENHANCED_FRAME_SUPPORT_MASK;
+	link_config->support_downspread_control = dpcd[DP_DPCD_MAX_DOWNSPREAD] &
+						  DP_DPCD_MAX_DOWNSPREAD_MASK;
+
+	return 0;
+}
+
+/**
+ * set_enhanced_frame_mode() - Enable/Disable enhanced frame mode
+ * @dev:    The DP device
+ * @enable: Flag to determine whether to enable (1) or disable (0) the enhanced
+ *          frame mode
+ *
+ * Enable or disable the enhanced framing symbol sequence for
+ * both the DisplayPort TX core and the RX device.
+ *
+ * Return: 0 if enabling/disabling the enhanced frame mode was successful, -ve
+ *         on error
+ */
+static int set_enhanced_frame_mode(struct udevice *dev, u8 enable)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 status;
+	u8 regval;
+
+	dp_sub->link_config.enhanced_framing_mode = enable;
+	/* Write enhanced frame mode enable to the DisplayPort TX core. */
+	writel(dp_sub->link_config.enhanced_framing_mode,
+	       dp_sub->base_addr + DP_ENHANCED_FRAME_EN);
+
+	/* Preserve the current RX device settings. */
+	status = aux_read(dev, DP_DPCD_LANE_COUNT_SET, 0x1, &regval);
+	if (status)
+		return status;
+
+	if (dp_sub->link_config.enhanced_framing_mode)
+		regval |= DP_DPCD_ENHANCED_FRAME_EN_MASK;
+	else
+		regval &= ~DP_DPCD_ENHANCED_FRAME_EN_MASK;
+
+	/* Write enhanced frame mode enable to the RX device. */
+	return aux_write(dev, DP_DPCD_LANE_COUNT_SET, 0x1, &regval);
+}
+
+/**
+ * set_lane_count() - Set the lane count
+ * @dev:        The DP device
+ * @lane_count: Lane count to set
+ *
+ * Set the number of lanes to be used by the main link for both
+ * the DisplayPort TX core and the RX device.
+ *
+ * Return: 0 if setting the lane count was successful, -ve on error
+ */
+static int set_lane_count(struct udevice *dev, u8 lane_count)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 status;
+	u8 regval;
+
+	dp_sub->link_config.lane_count = lane_count;
+	/* Write the new lane count to the DisplayPort TX core. */
+	writel(dp_sub->link_config.lane_count,
+	       dp_sub->base_addr + DP_LANE_COUNT_SET);
+
+	/* Preserve the current RX device settings. */
+	status = aux_read(dev, DP_DPCD_LANE_COUNT_SET, 0x1, &regval);
+	if (status)
+		return status;
+
+	regval &= ~DP_DPCD_LANE_COUNT_SET_MASK;
+	regval |= dp_sub->link_config.lane_count;
+
+	/* Write the new lane count to the RX device. */
+	return aux_write(dev, DP_DPCD_LANE_COUNT_SET, 0x1, &regval);
+}
+
+/**
+ * set_clk_speed() - Set DP phy clock speed
+ * @dev:   The DP device
+ * @speed: The clock frquency to set (one of PHY_CLOCK_SELECT_*)
+ *
+ * Set the clock frequency for the DisplayPort PHY corresponding to a desired
+ * data rate.
+ *
+ * Return: 0 if setting the DP phy clock speed was successful, -ve on error
+ */
+static int set_clk_speed(struct udevice *dev, u32 speed)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 regval;
+
+	/* Disable the DisplayPort TX core first. */
+	regval = readl(dp_sub->base_addr + DP_ENABLE);
+	writel(0, dp_sub->base_addr + DP_ENABLE);
+
+	/* Change speed of the feedback clock. */
+	writel(speed, dp_sub->base_addr + DP_PHY_CLOCK_SELECT);
+
+	/* Re-enable the DisplayPort TX core if it was previously enabled. */
+	if (regval)
+		writel(regval, dp_sub->base_addr + DP_ENABLE);
+
+	/* Wait until the PHY is ready. */
+	return wait_phy_ready(dev);
+}
+
+/**
+ * set_link_rate() - Set the link rate
+ * @dev:       The DP device
+ * @link_rate: The link rate to set (one of LINK_BW_SET_*)
+ *
+ * Set the data rate to be used by the main link for both the DisplayPort TX
+ * core and the RX device.
+ *
+ * Return: 0 if setting the link rate was successful, -ve on error
+ */
+static int set_link_rate(struct udevice *dev, u8 link_rate)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 status;
+
+	/* Write a corresponding clock frequency to the DisplayPort TX core. */
+	switch (link_rate) {
+	case DP_LINK_BW_SET_162GBPS:
+		status = set_clk_speed(dev, DP_PHY_CLOCK_SELECT_162GBPS);
+		break;
+	case DP_LINK_BW_SET_270GBPS:
+		status = set_clk_speed(dev, DP_PHY_CLOCK_SELECT_270GBPS);
+		break;
+	case DP_LINK_BW_SET_540GBPS:
+		status = set_clk_speed(dev, DP_PHY_CLOCK_SELECT_540GBPS);
+		break;
+	default:
+		status = -EINVAL;
+		break;
+	}
+	if (status)
+		return status;
+
+	dp_sub->link_config.link_rate = link_rate;
+	/* Write new link rate to the DisplayPort TX core. */
+	writel(dp_sub->link_config.link_rate,
+	       dp_sub->base_addr +
+	       DP_LINK_BW_SET);
+
+	/* Write new link rate to the RX device. */
+	return aux_write(dev, DP_DPCD_LINK_BW_SET, 0x1,
+			 &dp_sub->link_config.link_rate);
+}
+
+static int set_downspread(struct udevice *dev, u8 enable)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 status;
+	u8 regval;
+
+	dp_sub->link_config.support_downspread_control = enable;
+	/* Write downspread enable to the DisplayPort TX core. */
+	writel(dp_sub->link_config.support_downspread_control,
+	       dp_sub->base_addr + DP_DOWNSPREAD_CTRL);
+
+	/* Preserve the current RX device settings. */
+	status = aux_read(dev, DP_DPCD_DOWNSPREAD_CTRL, 0x1, &regval);
+	if (status)
+		return status;
+
+	if (dp_sub->link_config.support_downspread_control)
+		regval |= DP_DPCD_SPREAD_AMP_MASK;
+	else
+		regval &= ~DP_DPCD_SPREAD_AMP_MASK;
+
+	/* Write downspread enable to the RX device. */
+	return aux_write(dev, DP_DPCD_DOWNSPREAD_CTRL, 0x1, &regval);
+}
+
+static void set_serdes_vswing_preemp(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u8  index;
+	u8  vs_level_rx = dp_sub->link_config.vs_level;
+	u8  pe_level_rx = dp_sub->link_config.pe_level;
+
+	for (index = 0; index < dp_sub->link_config.lane_count; index++) {
+		/* Write new voltage swing levels to the TX registers. */
+		writel(vs[pe_level_rx][vs_level_rx], (ulong)SERDES_BASEADDR +
+			SERDES_L0_TX_MARGININGF + index * SERDES_LANE_OFFSET);
+		/* Write new pre-emphasis levels to the TX registers. */
+		writel(pe[pe_level_rx][vs_level_rx], (ulong)SERDES_BASEADDR +
+			SERDES_L0_TX_DEEMPHASIS + index * SERDES_LANE_OFFSET);
+	}
+}
+
+/**
+ * set_vswing_preemp() - Build AUX data to set voltage swing and pre-emphasis
+ * @dev:      The DP device
+ * @aux_data: Buffer to receive the built AUX data
+ *
+ * Build AUX data to set current voltage swing and pre-emphasis level settings;
+ * the necessary data is taken from the link_config structure.
+ */
+static void set_vswing_preemp(struct udevice *dev, u8 *aux_data)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u8 data = 0;
+	u8 vs_level_rx = dp_sub->link_config.vs_level;
+	u8 pe_level_rx = dp_sub->link_config.pe_level;
+
+	if (vs_level_rx >= DP_MAXIMUM_VS_LEVEL)
+		data |= DP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK;
+
+	/* The maximum pre-emphasis level has been reached. */
+	if (pe_level_rx >= DP_MAXIMUM_PE_LEVEL)
+		data |= DP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK;
+
+	/* Set up the data buffer for writing to the RX device. */
+	data |= (pe_level_rx << DP_DPCD_TRAINING_LANEX_SET_PE_SHIFT) |
+		 vs_level_rx;
+	memset(aux_data, data, 4);
+
+	set_serdes_vswing_preemp(dev);
+}
+
+static int set_training_pattern(struct udevice *dev, u32 pattern)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u8 aux_data[5];
+
+	writel(pattern, dp_sub->base_addr + TRAINING_PATTERN_SET);
+
+	aux_data[0] = pattern;
+	switch (pattern) {
+	case TRAINING_PATTERN_SET_OFF:
+		writel(0, dp_sub->base_addr + SCRAMBLING_DISABLE);
+		dp_sub->link_config.scrambler_en = 1;
+		break;
+	case TRAINING_PATTERN_SET_TP1:
+	case TRAINING_PATTERN_SET_TP2:
+	case TRAINING_PATTERN_SET_TP3:
+		aux_data[0] |= DP_DPCD_TP_SET_SCRAMB_DIS_MASK;
+		writel(1, dp_sub->base_addr + SCRAMBLING_DISABLE);
+		dp_sub->link_config.scrambler_en = 0;
+		break;
+	default:
+		break;
+	}
+	/*
+	 * Make the adjustments to both the DisplayPort TX core and the RX
+	 * device.
+	 */
+	set_vswing_preemp(dev, &aux_data[1]);
+	/*
+	 * Write the voltage swing and pre-emphasis levels for each lane to the
+	 * RX device.
+	 */
+	if (pattern == TRAINING_PATTERN_SET_OFF)
+		return aux_write(dev, DP_DPCD_TP_SET, 1, aux_data);
+	else
+		return aux_write(dev, DP_DPCD_TP_SET, 5, aux_data);
+}
+
+static int get_lane_status_adj_reqs(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 status;
+	u8 aux_data[8];
+
+	status = aux_read(dev, DP_DPCD_SINK_COUNT, 8, aux_data);
+	if (status)
+		return status;
+
+	/* Save XDPPSU_DPCD_SINK_COUNT contents. */
+	dp_sub->sink_count =
+		((aux_data[0] & DP_DPCD_SINK_COUNT_HIGH_MASK) >>
+		DP_DPCD_SINK_COUNT_HIGH_LOW_SHIFT) |
+		(aux_data[0] & DP_DPCD_SINK_COUNT_LOW_MASK);
+	memcpy(dp_sub->lane_status_ajd_reqs, &aux_data[2], 6);
+	return 0;
+}
+
+/**
+ * check_clock_recovery() - Check clock recovery success
+ * @dev:        The LogiCore DP TX device in question
+ * @lane_count: The number of lanes for which to check clock recovery success
+ *
+ * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
+ * that the clock recovery sequence during link training was successful - the
+ * RX device's link clock and data recovery unit has realized and maintained
+ * the frequency lock for all lanes currently in use.
+ *
+ * Return: 0 if clock recovery was successful on all lanes in question, -ve if
+ *         not
+ */
+static int check_clock_recovery(struct udevice *dev, u8 lane_count)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u8 *lane_status = dp_sub->lane_status_ajd_reqs;
+
+	switch (lane_count) {
+	case DP_LANE_COUNT_SET_2:
+		if (!(lane_status[0] & DP_DPCD_STATUS_LANE_1_CR_DONE_MASK))
+			return -EINVAL;
+	case DP_LANE_COUNT_SET_1:
+		if (!(lane_status[0] & DP_DPCD_STATUS_LANE_0_CR_DONE_MASK))
+			return -EINVAL;
+	default:
+		/* All (LaneCount) lanes have achieved clock recovery. */
+		break;
+	}
+	return 0;
+}
+
+/**
+ * adj_vswing_preemp() - Adjust voltage swing and pre-emphasis
+ * @dev: The DP device
+ *
+ * Set new voltage swing and pre-emphasis levels using the
+ * adjustment requests obtained from the RX device.
+ *
+ * Return: 0 if voltage swing and pre-emphasis could be adjusted successfully,
+ *         -ve on error
+ */
+static int adj_vswing_preemp(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u8 index, vs_level_adj_req[4], pe_level_adj_req[4];
+	u8 aux_data[4];
+	u8 *adj_reqs = &dp_sub->lane_status_ajd_reqs[4];
+
+	/*
+	 * Analyze the adjustment requests for changes in voltage swing and
+	 * pre-emphasis levels.
+	 */
+	vs_level_adj_req[0] = adj_reqs[0] & DP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
+	vs_level_adj_req[1] = (adj_reqs[0] & DP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
+			      DP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
+	pe_level_adj_req[0] = (adj_reqs[0] & DP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
+			      DP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
+	pe_level_adj_req[1] = (adj_reqs[0] & DP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
+			      DP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
+
+	/*
+	 * Change the drive settings to match the adjustment requests. Use the
+	 * greatest level requested.
+	 */
+	dp_sub->link_config.vs_level = 0;
+	dp_sub->link_config.pe_level = 0;
+	for (index = 0; index < dp_sub->link_config.lane_count; index++) {
+		if (vs_level_adj_req[index] > dp_sub->link_config.vs_level)
+			dp_sub->link_config.vs_level = vs_level_adj_req[index];
+
+		if (pe_level_adj_req[index] > dp_sub->link_config.pe_level)
+			dp_sub->link_config.pe_level = pe_level_adj_req[index];
+	}
+
+	if (dp_sub->link_config.pe_level > DP_MAXIMUM_PE_LEVEL)
+		dp_sub->link_config.pe_level = DP_MAXIMUM_PE_LEVEL;
+
+	if (dp_sub->link_config.vs_level > DP_MAXIMUM_VS_LEVEL)
+		dp_sub->link_config.vs_level = DP_MAXIMUM_VS_LEVEL;
+
+	if (dp_sub->link_config.pe_level >
+				(4 - dp_sub->link_config.vs_level)) {
+		dp_sub->link_config.pe_level =
+				4 - dp_sub->link_config.vs_level;
+	}
+	/*
+	 * Make the adjustments to both the DisplayPort TX core and the RX
+	 * device.
+	 */
+	set_vswing_preemp(dev, aux_data);
+	/*
+	 * Write the voltage swing and pre-emphasis levels for each lane to the
+	 * RX device.
+	 */
+	return aux_write(dev, DP_DPCD_TRAINING_LANE0_SET, 2, aux_data);
+}
+
+/**
+ * get_training_delay() - Get training delay
+ * @dev:            The DP device
+ * @training_state: The training state for which the required training delay
+ *                  should be queried
+ *
+ * Determine what the RX device's required training delay is for
+ * link training.
+ *
+ * Return: The training delay in us
+ */
+static u32 get_training_delay(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u8 *dpcd = dp_sub->dpcd_rx_caps;
+
+	if (dpcd[DP_DPCD_TRAIN_AUX_RD_INTERVAL])
+		return 400 * dpcd[DP_DPCD_TRAIN_AUX_RD_INTERVAL] * 10;
+
+	return 400;
+}
+
+/**
+ * training_state_clock_recovery() - Run clock recovery part of link training
+ * @dev: The DP device
+ *
+ * Run the clock recovery sequence as part of link training. The
+ * sequence is as follows:
+ *
+ *      0) Start signaling at the minimum voltage swing, pre-emphasis, and
+ *         post- cursor levels.
+ *      1) Transmit training pattern 1 over the main link with symbol
+ *         scrambling disabled.
+ *      2) The clock recovery loop. If clock recovery is unsuccessful after
+ *         MaxIterations loop iterations, return.
+ *      2a) Wait for at least the period of time specified in the RX device's
+ *          DisplayPort Configuration data (DPCD) register,
+ *          TRAINING_AUX_RD_INTERVAL.
+ *      2b) Check if all lanes have achieved clock recovery lock. If so,
+ *          return.
+ *      2c) Check if the same voltage swing level has been used 5 consecutive
+ *          times or if the maximum level has been reached. If so, return.
+ *      2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
+ *          requested by the RX device.
+ *      2e) Loop back to 2a.
+ *
+ * For a more detailed description of the clock recovery sequence, see section
+ * 3.5.1.2.1 of the DisplayPort 1.2a specification document.
+ *
+ * Return: The next state machine state to advance to
+ */
+static enum link_training_states training_state_clock_recovery(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 status, delay_us;
+	u8 prev_vs_level = 0, same_vs_level_count  = 0;
+	struct link_config *link_config = &dp_sub->link_config;
+
+	delay_us = get_training_delay(dev);
+	/* Start CRLock. */
+	/* Start from minimal voltage swing and pre-emphasis levels. */
+	dp_sub->link_config.vs_level = 0;
+	dp_sub->link_config.pe_level = 0;
+	/* Transmit training pattern 1. */
+	status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP1);
+	if (status)
+		return TS_FAILURE;
+
+	while (1) {
+		/* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
+		udelay(delay_us);
+		/* Get lane and adjustment requests. */
+		status = get_lane_status_adj_reqs(dev);
+		if (status)
+			/* The AUX read failed. */
+			return TS_FAILURE;
+
+		/*
+		 * Check if all lanes have realized and maintained the frequency
+		 * lock and get adjustment requests.
+		 */
+		status = check_clock_recovery(dev, dp_sub->link_config.lane_count);
+		if (status == 0)
+			return TS_CHANNEL_EQUALIZATION;
+		/*
+		 * Check if the same voltage swing for each lane has been used 5
+		 * consecutive times.
+		 */
+		if (prev_vs_level == link_config->vs_level) {
+			same_vs_level_count++;
+		} else {
+			same_vs_level_count = 0;
+			prev_vs_level = link_config->vs_level;
+		}
+		if (same_vs_level_count >= 5)
+			break;
+
+		/* Only try maximum voltage swing once. */
+		if (link_config->vs_level == DP_MAXIMUM_VS_LEVEL)
+			break;
+
+		/* Adjust the drive settings as requested by the RX device. */
+		status = adj_vswing_preemp(dev);
+		if (status)
+			/* The AUX write failed. */
+			return TS_FAILURE;
+	}
+	return TS_ADJUST_LINK_RATE;
+}
+
+/**
+ * check_channel_equalization() - Check channel equalization success
+ * @dev:        The DP device
+ * @lane_count: The number of lanes for which to check channel equalization
+ *              success
+ *
+ * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
+ * that the channel equalization sequence during link training was successful -
+ * the RX device has achieved channel equalization, symbol lock, and interlane
+ * alignment for all lanes currently in use.
+ *
+ * Return: 0 if channel equalization was successful on all lanes in question,
+ *         -ve if not
+ */
+static int check_channel_equalization(struct udevice *dev, u8 lane_count)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u8 *lane_status = dp_sub->lane_status_ajd_reqs;
+
+	/* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */
+	switch (lane_count) {
+	case DP_LANE_COUNT_SET_2:
+		if (!(lane_status[0] & DP_DPCD_STATUS_LANE_1_CE_DONE_MASK))
+			return -EINVAL;
+	case DP_LANE_COUNT_SET_1:
+		if (!(lane_status[0] & DP_DPCD_STATUS_LANE_0_CE_DONE_MASK))
+			return -EINVAL;
+	default:
+		/* All (LaneCount) lanes have achieved channel equalization. */
+		break;
+	}
+
+	/* Check that all LANEx_SYMBOL_LOCKED bits are set. */
+	switch (lane_count) {
+	case DP_LANE_COUNT_SET_2:
+		if (!(lane_status[0] & DP_DPCD_STATUS_LANE_1_SL_DONE_MASK))
+			return -EINVAL;
+	case DP_LANE_COUNT_SET_1:
+		if (!(lane_status[0] & DP_DPCD_STATUS_LANE_0_SL_DONE_MASK))
+			return -EINVAL;
+	default:
+		/* All (LaneCount) lanes have achieved symbol lock. */
+		break;
+	}
+
+	/* Check that interlane alignment is done. */
+	if (!(lane_status[2] & DP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK))
+		return -EINVAL;
+	return 0;
+}
+
+/**
+ * training_state_channel_equalization() - Run channel equalization part of
+ *                                         link training
+ * @dev: The DP device
+ *
+ * Run the channel equalization sequence as part of link
+ * training. The sequence is as follows:
+ *
+ *      0) Start signaling with the same drive settings used at the end of the
+ *         clock recovery sequence.
+ *      1) Transmit training pattern 2 (or 3) over the main link with symbol
+ *         scrambling disabled.
+ *      2) The channel equalization loop. If channel equalization is
+ *         unsuccessful after 5 loop iterations, return.
+ *      2a) Wait for at least the period of time specified in the RX device's
+ *          DisplayPort Configuration data (DPCD) register,
+ *          TRAINING_AUX_RD_INTERVAL.
+ *      2b) Check if all lanes have achieved channel equalization, symbol lock,
+ *          and interlane alignment. If so, return.
+ *      2c) Check if the same voltage swing level has been used 5 consecutive
+ *          times or if the maximum level has been reached. If so, return.
+ *      2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
+ *          requested by the RX device.
+ *      2e) Loop back to 2a.
+ *
+ * For a more detailed description of the channel equalization sequence, see
+ * section 3.5.1.2.2 of the DisplayPort 1.2a specification document.
+ *
+ * Return: The next state machine state to advance to
+ */
+static enum link_training_states training_state_channel_equalization(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 status, delay_us = 400, iteration_count = 0;
+
+	/* Write the current drive settings. */
+	/* Transmit training pattern 2/3. */
+	if (dp_sub->dpcd_rx_caps[DP_DPCD_MAX_LANE_COUNT] &
+						  DP_DPCD_TPS3_SUPPORT_MASK)
+		status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP3);
+	else
+		status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP2);
+
+	if (status)
+		return TS_FAILURE;
+
+	while (iteration_count < 5) {
+		/* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
+		udelay(delay_us);
+
+		/* Get lane and adjustment requests. */
+		status = get_lane_status_adj_reqs(dev);
+		if (status)
+			/* The AUX read failed. */
+			return TS_FAILURE;
+
+		/* Adjust the drive settings as requested by the RX device. */
+		status = adj_vswing_preemp(dev);
+		if (status)
+			/* The AUX write failed. */
+			return TS_FAILURE;
+
+		/* Check that all lanes still have their clocks locked. */
+		status = check_clock_recovery(dev, dp_sub->link_config.lane_count);
+		if (status)
+			break;
+		/*
+		 * Check that all lanes have accomplished channel
+		 * equalization, symbol lock, and interlane alignment.
+		 */
+		status = check_channel_equalization(dev, dp_sub->link_config.lane_count);
+		if (status == 0)
+			return TS_SUCCESS;
+		iteration_count++;
+	}
+
+	/*
+	 * Tried 5 times with no success. Try a reduced bitrate first, then
+	 * reduce the number of lanes.
+	 */
+	return TS_ADJUST_LINK_RATE;
+}
+
+static int check_lane_align(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u8 *lane_status = dp_sub->lane_status_ajd_reqs;
+
+	if (!(lane_status[2] & DP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK))
+		return -EINVAL;
+	return 0;
+}
+
+/**
+ * check_link_status() - Check status of link
+ * @dev:        The DP device
+ * @lane_count: The lane count to use for the check
+ *
+ * Check if the receiver's DisplayPort Configuration data (DPCD) indicates the
+ * receiver has achieved and maintained clock recovery, channel equalization,
+ * symbol lock, and interlane alignment for all lanes currently in use.
+ *
+ * Return: 0 if the link status is OK, -ve if a error occurred during checking
+ */
+static int check_link_status(struct udevice *dev, u8 lane_count)
+{
+	u32 status;
+
+	status = get_lane_status_adj_reqs(dev);
+	if (status)
+		/* The AUX read failed. */
+		return status;
+
+	/* Check if the link needs training. */
+	if ((check_clock_recovery(dev, lane_count) == 0) &&
+	    (check_channel_equalization(dev, lane_count) == 0) &&
+	    (check_lane_align(dev) == 0)) {
+		return 0;
+	}
+	return -EINVAL;
+}
+
+/**
+ * run_training() - Run link training
+ * @dev: The DP device
+ *
+ * Run the link training process. It is implemented as a state machine, with
+ * each state returning the next state. First, the clock recovery sequence will
+ * be run; if successful, the channel equalization sequence will run. If either
+ * the clock recovery or channel equalization sequence failed, the link rate or
+ * the number of lanes used will be reduced and training will be re-attempted.
+ * If training fails at the minimal data rate, 1.62 Gbps with a single lane,
+ * training will no longer re-attempt and fail.
+ *
+ * There are undocumented timeout constraints in the link training process. In
+ * DP v1.2a spec, Chapter 3.5.1.2.2 a 10ms limit for the complete training
+ * process is mentioned. Which individual timeouts are derived and implemented
+ * by sink manufacturers is unknown. So each step should be as short as
+ * possible and link training should start as soon as possible after HPD.
+ *
+ * Return: 0 if the training sequence ran successfully, -ve if a error occurred
+ *         or the training failed
+ */
+static int run_training(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 status;
+	enum link_training_states training_state = TS_CLOCK_RECOVERY;
+
+	while (1) {
+		switch (training_state) {
+		case TS_CLOCK_RECOVERY:
+				training_state = training_state_clock_recovery(dev);
+			break;
+		case TS_CHANNEL_EQUALIZATION:
+			training_state = training_state_channel_equalization(dev);
+			break;
+		default:
+			break;
+		}
+
+		if (training_state == TS_SUCCESS)
+			break;
+		else if (training_state == TS_FAILURE)
+			return -EINVAL;
+
+		if (training_state == TS_ADJUST_LANE_COUNT ||
+		    training_state == TS_ADJUST_LINK_RATE) {
+			status = set_training_pattern(dev, TRAINING_PATTERN_SET_OFF);
+			if (status)
+				return -EINVAL;
+		}
+	}
+
+	/* Final status check. */
+	return check_link_status(dev, dp_sub->link_config.lane_count);
+}
+
+void reset_dp_phy(struct udevice *dev, u32 reset)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 phyval, regval;
+
+	writel(0, dp_sub->base_addr + DP_ENABLE);
+	phyval = readl(dp_sub->base_addr + DP_PHY_CONFIG);
+	regval = phyval | reset;
+	writel(regval, dp_sub->base_addr + DP_PHY_CONFIG);
+	/* Remove the reset. */
+	writel(phyval, dp_sub->base_addr + DP_PHY_CONFIG);
+	/* Wait for the PHY to be ready. */
+	wait_phy_ready(dev);
+
+	writel(1, dp_sub->base_addr + DP_ENABLE);
+}
+
+/**
+ * establish_link() - Establish a link
+ * @dev: The DP device
+ *
+ * Check if the link needs training and run the training sequence if training
+ * is required.
+ *
+ * Return: 0 if the link was established successfully, -ve on error
+ */
+static int establish_link(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 status, re_enable_main_link;
+
+	reset_dp_phy(dev, DP_PHY_CONFIG_TX_PHY_8B10BEN_MASK |
+			  DP_PHY_CONFIG_PHY_RESET_MASK);
+
+	re_enable_main_link = readl(dp_sub->base_addr + DP_ENABLE_MAIN_STREAM);
+	if (re_enable_main_link)
+		enable_main_link(dev, 0);
+
+	status = run_training(dev);
+	if (status)
+		return status;
+
+	status = set_training_pattern(dev, TRAINING_PATTERN_SET_OFF);
+	if (status)
+		return status;
+
+	if (re_enable_main_link)
+		enable_main_link(dev, 1);
+
+	return check_link_status(dev, dp_sub->link_config.lane_count);
+}
+
+static int dp_hpd_train(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	struct link_config *link_config = &dp_sub->link_config;
+	u32 status;
+
+	status = get_rx_capabilities(dev);
+	if (status) {
+		debug("! Error getting RX caps.\n");
+		return status;
+	}
+
+	status = set_enhanced_frame_mode(dev, link_config->support_enhanced_framing_mode ? 1 : 0);
+	if (status) {
+		debug("! EFM set failed.\n");
+		return status;
+	}
+
+	status = set_lane_count(dev, (dp_sub->use_max_lane_count) ?
+				link_config->max_lane_count : dp_sub->lane_count);
+	if (status) {
+		debug("! Lane count set failed.\n");
+		return status;
+	}
+
+	status = set_link_rate(dev, (dp_sub->use_max_link_rate) ?
+			       link_config->max_link_rate : dp_sub->link_rate);
+	if (status) {
+		debug("! Link rate set failed.\n");
+		return status;
+	}
+
+	status = set_downspread(dev, link_config->support_downspread_control);
+	if (status) {
+		debug("! Setting downspread failed.\n");
+		return status;
+	}
+
+	debug("Lane count =%d\n", dp_sub->link_config.lane_count);
+	debug("Link rate =%d\n",  dp_sub->link_config.link_rate);
+
+	debug("Starting Training...\n");
+	status = establish_link(dev);
+	if (status == 0)
+		debug("! Training succeeded.\n");
+	else
+		debug("! Training failed.\n");
+
+	return status;
+}
+
+static void display_gfx_frame_buffer(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	if (!dp_sub->dp_dma->gfx.channel.cur)
+		dp_sub->dp_dma->gfx.trigger_status = DPDMA_TRIGGER_EN;
+}
+
+static void set_color_encode(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	struct main_stream_attributes *msa_config = &dp_sub->msa_config;
+
+	msa_config->y_cb_cr_colorimetry = 0;
+	msa_config->dynamic_range       = 0;
+	msa_config->component_format    = 0;
+	msa_config->misc0               = 0;
+	msa_config->misc1               = 0;
+	msa_config->component_format    = DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_RGB;
+}
+
+static void config_msa_recalculate(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	u32 video_bw, link_bw, words_per_line;
+	u8 bits_per_pixel;
+	struct main_stream_attributes *msa_config;
+	struct link_config *link_config;
+
+	msa_config = &dp_sub->msa_config;
+	link_config = &dp_sub->link_config;
+
+	msa_config->user_pixel_width = 1;
+
+	/* Compute the rest of the MSA values. */
+	msa_config->n_vid = 27 * 1000 * link_config->link_rate;
+	msa_config->h_start = msa_config->vid_timing_mode.video_timing.h_sync_width +
+			      msa_config->vid_timing_mode.video_timing.h_back_porch;
+	msa_config->v_start = msa_config->vid_timing_mode.video_timing.f0_pv_sync_width +
+			      msa_config->vid_timing_mode.video_timing.f0_pv_back_porch;
+
+	/* Miscellaneous attributes. */
+	if (msa_config->bits_per_color == 6)
+		msa_config->misc0 = DP_MAIN_STREAM_MISC0_BDC_6BPC;
+	else if (msa_config->bits_per_color == 8)
+		msa_config->misc0 = DP_MAIN_STREAM_MISC0_BDC_8BPC;
+	else if (msa_config->bits_per_color == 10)
+		msa_config->misc0 = DP_MAIN_STREAM_MISC0_BDC_10BPC;
+	else if (msa_config->bits_per_color == 12)
+		msa_config->misc0 = DP_MAIN_STREAM_MISC0_BDC_12BPC;
+	else if (msa_config->bits_per_color == 16)
+		msa_config->misc0 = DP_MAIN_STREAM_MISC0_BDC_16BPC;
+
+	msa_config->misc0 <<= DP_MAIN_STREAM_MISC0_BDC_SHIFT;
+
+	/* Need to set this. */
+	msa_config->misc0 |= msa_config->component_format <<
+			     DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT;
+
+	msa_config->misc0 |= msa_config->dynamic_range <<
+			     DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE_SHIFT;
+
+	msa_config->misc0 |= msa_config->y_cb_cr_colorimetry <<
+			     DP_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_SHIFT;
+
+	msa_config->misc0 |= msa_config->synchronous_clock_mode;
+	/*
+	 * Determine the number of bits per pixel for the specified color
+	 * component format.
+	 */
+	if (msa_config->misc1 == DP_MAIN_STREAM_MISC1_Y_ONLY_EN_MASK)
+		bits_per_pixel = msa_config->bits_per_color;
+	else if (msa_config->component_format ==
+			DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_YCBCR422)
+		/* YCbCr422 color component format. */
+		bits_per_pixel = msa_config->bits_per_color * 2;
+	else
+		/* RGB or YCbCr 4:4:4 color component format. */
+		bits_per_pixel = msa_config->bits_per_color * 3;
+
+	/* Calculate the data per lane. */
+	words_per_line = msa_config->vid_timing_mode.video_timing.h_active * bits_per_pixel;
+	if (words_per_line % 16)
+		words_per_line += 16;
+
+	words_per_line /= 16;
+	msa_config->data_per_lane = words_per_line - link_config->lane_count;
+	if (words_per_line % link_config->lane_count)
+		msa_config->data_per_lane += (words_per_line % link_config->lane_count);
+
+	/* Allocate a fixed size for single-stream transport (SST) operation. */
+	msa_config->transfer_unit_size = 64;
+
+	/*
+	 * Calculate the average number of bytes per transfer unit.
+	 * Note: Both the integer and the fractional part is stored in
+	 * AvgBytesPerTU.
+	 */
+	video_bw = ((msa_config->pixel_clock_hz / 1000) * bits_per_pixel) / 8;
+	link_bw = (link_config->lane_count * link_config->link_rate * 27);
+	msa_config->avg_bytes_per_tu = ((10 *
+					(video_bw * msa_config->transfer_unit_size)
+					/ link_bw) + 5) / 10;
+	/*
+	 * The number of initial wait cycles at the start of a new line by the
+	 * framing logic. This allows enough data to be buffered in the input
+	 * FIFO before video is sent.
+	 */
+	if ((msa_config->avg_bytes_per_tu / 1000) <= 4)
+		msa_config->init_wait = 64;
+	else
+		msa_config->init_wait = msa_config->transfer_unit_size -
+					(msa_config->avg_bytes_per_tu / 1000);
+}
+
+static void set_msa_bpc(struct udevice *dev, u8 bits_per_color)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	dp_sub->msa_config.bits_per_color = bits_per_color;
+	/* Calculate the rest of the MSA values. */
+	config_msa_recalculate(dev);
+}
+
+const struct video_timing_mode *get_video_mode_data(enum video_mode vm_id)
+{
+	if (vm_id < VIDC_VM_NUM_SUPPORTED)
+		return &vidc_video_timing_modes[vm_id];
+
+	return NULL;
+}
+
+static u64 get_pixelclk_by_vmid(enum video_mode vm_id)
+{
+	const struct video_timing_mode *vm;
+	u64 clk_hz;
+
+	vm = get_video_mode_data(vm_id);
+	/* For progressive mode, use only frame 0 vertical total. */
+	clk_hz = vm->video_timing.f0_pv_total;
+	/* Multiply the number of pixels by the frame rate. */
+	clk_hz *= vm->frame_rate;
+
+	/*
+	 * Multiply the vertical total by the horizontal total for number of
+	 * pixels.
+	 */
+	clk_hz *= vm->video_timing.h_total;
+
+	return clk_hz;
+}
+
+/**
+ * config_msa_video_mode() - Enable video output
+ * @dev: The DP device
+ * @msa: The MSA values to set for the device
+ *
+ * Return: 0 if the video was enabled successfully, -ve on error
+ */
+static void config_msa_video_mode(struct udevice *dev, enum video_mode videomode)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	struct main_stream_attributes *msa_config;
+
+	msa_config = &dp_sub->msa_config;
+
+	/* Configure the MSA values from the display monitor DMT table. */
+	msa_config->vid_timing_mode.vid_mode = vidc_video_timing_modes[videomode].vid_mode;
+	msa_config->vid_timing_mode.frame_rate = vidc_video_timing_modes[videomode].frame_rate;
+	msa_config->vid_timing_mode.video_timing.h_active =
+				vidc_video_timing_modes[videomode].video_timing.h_active;
+	msa_config->vid_timing_mode.video_timing.h_front_porch =
+				vidc_video_timing_modes[videomode].video_timing.h_front_porch;
+	msa_config->vid_timing_mode.video_timing.h_sync_width =
+				vidc_video_timing_modes[videomode].video_timing.h_sync_width;
+	msa_config->vid_timing_mode.video_timing.h_back_porch =
+				vidc_video_timing_modes[videomode].video_timing.h_back_porch;
+	msa_config->vid_timing_mode.video_timing.h_total =
+				vidc_video_timing_modes[videomode].video_timing.h_total;
+	msa_config->vid_timing_mode.video_timing.h_sync_polarity =
+			vidc_video_timing_modes[videomode].video_timing.h_sync_polarity;
+	msa_config->vid_timing_mode.video_timing.v_active =
+			vidc_video_timing_modes[videomode].video_timing.v_active;
+	msa_config->vid_timing_mode.video_timing.f0_pv_front_porch =
+			vidc_video_timing_modes[videomode].video_timing.f0_pv_front_porch;
+	msa_config->vid_timing_mode.video_timing.f0_pv_sync_width =
+			vidc_video_timing_modes[videomode].video_timing.f0_pv_sync_width;
+	msa_config->vid_timing_mode.video_timing.f0_pv_back_porch =
+			vidc_video_timing_modes[videomode].video_timing.f0_pv_back_porch;
+	msa_config->vid_timing_mode.video_timing.f0_pv_total =
+			vidc_video_timing_modes[videomode].video_timing.f0_pv_total;
+	msa_config->vid_timing_mode.video_timing.f1_v_front_porch =
+			vidc_video_timing_modes[videomode].video_timing.f1_v_front_porch;
+	msa_config->vid_timing_mode.video_timing.f1_v_sync_width =
+			vidc_video_timing_modes[videomode].video_timing.f1_v_sync_width;
+	msa_config->vid_timing_mode.video_timing.f1_v_back_porch =
+			vidc_video_timing_modes[videomode].video_timing.f1_v_back_porch;
+	msa_config->vid_timing_mode.video_timing.f1_v_total =
+			vidc_video_timing_modes[videomode].video_timing.f1_v_total;
+	msa_config->vid_timing_mode.video_timing.v_sync_polarity =
+			vidc_video_timing_modes[videomode].video_timing.v_sync_polarity;
+	msa_config->pixel_clock_hz = get_pixelclk_by_vmid(msa_config->vid_timing_mode.vid_mode);
+
+	/* Calculate the rest of the MSA values. */
+	config_msa_recalculate(dev);
+}
+
+static void set_pixel_clock(u64 freq_hz)
+{
+	u64 ext_divider, vco, vco_int_frac;
+	u32 pll_assigned, frac_int_fb_div, fraction, regpll = 0;
+	u8 pll;
+
+	pll_assigned = readl(CLK_FPD_BASEADDR + VIDEO_REF_CTRL) & VIDEO_REF_CTRL_SRCSEL_MASK;
+	if (pll_assigned)
+		pll = VPLL;
+
+	ext_divider = PLL_OUT_FREQ / freq_hz;
+	vco = freq_hz * ext_divider * 2;
+	vco_int_frac = (vco * INPUT_FREQ_PRECISION * SHIFT_DECIMAL) /
+			AVBUF_INPUT_REF_CLK;
+	frac_int_fb_div = vco_int_frac >> PRECISION;
+	fraction = vco_int_frac &  AVBUF_DECIMAL;
+
+	regpll |= ENABLE_BIT << PLL_CTRL_BYPASS_SHIFT;
+	regpll |= frac_int_fb_div << PLL_CTRL_FBDIV_SHIFT;
+	regpll |= (1 << PLL_CTRL_DIV2_SHIFT);
+	regpll |= (PSS_REF_CLK << PLL_CTRL_PRE_SRC_SHIFT);
+	writel(regpll, CLK_FPD_BASEADDR + VPLL_CTRL);
+
+	regpll = 0;
+	regpll |= VPLL_CFG_CP << PLL_CFG_CP_SHIFT;
+	regpll |= VPLL_CFG_RES << PLL_CFG_RES_SHIFT;
+	regpll |= VPLL_CFG_LFHF << PLL_CFG_LFHF_SHIFT;
+	regpll |= VPLL_CFG_LOCK_DLY << PLL_CFG_LOCK_DLY_SHIFT;
+	regpll |= VPLL_CFG_LOCK_CNT << PLL_CFG_LOCK_CNT_SHIFT;
+	writel(regpll, CLK_FPD_BASEADDR + VPLL_CFG);
+
+	regpll = (1U << PLL_FRAC_CFG_ENABLED_SHIFT) |
+		 (fraction << PLL_FRAC_CFG_DATA_SHIFT);
+	writel(regpll, CLK_FPD_BASEADDR + VPLL_FRAC_CFG);
+
+	clrsetbits_le32(CLK_FPD_BASEADDR + VPLL_CTRL,
+			PLL_CTRL_RESET_MASK,
+			(ENABLE_BIT << PLL_CTRL_RESET_SHIFT));
+
+	/* Deassert reset to the PLL. */
+	clrsetbits_le32(CLK_FPD_BASEADDR + VPLL_CTRL,
+			PLL_CTRL_RESET_MASK,
+			(DISABLE_BIT << PLL_CTRL_RESET_SHIFT));
+
+	while (!(readl(CLK_FPD_BASEADDR + PLL_STATUS) &
+		(1 << PLL_STATUS_VPLL_LOCK)))
+		;
+
+	/* Deassert Bypass. */
+	clrsetbits_le32(CLK_FPD_BASEADDR + VPLL_CTRL,
+			PLL_CTRL_BYPASS_MASK,
+			(DISABLE_BIT << PLL_CTRL_BYPASS_SHIFT));
+	udelay(1);
+
+	clrsetbits_le32(CLK_FPD_BASEADDR + VIDEO_REF_CTRL,
+			VIDEO_REF_CTRL_CLKACT_MASK,
+			(DISABLE_BIT << VIDEO_REF_CTRL_CLKACT_SHIFT));
+
+	clrsetbits_le32(CLK_FPD_BASEADDR + VIDEO_REF_CTRL,
+			VIDEO_REF_CTRL_DIVISOR1_MASK,
+			(ENABLE_BIT << VIDEO_REF_CTRL_DIVISOR1_SHIFT));
+
+	clrsetbits_le32(CLK_FPD_BASEADDR + VIDEO_REF_CTRL,
+			VIDEO_REF_CTRL_DIVISOR0_MASK,
+			(ext_divider << VIDEO_REF_CTRL_DIVISOR0_SHIFT));
+
+	clrsetbits_le32(CLK_FPD_BASEADDR + VIDEO_REF_CTRL,
+			VIDEO_REF_CTRL_CLKACT_MASK,
+			(ENABLE_BIT << VIDEO_REF_CTRL_CLKACT_SHIFT));
+}
+
+/**
+ * set_msa_values() - Set MSA values
+ * @dev: The DP device
+ *
+ * Set the main stream attributes registers of the DisplayPort TX
+ * core with the values specified in the main stream attributes configuration
+ * structure.
+ */
+static void set_msa_values(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	struct main_stream_attributes *msa_config;
+
+	msa_config = &dp_sub->msa_config;
+
+	/*
+	 * Set the main stream attributes to the associated DisplayPort TX core
+	 * registers.
+	 */
+	writel(msa_config->vid_timing_mode.video_timing.h_total,
+	       dp_sub->base_addr + DP_MAIN_STREAM_HTOTAL);
+	writel(msa_config->vid_timing_mode.video_timing.f0_pv_total,
+	       dp_sub->base_addr + DP_MAIN_STREAM_VTOTAL);
+	writel(msa_config->vid_timing_mode.video_timing.h_sync_polarity |
+	       (msa_config->vid_timing_mode.video_timing.v_sync_polarity
+		<< DP_MAIN_STREAM_POLARITY_VSYNC_POL_SHIFT),
+		dp_sub->base_addr + DP_MAIN_STREAM_POLARITY);
+	writel(msa_config->vid_timing_mode.video_timing.h_sync_width,
+	       dp_sub->base_addr + DP_MAIN_STREAM_HSWIDTH);
+	writel(msa_config->vid_timing_mode.video_timing.f0_pv_sync_width,
+	       dp_sub->base_addr + DP_MAIN_STREAM_VSWIDTH);
+	writel(msa_config->vid_timing_mode.video_timing.h_active,
+	       dp_sub->base_addr + DP_MAIN_STREAM_HRES);
+	writel(msa_config->vid_timing_mode.video_timing.v_active,
+	       dp_sub->base_addr + DP_MAIN_STREAM_VRES);
+	writel(msa_config->h_start, dp_sub->base_addr + DP_MAIN_STREAM_HSTART);
+	writel(msa_config->v_start, dp_sub->base_addr + DP_MAIN_STREAM_VSTART);
+	writel(msa_config->misc0, dp_sub->base_addr + DP_MAIN_STREAM_MISC0);
+	writel(msa_config->misc1, dp_sub->base_addr + DP_MAIN_STREAM_MISC1);
+	writel(msa_config->pixel_clock_hz / 1000, dp_sub->base_addr + DP_M_VID);
+	writel(msa_config->n_vid, dp_sub->base_addr + DP_N_VID);
+	writel(msa_config->user_pixel_width, dp_sub->base_addr + DP_USER_PIXEL_WIDTH);
+	writel(msa_config->data_per_lane, dp_sub->base_addr + DP_USER_DATA_COUNT_PER_LANE);
+	/*
+	 * Set the transfer unit values to the associated DisplayPort TX core
+	 * registers.
+	 */
+	writel(msa_config->transfer_unit_size, dp_sub->base_addr + DP_TU_SIZE);
+	writel(msa_config->avg_bytes_per_tu / 1000,
+	       dp_sub->base_addr + DP_MIN_BYTES_PER_TU);
+	writel((msa_config->avg_bytes_per_tu % 1000) * 1000,
+	       dp_sub->base_addr + DP_FRAC_BYTES_PER_TU);
+	writel(msa_config->init_wait, dp_sub->base_addr + DP_INIT_WAIT);
+}
+
+static void setup_video_stream(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+	struct main_stream_attributes *msa_config = &dp_sub->msa_config;
+
+	set_color_encode(dev);
+	set_msa_bpc(dev, dp_sub->bpc);
+	config_msa_video_mode(dev, dp_sub->video_mode);
+
+	/* Set pixel clock. */
+	dp_sub->pix_clk = msa_config->pixel_clock_hz;
+	set_pixel_clock(dp_sub->pix_clk);
+
+	/* Reset the transmitter. */
+	writel(1, dp_sub->base_addr + DP_SOFT_RESET);
+	udelay(10);
+	writel(0, dp_sub->base_addr + DP_SOFT_RESET);
+
+	set_msa_values(dev);
+
+	/* Issuing a soft-reset (AV_BUF_SRST_REG). */
+	writel(3, dp_sub->base_addr + AVBUF_BUF_SRST_REG); // Assert reset.
+	udelay(10);
+	writel(0, dp_sub->base_addr + AVBUF_BUF_SRST_REG); // De-ssert reset.
+
+	enable_main_link(dev, 1);
+
+	debug("DONE!\n");
+}
+
+static int dp_tx_start_link_training(struct udevice *dev)
+{
+	u32 status;
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	enable_main_link(dev, 0);
+
+	if (!is_dp_connected(dev)) {
+		debug("! Disconnected.\n");
+		return -ENODEV;
+	}
+
+	status = dp_tx_wakeup(dev);
+	if (status) {
+		debug("! Wakeup failed.\n");
+		return -EIO;
+	}
+
+	do {
+		mdelay(100);
+		status = dp_hpd_train(dev);
+		if (status == -EINVAL) {
+			debug("Lost connection\n\r");
+			return -EIO;
+		} else if (status) {
+			continue;
+		}
+		display_gfx_frame_buffer(dev);
+		setup_video_stream(dev);
+		status = check_link_status(dev, dp_sub->link_config.lane_count);
+		if (status == -EINVAL)
+			return -EIO;
+	} while (status != 0);
+
+	return 0;
+}
+
+static void init_run_config(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	dp_sub->dp_dma               = &dp_dma;
+	dp_sub->video_mode           = VIDC_VM_1024x768_60_P;
+	dp_sub->bpc                  = VIDC_BPC_8;
+	dp_sub->color_encode         = DP_CENC_RGB;
+	dp_sub->use_max_cfg_caps     = 1;
+	dp_sub->lane_count           = LANE_COUNT_1;
+	dp_sub->link_rate            = LINK_RATE_540GBPS;
+	dp_sub->en_sync_clk_mode     = 0;
+	dp_sub->use_max_lane_count   = 1;
+	dp_sub->use_max_link_rate    = 1;
+}
+
+static int dpdma_setup(struct udevice *dev)
+{
+	int status;
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	writel(DPDMA_ISR_VSYNC_INT_MASK, dp_sub->dp_dma->base_addr + DPDMA_IEN);
+	status = wait_for_bit_le32((u32 *)dp_sub->dp_dma->base_addr + DPDMA_ISR,
+				   DPDMA_ISR_VSYNC_INT_MASK, false, 1000, false);
+	if (status) {
+		debug("%s: INTR TIMEDOUT\n", __func__);
+		return status;
+	}
+	debug("INTR dma_vsync_intr_handler called...\n");
+	dma_vsync_intr_handler(dev);
+
+	return 0;
+}
+
+static int zynqmp_dpsub_init(struct udevice *dev)
+{
+	int status;
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	/* Initialize the dpdma configuration */
+	status = init_dpdma_subsys(dev);
+	if (status)
+		return -EINVAL;
+
+	config_msa_sync_clk_mode(dev, dp_sub->en_sync_clk_mode);
+	set_video_clk_source(dev, AVBUF_PS_CLK, AVBUF_PS_CLK);
+
+	return 0;
+}
+
+static int dp_tx_run(struct udevice *dev)
+{
+	u32 interrupt_signal_state, interrupt_status, hpd_state, hpd_event;
+	u32 hpd_pulse_detected, hpd_duration, status;
+	int attempts = 0;
+	struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
+
+	/* Continuously poll for HPD events. */
+	while (attempts < 5) {
+		/* Read interrupt registers. */
+		interrupt_signal_state = readl(dp_sub->base_addr + DP_INTERRUPT_SIG_STATE);
+		interrupt_status = readl(dp_sub->base_addr + DP_INTR_STATUS);
+		/* Check for HPD events. */
+		hpd_state = interrupt_signal_state & DP_INTERRUPT_SIG_STATE_HPD_STATE_MASK;
+		hpd_event = interrupt_status & DP_INTR_HPD_EVENT_MASK;
+		hpd_pulse_detected = interrupt_status & DP_INTR_HPD_PULSE_DETECTED_MASK;
+		if (hpd_pulse_detected)
+			hpd_duration = readl(dp_sub->base_addr + DP_HPD_DURATION);
+		else
+			attempts++;
+
+		/* HPD event handling. */
+		if (hpd_state && hpd_event) {
+			debug("+===> HPD connection event detected.\n");
+			/* Initiate link training. */
+			status = dp_tx_start_link_training(dev);
+			if (status) {
+				debug("Link training failed\n");
+				return status;
+			}
+			return 0;
+		} else if (hpd_state && hpd_pulse_detected && (hpd_duration >= 250)) {
+			debug("===> HPD pulse detected.\n");
+			/* Re-train if needed. */
+			status = dp_tx_start_link_training(dev);
+			if (status) {
+				debug("HPD pulse detection failed\n");
+				return status;
+			}
+			return 0;
+		} else if (!hpd_state && hpd_event) {
+			debug("+===> HPD disconnection event detected.\n\n");
+			/* Disable main link. */
+			enable_main_link(dev, 0);
+			break;
+		}
+	}
+	return -EINVAL;
+}
+
+static int zynqmp_dpsub_probe(struct udevice *dev)
+{
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct zynqmp_dpsub_priv *priv = dev_get_priv(dev);
+	struct clk clk;
+	int ret;
+	int mode = RGBA8888;
+
+	ret = clk_get_by_name(dev, "dp_apb_clk", &clk);
+	if (ret < 0) {
+		dev_err(dev, "failed to get clock\n");
+		return ret;
+	}
+
+	priv->clock = clk_get_rate(&clk);
+	if (IS_ERR_VALUE(priv->clock)) {
+		dev_err(dev, "failed to get rate\n");
+		return priv->clock;
+	}
+
+	ret = clk_enable(&clk);
+	if (ret) {
+		dev_err(dev, "failed to enable clock\n");
+		return ret;
+	}
+
+	dev_dbg(dev, "Base addr 0x%x, clock %d\n", (u32)priv->base_addr,
+		priv->clock);
+
+	/* Initialize the DisplayPort TX core. */
+	ret = init_dp_tx(dev);
+	if (ret)
+		return -EINVAL;
+
+	/* Initialize the runtime configuration */
+	init_run_config(dev);
+	/* Set the format graphics frame for Video Pipeline */
+	ret = set_nonlive_gfx_format(dev, mode);
+	if (ret)
+		return ret;
+
+	uc_priv->bpix = ffs(priv->non_live_graphics->bpp) - 1;
+	dev_dbg(dev, "BPP in bits %d, bpix %d\n",
+		priv->non_live_graphics->bpp, uc_priv->bpix);
+
+	uc_priv->fb = (void *)gd->fb_base;
+	uc_priv->xsize = vidc_video_timing_modes[priv->video_mode].video_timing.h_active;
+	uc_priv->ysize = vidc_video_timing_modes[priv->video_mode].video_timing.v_active;
+	/* Calculated by core but need it for my own setup */
+	uc_priv->line_length = uc_priv->xsize * VNBYTES(uc_priv->bpix);
+	/* Will be calculated again in video_post_probe() but I need that value now */
+	uc_priv->fb_size = uc_priv->line_length * uc_priv->ysize;
+
+	switch (mode) {
+	case RGBA8888:
+		uc_priv->format = VIDEO_RGBA8888;
+		break;
+	default:
+		debug("Unsupported mode\n");
+		return -EINVAL;
+	}
+
+	video_set_flush_dcache(dev, true);
+	debug("Video: WIDTH[%d]xHEIGHT[%d]xBPP[%d/%d] -- line length %d\n", uc_priv->xsize,
+	      uc_priv->ysize, uc_priv->bpix, VNBYTES(uc_priv->bpix), uc_priv->line_length);
+
+	enable_gfx_buffers(dev, 1);
+	avbuf_video_select(dev, AVBUF_VIDSTREAM1_NONE, AVBUF_VIDSTREAM2_NONLIVE_GFX);
+	config_gfx_pipeline(dev);
+	config_output_video(dev);
+
+	ret = zynqmp_dpsub_init(dev);
+	if (ret)
+		return ret;
+
+	/* Populate the FrameBuffer structure with the frame attributes */
+	priv->frame_buffer.stride = uc_priv->line_length;
+	priv->frame_buffer.line_size = priv->frame_buffer.stride;
+	priv->frame_buffer.size = priv->frame_buffer.line_size * uc_priv->ysize;
+
+	ret = dp_tx_run(dev);
+	if (ret)
+		return ret;
+
+	return dpdma_setup(dev);
+}
+
+static int zynqmp_dpsub_bind(struct udevice *dev)
+{
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+
+	/* This is maximum size to allocate - it depends on BPP setting */
+	plat->size = WIDTH * HEIGHT * 4;
+	/* plat->align is not defined that's why 1MB alignment is used */
+
+	/*
+	 * plat->base can be used for allocating own location for FB
+	 * if not defined then it is allocated by u-boot itself
+	 */
+
+	return 0;
+}
+
+static int zynqmp_dpsub_of_to_plat(struct udevice *dev)
+{
+	struct zynqmp_dpsub_priv *priv = dev_get_priv(dev);
+	struct resource res;
+	int ret;
+
+	ret = dev_read_resource_byname(dev, "dp", &res);
+	if (ret)
+		return ret;
+
+	priv->base_addr = res.start;
+
+	return 0;
+}
+
+static const struct udevice_id zynqmp_dpsub_ids[] = {
+	{ .compatible = "xlnx,zynqmp-dpsub-1.7" },
+	{ }
+};
+
+U_BOOT_DRIVER(zynqmp_dpsub_video) = {
+	.name = "zynqmp_dpsub_video",
+	.id = UCLASS_VIDEO,
+	.of_match = zynqmp_dpsub_ids,
+	.plat_auto = sizeof(struct video_uc_plat),
+	.bind = zynqmp_dpsub_bind,
+	.probe = zynqmp_dpsub_probe,
+	.priv_auto = sizeof(struct zynqmp_dpsub_priv),
+	.of_to_plat = zynqmp_dpsub_of_to_plat,
+};
diff --git a/drivers/video/zynqmp/zynqmp_dpsub.h b/drivers/video/zynqmp/zynqmp_dpsub.h
new file mode 100644
index 0000000000..7d2737e31a
--- /dev/null
+++ b/drivers/video/zynqmp/zynqmp_dpsub.h
@@ -0,0 +1,680 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
+ *
+ */
+
+#ifndef _VIDEO_ZYNQMP_DPSUB_H
+#define _VIDEO_ZYNQMP_DPSUB_H
+
+enum video_mode {
+	VIDC_VM_640x480_60_P = 0,
+	VIDC_VM_1024x768_60_P = 1,
+};
+
+enum {
+	LANE_COUNT_1 = 1,
+	LANE_COUNT_2 = 2,
+};
+
+enum {
+	LINK_RATE_162GBPS = 0x06,
+	LINK_RATE_270GBPS = 0x0A,
+	LINK_RATE_540GBPS = 0x14,
+};
+
+enum video_color_depth {
+	VIDC_BPC_6 = 6,
+	VIDC_BPC_8 = 8,
+	VIDC_BPC_10 = 10,
+	VIDC_BPC_12 = 12,
+	VIDC_BPC_14 = 14,
+	VIDC_BPC_16 = 16,
+	VIDC_BPC_NUM_SUPPORTED = 6,
+	VIDC_BPC_UNKNOWN
+};
+
+enum video_color_encoding {
+	DP_CENC_RGB = 0,
+	DP_CENC_YONLY,
+};
+
+enum dp_dma_channel_type {
+	VIDEO_CHAN,
+	GRAPHICS_CHAN,
+};
+
+enum dp_dma_channel_state {
+	DPDMA_DISABLE,
+	DPDMA_ENABLE,
+	DPDMA_IDLE,
+	DPDMA_PAUSE
+};
+
+enum link_training_states {
+	TS_CLOCK_RECOVERY,
+	TS_CHANNEL_EQUALIZATION,
+	TS_ADJUST_LINK_RATE,
+	TS_ADJUST_LANE_COUNT,
+	TS_FAILURE,
+	TS_SUCCESS
+};
+
+enum video_frame_rate {
+	VIDC_FR_60HZ = 60,
+	VIDC_FR_NUM_SUPPORTED = 2,
+	VIDC_FR_UNKNOWN
+};
+
+enum av_buf_video_modes {
+	INTERLEAVED,
+	SEMIPLANAR
+};
+
+enum av_buf_video_format {
+	RGBA8888 = 1,
+};
+
+enum av_buf_video_stream {
+	AVBUF_VIDSTREAM1_LIVE,
+	AVBUF_VIDSTREAM1_NONLIVE,
+	AVBUF_VIDSTREAM1_TPG,
+	AVBUF_VIDSTREAM1_NONE,
+};
+
+enum av_buf_gfx_stream {
+	AVBUF_VIDSTREAM2_DISABLEGFX = 0x0,
+	AVBUF_VIDSTREAM2_NONLIVE_GFX = 0x4,
+	AVBUF_VIDSTREAM2_LIVE_GFX = 0x8,
+	AVBUF_VIDSTREAM2_NONE = 0xC0,
+};
+
+/**
+ * struct aux_transaction - Description of an AUX channel transaction
+ * @cmd_code:  Command code of the transaction
+ * @num_bytes: The number of bytes in the transaction's payload data
+ * @address:   The DPCD address of the transaction
+ * @data:      Payload data of the AUX channel transaction
+ */
+struct aux_transaction {
+	u16 cmd_code;
+	u8 num_bytes;
+	u32 address;
+	u8 *data;
+};
+
+/**
+ * struct link_config - Description of link configuration
+ * @lane_count:                    Currently selected lane count for this link
+ * @link_rate:                     Currently selected link rate for this link
+ * @scrambler_en:                  Flag to determine whether the scrambler is
+ *                                 enabled for this link
+ * @enhanced_framing_mode:         Flag to determine whether enhanced framing
+ *                                 mode is active for this link
+ * @max_lane_count:                Maximum lane count for this link
+ * @max_link_rate:                 Maximum link rate for this link
+ * @support_enhanced_framing_mode: Flag to indicate whether the link supports
+ *                                 enhanced framing mode
+ * @vs_level:                      Voltage swing for each lane
+ * @pe_level:                      Pre-emphasis/cursor level for each lane
+ * @pattern:                      The current pattern currently in use over the main link
+ */
+struct link_config {
+	u8 lane_count;
+	u8 link_rate;
+	u8 scrambler_en;
+	u8 enhanced_framing_mode;
+	u8 max_lane_count;
+	u8 max_link_rate;
+	u8 support_enhanced_framing_mode;
+	u8 support_downspread_control;
+	u8 vs_level;
+	u8 pe_level;
+	u8 pattern;
+};
+
+struct video_timing {
+	u16 h_active;
+	u16 h_front_porch;
+	u16 h_sync_width;
+	u16 h_back_porch;
+	u16 h_total;
+	bool h_sync_polarity;
+	u16 v_active;
+	u16 f0_pv_front_porch;
+	u16 f0_pv_sync_width;
+	u16 f0_pv_back_porch;
+	u16 f0_pv_total;
+	u16 f1_v_front_porch;
+	u16 f1_v_sync_width;
+	u16 f1_v_back_porch;
+	u16 f1_v_total;
+	bool v_sync_polarity;
+};
+
+struct video_timing_mode {
+	enum video_mode  vid_mode;
+	char name[21];
+	enum video_frame_rate   frame_rate;
+	struct video_timing     video_timing;
+};
+
+/*
+ * struct main_stream_attributes - Main Stream Attributes (MSA)
+ * @pixel_clock_hz:            The pixel clock of the stream (in Hz)
+ * @h_start:                   Horizontal blank start (in pixels)
+ * @v_start:                   Vertical blank start (in lines).
+ * @misc0:                    Miscellaneous stream attributes 0
+ * @misc1:                    Miscellaneous stream attributes 1
+ * @n_vid                     N value for the video stream
+ * @user_pixel_width:          The width of the user data input port.
+ * @data_per_plane:           Used to translate the number of pixels per
+ *                            line to the native internal 16-bit datapath.
+ * @avg_bytes_per_tu:         Average number of bytes per transfer unit,
+ *                            scaled up by a factor of 1000.
+ * @transfer_unit_size:               Size of the transfer unit in the
+ *                            framing logic.
+ * @init_wait:                Number of initial wait cycles at the start
+ *                            of a new line by the framing logic.
+ * @bits_per_color:           Number of bits per color component.
+ * @component_format:         The component format currently in
+ *                            use by the video stream.
+ * @dynamic_range:            The dynamic range currently in use
+ *                            by the video stream.
+ * @y_cb_cr_colorimetry:       The YCbCr colorimetry currently in
+ *                            use by the video stream.
+ * @synchronous_clock_mode:    Synchronous clock mode is currently
+ *                            in use by the video stream.
+ */
+struct main_stream_attributes {
+	struct video_timing_mode vid_timing_mode;
+	u32 pixel_clock_hz;
+	u32 h_start;
+	u32 v_start;
+	u32 misc0;
+	u32 misc1;
+	u32 n_vid;
+	u32 user_pixel_width;
+	u32 data_per_lane;
+	u32 avg_bytes_per_tu;
+	u32 transfer_unit_size;
+	u32 init_wait;
+	u32 bits_per_color;
+	u8 component_format;
+	u8 dynamic_range;
+	u8 y_cb_cr_colorimetry;
+	u8 synchronous_clock_mode;
+};
+
+struct av_buf_vid_attribute {
+	enum av_buf_video_format video_format;
+	u8 value;
+	enum av_buf_video_modes mode;
+	u32 sf[3];
+	u8 sampling_en;
+	u8 is_rgb;
+	u8 swap;
+	u8 bpp;
+};
+
+struct av_buf_mode {
+	enum av_buf_video_stream video_src;
+	enum av_buf_gfx_stream gfx_src;
+	u8 video_clk;
+};
+
+struct dp_dma_descriptor {
+	u32 control;
+	u32 dscr_id;
+	u32 xfer_size;
+	u32 line_size_stride;
+	u32 lsb_timestamp;
+	u32 msb_timestamp;
+	u32 addr_ext;
+	u32 next_desr;
+	u32 src_addr;
+	u32 addr_ext_23;
+	u32 addr_ext_45;
+	u32 src_addr2;
+	u32 src_addr3;
+	u32 src_addr4;
+	u32 src_addr5;
+	u32 crc;
+};
+
+struct dp_dma_channel {
+	struct dp_dma_descriptor *cur;
+};
+
+struct dp_dma_frame_buffer {
+	u64 address;
+	u32 size;
+	u32 stride;
+	u32 line_size;
+};
+
+struct dp_dma_gfx_channel {
+	struct dp_dma_channel channel;
+	u8 trigger_status;
+	u8 av_buf_en;
+	struct dp_dma_frame_buffer *frame_buffer;
+};
+
+struct dp_dma {
+	phys_addr_t base_addr;
+	struct dp_dma_gfx_channel gfx;
+};
+
+/**
+ * struct zynqmp_dpsub_priv - Private structure
+ * @dev: Device uclass for video_ops
+ */
+struct zynqmp_dpsub_priv {
+	phys_addr_t base_addr;
+	u32 clock;
+	struct av_buf_vid_attribute *non_live_graphics;
+	struct av_buf_mode av_mode;
+	struct dp_dma_frame_buffer frame_buffer;
+
+	struct link_config link_config;
+	struct main_stream_attributes msa_config;
+	struct dp_dma  *dp_dma;
+	enum video_mode   video_mode;
+	enum video_color_depth  bpc;
+	enum video_color_encoding color_encode;
+	u32 pix_clk;
+	u8 dpcd_rx_caps[16];
+	u8 lane_status_ajd_reqs[6];
+	u8 sink_count;
+	u8 use_max_lane_count;
+	u8 use_max_link_rate;
+	u8 lane_count;
+	u8 link_rate;
+	u8 use_max_cfg_caps;
+	u8 en_sync_clk_mode;
+};
+
+/**************************** Variable Definitions ****************************/
+#define TRAINING_PATTERN_SET						0x000C
+#define TRAINING_PATTERN_SET_OFF					0x0
+#define SCRAMBLING_DISABLE						0x0014
+#define TRAINING_PATTERN_SET_TP1					0x1
+#define TRAINING_PATTERN_SET_TP2					0x2
+#define TRAINING_PATTERN_SET_TP3					0x3
+
+#define AVBUF_BUF_4BIT_SF						0x11111
+#define AVBUF_BUF_5BIT_SF						0x10842
+#define AVBUF_BUF_6BIT_SF						0x10410
+#define AVBUF_BUF_8BIT_SF						0x10101
+#define AVBUF_BUF_10BIT_SF						0x10040
+#define AVBUF_BUF_12BIT_SF						0x10000
+#define AVBUF_BUF_6BPC							0x000
+#define AVBUF_BUF_8BPC							0x001
+#define AVBUF_BUF_10BPC							0x010
+#define AVBUF_BUF_12BPC							0x011
+#define AVBUF_CHBUF3							0x0000B01C
+#define AVBUF_CHBUF3_BURST_LEN_SHIFT					2
+#define AVBUF_CHBUF3_FLUSH_MASK						0x00000002
+#define AVBUF_CHBUF0_EN_MASK						0x00000001
+#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT					0x0000B070
+#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK		0x0000000C
+#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK		0x00000003
+#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT					0x0000B070
+#define AVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR				0x0000B200
+#define AVBUF_V_BLEND_LAYER1_CONTROL					0x0000A01C
+#define AVBUF_V_BLEND_IN2CSC_COEFF0					0x0000A080
+#define AVBUF_BUF_FORMAT						0x0000B000
+#define AVBUF_BUF_FORMAT_NL_VID_FORMAT_MASK				0x0000001F
+#define AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK				0x00000F00
+#define AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT				8
+#define AVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT			1
+#define AVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT		4
+#define AVBUF_V_BLEND_OUTPUT_VID_FORMAT					0x0000A014
+#define AVBUF_V_BLEND_RGB2YCBCR_COEFF0					0x0000A020
+#define AVBUF_V_BLEND_LUMA_OUTCSC_OFFSET				0x0000A074
+#define AVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT		16
+#define AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT			1
+#define AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG				0x0000A00C
+#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT			1
+#define DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE_SHIFT			3
+#define DP_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_SHIFT			4
+#define DP_MAIN_STREAM_MISC1_Y_ONLY_EN_MASK				0x00000080
+#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_YCBCR422			0x1
+#define AVBUF_PL_CLK							0x0
+#define AVBUF_PS_CLK							0x1
+#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT		2
+#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT			0
+#define AVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT			1
+#define AVBUF_BUF_AUD_VID_CLK_SOURCE					0x0000B120
+#define AVBUF_BUF_SRST_REG						0x0000B124
+#define AVBUF_BUF_SRST_REG_VID_RST_MASK					0x00000002
+#define AVBUF_CLK_FPD_BASEADDR						0xFD1A0000
+#define AVBUF_CLK_LPD_BASEADDR						0xFF5E0000
+#define AVBUF_LPD_CTRL_OFFSET						16
+#define AVBUF_FPD_CTRL_OFFSET						12
+#define AVBUF_EXTERNAL_DIVIDER						2
+#define AVBUF_VIDEO_REF_CTRL						0x00000070
+#define AVBUF_VIDEO_REF_CTRL_SRCSEL_MASK				0x00000007
+#define AVBUF_VPLL_SRC_SEL						0
+#define AVBUF_DPLL_SRC_SEL						2
+#define AVBUF_RPLL_TO_FPD_SRC_SEL					3
+#define AVBUF_INPUT_REF_CLK						3333333333
+#define AVBUF_PLL_OUT_FREQ						1450000000
+#define AVBUF_INPUT_FREQ_PRECISION					100
+#define AVBUF_PRECISION							16
+#define AVBUF_SHIFT_DECIMAL						BIT(16)
+#define AVBUF_DECIMAL							(AVBUF_SHIFT_DECIMAL - 1)
+#define AVBUF_ENABLE_BIT						1
+#define AVBUF_DISABLE_BIT						0
+#define AVBUF_PLL_CTRL_BYPASS_SHIFT					3
+#define AVBUF_PLL_CTRL_FBDIV_SHIFT					8
+#define AVBUF_PLL_CTRL_DIV2_SHIFT					16
+#define AVBUF_PLL_CTRL_PRE_SRC_SHIFT					20
+#define AVBUF_PLL_CTRL							0x00000020
+#define AVBUF_PLL_CFG_CP_SHIFT						5
+#define AVBUF_PLL_CFG_RES_SHIFT						0
+#define AVBUF_PLL_CFG_LFHF_SHIFT					10
+#define AVBUF_PLL_CFG_LOCK_DLY_SHIFT					25
+#define AVBUF_PLL_CFG_LOCK_CNT_SHIFT					13
+#define AVBUF_PLL_FRAC_CFG						0x00000028
+#define AVBUF_PLL_FRAC_CFG_ENABLED_SHIFT				31
+#define AVBUF_PLL_FRAC_CFG_DATA_SHIFT					0
+#define AVBUF_PLL_CTRL_RESET_MASK					0x00000001
+#define AVBUF_PLL_CTRL_RESET_SHIFT					0
+#define AVBUF_PLL_STATUS						0x00000044
+#define AVBUF_REG_OFFSET						4
+#define AVBUF_PLL_CTRL_BYPASS_MASK					0x00000008
+#define AVBUF_PLL_CTRL_BYPASS_SHIFT					3
+#define AVBUF_DOMAIN_SWITCH_CTRL					0x00000044
+#define AVBUF_DOMAIN_SWITCH_DIVISOR0_MASK				0x00003F00
+#define AVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT				8
+#define AVBUF_PLL_CFG							0x00000024
+#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT			0
+#define AVBUF_VIDEO_REF_CTRL_CLKACT_MASK				0x01000000
+#define AVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT				24
+#define AVBUF_VIDEO_REF_CTRL_DIVISOR1_MASK				0x003F0000
+#define AVBUF_VIDEO_REF_CTRL_DIVISOR1_SHIFT				16
+#define AVBUF_VIDEO_REF_CTRL_DIVISOR0_MASK				0x00003F00
+#define AVBUF_VIDEO_REF_CTRL_DIVISOR0_SHIFT				8
+#define AVBUF_VIDEO_REF_CTRL_CLKACT_MASK				0x01000000
+#define AVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT				24
+
+#define DP_INTERRUPT_SIG_STATE						0x0130
+#define DP_INTR_STATUS							0x03A0
+#define DP_INTERRUPT_SIG_STATE_HPD_STATE_MASK				0x00000001
+#define DP_INTR_HPD_EVENT_MASK						0x00000002
+#define DP_INTR_HPD_PULSE_DETECTED_MASK					0x00000010
+#define DP_HPD_DURATION							0x0150
+#define DP_FORCE_SCRAMBLER_RESET					0x00C0
+#define DP_ENABLE_MAIN_STREAM						0x0084
+#define DP_IS_CONNECTED_MAX_TIMEOUT_COUNT				50
+#define DP_0_LINK_RATE							20
+#define DP_0_LANE_COUNT							1
+#define DP_ENHANCED_FRAME_EN						0x0008
+#define DP_LANE_COUNT_SET						0x0004
+#define DP_LINK_BW_SET_162GBPS						0x06
+#define DP_LINK_BW_SET_270GBPS						0x0A
+#define DP_LINK_BW_SET_540GBPS						0x14
+#define DP_LINK_BW_SET							0x0000
+#define DP_DOWNSPREAD_CTRL						0x0018
+#define DP_SCRAMBLING_DISABLE						0x0014
+#define DP_AUX_CMD_READ							0x9
+#define DP_AUX_CMD_WRITE						0x8
+#define DP_AUX_CMD_I2C_READ						0x1
+#define DP_AUX_CMD_I2C_READ_MOT						0x5
+#define DP_AUX_CMD_I2C_WRITE						0x0
+#define DP_AUX_CMD_I2C_WRITE_MOT					0x4
+#define DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK				0x00000002
+#define DP_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK			0x00000004
+#define DP_REPLY_STATUS							0x014C
+#define DP_AUX_MAX_TIMEOUT_COUNT					50
+#define DP_AUX_MAX_DEFER_COUNT						50
+#define DP_AUX_ADDRESS							0x0108
+#define DP_AUX_WRITE_FIFO						0x0104
+#define DP_AUX_CMD							0x0100
+#define DP_AUX_CMD_SHIFT						8
+#define DP_AUX_CMD_NBYTES_TRANSFER_MASK					0x0000000F
+#define DP_AUX_REPLY_CODE						0x0138
+#define DP_AUX_REPLY_CODE_DEFER						0x2
+#define DP_AUX_REPLY_CODE_I2C_DEFER					0x8
+#define DP_AUX_REPLY_CODE_NACK						0x1
+#define DP_AUX_REPLY_CODE_I2C_NACK					0x4
+#define DP_REPLY_DATA_COUNT						0x0148
+#define DP_AUX_REPLY_DATA						0x0134
+#define DP_LANE_COUNT_SET_1						0x01
+#define DP_LANE_COUNT_SET_2						0x02
+#define DP_MAXIMUM_PE_LEVEL						2
+#define DP_MAXIMUM_VS_LEVEL						3
+#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_RGB			0x0
+#define DP_MAIN_STREAM_MISC0_BDC_6BPC					0x0
+#define DP_MAIN_STREAM_MISC0_BDC_8BPC					0x1
+#define DP_MAIN_STREAM_MISC0_BDC_10BPC					0x2
+#define DP_MAIN_STREAM_MISC0_BDC_12BPC					0x3
+#define DP_MAIN_STREAM_MISC0_BDC_16BPC					0x4
+#define DP_MAIN_STREAM_MISC0_BDC_SHIFT					5
+#define DP_PHY_CONFIG_TX_PHY_8B10BEN_MASK				0x0010000
+#define DP_PHY_CONFIG_PHY_RESET_MASK					0x0000001
+#define DP_ENABLE_MAIN_STREAM						0x0084
+#define DP_SOFT_RESET							0x001C
+#define DP_MAIN_STREAM_HTOTAL						0x0180
+#define DP_MAIN_STREAM_VTOTAL						0x0184
+#define DP_MAIN_STREAM_POLARITY						0x0188
+#define DP_MAIN_STREAM_POLARITY_VSYNC_POL_SHIFT				1
+#define DP_MAIN_STREAM_HSWIDTH						0x018C
+#define DP_MAIN_STREAM_VSWIDTH						0x0190
+#define DP_MAIN_STREAM_HRES						0x0194
+#define DP_MAIN_STREAM_VRES						0x0198
+#define DP_MAIN_STREAM_HSTART						0x019C
+#define DP_MAIN_STREAM_VSTART						0x01A0
+#define DP_MAIN_STREAM_MISC0						0x01A4
+#define DP_MAIN_STREAM_MISC1						0x01A8
+#define DP_M_VID							0x01AC
+#define DP_N_VID							0x01B4
+#define DP_USER_PIXEL_WIDTH						0x01B8
+#define DP_USER_DATA_COUNT_PER_LANE					0x01BC
+#define DP_TU_SIZE							0x01B0
+#define DP_MIN_BYTES_PER_TU						0x01C4
+#define DP_FRAC_BYTES_PER_TU						0x01C8
+#define DP_INIT_WAIT							0x01CC
+#define DP_PHY_CLOCK_SELECT_162GBPS					0x1
+#define DP_PHY_CLOCK_SELECT_270GBPS					0x3
+#define DP_PHY_CLOCK_SELECT_540GBPS					0x5
+#define DP_PHY_STATUS							0x0280
+#define DP_PHY_STATUS_ALL_LANES_READY_MASK				0x00000013
+#define DP_PHY_STATUS_GT_PLL_LOCK_MASK					0x00000010
+#define DP_PHY_STATUS_RESET_LANE_0_DONE_MASK				0x00000001
+#define DP_INTR_HPD_IRQ_MASK						0x00000001
+#define DP_INTR_MASK							0x03A4
+#define DP_DP_ENABLE							0x1
+#define DP_PHY_CONFIG_GT_ALL_RESET_MASK					0x0000003
+#define DP_PHY_CLOCK_SELECT						0x0234
+#define DP_AUX_CLK_DIVIDER_VAL_MASK					0x000000FF
+#define DP_AUX_CLK_DIVIDER						0x010C
+#define DP_DISABLE							0x0
+#define DP_ENABLE							0x0080
+#define DP_SOFT_RESET_EN						0x1
+#define DP_PHY_CONFIG							0x0200
+#define DP_REPLY_STATUS_REPLY_RECEIVED_MASK				0x00000001
+#define DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK				0x00000002
+#define DP_REPLY_STATUS_REPLY_ERROR_MASK				0x00000008
+#define DP_AUX_MAX_WAIT							20000
+
+#define DP_DPCD_SINK_COUNT						0x00200
+#define DP_DPCD_TP_SET_SCRAMB_DIS_MASK					0x20
+#define DP_DPCD_STATUS_LANE_1_CR_DONE_MASK				0x10
+#define DP_DPCD_STATUS_LANE_0_CR_DONE_MASK				0x01
+#define DP_DPCD_STATUS_LANE_1_CE_DONE_MASK				0x20
+#define DP_DPCD_STATUS_LANE_0_CE_DONE_MASK				0x02
+#define DP_DPCD_STATUS_LANE_1_SL_DONE_MASK				0x40
+#define DP_DPCD_STATUS_LANE_0_SL_DONE_MASK				0x04
+#define DP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK			0x01
+#define DP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK				0x03
+#define DP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK				0x30
+#define DP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT				4
+#define DP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK				0x0C
+#define DP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT				2
+#define DP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK				0xC0
+#define DP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT				6
+#define DP_DPCD_TRAINING_LANE0_SET					0x00103
+#define DP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK				0x04
+#define DP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK				0x20
+#define DP_DPCD_TRAINING_LANEX_SET_PE_SHIFT				3
+#define DP_DPCD_SET_POWER_DP_PWR_VOLTAGE				0x00600
+#define DP_DPCD_RECEIVER_CAP_FIELD_START				0x00000
+#define DP_DPCD_MAX_LINK_RATE						0x00001
+#define DP_DPCD_MAX_LANE_COUNT						0x00002
+#define DP_DPCD_MAX_LANE_COUNT_MASK					0x1F
+#define DP_DPCD_ENHANCED_FRAME_SUPPORT_MASK				0x80
+#define DP_DPCD_MAX_DOWNSPREAD						0x00003
+#define DP_DPCD_MAX_DOWNSPREAD_MASK					0x01
+#define DP_DPCD_LANE_COUNT_SET						0x00101
+#define DP_DPCD_ENHANCED_FRAME_EN_MASK					0x80
+#define DP_DPCD_LINK_BW_SET						0x00100
+#define DP_DPCD_DOWNSPREAD_CTRL						0x00107
+#define DP_DPCD_SPREAD_AMP_MASK						0x10
+#define DP_DPCD_LANE_COUNT_SET_MASK					0x1F
+#define DP_DPCD_TPS3_SUPPORT_MASK					0x40
+#define DP_DPCD_TRAIN_AUX_RD_INTERVAL					0x0000E
+#define DP_DPCD_SINK_COUNT_HIGH_MASK					0x80
+#define DP_DPCD_SINK_COUNT_HIGH_LOW_SHIFT				1
+#define DP_DPCD_SINK_COUNT_LOW_MASK					0x3F
+#define DP_DPCD_TP_SET							0x00102
+
+#define SERDES_BASEADDR							0xFD400000
+#define SERDES_L0_TX_MARGININGF						0x0CC0
+#define SERDES_L0_TX_DEEMPHASIS						0x0048
+#define SERDES_LANE_OFFSET						0x4000
+
+#define DPDMA_TRIGGER_EN						1U
+#define DPDMA_RETRIGGER_EN						2U
+#define DPDMA_DESC_PREAMBLE						0xA5U
+#define DPDMA_DESC_IGNR_DONE						0x400U
+#define DPDMA_DESC_LAST_FRAME						0x200000U
+#define DPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT				18
+#define DPDMA_DESCRIPTOR_SRC_ADDR_WIDTH					32U
+#define DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT			16U
+#define DPDMA_CH0_DSCR_STRT_ADDR					0X0204U
+#define DPDMA_CH_OFFSET							0x100U
+#define DPDMA_CH0_CNTL							0x0218U
+#define DPDMA_CH3_CNTL							0x0518U
+#define DPDMA_CH0_DSCR_STRT_ADDRE					0x0200U
+#define DPDMA_CH3_DSCR_STRT_ADDR					0x0504
+#define DPDMA_CH3_DSCR_STRT_ADDRE					0x0500
+#define DPDMA_CH_CNTL_EN_MASK						0x1U
+#define DPDMA_CH_CNTL_PAUSE_MASK					0x2U
+#define DPDMA_GBL							0x0104U
+#define DPDMA_GBL_TRG_CH3_MASK						0x8
+#define DPDMA_TRIGGER_DONE						0U
+#define DPDMA_CH_CNTL_EN_MASK						0x1U
+#define DPDMA_CH_CNTL_PAUSE_MASK					0x2U
+#define DPDMA_CH_CNTL_QOS_DATA_RD_SHIFT					10U
+#define DPDMA_CH_CNTL_QOS_DATA_RD_MASK					0x3C00U
+#define DPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT					6U
+#define DPDMA_CH_CNTL_QOS_DSCR_RD_MASK					0x03C0U
+#define DPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT					2U
+#define DPDMA_CH_CNTL_QOS_DSCR_WR_MASK					0x3CU
+#define DPDMA_CH_OFFSET							0x100U
+#define DPDMA_WAIT_TIMEOUT						10000U
+#define DPDMA_AUDIO_ALIGNMENT						128U
+#define DPDMA_VIDEO_CHANNEL0						0U
+#define DPDMA_VIDEO_CHANNEL1						1U
+#define DPDMA_VIDEO_CHANNEL2						2U
+#define DPDMA_GRAPHICS_CHANNEL						3U
+#define DPDMA_AUDIO_CHANNEL0						4U
+#define DPDMA_AUDIO_CHANNEL1						5U
+#define DPDMA_DESC_PREAMBLE						0xA5U
+#define DPDMA_DESC_IGNR_DONE						0x400U
+#define DPDMA_DESC_UPDATE						0x200U
+#define DPDMA_DESC_COMP_INTR						0x100U
+#define DPDMA_DESC_LAST_FRAME						0x200000U
+#define DPDMA_DESC_DONE_SHIFT						31U
+#define DPDMA_QOS_MIN							4U
+#define DPDMA_QOS_MAX							11U
+#define DPDMA_BASE_ADDRESS						0xFD4C0000
+#define DPDMA_ISR							0x0004U
+#define DPDMA_IEN							0x000CU
+#define DPDMA_ISR_VSYNC_INT_MASK					0x08000000
+
+#define CLK_FPD_BASEADDR						0xFD1A0000
+#define VIDEO_REF_CTRL							0x00000070
+#define VIDEO_REF_CTRL_SRCSEL_MASK					0x00000007
+#define PLL_OUT_FREQ							1450000000
+#define INPUT_FREQ_PRECISION						100
+#define PRECISION							16
+#define SHIFT_DECIMAL							BIT(16)
+#define ENABLE_BIT							1
+#define DISABLE_BIT							0
+#define PLL_CTRL_BYPASS_SHIFT						3
+#define PLL_CTRL_FBDIV_SHIFT						8
+#define PLL_CTRL_DIV2_SHIFT						16
+#define PLL_CTRL_PRE_SRC_SHIFT						20
+#define PLL_CTRL							0x00000020
+#define VPLL_CTRL							0x00000038
+#define PLL_CFG								0x00000024
+#define VPLL								2
+#define VPLL_CFG							0x0000003C
+#define VPLL_CFG_CP							4
+#define VPLL_CFG_RES							6
+#define VPLL_CFG_LFHF							3
+#define VPLL_CFG_LOCK_DLY						63
+#define VPLL_CFG_LOCK_CNT						600
+#define PLL_STATUS_VPLL_LOCK						2
+#define PLL_CFG_CP_SHIFT						5
+#define PLL_CFG_RES_SHIFT						0
+#define PLL_CFG_LFHF_SHIFT						10
+#define PLL_CFG_LOCK_DLY_SHIFT						25
+#define PLL_CFG_LOCK_CNT_SHIFT						13
+#define PLL_FRAC_CFG							0x00000028
+#define VPLL_FRAC_CFG							0x00000040
+#define PLL_FRAC_CFG_ENABLED_SHIFT					31
+#define PLL_FRAC_CFG_DATA_SHIFT						0
+#define PLL_CTRL_RESET_MASK						0x00000001
+#define PLL_CTRL_RESET_SHIFT						0
+#define PLL_STATUS							0x00000044
+#define REG_OFFSET							4
+#define PLL_CTRL_BYPASS_MASK						0x00000008
+#define PLL_CTRL_BYPASS_SHIFT						3
+#define DOMAIN_SWITCH_CTRL						0x00000044
+#define DOMAIN_SWITCH_DIVISOR0_MASK					0x00003F00
+#define DOMAIN_SWITCH_DIVISOR0_SHIFT					8
+#define VIDEO_REF_CTRL_CLKACT_MASK					0x01000000
+#define VIDEO_REF_CTRL_CLKACT_SHIFT					24
+#define VIDEO_REF_CTRL_DIVISOR1_MASK					0x003F0000
+#define VIDEO_REF_CTRL_DIVISOR1_SHIFT					16
+#define VIDEO_REF_CTRL_DIVISOR0_MASK					0x00003F00
+#define VIDEO_REF_CTRL_DIVISOR0_SHIFT					8
+#define PSS_REF_CLK							0
+#define FPD_CTRL_OFFSET							12
+#define VIDC_VM_NUM_SUPPORTED						2
+
+static const u32 vs[4][4] = {
+	{ 0x2a, 0x27, 0x24, 0x20 },
+	{ 0x27, 0x23, 0x20, 0xff },
+	{ 0x24, 0x20, 0xff, 0xff },
+	{ 0xff, 0xff, 0xff, 0xff },
+};
+
+static const u32 pe[4][4] = {
+	{ 0x02, 0x02, 0x02, 0x02 },
+	{ 0x01, 0x01, 0x01, 0xff },
+	{ 0x00, 0x00, 0xff, 0xff },
+	{ 0xff, 0xff, 0xff, 0xff },
+};
+
+const struct video_timing_mode vidc_video_timing_modes[VIDC_VM_NUM_SUPPORTED] = {
+	{ VIDC_VM_640x480_60_P, "640x480@60Hz", VIDC_FR_60HZ,
+	{640, 16, 96, 48, 800, 0,
+	 480, 10, 2, 33, 525, 0, 0, 0, 0, 0} },
+	{ VIDC_VM_1024x768_60_P, "1024x768@60Hz", VIDC_FR_60HZ,
+	{1024, 24, 136, 160, 1344, 0,
+	 768, 3, 6, 29, 806, 0, 0, 0, 0, 0} },
+};
+
+const struct av_buf_vid_attribute avbuf_supported_formats[] = {
+	/* Non-Live Graphics formats */
+	{ RGBA8888, 0, INTERLEAVED,
+	{AVBUF_BUF_8BIT_SF, AVBUF_BUF_8BIT_SF, AVBUF_BUF_8BIT_SF},
+	 0, 1, 0, 32},
+};
+
+#endif
diff --git a/drivers/video/zynqmp_dpsub.c b/drivers/video/zynqmp_dpsub.c
deleted file mode 100644
index 4ead663cd5..0000000000
--- a/drivers/video/zynqmp_dpsub.c
+++ /dev/null
@@ -1,66 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2021 Xilinx Inc.
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <dm.h>
-#include <errno.h>
-#include <video.h>
-#include <dm/device_compat.h>
-
-#define WIDTH	640
-#define HEIGHT	480
-
-/**
- * struct zynqmp_dpsub_priv - Private structure
- * @dev: Device uclass for video_ops
- */
-struct zynqmp_dpsub_priv {
-	struct udevice *dev;
-};
-
-static int zynqmp_dpsub_probe(struct udevice *dev)
-{
-	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
-	struct zynqmp_dpsub_priv *priv = dev_get_priv(dev);
-
-	uc_priv->bpix = VIDEO_BPP16;
-	uc_priv->xsize = WIDTH;
-	uc_priv->ysize = HEIGHT;
-	uc_priv->rot = 0;
-
-	priv->dev = dev;
-
-	/* Only placeholder for power domain driver */
-	return 0;
-}
-
-static int zynqmp_dpsub_bind(struct udevice *dev)
-{
-	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
-
-	plat->size = WIDTH * HEIGHT * 16;
-
-	return 0;
-}
-
-static const struct video_ops zynqmp_dpsub_ops = {
-};
-
-static const struct udevice_id zynqmp_dpsub_ids[] = {
-	{ .compatible = "xlnx,zynqmp-dpsub-1.7" },
-	{ }
-};
-
-U_BOOT_DRIVER(zynqmp_dpsub_video) = {
-	.name = "zynqmp_dpsub_video",
-	.id = UCLASS_VIDEO,
-	.of_match = zynqmp_dpsub_ids,
-	.ops = &zynqmp_dpsub_ops,
-	.plat_auto = sizeof(struct video_uc_plat),
-	.bind = zynqmp_dpsub_bind,
-	.probe = zynqmp_dpsub_probe,
-	.priv_auto = sizeof(struct zynqmp_dpsub_priv),
-};
diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c
index 31bb21c534..c542016273 100644
--- a/drivers/virtio/virtio-uclass.c
+++ b/drivers/virtio/virtio-uclass.c
@@ -238,7 +238,7 @@ static int virtio_uclass_post_probe(struct udevice *udev)
 
 	ret = device_bind_driver(udev, name, str, &vdev);
 	if (ret == -ENOENT) {
-		debug("(%s): no driver configured\n", udev->name);
+		debug("(%s): %s driver not configured\n", udev->name, name);
 		return 0;
 	}
 	if (ret) {
@@ -248,7 +248,7 @@ static int virtio_uclass_post_probe(struct udevice *udev)
 	device_set_name_alloced(vdev);
 
 	if (uc_priv->device == VIRTIO_ID_BLOCK && !IS_ENABLED(CONFIG_SANDBOX)) {
-		ret = bootdev_setup_sibling_blk(vdev, "virtio_bootdev");
+		ret = bootdev_setup_for_sibling_blk(vdev, "virtio_bootdev");
 		if (ret)
 			return log_msg_ret("bootdev", ret);
 	}
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 646663528a..07fc4940e9 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -178,6 +178,13 @@ config WDT_MAX6370
 	help
 	  Select this to enable max6370 watchdog timer.
 
+config WDT_MCF
+	bool "ColdFire family watchdog timer support"
+	depends on WDT
+	help
+	  Select this to enable ColdFire watchdog timer,
+	  which supports mcf52x2 mcf532x mcf523x families.
+
 config WDT_MESON_GXBB
 	bool "Amlogic watchdog timer support"
 	depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index fd5d9c7376..eef786f5e7 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
 obj-$(CONFIG_WDT_FTWDT010) += ftwdt010_wdt.o
 obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o
 obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o
+obj-$(CONFIG_WDT_MCF) += mcf_wdt.o
 obj-$(CONFIG_WDT_MESON_GXBB) += meson_gxbb_wdt.o
 obj-$(CONFIG_WDT_MPC8xxx) += mpc8xxx_wdt.o
 obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o
diff --git a/drivers/watchdog/ftwdt010_wdt.c b/drivers/watchdog/ftwdt010_wdt.c
index a6b33b1720..1f5f301b12 100644
--- a/drivers/watchdog/ftwdt010_wdt.c
+++ b/drivers/watchdog/ftwdt010_wdt.c
@@ -25,8 +25,27 @@ struct ftwdt010_wdt_priv {
 	struct ftwdt010_wdt __iomem *regs;
 };
 
+static int ftwdt010_wdt_reset(struct udevice *dev)
+{
+	struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
+	struct ftwdt010_wdt *wd = priv->regs;
+
+	debug("Reset WDT..\n");
+
+	/* clear control register */
+	writel(0, &wd->wdcr);
+
+	/* Write Magic number */
+	writel(FTWDT010_WDRESTART_MAGIC, &wd->wdrestart);
+
+	/* Enable WDT */
+	writel(FTWDT010_WDCR_RST | FTWDT010_WDCR_ENABLE, &wd->wdcr);
+
+	return 0;
+}
+
 /*
- * Set the watchdog time interval.
+ * Set the watchdog time interval and start the timer.
  * Counter is 32 bit.
  */
 static int ftwdt010_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
@@ -52,24 +71,7 @@ static int ftwdt010_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
 
 	writel(reg, &wd->wdload);
 
-	return 0;
-}
-
-static int ftwdt010_wdt_reset(struct udevice *dev)
-{
-	struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
-	struct ftwdt010_wdt *wd = priv->regs;
-
-	/* clear control register */
-	writel(0, &wd->wdcr);
-
-	/* Write Magic number */
-	writel(FTWDT010_WDRESTART_MAGIC, &wd->wdrestart);
-
-	/* Enable WDT */
-	writel((FTWDT010_WDCR_RST | FTWDT010_WDCR_ENABLE), &wd->wdcr);
-
-	return 0;
+	return ftwdt010_wdt_reset(dev);
 }
 
 static int ftwdt010_wdt_stop(struct udevice *dev)
diff --git a/drivers/watchdog/mcf_wdt.c b/drivers/watchdog/mcf_wdt.c
new file mode 100644
index 0000000000..b36488bb5b
--- /dev/null
+++ b/drivers/watchdog/mcf_wdt.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * mcf_wdt.c - driver for ColdFire on-chip watchdog
+ *
+ * Author: Angelo Dureghello <angelo@kernel-space.org>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <hang.h>
+#include <asm/io.h>
+#include <wdt.h>
+#include <linux/bitops.h>
+
+#define DIVIDER_5XXX	4096
+#define DIVIDER_5282	8192
+
+#define WCR_EN          BIT(0)
+#define WCR_HALTED      BIT(1)
+#define WCR_DOZE        BIT(2)
+#define WCR_WAIT        BIT(3)
+
+struct watchdog_regs {
+	u16 wcr;        /* Control */
+	u16 wmr;        /* Service */
+	u16 wcntr;      /* Counter */
+	u16 wsr;        /* Reset Status */
+};
+
+static void mcf_watchdog_reset(struct watchdog_regs *wdog)
+{
+	if (!IS_ENABLED(CONFIG_WATCHDOG_RESET_DISABLE)) {
+		writew(0x5555, &wdog->wsr);
+		writew(0xaaaa, &wdog->wsr);
+	}
+}
+
+static void mcf_watchdog_init(struct watchdog_regs *wdog, u32 fixed_divider,
+			      u64 timeout_msecs)
+{
+	u32 wdog_module, cycles_per_sec;
+
+	cycles_per_sec = CFG_SYS_CLK / fixed_divider;
+
+	wdog_module = cycles_per_sec * ((u32)timeout_msecs / 1000);
+	wdog_module += (cycles_per_sec / 1000) * ((u32)timeout_msecs % 1000);
+
+	/* Limit check, max 16 bits */
+	if (wdog_module > 0xffff)
+		wdog_module = 0xffff;
+
+	/* Set timeout and enable watchdog */
+	writew((u16)wdog_module, &wdog->wmr);
+	writew(WCR_EN, &wdog->wcr);
+
+	mcf_watchdog_reset(wdog);
+}
+
+struct mcf_wdt_priv {
+	void __iomem *base;
+	u32 fixed_divider;
+};
+
+static int mcf_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+	hang();
+
+	return 0;
+}
+
+static int mcf_wdt_reset(struct udevice *dev)
+{
+	struct mcf_wdt_priv *priv = dev_get_priv(dev);
+
+	mcf_watchdog_reset(priv->base);
+
+	return 0;
+}
+
+static int mcf_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+	struct mcf_wdt_priv *priv = dev_get_priv(dev);
+
+	/* Timeout from fdt (timeout) comes in milliseconds */
+	mcf_watchdog_init(priv->base, priv->fixed_divider, timeout);
+
+	return 0;
+}
+
+static int mcf_wdt_stop(struct udevice *dev)
+{
+	struct mcf_wdt_priv *priv = dev_get_priv(dev);
+	struct watchdog_regs *wdog = (struct watchdog_regs *)priv->base;
+
+	setbits_be16(&wdog->wcr, WCR_HALTED);
+
+	return 0;
+}
+
+static int mcf_wdt_probe(struct udevice *dev)
+{
+	struct mcf_wdt_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -ENOENT;
+
+	priv->fixed_divider = (u32)dev_get_driver_data(dev);
+
+	return 0;
+}
+
+static const struct wdt_ops mcf_wdt_ops = {
+	.start		= mcf_wdt_start,
+	.stop		= mcf_wdt_stop,
+	.reset		= mcf_wdt_reset,
+	.expire_now	= mcf_wdt_expire_now,
+};
+
+static const struct udevice_id mcf_wdt_ids[] = {
+	{ .compatible = "fsl,mcf5208-wdt", .data = DIVIDER_5XXX },
+	{ .compatible = "fsl,mcf5282-wdt", .data = DIVIDER_5282 },
+	{}
+};
+
+U_BOOT_DRIVER(mcf_wdt) = {
+	.name		= "mcf_wdt",
+	.id		= UCLASS_WDT,
+	.of_match	= mcf_wdt_ids,
+	.probe		= mcf_wdt_probe,
+	.ops		= &mcf_wdt_ops,
+	.priv_auto	= sizeof(struct mcf_wdt_priv),
+	.flags		= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/watchdog/xilinx_tb_wdt.c b/drivers/watchdog/xilinx_tb_wdt.c
index 0f9fb02002..b38c400016 100644
--- a/drivers/watchdog/xilinx_tb_wdt.c
+++ b/drivers/watchdog/xilinx_tb_wdt.c
@@ -2,7 +2,7 @@
 /*
  * Xilinx AXI platforms watchdog timer driver.
  *
- * Author(s):	Michal Simek <michal.simek@xilinx.com>
+ * Author(s):	Michal Simek <michal.simek@amd.com>
  *		Shreenidhi Shedi <yesshedi@gmail.com>
  *
  * Copyright (c) 2011-2018 Xilinx Inc.
diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c
index d582e3cc8f..963ab22fb4 100644
--- a/drivers/watchdog/xilinx_wwdt.c
+++ b/drivers/watchdog/xilinx_wwdt.c
@@ -2,7 +2,7 @@
 /*
  * Xilinx window watchdog timer driver.
  *
- * Author(s):	Michal Simek <michal.simek@xilinx.com>
+ * Author(s):	Michal Simek <michal.simek@amd.com>
  *		Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
  *
  * Copyright (c) 2020, Xilinx Inc.
@@ -191,7 +191,8 @@ static const struct wdt_ops xlnx_wwdt_ops = {
 };
 
 static const struct udevice_id xlnx_wwdt_ids[] = {
-	{ .compatible = "xlnx,versal-wwdt-1.0", },
+	{ .compatible = "xlnx,versal-wwdt", },
+	{ .compatible = "xlnx,versal-wwdt-1.0", }, /* deprecated */
 	{},
 };
 
diff --git a/dts/Kconfig b/dts/Kconfig
index 3b7489f0f8..9152f5885e 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -171,7 +171,7 @@ config OF_LIST
 	default DEFAULT_DEVICE_TREE
 	help
 	  This option specifies a list of device tree files to use for DT
-	  control. These will be packaged into a FIT. At run-time, U-boot
+	  control. These will be packaged into a FIT. At run-time, U-Boot
 	  or SPL will select the correct DT to use by examining the
 	  hardware (e.g. reading a board ID value). This is a list of
 	  device tree files (without the directory or .dtb suffix)
@@ -254,7 +254,7 @@ config DTB_RESELECT
 config MULTI_DTB_FIT
 	bool "Support embedding several DTBs in a FIT image for u-boot"
 	help
-	  This option provides hooks to allow U-boot to parse an
+	  This option provides hooks to allow U-Boot to parse an
 	  appended FIT image and enable board specific code to then select
 	  the correct DTB to be used. Use this if you need to support
 	  multiple DTBs but don't use the SPL.
diff --git a/dts/Makefile b/dts/Makefile
index cb31113829..3437e54033 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -63,4 +63,6 @@ spl_dtbs: $(obj)/dt-$(SPL_NAME).dtb
 clean-files := dt.dtb.S
 
 # Let clean descend into dts directories
-subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts ../arch/powerpc/dts ../arch/riscv/dts
+subdir- += ../arch/arc/dts ../arch/arm/dts ../arch/m68k/dts ../arch/microblaze/dts	\
+	   ../arch/mips/dts ../arch/nios2/dts ../arch/powerpc/dts ../arch/riscv/dts	\
+	   ../arch/sandbox/dts ../arch/sh/dts ../arch/x86/dts ../arch/xtensa/dts
diff --git a/env/Kconfig b/env/Kconfig
index 2bbe4c466a..13e32104b4 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -55,20 +55,23 @@ config ENV_MAX_ENTRIES
 	  be generous and should work in most cases. This setting can be used
 	  to tune behaviour; see lib/hashtable.c for details.
 
-config ENV_IS_NOWHERE
-	bool "Environment is not stored"
-	default y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \
+config ENV_IS_DEFAULT
+	def_bool y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \
 		     !ENV_IS_IN_FAT && !ENV_IS_IN_FLASH && \
 		     !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
 		     !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
 		     !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
 		     !ENV_IS_IN_UBI
+	select ENV_IS_NOWHERE
+
+config ENV_IS_NOWHERE
+	bool "Environment is not stored"
 	help
-	  Define this if you don't want to or can't have an environment stored
+	  Define this if you don't care whether or not an environment is stored
 	  on a storage medium. In this case the environment will still exist
-	  while U-Boot is running, but once U-Boot exits it will not be
-	  stored. U-Boot will therefore always start up with a default
-	  environment.
+	  while U-Boot is running, but once U-Boot exits it may not be
+	  stored. If no other ENV_IS_IN_ is defined, U-Boot will always start
+	  up with the default environment.
 
 config ENV_IS_IN_EEPROM
 	bool "Environment in EEPROM"
@@ -659,6 +662,18 @@ config SYS_MMC_ENV_PART
 	  partition 0 or the first boot partition, which is 1 or some other defined
 	  partition.
 
+config USE_ENV_MMC_PARTITION
+	bool "use the mmc environment partition name"
+	depends on ENV_IS_IN_MMC
+
+config ENV_MMC_PARTITION
+	string "mmc environment partition name"
+	depends on USE_ENV_MMC_PARTITION
+	help
+	  MMC partition name used to save environment variables.
+	  If this variable is unset, u-boot will try to get the env partition name
+	  from the device-tree's /config node.
+
 config ENV_MMC_USE_DT
 	bool "Read partition name and offset in DT"
 	depends on ENV_IS_IN_MMC && OF_CONTROL
diff --git a/env/common.c b/env/common.c
index 8beb8e6aa4..0ecdb248a0 100644
--- a/env/common.c
+++ b/env/common.c
@@ -353,6 +353,7 @@ int env_check_redund(const char *buf1, int buf1_read_fail,
 				tmp_env2->crc;
 
 	if (!crc1_ok && !crc2_ok) {
+		gd->env_valid = ENV_INVALID;
 		return -ENOMSG; /* needed for env_load() */
 	} else if (crc1_ok && !crc2_ok) {
 		gd->env_valid = ENV_VALID;
diff --git a/env/env.c b/env/env.c
index ad774f4117..2aa52c98f8 100644
--- a/env/env.c
+++ b/env/env.c
@@ -217,9 +217,7 @@ int env_load(void)
 			printf("OK\n");
 			gd->env_load_prio = prio;
 
-#if !CONFIG_IS_ENABLED(ENV_APPEND)
 			return 0;
-#endif
 		} else if (ret == -ENOMSG) {
 			/* Handle "bad CRC" case */
 			if (best_prio == -1)
diff --git a/env/mmc.c b/env/mmc.c
index 7a5836ad66..cb14bbb58f 100644
--- a/env/mmc.c
+++ b/env/mmc.c
@@ -114,8 +114,13 @@ static inline s64 mmc_offset(struct mmc *mmc, int copy)
 	if (IS_ENABLED(CONFIG_SYS_MMC_ENV_PART))
 		hwpart = mmc_get_env_part(mmc);
 
+#if defined(CONFIG_ENV_MMC_PARTITION)
+	str = CONFIG_ENV_MMC_PARTITION;
+#else
 	/* look for the partition in mmc CONFIG_SYS_MMC_ENV_DEV */
 	str = ofnode_conf_read_str(dt_prop.partition);
+#endif
+
 	if (str) {
 		/* try to place the environment at end of the partition */
 		err = mmc_offset_try_partition(str, copy, &val);
diff --git a/fs/btrfs/compat.h b/fs/btrfs/compat.h
index 9cf8a10c76..02173dea5f 100644
--- a/fs/btrfs/compat.h
+++ b/fs/btrfs/compat.h
@@ -46,7 +46,7 @@
 /*
  * Read data from device specified by @desc and @part
  *
- * U-boot equivalent of pread().
+ * U-Boot equivalent of pread().
  *
  * Return the bytes of data read.
  * Return <0 for error.
diff --git a/fs/btrfs/crypto/hash.c b/fs/btrfs/crypto/hash.c
index 891a2974be..0a0b35fe9b 100644
--- a/fs/btrfs/crypto/hash.c
+++ b/fs/btrfs/crypto/hash.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 
+#include <asm/unaligned.h>
 #include <linux/xxhash.h>
-#include <linux/unaligned/access_ok.h>
 #include <linux/types.h>
 #include <u-boot/sha256.h>
 #include <u-boot/blake2.h>
diff --git a/fs/btrfs/extent-io.h b/fs/btrfs/extent-io.h
index 6b0c87da96..5c5c579d1e 100644
--- a/fs/btrfs/extent-io.h
+++ b/fs/btrfs/extent-io.h
@@ -8,7 +8,7 @@
  *   Use pointer to provide better alignment.
  * - Remove max_cache_size related interfaces
  *   Includes free_extent_buffer_nocache()
- *   As we don't cache eb in U-boot.
+ *   As we don't cache eb in U-Boot.
  * - Include headers
  *
  * Write related functions are kept as we still need to modify dummy extent
diff --git a/fs/erofs/data.c b/fs/erofs/data.c
index 761896054c..f4b21d7917 100644
--- a/fs/erofs/data.c
+++ b/fs/erofs/data.c
@@ -12,23 +12,23 @@ static int erofs_map_blocks_flatmode(struct erofs_inode *inode,
 	struct erofs_inode *vi = inode;
 	bool tailendpacking = (vi->datalayout == EROFS_INODE_FLAT_INLINE);
 
-	nblocks = DIV_ROUND_UP(inode->i_size, EROFS_BLKSIZ);
+	nblocks = BLK_ROUND_UP(inode->i_size);
 	lastblk = nblocks - tailendpacking;
 
 	/* there is no hole in flatmode */
 	map->m_flags = EROFS_MAP_MAPPED;
 
-	if (offset < blknr_to_addr(lastblk)) {
-		map->m_pa = blknr_to_addr(vi->u.i_blkaddr) + map->m_la;
-		map->m_plen = blknr_to_addr(lastblk) - offset;
+	if (offset < erofs_pos(lastblk)) {
+		map->m_pa = erofs_pos(vi->u.i_blkaddr) + map->m_la;
+		map->m_plen = erofs_pos(lastblk) - offset;
 	} else if (tailendpacking) {
 		/* 2 - inode inline B: inode, [xattrs], inline last blk... */
 		map->m_pa = iloc(vi->nid) + vi->inode_isize +
 			vi->xattr_isize + erofs_blkoff(map->m_la);
 		map->m_plen = inode->i_size - offset;
 
-		/* inline data should be located in one meta block */
-		if (erofs_blkoff(map->m_pa) + map->m_plen > PAGE_SIZE) {
+		/* inline data should be located in the same meta block */
+		if (erofs_blkoff(map->m_pa) + map->m_plen > erofs_blksiz()) {
 			erofs_err("inline data cross block boundary @ nid %" PRIu64,
 				  vi->nid);
 			DBG_BUGON(1);
@@ -55,7 +55,7 @@ int erofs_map_blocks(struct erofs_inode *inode,
 {
 	struct erofs_inode *vi = inode;
 	struct erofs_inode_chunk_index *idx;
-	u8 buf[EROFS_BLKSIZ];
+	u8 buf[EROFS_MAX_BLOCK_SIZE];
 	u64 chunknr;
 	unsigned int unit;
 	erofs_off_t pos;
@@ -87,7 +87,7 @@ int erofs_map_blocks(struct erofs_inode *inode,
 
 	map->m_la = chunknr << vi->u.chunkbits;
 	map->m_plen = min_t(erofs_off_t, 1UL << vi->u.chunkbits,
-			    roundup(inode->i_size - map->m_la, EROFS_BLKSIZ));
+			    roundup(inode->i_size - map->m_la, erofs_blksiz()));
 
 	/* handle block map */
 	if (!(vi->u.chunkformat & EROFS_CHUNK_FORMAT_INDEXES)) {
@@ -96,7 +96,7 @@ int erofs_map_blocks(struct erofs_inode *inode,
 		if (le32_to_cpu(*blkaddr) == EROFS_NULL_ADDR) {
 			map->m_flags = 0;
 		} else {
-			map->m_pa = blknr_to_addr(le32_to_cpu(*blkaddr));
+			map->m_pa = erofs_pos(le32_to_cpu(*blkaddr));
 			map->m_flags = EROFS_MAP_MAPPED;
 		}
 		goto out;
@@ -110,7 +110,7 @@ int erofs_map_blocks(struct erofs_inode *inode,
 	default:
 		map->m_deviceid = le16_to_cpu(idx->device_id) &
 			sbi.device_id_mask;
-		map->m_pa = blknr_to_addr(le32_to_cpu(idx->blkaddr));
+		map->m_pa = erofs_pos(le32_to_cpu(idx->blkaddr));
 		map->m_flags = EROFS_MAP_MAPPED;
 		break;
 	}
@@ -119,23 +119,23 @@ out:
 	return err;
 }
 
-int erofs_map_dev(struct erofs_sb_info *sbi, struct erofs_map_dev *map)
+int erofs_map_dev(struct erofs_map_dev *map)
 {
 	struct erofs_device_info *dif;
 	int id;
 
 	if (map->m_deviceid) {
-		if (sbi->extra_devices < map->m_deviceid)
+		if (sbi.extra_devices < map->m_deviceid)
 			return -ENODEV;
-	} else if (sbi->extra_devices) {
-		for (id = 0; id < sbi->extra_devices; ++id) {
+	} else if (sbi.extra_devices) {
+		for (id = 0; id < sbi.extra_devices; ++id) {
 			erofs_off_t startoff, length;
 
-			dif = sbi->devs + id;
+			dif = sbi.devs + id;
 			if (!dif->mapped_blkaddr)
 				continue;
-			startoff = blknr_to_addr(dif->mapped_blkaddr);
-			length = blknr_to_addr(dif->blocks);
+			startoff = erofs_pos(dif->mapped_blkaddr);
+			length = erofs_pos(dif->blocks);
 
 			if (map->m_pa >= startoff &&
 			    map->m_pa < startoff + length) {
@@ -147,19 +147,38 @@ int erofs_map_dev(struct erofs_sb_info *sbi, struct erofs_map_dev *map)
 	return 0;
 }
 
+int erofs_read_one_data(struct erofs_map_blocks *map, char *buffer, u64 offset,
+			size_t len)
+{
+	struct erofs_map_dev mdev;
+	int ret;
+
+	mdev = (struct erofs_map_dev) {
+		.m_deviceid = map->m_deviceid,
+		.m_pa = map->m_pa,
+	};
+	ret = erofs_map_dev(&mdev);
+	if (ret)
+		return ret;
+
+	ret = erofs_dev_read(mdev.m_deviceid, buffer, mdev.m_pa + offset, len);
+	if (ret < 0)
+		return -EIO;
+	return 0;
+}
+
 static int erofs_read_raw_data(struct erofs_inode *inode, char *buffer,
 			       erofs_off_t size, erofs_off_t offset)
 {
 	struct erofs_map_blocks map = {
 		.index = UINT_MAX,
 	};
-	struct erofs_map_dev mdev;
 	int ret;
 	erofs_off_t ptr = offset;
 
 	while (ptr < offset + size) {
 		char *const estart = buffer + ptr - offset;
-		erofs_off_t eend;
+		erofs_off_t eend, moff = 0;
 
 		map.m_la = ptr;
 		ret = erofs_map_blocks(inode, &map, 0);
@@ -168,14 +187,6 @@ static int erofs_read_raw_data(struct erofs_inode *inode, char *buffer,
 
 		DBG_BUGON(map.m_plen != map.m_llen);
 
-		mdev = (struct erofs_map_dev) {
-			.m_deviceid = map.m_deviceid,
-			.m_pa = map.m_pa,
-		};
-		ret = erofs_map_dev(&sbi, &mdev);
-		if (ret)
-			return ret;
-
 		/* trim extent */
 		eend = min(offset + size, map.m_la + map.m_llen);
 		DBG_BUGON(ptr < map.m_la);
@@ -193,19 +204,73 @@ static int erofs_read_raw_data(struct erofs_inode *inode, char *buffer,
 		}
 
 		if (ptr > map.m_la) {
-			mdev.m_pa += ptr - map.m_la;
+			moff = ptr - map.m_la;
 			map.m_la = ptr;
 		}
 
-		ret = erofs_dev_read(mdev.m_deviceid, estart, mdev.m_pa,
-				     eend - map.m_la);
-		if (ret < 0)
-			return -EIO;
+		ret = erofs_read_one_data(&map, estart, moff, eend - map.m_la);
+		if (ret)
+			return ret;
 		ptr = eend;
 	}
 	return 0;
 }
 
+int z_erofs_read_one_data(struct erofs_inode *inode,
+			  struct erofs_map_blocks *map, char *raw, char *buffer,
+			  erofs_off_t skip, erofs_off_t length, bool trimmed)
+{
+	struct erofs_map_dev mdev;
+	int ret = 0;
+
+	if (map->m_flags & EROFS_MAP_FRAGMENT) {
+		struct erofs_inode packed_inode = {
+			.nid = sbi.packed_nid,
+		};
+
+		ret = erofs_read_inode_from_disk(&packed_inode);
+		if (ret) {
+			erofs_err("failed to read packed inode from disk");
+			return ret;
+		}
+
+		return erofs_pread(&packed_inode, buffer, length - skip,
+				   inode->fragmentoff + skip);
+	}
+
+	/* no device id here, thus it will always succeed */
+	mdev = (struct erofs_map_dev) {
+		.m_pa = map->m_pa,
+	};
+	ret = erofs_map_dev(&mdev);
+	if (ret) {
+		DBG_BUGON(1);
+		return ret;
+	}
+
+	ret = erofs_dev_read(mdev.m_deviceid, raw, mdev.m_pa, map->m_plen);
+	if (ret < 0)
+		return ret;
+
+	ret = z_erofs_decompress(&(struct z_erofs_decompress_req) {
+			.in = raw,
+			.out = buffer,
+			.decodedskip = skip,
+			.interlaced_offset =
+				map->m_algorithmformat == Z_EROFS_COMPRESSION_INTERLACED ?
+					erofs_blkoff(map->m_la) : 0,
+			.inputsize = map->m_plen,
+			.decodedlength = length,
+			.alg = map->m_algorithmformat,
+			.partial_decoding = trimmed ? true :
+				!(map->m_flags & EROFS_MAP_FULL_MAPPED) ||
+					(map->m_flags & EROFS_MAP_PARTIAL_REF),
+			 });
+	if (ret < 0)
+		return ret;
+	return 0;
+}
+
 static int z_erofs_read_data(struct erofs_inode *inode, char *buffer,
 			     erofs_off_t size, erofs_off_t offset)
 {
@@ -213,8 +278,7 @@ static int z_erofs_read_data(struct erofs_inode *inode, char *buffer,
 	struct erofs_map_blocks map = {
 		.index = UINT_MAX,
 	};
-	struct erofs_map_dev mdev;
-	bool partial;
+	bool trimmed;
 	unsigned int bufsize = 0;
 	char *raw = NULL;
 	int ret = 0;
@@ -227,27 +291,17 @@ static int z_erofs_read_data(struct erofs_inode *inode, char *buffer,
 		if (ret)
 			break;
 
-		/* no device id here, thus it will always succeed */
-		mdev = (struct erofs_map_dev) {
-			.m_pa = map.m_pa,
-		};
-		ret = erofs_map_dev(&sbi, &mdev);
-		if (ret) {
-			DBG_BUGON(1);
-			break;
-		}
-
 		/*
 		 * trim to the needed size if the returned extent is quite
 		 * larger than requested, and set up partial flag as well.
 		 */
 		if (end < map.m_la + map.m_llen) {
 			length = end - map.m_la;
-			partial = true;
+			trimmed = true;
 		} else {
 			DBG_BUGON(end != map.m_la + map.m_llen);
 			length = map.m_llen;
-			partial = !(map.m_flags & EROFS_MAP_FULL_MAPPED);
+			trimmed = false;
 		}
 
 		if (map.m_la < offset) {
@@ -272,19 +326,10 @@ static int z_erofs_read_data(struct erofs_inode *inode, char *buffer,
 				break;
 			}
 		}
-		ret = erofs_dev_read(mdev.m_deviceid, raw, mdev.m_pa, map.m_plen);
-		if (ret < 0)
-			break;
 
-		ret = z_erofs_decompress(&(struct z_erofs_decompress_req) {
-					.in = raw,
-					.out = buffer + end - offset,
-					.decodedskip = skip,
-					.inputsize = map.m_plen,
-					.decodedlength = length,
-					.alg = map.m_algorithmformat,
-					.partial_decoding = partial
-					 });
+		ret = z_erofs_read_one_data(inode, &map, raw,
+					    buffer + end - offset, skip, length,
+					    trimmed);
 		if (ret < 0)
 			break;
 	}
@@ -301,8 +346,8 @@ int erofs_pread(struct erofs_inode *inode, char *buf,
 	case EROFS_INODE_FLAT_INLINE:
 	case EROFS_INODE_CHUNK_BASED:
 		return erofs_read_raw_data(inode, buf, count, offset);
-	case EROFS_INODE_FLAT_COMPRESSION_LEGACY:
-	case EROFS_INODE_FLAT_COMPRESSION:
+	case EROFS_INODE_COMPRESSED_FULL:
+	case EROFS_INODE_COMPRESSED_COMPACT:
 		return z_erofs_read_data(inode, buf, count, offset);
 	default:
 		break;
diff --git a/fs/erofs/decompress.c b/fs/erofs/decompress.c
index 2be3b844cf..e04e5c34a8 100644
--- a/fs/erofs/decompress.c
+++ b/fs/erofs/decompress.c
@@ -15,8 +15,8 @@ static int z_erofs_decompress_lz4(struct z_erofs_decompress_req *rq)
 	if (erofs_sb_has_lz4_0padding()) {
 		support_0padding = true;
 
-		while (!src[inputmargin & ~PAGE_MASK])
-			if (!(++inputmargin & ~PAGE_MASK))
+		while (!src[inputmargin & (erofs_blksiz() - 1)])
+			if (!(++inputmargin & (erofs_blksiz() - 1)))
 				break;
 
 		if (inputmargin >= rq->inputsize)
@@ -40,6 +40,9 @@ static int z_erofs_decompress_lz4(struct z_erofs_decompress_req *rq)
 					  rq->decodedlength);
 
 	if (ret != (int)rq->decodedlength) {
+		erofs_err("failed to %s decompress %d in[%u, %u] out[%u]",
+			  rq->partial_decoding ? "partial" : "full",
+			  ret, rq->inputsize, inputmargin, rq->decodedlength);
 		ret = -EIO;
 		goto out;
 	}
@@ -58,13 +61,30 @@ out:
 
 int z_erofs_decompress(struct z_erofs_decompress_req *rq)
 {
-	if (rq->alg == Z_EROFS_COMPRESSION_SHIFTED) {
-		if (rq->inputsize != EROFS_BLKSIZ)
+	if (rq->alg == Z_EROFS_COMPRESSION_INTERLACED) {
+		unsigned int count, rightpart, skip;
+
+		/* XXX: should support inputsize >= erofs_blksiz() later */
+		if (rq->inputsize > erofs_blksiz())
 			return -EFSCORRUPTED;
 
-		DBG_BUGON(rq->decodedlength > EROFS_BLKSIZ);
-		DBG_BUGON(rq->decodedlength < rq->decodedskip);
+		if (rq->decodedlength > erofs_blksiz())
+			return -EFSCORRUPTED;
+
+		if (rq->decodedlength < rq->decodedskip)
+			return -EFSCORRUPTED;
 
+		count = rq->decodedlength - rq->decodedskip;
+		skip = erofs_blkoff(rq->interlaced_offset + rq->decodedskip);
+		rightpart = min(erofs_blksiz() - skip, count);
+		memcpy(rq->out, rq->in + skip, rightpart);
+		memcpy(rq->out + rightpart, rq->in, count - rightpart);
+		return 0;
+	} else if (rq->alg == Z_EROFS_COMPRESSION_SHIFTED) {
+		if (rq->decodedlength > rq->inputsize)
+			return -EFSCORRUPTED;
+
+		DBG_BUGON(rq->decodedlength < rq->decodedskip);
 		memcpy(rq->out, rq->in + rq->decodedskip,
 		       rq->decodedlength - rq->decodedskip);
 		return 0;
diff --git a/fs/erofs/decompress.h b/fs/erofs/decompress.h
index 81d5fb84f6..4752f77950 100644
--- a/fs/erofs/decompress.h
+++ b/fs/erofs/decompress.h
@@ -14,6 +14,9 @@ struct z_erofs_decompress_req {
 	unsigned int decodedskip;
 	unsigned int inputsize, decodedlength;
 
+	/* cut point of interlaced uncompressed data */
+	unsigned int interlaced_offset;
+
 	/* indicate the algorithm will be used for decompression */
 	unsigned int alg;
 	bool partial_decoding;
diff --git a/fs/erofs/erofs_fs.h b/fs/erofs/erofs_fs.h
index 6b62c7a4f5..158e2c68a1 100644
--- a/fs/erofs/erofs_fs.h
+++ b/fs/erofs/erofs_fs.h
@@ -3,7 +3,7 @@
  * EROFS (Enhanced ROM File System) on-disk format definition
  *
  * Copyright (C) 2017-2018 HUAWEI, Inc.
- *             http://www.huawei.com/
+ *             https://www.huawei.com/
  * Copyright (C) 2021, Alibaba Cloud
  */
 #ifndef __EROFS_FS_H
@@ -18,33 +18,41 @@
 #define EROFS_SUPER_MAGIC_V1    0xE0F5E1E2
 #define EROFS_SUPER_OFFSET      1024
 
-#define EROFS_FEATURE_COMPAT_SB_CHKSUM		0x00000001
+#define EROFS_FEATURE_COMPAT_SB_CHKSUM          0x00000001
+#define EROFS_FEATURE_COMPAT_MTIME              0x00000002
 
 /*
  * Any bits that aren't in EROFS_ALL_FEATURE_INCOMPAT should
  * be incompatible with this kernel version.
  */
-#define EROFS_FEATURE_INCOMPAT_LZ4_0PADDING	0x00000001
+#define EROFS_FEATURE_INCOMPAT_ZERO_PADDING	0x00000001
 #define EROFS_FEATURE_INCOMPAT_COMPR_CFGS	0x00000002
 #define EROFS_FEATURE_INCOMPAT_BIG_PCLUSTER	0x00000002
 #define EROFS_FEATURE_INCOMPAT_CHUNKED_FILE	0x00000004
 #define EROFS_FEATURE_INCOMPAT_DEVICE_TABLE	0x00000008
+#define EROFS_FEATURE_INCOMPAT_COMPR_HEAD2	0x00000008
+#define EROFS_FEATURE_INCOMPAT_ZTAILPACKING	0x00000010
+#define EROFS_FEATURE_INCOMPAT_FRAGMENTS	0x00000020
+#define EROFS_FEATURE_INCOMPAT_DEDUPE		0x00000020
+#define EROFS_FEATURE_INCOMPAT_XATTR_PREFIXES	0x00000040
 #define EROFS_ALL_FEATURE_INCOMPAT		\
-	(EROFS_FEATURE_INCOMPAT_LZ4_0PADDING | \
+	(EROFS_FEATURE_INCOMPAT_ZERO_PADDING | \
 	 EROFS_FEATURE_INCOMPAT_COMPR_CFGS | \
 	 EROFS_FEATURE_INCOMPAT_BIG_PCLUSTER | \
 	 EROFS_FEATURE_INCOMPAT_CHUNKED_FILE | \
-	 EROFS_FEATURE_INCOMPAT_DEVICE_TABLE)
+	 EROFS_FEATURE_INCOMPAT_DEVICE_TABLE | \
+	 EROFS_FEATURE_INCOMPAT_COMPR_HEAD2 | \
+	 EROFS_FEATURE_INCOMPAT_ZTAILPACKING | \
+	 EROFS_FEATURE_INCOMPAT_FRAGMENTS | \
+	 EROFS_FEATURE_INCOMPAT_DEDUPE | \
+	 EROFS_FEATURE_INCOMPAT_XATTR_PREFIXES)
 
 #define EROFS_SB_EXTSLOT_SIZE	16
 
 struct erofs_deviceslot {
-	union {
-		u8 uuid[16];		/* used for device manager later */
-		u8 userdata[64];	/* digest(sha256), etc. */
-	} u;
-	__le32 blocks;			/* total fs blocks of this device */
-	__le32 mapped_blkaddr;		/* map starting at mapped_blkaddr */
+	u8 tag[64];		/* digest(sha256), etc. */
+	__le32 blocks;		/* total fs blocks of this device */
+	__le32 mapped_blkaddr;	/* map starting at mapped_blkaddr */
 	u8 reserved[56];
 };
 
@@ -55,14 +63,14 @@ struct erofs_super_block {
 	__le32 magic;           /* file system magic number */
 	__le32 checksum;        /* crc32c(super_block) */
 	__le32 feature_compat;
-	__u8 blkszbits;         /* support block_size == PAGE_SIZE only */
+	__u8 blkszbits;         /* filesystem block size in bit shift */
 	__u8 sb_extslots;	/* superblock size = 128 + sb_extslots * 16 */
 
 	__le16 root_nid;	/* nid of root directory */
 	__le64 inos;            /* total valid ino # (== f_files - f_favail) */
 
-	__le64 build_time;      /* inode v1 time derivation */
-	__le32 build_time_nsec;	/* inode v1 time derivation in nano scale */
+	__le64 build_time;      /* compact inode time derivation */
+	__le32 build_time_nsec;	/* compact inode time derivation in ns scale */
 	__le32 blocks;          /* used for statfs */
 	__le32 meta_blkaddr;	/* start block address of metadata area */
 	__le32 xattr_blkaddr;	/* start block address of shared xattr area */
@@ -77,39 +85,38 @@ struct erofs_super_block {
 	} __packed u1;
 	__le16 extra_devices;	/* # of devices besides the primary device */
 	__le16 devt_slotoff;	/* startoff = devt_slotoff * devt_slotsize */
-	__u8 reserved2[38];
+	__u8 dirblkbits;	/* directory block size in bit shift */
+	__u8 xattr_prefix_count;	/* # of long xattr name prefixes */
+	__le32 xattr_prefix_start;	/* start of long xattr prefixes */
+	__le64 packed_nid;	/* nid of the special packed inode */
+	__u8 reserved2[24];
 };
 
 /*
- * erofs inode datalayout (i_format in on-disk inode):
- * 0 - inode plain without inline data A:
- * inode, [xattrs], ... | ... | no-holed data
- * 1 - inode VLE compression B (legacy):
- * inode, [xattrs], extents ... | ...
- * 2 - inode plain with inline data C:
- * inode, [xattrs], last_inline_data, ... | ... | no-holed data
- * 3 - inode compression D:
- * inode, [xattrs], map_header, extents ... | ...
- * 4 - inode chunk-based E:
- * inode, [xattrs], chunk indexes ... | ...
+ * EROFS inode datalayout (i_format in on-disk inode):
+ * 0 - uncompressed flat inode without tail-packing inline data:
+ * 1 - compressed inode with non-compact indexes:
+ * 2 - uncompressed flat inode with tail-packing inline data:
+ * 3 - compressed inode with compact indexes:
+ * 4 - chunk-based inode with (optional) multi-device support:
  * 5~7 - reserved
  */
 enum {
 	EROFS_INODE_FLAT_PLAIN			= 0,
-	EROFS_INODE_FLAT_COMPRESSION_LEGACY	= 1,
+	EROFS_INODE_COMPRESSED_FULL		= 1,
 	EROFS_INODE_FLAT_INLINE			= 2,
-	EROFS_INODE_FLAT_COMPRESSION		= 3,
+	EROFS_INODE_COMPRESSED_COMPACT		= 3,
 	EROFS_INODE_CHUNK_BASED			= 4,
 	EROFS_INODE_DATALAYOUT_MAX
 };
 
 static inline bool erofs_inode_is_data_compressed(unsigned int datamode)
 {
-	return datamode == EROFS_INODE_FLAT_COMPRESSION ||
-		datamode == EROFS_INODE_FLAT_COMPRESSION_LEGACY;
+	return datamode == EROFS_INODE_COMPRESSED_COMPACT ||
+		datamode == EROFS_INODE_COMPRESSED_FULL;
 }
 
-/* bit definitions of inode i_advise */
+/* bit definitions of inode i_format */
 #define EROFS_I_VERSION_BITS            1
 #define EROFS_I_DATALAYOUT_BITS         3
 
@@ -127,11 +134,30 @@ static inline bool erofs_inode_is_data_compressed(unsigned int datamode)
 #define EROFS_CHUNK_FORMAT_ALL	\
 	(EROFS_CHUNK_FORMAT_BLKBITS_MASK | EROFS_CHUNK_FORMAT_INDEXES)
 
+/* 32-byte on-disk inode */
+#define EROFS_INODE_LAYOUT_COMPACT	0
+/* 64-byte on-disk inode */
+#define EROFS_INODE_LAYOUT_EXTENDED	1
+
 struct erofs_inode_chunk_info {
 	__le16 format;		/* chunk blkbits, etc. */
 	__le16 reserved;
 };
 
+union erofs_inode_i_u {
+	/* total compressed blocks for compressed inodes */
+	__le32 compressed_blocks;
+
+	/* block address for uncompressed flat inodes */
+	__le32 raw_blkaddr;
+
+	/* for device files, used to indicate old/new device # */
+	__le32 rdev;
+
+	/* for chunk-based files, it contains the summary info */
+	struct erofs_inode_chunk_info c;
+};
+
 /* 32-byte reduced form of an ondisk inode */
 struct erofs_inode_compact {
 	__le16 i_format;	/* inode format hints */
@@ -142,28 +168,14 @@ struct erofs_inode_compact {
 	__le16 i_nlink;
 	__le32 i_size;
 	__le32 i_reserved;
-	union {
-		/* file total compressed blocks for data mapping 1 */
-		__le32 compressed_blocks;
-		__le32 raw_blkaddr;
+	union erofs_inode_i_u i_u;
 
-		/* for device files, used to indicate old/new device # */
-		__le32 rdev;
-
-		/* for chunk-based files, it contains the summary info */
-		struct erofs_inode_chunk_info c;
-	} i_u;
-	__le32 i_ino;           /* only used for 32-bit stat compatibility */
+	__le32 i_ino;		/* only used for 32-bit stat compatibility */
 	__le16 i_uid;
 	__le16 i_gid;
 	__le32 i_reserved2;
 };
 
-/* 32 bytes on-disk inode */
-#define EROFS_INODE_LAYOUT_COMPACT	0
-/* 64 bytes on-disk inode */
-#define EROFS_INODE_LAYOUT_EXTENDED	1
-
 /* 64-byte complete form of an ondisk inode */
 struct erofs_inode_extended {
 	__le16 i_format;	/* inode format hints */
@@ -173,33 +185,17 @@ struct erofs_inode_extended {
 	__le16 i_mode;
 	__le16 i_reserved;
 	__le64 i_size;
-	union {
-		/* file total compressed blocks for data mapping 1 */
-		__le32 compressed_blocks;
-		__le32 raw_blkaddr;
-
-		/* for device files, used to indicate old/new device # */
-		__le32 rdev;
-
-		/* for chunk-based files, it contains the summary info */
-		struct erofs_inode_chunk_info c;
-	} i_u;
-
-	/* only used for 32-bit stat compatibility */
-	__le32 i_ino;
+	union erofs_inode_i_u i_u;
 
+	__le32 i_ino;		/* only used for 32-bit stat compatibility */
 	__le32 i_uid;
 	__le32 i_gid;
-	__le64 i_ctime;
-	__le32 i_ctime_nsec;
+	__le64 i_mtime;
+	__le32 i_mtime_nsec;
 	__le32 i_nlink;
 	__u8   i_reserved2[16];
 };
 
-#define EROFS_MAX_SHARED_XATTRS         (128)
-/* h_shared_count between 129 ... 255 are special # */
-#define EROFS_SHARED_XATTR_EXTENT       (255)
-
 /*
  * inline xattrs (n == i_xattr_icount):
  * erofs_xattr_ibody_header(1) + (n - 1) * 4 bytes
@@ -226,6 +222,13 @@ struct erofs_xattr_ibody_header {
 #define EROFS_XATTR_INDEX_LUSTRE            5
 #define EROFS_XATTR_INDEX_SECURITY          6
 
+/*
+ * bit 7 of e_name_index is set when it refers to a long xattr name prefix,
+ * while the remained lower bits represent the index of the prefix.
+ */
+#define EROFS_XATTR_LONG_PREFIX		0x80
+#define EROFS_XATTR_LONG_PREFIX_MASK	0x7f
+
 /* xattr entry (for both inline & shared xattrs) */
 struct erofs_xattr_entry {
 	__u8   e_name_len;      /* length of name */
@@ -235,6 +238,12 @@ struct erofs_xattr_entry {
 	char   e_name[0];       /* attribute name */
 };
 
+/* long xattr name prefix */
+struct erofs_xattr_long_prefix {
+	__u8   base_index;	/* short xattr name prefix index */
+	char   infix[0];	/* infix apart from short prefix */
+};
+
 static inline unsigned int erofs_xattr_ibody_size(__le16 i_xattr_icount)
 {
 	if (!i_xattr_icount)
@@ -265,6 +274,29 @@ struct erofs_inode_chunk_index {
 	__le32 blkaddr;		/* start block address of this inode chunk */
 };
 
+/* dirent sorts in alphabet order, thus we can do binary search */
+struct erofs_dirent {
+	__le64 nid;     /* node number */
+	__le16 nameoff; /* start offset of file name */
+	__u8 file_type; /* file type */
+	__u8 reserved;  /* reserved */
+} __packed;
+
+/* file types used in inode_info->flags */
+enum {
+	EROFS_FT_UNKNOWN,
+	EROFS_FT_REG_FILE,
+	EROFS_FT_DIR,
+	EROFS_FT_CHRDEV,
+	EROFS_FT_BLKDEV,
+	EROFS_FT_FIFO,
+	EROFS_FT_SOCK,
+	EROFS_FT_SYMLINK,
+	EROFS_FT_MAX
+};
+
+#define EROFS_NAME_LEN      255
+
 /* maximum supported size of a physical compression cluster */
 #define Z_EROFS_PCLUSTER_MAX_SIZE	(1024 * 1024)
 
@@ -275,7 +307,7 @@ enum {
 	Z_EROFS_COMPRESSION_MAX
 };
 
-#define Z_EROFS_ALL_COMPR_ALGS		(1 << (Z_EROFS_COMPRESSION_MAX - 1))
+#define Z_EROFS_ALL_COMPR_ALGS		((1 << Z_EROFS_COMPRESSION_MAX) - 1)
 
 /* 14 bytes (+ length field = 16 bytes) */
 struct z_erofs_lz4_cfgs {
@@ -290,6 +322,7 @@ struct z_erofs_lzma_cfgs {
 	__le16 format;
 	u8 reserved[8];
 } __packed;
+
 #define Z_EROFS_LZMA_MAX_DICT_SIZE	(8 * Z_EROFS_PCLUSTER_MAX_SIZE)
 
 /*
@@ -298,13 +331,28 @@ struct z_erofs_lzma_cfgs {
  *                                  (4B) + 2B + (4B) if compacted 2B is on.
  * bit 1 : HEAD1 big pcluster (0 - off; 1 - on)
  * bit 2 : HEAD2 big pcluster (0 - off; 1 - on)
+ * bit 3 : tailpacking inline pcluster (0 - off; 1 - on)
+ * bit 4 : interlaced plain pcluster (0 - off; 1 - on)
+ * bit 5 : fragment pcluster (0 - off; 1 - on)
  */
 #define Z_EROFS_ADVISE_COMPACTED_2B		0x0001
 #define Z_EROFS_ADVISE_BIG_PCLUSTER_1		0x0002
 #define Z_EROFS_ADVISE_BIG_PCLUSTER_2		0x0004
+#define Z_EROFS_ADVISE_INLINE_PCLUSTER		0x0008
+#define Z_EROFS_ADVISE_INTERLACED_PCLUSTER	0x0010
+#define Z_EROFS_ADVISE_FRAGMENT_PCLUSTER	0x0020
 
+#define Z_EROFS_FRAGMENT_INODE_BIT              7
 struct z_erofs_map_header {
-	__le32	h_reserved1;
+	union {
+		/* fragment data offset in the packed inode */
+		__le32  h_fragmentoff;
+		struct {
+			__le16  h_reserved1;
+			/* indicates the encoded size of tailpacking data */
+			__le16  h_idata_size;
+		};
+	};
 	__le16	h_advise;
 	/*
 	 * bit 0-3 : algorithm type of head 1 (logical cluster type 01);
@@ -313,107 +361,85 @@ struct z_erofs_map_header {
 	__u8	h_algorithmtype;
 	/*
 	 * bit 0-2 : logical cluster bits - 12, e.g. 0 for 4096;
-	 * bit 3-7 : reserved.
+	 * bit 3-6 : reserved;
+	 * bit 7   : move the whole file into packed inode or not.
 	 */
 	__u8	h_clusterbits;
 };
 
-#define Z_EROFS_VLE_LEGACY_HEADER_PADDING       8
-
 /*
- * Fixed-sized output compression ondisk Logical Extent cluster type:
- *    0 - literal (uncompressed) cluster
- *    1 - compressed cluster (for the head logical cluster)
- *    2 - compressed cluster (for the other logical clusters)
+ * On-disk logical cluster type:
+ *    0   - literal (uncompressed) lcluster
+ *    1,3 - compressed lcluster (for HEAD lclusters)
+ *    2   - compressed lcluster (for NONHEAD lclusters)
  *
  * In detail,
- *    0 - literal (uncompressed) cluster,
+ *    0 - literal (uncompressed) lcluster,
  *        di_advise = 0
- *        di_clusterofs = the literal data offset of the cluster
- *        di_blkaddr = the blkaddr of the literal cluster
+ *        di_clusterofs = the literal data offset of the lcluster
+ *        di_blkaddr = the blkaddr of the literal pcluster
  *
- *    1 - compressed cluster (for the head logical cluster)
- *        di_advise = 1
- *        di_clusterofs = the decompressed data offset of the cluster
- *        di_blkaddr = the blkaddr of the compressed cluster
+ *    1,3 - compressed lcluster (for HEAD lclusters)
+ *        di_advise = 1 or 3
+ *        di_clusterofs = the decompressed data offset of the lcluster
+ *        di_blkaddr = the blkaddr of the compressed pcluster
  *
- *    2 - compressed cluster (for the other logical clusters)
+ *    2 - compressed lcluster (for NONHEAD lclusters)
  *        di_advise = 2
  *        di_clusterofs =
- *           the decompressed data offset in its own head cluster
- *        di_u.delta[0] = distance to its corresponding head cluster
- *        di_u.delta[1] = distance to its corresponding tail cluster
- *                (di_advise could be 0, 1 or 2)
+ *           the decompressed data offset in its own HEAD lcluster
+ *        di_u.delta[0] = distance to this HEAD lcluster
+ *        di_u.delta[1] = distance to the next HEAD lcluster
  */
 enum {
-	Z_EROFS_VLE_CLUSTER_TYPE_PLAIN		= 0,
-	Z_EROFS_VLE_CLUSTER_TYPE_HEAD		= 1,
-	Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD	= 2,
-	Z_EROFS_VLE_CLUSTER_TYPE_RESERVED	= 3,
-	Z_EROFS_VLE_CLUSTER_TYPE_MAX
+	Z_EROFS_LCLUSTER_TYPE_PLAIN	= 0,
+	Z_EROFS_LCLUSTER_TYPE_HEAD1	= 1,
+	Z_EROFS_LCLUSTER_TYPE_NONHEAD	= 2,
+	Z_EROFS_LCLUSTER_TYPE_HEAD2	= 3,
+	Z_EROFS_LCLUSTER_TYPE_MAX
 };
 
-#define Z_EROFS_VLE_DI_CLUSTER_TYPE_BITS        2
-#define Z_EROFS_VLE_DI_CLUSTER_TYPE_BIT         0
+#define Z_EROFS_LI_LCLUSTER_TYPE_BITS        2
+#define Z_EROFS_LI_LCLUSTER_TYPE_BIT         0
+
+/* (noncompact only, HEAD) This pcluster refers to partial decompressed data */
+#define Z_EROFS_LI_PARTIAL_REF		(1 << 15)
 
 /*
  * D0_CBLKCNT will be marked _only_ at the 1st non-head lcluster to store the
  * compressed block count of a compressed extent (in logical clusters, aka.
  * block count of a pcluster).
  */
-#define Z_EROFS_VLE_DI_D0_CBLKCNT		(1 << 11)
+#define Z_EROFS_LI_D0_CBLKCNT		(1 << 11)
 
-struct z_erofs_vle_decompressed_index {
+struct z_erofs_lcluster_index {
 	__le16 di_advise;
-	/* where to decompress in the head cluster */
+	/* where to decompress in the head lcluster */
 	__le16 di_clusterofs;
 
 	union {
-		/* for the head cluster */
+		/* for the HEAD lclusters */
 		__le32 blkaddr;
 		/*
-		 * for the rest clusters
-		 * eg. for 4k page-sized cluster, maximum 4K*64k = 256M)
-		 * [0] - pointing to the head cluster
-		 * [1] - pointing to the tail cluster
+		 * for the NONHEAD lclusters
+		 * [0] - distance to its HEAD lcluster
+		 * [1] - distance to the next HEAD lcluster
 		 */
 		__le16 delta[2];
 	} di_u;
 };
 
-#define Z_EROFS_VLE_LEGACY_INDEX_ALIGN(size) \
-	(round_up(size, sizeof(struct z_erofs_vle_decompressed_index)) + \
-	 sizeof(struct z_erofs_map_header) + Z_EROFS_VLE_LEGACY_HEADER_PADDING)
-
-#define Z_EROFS_VLE_EXTENT_ALIGN(size) round_up(size, \
-	sizeof(struct z_erofs_vle_decompressed_index))
-
-/* dirent sorts in alphabet order, thus we can do binary search */
-struct erofs_dirent {
-	__le64 nid;     /* node number */
-	__le16 nameoff; /* start offset of file name */
-	__u8 file_type; /* file type */
-	__u8 reserved;  /* reserved */
-} __packed;
-
-/* file types used in inode_info->flags */
-enum {
-	EROFS_FT_UNKNOWN,
-	EROFS_FT_REG_FILE,
-	EROFS_FT_DIR,
-	EROFS_FT_CHRDEV,
-	EROFS_FT_BLKDEV,
-	EROFS_FT_FIFO,
-	EROFS_FT_SOCK,
-	EROFS_FT_SYMLINK,
-	EROFS_FT_MAX
-};
-
-#define EROFS_NAME_LEN      255
+#define Z_EROFS_FULL_INDEX_ALIGN(end)	\
+	(round_up(end, 8) + sizeof(struct z_erofs_map_header) + 8)
 
 /* check the EROFS on-disk layout strictly at compile time */
 static inline void erofs_check_ondisk_layout_definitions(void)
 {
+	const __le64 fmh __maybe_unused =
+		*(__le64 *)&(struct z_erofs_map_header) {
+			.h_clusterbits = 1 << Z_EROFS_FRAGMENT_INODE_BIT
+		};
+
 	BUILD_BUG_ON(sizeof(struct erofs_super_block) != 128);
 	BUILD_BUG_ON(sizeof(struct erofs_inode_compact) != 32);
 	BUILD_BUG_ON(sizeof(struct erofs_inode_extended) != 64);
@@ -422,15 +448,18 @@ static inline void erofs_check_ondisk_layout_definitions(void)
 	BUILD_BUG_ON(sizeof(struct erofs_inode_chunk_info) != 4);
 	BUILD_BUG_ON(sizeof(struct erofs_inode_chunk_index) != 8);
 	BUILD_BUG_ON(sizeof(struct z_erofs_map_header) != 8);
-	BUILD_BUG_ON(sizeof(struct z_erofs_vle_decompressed_index) != 8);
+	BUILD_BUG_ON(sizeof(struct z_erofs_lcluster_index) != 8);
 	BUILD_BUG_ON(sizeof(struct erofs_dirent) != 12);
 	/* keep in sync between 2 index structures for better extendibility */
 	BUILD_BUG_ON(sizeof(struct erofs_inode_chunk_index) !=
-		     sizeof(struct z_erofs_vle_decompressed_index));
+		     sizeof(struct z_erofs_lcluster_index));
 	BUILD_BUG_ON(sizeof(struct erofs_deviceslot) != 128);
 
-	BUILD_BUG_ON(BIT(Z_EROFS_VLE_DI_CLUSTER_TYPE_BITS) <
-		     Z_EROFS_VLE_CLUSTER_TYPE_MAX - 1);
+	BUILD_BUG_ON(BIT(Z_EROFS_LI_LCLUSTER_TYPE_BITS) <
+		     Z_EROFS_LCLUSTER_TYPE_MAX - 1);
+	/* exclude old compiler versions like gcc 7.5.0 */
+	BUILD_BUG_ON(__builtin_constant_p(fmh) ?
+		     fmh != cpu_to_le64(1ULL << 63) : 0);
 }
 
 #endif
diff --git a/fs/erofs/fs.c b/fs/erofs/fs.c
index 89269750f8..7bd2e8fcfc 100644
--- a/fs/erofs/fs.c
+++ b/fs/erofs/fs.c
@@ -25,8 +25,8 @@ int erofs_dev_read(int device_id, void *buf, u64 offset, size_t len)
 
 int erofs_blk_read(void *buf, erofs_blk_t start, u32 nblocks)
 {
-	return erofs_dev_read(0, buf, blknr_to_addr(start),
-			 blknr_to_addr(nblocks));
+	return erofs_dev_read(0, buf, erofs_pos(start),
+			 erofs_pos(nblocks));
 }
 
 int erofs_probe(struct blk_desc *fs_dev_desc,
@@ -52,7 +52,7 @@ struct erofs_dir_stream {
 	struct fs_dirent dirent;
 
 	struct erofs_inode inode;
-	char dblk[EROFS_BLKSIZ];
+	char dblk[EROFS_MAX_BLOCK_SIZE];
 	unsigned int maxsize, de_end;
 	erofs_off_t pos;
 };
@@ -125,7 +125,7 @@ int erofs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
 		return 1;
 
 	if (!dirs->maxsize) {
-		dirs->maxsize = min_t(unsigned int, EROFS_BLKSIZ,
+		dirs->maxsize = min_t(unsigned int, EROFS_MAX_BLOCK_SIZE,
 				      dirs->inode.i_size - pos);
 
 		err = erofs_pread(&dirs->inode, dirs->dblk,
@@ -136,7 +136,7 @@ int erofs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
 		de = (struct erofs_dirent *)dirs->dblk;
 		dirs->de_end = le16_to_cpu(de->nameoff);
 		if (dirs->de_end < sizeof(struct erofs_dirent) ||
-		    dirs->de_end >= EROFS_BLKSIZ) {
+		    dirs->de_end >= EROFS_MAX_BLOCK_SIZE) {
 			erofs_err("invalid de[0].nameoff %u @ nid %llu",
 				  dirs->de_end, de->nid | 0ULL);
 			return -EFSCORRUPTED;
@@ -183,7 +183,7 @@ int erofs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
 
 	pos += sizeof(*de);
 	if (erofs_blkoff(pos) >= dirs->de_end) {
-		pos = blknr_to_addr(erofs_blknr(pos) + 1);
+		pos = erofs_pos(erofs_blknr(pos) + 1);
 		dirs->maxsize = 0;
 	}
 	dirs->pos = pos;
diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h
index 4af7c91560..1875f37fcd 100644
--- a/fs/erofs/internal.h
+++ b/fs/erofs/internal.h
@@ -2,6 +2,7 @@
 #ifndef __EROFS_INTERNAL_H
 #define __EROFS_INTERNAL_H
 
+#include "linux/compat.h"
 #define __packed __attribute__((__packed__))
 
 #include <linux/stat.h>
@@ -30,8 +31,9 @@
 
 #define PAGE_MASK		(~(PAGE_SIZE - 1))
 
-#define LOG_BLOCK_SIZE          (12)
-#define EROFS_BLKSIZ            (1U << LOG_BLOCK_SIZE)
+#ifndef EROFS_MAX_BLOCK_SIZE
+#define EROFS_MAX_BLOCK_SIZE	PAGE_SIZE
+#endif
 
 #define EROFS_ISLOTBITS		5
 #define EROFS_SLOTSIZE		(1U << EROFS_ISLOTBITS)
@@ -44,11 +46,15 @@ typedef u32 erofs_blk_t;
 #define NULL_ADDR	((unsigned int)-1)
 #define NULL_ADDR_UL	((unsigned long)-1)
 
-#define erofs_blknr(addr)       ((addr) / EROFS_BLKSIZ)
-#define erofs_blkoff(addr)      ((addr) % EROFS_BLKSIZ)
-#define blknr_to_addr(nr)       ((erofs_off_t)(nr) * EROFS_BLKSIZ)
+/* global sbi */
+extern struct erofs_sb_info sbi;
+
+#define erofs_blksiz()		(1u << sbi.blkszbits)
+#define erofs_blknr(addr)       ((addr) >> sbi.blkszbits)
+#define erofs_blkoff(addr)      ((addr) & (erofs_blksiz() - 1))
+#define erofs_pos(nr)           ((erofs_off_t)(nr) << sbi.blkszbits)
 
-#define BLK_ROUND_UP(addr)	DIV_ROUND_UP(addr, EROFS_BLKSIZ)
+#define BLK_ROUND_UP(addr)	DIV_ROUND_UP(addr, 1u << sbi.blkszbits)
 
 struct erofs_buffer_head;
 
@@ -57,6 +63,8 @@ struct erofs_device_info {
 	u32 mapped_blkaddr;
 };
 
+#define EROFS_PACKED_NID_UNALLOCATED	-1
+
 struct erofs_sb_info {
 	struct erofs_device_info *devs;
 
@@ -72,6 +80,7 @@ struct erofs_sb_info {
 	u32 build_time_nsec;
 
 	unsigned char islotbits;
+	unsigned char blkszbits;
 
 	/* what we really care is nid, rather than ino.. */
 	erofs_nid_t root_nid;
@@ -79,23 +88,26 @@ struct erofs_sb_info {
 	u64 inos;
 
 	u8 uuid[16];
+	char volume_name[16];
 
 	u16 available_compr_algs;
 	u16 lz4_max_distance;
+
 	u32 checksum;
 	u16 extra_devices;
 	union {
 		u16 devt_slotoff;		/* used for mkfs */
 		u16 device_id_mask;		/* used for others */
 	};
-};
+	erofs_nid_t packed_nid;
 
-/* global sbi */
-extern struct erofs_sb_info sbi;
+	u32 xattr_prefix_start;
+	u8 xattr_prefix_count;
+};
 
 static inline erofs_off_t iloc(erofs_nid_t nid)
 {
-	return blknr_to_addr(sbi.meta_blkaddr) + (nid << sbi.islotbits);
+	return erofs_pos(sbi.meta_blkaddr) + (nid << sbi.islotbits);
 }
 
 #define EROFS_FEATURE_FUNCS(name, compat, feature) \
@@ -112,11 +124,15 @@ static inline void erofs_sb_clear_##name(void) \
 	sbi.feature_##compat &= ~EROFS_FEATURE_##feature; \
 }
 
-EROFS_FEATURE_FUNCS(lz4_0padding, incompat, INCOMPAT_LZ4_0PADDING)
+EROFS_FEATURE_FUNCS(lz4_0padding, incompat, INCOMPAT_ZERO_PADDING)
 EROFS_FEATURE_FUNCS(compr_cfgs, incompat, INCOMPAT_COMPR_CFGS)
 EROFS_FEATURE_FUNCS(big_pcluster, incompat, INCOMPAT_BIG_PCLUSTER)
 EROFS_FEATURE_FUNCS(chunked_file, incompat, INCOMPAT_CHUNKED_FILE)
 EROFS_FEATURE_FUNCS(device_table, incompat, INCOMPAT_DEVICE_TABLE)
+EROFS_FEATURE_FUNCS(ztailpacking, incompat, INCOMPAT_ZTAILPACKING)
+EROFS_FEATURE_FUNCS(fragments, incompat, INCOMPAT_FRAGMENTS)
+EROFS_FEATURE_FUNCS(dedupe, incompat, INCOMPAT_DEDUPE)
+EROFS_FEATURE_FUNCS(xattr_prefixes, incompat, INCOMPAT_XATTR_PREFIXES)
 EROFS_FEATURE_FUNCS(sb_chksum, compat, COMPAT_SB_CHKSUM)
 
 #define EROFS_I_EA_INITED	(1 << 0)
@@ -130,6 +146,8 @@ struct erofs_inode {
 		unsigned int flags;
 		/* (mkfs.erofs) device ID containing source file */
 		u32 dev;
+		/* (mkfs.erofs) queued sub-directories blocking dump */
+		u32 subdirs_queued;
 	};
 	unsigned int i_count;
 	struct erofs_inode *i_parent;
@@ -140,8 +158,8 @@ struct erofs_inode {
 	u64 i_ino[2];
 	u32 i_uid;
 	u32 i_gid;
-	u64 i_ctime;
-	u32 i_ctime_nsec;
+	u64 i_mtime;
+	u32 i_mtime_nsec;
 	u32 i_nlink;
 
 	union {
@@ -154,20 +172,31 @@ struct erofs_inode {
 		};
 	} u;
 
+	char *i_srcpath;
+
 	unsigned char datalayout;
 	unsigned char inode_isize;
 	/* inline tail-end packing size */
 	unsigned short idata_size;
+	bool compressed_idata;
+	bool lazy_tailblock;
 
 	unsigned int xattr_isize;
 	unsigned int extent_isize;
 
+	unsigned int xattr_shared_count;
+	unsigned int *xattr_shared_xattrs;
+
 	erofs_nid_t nid;
 	struct erofs_buffer_head *bh;
 	struct erofs_buffer_head *bh_inline, *bh_data;
 
 	void *idata;
 
+	/* (ztailpacking) in order to recover uncompressed EOF data */
+	void *eof_tailraw;
+	unsigned int eof_tailrawsize;
+
 	union {
 		void *compressmeta;
 		void *chunkindexes;
@@ -176,8 +205,14 @@ struct erofs_inode {
 			uint8_t  z_algorithmtype[2];
 			uint8_t  z_logical_clusterbits;
 			uint8_t  z_physical_clusterblks;
+			uint64_t z_tailextent_headlcn;
+			unsigned int    z_idataoff;
+#define z_idata_size	idata_size
 		};
 	};
+	uint64_t capabilities;
+	erofs_off_t fragmentoff;
+	unsigned int fragment_size;
 };
 
 static inline bool is_inode_layout_compression(struct erofs_inode *inode)
@@ -216,6 +251,14 @@ struct erofs_dentry {
 	};
 };
 
+static inline bool is_dot_dotdot_len(const char *name, unsigned int len)
+{
+	if (len >= 1 && name[0] != '.')
+		return false;
+
+	return len == 1 || (len == 2 && name[1] == '.');
+}
+
 static inline bool is_dot_dotdot(const char *name)
 {
 	if (name[0] != '.')
@@ -229,6 +272,8 @@ enum {
 	BH_Mapped,
 	BH_Encoded,
 	BH_FullMapped,
+	BH_Fragment,
+	BH_Partialref,
 };
 
 /* Has a disk mapping */
@@ -239,9 +284,13 @@ enum {
 #define EROFS_MAP_ENCODED	(1 << BH_Encoded)
 /* The length of extent is full */
 #define EROFS_MAP_FULL_MAPPED	(1 << BH_FullMapped)
+/* Located in the special packed inode */
+#define EROFS_MAP_FRAGMENT	(1 << BH_Fragment)
+/* The extent refers to partial decompressed data */
+#define EROFS_MAP_PARTIAL_REF	(1 << BH_Partialref)
 
 struct erofs_map_blocks {
-	char mpage[EROFS_BLKSIZ];
+	char mpage[EROFS_MAX_BLOCK_SIZE];
 
 	erofs_off_t m_pa, m_la;
 	u64 m_plen, m_llen;
@@ -257,9 +306,12 @@ struct erofs_map_blocks {
  * approach instead if possible since it's more metadata lightweight.)
  */
 #define EROFS_GET_BLOCKS_FIEMAP	0x0002
+/* Used to map tail extent for tailpacking inline or fragment pcluster */
+#define EROFS_GET_BLOCKS_FINDTAIL	0x0008
 
 enum {
 	Z_EROFS_COMPRESSION_SHIFTED = Z_EROFS_COMPRESSION_MAX,
+	Z_EROFS_COMPRESSION_INTERLACED,
 	Z_EROFS_COMPRESSION_RUNTIME_MAX
 };
 
@@ -274,6 +326,7 @@ int erofs_dev_read(int device_id, void *buf, u64 offset, size_t len);
 
 /* super.c */
 int erofs_read_superblock(void);
+void erofs_put_super(void);
 
 /* namei.c */
 int erofs_read_inode_from_disk(struct erofs_inode *vi);
@@ -283,9 +336,40 @@ int erofs_read_inode_from_disk(struct erofs_inode *vi);
 /* data.c */
 int erofs_pread(struct erofs_inode *inode, char *buf,
 		erofs_off_t count, erofs_off_t offset);
-int erofs_map_blocks(struct erofs_inode *inode,
-		     struct erofs_map_blocks *map, int flags);
-int erofs_map_dev(struct erofs_sb_info *sbi, struct erofs_map_dev *map);
+int erofs_map_blocks(struct erofs_inode *inode, struct erofs_map_blocks *map,
+		     int flags);
+int erofs_map_dev(struct erofs_map_dev *map);
+int erofs_read_one_data(struct erofs_map_blocks *map, char *buffer, u64 offset,
+			size_t len);
+int z_erofs_read_one_data(struct erofs_inode *inode,
+			  struct erofs_map_blocks *map, char *raw, char *buffer,
+			  erofs_off_t skip, erofs_off_t length, bool trimmed);
+
+static inline int erofs_get_occupied_size(const struct erofs_inode *inode,
+					  erofs_off_t *size)
+{
+	*size = 0;
+	switch (inode->datalayout) {
+	case EROFS_INODE_FLAT_INLINE:
+	case EROFS_INODE_FLAT_PLAIN:
+	case EROFS_INODE_CHUNK_BASED:
+		*size = inode->i_size;
+		break;
+	case EROFS_INODE_COMPRESSED_FULL:
+	case EROFS_INODE_COMPRESSED_COMPACT:
+		*size = inode->u.i_blocks * erofs_blksiz();
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+	return 0;
+}
+
+/* data.c */
+int erofs_getxattr(struct erofs_inode *vi, const char *name, char *buffer,
+		   size_t buffer_size);
+int erofs_listxattr(struct erofs_inode *vi, char *buffer, size_t buffer_size);
+
 /* zmap.c */
 int z_erofs_fill_inode(struct erofs_inode *vi);
 int z_erofs_map_blocks_iter(struct erofs_inode *vi,
diff --git a/fs/erofs/namei.c b/fs/erofs/namei.c
index d1d4757c50..bde995f1bf 100644
--- a/fs/erofs/namei.c
+++ b/fs/erofs/namei.c
@@ -1,6 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0+
 #include "internal.h"
 
+#define makedev(major, minor) ((dev_t)((((major) & 0xfff) << 8) | ((minor) & 0xff)))
+static dev_t erofs_new_decode_dev(u32 dev)
+{
+	const unsigned int major = (dev & 0xfff00) >> 8;
+	const unsigned int minor = (dev & 0xff) | ((dev >> 12) & 0xfff00);
+
+	return makedev(major, minor);
+}
+
 int erofs_read_inode_from_disk(struct erofs_inode *vi)
 {
 	int ret, ifmt;
@@ -26,7 +35,8 @@ int erofs_read_inode_from_disk(struct erofs_inode *vi)
 	case EROFS_INODE_LAYOUT_EXTENDED:
 		vi->inode_isize = sizeof(struct erofs_inode_extended);
 
-		ret = erofs_dev_read(0, buf + sizeof(*dic), inode_loc + sizeof(*dic),
+		ret = erofs_dev_read(0, buf + sizeof(*dic),
+				     inode_loc + sizeof(*dic),
 				     sizeof(*die) - sizeof(*dic));
 		if (ret < 0)
 			return -EIO;
@@ -43,7 +53,8 @@ int erofs_read_inode_from_disk(struct erofs_inode *vi)
 			break;
 		case S_IFCHR:
 		case S_IFBLK:
-			vi->u.i_rdev = 0;
+			vi->u.i_rdev =
+				erofs_new_decode_dev(le32_to_cpu(die->i_u.rdev));
 			break;
 		case S_IFIFO:
 		case S_IFSOCK:
@@ -57,8 +68,8 @@ int erofs_read_inode_from_disk(struct erofs_inode *vi)
 		vi->i_gid = le32_to_cpu(die->i_gid);
 		vi->i_nlink = le32_to_cpu(die->i_nlink);
 
-		vi->i_ctime = le64_to_cpu(die->i_ctime);
-		vi->i_ctime_nsec = le64_to_cpu(die->i_ctime_nsec);
+		vi->i_mtime = le64_to_cpu(die->i_mtime);
+		vi->i_mtime_nsec = le64_to_cpu(die->i_mtime_nsec);
 		vi->i_size = le64_to_cpu(die->i_size);
 		if (vi->datalayout == EROFS_INODE_CHUNK_BASED)
 			/* fill chunked inode summary info */
@@ -77,7 +88,8 @@ int erofs_read_inode_from_disk(struct erofs_inode *vi)
 			break;
 		case S_IFCHR:
 		case S_IFBLK:
-			vi->u.i_rdev = 0;
+			vi->u.i_rdev =
+				erofs_new_decode_dev(le32_to_cpu(dic->i_u.rdev));
 			break;
 		case S_IFIFO:
 		case S_IFSOCK:
@@ -91,8 +103,8 @@ int erofs_read_inode_from_disk(struct erofs_inode *vi)
 		vi->i_gid = le16_to_cpu(dic->i_gid);
 		vi->i_nlink = le16_to_cpu(dic->i_nlink);
 
-		vi->i_ctime = sbi.build_time;
-		vi->i_ctime_nsec = sbi.build_time_nsec;
+		vi->i_mtime = sbi.build_time;
+		vi->i_mtime_nsec = sbi.build_time_nsec;
 
 		vi->i_size = le32_to_cpu(dic->i_size);
 		if (vi->datalayout == EROFS_INODE_CHUNK_BASED)
@@ -111,10 +123,13 @@ int erofs_read_inode_from_disk(struct erofs_inode *vi)
 				  vi->u.chunkformat, vi->nid | 0ULL);
 			return -EOPNOTSUPP;
 		}
-		vi->u.chunkbits = LOG_BLOCK_SIZE +
+		vi->u.chunkbits = sbi.blkszbits +
 			(vi->u.chunkformat & EROFS_CHUNK_FORMAT_BLKBITS_MASK);
-	} else if (erofs_inode_is_data_compressed(vi->datalayout))
-		z_erofs_fill_inode(vi);
+	} else if (erofs_inode_is_data_compressed(vi->datalayout)) {
+		if (erofs_blksiz() != EROFS_MAX_BLOCK_SIZE)
+			return -EOPNOTSUPP;
+		return z_erofs_fill_inode(vi);
+	}
 	return 0;
 bogusimode:
 	erofs_err("bogus i_mode (%o) @ nid %llu", vi->i_mode, vi->nid | 0ULL);
@@ -163,12 +178,11 @@ struct nameidata {
 	unsigned int	ftype;
 };
 
-int erofs_namei(struct nameidata *nd,
-		const char *name, unsigned int len)
+int erofs_namei(struct nameidata *nd, const char *name, unsigned int len)
 {
 	erofs_nid_t nid = nd->nid;
 	int ret;
-	char buf[EROFS_BLKSIZ];
+	char buf[EROFS_MAX_BLOCK_SIZE];
 	struct erofs_inode vi = { .nid = nid };
 	erofs_off_t offset;
 
@@ -179,7 +193,7 @@ int erofs_namei(struct nameidata *nd,
 	offset = 0;
 	while (offset < vi.i_size) {
 		erofs_off_t maxsize = min_t(erofs_off_t,
-					    vi.i_size - offset, EROFS_BLKSIZ);
+					    vi.i_size - offset, erofs_blksiz());
 		struct erofs_dirent *de = (void *)buf;
 		unsigned int nameoff;
 
@@ -189,7 +203,7 @@ int erofs_namei(struct nameidata *nd,
 
 		nameoff = le16_to_cpu(de->nameoff);
 		if (nameoff < sizeof(struct erofs_dirent) ||
-		    nameoff >= PAGE_SIZE) {
+		    nameoff >= erofs_blksiz()) {
 			erofs_err("invalid de[0].nameoff %u @ nid %llu",
 				  nameoff, nid | 0ULL);
 			return -EFSCORRUPTED;
diff --git a/fs/erofs/super.c b/fs/erofs/super.c
index 8277d9b53f..d33926281b 100644
--- a/fs/erofs/super.c
+++ b/fs/erofs/super.c
@@ -9,7 +9,7 @@ static bool check_layout_compatibility(struct erofs_sb_info *sbi,
 	sbi->feature_incompat = feature;
 
 	/* check if current kernel meets all mandatory requirements */
-	if (feature & (~EROFS_ALL_FEATURE_INCOMPAT)) {
+	if (feature & ~EROFS_ALL_FEATURE_INCOMPAT) {
 		erofs_err("unidentified incompatible feature %x, please upgrade kernel version",
 			  feature & ~EROFS_ALL_FEATURE_INCOMPAT);
 		return false;
@@ -40,14 +40,18 @@ static int erofs_init_devices(struct erofs_sb_info *sbi,
 
 	sbi->device_id_mask = roundup_pow_of_two(ondisk_extradevs + 1) - 1;
 	sbi->devs = calloc(ondisk_extradevs, sizeof(*sbi->devs));
+	if (!sbi->devs)
+		return -ENOMEM;
 	pos = le16_to_cpu(dsb->devt_slotoff) * EROFS_DEVT_SLOT_SIZE;
 	for (i = 0; i < ondisk_extradevs; ++i) {
 		struct erofs_deviceslot dis;
 		int ret;
 
 		ret = erofs_dev_read(0, &dis, pos, sizeof(dis));
-		if (ret < 0)
+		if (ret < 0) {
+			free(sbi->devs);
 			return ret;
+		}
 
 		sbi->devs[i].mapped_blkaddr = dis.mapped_blkaddr;
 		sbi->total_blocks += dis.blocks;
@@ -58,42 +62,41 @@ static int erofs_init_devices(struct erofs_sb_info *sbi,
 
 int erofs_read_superblock(void)
 {
-	char data[EROFS_BLKSIZ];
+	u8 data[EROFS_MAX_BLOCK_SIZE];
 	struct erofs_super_block *dsb;
-	unsigned int blkszbits;
 	int ret;
 
-	ret = erofs_blk_read(data, 0, 1);
+	ret = erofs_blk_read(data, 0, erofs_blknr(sizeof(data)));
 	if (ret < 0) {
-		erofs_dbg("cannot read erofs superblock: %d", ret);
+		erofs_err("cannot read erofs superblock: %d", ret);
 		return -EIO;
 	}
 	dsb = (struct erofs_super_block *)(data + EROFS_SUPER_OFFSET);
 
 	ret = -EINVAL;
 	if (le32_to_cpu(dsb->magic) != EROFS_SUPER_MAGIC_V1) {
-		erofs_dbg("cannot find valid erofs superblock");
+		erofs_err("cannot find valid erofs superblock");
 		return ret;
 	}
 
 	sbi.feature_compat = le32_to_cpu(dsb->feature_compat);
 
-	blkszbits = dsb->blkszbits;
-	/* 9(512 bytes) + LOG_SECTORS_PER_BLOCK == LOG_BLOCK_SIZE */
-	if (blkszbits != LOG_BLOCK_SIZE) {
-		erofs_err("blksize %u isn't supported on this platform",
-			  1 << blkszbits);
+	sbi.blkszbits = dsb->blkszbits;
+	if (sbi.blkszbits < 9 ||
+	    sbi.blkszbits > ilog2(EROFS_MAX_BLOCK_SIZE)) {
+		erofs_err("blksize %llu isn't supported on this platform",
+			  erofs_blksiz() | 0ULL);
 		return ret;
-	}
-
-	if (!check_layout_compatibility(&sbi, dsb))
+	} else if (!check_layout_compatibility(&sbi, dsb)) {
 		return ret;
+	}
 
 	sbi.primarydevice_blocks = le32_to_cpu(dsb->blocks);
 	sbi.meta_blkaddr = le32_to_cpu(dsb->meta_blkaddr);
 	sbi.xattr_blkaddr = le32_to_cpu(dsb->xattr_blkaddr);
 	sbi.islotbits = EROFS_ISLOTBITS;
 	sbi.root_nid = le16_to_cpu(dsb->root_nid);
+	sbi.packed_nid = le64_to_cpu(dsb->packed_nid);
 	sbi.inos = le64_to_cpu(dsb->inos);
 	sbi.checksum = le32_to_cpu(dsb->checksum);
 
diff --git a/fs/erofs/zmap.c b/fs/erofs/zmap.c
index be2599ac4f..4f64258b00 100644
--- a/fs/erofs/zmap.c
+++ b/fs/erofs/zmap.c
@@ -1,14 +1,19 @@
 // SPDX-License-Identifier: GPL-2.0+
 #include "internal.h"
 
+static int z_erofs_do_map_blocks(struct erofs_inode *vi,
+				 struct erofs_map_blocks *map,
+				 int flags);
+
 int z_erofs_fill_inode(struct erofs_inode *vi)
 {
 	if (!erofs_sb_has_big_pcluster() &&
-	    vi->datalayout == EROFS_INODE_FLAT_COMPRESSION_LEGACY) {
+	    !erofs_sb_has_ztailpacking() && !erofs_sb_has_fragments() &&
+	    vi->datalayout == EROFS_INODE_COMPRESSED_FULL) {
 		vi->z_advise = 0;
 		vi->z_algorithmtype[0] = 0;
 		vi->z_algorithmtype[1] = 0;
-		vi->z_logical_clusterbits = LOG_BLOCK_SIZE;
+		vi->z_logical_clusterbits = sbi.blkszbits;
 
 		vi->flags |= EROFS_I_Z_INITED;
 	}
@@ -25,15 +30,23 @@ static int z_erofs_fill_inode_lazy(struct erofs_inode *vi)
 	if (vi->flags & EROFS_I_Z_INITED)
 		return 0;
 
-	DBG_BUGON(!erofs_sb_has_big_pcluster() &&
-		  vi->datalayout == EROFS_INODE_FLAT_COMPRESSION_LEGACY);
 	pos = round_up(iloc(vi->nid) + vi->inode_isize + vi->xattr_isize, 8);
-
 	ret = erofs_dev_read(0, buf, pos, sizeof(buf));
 	if (ret < 0)
 		return -EIO;
 
 	h = (struct z_erofs_map_header *)buf;
+	/*
+	 * if the highest bit of the 8-byte map header is set, the whole file
+	 * is stored in the packed inode. The rest bits keeps z_fragmentoff.
+	 */
+	if (h->h_clusterbits >> Z_EROFS_FRAGMENT_INODE_BIT) {
+		vi->z_advise = Z_EROFS_ADVISE_FRAGMENT_PCLUSTER;
+		vi->fragmentoff = le64_to_cpu(*(__le64 *)h) ^ (1ULL << 63);
+		vi->z_tailextent_headlcn = 0;
+		goto out;
+	}
+
 	vi->z_advise = le16_to_cpu(h->h_advise);
 	vi->z_algorithmtype[0] = h->h_algorithmtype & 15;
 	vi->z_algorithmtype[1] = h->h_algorithmtype >> 4;
@@ -44,14 +57,41 @@ static int z_erofs_fill_inode_lazy(struct erofs_inode *vi)
 		return -EOPNOTSUPP;
 	}
 
-	vi->z_logical_clusterbits = LOG_BLOCK_SIZE + (h->h_clusterbits & 7);
-	if (vi->datalayout == EROFS_INODE_FLAT_COMPRESSION &&
+	vi->z_logical_clusterbits = sbi.blkszbits + (h->h_clusterbits & 7);
+	if (vi->datalayout == EROFS_INODE_COMPRESSED_COMPACT &&
 	    !(vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_1) ^
 	    !(vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_2)) {
 		erofs_err("big pcluster head1/2 of compact indexes should be consistent for nid %llu",
 			  vi->nid * 1ULL);
 		return -EFSCORRUPTED;
 	}
+
+	if (vi->z_advise & Z_EROFS_ADVISE_INLINE_PCLUSTER) {
+		struct erofs_map_blocks map = { .index = UINT_MAX };
+
+		vi->idata_size = le16_to_cpu(h->h_idata_size);
+		ret = z_erofs_do_map_blocks(vi, &map,
+					    EROFS_GET_BLOCKS_FINDTAIL);
+		if (!map.m_plen ||
+		    erofs_blkoff(map.m_pa) + map.m_plen > erofs_blksiz()) {
+			erofs_err("invalid tail-packing pclustersize %llu",
+				  map.m_plen | 0ULL);
+			return -EFSCORRUPTED;
+		}
+		if (ret < 0)
+			return ret;
+	}
+	if (vi->z_advise & Z_EROFS_ADVISE_FRAGMENT_PCLUSTER &&
+	    !(h->h_clusterbits >> Z_EROFS_FRAGMENT_INODE_BIT)) {
+		struct erofs_map_blocks map = { .index = UINT_MAX };
+
+		vi->fragmentoff = le32_to_cpu(h->h_fragmentoff);
+		ret = z_erofs_do_map_blocks(vi, &map,
+					    EROFS_GET_BLOCKS_FINDTAIL);
+		if (ret < 0)
+			return ret;
+	}
+out:
 	vi->flags |= EROFS_I_Z_INITED;
 	return 0;
 }
@@ -66,7 +106,9 @@ struct z_erofs_maprecorder {
 	u8  type, headtype;
 	u16 clusterofs;
 	u16 delta[2];
-	erofs_blk_t pblk, compressedlcs;
+	erofs_blk_t pblk, compressedblks;
+	erofs_off_t nextpackoff;
+	bool partialref;
 };
 
 static int z_erofs_reload_indexes(struct z_erofs_maprecorder *m,
@@ -93,11 +135,10 @@ static int legacy_load_cluster_from_disk(struct z_erofs_maprecorder *m,
 {
 	struct erofs_inode *const vi = m->inode;
 	const erofs_off_t ibase = iloc(vi->nid);
-	const erofs_off_t pos =
-		Z_EROFS_VLE_LEGACY_INDEX_ALIGN(ibase + vi->inode_isize +
-					       vi->xattr_isize) +
-		lcn * sizeof(struct z_erofs_vle_decompressed_index);
-	struct z_erofs_vle_decompressed_index *di;
+	const erofs_off_t pos = Z_EROFS_FULL_INDEX_ALIGN(ibase +
+			vi->inode_isize + vi->xattr_isize) +
+		lcn * sizeof(struct z_erofs_lcluster_index);
+	struct z_erofs_lcluster_index *di;
 	unsigned int advise, type;
 	int err;
 
@@ -105,29 +146,32 @@ static int legacy_load_cluster_from_disk(struct z_erofs_maprecorder *m,
 	if (err)
 		return err;
 
+	m->nextpackoff = pos + sizeof(struct z_erofs_lcluster_index);
 	m->lcn = lcn;
 	di = m->kaddr + erofs_blkoff(pos);
 
 	advise = le16_to_cpu(di->di_advise);
-	type = (advise >> Z_EROFS_VLE_DI_CLUSTER_TYPE_BIT) &
-		((1 << Z_EROFS_VLE_DI_CLUSTER_TYPE_BITS) - 1);
+	type = (advise >> Z_EROFS_LI_LCLUSTER_TYPE_BIT) &
+		((1 << Z_EROFS_LI_LCLUSTER_TYPE_BITS) - 1);
 	switch (type) {
-	case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD:
+	case Z_EROFS_LCLUSTER_TYPE_NONHEAD:
 		m->clusterofs = 1 << vi->z_logical_clusterbits;
 		m->delta[0] = le16_to_cpu(di->di_u.delta[0]);
-		if (m->delta[0] & Z_EROFS_VLE_DI_D0_CBLKCNT) {
+		if (m->delta[0] & Z_EROFS_LI_D0_CBLKCNT) {
 			if (!(vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_1)) {
 				DBG_BUGON(1);
 				return -EFSCORRUPTED;
 			}
-			m->compressedlcs = m->delta[0] &
-				~Z_EROFS_VLE_DI_D0_CBLKCNT;
+			m->compressedblks = m->delta[0] &
+				~Z_EROFS_LI_D0_CBLKCNT;
 			m->delta[0] = 1;
 		}
 		m->delta[1] = le16_to_cpu(di->di_u.delta[1]);
 		break;
-	case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
-	case Z_EROFS_VLE_CLUSTER_TYPE_HEAD:
+	case Z_EROFS_LCLUSTER_TYPE_PLAIN:
+	case Z_EROFS_LCLUSTER_TYPE_HEAD1:
+		if (advise & Z_EROFS_LI_PARTIAL_REF)
+			m->partialref = true;
 		m->clusterofs = le16_to_cpu(di->di_clusterofs);
 		m->pblk = le32_to_cpu(di->di_u.blkaddr);
 		break;
@@ -164,25 +208,25 @@ static int get_compacted_la_distance(unsigned int lclusterbits,
 		lo = decode_compactedbits(lclusterbits, lomask,
 					  in, encodebits * i, &type);
 
-		if (type != Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD)
+		if (type != Z_EROFS_LCLUSTER_TYPE_NONHEAD)
 			return d1;
 		++d1;
 	} while (++i < vcnt);
 
-	/* vcnt - 1 (Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) item */
-	if (!(lo & Z_EROFS_VLE_DI_D0_CBLKCNT))
+	/* vcnt - 1 (Z_EROFS_LCLUSTER_TYPE_NONHEAD) item */
+	if (!(lo & Z_EROFS_LI_D0_CBLKCNT))
 		d1 += lo - 1;
 	return d1;
 }
 
 static int unpack_compacted_index(struct z_erofs_maprecorder *m,
 				  unsigned int amortizedshift,
-				  unsigned int eofs, bool lookahead)
+				  erofs_off_t pos, bool lookahead)
 {
 	struct erofs_inode *const vi = m->inode;
 	const unsigned int lclusterbits = vi->z_logical_clusterbits;
 	const unsigned int lomask = (1 << lclusterbits) - 1;
-	unsigned int vcnt, base, lo, encodebits, nblk;
+	unsigned int vcnt, base, lo, encodebits, nblk, eofs;
 	int i;
 	u8 *in, type;
 	bool big_pcluster;
@@ -194,8 +238,12 @@ static int unpack_compacted_index(struct z_erofs_maprecorder *m,
 	else
 		return -EOPNOTSUPP;
 
+	/* it doesn't equal to round_up(..) */
+	m->nextpackoff = round_down(pos, vcnt << amortizedshift) +
+			 (vcnt << amortizedshift);
 	big_pcluster = vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_1;
 	encodebits = ((vcnt << amortizedshift) - sizeof(__le32)) * 8 / vcnt;
+	eofs = erofs_blkoff(pos);
 	base = round_down(eofs, vcnt << amortizedshift);
 	in = m->kaddr + base;
 
@@ -204,20 +252,19 @@ static int unpack_compacted_index(struct z_erofs_maprecorder *m,
 	lo = decode_compactedbits(lclusterbits, lomask,
 				  in, encodebits * i, &type);
 	m->type = type;
-	if (type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) {
+	if (type == Z_EROFS_LCLUSTER_TYPE_NONHEAD) {
 		m->clusterofs = 1 << lclusterbits;
 
 		/* figure out lookahead_distance: delta[1] if needed */
 		if (lookahead)
 			m->delta[1] = get_compacted_la_distance(lclusterbits,
-								encodebits,
-								vcnt, in, i);
-		if (lo & Z_EROFS_VLE_DI_D0_CBLKCNT) {
+								encodebits, vcnt, in, i);
+		if (lo & Z_EROFS_LI_D0_CBLKCNT) {
 			if (!big_pcluster) {
 				DBG_BUGON(1);
 				return -EFSCORRUPTED;
 			}
-			m->compressedlcs = lo & ~Z_EROFS_VLE_DI_D0_CBLKCNT;
+			m->compressedblks = lo & ~Z_EROFS_LI_D0_CBLKCNT;
 			m->delta[0] = 1;
 			return 0;
 		} else if (i + 1 != (int)vcnt) {
@@ -231,9 +278,9 @@ static int unpack_compacted_index(struct z_erofs_maprecorder *m,
 		 */
 		lo = decode_compactedbits(lclusterbits, lomask,
 					  in, encodebits * (i - 1), &type);
-		if (type != Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD)
+		if (type != Z_EROFS_LCLUSTER_TYPE_NONHEAD)
 			lo = 0;
-		else if (lo & Z_EROFS_VLE_DI_D0_CBLKCNT)
+		else if (lo & Z_EROFS_LI_D0_CBLKCNT)
 			lo = 1;
 		m->delta[0] = lo + 1;
 		return 0;
@@ -247,7 +294,7 @@ static int unpack_compacted_index(struct z_erofs_maprecorder *m,
 			--i;
 			lo = decode_compactedbits(lclusterbits, lomask,
 						  in, encodebits * i, &type);
-			if (type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD)
+			if (type == Z_EROFS_LCLUSTER_TYPE_NONHEAD)
 				i -= lo;
 
 			if (i >= 0)
@@ -259,13 +306,13 @@ static int unpack_compacted_index(struct z_erofs_maprecorder *m,
 			--i;
 			lo = decode_compactedbits(lclusterbits, lomask,
 						  in, encodebits * i, &type);
-			if (type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) {
-				if (lo & Z_EROFS_VLE_DI_D0_CBLKCNT) {
+			if (type == Z_EROFS_LCLUSTER_TYPE_NONHEAD) {
+				if (lo & Z_EROFS_LI_D0_CBLKCNT) {
 					--i;
-					nblk += lo & ~Z_EROFS_VLE_DI_D0_CBLKCNT;
+					nblk += lo & ~Z_EROFS_LI_D0_CBLKCNT;
 					continue;
 				}
-				if (lo == 1) {
+				if (lo <= 1) {
 					DBG_BUGON(1);
 					/* --i; ++nblk;	continue; */
 					return -EFSCORRUPTED;
@@ -289,7 +336,7 @@ static int compacted_load_cluster_from_disk(struct z_erofs_maprecorder *m,
 	const erofs_off_t ebase = round_up(iloc(vi->nid) + vi->inode_isize +
 					   vi->xattr_isize, 8) +
 		sizeof(struct z_erofs_map_header);
-	const unsigned int totalidx = DIV_ROUND_UP(vi->i_size, EROFS_BLKSIZ);
+	const unsigned int totalidx = BLK_ROUND_UP(vi->i_size);
 	unsigned int compacted_4b_initial, compacted_2b;
 	unsigned int amortizedshift;
 	erofs_off_t pos;
@@ -307,7 +354,8 @@ static int compacted_load_cluster_from_disk(struct z_erofs_maprecorder *m,
 	if (compacted_4b_initial == 32 / 4)
 		compacted_4b_initial = 0;
 
-	if (vi->z_advise & Z_EROFS_ADVISE_COMPACTED_2B)
+	if ((vi->z_advise & Z_EROFS_ADVISE_COMPACTED_2B) &&
+	    compacted_4b_initial < totalidx)
 		compacted_2b = rounddown(totalidx - compacted_4b_initial, 16);
 	else
 		compacted_2b = 0;
@@ -332,8 +380,7 @@ out:
 	err = z_erofs_reload_indexes(m, erofs_blknr(pos));
 	if (err)
 		return err;
-	return unpack_compacted_index(m, amortizedshift, erofs_blkoff(pos),
-				      lookahead);
+	return unpack_compacted_index(m, amortizedshift, pos, lookahead);
 }
 
 static int z_erofs_load_cluster_from_disk(struct z_erofs_maprecorder *m,
@@ -341,10 +388,10 @@ static int z_erofs_load_cluster_from_disk(struct z_erofs_maprecorder *m,
 {
 	const unsigned int datamode = m->inode->datalayout;
 
-	if (datamode == EROFS_INODE_FLAT_COMPRESSION_LEGACY)
+	if (datamode == EROFS_INODE_COMPRESSED_FULL)
 		return legacy_load_cluster_from_disk(m, lcn);
 
-	if (datamode == EROFS_INODE_FLAT_COMPRESSION)
+	if (datamode == EROFS_INODE_COMPRESSED_COMPACT)
 		return compacted_load_cluster_from_disk(m, lcn, lookahead);
 
 	return -EINVAL;
@@ -373,7 +420,7 @@ static int z_erofs_extent_lookback(struct z_erofs_maprecorder *m,
 		return err;
 
 	switch (m->type) {
-	case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD:
+	case Z_EROFS_LCLUSTER_TYPE_NONHEAD:
 		if (!m->delta[0]) {
 			erofs_err("invalid lookback distance 0 @ nid %llu",
 				  (unsigned long long)vi->nid);
@@ -381,8 +428,8 @@ static int z_erofs_extent_lookback(struct z_erofs_maprecorder *m,
 			return -EFSCORRUPTED;
 		}
 		return z_erofs_extent_lookback(m, m->delta[0]);
-	case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
-	case Z_EROFS_VLE_CLUSTER_TYPE_HEAD:
+	case Z_EROFS_LCLUSTER_TYPE_PLAIN:
+	case Z_EROFS_LCLUSTER_TYPE_HEAD1:
 		m->headtype = m->type;
 		map->m_la = (lcn << lclusterbits) | m->clusterofs;
 		break;
@@ -404,16 +451,17 @@ static int z_erofs_get_extent_compressedlen(struct z_erofs_maprecorder *m,
 	unsigned long lcn;
 	int err;
 
-	DBG_BUGON(m->type != Z_EROFS_VLE_CLUSTER_TYPE_PLAIN &&
-		  m->type != Z_EROFS_VLE_CLUSTER_TYPE_HEAD);
-	if (m->headtype == Z_EROFS_VLE_CLUSTER_TYPE_PLAIN ||
+	DBG_BUGON(m->type != Z_EROFS_LCLUSTER_TYPE_PLAIN &&
+		  m->type != Z_EROFS_LCLUSTER_TYPE_HEAD1);
+
+	if (m->headtype == Z_EROFS_LCLUSTER_TYPE_PLAIN ||
 	    !(vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_1)) {
 		map->m_plen = 1 << lclusterbits;
 		return 0;
 	}
 
 	lcn = m->lcn + 1;
-	if (m->compressedlcs)
+	if (m->compressedblks)
 		goto out;
 
 	err = z_erofs_load_cluster_from_disk(m, lcn, false);
@@ -422,28 +470,28 @@ static int z_erofs_get_extent_compressedlen(struct z_erofs_maprecorder *m,
 
 	/*
 	 * If the 1st NONHEAD lcluster has already been handled initially w/o
-	 * valid compressedlcs, which means at least it mustn't be CBLKCNT, or
+	 * valid compressedblks, which means at least it mustn't be CBLKCNT, or
 	 * an internal implemenatation error is detected.
 	 *
 	 * The following code can also handle it properly anyway, but let's
 	 * BUG_ON in the debugging mode only for developers to notice that.
 	 */
 	DBG_BUGON(lcn == initial_lcn &&
-		  m->type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD);
+		  m->type == Z_EROFS_LCLUSTER_TYPE_NONHEAD);
 
 	switch (m->type) {
-	case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
-	case Z_EROFS_VLE_CLUSTER_TYPE_HEAD:
+	case Z_EROFS_LCLUSTER_TYPE_PLAIN:
+	case Z_EROFS_LCLUSTER_TYPE_HEAD1:
 		/*
 		 * if the 1st NONHEAD lcluster is actually PLAIN or HEAD type
 		 * rather than CBLKCNT, it's a 1 lcluster-sized pcluster.
 		 */
-		m->compressedlcs = 1;
+		m->compressedblks = 1 << (lclusterbits - sbi.blkszbits);
 		break;
-	case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD:
+	case Z_EROFS_LCLUSTER_TYPE_NONHEAD:
 		if (m->delta[0] != 1)
 			goto err_bonus_cblkcnt;
-		if (m->compressedlcs)
+		if (m->compressedblks)
 			break;
 		/* fallthrough */
 	default:
@@ -453,7 +501,7 @@ static int z_erofs_get_extent_compressedlen(struct z_erofs_maprecorder *m,
 		return -EFSCORRUPTED;
 	}
 out:
-	map->m_plen = m->compressedlcs << lclusterbits;
+	map->m_plen = m->compressedblks << sbi.blkszbits;
 	return 0;
 err_bonus_cblkcnt:
 	erofs_err("bogus CBLKCNT @ lcn %lu of nid %llu",
@@ -481,11 +529,11 @@ static int z_erofs_get_extent_decompressedlen(struct z_erofs_maprecorder *m)
 		if (err)
 			return err;
 
-		if (m->type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) {
+		if (m->type == Z_EROFS_LCLUSTER_TYPE_NONHEAD) {
 			DBG_BUGON(!m->delta[1] &&
 				  m->clusterofs != 1 << lclusterbits);
-		} else if (m->type == Z_EROFS_VLE_CLUSTER_TYPE_PLAIN ||
-			   m->type == Z_EROFS_VLE_CLUSTER_TYPE_HEAD) {
+		} else if (m->type == Z_EROFS_LCLUSTER_TYPE_PLAIN ||
+			   m->type == Z_EROFS_LCLUSTER_TYPE_HEAD1) {
 			/* go on until the next HEAD lcluster */
 			if (lcn != headlcn)
 				break;
@@ -504,10 +552,12 @@ static int z_erofs_get_extent_decompressedlen(struct z_erofs_maprecorder *m)
 	return 0;
 }
 
-int z_erofs_map_blocks_iter(struct erofs_inode *vi,
-			    struct erofs_map_blocks *map,
-			    int flags)
+static int z_erofs_do_map_blocks(struct erofs_inode *vi,
+				 struct erofs_map_blocks *map,
+				 int flags)
 {
+	bool ztailpacking = vi->z_advise & Z_EROFS_ADVISE_INLINE_PCLUSTER;
+	bool fragment = vi->z_advise & Z_EROFS_ADVISE_FRAGMENT_PCLUSTER;
 	struct z_erofs_maprecorder m = {
 		.inode = vi,
 		.map = map,
@@ -518,20 +568,8 @@ int z_erofs_map_blocks_iter(struct erofs_inode *vi,
 	unsigned long initial_lcn;
 	unsigned long long ofs, end;
 
-	/* when trying to read beyond EOF, leave it unmapped */
-	if (map->m_la >= vi->i_size) {
-		map->m_llen = map->m_la + 1 - vi->i_size;
-		map->m_la = vi->i_size;
-		map->m_flags = 0;
-		goto out;
-	}
-
-	err = z_erofs_fill_inode_lazy(vi);
-	if (err)
-		goto out;
-
 	lclusterbits = vi->z_logical_clusterbits;
-	ofs = map->m_la;
+	ofs = flags & EROFS_GET_BLOCKS_FINDTAIL ? vi->i_size - 1 : map->m_la;
 	initial_lcn = ofs >> lclusterbits;
 	endoff = ofs & ((1 << lclusterbits) - 1);
 
@@ -539,11 +577,14 @@ int z_erofs_map_blocks_iter(struct erofs_inode *vi,
 	if (err)
 		goto out;
 
+	if (ztailpacking && (flags & EROFS_GET_BLOCKS_FINDTAIL))
+		vi->z_idataoff = m.nextpackoff;
+
 	map->m_flags = EROFS_MAP_MAPPED | EROFS_MAP_ENCODED;
 	end = (m.lcn + 1ULL) << lclusterbits;
 	switch (m.type) {
-	case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
-	case Z_EROFS_VLE_CLUSTER_TYPE_HEAD:
+	case Z_EROFS_LCLUSTER_TYPE_PLAIN:
+	case Z_EROFS_LCLUSTER_TYPE_HEAD1:
 		if (endoff >= m.clusterofs) {
 			m.headtype = m.type;
 			map->m_la = (m.lcn << lclusterbits) | m.clusterofs;
@@ -560,7 +601,7 @@ int z_erofs_map_blocks_iter(struct erofs_inode *vi,
 		map->m_flags |= EROFS_MAP_FULL_MAPPED;
 		m.delta[0] = 1;
 		/* fallthrough */
-	case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD:
+	case Z_EROFS_LCLUSTER_TYPE_NONHEAD:
 		/* get the correspoinding first chunk */
 		err = z_erofs_extent_lookback(&m, m.delta[0]);
 		if (err)
@@ -572,18 +613,43 @@ int z_erofs_map_blocks_iter(struct erofs_inode *vi,
 		err = -EOPNOTSUPP;
 		goto out;
 	}
-
+	if (m.partialref)
+		map->m_flags |= EROFS_MAP_PARTIAL_REF;
 	map->m_llen = end - map->m_la;
-	map->m_pa = blknr_to_addr(m.pblk);
-
-	err = z_erofs_get_extent_compressedlen(&m, initial_lcn);
-	if (err)
-		goto out;
+	if (flags & EROFS_GET_BLOCKS_FINDTAIL) {
+		vi->z_tailextent_headlcn = m.lcn;
+		/* for non-compact indexes, fragmentoff is 64 bits */
+		if (fragment && vi->datalayout == EROFS_INODE_COMPRESSED_FULL)
+			vi->fragmentoff |= (u64)m.pblk << 32;
+	}
+	if (ztailpacking && m.lcn == vi->z_tailextent_headlcn) {
+		map->m_flags |= EROFS_MAP_META;
+		map->m_pa = vi->z_idataoff;
+		map->m_plen = vi->z_idata_size;
+	} else if (fragment && m.lcn == vi->z_tailextent_headlcn) {
+		map->m_flags |= EROFS_MAP_FRAGMENT;
+	} else {
+		map->m_pa = erofs_pos(m.pblk);
+		err = z_erofs_get_extent_compressedlen(&m, initial_lcn);
+		if (err)
+			goto out;
+	}
 
-	if (m.headtype == Z_EROFS_VLE_CLUSTER_TYPE_PLAIN)
-		map->m_algorithmformat = Z_EROFS_COMPRESSION_SHIFTED;
-	else
+	if (m.headtype == Z_EROFS_LCLUSTER_TYPE_PLAIN) {
+		if (map->m_llen > map->m_plen) {
+			DBG_BUGON(1);
+			err = -EFSCORRUPTED;
+			goto out;
+		}
+		if (vi->z_advise & Z_EROFS_ADVISE_INTERLACED_PCLUSTER)
+			map->m_algorithmformat =
+				Z_EROFS_COMPRESSION_INTERLACED;
+		else
+			map->m_algorithmformat =
+				Z_EROFS_COMPRESSION_SHIFTED;
+	} else {
 		map->m_algorithmformat = vi->z_algorithmtype[0];
+	}
 
 	if (flags & EROFS_GET_BLOCKS_FIEMAP) {
 		err = z_erofs_get_extent_decompressedlen(&m);
@@ -595,7 +661,38 @@ out:
 	erofs_dbg("m_la %" PRIu64 " m_pa %" PRIu64 " m_llen %" PRIu64 " m_plen %" PRIu64 " m_flags 0%o",
 		  map->m_la, map->m_pa,
 		  map->m_llen, map->m_plen, map->m_flags);
+	return err;
+}
 
+int z_erofs_map_blocks_iter(struct erofs_inode *vi,
+			    struct erofs_map_blocks *map,
+			    int flags)
+{
+	int err = 0;
+
+	/* when trying to read beyond EOF, leave it unmapped */
+	if (map->m_la >= vi->i_size) {
+		map->m_llen = map->m_la + 1 - vi->i_size;
+		map->m_la = vi->i_size;
+		map->m_flags = 0;
+		goto out;
+	}
+
+	err = z_erofs_fill_inode_lazy(vi);
+	if (err)
+		goto out;
+
+	if ((vi->z_advise & Z_EROFS_ADVISE_FRAGMENT_PCLUSTER) &&
+	    !vi->z_tailextent_headlcn) {
+		map->m_la = 0;
+		map->m_llen = vi->i_size;
+		map->m_flags = EROFS_MAP_MAPPED | EROFS_MAP_FULL_MAPPED |
+				EROFS_MAP_FRAGMENT;
+		goto out;
+	}
+
+	err = z_erofs_do_map_blocks(vi, map, flags);
+out:
 	DBG_BUGON(err < 0 && err != -ENOMEM);
 	return err;
 }
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 2da93dae3c..d1476aa433 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -8,6 +8,8 @@
  * 2003-03-10 - kharris@nexus-tech.net - ported to uboot
  */
 
+#define LOG_CATEGORY	LOGC_FS
+
 #include <common.h>
 #include <blk.h>
 #include <config.h>
@@ -97,8 +99,8 @@ int fat_register_device(struct blk_desc *dev_desc, int part_no)
 	/* Read the partition table, if present */
 	if (part_get_info(dev_desc, part_no, &info)) {
 		if (part_no != 0) {
-			printf("** Partition %d not valid on device %d **\n",
-					part_no, dev_desc->devnum);
+			log_err("Partition %d invalid on device %d\n", part_no,
+				dev_desc->devnum);
 			return -1;
 		}
 
@@ -168,7 +170,7 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry)
 	__u32 ret = 0x00;
 
 	if (CHECK_CLUST(entry, mydata->fatsize)) {
-		printf("Error: Invalid FAT entry: 0x%08x\n", entry);
+		log_err("Invalid FAT entry: %#08x\n", entry);
 		return ret;
 	}
 
@@ -586,19 +588,19 @@ static int get_fs_info(fsdata *mydata)
 	mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0];
 	mydata->clust_size = bs.cluster_size;
 	if (mydata->sect_size != cur_part_info.blksz) {
-		printf("Error: FAT sector size mismatch (fs=%hu, dev=%lu)\n",
-				mydata->sect_size, cur_part_info.blksz);
+		log_err("FAT sector size mismatch (fs=%u, dev=%lu)\n",
+			mydata->sect_size, cur_part_info.blksz);
 		return -1;
 	}
 	if (mydata->clust_size == 0) {
-		printf("Error: FAT cluster size not set\n");
+		log_err("FAT cluster size not set\n");
 		return -1;
 	}
 	if ((unsigned int)mydata->clust_size * mydata->sect_size >
 	    MAX_CLUSTSIZE) {
-		printf("Error: FAT cluster size too big (cs=%u, max=%u)\n",
-		       (unsigned int)mydata->clust_size * mydata->sect_size,
-		       MAX_CLUSTSIZE);
+		log_err("FAT cluster size too big (cs=%u, max=%u)\n",
+			(uint)mydata->clust_size * mydata->sect_size,
+			MAX_CLUSTSIZE);
 		return -1;
 	}
 
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index 413fc432eb..a6294419b8 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -132,9 +132,9 @@ static int set_name(fat_itr *itr, const char *filename, char *shortname)
 		return period_location;
 	if (*dirent.name == ' ')
 		*dirent.name = '_';
-	/* 0xe5 signals a deleted directory entry. Replace it by 0x05. */
-	if (*dirent.name == 0xe5)
-		*dirent.name = 0x05;
+	/* Substitute character 0xe5 signaling deletetion by character 0x05 */
+	if (*dirent.name == DELETED_FLAG)
+		*dirent.name = aRING;
 
 	/* If filename and short name are the same, quit. */
 	sprintf(buf, "%.*s.%.3s", period_location, dirent.name, dirent.ext);
@@ -1571,8 +1571,9 @@ int fat_unlink(const char *filename)
 	char *filename_copy, *dirname, *basename;
 
 	filename_copy = strdup(filename);
-	if (!filename_copy) {
-		printf("Error: allocating memory\n");
+	itr = malloc_cache_aligned(sizeof(fat_itr));
+	if (!itr || !filename_copy) {
+		printf("Error: out of memory\n");
 		ret = -ENOMEM;
 		goto exit;
 	}
@@ -1584,13 +1585,6 @@ int fat_unlink(const char *filename)
 		goto exit;
 	}
 
-	itr = malloc_cache_aligned(sizeof(fat_itr));
-	if (!itr) {
-		printf("Error: allocating memory\n");
-		ret = -ENOMEM;
-		goto exit;
-	}
-
 	ret = fat_itr_root(itr, &fsdata);
 	if (ret)
 		goto exit;
@@ -1605,7 +1599,7 @@ int fat_unlink(const char *filename)
 	}
 
 	if (!find_directory_entry(itr, basename)) {
-		printf("%s: doesn't exist\n", basename);
+		log_err("%s: doesn't exist (%d)\n", basename, -ENOENT);
 		ret = -ENOENT;
 		goto exit;
 	}
diff --git a/fs/fs.c b/fs/fs.c
index 8324b4a22f..2b815b1db0 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -13,6 +13,7 @@
 #include <env.h>
 #include <lmb.h>
 #include <log.h>
+#include <malloc.h>
 #include <mapmem.h>
 #include <part.h>
 #include <ext4fs.h>
@@ -26,6 +27,7 @@
 #include <asm/io.h>
 #include <div64.h>
 #include <linux/math64.h>
+#include <linux/sizes.h>
 #include <efi_loader.h>
 #include <squashfs.h>
 #include <erofs.h>
@@ -1008,3 +1010,59 @@ int do_fs_types(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
 	puts("\n");
 	return CMD_RET_SUCCESS;
 }
+
+int fs_read_alloc(const char *fname, ulong size, uint align, void **bufp)
+{
+	loff_t bytes_read;
+	ulong addr;
+	char *buf;
+	int ret;
+
+	buf = memalign(align, size + 1);
+	if (!buf)
+		return log_msg_ret("buf", -ENOMEM);
+	addr = map_to_sysmem(buf);
+
+	ret = fs_read(fname, addr, 0, size, &bytes_read);
+	if (ret) {
+		free(buf);
+		return log_msg_ret("read", ret);
+	}
+	if (size != bytes_read)
+		return log_msg_ret("bread", -EIO);
+	buf[size] = '\0';
+
+	*bufp = buf;
+
+	return 0;
+}
+
+int fs_load_alloc(const char *ifname, const char *dev_part_str,
+		  const char *fname, ulong max_size, ulong align, void **bufp,
+		  ulong *sizep)
+{
+	loff_t size;
+	void *buf;
+	int ret;
+
+	if (fs_set_blk_dev(ifname, dev_part_str, FS_TYPE_ANY))
+		return log_msg_ret("set", -ENOMEDIUM);
+
+	ret = fs_size(fname, &size);
+	if (ret)
+		return log_msg_ret("sz", -ENOENT);
+
+	if (size >= (max_size ?: SZ_1G))
+		return log_msg_ret("sz", -E2BIG);
+
+	if (fs_set_blk_dev(ifname, dev_part_str, FS_TYPE_ANY))
+		return log_msg_ret("set", -ENOMEDIUM);
+
+	ret = fs_read_alloc(fname, size, align, &buf);
+	if (ret)
+		return log_msg_ret("al", ret);
+	*sizep = size;
+	*bufp = buf;
+
+	return 0;
+}
diff --git a/fs/sandbox/host_bootdev.c b/fs/sandbox/host_bootdev.c
index 0d12ee4ef7..3ef5362760 100644
--- a/fs/sandbox/host_bootdev.c
+++ b/fs/sandbox/host_bootdev.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Bootdevice for MMC
+ * Bootdev for sandbox host
  *
  * Copyright 2021 Google LLC
  * Written by Simon Glass <sjg@chromium.org>
diff --git a/fs/semihostingfs.c b/fs/semihostingfs.c
index 96eb3349a2..3592338a68 100644
--- a/fs/semihostingfs.c
+++ b/fs/semihostingfs.c
@@ -57,8 +57,12 @@ static int smh_fs_write_at(const char *filename, loff_t pos, void *buffer,
 {
 	long fd, size, ret;
 
+	/* Try to open existing file */
 	fd = smh_open(filename, MODE_READ | MODE_BINARY | MODE_PLUS);
 	if (fd < 0)
+		/* Create new file */
+		fd = smh_open(filename, MODE_WRITE | MODE_BINARY);
+	if (fd < 0)
 		return fd;
 	ret = smh_seek(fd, pos);
 	if (ret < 0) {
diff --git a/include/.gitignore b/include/.gitignore
deleted file mode 100644
index 8e41a9511d..0000000000
--- a/include/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-/autoconf.mk*
-/bmp_logo.h
-/bmp_logo_data.h
-/config.h
diff --git a/include/ali512x.h b/include/ali512x.h
deleted file mode 100644
index 6bb67009c1..0000000000
--- a/include/ali512x.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
- */
-
-#ifndef __ASM_IC_ALI512X_H_
-#define __ASM_IC_ALI512X_H_
-
-# define ALI_INDEX    0x3f0
-# define ALI_DATA     0x3f1
-
-# define ALI_ENABLED  1
-# define ALI_DISABLED 0
-
-# define ALI_UART1    0
-# define ALI_UART2    1
-
-/* setup functions */
-void ali512x_init(void);
-void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel);
-void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel);
-void ali512x_set_uart(int enabled, int index, u16 io, u8 irq);
-void ali512x_set_rtc(int enabled, u16 io, u8 irq);
-void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq);
-void ali512x_set_cio(int enabled);
-
-
-/* common I/O functions */
-void ali512x_cio_function(int pin, int special, int inv, int input);
-void ali512x_cio_out(int pin, int value);
-int ali512x_cio_in(int pin);
-
-/* misc features */
-void ali512x_set_uart2_irda(int enabled);
-
-#endif
diff --git a/include/andestech/andes_pcu.h b/include/andestech/andes_pcu.h
deleted file mode 100644
index d24b82d18e..0000000000
--- a/include/andestech/andes_pcu.h
+++ /dev/null
@@ -1,354 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011 Andes Technology Corp
- * Macpaul Lin <macpaul@andestech.com>
- */
-
-/*
- * Andes Power Control Unit
- */
-#ifndef __ANDES_PCU_H
-#define __ANDES_PCU_H
-
-#ifndef __ASSEMBLY__
-
-struct pcs {
-	unsigned int	cr;		/* PCSx Configuration (clock scaling) */
-	unsigned int	parm;		/* PCSx Parameter*/
-	unsigned int	stat1;		/* PCSx Status 1 */
-	unsigned int	stat2;		/* PCSx Stusts 2 */
-	unsigned int	pdd;		/* PCSx PDD */
-};
-
-struct andes_pcu {
-	unsigned int	rev;		/* 0x00 - PCU Revision */
-	unsigned int	spinfo;		/* 0x04 - Scratch Pad Info */
-	unsigned int	rsvd1[2];	/* 0x08-0x0C: Reserved */
-	unsigned int	soc_id;		/* 0x10 - SoC ID */
-	unsigned int	soc_ahb;	/* 0x14 - SoC AHB configuration */
-	unsigned int	soc_apb;	/* 0x18 - SoC APB configuration */
-	unsigned int	rsvd2;		/* 0x1C */
-	unsigned int	dcsrcr0;	/* 0x20 - Driving Capability
-						and Slew Rate Control 0 */
-	unsigned int	dcsrcr1;	/* 0x24 - Driving Capability
-						and Slew Rate Control 1 */
-	unsigned int	dcsrcr2;	/* 0x28 - Driving Capability
-						and Slew Rate Control 2 */
-	unsigned int	rsvd3;		/* 0x2C */
-	unsigned int	mfpsr0;		/* 0x30 - Multi-Func Port Setting 0 */
-	unsigned int	mfpsr1;		/* 0x34 - Multi-Func Port Setting 1 */
-	unsigned int	dmaes;		/* 0x38 - DMA Engine Selection */
-	unsigned int	rsvd4;		/* 0x3C */
-	unsigned int	oscc;		/* 0x40 - OSC Control */
-	unsigned int	pwmcd;		/* 0x44 - PWM Clock divider */
-	unsigned int	socmisc;	/* 0x48 - SoC Misc. */
-	unsigned int	rsvd5[13];	/* 0x4C-0x7C: Reserved */
-	unsigned int	bsmcr;		/* 0x80 - BSM Controrl */
-	unsigned int	bsmst;		/* 0x84 - BSM Status */
-	unsigned int	wes;		/* 0x88 - Wakeup Event Sensitivity*/
-	unsigned int	west;		/* 0x8C - Wakeup Event Status */
-	unsigned int	rsttiming;	/* 0x90 - Reset Timing  */
-	unsigned int	intr_st;	/* 0x94 - PCU Interrupt Status */
-	unsigned int	rsvd6[2];	/* 0x98-0x9C: Reserved */
-	struct pcs	pcs1;		/* 0xA0-0xB0: PCS1 (clock scaling) */
-	unsigned int	pcsrsvd1[3];	/* 0xB4-0xBC: Reserved */
-	struct pcs	pcs2;		/* 0xC0-0xD0: PCS2 (AHB clock gating) */
-	unsigned int	pcsrsvd2[3];	/* 0xD4-0xDC: Reserved */
-	struct pcs	pcs3;		/* 0xE0-0xF0: PCS3 (APB clock gating) */
-	unsigned int	pcsrsvd3[3];	/* 0xF4-0xFC: Reserved */
-	struct pcs	pcs4;		/* 0x100-0x110: PCS4 main PLL scaling */
-	unsigned int	pcsrsvd4[3];	/* 0x114-0x11C: Reserved */
-	struct pcs	pcs5;		/* 0x120-0x130: PCS5 PCI PLL scaling */
-	unsigned int	pcsrsvd5[3];	/* 0x134-0x13C: Reserved */
-	struct pcs	pcs6;		/* 0x140-0x150: PCS6 AC97 PLL scaling */
-	unsigned int	pcsrsvd6[3];	/* 0x154-0x15C: Reserved */
-	struct pcs	pcs7;		/* 0x160-0x170: PCS7 GMAC PLL scaling */
-	unsigned int	pcsrsvd7[3];	/* 0x174-0x17C: Reserved */
-	struct pcs	pcs8;		/* 0x180-0x190: PCS8 voltage scaling */
-	unsigned int	pcsrsvd8[3];	/* 0x194-0x19C: Reserved */
-	struct pcs	pcs9;		/* 0x1A0-0x1B0: PCS9 power control */
-	unsigned int	pcsrsvd9[93];	/* 0x1B4-0x3FC: Reserved */
-	unsigned int	pmspdm[40];	/* 0x400-0x4fC: Power Manager
-							Scratch Pad Memory 0 */
-};
-#endif /* __ASSEMBLY__ */
-
-/*
- * PCU Revision Register (ro)
- */
-#define ANDES_PCU_REV_NUMBER_PCS(x)	(((x) >> 0) & 0xff)
-#define ANDES_PCU_REV_VER(x)		(((x) >> 16) & 0xffff)
-
-/*
- * Scratch Pad Info Register (ro)
- */
-#define ANDES_PCU_SPINFO_SIZE(x)	(((x) >> 0) & 0xff)
-#define ANDES_PCU_SPINFO_OFFSET(x)	(((x) >> 8) & 0xf)
-
-/*
- * SoC ID Register (ro)
- */
-#define ANDES_PCU_SOC_ID_VER_MINOR(x)	(((x) >> 0) & 0xf)
-#define ANDES_PCU_SOC_ID_VER_MAJOR(x)	(((x) >> 4) & 0xfff)
-#define ANDES_PCU_SOC_ID_DEVICEID(x)	(((x) >> 16) & 0xffff)
-
-/*
- * SoC AHB Configuration Register (ro)
- */
-#define ANDES_PCU_SOC_AHB_AHBC(x)		((x) << 0)
-#define ANDES_PCU_SOC_AHB_APBREG(x)		((x) << 1)
-#define ANDES_PCU_SOC_AHB_APB(x)		((x) << 2)
-#define ANDES_PCU_SOC_AHB_DLM1(x)		((x) << 3)
-#define ANDES_PCU_SOC_AHB_SPIROM(x)		((x) << 4)
-#define ANDES_PCU_SOC_AHB_DDR2C(x)		((x) << 5)
-#define ANDES_PCU_SOC_AHB_DDR2MEM(x)		((x) << 6)
-#define ANDES_PCU_SOC_AHB_DMAC(x)		((x) << 7)
-#define ANDES_PCU_SOC_AHB_DLM2(x)		((x) << 8)
-#define ANDES_PCU_SOC_AHB_GPU(x)		((x) << 9)
-#define ANDES_PCU_SOC_AHB_GMAC(x)		((x) << 12)
-#define ANDES_PCU_SOC_AHB_IDE(x)		((x) << 13)
-#define ANDES_PCU_SOC_AHB_USBOTG(x)		((x) << 14)
-#define ANDES_PCU_SOC_AHB_INTC(x)		((x) << 15)
-#define ANDES_PCU_SOC_AHB_LPCIO(x)		((x) << 16)
-#define ANDES_PCU_SOC_AHB_LPCREG(x)		((x) << 17)
-#define ANDES_PCU_SOC_AHB_PCIIO(x)		((x) << 18)
-#define ANDES_PCU_SOC_AHB_PCIMEM(x)		((x) << 19)
-#define ANDES_PCU_SOC_AHB_L2CC(x)		((x) << 20)
-#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x)		((x) << 27)
-#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x)	((x) << 28)
-#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x)	((x) << 29)
-#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x)	((x) << 30)
-#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x)	((x) << 31)
-
-/*
- * SoC APB Configuration Register (ro)
- */
-#define ANDES_PCU_SOC_APB_CFC(x)	((x) << 1)
-#define ANDES_PCU_SOC_APB_SSP(x)	((x) << 2)
-#define ANDES_PCU_SOC_APB_UART1(x)	((x) << 3)
-#define ANDES_PCU_SOC_APB_SDC(x)	((x) << 5)
-#define ANDES_PCU_SOC_APB_AC97I2S(x)	((x) << 6)
-#define ANDES_PCU_SOC_APB_UART2(x)	((x) << 8)
-#define ANDES_PCU_SOC_APB_PCU(x)	((x) << 16)
-#define ANDES_PCU_SOC_APB_TMR(x)	((x) << 17)
-#define ANDES_PCU_SOC_APB_WDT(x)	((x) << 18)
-#define ANDES_PCU_SOC_APB_RTC(x)	((x) << 19)
-#define ANDES_PCU_SOC_APB_GPIO(x)	((x) << 20)
-#define ANDES_PCU_SOC_APB_I2C(x)	((x) << 22)
-#define ANDES_PCU_SOC_APB_PWM(x)	((x) << 23)
-
-/*
- * Driving Capability and Slew Rate Control Register 0 (rw)
- */
-#define ANDES_PCU_DCSRCR0_TRIAHB(x)	(((x) & 0x1f) << 0)
-#define ANDES_PCU_DCSRCR0_LPC(x)	(((x) & 0xf) << 8)
-#define ANDES_PCU_DCSRCR0_ULPI(x)	(((x) & 0xf) << 12)
-#define ANDES_PCU_DCSRCR0_GMAC(x)	(((x) & 0xf) << 16)
-#define ANDES_PCU_DCSRCR0_GPU(x)	(((x) & 0xf) << 20)
-
-/*
- * Driving Capability and Slew Rate Control Register 1 (rw)
- */
-#define ANDES_PCU_DCSRCR1_I2C(x)	(((x) & 0xf) << 0)
-
-/*
- * Driving Capability and Slew Rate Control Register 2 (rw)
- */
-#define ANDES_PCU_DCSRCR2_UART1(x)	(((x) & 0xf) << 0)
-#define ANDES_PCU_DCSRCR2_UART2(x)	(((x) & 0xf) << 4)
-#define ANDES_PCU_DCSRCR2_AC97(x)	(((x) & 0xf) << 8)
-#define ANDES_PCU_DCSRCR2_SPI(x)	(((x) & 0xf) << 12)
-#define ANDES_PCU_DCSRCR2_SD(x)		(((x) & 0xf) << 16)
-#define ANDES_PCU_DCSRCR2_CFC(x)	(((x) & 0xf) << 20)
-#define ANDES_PCU_DCSRCR2_GPIO(x)	(((x) & 0xf) << 24)
-#define ANDES_PCU_DCSRCR2_PCU(x)	(((x) & 0xf) << 28)
-
-/*
- * Multi-function Port Setting Register 0 (rw)
- */
-#define ANDES_PCU_MFPSR0_PCIMODE(x)		((x) << 0)
-#define ANDES_PCU_MFPSR0_IDEMODE(x)		((x) << 1)
-#define ANDES_PCU_MFPSR0_MINI_TC01(x)		((x) << 2)
-#define ANDES_PCU_MFPSR0_AHB_DEBUG(x)		((x) << 3)
-#define ANDES_PCU_MFPSR0_AHB_TARGET(x)		((x) << 4)
-#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x)		(((x) & 0x7) << 28)
-#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x)	((x) << 31)
-
-/*
- * Multi-function Port Setting Register 1 (rw)
- */
-#define ANDES_PCU_MFPSR1_SUSPEND(x)		((x) << 0)
-#define ANDES_PCU_MFPSR1_PWM0(x)		((x) << 1)
-#define ANDES_PCU_MFPSR1_PWM1(x)		((x) << 2)
-#define ANDES_PCU_MFPSR1_AC97CLKOUT(x)		((x) << 3)
-#define ANDES_PCU_MFPSR1_PWREN(x)		((x) << 4)
-#define ANDES_PCU_MFPSR1_PME(x)			((x) << 5)
-#define ANDES_PCU_MFPSR1_I2C(x)			((x) << 6)
-#define ANDES_PCU_MFPSR1_UART1(x)		((x) << 7)
-#define ANDES_PCU_MFPSR1_UART2(x)		((x) << 8)
-#define ANDES_PCU_MFPSR1_SPI(x)			((x) << 9)
-#define ANDES_PCU_MFPSR1_SD(x)			((x) << 10)
-#define ANDES_PCU_MFPSR1_GPUPLLSRC(x)		((x) << 27)
-#define ANDES_PCU_MFPSR1_DVOMODE(x)		((x) << 28)
-#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x)	((x) << 29)
-#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x)	((x) << 30)
-#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x)	((x) << 31)
-
-/*
- * DMA Engine Selection Register (rw)
- */
-#define ANDES_PCU_DMAES_AC97RX(x)		((x) << 2)
-#define ANDES_PCU_DMAES_AC97TX(x)		((x) << 3)
-#define ANDES_PCU_DMAES_UART1RX(x)		((x) << 4)
-#define ANDES_PCU_DMAES_UART1TX(x)		((x) << 5)
-#define ANDES_PCU_DMAES_UART2RX(x)		((x) << 6)
-#define ANDES_PCU_DMAES_UART2TX(x)		((x) << 7)
-#define ANDES_PCU_DMAES_SDDMA(x)		((x) << 8)
-#define ANDES_PCU_DMAES_CFCDMA(x)		((x) << 9)
-
-/*
- * OSC Control Register (rw)
- */
-#define ANDES_PCU_OSCC_OSCH_OFF(x)	((x) << 0)
-#define ANDES_PCU_OSCC_OSCH_STABLE(x)	((x) << 1)
-#define ANDES_PCU_OSCC_OSCH_TRI(x)	((x) << 2)
-#define ANDES_PCU_OSCC_OSCH_RANGE(x)	(((x) & 0x3) << 4)
-#define ANDES_PCU_OSCC_OSCH2_RANGE(x)	(((x) & 0x3) << 6)
-#define ANDES_PCU_OSCC_OSCH3_RANGE(x)	(((x) & 0x3) << 8)
-
-/*
- * PWM Clock Divider Register (rw)
- */
-#define ANDES_PCU_PWMCD_PWMDIV(x)	(((x) & 0xf) << 0)
-
-/*
- * SoC Misc. Register (rw)
- */
-#define ANDES_PCU_SOCMISC_RSCPUA(x)		((x) << 0)
-#define ANDES_PCU_SOCMISC_RSCPUB(x)		((x) << 1)
-#define ANDES_PCU_SOCMISC_RSPCI(x)		((x) << 2)
-#define ANDES_PCU_SOCMISC_USBWAKE(x)		((x) << 3)
-#define ANDES_PCU_SOCMISC_EXLM_WAITA(x)		(((x) & 0x3) << 4)
-#define ANDES_PCU_SOCMISC_EXLM_WAITB(x)		(((x) & 0x3) << 6)
-#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x)	(((x) << 8)
-#define ANDES_PCU_SOCMISC_300MHZSEL(x)		(((x) << 9)
-#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x)	(((x) << 10)
-#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x)	(((x) << 11)
-#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x)	(((x) << 12)
-#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x)	(((x) << 13)
-#define ANDES_PCU_SOCMISC_ENCPUA(x)		(((x) << 14)
-#define ANDES_PCU_SOCMISC_ENCPUB(x)		(((x) << 15)
-#define ANDES_PCU_SOCMISC_PWON_PWBTN(x)		(((x) << 16)
-#define ANDES_PCU_SOCMISC_PWON_GPIO1(x)		(((x) << 17)
-#define ANDES_PCU_SOCMISC_PWON_GPIO2(x)		(((x) << 18)
-#define ANDES_PCU_SOCMISC_PWON_GPIO3(x)		(((x) << 19)
-#define ANDES_PCU_SOCMISC_PWON_GPIO4(x)		(((x) << 20)
-#define ANDES_PCU_SOCMISC_PWON_GPIO5(x)		(((x) << 21)
-#define ANDES_PCU_SOCMISC_PWON_WOL(x)		(((x) << 22)
-#define ANDES_PCU_SOCMISC_PWON_RTC(x)		(((x) << 23)
-#define ANDES_PCU_SOCMISC_PWON_RTCALM(x)	(((x) << 24)
-#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x)	(((x) << 25)
-#define ANDES_PCU_SOCMISC_PWON_PME(x)		(((x) << 26)
-#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x)	(((x) << 27)
-#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x)	(((x) << 28)
-#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x)	(((x) << 29)
-#define ANDES_PCU_SOCMISC_WD_RESET(x)		(((x) << 30)
-#define ANDES_PCU_SOCMISC_HW_RESET(x)		(((x) << 31)
-
-/*
- * BSM Control Register (rw)
- */
-#define ANDES_PCU_BSMCR_LINK0(x)	(((x) & 0xf) << 0)
-#define ANDES_PCU_BSMCR_LINK1(x)	(((x) & 0xf) << 4)
-#define ANDES_PCU_BSMCR_SYNCSRC(x)	(((x) & 0xf) << 24)
-#define ANDES_PCU_BSMCR_CMD(x)		(((x) & 0x7) << 28)
-#define ANDES_PCU_BSMCR_IE(x)		((x) << 31)
-
-/*
- * BSM Status Register
- */
-#define ANDES_PCU_BSMSR_CI0(x)		(((x) & 0xf) << 0)
-#define ANDES_PCU_BSMSR_CI1(x)		(((x) & 0xf) << 4)
-#define ANDES_PCU_BSMSR_SYNCSRC(x)	(((x) & 0xf) << 24)
-#define ANDES_PCU_BSMSR_BSMST(x)	(((x) & 0xf) << 28)
-
-/*
- * Wakeup Event Sensitivity Register (rw)
- */
-#define ANDES_PCU_WESR_POLOR(x)		(((x) & 0xff) << 0)
-
-/*
- * Wakeup Event Status Register (ro)
- */
-#define ANDES_PCU_WEST_SIG(x)		(((x) & 0xff) << 0)
-
-/*
- * Reset Timing Register
- */
-#define ANDES_PCU_RSTTIMING_RG0(x)	(((x) & 0xff) << 0)
-#define ANDES_PCU_RSTTIMING_RG1(x)	(((x) & 0xff) << 8)
-#define ANDES_PCU_RSTTIMING_RG2(x)	(((x) & 0xff) << 16)
-#define ANDES_PCU_RSTTIMING_RG3(x)	(((x) & 0xff) << 24)
-
-/*
- * PCU Interrupt Status Register
- */
-#define ANDES_PCU_INTR_ST_BSM(x)	((x) << 0)
-#define ANDES_PCU_INTR_ST_PCS1(x)	((x) << 1)
-#define ANDES_PCU_INTR_ST_PCS2(x)	((x) << 2)
-#define ANDES_PCU_INTR_ST_PCS3(x)	((x) << 3)
-#define ANDES_PCU_INTR_ST_PCS4(x)	((x) << 4)
-#define ANDES_PCU_INTR_ST_PCS5(x)	((x) << 5)
-#define ANDES_PCU_INTR_ST_PCS6(x)	((x) << 6)
-#define ANDES_PCU_INTR_ST_PCS7(x)	((x) << 7)
-#define ANDES_PCU_INTR_ST_PCS8(x)	((x) << 8)
-#define ANDES_PCU_INTR_ST_PCS9(x)	((x) << 9)
-
-/*
- * PCSx Configuration Register
- */
-#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x)	(((x) & 0xff) << 0)
-#define ANDES_PCU_PCSX_CR_LW(x)		(((x) & 0xf) << 16)
-#define ANDES_PCU_PCSX_CR_LS(x)		(((x) & 0xf) << 20)
-#define ANDES_PCU_PCSX_CR_TYPE(x)	(((x) >> 28) & 0x7)	/* (ro) */
-
-/*
- * PCSx Parameter Register (rw)
- */
-#define ANDES_PCU_PCSX_PARM_NEXT(x)	(((x) & 0xffffff) << 0)
-#define ANDES_PCU_PCSX_PARM_SYNCSRC(x)	(((x) & 0xf) << 24)
-#define ANDES_PCU_PCSX_PARM_PCSCMD(x)	(((x) & 0x7) << 28)
-#define ANDES_PCU_PCSX_PARM_IE(x)	(((x) << 31)
-
-/*
- * PCSx Status Register 1
- */
-#define ANDES_PCU_PCSX_STAT1_ERRNO(x)	(((x) & 0xf) << 0)
-#define ANDES_PCU_PCSX_STAT1_ST(x)	(((x) & 0x7) << 28)
-
-/*
- * PCSx Status Register 2
- */
-#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x)	(((x) & 0xffffff) << 0)
-#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x)		(((x) & 0xf) << 24)
-
-/*
- * PCSx PDD Register
- * This is reserved for PCS(1-7)
- */
-#define ANDES_PCU_PCS8_PDD_1BYTE(x)		(((x) & 0xff) << 0)
-#define ANDES_PCU_PCS8_PDD_2BYTE(x)		(((x) & 0xff) << 8)
-#define ANDES_PCU_PCS8_PDD_3BYTE(x)		(((x) & 0xff) << 16)
-#define ANDES_PCU_PCS8_PDD_4BYTE(x)		(((x) & 0xff) << 24)
-
-#define ANDES_PCU_PCS9_PDD_TIME1(x)		(((x) & 0x3f) << 0)
-#define ANDES_PCU_PCS9_PDD_TIME2(x)		(((x) & 0x3f) << 6)
-#define ANDES_PCU_PCS9_PDD_TIME3(x)		(((x) & 0x3f) << 12)
-#define ANDES_PCU_PCS9_PDD_TIME4(x)		(((x) & 0x3f) << 18)
-#define ANDES_PCU_PCS9_PDD_TICKTYPE(x)		((x) << 24)
-#define ANDES_PCU_PCS9_PDD_GPU_SRST(x)		((x) << 27)
-#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x)		(((x) & 0x3) << 28)
-#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x)		((x) << 30)
-#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x)	((x) << 31)
-
-#endif	/* __ANDES_PCU_H */
diff --git a/include/android_ab.h b/include/android_ab.h
index 3eb61125c6..1fee7582b9 100644
--- a/include/android_ab.h
+++ b/include/android_ab.h
@@ -30,6 +30,7 @@ struct disk_partition;
  * @param[in] part_info Place to store the partition information
  * Return: The slot number (>= 0) on success, or a negative on error
  */
-int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info);
+int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info,
+                   bool dec_tries);
 
 #endif /* __ANDROID_AB_H */
diff --git a/include/arm_ffa.h b/include/arm_ffa.h
new file mode 100644
index 0000000000..db9b1be995
--- /dev/null
+++ b/include/arm_ffa.h
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#ifndef __ARM_FFA_H
+#define __ARM_FFA_H
+
+#include <linux/printk.h>
+
+/*
+ * This header is public. It can be used by clients to access
+ * data structures and definitions they need
+ */
+
+/*
+ * struct ffa_partition_info - Partition information descriptor
+ * @id:	Partition ID
+ * @exec_ctxt:	Execution context count
+ * @properties:	Partition properties
+ *
+ * Data structure containing information about partitions instantiated in the system
+ * This structure is filled with the data queried by FFA_PARTITION_INFO_GET
+ */
+struct ffa_partition_info {
+	u16 id;
+	u16 exec_ctxt;
+/* partition supports receipt of direct requests */
+#define FFA_PARTITION_DIRECT_RECV	BIT(0)
+/* partition can send direct requests. */
+#define FFA_PARTITION_DIRECT_SEND	BIT(1)
+/* partition can send and receive indirect messages. */
+#define FFA_PARTITION_INDIRECT_MSG	BIT(2)
+	u32 properties;
+};
+
+/*
+ * struct ffa_partition_uuid - 16 bytes UUID transmitted by FFA_PARTITION_INFO_GET
+ * @a1-4:	32-bit words access to the UUID data
+ *
+ */
+struct ffa_partition_uuid {
+	u32 a1; /* w1 */
+	u32 a2; /* w2 */
+	u32 a3; /* w3 */
+	u32 a4; /* w4 */
+};
+
+/**
+ * struct ffa_partition_desc - the secure partition descriptor
+ * @info:	partition information
+ * @sp_uuid:	the secure partition UUID
+ *
+ * Each partition has its descriptor containing the partitions information and the UUID
+ */
+struct ffa_partition_desc {
+	struct ffa_partition_info info;
+	struct ffa_partition_uuid sp_uuid;
+};
+
+/*
+ * struct ffa_send_direct_data - Data structure hosting the data
+ *                                       used by FFA_MSG_SEND_DIRECT_{REQ,RESP}
+ * @data0-4:	Data read/written from/to x3-x7 registers
+ *
+ * Data structure containing the data to be sent by FFA_MSG_SEND_DIRECT_REQ
+ * or read from FFA_MSG_SEND_DIRECT_RESP
+ */
+
+/* For use with FFA_MSG_SEND_DIRECT_{REQ,RESP} which pass data via registers */
+struct ffa_send_direct_data {
+	ulong data0; /* w3/x3 */
+	ulong data1; /* w4/x4 */
+	ulong data2; /* w5/x5 */
+	ulong data3; /* w6/x6 */
+	ulong data4; /* w7/x7 */
+};
+
+struct udevice;
+
+/**
+ * struct ffa_bus_ops - Operations for FF-A
+ * @partition_info_get:	callback for the FFA_PARTITION_INFO_GET
+ * @sync_send_receive:	callback for the FFA_MSG_SEND_DIRECT_REQ
+ * @rxtx_unmap:	callback for the FFA_RXTX_UNMAP
+ *
+ * The data structure providing all the operations supported by the driver.
+ * This structure is EFI runtime resident.
+ */
+struct ffa_bus_ops {
+	int (*partition_info_get)(struct udevice *dev, const char *uuid_str,
+				  u32 *sp_count, struct ffa_partition_desc **sp_descs);
+	int (*sync_send_receive)(struct udevice *dev, u16 dst_part_id,
+				 struct ffa_send_direct_data *msg,
+				 bool is_smc64);
+	int (*rxtx_unmap)(struct udevice *dev);
+};
+
+#define ffa_get_ops(dev)        ((struct ffa_bus_ops *)(dev)->driver->ops)
+
+/**
+ * ffa_rxtx_unmap() - FFA_RXTX_UNMAP driver operation
+ * Please see ffa_unmap_rxtx_buffers_hdlr() description for more details.
+ */
+int ffa_rxtx_unmap(struct udevice *dev);
+
+/**
+ * ffa_unmap_rxtx_buffers_hdlr() - FFA_RXTX_UNMAP handler function
+ * @dev: The arm_ffa bus device
+ *
+ * This function implements FFA_RXTX_UNMAP FF-A function
+ * to unmap the RX/TX buffers
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_unmap_rxtx_buffers_hdlr(struct udevice *dev);
+
+/**
+ * ffa_sync_send_receive() - FFA_MSG_SEND_DIRECT_{REQ,RESP} driver operation
+ * Please see ffa_msg_send_direct_req_hdlr() description for more details.
+ */
+int ffa_sync_send_receive(struct udevice *dev, u16 dst_part_id,
+			  struct ffa_send_direct_data *msg, bool is_smc64);
+
+/**
+ * ffa_msg_send_direct_req_hdlr() - FFA_MSG_SEND_DIRECT_{REQ,RESP} handler function
+ * @dev: The arm_ffa bus device
+ * @dst_part_id: destination partition ID
+ * @msg: pointer to the message data preallocated by the client (in/out)
+ * @is_smc64: select 64-bit or 32-bit FF-A ABI
+ *
+ * This function implements FFA_MSG_SEND_DIRECT_{REQ,RESP}
+ * FF-A functions.
+ *
+ * FFA_MSG_SEND_DIRECT_REQ is used to send the data to the secure partition.
+ * The response from the secure partition is handled by reading the
+ * FFA_MSG_SEND_DIRECT_RESP arguments.
+ *
+ * The maximum size of the data that can be exchanged is 40 bytes which is
+ * sizeof(struct ffa_send_direct_data) as defined by the FF-A specification 1.0
+ * in the section relevant to FFA_MSG_SEND_DIRECT_{REQ,RESP}
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_msg_send_direct_req_hdlr(struct udevice *dev, u16 dst_part_id,
+				 struct ffa_send_direct_data *msg, bool is_smc64);
+
+/**
+ * ffa_partition_info_get() - FFA_PARTITION_INFO_GET driver operation
+ * Please see ffa_get_partitions_info_hdlr() description for more details.
+ */
+int ffa_partition_info_get(struct udevice *dev, const char *uuid_str,
+			   u32 *sp_count, struct ffa_partition_desc **sp_descs);
+
+/**
+ * ffa_get_partitions_info_hdlr() - FFA_PARTITION_INFO_GET handler function
+ *	@uuid_str: pointer to the UUID string
+ *	@sp_count: address of the variable containing the number of partitions matching the UUID
+ *			 The variable is set by the driver
+ *	@sp_descs: address of the descriptors of the partitions matching the UUID
+ *			 The address is set by the driver
+ *
+ * Return the number of partitions and their descriptors matching the UUID
+ *
+ * Query the secure partition data from uc_priv.
+ * If not found, invoke FFA_PARTITION_INFO_GET
+ * FF-A function to query the partition information from secure world.
+ *
+ * A client of the FF-A driver should know the UUID of the service it wants to
+ * access. It should use the UUID to request the FF-A driver to provide the
+ * partition(s) information of the service. The FF-A driver uses
+ * PARTITION_INFO_GET to obtain this information. This is implemented through
+ * ffa_get_partitions_info_hdlr() function.
+ * A new FFA_PARTITION_INFO_GET call is issued (first one performed through
+ * ffa_cache_partitions_info) allowing to retrieve the partition(s) information.
+ * They are not saved (already done). We only update the UUID in the cached area.
+ * This assumes that partitions data does not change in the secure world.
+ * Otherwise u-boot will have an outdated partition data. The benefit of caching
+ * the information in the FF-A driver is to accommodate discovery after
+ * ExitBootServices().
+ *
+ * Return:
+ *
+ * @sp_count: the number of partitions
+ * @sp_descs: address of the partitions descriptors
+ *
+ * On success 0 is returned. Otherwise, failure
+ */
+int ffa_get_partitions_info_hdlr(struct udevice *dev, const char *uuid_str,
+				 u32 *sp_count, struct ffa_partition_desc **sp_descs);
+
+struct ffa_priv;
+
+/**
+ * ffa_set_smc_conduit() - Set the SMC conduit
+ * @dev: The FF-A bus device
+ *
+ * Selects the SMC conduit by setting the FF-A ABI invoke function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_set_smc_conduit(struct udevice *dev);
+
+#endif
diff --git a/include/arm_ffa_priv.h b/include/arm_ffa_priv.h
new file mode 100644
index 0000000000..d564c33c64
--- /dev/null
+++ b/include/arm_ffa_priv.h
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#ifndef __ARM_FFA_PRV_H
+#define __ARM_FFA_PRV_H
+
+#include <mapmem.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+
+/* This header is exclusively used by the FF-A Uclass and FF-A driver(s) */
+
+/* Arm FF-A driver name */
+#define FFA_DRV_NAME "arm_ffa"
+
+/* The FF-A SMC function definitions */
+
+#if CONFIG_IS_ENABLED(SANDBOX)
+
+/* Providing Arm SMCCC declarations to sandbox */
+
+/**
+ * struct sandbox_smccc_1_2_regs - emulated SMC call arguments or results
+ * @a0-a17 argument values from registers 0 to 17
+ */
+struct sandbox_smccc_1_2_regs {
+	ulong a0;
+	ulong a1;
+	ulong a2;
+	ulong a3;
+	ulong a4;
+	ulong a5;
+	ulong a6;
+	ulong a7;
+	ulong a8;
+	ulong a9;
+	ulong a10;
+	ulong a11;
+	ulong a12;
+	ulong a13;
+	ulong a14;
+	ulong a15;
+	ulong a16;
+	ulong a17;
+};
+
+typedef struct sandbox_smccc_1_2_regs ffa_value_t;
+
+#define ARM_SMCCC_FAST_CALL		1UL
+#define ARM_SMCCC_OWNER_STANDARD	4
+#define ARM_SMCCC_SMC_32		0
+#define ARM_SMCCC_SMC_64		1
+#define ARM_SMCCC_TYPE_SHIFT		31
+#define ARM_SMCCC_CALL_CONV_SHIFT	30
+#define ARM_SMCCC_OWNER_MASK		0x3f
+#define ARM_SMCCC_OWNER_SHIFT		24
+#define ARM_SMCCC_FUNC_MASK		0xffff
+
+#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \
+	(((type) << ARM_SMCCC_TYPE_SHIFT) | \
+	((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \
+	(((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \
+	((func_num) & ARM_SMCCC_FUNC_MASK))
+
+#else
+/* CONFIG_ARM64 */
+#include <linux/arm-smccc.h>
+typedef struct arm_smccc_1_2_regs ffa_value_t;
+#endif
+
+/* Defining the function pointer type for the function executing the FF-A ABIs */
+typedef void (*invoke_ffa_fn_t)(ffa_value_t args, ffa_value_t *res);
+
+/* FF-A driver version definitions */
+
+#define MAJOR_VERSION_MASK		GENMASK(30, 16)
+#define MINOR_VERSION_MASK		GENMASK(15, 0)
+#define GET_FFA_MAJOR_VERSION(x)		\
+				((u16)(FIELD_GET(MAJOR_VERSION_MASK, (x))))
+#define GET_FFA_MINOR_VERSION(x)		\
+				((u16)(FIELD_GET(MINOR_VERSION_MASK, (x))))
+#define PACK_VERSION_INFO(major, minor)			\
+	(FIELD_PREP(MAJOR_VERSION_MASK, (major)) |	\
+	 FIELD_PREP(MINOR_VERSION_MASK, (minor)))
+
+#define FFA_MAJOR_VERSION		(1)
+#define FFA_MINOR_VERSION		(0)
+#define FFA_VERSION_1_0		\
+			PACK_VERSION_INFO(FFA_MAJOR_VERSION, FFA_MINOR_VERSION)
+
+/* Endpoint ID mask (u-boot endpoint ID) */
+
+#define GET_SELF_ENDPOINT_ID_MASK		GENMASK(15, 0)
+#define GET_SELF_ENDPOINT_ID(x)		\
+			((u16)(FIELD_GET(GET_SELF_ENDPOINT_ID_MASK, (x))))
+
+#define PREP_SELF_ENDPOINT_ID_MASK		GENMASK(31, 16)
+#define PREP_SELF_ENDPOINT_ID(x)		\
+			(FIELD_PREP(PREP_SELF_ENDPOINT_ID_MASK, (x)))
+
+/* Partition endpoint ID mask  (partition with which u-boot communicates with) */
+
+#define PREP_PART_ENDPOINT_ID_MASK		GENMASK(15, 0)
+#define PREP_PART_ENDPOINT_ID(x)		\
+			(FIELD_PREP(PREP_PART_ENDPOINT_ID_MASK, (x)))
+
+/* Definitions of the Arm FF-A interfaces supported by the Arm FF-A driver */
+
+#define FFA_SMC(calling_convention, func_num)				\
+	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, (calling_convention),	\
+			   ARM_SMCCC_OWNER_STANDARD, (func_num))
+
+#define FFA_SMC_32(func_num)				FFA_SMC(ARM_SMCCC_SMC_32, (func_num))
+#define FFA_SMC_64(func_num)				FFA_SMC(ARM_SMCCC_SMC_64, (func_num))
+
+enum ffa_abis {
+	FFA_ERROR                 = 0x60,
+	FFA_SUCCESS               = 0x61,
+	FFA_INTERRUPT             = 0x62,
+	FFA_VERSION               = 0x63,
+	FFA_FEATURES              = 0x64,
+	FFA_RX_RELEASE            = 0x65,
+	FFA_RXTX_MAP              = 0x66,
+	FFA_RXTX_UNMAP            = 0x67,
+	FFA_PARTITION_INFO_GET    = 0x68,
+	FFA_ID_GET                = 0x69,
+	FFA_RUN                   = 0x6d,
+	FFA_MSG_SEND_DIRECT_REQ   = 0x6f,
+	FFA_MSG_SEND_DIRECT_RESP  = 0x70,
+
+	/* To be updated when adding new FFA IDs */
+	FFA_FIRST_ID              = FFA_ERROR, /* Lowest number ID */
+	FFA_LAST_ID               = FFA_MSG_SEND_DIRECT_RESP, /* Highest number ID */
+};
+
+enum ffa_abi_errcode {
+	NOT_SUPPORTED = 1,
+	INVALID_PARAMETERS,
+	NO_MEMORY,
+	BUSY,
+	INTERRUPTED,
+	DENIED,
+	RETRY,
+	ABORTED,
+	MAX_NUMBER_FFA_ERR
+};
+
+extern int ffa_to_std_errmap[MAX_NUMBER_FFA_ERR];
+
+/* Container structure and helper macros to map between an FF-A error and relevant error log */
+struct ffa_abi_errmap {
+	char *err_str[MAX_NUMBER_FFA_ERR];
+};
+
+#define FFA_ERRMAP_COUNT (FFA_LAST_ID - FFA_FIRST_ID + 1)
+#define FFA_ID_TO_ERRMAP_ID(ffa_id) ((ffa_id) - FFA_FIRST_ID)
+
+/**
+ * enum ffa_rxtx_buf_sizes - minimum sizes supported
+ * for the RX/TX buffers
+ */
+enum ffa_rxtx_buf_sizes {
+	RXTX_4K,
+	RXTX_64K,
+	RXTX_16K
+};
+
+/**
+ * struct ffa_rxtxpair - Hosts the RX/TX buffers virtual addresses
+ * @rxbuf:	virtual address of the RX buffer
+ * @txbuf:	virtual address of the TX buffer
+ * @rxtx_min_pages:	RX/TX buffers minimum size in pages
+ *
+ * Hosts the virtual addresses of the mapped RX/TX buffers
+ * These addresses are used by the FF-A functions that use the RX/TX buffers
+ */
+struct ffa_rxtxpair {
+	void *rxbuf; /* Virtual address returned by memalign */
+	void *txbuf; /* Virtual address returned by memalign */
+	size_t rxtx_min_pages; /* Minimum number of pages in each of the RX/TX buffers */
+};
+
+struct ffa_partition_desc;
+
+/**
+ * struct ffa_partitions - descriptors for all secure partitions
+ * @count:	The number of partitions descriptors
+ * @descs	The partitions descriptors table
+ *
+ * Contains the partitions descriptors table
+ */
+struct ffa_partitions {
+	u32 count;
+	struct ffa_partition_desc *descs; /* Virtual address */
+};
+
+/**
+ * struct ffa_priv - the driver private data structure
+ *
+ * @fwk_version:	FF-A framework version
+ * @emul:	FF-A sandbox emulator
+ * @id:	u-boot endpoint ID
+ * @partitions:	The partitions descriptors structure
+ * @pair:	The RX/TX buffers pair
+ *
+ * The device private data structure containing all the
+ * data read from secure world.
+ */
+struct ffa_priv {
+	u32 fwk_version;
+	struct udevice *emul;
+	u16 id;
+	struct ffa_partitions partitions;
+	struct ffa_rxtxpair pair;
+};
+
+/**
+ * ffa_get_version_hdlr() - FFA_VERSION handler function
+ * @dev: The FF-A bus device
+ *
+ * Implement FFA_VERSION FF-A function
+ * to get from the secure world the FF-A framework version
+ * FFA_VERSION is used to discover the FF-A framework.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_get_version_hdlr(struct udevice *dev);
+
+/**
+ * invoke_ffa_fn() - SMC wrapper
+ * @args: FF-A ABI arguments to be copied to Xn registers
+ * @res: FF-A ABI return data to be copied from Xn registers
+ *
+ * Calls low level SMC implementation.
+ * This function should be implemented by the user driver.
+ */
+void invoke_ffa_fn(ffa_value_t args, ffa_value_t *res);
+
+#endif
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index a1e1b9d640..8fc205ded1 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -301,6 +301,12 @@ struct global_data {
 	 * @timebase_l: low 32 bits of timer
 	 */
 	unsigned int timebase_l;
+	/**
+	 * @malloc_start: start of malloc() region
+	 */
+#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA)
+	unsigned long malloc_start;
+#endif
 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
 	/**
 	 * @malloc_base: base address of early malloc()
@@ -560,6 +566,13 @@ static_assert(sizeof(struct global_data) == GD_SIZE);
 #define gd_event_state()	NULL
 #endif
 
+#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA)
+#define gd_malloc_start()		gd->malloc_start
+#define gd_set_malloc_start(_val)	gd->malloc_start = (_val)
+#else
+#define gd_malloc_start()	0
+#define gd_set_malloc_start(val)
+#endif
 /**
  * enum gd_flags - global data flags
  *
diff --git a/include/asm-generic/types.h b/include/asm-generic/types.h
deleted file mode 100644
index 7c076c56ce..0000000000
--- a/include/asm-generic/types.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_GENERIC_TYPES_H
-#define _ASM_GENERIC_TYPES_H
-/*
- * int-ll64 is used everywhere now.
- */
-#include <asm-generic/int-ll64.h>
-
-#endif /* _ASM_GENERIC_TYPES_H */
diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h
index 3d33a5a063..9e5d93ec30 100644
--- a/include/asm-generic/unaligned.h
+++ b/include/asm-generic/unaligned.h
@@ -1,24 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 #ifndef _GENERIC_UNALIGNED_H
 #define _GENERIC_UNALIGNED_H
 
 #include <asm/byteorder.h>
 
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-/*
- * Select endianness
- */
-#if defined(__LITTLE_ENDIAN)
-#define get_unaligned	__get_unaligned_le
-#define put_unaligned	__put_unaligned_le
-#elif defined(__BIG_ENDIAN)
-#define get_unaligned	__get_unaligned_be
-#define put_unaligned	__put_unaligned_be
-#else
-#error invalid endian
-#endif
+#define __get_unaligned_t(type, ptr) ({						\
+	const struct { type x; } __packed * __pptr = (typeof(__pptr))(ptr);	\
+	__pptr->x;								\
+})
+
+#define __put_unaligned_t(type, val, ptr) do {					\
+	struct { type x; } __packed * __pptr = (typeof(__pptr))(ptr);		\
+	__pptr->x = (val);							\
+} while (0)
+
+#define get_unaligned(ptr)	__get_unaligned_t(typeof(*(ptr)), (ptr))
+#define put_unaligned(val, ptr) __put_unaligned_t(typeof(*(ptr)), (val), (ptr))
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+	return le16_to_cpu(__get_unaligned_t(__le16, p));
+}
+
+static inline u32 get_unaligned_le32(const void *p)
+{
+	return le32_to_cpu(__get_unaligned_t(__le32, p));
+}
+
+static inline u64 get_unaligned_le64(const void *p)
+{
+	return le64_to_cpu(__get_unaligned_t(__le64, p));
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+	__put_unaligned_t(__le16, cpu_to_le16(val), p);
+}
+
+static inline void put_unaligned_le32(u32 val, void *p)
+{
+	__put_unaligned_t(__le32, cpu_to_le32(val), p);
+}
+
+static inline void put_unaligned_le64(u64 val, void *p)
+{
+	__put_unaligned_t(__le64, cpu_to_le64(val), p);
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+	return be16_to_cpu(__get_unaligned_t(__be16, p));
+}
+
+static inline u32 get_unaligned_be32(const void *p)
+{
+	return be32_to_cpu(__get_unaligned_t(__be32, p));
+}
+
+static inline u64 get_unaligned_be64(const void *p)
+{
+	return be64_to_cpu(__get_unaligned_t(__be64, p));
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+	__put_unaligned_t(__be16, cpu_to_be16(val), p);
+}
+
+static inline void put_unaligned_be32(u32 val, void *p)
+{
+	__put_unaligned_t(__be32, cpu_to_be32(val), p);
+}
+
+static inline void put_unaligned_be64(u64 val, void *p)
+{
+	__put_unaligned_t(__be64, cpu_to_be64(val), p);
+}
 
 /* Allow unaligned memory access */
 void allow_unaligned(void);
diff --git a/include/bloblist.h b/include/bloblist.h
index 2a2f1700eb..7ea72c6bd4 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -113,6 +113,7 @@ enum bloblist_tag_t {
 	BLOBLISTT_PROJECT_AREA = 0x8000,
 	BLOBLISTT_U_BOOT_SPL_HANDOFF = 0x8000, /* Hand-off info from SPL */
 	BLOBLISTT_VBE		= 0x8001,	/* VBE per-phase state */
+	BLOBLISTT_U_BOOT_VIDEO = 0x8002, /* Video information from SPL */
 
 	/*
 	 * Vendor-specific tags are permitted here. Projects can be open source
diff --git a/include/bootdev.h b/include/bootdev.h
index e72ef3650f..848233187f 100644
--- a/include/bootdev.h
+++ b/include/bootdev.h
@@ -200,7 +200,7 @@ void bootdev_clear_bootflows(struct udevice *dev);
  * All fields in @bflow must be set up. Note that @bflow->dev is used to add the
  * bootflow to that device.
  *
- * @dev: Bootdevice device to add to
+ * @dev: Bootdev device to add to
  * @bflow: Bootflow to add. Note that fields within bflow must be allocated
  *	since this function takes over ownership of these. This functions makes
  *	a copy of @bflow itself (without allocating its fields again), so the
@@ -371,7 +371,7 @@ int bootdev_next_prio(struct bootflow_iter *iter, struct udevice **devp);
 /**
  * bootdev_setup_for_dev() - Bind a new bootdev device (deprecated)
  *
- * Please use bootdev_setup_sibling_blk() instead since it supports multiple
+ * Please use bootdev_setup_for_sibling_blk() instead since it supports multiple
  * (child) block devices for each media device.
  *
  * Creates a bootdev device as a child of @parent. This should be called from
@@ -386,7 +386,7 @@ int bootdev_next_prio(struct bootflow_iter *iter, struct udevice **devp);
 int bootdev_setup_for_dev(struct udevice *parent, const char *drv_name);
 
 /**
- * bootdev_setup_for_blk() - Bind a new bootdev device for a blk device
+ * bootdev_setup_for_sibling_blk() - Bind a new bootdev device for a blk device
  *
  * Creates a bootdev device as a sibling of @blk. This should be called from
  * the driver's bind() method or its uclass' post_bind() method, at the same
@@ -398,7 +398,7 @@ int bootdev_setup_for_dev(struct udevice *parent, const char *drv_name);
  * @drv_name: Name of bootdev driver to bind
  * Return: 0 if OK, -ve on error
  */
-int bootdev_setup_sibling_blk(struct udevice *blk, const char *drv_name);
+int bootdev_setup_for_sibling_blk(struct udevice *blk, const char *drv_name);
 
 /**
  * bootdev_get_sibling_blk() - Locate the block device for a bootdev
@@ -428,8 +428,8 @@ static inline int bootdev_setup_for_dev(struct udevice *parent,
 	return 0;
 }
 
-static inline int bootdev_setup_sibling_blk(struct udevice *blk,
-					    const char *drv_name)
+static inline int bootdev_setup_for_sibling_blk(struct udevice *blk,
+						const char *drv_name)
 {
 	return 0;
 }
diff --git a/include/bootflow.h b/include/bootflow.h
index f20f575030..4152577afb 100644
--- a/include/bootflow.h
+++ b/include/bootflow.h
@@ -58,7 +58,7 @@ enum bootflow_flags_t {
  *
  * @bm_node: Points to siblings in the same bootdev
  * @glob_node: Points to siblings in the global list (all bootdev)
- * @dev: Bootdevice device which produced this bootflow
+ * @dev: Bootdev device which produced this bootflow
  * @blk: Block device which contains this bootflow, NULL if this is a network
  *	device or sandbox 'host' device
  * @part: Partition number (0 for whole device)
@@ -81,6 +81,8 @@ enum bootflow_flags_t {
  * @fdt_size: Size of FDT file
  * @fdt_addr: Address of loaded fdt
  * @flags: Flags for the bootflow (see enum bootflow_flags_t)
+ * @cmdline: OS command line, or NULL if not known (allocated)
+ * @x86_setup: Pointer to x86 setup block inside @buf, NULL if not present
  */
 struct bootflow {
 	struct list_head bm_node;
@@ -104,6 +106,8 @@ struct bootflow {
 	int fdt_size;
 	ulong fdt_addr;
 	int flags;
+	char *cmdline;
+	char *x86_setup;
 };
 
 /**
@@ -440,4 +444,98 @@ int bootflow_menu_apply_theme(struct expo *exp, ofnode node);
 int bootflow_menu_run(struct bootstd_priv *std, bool text_mode,
 		      struct bootflow **bflowp);
 
+#define BOOTFLOWCL_EMPTY	((void *)1)
+
+/**
+ * cmdline_set_arg() - Update or read an argument in a cmdline string
+ *
+ * Handles updating a single arg in a cmdline string, returning it in a supplied
+ * buffer; also reading an arg from a cmdline string
+ *
+ * When updating, consecutive spaces are squashed as are spaces at the start and
+ * end.
+ *
+ * @buf: Working buffer to use (initial contents are ignored). Use NULL when
+ * reading
+ * @maxlen: Length of working buffer. Use 0 when reading
+ * @cmdline: Command line to update, in the form:
+ *
+ *	fred mary= jane=123 john="has spaces"
+ *
+ * @set_arg: Argument to set or read (may or may not exist)
+ * @new_val: Value for the new argument. May not include quotes (") but may
+ * include embedded spaces, in which case it will be quoted when added to the
+ * command line. Use NULL to delete the argument from @cmdline, BOOTFLOWCL_EMPTY
+ * to set it to an empty value (no '=' sign after arg), "" to add an '=' sign
+ * but with an empty value. Use NULL when reading.
+ * @posp: Ignored when setting an argument; when getting an argument, returns
+ * the start position of its value in @cmdline, after the first quote, if any
+ *
+ * Return:
+ * For updating:
+ *	length of new buffer (including \0 terminator) on success, -ENOENT if
+ *	@new_val is NULL and @set_arg does not exist in @from, -EINVAL if a
+ *	quoted arg-value in @from is not terminated with a quote, -EBADF if
+ *	@new_val has spaces but does not start and end with quotes (or it has
+ *	quotes in the middle of the string), -E2BIG if @maxlen is too small
+ * For reading:
+ *	length of arg value (excluding quotes), -ENOENT if not found
+ */
+int cmdline_set_arg(char *buf, int maxlen, const char *cmdline,
+		    const char *set_arg, const char *new_val, int *posp);
+
+/**
+ * bootflow_cmdline_set_arg() - Set a single argument for a bootflow
+ *
+ * Update the allocated cmdline and set the bootargs variable
+ *
+ * @bflow: Bootflow to update
+ * @arg: Argument to update (e.g. "console")
+ * @val: Value to set (e.g. "ttyS2") or NULL to delete the argument if present,
+ * "" to set it to an empty value (e.g. "console=") and BOOTFLOWCL_EMPTY to add
+ * it without any value ("initrd")
+ * @set_env: true to set the "bootargs" environment variable too
+ *
+ * Return: 0 if OK, -ENOMEM if out of memory
+ */
+int bootflow_cmdline_set_arg(struct bootflow *bflow, const char *arg,
+			     const char *val, bool set_env);
+
+/**
+ * cmdline_get_arg() - Read an argument from a cmdline
+ *
+ * @cmdline: Command line to read, in the form:
+ *
+ *	fred mary= jane=123 john="has spaces"
+ * @arg: Argument to read (may or may not exist)
+ * @posp: Returns position of argument (after any leading quote) if present
+ * Return: Length of argument value excluding quotes if found, -ENOENT if not
+ * found
+ */
+int cmdline_get_arg(const char *cmdline, const char *arg, int *posp);
+
+/**
+ * bootflow_cmdline_get_arg() - Read an argument from a cmdline
+ *
+ * @bootflow: Bootflow to read from
+ * @arg: Argument to read (may or may not exist)
+ * @valp: Returns a pointer to the argument (after any leading quote) if present
+ * Return: Length of argument value excluding quotes if found, -ENOENT if not
+ * found
+ */
+int bootflow_cmdline_get_arg(struct bootflow *bflow, const char *arg,
+			     const char **val);
+
+/**
+ * bootflow_cmdline_auto() - Automatically set a value for a known argument
+ *
+ * This handles a small number of known arguments, for Linux in particular. It
+ * adds suitable kernel parameters automatically, e.g. to enable the console.
+ *
+ * @bflow: Bootflow to update
+ * @arg: Name of argument to set (e.g. "earlycon" or "console")
+ * Return: 0 if OK -ve on error
+ */
+int bootflow_cmdline_auto(struct bootflow *bflow, const char *arg);
+
 #endif
diff --git a/include/bootmeth.h b/include/bootmeth.h
index c3df9702e8..7cb7da33de 100644
--- a/include/bootmeth.h
+++ b/include/bootmeth.h
@@ -263,6 +263,19 @@ int bootmeth_setup_iter_order(struct bootflow_iter *iter, bool include_global);
 int bootmeth_set_order(const char *order_str);
 
 /**
+ * bootmeth_setup_fs() - Set up read to read a file
+ *
+ * We must redo the setup before each filesystem operation. This function
+ * handles that, including setting the filesystem type if a block device is not
+ * being used
+ *
+ * @bflow: Information about file to try
+ * @desc: Block descriptor to read from (NULL if not a block device)
+ * Return: 0 if OK, -ve on error
+ */
+int bootmeth_setup_fs(struct bootflow *bflow, struct blk_desc *desc);
+
+/**
  * bootmeth_try_file() - See we can access a given file
  *
  * Check for a file with a given name. If found, the filename is allocated in
diff --git a/include/bootstd.h b/include/bootstd.h
index dddb3e1538..7802564bcc 100644
--- a/include/bootstd.h
+++ b/include/bootstd.h
@@ -69,7 +69,7 @@ const char *const *const bootstd_get_bootdev_order(struct udevice *dev,
 /**
  * bootstd_get_prefixes() - Get the filename-prefixes list
  *
- * This reads the prefixes, e.g. {"/", "/bpot", NULL}
+ * This reads the prefixes, e.g. {"/", "/boot", NULL}
  *
  * The list is alloced by the bootstd driver so should not be freed. That is the
  * reason for all the const stuff in the function signature
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 9d2a225e7e..2a136b96a6 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -35,11 +35,15 @@
 	#devtypel "_boot=" \
 	BOOTENV_SHARED_BLKDEV_BODY(devtypel)
 
+#define BOOTENV_DEV_BLKDEV_NONE(devtypeu, devtypel, instance)
+
 #define BOOTENV_DEV_BLKDEV(devtypeu, devtypel, instance) \
 	"bootcmd_" #devtypel #instance "=" \
 		"devnum=" #instance "; " \
 		"run " #devtypel "_boot\0"
 
+#define BOOTENV_DEV_NAME_BLKDEV_NONE(devtypeu, devtypel, instance)
+
 #define BOOTENV_DEV_NAME_BLKDEV(devtypeu, devtypel, instance) \
 	#devtypel #instance " "
 
@@ -59,6 +63,10 @@
 #define BOOTENV_SHARED_MMC	BOOTENV_SHARED_BLKDEV(mmc)
 #define BOOTENV_DEV_MMC		BOOTENV_DEV_BLKDEV
 #define BOOTENV_DEV_NAME_MMC	BOOTENV_DEV_NAME_BLKDEV
+#elif defined(CONFIG_SPL_BUILD)
+#define BOOTENV_SHARED_MMC
+#define BOOTENV_DEV_MMC		BOOTENV_DEV_BLKDEV_NONE
+#define BOOTENV_DEV_NAME_MMC	BOOTENV_DEV_NAME_BLKDEV_NONE
 #else
 #define BOOTENV_SHARED_MMC
 #define BOOTENV_DEV_MMC \
@@ -190,6 +198,10 @@
 #define BOOTENV_SHARED_SATA	BOOTENV_SHARED_BLKDEV(sata)
 #define BOOTENV_DEV_SATA	BOOTENV_DEV_BLKDEV
 #define BOOTENV_DEV_NAME_SATA	BOOTENV_DEV_NAME_BLKDEV
+#elif defined(CONFIG_SPL_BUILD)
+#define BOOTENV_SHARED_SATA
+#define BOOTENV_DEV_SATA	BOOTENV_DEV_BLKDEV_NONE
+#define BOOTENV_DEV_NAME_SATA	BOOTENV_DEV_NAME_BLKDEV_NONE
 #else
 #define BOOTENV_SHARED_SATA
 #define BOOTENV_DEV_SATA \
@@ -293,6 +305,11 @@
 		BOOTENV_SHARED_BLKDEV_BODY(usb)
 #define BOOTENV_DEV_USB		BOOTENV_DEV_BLKDEV
 #define BOOTENV_DEV_NAME_USB	BOOTENV_DEV_NAME_BLKDEV
+#elif defined(CONFIG_SPL_BUILD)
+#define BOOTENV_RUN_NET_USB_START
+#define BOOTENV_SHARED_USB
+#define BOOTENV_DEV_USB		BOOTENV_DEV_BLKDEV_NONE
+#define BOOTENV_DEV_NAME_USB	BOOTENV_DEV_NAME_BLKDEV_NONE
 #else
 #define BOOTENV_RUN_NET_USB_START
 #define BOOTENV_SHARED_USB
@@ -395,6 +412,9 @@
 		"\0"
 #define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \
 	"dhcp "
+#elif defined(CONFIG_SPL_BUILD)
+#define BOOTENV_DEV_DHCP	BOOTENV_DEV_BLKDEV_NONE
+#define BOOTENV_DEV_NAME_DHCP	BOOTENV_DEV_NAME_BLKDEV_NONE
 #else
 #define BOOTENV_DEV_DHCP \
 	BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP
@@ -413,6 +433,9 @@
 		"fi\0"
 #define BOOTENV_DEV_NAME_PXE(devtypeu, devtypel, instance) \
 	"pxe "
+#elif defined(CONFIG_SPL_BUILD)
+#define BOOTENV_DEV_PXE		BOOTENV_DEV_BLKDEV_NONE
+#define BOOTENV_DEV_NAME_PXE	BOOTENV_DEV_NAME_BLKDEV_NONE
 #else
 #define BOOTENV_DEV_PXE \
 	BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 7ee46abffd..284291af2f 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2023 NXP
  */
 
 /*
@@ -283,7 +283,9 @@
 #define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /* Serial Port */
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
 #define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#endif
 
 #define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index f196bd76e6..01db298f38 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2023 NXP
  */
 
 #ifndef __CONFIG_H
@@ -238,7 +238,9 @@
  * open - index 2
  * shorted - index 1
  */
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
 #define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#endif
 
 #define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index f213d2de77..0b9dde3e0e 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2023 NXP
  */
 
 /*
@@ -215,7 +215,9 @@
 /*
  * Serial Port
  */
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
 #define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#endif
 #define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 506f1b7e26..78e136224e 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2023 NXP
  */
 
 /*
@@ -77,7 +77,9 @@
  * open - index 2
  * shorted - index 1
  */
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
 #define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#endif
 
 #define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
diff --git a/include/configs/ae350.h b/include/configs/ae350.h
index b566ecf296..23e4801379 100644
--- a/include/configs/ae350.h
+++ b/include/configs/ae350.h
@@ -83,11 +83,15 @@
 #include <config_distro_bootcmd.h>
 
 #define CFG_EXTRA_ENV_SETTINGS	\
-				"kernel_addr_r=0x00080000\0" \
-				"pxefile_addr_r=0x01f00000\0" \
-				"scriptaddr=0x01f00000\0" \
-				"fdt_addr_r=0x02000000\0" \
-				"ramdisk_addr_r=0x02800000\0" \
+				"fdt_high=0xffffffffffffffff\0" \
+				"initrd_high=0xffffffffffffffff\0" \
+				"kernel_addr_r=0x00600000\0" \
+				"kernel_comp_addr_r=0x04600000\0" \
+				"kernel_comp_size=0x04000000\0" \
+				"pxefile_addr_r=0x08600000\0" \
+				"scriptaddr=0x08700000\0" \
+				"fdt_addr_r=0x08800000\0" \
+				"ramdisk_addr_r=0x08900000\0" \
 				BOOTENV
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 5b47778517..504b1f0228 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -76,7 +76,7 @@
 #include <config_distro_bootcmd.h>
 
 #ifndef CONFIG_SPL_BUILD
-#include <environment/ti/dfu.h>
+#include <env/ti/dfu.h>
 
 #define CFG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index a2f73c4754..7ee7b7e4f4 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -64,7 +64,7 @@
 #include <config_distro_bootcmd.h>
 
 #ifndef CONFIG_SPL_BUILD
-#include <environment/ti/dfu.h>
+#include <env/ti/dfu.h>
 
 #define CFG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index ba91f2b054..06edde6902 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -11,7 +11,7 @@
 #ifndef __CONFIG_AM57XX_EVM_H
 #define __CONFIG_AM57XX_EVM_H
 
-#include <environment/ti/dfu.h>
+#include <env/ti/dfu.h>
 #include <linux/sizes.h>
 
 #define CFG_SYS_NS16550_COM1		UART1_BASE	/* Base EVM has UART0 */
diff --git a/include/configs/am62ax_evm.h b/include/configs/am62ax_evm.h
index d8ef2509a8..57003f120f 100644
--- a/include/configs/am62ax_evm.h
+++ b/include/configs/am62ax_evm.h
@@ -9,83 +9,12 @@
 #define __CONFIG_AM62AX_EVM_H
 
 #include <linux/sizes.h>
-#include <environment/ti/mmc.h>
-#include <environment/ti/k3_dfu.h>
+#include <env/ti/mmc.h>
+#include <env/ti/k3_dfu.h>
 
 /* DDR Configuration */
 #define CFG_SYS_SDRAM_BASE1		0x880000000
 
-#define PARTS_DEFAULT \
-	/* Linux partitions */ \
-	"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
-
-/* U-Boot general configuration */
-#define EXTRA_ENV_AM62A7_BOARD_SETTINGS					\
-	"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"	\
-	"findfdt="							\
-		"setenv name_fdt ${default_device_tree};"		\
-		"setenv fdtfile ${name_fdt}\0"				\
-	"name_kern=Image\0"						\
-	"console=ttyS2,115200n8\0"					\
-	"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 "	\
-		"${mtdparts}\0"						\
-	"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
-
-/* U-Boot MMC-specific configuration */
-#define EXTRA_ENV_AM62A7_BOARD_SETTINGS_MMC				\
-	"boot=mmc\0"							\
-	"mmcdev=1\0"							\
-	"bootpart=1:2\0"						\
-	"bootdir=/boot\0"						\
-	"rd_spec=-\0"							\
-	"init_mmc=run args_all args_mmc\0"				\
-	"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
-	"get_overlay_mmc="						\
-		"fdt address ${fdtaddr};"				\
-		"fdt resize 0x100000;"					\
-		"for overlay in $name_overlays;"			\
-		"do;"							\
-		"load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && "	\
-		"fdt apply ${dtboaddr};"				\
-		"done;\0"						\
-	"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "		\
-		"${bootdir}/${name_kern}\0"				\
-	"get_fit_mmc=load mmc ${bootpart} ${addr_fit} "			\
-		"${bootdir}/${name_fit}\0"				\
-	"partitions=" PARTS_DEFAULT
-
-#define BOOTENV_DEV_TI_MMC(devtypeu, devtypel, instance)		\
-	DEFAULT_MMC_TI_ARGS						\
-	EXTRA_ENV_AM62A7_BOARD_SETTINGS_MMC				\
-	"bootcmd_ti_mmc="						\
-		"run findfdt; run envboot; run init_mmc;"		\
-		"if test ${boot_fit} -eq 1; then;"			\
-			"run get_fit_mmc; run get_overlaystring;"	\
-			"run run_fit;"					\
-		"else;"							\
-			"run get_kern_mmc; run get_fdt_mmc;"		\
-			"run get_overlay_mmc;"				\
-			"run run_kern;"					\
-		"fi;\0"
-
-#define BOOTENV_DEV_NAME_TI_MMC(devtyeu, devtypel, instance)		\
-	"ti_mmc "
-
-#if IS_ENABLED(CONFIG_CMD_MMC)
-	#define BOOT_TARGET_MMC(func)					\
-		func(TI_MMC, ti_mmc, na)
-#else
-	#define BOOT_TARGET_MMC(func)
-#endif /* IS_ENABLED(CONFIG_CMD_MMC) */
-
-#define BOOT_TARGET_DEVICES(func)					\
-	BOOT_TARGET_MMC(func)
-
-#include <config_distro_bootcmd.h>
-
-/* Incorporate settings into the U-Boot environment */
-#define CFG_EXTRA_ENV_SETTINGS					\
-	BOOTENV
 
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h
index 7bf07809b0..44180dc768 100644
--- a/include/configs/am62x_evm.h
+++ b/include/configs/am62x_evm.h
@@ -10,38 +10,11 @@
 #define __CONFIG_AM625_EVM_H
 
 #include <config_distro_bootcmd.h>
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
 
 /* DDR Configuration */
 #define CFG_SYS_SDRAM_BASE1		0x880000000
 
-#ifdef CONFIG_CMD_MMC
-#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
-#else
-#define DISTRO_BOOT_DEV_MMC(func)
-#endif
-
-#ifdef CONFIG_CMD_PXE
-#define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na)
-#else
-#define DISTRO_BOOT_DEV_PXE(func)
-#endif
-
-#ifdef CONFIG_CMD_DHCP
-#define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na)
-#else
-#define DISTRO_BOOT_DEV_DHCP(func)
-#endif
-
-#define BOOT_TARGET_DEVICES(func) \
-	DISTRO_BOOT_DEV_MMC(func) \
-	DISTRO_BOOT_DEV_PXE(func) \
-	DISTRO_BOOT_DEV_DHCP(func)
-
-/* Incorporate settings into the U-Boot environment */
-#define CFG_EXTRA_ENV_SETTINGS					\
-	BOOTENV
-
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
 
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index 1e37ab47b9..062102a610 100644
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h
@@ -11,9 +11,9 @@
 
 #include <linux/sizes.h>
 #include <config_distro_bootcmd.h>
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
 #include <asm/arch/am64_hardware.h>
-#include <environment/ti/k3_dfu.h>
+#include <env/ti/k3_dfu.h>
 
 /* DDR Configuration */
 #define CFG_SYS_SDRAM_BASE1		0x880000000
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index c54957300a..9e90239a1c 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -10,27 +10,13 @@
 #define __CONFIG_AM654_EVM_H
 
 #include <linux/sizes.h>
-#include <environment/ti/mmc.h>
-#include <environment/ti/k3_rproc.h>
-#include <environment/ti/k3_dfu.h>
+#include <env/ti/mmc.h>
+#include <env/ti/k3_rproc.h>
+#include <env/ti/k3_dfu.h>
 
 /* DDR Configuration */
 #define CFG_SYS_SDRAM_BASE1		0x880000000
 
-#ifdef CONFIG_TARGET_AM654_A53_EVM
-#define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 1) \
-	func(MMC, mmc, 0)
-
-#include <config_distro_bootcmd.h>
-#else
-#define BOOTENV
-#endif
-
-/* Incorporate settings into the U-Boot environment */
-#define CFG_EXTRA_ENV_SETTINGS					\
-	BOOTENV
-
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
 
diff --git a/include/configs/arbel.h b/include/configs/arbel.h
index 8e27fb52a1..891257bc93 100644
--- a/include/configs/arbel.h
+++ b/include/configs/arbel.h
@@ -7,12 +7,13 @@
 #define __CONFIG_ARBEL_H
 
 #define CFG_SYS_SDRAM_BASE		0x0
-#define CFG_SYS_BOOTMAPSZ		(20 << 20)
+#define CFG_SYS_BOOTMAPSZ		(30 << 20)
+#define CFG_SYS_BOOTM_LEN		(20 << 20)
 #define CFG_SYS_INIT_RAM_ADDR	CFG_SYS_SDRAM_BASE
 #define CFG_SYS_INIT_RAM_SIZE	0x8000
 
 /* Default environemnt variables */
-#define CFG_EXTRA_ENV_SETTINGS   "uimage_flash_addr=80200000\0"   \
+#define CFG_EXTRA_ENV_SETTINGS   "uimage_flash_addr=80400000\0"   \
 		"stdin=serial\0"   \
 		"stdout=serial\0"   \
 		"stderr=serial\0"    \
diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h
index b0df328cd8..9b0f5cedcd 100644
--- a/include/configs/bayleybay.h
+++ b/include/configs/bayleybay.h
@@ -2,20 +2,3 @@
 /*
  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS	"stdin=serial,usbkbd\0" \
-					"stdout=serial,vidconsole\0" \
-					"stderr=serial,vidconsole\0"
-
-/* Environment configuration */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/cherryhill.h b/include/configs/cherryhill.h
index d6ce70a96a..a3009571de 100644
--- a/include/configs/cherryhill.h
+++ b/include/configs/cherryhill.h
@@ -2,16 +2,3 @@
 /*
  * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
  */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS	"stdin=usbkbd,serial\0" \
-					"stdout=vidconsole,serial\0" \
-					"stderr=vidconsole,serial\0"
-
-/* Environment configuration */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h
index 60617e6fec..03c364f29f 100644
--- a/include/configs/conga-qeval20-qa3-e3845.h
+++ b/include/configs/conga-qeval20-qa3-e3845.h
@@ -16,8 +16,6 @@
 					"stdout=serial\0" \
 					"stderr=serial\0"
 
-#define VIDEO_IO_OFFSET				0
-
 #undef CFG_EXTRA_ENV_SETTINGS
 #define CFG_EXTRA_ENV_SETTINGS				\
 	"kernel-ver=4.4.0-22\0"					\
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index b4f49bf528..e00c408f29 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -2,23 +2,3 @@
 /*
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define SPLASH_SETTINGS "splashsource=virtio_fs\0" \
-	"splashimage=0x1000000\0"
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd,usbkbd\0" \
-					"stdout=serial,vidconsole\0" \
-					"stderr=serial,vidconsole\0"
-
-/* ATA/IDE support */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h
index 31639e48da..0406786f7c 100644
--- a/include/configs/cougarcanyon2.h
+++ b/include/configs/cougarcanyon2.h
@@ -2,16 +2,3 @@
 /*
  * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd,usbkbd\0" \
-					"stdout=serial,vga\0" \
-					"stderr=serial,vga\0"
-
-/* Environment configuration */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index 387bb8800e..0c842dd01e 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -2,20 +2,3 @@
 /*
  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
  */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd,usbkbd\0" \
-					"stdout=serial,vidconsole\0" \
-					"stderr=serial,vidconsole\0"
-
-/* Environment configuration */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 736af88a02..cef404218e 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -143,7 +143,7 @@
 	"fdtaddr=0xc0600000\0" \
 	"scriptaddr=0xc0600000\0"
 
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
 
 #define CFG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h
index 05389a435b..be095e28a1 100644
--- a/include/configs/dfi-bt700.h
+++ b/include/configs/dfi-bt700.h
@@ -20,8 +20,6 @@
 					"stdout=serial\0" \
 					"stderr=serial\0"
 
-#define VIDEO_IO_OFFSET				0
-
 #undef CFG_EXTRA_ENV_SETTINGS
 #define CFG_EXTRA_ENV_SETTINGS				\
 	"kernel-ver=4.4.0-24\0"					\
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index ef1d5a1126..633ec1f32f 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -11,7 +11,7 @@
 #ifndef __CONFIG_DRA7XX_EVM_H
 #define __CONFIG_DRA7XX_EVM_H
 
-#include <environment/ti/dfu.h>
+#include <env/ti/dfu.h>
 
 #define CFG_MAX_MEM_MAPPED		0x80000000
 
diff --git a/include/configs/eagle.h b/include/configs/eagle.h
deleted file mode 100644
index c751f75a7d..0000000000
--- a/include/configs/eagle.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * include/configs/eagle.h
- *     This file is Eagle board configuration.
- *
- * Copyright (C) 2015 Renesas Electronics Corporation
- */
-
-#ifndef __EAGLE_H
-#define __EAGLE_H
-
-#include "rcar-gen3-common.h"
-
-/* Environment compatibility */
-
-/* Board Clock */
-/* XTAL_CLK : 33.33MHz */
-
-#endif /* __EAGLE_H */
diff --git a/include/configs/edison.h b/include/configs/edison.h
index 455a889b64..127c2c4546 100644
--- a/include/configs/edison.h
+++ b/include/configs/edison.h
@@ -2,14 +2,3 @@
 /*
  * Copyright (c) 2017 Intel Corp.
  */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/ibmpc.h>
-
-/* Miscellaneous configurable options */
-
-#define CFG_SYS_STACK_SIZE			(32 * 1024)
-
-#endif
diff --git a/include/configs/efi-x86_app.h b/include/configs/efi-x86_app.h
index 843ed8b9d1..d5824049d6 100644
--- a/include/configs/efi-x86_app.h
+++ b/include/configs/efi-x86_app.h
@@ -2,14 +2,3 @@
 /*
  * Copyright (c) 2015 Google, Inc
  */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS	"stdin=serial\0" \
-					"stdout=vidconsole\0" \
-					"stderr=vidconsole\0"
-
-#endif
diff --git a/include/configs/efi-x86_payload.h b/include/configs/efi-x86_payload.h
index c72b067c36..e00c408f29 100644
--- a/include/configs/efi-x86_payload.h
+++ b/include/configs/efi-x86_payload.h
@@ -2,20 +2,3 @@
 /*
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd,usbkbd\0" \
-					"stdout=serial,vidconsole\0" \
-					"stderr=serial,vidconsole\0"
-
-/* ATA/IDE support */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index 0380ac287b..9b0f5cedcd 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -2,22 +2,3 @@
 /*
  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-/* ns16550 UART is memory-mapped in Quark SoC */
-
-#define CFG_STD_DEVICES_SETTINGS	"stdin=serial\0" \
-					"stdout=serial\0" \
-					"stderr=serial\0"
-
-/* Environment configuration */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
index d85ae21e23..fa20651d2d 100644
--- a/include/configs/imx8mm_beacon.h
+++ b/include/configs/imx8mm_beacon.h
@@ -9,8 +9,17 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
+#define UBOOT_ITB_OFFSET			0x57C00
+#define FSPI_CONF_BLOCK_SIZE		0x1000
+#define UBOOT_ITB_OFFSET_FSPI  \
+	(UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE)
+#ifdef CONFIG_FSPI_CONF_HEADER
+#define CFG_SYS_UBOOT_BASE  \
+	(QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI)
+#else
 #define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#endif
 
 #ifdef CONFIG_SPL_BUILD
 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
@@ -19,56 +28,6 @@
 
 #endif
 
-/* Initial environment variables */
-#define CFG_EXTRA_ENV_SETTINGS		\
-	"script=boot.scr\0" \
-	"image=Image\0" \
-	"console=ttymxc1,115200\0" \
-	"fdt_addr=0x43000000\0"			\
-	"boot_fit=try\0" \
-	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
-	"initrd_addr=0x43800000\0"		\
-	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
-	"mmcpart=1\0" \
-	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
-	"mmcautodetect=yes\0" \
-	"mmcargs=setenv bootargs console=${console},${baudrate}" \
-	" root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \
-	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
-	" ${script};\0" \
-	"bootscript=echo Running bootscript from mmc ...; " \
-		"source\0" \
-	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run finduuid; " \
-		"run mmcargs; " \
-		"if run loadfdt; then " \
-			"booti ${loadaddr} - ${fdt_addr}; " \
-		"else " \
-			"echo WARN: Cannot load the DT; " \
-		"fi; " \
-	"netargs=setenv bootargs console=${console} " \
-		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-	"netboot=echo Booting from net ...; " \
-		"run netargs;  " \
-		"if test ${ip_dyn} = yes; then " \
-			"setenv get_cmd dhcp; " \
-		"else " \
-			"setenv get_cmd tftp; " \
-		"fi; " \
-		"${get_cmd} ${loadaddr} ${image}; " \
-		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
-			"bootm ${loadaddr}; " \
-		"else " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"booti ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"echo WARN: Cannot load the DT; " \
-			"fi; " \
-		"fi;\0"
-
 /* Link Definitions */
 
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h
index 5579a05d16..046d5685d0 100644
--- a/include/configs/imx8mm_venice.h
+++ b/include/configs/imx8mm_venice.h
@@ -26,16 +26,16 @@
 	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
-	"splblk=0x42\0" \
 	BOOTENV
 
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
 #define CFG_SYS_INIT_RAM_SIZE        SZ_2M
 
+/* SDRAM configuration: 4GiB */
 #define CFG_SYS_SDRAM_BASE           0x40000000
-
-/* SDRAM configuration */
-#define PHYS_SDRAM                      0x40000000
-#define PHYS_SDRAM_SIZE			SZ_4G
+#define PHYS_SDRAM                   0x40000000
+#define PHYS_SDRAM_SIZE              0x80000000      /* 2 GB */
+#define PHYS_SDRAM_2                 0xC0000000
+#define PHYS_SDRAM_2_SIZE            0x80000000      /* 2 GB */
 
 #endif
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
index 1880d0311e..699e209044 100644
--- a/include/configs/imx8mn_beacon.h
+++ b/include/configs/imx8mn_beacon.h
@@ -12,67 +12,6 @@
 #define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
-/* Initial environment variables */
-#define CFG_EXTRA_ENV_SETTINGS		\
-	"script=boot.scr\0" \
-	"image=Image\0" \
-	"ramdiskimage=rootfs.cpio.uboot\0" \
-	"console=ttymxc1,115200\0" \
-	"fdt_addr=0x43000000\0"			\
-	"ramdisk_addr=0x44000000\0" \
-	"boot_fdt=try\0" \
-	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
-	"initrd_addr=0x43800000\0"		\
-	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
-	"mmcpart=1\0" \
-	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
-	"mmcautodetect=yes\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-	" root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \
-	"ramargs=setenv bootargs console=${console} root=/dev/ram rw " \
-	" ${optargs}\0" \
-	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
-	"bootscript=echo Running bootscript from mmc ...; " \
-		"source\0" \
-	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-	"loadramdisk=load mmc ${mmcdev} ${ramdisk_addr} ${ramdiskimage}\0"\
-	"mmcboot=echo Booting from mmc ...; " \
-		"run finduuid; run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"booti ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"echo WARN: Cannot load the DT; " \
-			"fi; " \
-		"else " \
-			"echo wait for boot; " \
-		"fi;\0" \
-	"netargs=setenv bootargs console=${console} " \
-		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-	"netboot=echo Booting from net ...; " \
-		"run netargs;  " \
-		"if test ${ip_dyn} = yes; then " \
-			"setenv get_cmd dhcp; " \
-		"else " \
-			"setenv get_cmd tftp; " \
-		"fi; " \
-		"${get_cmd} ${loadaddr} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"booti ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"echo WARN: Cannot load the DT; " \
-			"fi; " \
-		"else " \
-			"booti; " \
-		"fi;\0" \
-	"ramboot=echo Booting from RAMdisk...; "\
-		"run loadimage; run loadfdt; fdt addr $fdt_addr; "\
-		"run loadramdisk; run ramargs; " \
-		"booti ${loadaddr} ${ramdisk_addr} ${fdt_addr} ${optargs}\0"
-
 /* Link Definitions */
 
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h
index 80c2df9f30..1cc054a82b 100644
--- a/include/configs/imx8mn_venice.h
+++ b/include/configs/imx8mn_venice.h
@@ -20,16 +20,16 @@
 	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
-	"splblk=0x40\0" \
 	BOOTENV
 
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
 #define CFG_SYS_INIT_RAM_SIZE        SZ_2M
 
+/* SDRAM configuration: 4GiB */
 #define CFG_SYS_SDRAM_BASE           0x40000000
-
-/* SDRAM configuration */
-#define PHYS_SDRAM                      0x40000000
-#define PHYS_SDRAM_SIZE			SZ_4G
+#define PHYS_SDRAM                   0x40000000
+#define PHYS_SDRAM_SIZE              0x80000000      /* 2 GB */
+#define PHYS_SDRAM_2                 0xC0000000
+#define PHYS_SDRAM_2_SIZE            0x80000000      /* 2 GB */
 
 #endif
diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h
index 4b32d5a77e..47413ecd7f 100644
--- a/include/configs/imx8mp_venice.h
+++ b/include/configs/imx8mp_venice.h
@@ -20,16 +20,16 @@
 	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
-	"splblk=0x40\0" \
 	BOOTENV
 
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
 #define CFG_SYS_INIT_RAM_SIZE        SZ_2M
 
+/* SDRAM configuration: 4GiB */
 #define CFG_SYS_SDRAM_BASE           0x40000000
-
-/* SDRAM configuration */
-#define PHYS_SDRAM                      0x40000000
-#define PHYS_SDRAM_SIZE			SZ_4G
+#define PHYS_SDRAM                   0x40000000
+#define PHYS_SDRAM_SIZE              0x80000000      /* 2 GB */
+#define PHYS_SDRAM_2                 0xC0000000
+#define PHYS_SDRAM_2_SIZE            0x80000000      /* 2 GB */
 
 #endif
diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h
index 82174b8678..4968722d18 100644
--- a/include/configs/iot2050.h
+++ b/include/configs/iot2050.h
@@ -13,32 +13,18 @@
 
 #include <linux/sizes.h>
 
-#if IS_ENABLED(CONFIG_CMD_USB)
-# define BOOT_TARGET_USB(func) \
-	func(USB, usb, 0) \
-	func(USB, usb, 1) \
-	func(USB, usb, 2)
-#else
-# define BOOT_TARGET_USB(func)
-#endif
+#include <configs/ti_armv7_common.h>
 
 /*
  * This defines all MMC devices, even if the basic variant has no mmc1.
  * The non-supported device will be removed from the boot targets during
  * runtime, when that board was detected.
  */
+#undef BOOT_TARGET_DEVICES
 #define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 1) \
-	func(MMC, mmc, 0) \
-	BOOT_TARGET_USB(func)
-
-#include <config_distro_bootcmd.h>
-
-#define CFG_EXTRA_ENV_SETTINGS						\
-	DEFAULT_LINUX_BOOT_ENV						\
-	BOOTENV
-
-#include <configs/ti_armv7_common.h>
+       func(MMC, mmc, 1) \
+       func(MMC, mmc, 0) \
+       BOOT_TARGET_USB(func)
 
 #ifdef CONFIG_ENV_WRITEABLE_LIST
 #define CFG_ENV_FLAGS_LIST_STATIC					\
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index de92cd48fb..ea39d1bf82 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -24,40 +24,8 @@
 #define CFG_SYS_UBOOT_BASE		0x50080000
 #endif
 
-#if CONFIG_IS_ENABLED(CMD_PXE)
-# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
-#else
-# define BOOT_TARGET_PXE(func)
-#endif
-
-#if CONFIG_IS_ENABLED(CMD_DHCP)
-# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
-#else
-# define BOOT_TARGET_DHCP(func)
-#endif
-
-#ifdef CONFIG_CMD_USB
-# define BOOT_TARGET_USB(func)	func(USB, usb, 0)
-#else
-# define BOOT_TARGET_USB(func)
-#endif
-
-#define BOOT_TARGET_DEVICES(func) \
-	BOOT_TARGET_USB(func) \
-	func(MMC, mmc, 1) \
-	func(MMC, mmc, 0) \
-	BOOT_TARGET_PXE(func) \
-	BOOT_TARGET_DHCP(func)
-
-#include <config_distro_bootcmd.h>
-
-/* Incorporate settings into the U-Boot environment */
-#define CFG_EXTRA_ENV_SETTINGS					\
-	BOOTENV
-
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
 
-/* MMC ENV related defines */
 
 #endif /* __CONFIG_J721E_EVM_H */
diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h
index 1e0da9f96c..692c6bb5e4 100644
--- a/include/configs/j721s2_evm.h
+++ b/include/configs/j721s2_evm.h
@@ -23,12 +23,7 @@
 #define CFG_SYS_UBOOT_BASE		0x50080000
 #endif
 
-/* Incorporate settings into the U-Boot environment */
-#define CFG_EXTRA_ENV_SETTINGS
-
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
 
-/* MMC ENV related defines */
-
 #endif /* __CONFIG_J721S2_EVM_H */
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 929c9a26de..5cdd87c0a1 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -9,33 +9,8 @@
 #ifndef __CONFIG_K2E_EVM_H
 #define __CONFIG_K2E_EVM_H
 
-#include <environment/ti/spi.h>
-
-#ifdef CONFIG_TI_SECURE_DEVICE
-#define DEFAULT_SEC_BOOT_ENV						\
-	DEFAULT_FIT_TI_ARGS						\
-	"findfdt=setenv fdtfile ${name_fdt}\0"
-#else
-#define DEFAULT_SEC_BOOT_ENV
-#endif
-
-/* U-Boot general configuration */
-#define ENV_KS2_BOARD_SETTINGS						\
-	DEFAULT_FW_INITRAMFS_BOOT_ENV					\
-	DEFAULT_SEC_BOOT_ENV						\
-	"boot=ubi\0"							\
-	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
-	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
-	"name_fdt=keystone-k2e-evm.dtb\0"				\
-	"name_mon=skern-k2e.bin\0"					\
-	"name_ubi=k2e-evm-ubifs.ubi\0"					\
-	"name_uboot=u-boot-spi-k2e-evm.gph\0"				\
-	"name_fs=arago-console-image-k2e-evm.cpio.gz\0"
-
 #include <configs/ti_armv7_keystone2.h>
 
-#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
-
 /* Network */
 #define CFG_KSNET_CPSW_NUM_PORTS	9
 
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index d0634a99f4..2f25d393a3 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -9,53 +9,10 @@
 #ifndef __CONFIG_K2G_EVM_H
 #define __CONFIG_K2G_EVM_H
 
-#include <environment/ti/mmc.h>
-#include <environment/ti/spi.h>
-
-/* U-Boot general configuration */
-#define ENV_KS2_BOARD_SETTINGS						\
-	DEFAULT_MMC_TI_ARGS						\
-	DEFAULT_PMMC_BOOT_ENV						\
-	DEFAULT_FW_INITRAMFS_BOOT_ENV					\
-	DEFAULT_FIT_TI_ARGS						\
-	"boot=mmc\0"							\
-	"console=ttyS0,115200n8\0"					\
-	"bootpart=0:2\0"						\
-	"bootdir=/boot\0"						\
-	"rd_spec=-\0"							\
-	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
-	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
-	"findfdt="\
-		"if test $board_name = 66AK2GGP; then " \
-			 "setenv name_fdt keystone-k2g-evm.dtb; " \
-		"else if test $board_name = 66AK2GG1; then " \
-			"setenv name_fdt keystone-k2g-evm.dtb; " \
-		"else if test $board_name = 66AK2GIC; then " \
-			 "setenv name_fdt keystone-k2g-ice.dtb; " \
-		"else if test $board_name = 66AK2GI1; then " \
-			 "setenv name_fdt keystone-k2g-ice.dtb; " \
-		"else if test $name_fdt = undefined; then " \
-			"echo WARNING: Could not determine device tree to use;"\
-		"fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \
-	"name_mon=skern-k2g.bin\0"					\
-	"name_ubi=k2g-evm-ubifs.ubi\0"					\
-	"name_uboot=u-boot-spi-k2g-evm.gph\0"				\
-	"init_mmc=run args_all args_mmc\0"				\
-	"init_fw_rd_mmc=load mmc ${bootpart} ${rdaddr} "		\
-		"${bootdir}/${name_fw_rd}; run set_rd_spec\0"		\
-	"soc_variant=k2g\0"						\
-	"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0"\
-	"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "		\
-		"${bootdir}/${name_kern}\0"				\
-	"get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\
-	"name_fs=arago-base-tisdk-image-k2g-evm.cpio\0"
-
 /* Network */
 #define CFG_KSNET_CPSW_NUM_PORTS	2
 #define PHY_ANEG_TIMEOUT	10000 /* PHY needs longer aneg time */
 
-#define SPI_MTD_PARTS	KEYSTONE_SPI1_MTD_PARTS
-
 #include <configs/ti_armv7_keystone2.h>
 
 #endif /* __CONFIG_K2G_EVM_H */
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 05b4a3c204..5e52bbb98f 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -9,33 +9,8 @@
 #ifndef __CONFIG_K2HK_EVM_H
 #define __CONFIG_K2HK_EVM_H
 
-#include <environment/ti/spi.h>
-
-#ifdef CONFIG_TI_SECURE_DEVICE
-#define DEFAULT_SEC_BOOT_ENV						\
-	DEFAULT_FIT_TI_ARGS						\
-	"findfdt=setenv fdtfile ${name_fdt}\0"
-#else
-#define DEFAULT_SEC_BOOT_ENV
-#endif
-
-/* U-Boot general configuration */
-#define ENV_KS2_BOARD_SETTINGS						\
-	DEFAULT_FW_INITRAMFS_BOOT_ENV					\
-	DEFAULT_SEC_BOOT_ENV						\
-	"boot=ubi\0"							\
-	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
-	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
-	"name_fdt=keystone-k2hk-evm.dtb\0"				\
-	"name_mon=skern-k2hk.bin\0"					\
-	"name_ubi=k2hk-evm-ubifs.ubi\0"					\
-	"name_uboot=u-boot-spi-k2hk-evm.gph\0"				\
-	"name_fs=arago-console-image-k2hk-evm.cpio.gz\0"
-
 #include <configs/ti_armv7_keystone2.h>
 
-#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
-
 /* Network */
 #define CFG_KSNET_CPSW_NUM_PORTS	5
 
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index b1b839b504..199959fbd4 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -9,33 +9,8 @@
 #ifndef __CONFIG_K2L_EVM_H
 #define __CONFIG_K2L_EVM_H
 
-#include <environment/ti/spi.h>
-
-#ifdef CONFIG_TI_SECURE_DEVICE
-#define DEFAULT_SEC_BOOT_ENV						\
-	DEFAULT_FIT_TI_ARGS						\
-	"findfdt=setenv fdtfile ${name_fdt}\0"
-#else
-#define DEFAULT_SEC_BOOT_ENV
-#endif
-
-/* U-Boot general configuration */
-#define ENV_KS2_BOARD_SETTINGS						\
-	DEFAULT_FW_INITRAMFS_BOOT_ENV					\
-	DEFAULT_SEC_BOOT_ENV						\
-	"boot=ubi\0"							\
-	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
-	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0"	\
-	"name_fdt=keystone-k2l-evm.dtb\0"				\
-	"name_mon=skern-k2l.bin\0"					\
-	"name_ubi=k2l-evm-ubifs.ubi\0"					\
-	"name_uboot=u-boot-spi-k2l-evm.gph\0"				\
-	"name_fs=arago-console-image-k2l-evm.cpio.gz\0"
-
 #include <configs/ti_armv7_keystone2.h>
 
-#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
-
 /* Network */
 #define CFG_KSNET_CPSW_NUM_PORTS	5
 
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index 8cc4e0db03..6404b35911 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -11,6 +11,11 @@
 /* RTC */
 #define CFG_SYS_RTC_BUS_NUM		4
 
+#if defined(CONFIG_FSL_MC_ENET)
+#define AQR113C_PHY_ADDR1		0x0
+#define AQR113C_PHY_ADDR2		0x08
+#endif
+
 /* EMC2305 */
 #define I2C_MUX_CH_EMC2305		0x09
 #define I2C_EMC2305_ADDR		0x4D
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 9244601284..801cdae470 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -11,6 +11,9 @@
 #if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
 #define GICD_BASE			0xffc01000
 #define GICC_BASE			0xffc02000
+#elif defined(CONFIG_MESON_A1)
+#define GICD_BASE			0xff901000
+#define GICC_BASE			0xff902000
 #else /* MESON GXL and GXBB */
 #define GICD_BASE			0xc4301000
 #define GICC_BASE			0xc4302000
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 4a12c2f72c..068a2af2c1 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -2,21 +2,3 @@
 /*
  * Copyright (C) 2015 Google, Inc
  */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS	"stdin=usbkbd,serial\0" \
-					"stdout=vidconsole,serial\0" \
-					"stderr=vidconsole,serial\0" \
-					"usb_pgood_delay=40\0"
-
-#define VIDEO_IO_OFFSET				0
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h
index d5bd492634..d69d35fa96 100644
--- a/include/configs/mt7620.h
+++ b/include/configs/mt7620.h
@@ -10,10 +10,9 @@
 
 #define CFG_SYS_SDRAM_BASE		0x80000000
 
-#define CFG_SYS_INIT_SP_OFFSET	0x400000
+#define CFG_SYS_INIT_SP_OFFSET		0x400000
 
 /* SPL */
-
 #define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
 
 /* Dummy value */
diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h
index a9574940d4..bf2bc2d45c 100644
--- a/include/configs/mt7621.h
+++ b/include/configs/mt7621.h
@@ -12,13 +12,11 @@
 
 #define CFG_MAX_MEM_MAPPED		0x1c000000
 
-#define CFG_SYS_INIT_SP_OFFSET	0x800000
+#define CFG_SYS_INIT_SP_OFFSET		0x800000
 
 /* MMC */
 #define MMC_SUPPORTS_TUNING
 
-/* NAND */
-
 /* Serial SPL */
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
 #define CFG_SYS_NS16550_CLK		50000000
@@ -26,7 +24,7 @@
 #endif
 
 /* Serial common */
-#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200, \
 					  230400, 460800, 921600 }
 
 /* Dummy value */
diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h
index 6541512953..4a056954bf 100644
--- a/include/configs/mt7622.h
+++ b/include/configs/mt7622.h
@@ -9,14 +9,4 @@
 #ifndef __MT7622_H
 #define __MT7622_H
 
-/* Uboot definition */
-#define CFG_SYS_UBOOT_BASE                   CONFIG_TEXT_BASE
-
-/* SPL -> Uboot */
-#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
-/* DRAM */
-#define CFG_SYS_SDRAM_BASE		0x40000000
-
-/* Ethernet */
-
 #endif
diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h
index db12377b00..fca234a1dc 100644
--- a/include/configs/mt7623.h
+++ b/include/configs/mt7623.h
@@ -11,12 +11,6 @@
 
 #include <linux/sizes.h>
 
-/* Miscellaneous configurable options */
-
-/* Environment */
-
-/* Preloader -> Uboot */
-
 /* MMC */
 #define MMC_SUPPORTS_TUNING
 
@@ -32,8 +26,6 @@
 	"fdt_addr_r=" FDT_HIGH "\0"			\
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
 
-/* Ethernet */
-
 #ifdef CONFIG_DISTRO_DEFAULTS
 
 #define BOOT_TARGET_DEVICES(func)	\
diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h
index 9df2715fc7..0ac376d33c 100644
--- a/include/configs/mt7628.h
+++ b/include/configs/mt7628.h
@@ -10,7 +10,7 @@
 
 #define CFG_SYS_SDRAM_BASE		0x80000000
 
-#define CFG_SYS_INIT_SP_OFFSET	0x80000
+#define CFG_SYS_INIT_SP_OFFSET		0x80000
 
 /* Serial SPL */
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
@@ -19,11 +19,10 @@
 #endif
 
 /* Serial common */
-#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200, \
 					  230400, 460800, 921600 }
 
 /* SPL */
-
 #define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
 
 /* Dummy value */
diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h
index f6ab486fa2..59cdd22a1c 100644
--- a/include/configs/mt7629.h
+++ b/include/configs/mt7629.h
@@ -9,21 +9,10 @@
 #ifndef __MT7629_H
 #define __MT7629_H
 
-#include <linux/sizes.h>
-
-/* Miscellaneous configurable options */
-
-/* Environment */
-
+/* SPL */
 #define CFG_SYS_UBOOT_BASE		(0x30000000 + CONFIG_SPL_PAD_TO)
 
-/* SPL -> Uboot */
-
-/* UBoot -> Kernel */
-
 /* DRAM */
 #define CFG_SYS_SDRAM_BASE		0x40000000
 
-/* Ethernet */
-
 #endif
diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h
index 14c885ec55..a6d647edc4 100644
--- a/include/configs/mt7981.h
+++ b/include/configs/mt7981.h
@@ -9,13 +9,4 @@
 #ifndef __MT7981_H
 #define __MT7981_H
 
-/* Uboot definition */
-#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
-
-/* SPL -> Uboot */
-#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
-
-/* DRAM */
-#define CFG_SYS_SDRAM_BASE		0x40000000
-
 #endif
diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h
index 0c41af1fc3..090b4c6833 100644
--- a/include/configs/mt7986.h
+++ b/include/configs/mt7986.h
@@ -9,13 +9,4 @@
 #ifndef __MT7986_H
 #define __MT7986_H
 
-/* Uboot definition */
-#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
-
-/* SPL -> Uboot */
-#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
-
-/* DRAM */
-#define CFG_SYS_SDRAM_BASE		0x40000000
-
 #endif
diff --git a/include/configs/mt7988.h b/include/configs/mt7988.h
new file mode 100644
index 0000000000..e63825a5a1
--- /dev/null
+++ b/include/configs/mt7988.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT7988 SoC
+ *
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#ifndef __MT7988_H
+#define __MT7988_H
+
+#define CFG_MAX_MEM_MAPPED		0xC0000000
+
+#endif
diff --git a/include/configs/odroid_m1.h b/include/configs/odroid_m1.h
new file mode 100644
index 0000000000..0d2e9fd94b
--- /dev/null
+++ b/include/configs/odroid_m1.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ODROID_M1_H
+#define __ODROID_M1_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+	"cramfsaddr=0x0c000000\0"
+
+#include <configs/rk3568_common.h>
+
+#endif
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index adb25a6297..f44967787c 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -67,7 +67,7 @@
 
 #include <config_distro_bootcmd.h>
 
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
 
 #define CFG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index af0093511a..fc2655a17b 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -135,7 +135,7 @@
 	"fdtaddr=0xc0600000\0" \
 	"scriptaddr=0xc0600000\0"
 
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
 
 #define CFG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h
index 4e6dc79f41..8668da6eba 100644
--- a/include/configs/phycore_am335x_r2.h
+++ b/include/configs/phycore_am335x_r2.h
@@ -59,8 +59,8 @@
 	func(NAND, nand, 0)
 
 #include <config_distro_bootcmd.h>
-#include <environment/ti/dfu.h>
-#include <environment/ti/mmc.h>
+#include <env/ti/dfu.h>
+#include <env/ti/mmc.h>
 
 #define CFG_EXTRA_ENV_SETTINGS \
 	DEFAULT_MMC_TI_ARGS \
diff --git a/include/configs/poleg.h b/include/configs/poleg.h
index c3f1d3393c..1e96e838be 100644
--- a/include/configs/poleg.h
+++ b/include/configs/poleg.h
@@ -27,6 +27,8 @@
 		"eth1addr=00:00:F7:A0:00:FD\0"   \
 		"eth2addr=00:00:F7:A0:00:FE\0"    \
 		"eth3addr=00:00:F7:A0:00:FF\0"    \
+		"console=ttyS0,115200n8\0" \
+		"earlycon=uart8250,mmio32,0xf0000000\0" \
 		"common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram "   \
 		"console=${console} mem=${mem} ramdisk_size=48000 basemac=${ethaddr}\0"    \
 		"sd_prog=fatload mmc 0 10000000 image-bmc; cp.b 10000000 80000000 ${filesize}\0"  \
diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h
index 6fbd2679f0..13ed901176 100644
--- a/include/configs/px30_common.h
+++ b/include/configs/px30_common.h
@@ -21,8 +21,9 @@
 	"pxefile_addr_r=0x00600000\0" \
 	"fdt_addr_r=0x08300000\0" \
 	"kernel_addr_r=0x00280000\0" \
-	"kernel_addr_c=0x03e80000\0" \
-	"ramdisk_addr_r=0x0a200000\0"
+	"ramdisk_addr_r=0x0a200000\0" \
+	"kernel_comp_addr_r=0x03e80000\0" \
+	"kernel_comp_size=0x2000000\0"
 
 #define CFG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index 20135f569e..584559cfa3 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -11,30 +11,25 @@
 #define CFG_SYS_SDRAM_BASE		0x80000000
 
 #define RISCV_MMODE_TIMERBASE		0x2000000
+#define RISCV_MMODE_TIMEROFF		0xbff8
 #define RISCV_MMODE_TIMER_FREQ		1000000
-
 #define RISCV_SMODE_TIMER_FREQ		1000000
 
 /* Environment options */
 
+#define CFG_STD_DEVICES_SETTINGS	"stdin=serial,usbkbd\0" \
+					"stdout=serial,vidconsole\0" \
+					"stderr=serial,vidconsole\0"
+
 #define BOOT_TARGET_DEVICES(func) \
-	func(QEMU, qemu, na) \
 	func(VIRTIO, virtio, 0) \
 	func(SCSI, scsi, 0) \
 	func(DHCP, dhcp, na)
 
 #include <config_distro_bootcmd.h>
 
-#define BOOTENV_DEV_QEMU(devtypeu, devtypel, instance) \
-	"bootcmd_qemu=" \
-		"if env exists kernel_start; then " \
-			"bootm ${kernel_start} - ${fdtcontroladdr};" \
-		"fi;\0"
-
-#define BOOTENV_DEV_NAME_QEMU(devtypeu, devtypel, instance) \
-	"qemu "
-
 #define CFG_EXTRA_ENV_SETTINGS \
+	CFG_STD_DEVICES_SETTINGS \
 	"fdt_high=0xffffffffffffffff\0" \
 	"initrd_high=0xffffffffffffffff\0" \
 	"kernel_addr_r=0x84000000\0" \
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index 33263a46a4..9b0f5cedcd 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -2,34 +2,3 @@
 /*
  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-#define BOOT_TARGET_DEVICES(func) \
-	func(USB, usb, 0) \
-	func(SCSI, scsi, 0) \
-	func(VIRTIO, virtio, 0) \
-	func(IDE, ide, 0) \
-	func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd\0" \
-					"stdout=serial,vidconsole\0" \
-					"stderr=serial,vidconsole\0"
-
-/*
- * ATA/SATA support for QEMU x86 targets
- *   - Only legacy IDE controller is supported for QEMU '-M pc' target
- *   - AHCI controller is supported for QEMU '-M q35' target
- */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/quartz64_rk3566.h b/include/configs/quartz64_rk3566.h
new file mode 100644
index 0000000000..dfe0fee94c
--- /dev/null
+++ b/include/configs/quartz64_rk3566.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __QUARTZ64_RK3566_H
+#define __QUARTZ64_RK3566_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+
+#include <configs/rk3568_common.h>
+
+#endif
diff --git a/include/configs/rock5a-rk3588s.h b/include/configs/rock5a-rk3588s.h
new file mode 100644
index 0000000000..9a2d3ee9f5
--- /dev/null
+++ b/include/configs/rock5a-rk3588s.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ */
+
+#ifndef __ROCK5A_RK3588_H
+#define __ROCK5A_RK3588_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __ROCK5A_RK3588_H */
diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h
index 1ec1640f99..a64c0c6364 100644
--- a/include/configs/rv1126_common.h
+++ b/include/configs/rv1126_common.h
@@ -24,6 +24,7 @@
 	"scriptaddr=0x00000000\0" \
 	"pxefile_addr_r=0x00100000\0" \
 	"fdt_addr_r=0x08300000\0" \
+	"fdtoverlay_addr_r=0x02000000\0" \
 	"kernel_addr_r=0x02008000\0" \
 	"ramdisk_addr_r=0x0a200000\0"
 
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index de3a0dcdd5..2996b37572 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -14,8 +14,8 @@
 #define CFG_SYS_SDRAM_BASE		0x80000000
 
 #define RISCV_MMODE_TIMERBASE		0x2000000
+#define RISCV_MMODE_TIMEROFF		0xbff8
 #define RISCV_MMODE_TIMER_FREQ		1000000
-
 #define RISCV_SMODE_TIMER_FREQ		1000000
 
 /* Environment options */
@@ -26,7 +26,7 @@
 	func(DHCP, dhcp, na)
 
 #include <config_distro_bootcmd.h>
-#include <environment/distro/sf.h>
+#include <env/distro/sf.h>
 
 #define TYPE_GUID_LOADER1	"5B193300-FC78-40CD-8002-E86C45580B47"
 #define TYPE_GUID_LOADER2	"2E54B353-1271-4842-806F-E436D6AF6985"
diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h
index 20b99a1021..85f6a968e0 100644
--- a/include/configs/slimbootloader.h
+++ b/include/configs/slimbootloader.h
@@ -2,38 +2,3 @@
 /*
  * Copyright (C) 2019 Intel Corporation <www.intel.com>
  */
-
-#ifndef __SLIMBOOTLOADER_CONFIG_H__
-#define __SLIMBOOTLOADER_CONFIG_H__
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS		\
-	"stdin=serial,i8042-kbd,usbkbd\0"	\
-	"stdout=serial\0"			\
-	"stderr=serial\0"
-
-/*
- * Override CFG_EXTRA_ENV_SETTINGS in x86-common.h
- */
-#undef CFG_EXTRA_ENV_SETTINGS
-#define CFG_EXTRA_ENV_SETTINGS		\
-	CFG_STD_DEVICES_SETTINGS		\
-	"netdev=eth0\0"				\
-	"consoledev=ttyS0\0"			\
-	"ramdiskaddr=0x4000000\0"		\
-	"ramdiskfile=initrd\0"			\
-	"bootdev=usb\0"				\
-	"bootdevnum=0\0"			\
-	"bootdevpart=0\0"			\
-	"bootfsload=fatload\0"			\
-	"bootusb=setenv bootdev usb; boot\0"	\
-	"bootscsi=setenv bootdev scsi; boot\0"	\
-	"bootmmc=setenv bootdev mmc; boot\0"	\
-	"bootargs=console=ttyS0,115200 console=tty0\0"
-
-/*
- * Override CONFIG_BOOTCOMMAND in x86-common.h
- */
-
-#endif /* __SLIMBOOTLOADER_CONFIG_H__ */
diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h
index b2e7aa1514..5f7eabd3fc 100644
--- a/include/configs/som-db5800-som-6867.h
+++ b/include/configs/som-db5800-som-6867.h
@@ -16,6 +16,4 @@
 					"stdout=serial,vidconsole\0" \
 					"stderr=serial,vidconsole\0"
 
-#define VIDEO_IO_OFFSET				0
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h
index 93dcc22d36..4ee02b8420 100644
--- a/include/configs/starfive-visionfive2.h
+++ b/include/configs/starfive-visionfive2.h
@@ -9,6 +9,7 @@
 #define _STARFIVE_VISIONFIVE2_H
 
 #define RISCV_MMODE_TIMERBASE		0x2000000
+#define RISCV_MMODE_TIMEROFF		0xbff8
 #define RISCV_MMODE_TIMER_FREQ		4000000
 #define RISCV_SMODE_TIMER_FREQ		4000000
 
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 34856d3004..9bf01cac47 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -36,6 +36,4 @@
 #define CFG_SYS_UBOOT_BASE		(CFG_SYS_FLASH_BASE + \
 					 CONFIG_SPL_PAD_TO)
 
-/* For splashcreen */
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h
index 7db72a19ed..29a1197b5a 100644
--- a/include/configs/stm32mp15_common.h
+++ b/include/configs/stm32mp15_common.h
@@ -92,19 +92,6 @@
 		"run distro_bootcmd;" \
 	"fi;\0"
 
-#ifdef CONFIG_FASTBOOT_CMD_OEM_FORMAT
-/* eMMC default partitions for fastboot command: oem format */
-#define STM32MP_PARTS_DEFAULT \
-	"partitions=" \
-	"name=ssbl,size=2M;" \
-	"name=bootfs,size=64MB,bootable;" \
-	"name=vendorfs,size=16M;" \
-	"name=rootfs,size=746M;" \
-	"name=userfs,size=-\0"
-#else
-#define STM32MP_PARTS_DEFAULT
-#endif
-
 #define STM32MP_EXTRA \
 	"env_check=if env info -p -d -q; then env save; fi\0" \
 	"boot_net_usb_start=true\0"
@@ -138,7 +125,6 @@
 #define CFG_EXTRA_ENV_SETTINGS \
 	STM32MP_MEM_LAYOUT \
 	STM32MP_BOOTCMD \
-	STM32MP_PARTS_DEFAULT \
 	BOOTENV \
 	STM32MP_EXTRA \
 	STM32MP_BOARD_EXTRA_ENV
diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h
index 866cd7a719..60838cb0e3 100644
--- a/include/configs/stm32mp15_st_common.h
+++ b/include/configs/stm32mp15_st_common.h
@@ -10,7 +10,9 @@
 
 #define STM32MP_BOARD_EXTRA_ENV \
 	"usb_pgood_delay=2000\0" \
-	"console=ttySTM0\0"
+	"console=ttySTM0\0" \
+	"splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"splashpos=m,m\0"
 
 #include <configs/stm32mp15_common.h>
 
@@ -47,7 +49,6 @@
 #define CFG_EXTRA_ENV_SETTINGS \
 	STM32MP_MEM_LAYOUT \
 	ST_STM32MP1_BOOTCMD \
-	STM32MP_PARTS_DEFAULT \
 	BOOTENV \
 	STM32MP_EXTRA \
 	STM32MP_BOARD_EXTRA_ENV
diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h
index 8f44c6f66a..cd7359c2f8 100644
--- a/include/configs/synquacer.h
+++ b/include/configs/synquacer.h
@@ -40,19 +40,29 @@
 
 /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
 
+#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
+#define DEFAULT_DFU_ALT_INFO
+#else
 #define DEFAULT_DFU_ALT_INFO "dfu_alt_info="				\
 			"mtd nor1=u-boot.bin raw 200000 100000;"	\
 			"fip.bin raw 180000 78000;"			\
 			"optee.bin raw 500000 100000\0"
+#endif
 
 /* GUIDs for capsule updatable firmware images */
 #define DEVELOPERBOX_UBOOT_IMAGE_GUID \
 	EFI_GUID(0x53a92e83, 0x4ef4, 0x473a, 0x8b, 0x0d, \
 		 0xb5, 0xd8, 0xc7, 0xb2, 0xd6, 0x00)
 
+#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
+#define DEVELOPERBOX_FIP_IMAGE_GUID \
+	EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \
+		 0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08)
+#else
 #define DEVELOPERBOX_FIP_IMAGE_GUID \
 	EFI_GUID(0x880866e9, 0x84ba, 0x4793, 0xa9, 0x08, \
 		 0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98)
+#endif
 
 #define DEVELOPERBOX_OPTEE_IMAGE_GUID \
 	EFI_GUID(0xc1b629f1, 0xce0e, 0x4894, 0x82, 0xbf, \
diff --git a/include/configs/ten64.h b/include/configs/ten64.h
index e86c163132..d2bef9b6e5 100644
--- a/include/configs/ten64.h
+++ b/include/configs/ten64.h
@@ -15,15 +15,20 @@
 #define QSPI_NOR_BOOTCOMMAND	"run distro_bootcmd"
 #define SD_BOOTCOMMAND		"run distro_bootcmd"
 
+#define SD_FIRMWARE_PATH "firmware/traverse/ten64/"
+
 #define QSPI_MC_INIT_CMD				\
 	"sf probe 0:0 && sf read 0x80000000 0x300000 0x200000 &&"	\
 	"sf read 0x80200000 0x5C0000 0x40000 &&"				\
 	"fsl_mc start mc 0x80000000 0x80200000 && " \
-	"sf read 0x80300000 0x580000 0x40000 && fsl_mc lazyapply DPL 0x80300000\0"
+	"sf read 0x8E000000 0x580000 0x40000 && fsl_mc lazyapply DPL 0x8E000000 && "\
+	"echo 'default DPL loaded'\0"
 #define SD_MC_INIT_CMD				\
-	"mmcinfo; fatload mmc 0 0x80000000 mcfirmware/mc_ls1088a.itb; "\
-	"fatload mmc 0 0x80200000 dpaa2config/dpc.0x1D-0x0D.dtb; "\
-	"fsl_mc start mc 0x80000000 0x80200000\0"
+	"mmcinfo; fatload mmc 0 0x80000000 " SD_FIRMWARE_PATH "mc_ls1088a.itb; "\
+	"fatload mmc 0 0x80200000 " SD_FIRMWARE_PATH "dpc.0x1D-0x0D.dtb; "\
+	"fsl_mc start mc 0x80000000 0x80200000 && "	\
+	"fatload mmc 0 0x8E000000 " SD_FIRMWARE_PATH "eth-dpl-all.dtb && " \
+	"fsl_mc lazyapply DPL 0x8E000000 && echo 'default DPL loaded'\0"
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(NVME, nvme, 0) \
@@ -34,8 +39,22 @@
 	func(PXE, pxe, 0)
 #include <config_distro_bootcmd.h>
 
+#define OPENWRT_NAND_BOOTCMD	\
+	"bootcmd_openwrt_nand=ubi part ubi${openwrt_active_sys} && "\
+	"ubi read $load_addr kernel && " \
+	"setenv bootargs \"root=/dev/ubiblock0_1 earlycon ubi.mtd=ubi${openwrt_active_sys}\" &&"\
+	"bootm $load_addr#ten64\0"
 #undef CFG_EXTRA_ENV_SETTINGS
 
+#if CONFIG_IS_ENABLED(CMD_BOOTMENU)
+#define DEFAULT_MENU_ENTRIES \
+	"bootmenu_0=Continue standard boot=run bootcmd\0" \
+	"bootmenu_1=Boot into recovery=run bootcmd_recovery\0" \
+	"bootmenu_2=Boot OpenWrt from NAND=run bootcmd_openwrt_nand\0"
+#else
+#define DEFAULT_MENU_ENTRIES ""
+#endif /* CONFIG_IS_ENABLED(CMD_BOOTMENU) */
+
 #define CFG_EXTRA_ENV_SETTINGS \
 	"BOARD=ten64\0"					\
 	"fdt_addr_r=0x90000000\0"		\
@@ -43,9 +62,12 @@
 	"kernel_addr_r=0x81000000\0"		\
 	"load_addr=0xa0000000\0"		\
 	BOOTENV \
+	OPENWRT_NAND_BOOTCMD \
+	"openwrt_active_sys=a\0" \
 	"load_efi_dtb=mtd read devicetree $fdt_addr_r && fdt addr $fdt_addr_r && " \
 	"fdt resize && fdt boardsetup\0" \
-	"bootcmd_recovery=mtd read recovery 0xa0000000; mtd read dpl 0x80100000 && " \
-	"fsl_mc apply DPL 0x80100000 && bootm 0xa0000000#ten64\0"
+	"bootcmd_recovery=mtd read recovery 0xa0000000;  " \
+	"setenv bootargs \"earlycon root=/dev/ram0 ramdisk_size=0x3000000\" && bootm 0xa0000000#ten64\0" \
+	DEFAULT_MENU_ENTRIES
 
 #endif /* __TEN64_H */
diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h
new file mode 100644
index 0000000000..87496a52c4
--- /dev/null
+++ b/include/configs/th1520_lpi4a.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Yixun Lan <dlan@gentoo.org>
+ *
+ */
+
+#ifndef __TH1520_LPI4A_H
+#define __TH1520_LPI4A_H
+
+#include <linux/sizes.h>
+
+#define CFG_SYS_SDRAM_BASE		0x00000000
+
+#define UART_BASE	0xffe7014000
+#define UART_REG_WIDTH  32
+
+/* Environment options */
+
+#define CFG_EXTRA_ENV_SETTINGS \
+	"PS1=[LPi4A]# \0"
+
+#endif /* __TH1520_LPI4A_H */
diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h
index b23b878307..46aef23821 100644
--- a/include/configs/theadorable-x86-common.h
+++ b/include/configs/theadorable-x86-common.h
@@ -15,8 +15,6 @@
 					"stdout=serial\0" \
 					"stderr=serial\0"
 
-#define VIDEO_IO_OFFSET				0
-
 /* Environment settings */
 
 #undef CFG_EXTRA_ENV_SETTINGS
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
deleted file mode 100644
index ac6d46f917..0000000000
--- a/include/configs/ti816x_evm.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * ti816x_evm.h
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- */
-
-#ifndef __CONFIG_TI816X_EVM_H
-#define __CONFIG_TI816X_EVM_H
-
-#include <configs/ti_armv7_omap.h>
-#include <asm/arch/omap.h>
-
-#define CFG_EXTRA_ENV_SETTINGS	\
-	DEFAULT_LINUX_BOOT_ENV
-
-/* Clock Defines */
-#define V_OSCK          24000000    /* Clock output from T2 */
-#define V_SCLK          (V_OSCK >> 1)
-
-#define CFG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2048MB */
-#define CFG_SYS_SDRAM_BASE		0x80000000
-
-/**
- * Platform/Board specific defs
- */
-#define CFG_SYS_TIMERBASE    0x4802E000
-
-/*
- * NS16550 Configuration
- */
-#define CFG_SYS_NS16550_CLK      (48000000)
-#define CFG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
-
-/* allow overwriting serial config and ethaddr */
-
-
-/*
- * GPMC NAND block.  We support 1 device and the physical address to
- * access CS0 at is 0x8000000.
- */
-#define CFG_SYS_NAND_BASE		0x8000000
-
-/* NAND: SPL related configs */
-
-/* NAND: device related configs */
-/* NAND: driver related configs */
-#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
-					 10, 11, 12, 13, 14, 15, 16, 17, \
-					 18, 19, 20, 21, 22, 23, 24, 25, \
-					 26, 27, 28, 29, 30, 31, 32, 33, \
-					 34, 35, 36, 37, 38, 39, 40, 41, \
-					 42, 43, 44, 45, 46, 47, 48, 49, \
-					 50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CFG_SYS_NAND_ECCSIZE		512
-#define CFG_SYS_NAND_ECCBYTES	14
-
-/* SPL */
-/* Defines for SPL */
-
-#endif
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 149a74d98e..dbbeff34ba 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -154,4 +154,54 @@
 #define NETARGS ""
 #endif
 
+#ifdef CONFIG_ARM64
+#ifdef CONFIG_DISTRO_DEFAULTS
+#ifdef CONFIG_CMD_PXE
+# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+# define BOOT_TARGET_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DHCP(func)
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_MMC(func) \
+	func(TI_MMC, ti_mmc, na) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1)
+#else
+#define BOOT_TARGET_MMC(func)
+#endif
+
+#define BOOTENV_DEV_TI_MMC(devtypeu, devtypel, instance)
+
+#define BOOTENV_DEV_NAME_TI_MMC(devtyeu, devtypel, instance)		\
+	"ti_mmc "
+
+#ifdef CONFIG_CMD_USB
+# define BOOT_TARGET_USB(func)	func(USB, usb, 0)
+#else
+# define BOOT_TARGET_USB(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_MMC(func) \
+	BOOT_TARGET_USB(func) \
+	BOOT_TARGET_PXE(func) \
+	BOOT_TARGET_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+
+/* Incorporate settings into the U-Boot environment */
+#define CFG_EXTRA_ENV_SETTINGS					\
+	BOOTENV
+
+#endif
+
+#endif /* CONFIG_ARM64 */
+
 #endif	/* __CONFIG_TI_ARMV7_COMMON_H__ */
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index a47f0902a2..72c04d8a99 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -63,111 +63,12 @@
 #define CFG_SYS_NAND_LARGEPAGE
 #define CFG_SYS_NAND_BASE_LIST		{ 0x30000000, }
 
-#define DFU_ALT_INFO_MMC \
-	"dfu_alt_info_mmc=" \
-	"MLO fat 0 1;" \
-	"u-boot.img fat 0 1;" \
-	"uEnv.txt fat 0 1\0"
 
-/* DFU settings */
-#define DFUARGS \
-	"dfu_bufsiz=0x10000\0" \
-	DFU_ALT_INFO_MMC \
 
 /* U-Boot general configuration */
 
 /* EDMA3 */
 
-#define KERNEL_MTD_PARTS						\
-	"mtdparts="							\
-	SPI_MTD_PARTS
-
-#define DEFAULT_FW_INITRAMFS_BOOT_ENV					\
-	"name_fw_rd=k2-fw-initrd.cpio.gz\0"				\
-	"set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0"		\
-	"init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; "	\
-		"run set_rd_spec\0"					\
-	"init_fw_rd_nfs=nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; "	\
-		"run set_rd_spec\0"					\
-	"init_fw_rd_ramfs=setenv rd_spec -\0"				\
-	"init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; "	\
-		"run set_rd_spec\0"					\
-
-#define DEFAULT_PMMC_BOOT_ENV						\
-	"set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \
-	"dev_pmmc=0\0"							\
-	"get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0"	\
-	"get_pmmc_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_pmmc}\0"	\
-	"get_pmmc_ramfs=run get_pmmc_net\0"				\
-	"get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} "		\
-			"${bootdir}/${name_pmmc}\0"			\
-	"get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0"	\
-	"run_pmmc=rproc init; rproc list; "				\
-		"rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; "	\
-		"rproc start ${dev_pmmc}\0"				\
-
-#define CFG_EXTRA_ENV_SETTINGS					\
-	DEFAULT_LINUX_BOOT_ENV						\
-	ENV_KS2_BOARD_SETTINGS						\
-	DFUARGS								\
-	"bootdir=/boot\0" \
-	"tftp_root=/\0"							\
-	"nfs_root=/export\0"						\
-	"mem_lpae=1\0"							\
-	"uinitrd_fixup=1\0"						\
-	"addr_ubi=0x82000000\0"						\
-	"addr_secdb_key=0xc000000\0"					\
-	"name_kern=zImage\0"						\
-	"addr_mon=0x87000000\0"						\
-	"addr_non_sec_mon=0x0c097fc0\0"					\
-	"addr_load_sec_bm=0x0c09c000\0"					\
-	"run_mon=mon_install ${addr_mon}\0"				\
-	"run_mon_hs=mon_install ${addr_non_sec_mon} "			\
-			"${addr_load_sec_bm}\0"				\
-	"run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0"		\
-	"init_net=run args_all args_net\0"				\
-	"init_nfs=setenv autoload no; dhcp; run args_all args_net\0"	\
-	"init_ubi=run args_all args_ubi; "				\
-		"ubi part ubifs; ubifsmount ubi:rootfs;\0"			\
-	"get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0"	\
-	"get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}\0"	\
-	"get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0"		\
-	"get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0"	\
-	"get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern}\0"	\
-	"get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0"		\
-	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
-	"get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0"	\
-	"get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0"	\
-	"get_fit_net=dhcp ${addr_fit} ${tftp_root}/${name_fit}\0"	\
-	"get_fit_nfs=nfs ${addr_fit} ${nfs_root}/boot/${name_fit}\0"	\
-	"get_fit_ubi=ubifsload ${addr_fit} ${bootdir}/${name_fit}\0"	\
-	"get_fit_mmc=load mmc ${bootpart} ${addr_fit} ${bootdir}/${name_fit}\0" \
-	"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0"	\
-	"get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \
-	"burn_uboot_spi=sf probe; sf erase 0 0x100000; "		\
-		"sf write ${loadaddr} 0 ${filesize}\0"		\
-	"burn_uboot_nand=nand erase 0 0x100000; "			\
-		"nand write ${loadaddr} 0 ${filesize}\0"		\
-	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait "	\
-		KERNEL_MTD_PARTS					\
-	"args_net=setenv bootargs ${bootargs} rootfstype=nfs "		\
-		"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},"	\
-		"${nfs_options} ip=dhcp\0"				\
-	"nfs_options=v3,tcp,rsize=4096,wsize=4096\0"			\
-	"get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0"	\
-	"get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0"	\
-	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
-	"get_fit_ramfs=dhcp ${addr_fit} ${tftp_root}/${name_fit}\0"	\
-	"get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0"	\
-	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0"	\
-	"get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0"	\
-	"burn_ubi=nand erase.part ubifs; "				\
-		"nand write ${addr_ubi} ubifs ${filesize}\0"		\
-	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0"		\
-	"args_ramfs=setenv bootargs ${bootargs} "			\
-		"rdinit=/sbin/init rw root=/dev/ram0 "			\
-		"initrd=0x808080000,80M\0"				\
-	"no_post=1\0"
 
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 9e312ac16d..c4f116aabf 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -56,7 +56,7 @@
 	func(DHCP, dhcp, na)
 
 #include <config_distro_bootcmd.h>
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
 
 #define CFG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 74a39c4078..4e5aa74147 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -39,8 +39,8 @@
 #define DFUARGS
 #endif
 
-#include <environment/ti/mmc.h>
-#include <environment/ti/nand.h>
+#include <env/ti/mmc.h>
+#include <env/ti/nand.h>
 
 #ifndef CONSOLEDEV
 #define CONSOLEDEV "ttyS2"
diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h
new file mode 100644
index 0000000000..58c2e88c0b
--- /dev/null
+++ b/include/configs/v3hsk.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/v3hsk.h
+ *     This file is V3HSK board configuration.
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ */
+
+#ifndef __V3HSK_H
+#define __V3HSK_H
+
+#include "rcar-gen3-common.h"
+
+/* Environment compatibility */
+
+/* SH Ether */
+#define CFG_SH_ETHER_USE_PORT	0
+#define CFG_SH_ETHER_PHY_ADDR	0x0
+#define CFG_SH_ETHER_PHY_MODE	PHY_INTERFACE_MODE_RGMII_ID
+#define CFG_SH_ETHER_CACHE_WRITEBACK
+#define CFG_SH_ETHER_CACHE_INVALIDATE
+#define CFG_SH_ETHER_ALIGNE_SIZE	64
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+
+#endif /* __V3HSK_H */
diff --git a/include/configs/verdin-am62.h b/include/configs/verdin-am62.h
new file mode 100644
index 0000000000..7990ea8310
--- /dev/null
+++ b/include/configs/verdin-am62.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Configuration header file for Verdin AM62 SoM
+ *
+ * Copyright 2023 Toradex - https://www.toradex.com/
+ */
+
+#ifndef __VERDIN_AM62_H
+#define __VERDIN_AM62_H
+
+#define RAMDISK_ADDR_R		0x90300000
+#define SCRIPTADDR		0x90280000
+
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE	0x80000000
+#define CFG_SYS_SDRAM_BASE1	0x880000000
+#define CFG_SYS_SDRAM_SIZE	SZ_2G /* Maximum supported size */
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"fdt_addr_r=0x90200000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"kernel_comp_addr_r=0x80200000\0" \
+	"kernel_comp_size=0x08000000\0" \
+	"ramdisk_addr_r=" __stringify(RAMDISK_ADDR_R) "\0" \
+	"scriptaddr=" __stringify(SCRIPTADDR) "\0"
+
+#if CONFIG_TARGET_VERDIN_AM62_A53
+/* Enable Distro Boot */
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#else /* CONFIG_TARGET_VERDIN_AM62_A53 */
+#define BOOTENV \
+	""
+#endif /* CONFIG_TARGET_VERDIN_AM62_A53 */
+
+/* Incorporate settings into the U-Boot environment */
+#define CFG_EXTRA_ENV_SETTINGS \
+	BOOTENV \
+	MEM_LAYOUT_ENV_SETTINGS \
+	"boot_scripts=boot.scr\0" \
+	"boot_script_dhcp=boot.scr\0" \
+	"console=ttyS2\0" \
+	"fdt_board=dev\0" \
+	"setup=setenv setupargs console=tty1 console=${console},${baudrate} " \
+		"consoleblank=0 earlycon=ns16550a,mmio32,0x02800000\0" \
+	"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
+		"if test \"$confirm\" = \"y\"; then " \
+		"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
+		"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
+		"${blkcnt}; fi\0"
+
+#endif /* __VERDIN_AM62_H */
diff --git a/include/configs/x240.h b/include/configs/x240.h
new file mode 100644
index 0000000000..3601df588d
--- /dev/null
+++ b/include/configs/x240.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Allied Telesis
+ */
+
+#ifndef __X240_H_
+#define __X240_H_
+
+#include <asm/arch/soc.h>
+
+/* additions for new ARM relocation support */
+#define CFG_SYS_SDRAM_BASE   0x200000000
+
+#define CFG_SYS_BAUDRATE_TABLE   { 9600, 19200, 38400, 57600, \
+				      115200, 230400, 460800, 921600 }
+
+/* Default Env vars */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CFG_EXTRA_ENV_SETTINGS   \
+	BOOTENV \
+	"kernel_addr_r=0x202000000\0" \
+	"fdt_addr_r=0x201000000\0"    \
+	"ramdisk_addr_r=0x206000000\0"    \
+	"fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CFG_SYS_TCLK     325000000
+
+#endif /* __X240_H_ */
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index 98abb00927..6bf90c7de4 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -10,8 +10,6 @@
 #define CFG_X86_REFCODE_ADDR			0xffea0000
 #define CFG_X86_REFCODE_RUN_ADDR		0
 
-#define VIDEO_IO_OFFSET				0
-
 #define CFG_STD_DEVICES_SETTINGS	"stdin=usbkbd,i8042-kbd,serial\0" \
 					"stdout=vidconsole,serial\0" \
 					"stderr=vidconsole,serial\0"
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index c1c5a09a35..8bd0716c08 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -5,22 +5,10 @@
  * Graeme Russ, graeme.russ@gmail.com.
  */
 
-#include <asm/ibmpc.h>
-
 #ifndef __CONFIG_X86_COMMON_H
 #define __CONFIG_X86_COMMON_H
 
 /*-----------------------------------------------------------------------
- * CPU Features
- */
-
-#define CFG_SYS_STACK_SIZE			(32 * 1024)
-
-/*-----------------------------------------------------------------------
- * Environment configuration
- */
-
-/*-----------------------------------------------------------------------
  * USB configuration
  */
 
@@ -32,18 +20,11 @@
 #define CFG_OTHBOOTARGS	"othbootargs=acpi=off\0"
 #endif
 
-#if defined(CONFIG_DISTRO_DEFAULTS)
-#define DISTRO_BOOTENV		BOOTENV
-#else
-#define DISTRO_BOOTENV
-#endif
-
 #ifndef SPLASH_SETTINGS
 #define SPLASH_SETTINGS
 #endif
 
 #define CFG_EXTRA_ENV_SETTINGS			\
-	DISTRO_BOOTENV					\
 	CFG_STD_DEVICES_SETTINGS			\
 	SPLASH_SETTINGS					\
 	"pciconfighost=1\0"				\
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index e70acd93ba..a403999977 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@ -2,7 +2,7 @@
 /*
  * Configuration for Xilinx Versal
  * (C) Copyright 2016 - 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  *
  * Based on Configuration for Xilinx ZynqMP
  */
diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h
index 23655a4752..628fd80baa 100644
--- a/include/configs/xilinx_versal_mini.h
+++ b/include/configs/xilinx_versal_mini.h
@@ -3,8 +3,8 @@
  * Configuration for Xilinx Versal MINI configuration
  *
  * (C) Copyright 2018-2019 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 #ifndef __CONFIG_VERSAL_MINI_H
diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h
index 424ead038e..613cce46f9 100644
--- a/include/configs/xilinx_versal_net.h
+++ b/include/configs/xilinx_versal_net.h
@@ -76,20 +76,24 @@
 # define BOOT_TARGET_DEVICES_DHCP(func)
 #endif
 
-#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL_NET)
-# define BOOT_TARGET_DEVICES_XSPI(func)	func(XSPI, xspi, 0)
+#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL)
+# define BOOT_TARGET_DEVICES_XSPI(func)	func(XSPI, xspi, 0) func(XSPI, xspi, 1)
+# define BOOTENV_DEV_SHARED_XSPI \
+	"xspi_boot=sf probe $devnum_xspi:0 0 0 && " \
+	"sf read $scriptaddr $script_offset_f $script_size_f && " \
+	"echo XSPI: Trying to boot script at ${scriptaddr} && " \
+	"source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0"
 #else
 # define BOOT_TARGET_DEVICES_XSPI(func)
+# define BOOTENV_DEV_SHARED_XSPI
 #endif
 
 #define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \
-	"bootcmd_xspi0=sf probe 0 0 0 && " \
-	"sf read $scriptaddr $script_offset_f $script_size_f && " \
-	"echo XSPI: Trying to boot script at ${scriptaddr} && " \
-	"source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0"
+	"bootcmd_" #devtypel #instance "=" \
+	"devnum_xspi=" #instance "; run " #devtypel "_boot\0" \
 
 #define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \
-	"xspi0 "
+	""
 
 #define BOOT_TARGET_DEVICES_JTAG(func)	func(JTAG, jtag, na)
 
@@ -127,6 +131,7 @@
 #define CFG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	BOOTENV \
+	BOOTENV_DEV_SHARED_XSPI \
 	DFU_ALT_INFO
 #endif
 
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 011f0034c5..74264b7bee 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -2,7 +2,7 @@
 /*
  * Configuration for Xilinx ZynqMP
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  *
  * Based on Configuration for Versatile Express
  */
@@ -60,6 +60,9 @@
 	"scriptaddr=0x20000000\0" \
 	"ramdisk_addr_r=0x02100000\0" \
 	"script_size_f=0x80000\0" \
+	"stdin=serial\0" \
+	"stdout=serial,vidconsole\0" \
+	"stderr=serial,vidconsole\0" \
 
 #if defined(CONFIG_MMC_SDHCI_ZYNQ)
 # define BOOT_TARGET_DEVICES_MMC(func)	func(MMC, mmc, 0) func(MMC, mmc, 1)
diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h
index 9af0545664..8afccb7f73 100644
--- a/include/configs/xilinx_zynqmp_mini.h
+++ b/include/configs/xilinx_zynqmp_mini.h
@@ -3,8 +3,8 @@
  * Configuration for Xilinx ZynqMP Flash utility
  *
  * (C) Copyright 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 #ifndef __CONFIG_ZYNQMP_MINI_H
diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h
index 1b6e26ee39..cf3747aab1 100644
--- a/include/configs/xilinx_zynqmp_mini_nand.h
+++ b/include/configs/xilinx_zynqmp_mini_nand.h
@@ -3,8 +3,8 @@
  * Configuration for Xilinx ZynqMP Nand Flash utility
  *
  * (C) Copyright 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 #ifndef __CONFIG_ZYNQMP_MINI_NAND_H
diff --git a/include/dm/device.h b/include/dm/device.h
index b86bf90609..e54cb6bca4 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -367,7 +367,7 @@ struct udevice_id {
  * @ops: Driver-specific operations. This is typically a list of function
  * pointers defined by the driver, to implement driver functions required by
  * the uclass.
- * @flags: driver flags - see `DM_FLAGS_...`
+ * @flags: driver flags - see `DM_FLAG_...`
  * @acpi_ops: Advanced Configuration and Power Interface (ACPI) operations,
  * allowing the device to add things to the ACPI tables passed to Linux
  */
diff --git a/include/dm/of.h b/include/dm/of.h
index fce7cef0ff..b1c934f610 100644
--- a/include/dm/of.h
+++ b/include/dm/of.h
@@ -63,6 +63,8 @@ struct device_node {
 	struct device_node *sibling;
 };
 
+#define BAD_OF_ROOT	0xdead11e3
+
 #define OF_MAX_PHANDLE_ARGS 16
 
 /**
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 443db6252d..0f38b3e736 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -353,6 +353,16 @@ static inline oftree oftree_from_np(struct device_node *root)
 }
 
 /**
+ * oftree_dispose() - Dispose of an oftree
+ *
+ * This can be used to dispose of a tree that has been created (other than
+ * the control FDT which must not be disposed)
+ *
+ * @tree: Tree to dispose
+ */
+void oftree_dispose(oftree tree);
+
+/**
  * ofnode_name_eq() - Check if the node name is equivalent to a given name
  *                    ignoring the unit address
  *
diff --git a/include/dm/platform_data/serial_pl01x.h b/include/dm/platform_data/serial_pl01x.h
index e3d4e308a1..811697ce5c 100644
--- a/include/dm/platform_data/serial_pl01x.h
+++ b/include/dm/platform_data/serial_pl01x.h
@@ -20,7 +20,11 @@ enum pl01x_type {
  * @skip_init: Don't attempt to change port configuration (also means @clock
  * is ignored)
  */
+#include <dt-structs.h>
 struct pl01x_serial_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_serial_pl01x dtplat;
+#endif
 	unsigned long base;
 	enum pl01x_type type;
 	unsigned int clock;
diff --git a/include/dm/platform_data/spi_pl022.h b/include/dm/platform_data/spi_pl022.h
deleted file mode 100644
index 7f74b3cbc5..0000000000
--- a/include/dm/platform_data/spi_pl022.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2018
- * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
- *
- * Structure for use with U_BOOT_DRVINFO for pl022 SPI devices or to use
- * in of_to_plat.
- */
-
-#ifndef __spi_pl022_h
-#define __spi_pl022_h
-
-#include <fdtdec.h>
-
-struct pl022_spi_pdata {
-	fdt_addr_t addr;
-	fdt_size_t size;
-	unsigned int freq;
-};
-
-#endif /* __spi_pl022_h */
diff --git a/include/dm/read.h b/include/dm/read.h
index 56ac076c9f..c2615f72f4 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -247,6 +247,20 @@ fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index,
 				    fdt_size_t *size);
 
 /**
+ * dev_read_addr_size_index_ptr() - Get the indexed reg property of a device
+ *                                  as a pointer
+ *
+ * @dev: Device to read from
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ *	   and @index is used to select which one is required
+ * @size: place to put size value (on success)
+ *
+ * Return: pointer or NULL if not found
+ */
+void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index,
+				   fdt_size_t *size);
+
+/**
  * dev_remap_addr_index() - Get the indexed reg property of a device
  *                               as a memory-mapped I/O pointer
  *
@@ -347,18 +361,13 @@ fdt_addr_t dev_read_addr_pci(const struct udevice *dev);
 void *dev_remap_addr(const struct udevice *dev);
 
 /**
- * dev_read_addr_size() - get address and size from a device property
- *
- * This does no address translation. It simply reads an property that contains
- * an address and a size value, one after the other.
+ * dev_read_addr_size() - Get the reg property of a device
  *
  * @dev: Device to read from
- * @propname: property to read
  * @sizep: place to put size value (on success)
  * Return: address value, or FDT_ADDR_T_NONE on error
  */
-fdt_addr_t dev_read_addr_size(const struct udevice *dev, const char *propname,
-			      fdt_size_t *sizep);
+fdt_addr_t dev_read_addr_size(const struct udevice *dev, fdt_size_t *sizep);
 
 /**
  * dev_read_name() - get the name of a device's node
@@ -957,6 +966,13 @@ static inline fdt_addr_t dev_read_addr_size_index(const struct udevice *dev,
 	return devfdt_get_addr_size_index(dev, index, size);
 }
 
+static inline void *dev_read_addr_size_index_ptr(const struct udevice *dev,
+						 int index,
+						 fdt_size_t *size)
+{
+	return devfdt_get_addr_size_index_ptr(dev, index, size);
+}
+
 static inline fdt_addr_t dev_read_addr_name(const struct udevice *dev,
 					    const char *name)
 {
@@ -1002,10 +1018,9 @@ static inline void *dev_remap_addr_name(const struct udevice *dev,
 }
 
 static inline fdt_addr_t dev_read_addr_size(const struct udevice *dev,
-					    const char *propname,
 					    fdt_size_t *sizep)
 {
-	return ofnode_get_addr_size(dev_ofnode(dev), propname, sizep);
+	return dev_read_addr_size_index(dev, 0, sizep);
 }
 
 static inline const char *dev_read_name(const struct udevice *dev)
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 307ad6931c..0432c95c9e 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -4,6 +4,11 @@
  *
  * (C) Copyright 2012
  * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
  */
 
 #ifndef _DM_UCLASS_ID_H
@@ -57,6 +62,8 @@ enum uclass_id {
 	UCLASS_ETH,		/* Ethernet device */
 	UCLASS_ETH_PHY,		/* Ethernet PHY device */
 	UCLASS_EXTCON,		/* External Connector Class */
+	UCLASS_FFA,		/* Arm Firmware Framework for Armv8-A */
+	UCLASS_FFA_EMUL,		/* sandbox FF-A device emulator */
 	UCLASS_FIRMWARE,	/* Firmware */
 	UCLASS_FPGA,		/* FPGA device */
 	UCLASS_FUZZING_ENGINE,	/* Fuzzing engine */
diff --git a/include/dp83848.h b/include/dp83848.h
deleted file mode 100644
index f1bc3d86f2..0000000000
--- a/include/dp83848.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * DP83848 ethernet Physical layer
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- */
-
-
-/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */
-
-#define DP83848_CTL_REG		0x0	/* Basic Mode Control Reg */
-#define DP83848_STAT_REG		0x1	/* Basic Mode Status Reg */
-#define DP83848_PHYID1_REG		0x2	/* PHY Idendifier Reg 1 */
-#define DP83848_PHYID2_REG		0x3	/* PHY Idendifier Reg 2 */
-#define DP83848_ANA_REG			0x4	/* Auto_Neg Advt Reg  */
-#define DP83848_ANLPA_REG		0x5	/* Auto_neg Link Partner Ability Reg */
-#define DP83848_ANE_REG			0x6	/* Auto-neg Expansion Reg  */
-#define DP83848_PHY_STAT_REG		0x10	/* PHY Status Register  */
-#define DP83848_PHY_INTR_CTRL_REG	0x11	/* PHY Interrupt Control Register */
-#define DP83848_PHY_CTRL_REG		0x19	/* PHY Status Register  */
-
-/*--Bit definitions: DP83848_CTL_REG */
-#define DP83848_RESET		(1 << 15)  /* 1= S/W Reset */
-#define DP83848_LOOPBACK	(1 << 14)  /* 1=loopback Enabled */
-#define DP83848_SPEED_SELECT	(1 << 13)
-#define DP83848_AUTONEG		(1 << 12)
-#define DP83848_POWER_DOWN	(1 << 11)
-#define DP83848_ISOLATE		(1 << 10)
-#define DP83848_RESTART_AUTONEG	(1 << 9)
-#define DP83848_DUPLEX_MODE	(1 << 8)
-#define DP83848_COLLISION_TEST	(1 << 7)
-
-/*--Bit definitions: DP83848_STAT_REG */
-#define DP83848_100BASE_T4	(1 << 15)
-#define DP83848_100BASE_TX_FD	(1 << 14)
-#define DP83848_100BASE_TX_HD	(1 << 13)
-#define DP83848_10BASE_T_FD	(1 << 12)
-#define DP83848_10BASE_T_HD	(1 << 11)
-#define DP83848_MF_PREAMB_SUPPR	(1 << 6)
-#define DP83848_AUTONEG_COMP	(1 << 5)
-#define DP83848_RMT_FAULT	(1 << 4)
-#define DP83848_AUTONEG_ABILITY	(1 << 3)
-#define DP83848_LINK_STATUS	(1 << 2)
-#define DP83848_JABBER_DETECT	(1 << 1)
-#define DP83848_EXTEND_CAPAB	(1 << 0)
-
-/*--definitions: DP83848_PHYID1 */
-#define DP83848_PHYID1_OUI	0x2000
-#define DP83848_PHYID2_OUI	0x5c90
-
-/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */
-#define DP83848_NP		(1 << 15)
-#define DP83848_ACK		(1 << 14)
-#define DP83848_RF		(1 << 13)
-#define DP83848_PAUSE		(1 << 10)
-#define DP83848_T4		(1 << 9)
-#define DP83848_TX_FDX		(1 << 8)
-#define DP83848_TX_HDX		(1 << 7)
-#define DP83848_10_FDX		(1 << 6)
-#define DP83848_10_HDX		(1 << 5)
-#define DP83848_AN_IEEE_802_3	0x0001
-
-/*--Bit definitions: DP83848_ANER */
-#define DP83848_PDF		(1 << 4)
-#define DP83848_LP_NP_ABLE	(1 << 3)
-#define DP83848_NP_ABLE		(1 << 2)
-#define DP83848_PAGE_RX		(1 << 1)
-#define DP83848_LP_AN_ABLE	(1 << 0)
-
-/*--Bit definitions: DP83848_PHY_STAT */
-#define DP83848_RX_ERR_LATCH		(1 << 13)
-#define DP83848_POLARITY_STAT		(1 << 12)
-#define DP83848_FALSE_CAR_SENSE		(1 << 11)
-#define DP83848_SIG_DETECT		(1 << 10)
-#define DP83848_DESCRAM_LOCK		(1 << 9)
-#define DP83848_PAGE_RCV		(1 << 8)
-#define DP83848_PHY_RMT_FAULT		(1 << 6)
-#define DP83848_JABBER			(1 << 5)
-#define DP83848_AUTONEG_COMPLETE	(1 << 4)
-#define DP83848_LOOPBACK_STAT		(1 << 3)
-#define DP83848_DUPLEX			(1 << 2)
-#define DP83848_SPEED			(1 << 1)
-#define DP83848_LINK			(1 << 0)
diff --git a/include/ds1722.h b/include/ds1722.h
deleted file mode 100644
index e115696cea..0000000000
--- a/include/ds1722.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef _DS1722_H_
-#define _DS1722_H_
-
-#define DS1722_RESOLUTION_8BIT	0x0
-#define DS1722_RESOLUTION_9BIT	0x1
-#define DS1722_RESOLUTION_10BIT	0x2
-#define DS1722_RESOLUTION_11BIT	0x3
-#define DS1722_RESOLUTION_12BIT	0x4
-
-int ds1722_probe(int dev);
-
-#endif /* _DS1722_H_ */
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index 9d5cc2ddde..3f28ce685f 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -324,8 +324,18 @@
 #define IMX8MP_CLK_CLKOUT2_SEL			317
 #define IMX8MP_CLK_CLKOUT2_DIV			318
 #define IMX8MP_CLK_CLKOUT2			319
-
-#define IMX8MP_CLK_END				320
+#define IMX8MP_CLK_USB_SUSP			320
+#define IMX8MP_CLK_AUDIO_AHB_ROOT		IMX8MP_CLK_AUDIO_ROOT
+#define IMX8MP_CLK_AUDIO_AXI_ROOT		321
+#define IMX8MP_CLK_SAI1_ROOT			322
+#define IMX8MP_CLK_SAI2_ROOT			323
+#define IMX8MP_CLK_SAI3_ROOT			324
+#define IMX8MP_CLK_SAI5_ROOT			325
+#define IMX8MP_CLK_SAI6_ROOT			326
+#define IMX8MP_CLK_SAI7_ROOT			327
+#define IMX8MP_CLK_PDM_ROOT			328
+#define IMX8MP_CLK_MEDIA_LDB_ROOT		329
+#define IMX8MP_CLK_END				330
 
 #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG		0
 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1		1
diff --git a/include/dt-bindings/clock/microchip-mpfs-clock.h b/include/dt-bindings/clock/microchip-mpfs-clock.h
index c7ed0a8db7..79775a5134 100644
--- a/include/dt-bindings/clock/microchip-mpfs-clock.h
+++ b/include/dt-bindings/clock/microchip-mpfs-clock.h
@@ -1,7 +1,7 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
 /*
- * Copyright (C) 2020 Microchip Technology Inc.
- * Padmarao Begari <padmarao.begari@microchip.com>
+ * Daire McNamara,<daire.mcnamara@microchip.com>
+ * Copyright (C) 2020-2022 Microchip Technology Inc.  All rights reserved.
  */
 
 #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
@@ -45,4 +45,27 @@
 #define CLK_RTCREF	33
 #define CLK_MSSPLL	34
 
+/* Clock Conditioning Circuitry Clock IDs */
+
+#define CLK_CCC_PLL0		0
+#define CLK_CCC_PLL1		1
+#define CLK_CCC_DLL0		2
+#define CLK_CCC_DLL1		3
+
+#define CLK_CCC_PLL0_OUT0	4
+#define CLK_CCC_PLL0_OUT1	5
+#define CLK_CCC_PLL0_OUT2	6
+#define CLK_CCC_PLL0_OUT3	7
+
+#define CLK_CCC_PLL1_OUT0	8
+#define CLK_CCC_PLL1_OUT1	9
+#define CLK_CCC_PLL1_OUT2	10
+#define CLK_CCC_PLL1_OUT3	11
+
+#define CLK_CCC_DLL0_OUT0	12
+#define CLK_CCC_DLL0_OUT1	13
+
+#define CLK_CCC_DLL1_OUT0	14
+#define CLK_CCC_DLL1_OUT1	15
+
 #endif	/* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
new file mode 100644
index 0000000000..5c21bf6311
--- /dev/null
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -0,0 +1,349 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7988_H
+#define _DT_BINDINGS_CLK_MT7988_H
+
+/* INFRACFG */
+/* mtk_fixed_factor */
+#define CK_INFRA_CK_F26M	  0
+#define CK_INFRA_PWM_O		  1
+#define CK_INFRA_PCIE_OCC_P0	  2
+#define CK_INFRA_PCIE_OCC_P1	  3
+#define CK_INFRA_PCIE_OCC_P2	  4
+#define CK_INFRA_PCIE_OCC_P3	  5
+#define CK_INFRA_133M_HCK	  6
+#define CK_INFRA_133M_PHCK	  7
+#define CK_INFRA_66M_PHCK	  8
+#define CK_INFRA_FAUD_L_O	  9
+#define CK_INFRA_FAUD_AUD_O	  10
+#define CK_INFRA_FAUD_EG2_O	  11
+#define CK_INFRA_I2C_O		  12
+#define CK_INFRA_UART_O0	  13
+#define CK_INFRA_UART_O1	  14
+#define CK_INFRA_UART_O2	  15
+#define CK_INFRA_NFI_O		  16
+#define CK_INFRA_SPINFI_O	  17
+#define CK_INFRA_SPI0_O		  18
+#define CK_INFRA_SPI1_O		  19
+#define CK_INFRA_LB_MUX_FRTC	  20
+#define CK_INFRA_FRTC		  21
+#define CK_INFRA_FMSDC400_O	  22
+#define CK_INFRA_FMSDC2_HCK_OCC	  23
+#define CK_INFRA_PERI_133M	  24
+#define CK_INFRA_USB_O		  25
+#define CK_INFRA_USB_O_P1	  26
+#define CK_INFRA_USB_FRMCNT_O	  27
+#define CK_INFRA_USB_FRMCNT_O_P1  28
+#define CK_INFRA_USB_XHCI_O	  29
+#define CK_INFRA_USB_XHCI_O_P1	  30
+#define CK_INFRA_USB_PIPE_O	  31
+#define CK_INFRA_USB_PIPE_O_P1	  32
+#define CK_INFRA_USB_UTMI_O	  33
+#define CK_INFRA_USB_UTMI_O_P1	  34
+#define CK_INFRA_PCIE_PIPE_OCC_P0 35
+#define CK_INFRA_PCIE_PIPE_OCC_P1 36
+#define CK_INFRA_PCIE_PIPE_OCC_P2 37
+#define CK_INFRA_PCIE_PIPE_OCC_P3 38
+#define CK_INFRA_F26M_O0	  39
+#define CK_INFRA_F26M_O1	  40
+#define CK_INFRA_133M_MCK	  41
+#define CK_INFRA_66M_MCK	  42
+#define CK_INFRA_PERI_66M_O	  43
+#define CK_INFRA_USB_SYS_O	  44
+#define CK_INFRA_USB_SYS_O_P1	  45
+
+/* INFRACFG_AO */
+#define GATE_OFFSET 65
+/* mtk_mux */
+#define CK_INFRA_MUX_UART0_SEL		46 /* Linux CLK ID (0) */
+#define CK_INFRA_MUX_UART1_SEL		47 /* Linux CLK ID (1) */
+#define CK_INFRA_MUX_UART2_SEL		48 /* Linux CLK ID (2) */
+#define CK_INFRA_MUX_SPI0_SEL		49 /* Linux CLK ID (3) */
+#define CK_INFRA_MUX_SPI1_SEL		50 /* Linux CLK ID (4) */
+#define CK_INFRA_MUX_SPI2_SEL		51 /* Linux CLK ID (5) */
+#define CK_INFRA_PWM_SEL		52 /* Linux CLK ID (6) */
+#define CK_INFRA_PWM_CK1_SEL		53 /* Linux CLK ID (7) */
+#define CK_INFRA_PWM_CK2_SEL		54 /* Linux CLK ID (8) */
+#define CK_INFRA_PWM_CK3_SEL		55 /* Linux CLK ID (9) */
+#define CK_INFRA_PWM_CK4_SEL		56 /* Linux CLK ID (10) */
+#define CK_INFRA_PWM_CK5_SEL		57 /* Linux CLK ID (11) */
+#define CK_INFRA_PWM_CK6_SEL		58 /* Linux CLK ID (12) */
+#define CK_INFRA_PWM_CK7_SEL		59 /* Linux CLK ID (13) */
+#define CK_INFRA_PWM_CK8_SEL		60 /* Linux CLK ID (14) */
+#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */
+#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */
+#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */
+#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */
+/* mtk_gate */
+#define CK_INFRA_66M_GPT_BCK	     (65 - GATE_OFFSET) /* Linux CLK ID (19) */
+#define CK_INFRA_66M_PWM_HCK	     (66 - GATE_OFFSET) /* Linux CLK ID (20) */
+#define CK_INFRA_66M_PWM_BCK	     (67 - GATE_OFFSET) /* Linux CLK ID (21) */
+#define CK_INFRA_66M_PWM_CK1	     (68 - GATE_OFFSET) /* Linux CLK ID (22) */
+#define CK_INFRA_66M_PWM_CK2	     (69 - GATE_OFFSET) /* Linux CLK ID (23) */
+#define CK_INFRA_66M_PWM_CK3	     (70 - GATE_OFFSET) /* Linux CLK ID (24) */
+#define CK_INFRA_66M_PWM_CK4	     (71 - GATE_OFFSET) /* Linux CLK ID (25) */
+#define CK_INFRA_66M_PWM_CK5	     (72 - GATE_OFFSET) /* Linux CLK ID (26) */
+#define CK_INFRA_66M_PWM_CK6	     (73 - GATE_OFFSET) /* Linux CLK ID (27) */
+#define CK_INFRA_66M_PWM_CK7	     (74 - GATE_OFFSET) /* Linux CLK ID (28) */
+#define CK_INFRA_66M_PWM_CK8	     (75 - GATE_OFFSET) /* Linux CLK ID (29) */
+#define CK_INFRA_133M_CQDMA_BCK	     (76 - GATE_OFFSET) /* Linux CLK ID (30) */
+#define CK_INFRA_66M_AUD_SLV_BCK     (77 - GATE_OFFSET) /* Linux CLK ID (31) */
+#define CK_INFRA_AUD_26M	     (78 - GATE_OFFSET) /* Linux CLK ID (32) */
+#define CK_INFRA_AUD_L		     (79 - GATE_OFFSET) /* Linux CLK ID (33) */
+#define CK_INFRA_AUD_AUD	     (80 - GATE_OFFSET) /* Linux CLK ID (34) */
+#define CK_INFRA_AUD_EG2	     (81 - GATE_OFFSET) /* Linux CLK ID (35) */
+#define CK_INFRA_DRAMC_F26M	     (82 - GATE_OFFSET) /* Linux CLK ID (36) */
+#define CK_INFRA_133M_DBG_ACKM	     (83 - GATE_OFFSET) /* Linux CLK ID (37) */
+#define CK_INFRA_66M_AP_DMA_BCK	     (84 - GATE_OFFSET) /* Linux CLK ID (38) */
+#define CK_INFRA_66M_SEJ_BCK	     (85 - GATE_OFFSET) /* Linux CLK ID (39) */
+#define CK_INFRA_PRE_CK_SEJ_F13M     (86 - GATE_OFFSET) /* Linux CLK ID (40) */
+#define CK_INFRA_66M_TRNG	     (87 - GATE_OFFSET) /* Linux CLK ID (41) */
+#define CK_INFRA_26M_THERM_SYSTEM    (88 - GATE_OFFSET) /* Linux CLK ID (42) */
+#define CK_INFRA_I2C_BCK	     (89 - GATE_OFFSET) /* Linux CLK ID (43) */
+#define CK_INFRA_66M_UART0_PCK	     (90 - GATE_OFFSET) /* Linux CLK ID (44) */
+#define CK_INFRA_66M_UART1_PCK	     (91 - GATE_OFFSET) /* Linux CLK ID (45) */
+#define CK_INFRA_66M_UART2_PCK	     (92 - GATE_OFFSET) /* Linux CLK ID (46) */
+#define CK_INFRA_52M_UART0_CK	     (93 - GATE_OFFSET) /* Linux CLK ID (47) */
+#define CK_INFRA_52M_UART1_CK	     (94 - GATE_OFFSET) /* Linux CLK ID (48) */
+#define CK_INFRA_52M_UART2_CK	     (95 - GATE_OFFSET) /* Linux CLK ID (49) */
+#define CK_INFRA_NFI		     (96 - GATE_OFFSET) /* Linux CLK ID (50) */
+#define CK_INFRA_SPINFI		     (97 - GATE_OFFSET) /* Linux CLK ID (51) */
+#define CK_INFRA_66M_NFI_HCK	     (98 - GATE_OFFSET) /* Linux CLK ID (52) */
+#define CK_INFRA_104M_SPI0	     (99 - GATE_OFFSET) /* Linux CLK ID (53) */
+#define CK_INFRA_104M_SPI1	     (100 - GATE_OFFSET) /* Linux CLK ID (54) */
+#define CK_INFRA_104M_SPI2_BCK	     (101 - GATE_OFFSET) /* Linux CLK ID (55) */
+#define CK_INFRA_66M_SPI0_HCK	     (102 - GATE_OFFSET) /* Linux CLK ID (56) */
+#define CK_INFRA_66M_SPI1_HCK	     (103 - GATE_OFFSET) /* Linux CLK ID (57) */
+#define CK_INFRA_66M_SPI2_HCK	     (104 - GATE_OFFSET) /* Linux CLK ID (58) */
+#define CK_INFRA_66M_FLASHIF_AXI     (105 - GATE_OFFSET) /* Linux CLK ID (59) */
+#define CK_INFRA_RTC		     (106 - GATE_OFFSET) /* Linux CLK ID (60) */
+#define CK_INFRA_26M_ADC_BCK	     (107 - GATE_OFFSET) /* Linux CLK ID (61) */
+#define CK_INFRA_RC_ADC		     (108 - GATE_OFFSET) /* Linux CLK ID (62) */
+#define CK_INFRA_MSDC400	     (109 - GATE_OFFSET) /* Linux CLK ID (63) */
+#define CK_INFRA_MSDC2_HCK	     (110 - GATE_OFFSET) /* Linux CLK ID (64) */
+#define CK_INFRA_133M_MSDC_0_HCK     (111 - GATE_OFFSET) /* Linux CLK ID (65) */
+#define CK_INFRA_66M_MSDC_0_HCK	     (112 - GATE_OFFSET) /* Linux CLK ID (66) */
+#define CK_INFRA_133M_CPUM_BCK	     (113 - GATE_OFFSET) /* Linux CLK ID (67) */
+#define CK_INFRA_BIST2FPC	     (114 - GATE_OFFSET) /* Linux CLK ID (68) */
+#define CK_INFRA_I2C_X16W_MCK_CK_P1  (115 - GATE_OFFSET) /* Linux CLK ID (69) */
+#define CK_INFRA_I2C_X16W_PCK_CK_P1  (116 - GATE_OFFSET) /* Linux CLK ID (70) */
+#define CK_INFRA_133M_USB_HCK	     (117 - GATE_OFFSET) /* Linux CLK ID (71) */
+#define CK_INFRA_133M_USB_HCK_CK_P1  (118 - GATE_OFFSET) /* Linux CLK ID (72) */
+#define CK_INFRA_66M_USB_HCK	     (119 - GATE_OFFSET) /* Linux CLK ID (73) */
+#define CK_INFRA_66M_USB_HCK_CK_P1   (120 - GATE_OFFSET) /* Linux CLK ID (74) */
+#define CK_INFRA_USB_SYS	     (121 - GATE_OFFSET) /* Linux CLK ID (75) */
+#define CK_INFRA_USB_SYS_CK_P1	     (122 - GATE_OFFSET) /* Linux CLK ID (76) */
+#define CK_INFRA_USB_REF	     (123 - GATE_OFFSET) /* Linux CLK ID (77) */
+#define CK_INFRA_USB_CK_P1	     (124 - GATE_OFFSET) /* Linux CLK ID (78) */
+#define CK_INFRA_USB_FRMCNT	     (125 - GATE_OFFSET) /* Linux CLK ID (79) */
+#define CK_INFRA_USB_FRMCNT_CK_P1    (126 - GATE_OFFSET) /* Linux CLK ID (80) */
+#define CK_INFRA_USB_PIPE	     (127 - GATE_OFFSET) /* Linux CLK ID (81) */
+#define CK_INFRA_USB_PIPE_CK_P1	     (128 - GATE_OFFSET) /* Linux CLK ID (82) */
+#define CK_INFRA_USB_UTMI	     (129 - GATE_OFFSET) /* Linux CLK ID (83) */
+#define CK_INFRA_USB_UTMI_CK_P1	     (130 - GATE_OFFSET) /* Linux CLK ID (84) */
+#define CK_INFRA_USB_XHCI	     (131 - GATE_OFFSET) /* Linux CLK ID (85) */
+#define CK_INFRA_USB_XHCI_CK_P1	     (132 - GATE_OFFSET) /* Linux CLK ID (86) */
+#define CK_INFRA_PCIE_GFMUX_TL_P0    (133 - GATE_OFFSET) /* Linux CLK ID (87) */
+#define CK_INFRA_PCIE_GFMUX_TL_P1    (134 - GATE_OFFSET) /* Linux CLK ID (88) */
+#define CK_INFRA_PCIE_GFMUX_TL_P2    (135 - GATE_OFFSET) /* Linux CLK ID (89) */
+#define CK_INFRA_PCIE_GFMUX_TL_P3    (136 - GATE_OFFSET) /* Linux CLK ID (90) */
+#define CK_INFRA_PCIE_PIPE_P0	     (137 - GATE_OFFSET) /* Linux CLK ID (91) */
+#define CK_INFRA_PCIE_PIPE_P1	     (138 - GATE_OFFSET) /* Linux CLK ID (92) */
+#define CK_INFRA_PCIE_PIPE_P2	     (139 - GATE_OFFSET) /* Linux CLK ID (93) */
+#define CK_INFRA_PCIE_PIPE_P3	     (140 - GATE_OFFSET) /* Linux CLK ID (94) */
+#define CK_INFRA_133M_PCIE_CK_P0     (141 - GATE_OFFSET) /* Linux CLK ID (95) */
+#define CK_INFRA_133M_PCIE_CK_P1     (142 - GATE_OFFSET) /* Linux CLK ID (96) */
+#define CK_INFRA_133M_PCIE_CK_P2     (143 - GATE_OFFSET) /* Linux CLK ID (97) */
+#define CK_INFRA_133M_PCIE_CK_P3     (144 - GATE_OFFSET) /* Linux CLK ID (98) */
+#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */
+#define CK_INFRA_PCIE_PERI_26M_CK_P1                                           \
+	(146 - GATE_OFFSET) /* Linux CLK ID (100) */
+#define CK_INFRA_PCIE_PERI_26M_CK_P2                                           \
+	(147 - GATE_OFFSET) /* Linux CLK ID (101) */
+#define CK_INFRA_PCIE_PERI_26M_CK_P3                                           \
+	(148 - GATE_OFFSET) /* Linux CLK ID (102) */
+
+/* TOPCKGEN */
+/* mtk_fixed_factor */
+#define CK_TOP_CB_CKSQ_40M    0 /* Linux CLK ID (74) */
+#define CK_TOP_CB_M_416M      1 /* Linux CLK ID (75) */
+#define CK_TOP_CB_M_D2	      2 /* Linux CLK ID (76) */
+#define CK_TOP_M_D3_D2	      3 /* Linux CLK ID (77) */
+#define CK_TOP_CB_M_D4	      4 /* Linux CLK ID (78) */
+#define CK_TOP_CB_M_D8	      5 /* Linux CLK ID (79) */
+#define CK_TOP_M_D8_D2	      6 /* Linux CLK ID (80) */
+#define CK_TOP_CB_MM_720M     7 /* Linux CLK ID (81) */
+#define CK_TOP_CB_MM_D2	      8 /* Linux CLK ID (82) */
+#define CK_TOP_CB_MM_D3_D5    9 /* Linux CLK ID (83) */
+#define CK_TOP_CB_MM_D4	      10 /* Linux CLK ID (84) */
+#define CK_TOP_MM_D6_D2	      11 /* Linux CLK ID (85) */
+#define CK_TOP_CB_MM_D8	      12 /* Linux CLK ID (86) */
+#define CK_TOP_CB_APLL2_196M  13 /* Linux CLK ID (87) */
+#define CK_TOP_CB_APLL2_D4    14 /* Linux CLK ID (88) */
+#define CK_TOP_CB_NET1_D4     15 /* Linux CLK ID (89) */
+#define CK_TOP_CB_NET1_D5     16 /* Linux CLK ID (90) */
+#define CK_TOP_NET1_D5_D2     17 /* Linux CLK ID (91) */
+#define CK_TOP_NET1_D5_D4     18 /* Linux CLK ID (92) */
+#define CK_TOP_CB_NET1_D8     19 /* Linux CLK ID (93) */
+#define CK_TOP_NET1_D8_D2     20 /* Linux CLK ID (94) */
+#define CK_TOP_NET1_D8_D4     21 /* Linux CLK ID (95) */
+#define CK_TOP_NET1_D8_D8     22 /* Linux CLK ID (96) */
+#define CK_TOP_NET1_D8_D16    23 /* Linux CLK ID (97) */
+#define CK_TOP_CB_NET2_800M   24 /* Linux CLK ID (98) */
+#define CK_TOP_CB_NET2_D2     25 /* Linux CLK ID (99) */
+#define CK_TOP_CB_NET2_D4     26 /* Linux CLK ID (100) */
+#define CK_TOP_NET2_D4_D4     27 /* Linux CLK ID (101) */
+#define CK_TOP_NET2_D4_D8     28 /* Linux CLK ID (102) */
+#define CK_TOP_CB_NET2_D6     29 /* Linux CLK ID (103) */
+#define CK_TOP_CB_NET2_D8     30 /* Linux CLK ID (104) */
+#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */
+#define CK_TOP_CB_SGM_325M    32 /* Linux CLK ID (106) */
+#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */
+#define CK_TOP_CB_MSDC_400M   34 /* Linux CLK ID (108) */
+#define CK_TOP_CKSQ_40M_D2    35 /* Linux CLK ID (109) */
+#define CK_TOP_CB_RTC_32K     36 /* Linux CLK ID (110) */
+#define CK_TOP_CB_RTC_32P7K   37 /* Linux CLK ID (111) */
+#define CK_TOP_INFRA_F32K     38 /* Linux CLK ID (112) */
+#define CK_TOP_CKSQ_SRC	      39 /* Linux CLK ID (113) */
+#define CK_TOP_NETSYS_2X      40 /* Linux CLK ID (114) */
+#define CK_TOP_NETSYS_GSW     41 /* Linux CLK ID (115) */
+#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */
+#define CK_TOP_EIP197	      43 /* Linux CLK ID (117) */
+#define CK_TOP_EMMC_250M      44 /* Linux CLK ID (118) */
+#define CK_TOP_EMMC_400M      45 /* Linux CLK ID (119) */
+#define CK_TOP_SPI	      46 /* Linux CLK ID (120) */
+#define CK_TOP_SPIM_MST	      47 /* Linux CLK ID (121) */
+#define CK_TOP_NFI1X	      48 /* Linux CLK ID (122) */
+#define CK_TOP_SPINFI_BCK     49 /* Linux CLK ID (123) */
+#define CK_TOP_I2C_BCK	      50 /* Linux CLK ID (124) */
+#define CK_TOP_USB_SYS	      51 /* Linux CLK ID (125) */
+#define CK_TOP_USB_SYS_P1     52 /* Linux CLK ID (126) */
+#define CK_TOP_USB_XHCI	      53 /* Linux CLK ID (127) */
+#define CK_TOP_USB_XHCI_P1    54 /* Linux CLK ID (128) */
+#define CK_TOP_USB_FRMCNT     55 /* Linux CLK ID (129) */
+#define CK_TOP_USB_FRMCNT_P1  56 /* Linux CLK ID (130) */
+#define CK_TOP_AUD	      57 /* Linux CLK ID (131) */
+#define CK_TOP_A1SYS	      58 /* Linux CLK ID (132) */
+#define CK_TOP_AUD_L	      59 /* Linux CLK ID (133) */
+#define CK_TOP_A_TUNER	      60 /* Linux CLK ID (134) */
+#define CK_TOP_SYSAXI	      61 /* Linux CLK ID (135) */
+#define CK_TOP_INFRA_F26M     62 /* Linux CLK ID (136) */
+#define CK_TOP_USB_REF	      63 /* Linux CLK ID (137) */
+#define CK_TOP_USB_CK_P1      64 /* Linux CLK ID (138) */
+/* mtk_mux */
+#define CK_TOP_NETSYS_SEL	      65 /* Linux CLK ID (0) */
+#define CK_TOP_NETSYS_500M_SEL	      66 /* Linux CLK ID (1) */
+#define CK_TOP_NETSYS_2X_SEL	      67 /* Linux CLK ID (2) */
+#define CK_TOP_NETSYS_GSW_SEL	      68 /* Linux CLK ID (3) */
+#define CK_TOP_ETH_GMII_SEL	      69 /* Linux CLK ID (4) */
+#define CK_TOP_NETSYS_MCU_SEL	      70 /* Linux CLK ID (5) */
+#define CK_TOP_NETSYS_PAO_2X_SEL      71 /* Linux CLK ID (6) */
+#define CK_TOP_EIP197_SEL	      72 /* Linux CLK ID (7) */
+#define CK_TOP_AXI_INFRA_SEL	      73 /* Linux CLK ID (8) */
+#define CK_TOP_UART_SEL		      74 /* Linux CLK ID (9) */
+#define CK_TOP_EMMC_250M_SEL	      75 /* Linux CLK ID (10) */
+#define CK_TOP_EMMC_400M_SEL	      76 /* Linux CLK ID (11) */
+#define CK_TOP_SPI_SEL		      77 /* Linux CLK ID (12) */
+#define CK_TOP_SPIM_MST_SEL	      78 /* Linux CLK ID (13) */
+#define CK_TOP_NFI1X_SEL	      79 /* Linux CLK ID (14) */
+#define CK_TOP_SPINFI_SEL	      80 /* Linux CLK ID (15) */
+#define CK_TOP_PWM_SEL		      81 /* Linux CLK ID (16) */
+#define CK_TOP_I2C_SEL		      82 /* Linux CLK ID (17) */
+#define CK_TOP_PCIE_MBIST_250M_SEL    83 /* Linux CLK ID (18) */
+#define CK_TOP_PEXTP_TL_SEL	      84 /* Linux CLK ID (19) */
+#define CK_TOP_PEXTP_TL_P1_SEL	      85 /* Linux CLK ID (20) */
+#define CK_TOP_PEXTP_TL_P2_SEL	      86 /* Linux CLK ID (21) */
+#define CK_TOP_PEXTP_TL_P3_SEL	      87 /* Linux CLK ID (22) */
+#define CK_TOP_USB_SYS_SEL	      88 /* Linux CLK ID (23) */
+#define CK_TOP_USB_SYS_P1_SEL	      89 /* Linux CLK ID (24) */
+#define CK_TOP_USB_XHCI_SEL	      90 /* Linux CLK ID (25) */
+#define CK_TOP_USB_XHCI_P1_SEL	      91 /* Linux CLK ID (26) */
+#define CK_TOP_USB_FRMCNT_SEL	      92 /* Linux CLK ID (27) */
+#define CK_TOP_USB_FRMCNT_P1_SEL      93 /* Linux CLK ID (28) */
+#define CK_TOP_AUD_SEL		      94 /* Linux CLK ID (29) */
+#define CK_TOP_A1SYS_SEL	      95 /* Linux CLK ID (30) */
+#define CK_TOP_AUD_L_SEL	      96 /* Linux CLK ID (31) */
+#define CK_TOP_A_TUNER_SEL	      97 /* Linux CLK ID (32) */
+#define CK_TOP_SSPXTP_SEL	      98 /* Linux CLK ID (33) */
+#define CK_TOP_USB_PHY_SEL	      99 /* Linux CLK ID (34) */
+#define CK_TOP_USXGMII_SBUS_0_SEL     100 /* Linux CLK ID (35) */
+#define CK_TOP_USXGMII_SBUS_1_SEL     101 /* Linux CLK ID (36) */
+#define CK_TOP_SGM_0_SEL	      102 /* Linux CLK ID (37) */
+#define CK_TOP_SGM_SBUS_0_SEL	      103 /* Linux CLK ID (38) */
+#define CK_TOP_SGM_1_SEL	      104 /* Linux CLK ID (39) */
+#define CK_TOP_SGM_SBUS_1_SEL	      105 /* Linux CLK ID (40) */
+#define CK_TOP_XFI_PHY_0_XTAL_SEL     106 /* Linux CLK ID (41) */
+#define CK_TOP_XFI_PHY_1_XTAL_SEL     107 /* Linux CLK ID (42) */
+#define CK_TOP_SYSAXI_SEL	      108 /* Linux CLK ID (43) */
+#define CK_TOP_SYSAPB_SEL	      109 /* Linux CLK ID (44) */
+#define CK_TOP_ETH_REFCK_50M_SEL      110 /* Linux CLK ID (45) */
+#define CK_TOP_ETH_SYS_200M_SEL	      111 /* Linux CLK ID (46) */
+#define CK_TOP_ETH_SYS_SEL	      112 /* Linux CLK ID (47) */
+#define CK_TOP_ETH_XGMII_SEL	      113 /* Linux CLK ID (48) */
+#define CK_TOP_BUS_TOPS_SEL	      114 /* Linux CLK ID (49) */
+#define CK_TOP_NPU_TOPS_SEL	      115 /* Linux CLK ID (50) */
+#define CK_TOP_DRAMC_SEL	      116 /* Linux CLK ID (51) */
+#define CK_TOP_DRAMC_MD32_SEL	      117 /* Linux CLK ID (52) */
+#define CK_TOP_INFRA_F26M_SEL	      118 /* Linux CLK ID (53) */
+#define CK_TOP_PEXTP_P0_SEL	      119 /* Linux CLK ID (54) */
+#define CK_TOP_PEXTP_P1_SEL	      120 /* Linux CLK ID (55) */
+#define CK_TOP_PEXTP_P2_SEL	      121 /* Linux CLK ID (56) */
+#define CK_TOP_PEXTP_P3_SEL	      122 /* Linux CLK ID (57) */
+#define CK_TOP_DA_XTP_GLB_P0_SEL      123 /* Linux CLK ID (58) */
+#define CK_TOP_DA_XTP_GLB_P1_SEL      124 /* Linux CLK ID (59) */
+#define CK_TOP_DA_XTP_GLB_P2_SEL      125 /* Linux CLK ID (60) */
+#define CK_TOP_DA_XTP_GLB_P3_SEL      126 /* Linux CLK ID (61) */
+#define CK_TOP_CKM_SEL		      127 /* Linux CLK ID (62) */
+#define CK_TOP_DA_SELM_XTAL_SEL	      128 /* Linux CLK ID (63) */
+#define CK_TOP_PEXTP_SEL	      129 /* Linux CLK ID (64) */
+#define CK_TOP_TOPS_P2_26M_SEL	      130 /* Linux CLK ID (65) */
+#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */
+#define CK_TOP_NETSYS_SYNC_250M_SEL   132 /* Linux CLK ID (67) */
+#define CK_TOP_MACSEC_SEL	      133 /* Linux CLK ID (68) */
+#define CK_TOP_NETSYS_TOPS_400M_SEL   134 /* Linux CLK ID (69) */
+#define CK_TOP_NETSYS_PPEFB_250M_SEL  135 /* Linux CLK ID (70) */
+#define CK_TOP_NETSYS_WARP_SEL	      136 /* Linux CLK ID (71) */
+#define CK_TOP_ETH_MII_SEL	      137 /* Linux CLK ID (72) */
+#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */
+
+/* APMIXEDSYS */
+/* mtk_pll_data */
+#define CK_APMIXED_NETSYSPLL  0
+#define CK_APMIXED_MPLL	      1
+#define CK_APMIXED_MMPLL      2
+#define CK_APMIXED_APLL2      3
+#define CK_APMIXED_NET1PLL    4
+#define CK_APMIXED_NET2PLL    5
+#define CK_APMIXED_WEDMCUPLL  6
+#define CK_APMIXED_SGMPLL     7
+#define CK_APMIXED_ARM_B      8
+#define CK_APMIXED_CCIPLL2_B  9
+#define CK_APMIXED_USXGMIIPLL 10
+#define CK_APMIXED_MSDCPLL    11
+
+/* ETHSYS ETH DMA  */
+/* mtk_gate */
+#define CK_ETHDMA_FE_EN 0
+
+/* SGMIISYS_0 */
+/* mtk_gate */
+#define CK_SGM0_TX_EN 0
+#define CK_SGM0_RX_EN 1
+
+/* SGMIISYS_1 */
+/* mtk_gate */
+#define CK_SGM1_TX_EN 0
+#define CK_SGM1_RX_EN 1
+
+/* ETHWARP */
+/* mtk_gate */
+#define CK_ETHWARP_WOCPU2_EN 0
+#define CK_ETHWARP_WOCPU1_EN 1
+#define CK_ETHWARP_WOCPU0_EN 2
+
+#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index 77b70e7a83..b51e3829ff 100644
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -8,6 +8,11 @@
 #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
 #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
 
+#define JH7110_SYSCLK_PLL0_OUT			0
+#define JH7110_SYSCLK_PLL1_OUT			1
+#define JH7110_SYSCLK_PLL2_OUT			2
+#define JH7110_PLLCLK_END			3
+
 #define JH7110_SYSCLK_CPU_ROOT			0
 #define JH7110_SYSCLK_CPU_CORE			1
 #define JH7110_SYSCLK_CPU_BUS			2
@@ -199,59 +204,55 @@
 #define JH7110_SYSCLK_TDM_CLK_TDM_N		188
 #define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG	189
 
-#define JH7110_SYSCLK_PLL0_OUT			190
-#define JH7110_SYSCLK_PLL1_OUT			191
-#define JH7110_SYSCLK_PLL2_OUT			192
-
-#define JH7110_SYSCLK_END			193
+#define JH7110_SYSCLK_END			190
 
-#define JH7110_AONCLK_OSC_DIV4		(JH7110_SYSCLK_END + 0)
-#define JH7110_AONCLK_APB_FUNC		(JH7110_SYSCLK_END + 1)
-#define JH7110_AONCLK_GMAC0_AHB	(JH7110_SYSCLK_END + 2)
-#define JH7110_AONCLK_GMAC0_AXI	(JH7110_SYSCLK_END + 3)
-#define JH7110_AONCLK_GMAC0_RMII_RTX	(JH7110_SYSCLK_END + 4)
-#define JH7110_AONCLK_GMAC0_TX		(JH7110_SYSCLK_END + 5)
-#define JH7110_AONCLK_GMAC0_TX_INV	(JH7110_SYSCLK_END + 6)
-#define JH7110_AONCLK_GMAC0_RX		(JH7110_SYSCLK_END + 7)
-#define JH7110_AONCLK_GMAC0_RX_INV	(JH7110_SYSCLK_END + 8)
-#define JH7110_AONCLK_OTPC_APB		(JH7110_SYSCLK_END  + 9)
-#define JH7110_AONCLK_RTC_APB		(JH7110_SYSCLK_END + 10)
-#define JH7110_AONCLK_RTC_INTERNAL	(JH7110_SYSCLK_END + 11)
-#define JH7110_AONCLK_RTC_32K		(JH7110_SYSCLK_END + 12)
-#define JH7110_AONCLK_RTC_CAL		(JH7110_SYSCLK_END + 13)
+#define JH7110_AONCLK_OSC_DIV4			0
+#define JH7110_AONCLK_APB_FUNC			1
+#define JH7110_AONCLK_GMAC0_AHB			2
+#define JH7110_AONCLK_GMAC0_AXI			3
+#define JH7110_AONCLK_GMAC0_RMII_RTX		4
+#define JH7110_AONCLK_GMAC0_TX			5
+#define JH7110_AONCLK_GMAC0_TX_INV		6
+#define JH7110_AONCLK_GMAC0_RX			7
+#define JH7110_AONCLK_GMAC0_RX_INV		8
+#define JH7110_AONCLK_OTPC_APB			9
+#define JH7110_AONCLK_RTC_APB			10
+#define JH7110_AONCLK_RTC_INTERNAL		11
+#define JH7110_AONCLK_RTC_32K			12
+#define JH7110_AONCLK_RTC_CAL			13
 
-#define JH7110_AONCLK_END		(JH7110_SYSCLK_END + 14)
+#define JH7110_AONCLK_END			14
 
-#define JH7110_STGCLK_HIFI4_CORE	(JH7110_AONCLK_END + 0)
-#define JH7110_STGCLK_USB_APB		(JH7110_AONCLK_END + 1)
-#define JH7110_STGCLK_USB_UTMI_APB	(JH7110_AONCLK_END + 2)
-#define JH7110_STGCLK_USB_AXI		(JH7110_AONCLK_END + 3)
-#define JH7110_STGCLK_USB_LPM		(JH7110_AONCLK_END + 4)
-#define JH7110_STGCLK_USB_STB		(JH7110_AONCLK_END + 5)
-#define JH7110_STGCLK_USB_APP_125	(JH7110_AONCLK_END + 6)
-#define JH7110_STGCLK_USB_REFCLK	(JH7110_AONCLK_END + 7)
-#define JH7110_STGCLK_PCIE0_AXI	(JH7110_AONCLK_END + 8)
-#define JH7110_STGCLK_PCIE0_APB	(JH7110_AONCLK_END + 9)
-#define JH7110_STGCLK_PCIE0_TL		(JH7110_AONCLK_END + 10)
-#define JH7110_STGCLK_PCIE1_AXI	(JH7110_AONCLK_END + 11)
-#define JH7110_STGCLK_PCIE1_APB	(JH7110_AONCLK_END + 12)
-#define JH7110_STGCLK_PCIE1_TL		(JH7110_AONCLK_END + 13)
-#define JH7110_STGCLK_PCIE01_MAIN	(JH7110_AONCLK_END + 14)
-#define JH7110_STGCLK_SEC_HCLK		(JH7110_AONCLK_END + 15)
-#define JH7110_STGCLK_SEC_MISCAHB	(JH7110_AONCLK_END + 16)
-#define JH7110_STGCLK_MTRX_GRP0_MAIN	(JH7110_AONCLK_END + 17)
-#define JH7110_STGCLK_MTRX_GRP0_BUS	(JH7110_AONCLK_END + 18)
-#define JH7110_STGCLK_MTRX_GRP0_STG	(JH7110_AONCLK_END + 19)
-#define JH7110_STGCLK_MTRX_GRP1_MAIN	(JH7110_AONCLK_END + 20)
-#define JH7110_STGCLK_MTRX_GRP1_BUS	(JH7110_AONCLK_END + 21)
-#define JH7110_STGCLK_MTRX_GRP1_STG	(JH7110_AONCLK_END + 22)
-#define JH7110_STGCLK_MTRX_GRP1_HIFI	(JH7110_AONCLK_END + 23)
-#define JH7110_STGCLK_E2_RTC		(JH7110_AONCLK_END + 24)
-#define JH7110_STGCLK_E2_CORE		(JH7110_AONCLK_END + 25)
-#define JH7110_STGCLK_E2_DBG		(JH7110_AONCLK_END + 26)
-#define JH7110_STGCLK_DMA1P_AXI	(JH7110_AONCLK_END + 27)
-#define JH7110_STGCLK_DMA1P_AHB	(JH7110_AONCLK_END + 28)
+#define JH7110_STGCLK_HIFI4_CORE		0
+#define JH7110_STGCLK_USB_APB			1
+#define JH7110_STGCLK_USB_UTMI_APB		2
+#define JH7110_STGCLK_USB_AXI			3
+#define JH7110_STGCLK_USB_LPM			4
+#define JH7110_STGCLK_USB_STB			5
+#define JH7110_STGCLK_USB_APP_125		6
+#define JH7110_STGCLK_USB_REFCLK		7
+#define JH7110_STGCLK_PCIE0_AXI			8
+#define JH7110_STGCLK_PCIE0_APB			9
+#define JH7110_STGCLK_PCIE0_TL			10
+#define JH7110_STGCLK_PCIE1_AXI			11
+#define JH7110_STGCLK_PCIE1_APB			12
+#define JH7110_STGCLK_PCIE1_TL			13
+#define JH7110_STGCLK_PCIE01_MAIN		14
+#define JH7110_STGCLK_SEC_HCLK			15
+#define JH7110_STGCLK_SEC_MISCAHB		16
+#define JH7110_STGCLK_MTRX_GRP0_MAIN		17
+#define JH7110_STGCLK_MTRX_GRP0_BUS		18
+#define JH7110_STGCLK_MTRX_GRP0_STG		19
+#define JH7110_STGCLK_MTRX_GRP1_MAIN		20
+#define JH7110_STGCLK_MTRX_GRP1_BUS		21
+#define JH7110_STGCLK_MTRX_GRP1_STG		22
+#define JH7110_STGCLK_MTRX_GRP1_HIFI		23
+#define JH7110_STGCLK_E2_RTC			24
+#define JH7110_STGCLK_E2_CORE			25
+#define JH7110_STGCLK_E2_DBG			26
+#define JH7110_STGCLK_DMA1P_AXI			27
+#define JH7110_STGCLK_DMA1P_AHB			28
 
-#define JH7110_STGCLK_END		(JH7110_AONCLK_END + 29)
+#define JH7110_STGCLK_END			29
 
 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h
index 799dee5b80..da4cb75674 100644
--- a/include/dt-bindings/clock/stm32mp13-clks.h
+++ b/include/dt-bindings/clock/stm32mp13-clks.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
 /*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
  * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
  */
 
diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h
new file mode 100644
index 0000000000..40e57a5ff1
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-a1-gpio.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Qianggui Song <qianggui.song@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_MESON_A1_GPIO_H
+#define _DT_BINDINGS_MESON_A1_GPIO_H
+
+#define GPIOP_0		0
+#define GPIOP_1		1
+#define GPIOP_2		2
+#define GPIOP_3		3
+#define GPIOP_4		4
+#define GPIOP_5		5
+#define GPIOP_6		6
+#define GPIOP_7		7
+#define GPIOP_8		8
+#define GPIOP_9		9
+#define GPIOP_10	10
+#define GPIOP_11	11
+#define GPIOP_12	12
+#define GPIOB_0		13
+#define GPIOB_1		14
+#define GPIOB_2		15
+#define GPIOB_3		16
+#define GPIOB_4		17
+#define GPIOB_5		18
+#define GPIOB_6		19
+#define GPIOX_0		20
+#define GPIOX_1		21
+#define GPIOX_2		22
+#define GPIOX_3		23
+#define GPIOX_4		24
+#define GPIOX_5		25
+#define GPIOX_6		26
+#define GPIOX_7		27
+#define GPIOX_8		28
+#define GPIOX_9		29
+#define GPIOX_10	30
+#define GPIOX_11	31
+#define GPIOX_12	32
+#define GPIOX_13	33
+#define GPIOX_14	34
+#define GPIOX_15	35
+#define GPIOX_16	36
+#define GPIOF_0		37
+#define GPIOF_1		38
+#define GPIOF_2		39
+#define GPIOF_3		40
+#define GPIOF_4		41
+#define GPIOF_5		42
+#define GPIOF_6		43
+#define GPIOF_7		44
+#define GPIOF_8		45
+#define GPIOF_9		46
+#define GPIOF_10	47
+#define GPIOF_11	48
+#define GPIOF_12	49
+#define GPIOA_0		50
+#define GPIOA_1		51
+#define GPIOA_2		52
+#define GPIOA_3		53
+#define GPIOA_4		54
+#define GPIOA_5		55
+#define GPIOA_6		56
+#define GPIOA_7		57
+#define GPIOA_8		58
+#define GPIOA_9		59
+#define GPIOA_10	60
+#define GPIOA_11	61
+
+#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */
diff --git a/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h b/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h
deleted file mode 100644
index eba1bac7df..0000000000
--- a/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/* Copyright (c) 2020-2021 Microchip Technology Inc */
-
-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
-
-#define PLIC_INT_INVALID						0
-#define PLIC_INT_L2_METADATA_CORR				1
-#define PLIC_INT_L2_METADATA_UNCORR				2
-#define PLIC_INT_L2_DATA_CORR					3
-#define PLIC_INT_L2_DATA_UNCORR					4
-#define PLIC_INT_DMA_CH0_DONE					5
-#define PLIC_INT_DMA_CH0_ERR					6
-#define PLIC_INT_DMA_CH1_DONE					7
-#define PLIC_INT_DMA_CH1_ERR					8
-#define PLIC_INT_DMA_CH2_DONE					9
-#define PLIC_INT_DMA_CH2_ERR					10
-#define PLIC_INT_DMA_CH3_DONE					11
-#define PLIC_INT_DMA_CH3_ERR					12
-
-#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0		13
-#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1		14
-#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2		15
-#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3		16
-#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4		17
-#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5		18
-#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6		19
-#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7		20
-#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8		21
-#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9		22
-#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10		23
-#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11		24
-#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12		25
-#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13		26
-#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14		27
-#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15		28
-#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16		29
-#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17		30
-#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18		31
-#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19		32
-#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20		33
-#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21		34
-#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22		35
-#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23		36
-#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24		37
-#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25		38
-#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26		39
-#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27		40
-#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28		41
-#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29		42
-#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30		43
-#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31		44
-#define PLIC_INT_GPIO1_BIT18					45
-#define PLIC_INT_GPIO1_BIT19					46
-#define PLIC_INT_GPIO1_BIT20					47
-#define PLIC_INT_GPIO1_BIT21					48
-#define PLIC_INT_GPIO1_BIT22					49
-#define PLIC_INT_GPIO1_BIT23					50
-#define PLIC_INT_GPIO0_NON_DIRECT				51
-#define PLIC_INT_GPIO1_NON_DIRECT				52
-#define PLIC_INT_GPIO2_NON_DIRECT				53
-#define PLIC_INT_SPI0							54
-#define PLIC_INT_SPI1							55
-#define PLIC_INT_CAN0							56
-#define PLIC_INT_CAN1							57
-#define PLIC_INT_I2C0_MAIN						58
-#define PLIC_INT_I2C0_ALERT						59
-#define PLIC_INT_I2C0_SUS						60
-#define PLIC_INT_I2C1_MAIN						61
-#define PLIC_INT_I2C1_ALERT						62
-#define PLIC_INT_I2C1_SUS						63
-#define PLIC_INT_MAC0_INT						64
-#define PLIC_INT_MAC0_QUEUE1					65
-#define PLIC_INT_MAC0_QUEUE2					66
-#define PLIC_INT_MAC0_QUEUE3					67
-#define PLIC_INT_MAC0_EMAC						68
-#define PLIC_INT_MAC0_MMSL						69
-#define PLIC_INT_MAC1_INT						70
-#define PLIC_INT_MAC1_QUEUE1					71
-#define PLIC_INT_MAC1_QUEUE2					72
-#define PLIC_INT_MAC1_QUEUE3					73
-#define PLIC_INT_MAC1_EMAC						74
-#define PLIC_INT_MAC1_MMSL						75
-#define PLIC_INT_DDRC_TRAIN						76
-#define PLIC_INT_SCB_INTERRUPT					77
-#define PLIC_INT_ECC_ERROR						78
-#define PLIC_INT_ECC_CORRECT					79
-#define PLIC_INT_RTC_WAKEUP						80
-#define PLIC_INT_RTC_MATCH						81
-#define PLIC_INT_TIMER1							82
-#define PLIC_INT_TIMER2							83
-#define PLIC_INT_ENVM							84
-#define PLIC_INT_QSPI							85
-#define PLIC_INT_USB_DMA						86
-#define PLIC_INT_USB_MC							87
-#define PLIC_INT_MMC_MAIN						88
-#define PLIC_INT_MMC_WAKEUP						89
-#define PLIC_INT_MMUART0						90
-#define PLIC_INT_MMUART1						91
-#define PLIC_INT_MMUART2						92
-#define PLIC_INT_MMUART3						93
-#define PLIC_INT_MMUART4						94
-#define PLIC_INT_G5C_DEVRST						95
-#define PLIC_INT_G5C_MESSAGE					96
-#define PLIC_INT_USOC_VC_INTERRUPT				97
-#define PLIC_INT_USOC_SMB_INTERRUPT				98
-#define PLIC_INT_E51_0_MAINTENACE				99
-#define PLIC_INT_WDOG0_MRVP						100
-#define PLIC_INT_WDOG1_MRVP						101
-#define PLIC_INT_WDOG2_MRVP						102
-#define PLIC_INT_WDOG3_MRVP						103
-#define PLIC_INT_WDOG4_MRVP						104
-#define PLIC_INT_WDOG0_TOUT						105
-#define PLIC_INT_WDOG1_TOUT						106
-#define PLIC_INT_WDOG2_TOUT						107
-#define PLIC_INT_WDOG3_TOUT						108
-#define PLIC_INT_WDOG4_TOUT						109
-#define PLIC_INT_G5C_MSS_SPI					110
-#define PLIC_INT_VOLT_TEMP_ALARM				111
-#define PLIC_INT_ATHENA_COMPLETE				112
-#define PLIC_INT_ATHENA_ALARM					113
-#define PLIC_INT_ATHENA_BUS_ERROR				114
-#define PLIC_INT_USOC_AXIC_US					115
-#define PLIC_INT_USOC_AXIC_DS					116
-#define PLIC_INT_SPARE							117
-#define PLIC_INT_FABRIC_F2H_0					118
-#define PLIC_INT_FABRIC_F2H_1					119
-#define PLIC_INT_FABRIC_F2H_2					120
-#define PLIC_INT_FABRIC_F2H_3					121
-#define PLIC_INT_FABRIC_F2H_4					122
-#define PLIC_INT_FABRIC_F2H_5					123
-#define PLIC_INT_FABRIC_F2H_6					124
-#define PLIC_INT_FABRIC_F2H_7					125
-#define PLIC_INT_FABRIC_F2H_8					126
-#define PLIC_INT_FABRIC_F2H_9					127
-#define PLIC_INT_FABRIC_F2H_10					128
-#define PLIC_INT_FABRIC_F2H_11					129
-#define PLIC_INT_FABRIC_F2H_12					130
-#define PLIC_INT_FABRIC_F2H_13					131
-#define PLIC_INT_FABRIC_F2H_14					132
-#define PLIC_INT_FABRIC_F2H_15					133
-#define PLIC_INT_FABRIC_F2H_16					134
-#define PLIC_INT_FABRIC_F2H_17					135
-#define PLIC_INT_FABRIC_F2H_18					136
-#define PLIC_INT_FABRIC_F2H_19					137
-#define PLIC_INT_FABRIC_F2H_20					138
-#define PLIC_INT_FABRIC_F2H_21					139
-#define PLIC_INT_FABRIC_F2H_22					140
-#define PLIC_INT_FABRIC_F2H_23					141
-#define PLIC_INT_FABRIC_F2H_24					142
-#define PLIC_INT_FABRIC_F2H_25					143
-#define PLIC_INT_FABRIC_F2H_26					144
-#define PLIC_INT_FABRIC_F2H_27					145
-#define PLIC_INT_FABRIC_F2H_28					146
-#define PLIC_INT_FABRIC_F2H_29					147
-#define PLIC_INT_FABRIC_F2H_30					148
-#define PLIC_INT_FABRIC_F2H_31					149
-#define PLIC_INT_FABRIC_F2H_32					150
-#define PLIC_INT_FABRIC_F2H_33					151
-#define PLIC_INT_FABRIC_F2H_34					152
-#define PLIC_INT_FABRIC_F2H_35					153
-#define PLIC_INT_FABRIC_F2H_36					154
-#define PLIC_INT_FABRIC_F2H_37					155
-#define PLIC_INT_FABRIC_F2H_38					156
-#define PLIC_INT_FABRIC_F2H_39					157
-#define PLIC_INT_FABRIC_F2H_40					158
-#define PLIC_INT_FABRIC_F2H_41					159
-#define PLIC_INT_FABRIC_F2H_42					160
-#define PLIC_INT_FABRIC_F2H_43					161
-#define PLIC_INT_FABRIC_F2H_44					162
-#define PLIC_INT_FABRIC_F2H_45					163
-#define PLIC_INT_FABRIC_F2H_46					164
-#define PLIC_INT_FABRIC_F2H_47					165
-#define PLIC_INT_FABRIC_F2H_48					166
-#define PLIC_INT_FABRIC_F2H_49					167
-#define PLIC_INT_FABRIC_F2H_50					168
-#define PLIC_INT_FABRIC_F2H_51					169
-#define PLIC_INT_FABRIC_F2H_52					170
-#define PLIC_INT_FABRIC_F2H_53					171
-#define PLIC_INT_FABRIC_F2H_54					172
-#define PLIC_INT_FABRIC_F2H_55					173
-#define PLIC_INT_FABRIC_F2H_56					174
-#define PLIC_INT_FABRIC_F2H_57					175
-#define PLIC_INT_FABRIC_F2H_58					176
-#define PLIC_INT_FABRIC_F2H_59					177
-#define PLIC_INT_FABRIC_F2H_60					178
-#define PLIC_INT_FABRIC_F2H_61					179
-#define PLIC_INT_FABRIC_F2H_62					180
-#define PLIC_INT_FABRIC_F2H_63					181
-#define PLIC_INT_BUS_ERROR_UNIT_HART_0			182
-#define PLIC_INT_BUS_ERROR_UNIT_HART_1			183
-#define PLIC_INT_BUS_ERROR_UNIT_HART_2			184
-#define PLIC_INT_BUS_ERROR_UNIT_HART_3			185
-#define PLIC_INT_BUS_ERROR_UNIT_HART_4			186
-
-#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */
diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h
deleted file mode 100644
index c4331b8521..0000000000
--- a/include/dt-bindings/interrupt-controller/riscv-hart.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/* Copyright (c) 2020-2021 Microchip Technology Inc */
-
-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
-
-#define HART_INT_U_SOFT   0
-#define HART_INT_S_SOFT   1
-#define HART_INT_M_SOFT   3
-#define HART_INT_U_TIMER  4
-#define HART_INT_S_TIMER  5
-#define HART_INT_M_TIMER  7
-#define HART_INT_U_EXT    8
-#define HART_INT_S_EXT    9
-#define HART_INT_M_EXT    11
-
-#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */
diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bindings/media/video-interfaces.h
new file mode 100644
index 0000000000..68ac4e05e3
--- /dev/null
+++ b/include/dt-bindings/media/video-interfaces.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2022 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ */
+
+#ifndef __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__
+#define __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__
+
+#define MEDIA_BUS_TYPE_CSI2_CPHY		1
+#define MEDIA_BUS_TYPE_CSI1			2
+#define MEDIA_BUS_TYPE_CCP2			3
+#define MEDIA_BUS_TYPE_CSI2_DPHY		4
+#define MEDIA_BUS_TYPE_PARALLEL			5
+#define MEDIA_BUS_TYPE_BT656			6
+
+#endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */
diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h
index 84795ec27a..d2478d9ae3 100644
--- a/include/dt-bindings/memory/bcm-ns3-mc.h
+++ b/include/dt-bindings/memory/bcm-ns3-mc.h
@@ -28,7 +28,7 @@
 #define BCM_NS3_MEM_SHARE_START    0x8d000000
 #define BCM_NS3_MEM_SHARE_LEN      0x020fffff
 
-/* ATF/U-boot/Linux error logs */
+/* ATF/U-Boot/Linux error logs */
 #define BCM_NS3_MEM_ELOG_START     0x8f113000
 #define BCM_NS3_MEM_ELOG_LEN       0x00100000
 
diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h
new file mode 100644
index 0000000000..8e39dfc0b6
--- /dev/null
+++ b/include/dt-bindings/power/meson-a1-power.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2023 SberDevices, Inc.
+ * Author: Alexey Romanov <avromanov@sberdevices.ru>
+ */
+
+#ifndef _DT_BINDINGS_MESON_A1_POWER_H
+#define _DT_BINDINGS_MESON_A1_POWER_H
+
+#define PWRC_DSPA_ID	8
+#define PWRC_DSPB_ID	9
+#define PWRC_UART_ID	10
+#define PWRC_DMC_ID	11
+#define PWRC_I2C_ID	12
+#define PWRC_PSRAM_ID	13
+#define PWRC_ACODEC_ID	14
+#define PWRC_AUDIO_ID	15
+#define PWRC_OTP_ID	16
+#define PWRC_DMA_ID	17
+#define PWRC_SD_EMMC_ID	18
+#define PWRC_RAMA_ID	19
+#define PWRC_RAMB_ID	20
+#define PWRC_IR_ID	21
+#define PWRC_SPICC_ID	22
+#define PWRC_SPIFC_ID	23
+#define PWRC_USB_ID	24
+#define PWRC_NIC_ID	25
+#define PWRC_PDMIN_ID	26
+#define PWRC_RSA_ID	27
+#define PWRC_MAX_ID	28
+
+#endif
diff --git a/include/dt-bindings/reset/mt7988-reset.h b/include/dt-bindings/reset/mt7988-reset.h
new file mode 100644
index 0000000000..d30011f941
--- /dev/null
+++ b/include/dt-bindings/reset/mt7988-reset.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MTK_RESET_H_
+#define _DT_BINDINGS_MTK_RESET_H_
+
+/* ETHDMA Subsystem resets */
+#define ETHDMA_FE_RST			6
+#define ETHDMA_PMTR_RST			8
+#define ETHDMA_GMAC_RST			23
+#define ETHDMA_WDMA0_RST		24
+#define ETHDMA_WDMA1_RST		25
+#define ETHDMA_WDMA2_RST		26
+#define ETHDMA_PPE0_RST			29
+#define ETHDMA_PPE1_RST			30
+#define ETHDMA_PPE2_RST			31
+
+/* ETHWARP Subsystem resets */
+#define ETHWARP_GSW_RST			9
+#define ETHWARP_EIP197_RST		10
+#define ETHWARP_WOCPU0_RST		32
+#define ETHWARP_WOCPU1_RST		33
+#define ETHWARP_WOCPU2_RST		34
+#define ETHWARP_WOX_NET_MUX_RST		35
+#define ETHWARP_WED0_RST		36
+#define ETHWARP_WED1_RST		37
+#define ETHWARP_WED2_RST		38
+
+#endif /* _DT_BINDINGS_MTK_RESET_H_ */
diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h
index 18ccb05db6..1b83a01de8 100644
--- a/include/dt-bindings/reset/stm32mp13-resets.h
+++ b/include/dt-bindings/reset/stm32mp13-resets.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
 /*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
  * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
  */
 
diff --git a/include/efi_api.h b/include/efi_api.h
index 55a4c989fc..8f5ef5f680 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -579,6 +579,13 @@ struct efi_device_path_vendor {
 	u8 vendor_data[];
 } __packed;
 
+struct efi_device_path_udevice {
+	struct efi_device_path dp;
+	efi_guid_t guid;
+	int uclass_id;
+	int dev_number;
+} __packed;
+
 struct efi_device_path_controller {
 	struct efi_device_path dp;
 	u32 controller_number;
diff --git a/include/efi_config.h b/include/efi_config.h
index 01ce9b2b06..d7c1601137 100644
--- a/include/efi_config.h
+++ b/include/efi_config.h
@@ -105,11 +105,6 @@ efi_status_t eficonfig_process_common(struct efimenu *efi_menu,
 				      void (*item_data_print)(void *),
 				      char *(*item_choice)(void *));
 efi_status_t eficonfig_process_select_file(void *data);
-efi_status_t eficonfig_get_unused_bootoption(u16 *buf,
-					     efi_uintn_t buf_size, u32 *index);
-efi_status_t eficonfig_append_bootorder(u16 index);
-efi_status_t eficonfig_generate_media_device_boot_option(void);
-
 efi_status_t eficonfig_append_menu_entry(struct efimenu *efi_menu,
 					 char *title, eficonfig_entry_func func,
 					 void *data);
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 38d7f66bab..4a29ddaef4 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -517,6 +517,17 @@ struct efi_register_notify_event {
 int efi_init_early(void);
 /* Initialize efi execution environment */
 efi_status_t efi_init_obj_list(void);
+/* Append new boot option in BootOrder variable */
+efi_status_t efi_bootmgr_append_bootorder(u16 index);
+/* Get unused "Boot####" index */
+efi_status_t efi_bootmgr_get_unused_bootoption(u16 *buf,
+					       efi_uintn_t buf_size, u32 *index);
+/* Generate the media device boot option */
+efi_status_t efi_bootmgr_update_media_device_boot_option(void);
+/* Delete selected boot option */
+efi_status_t efi_bootmgr_delete_boot_option(u16 boot_index);
+/* search the boot option index in BootOrder */
+bool efi_search_bootorder(u16 *bootorder, efi_uintn_t num, u32 target, u32 *index);
 /* Set up console modes */
 void efi_setup_console_size(void);
 /* Install device tree */
@@ -618,7 +629,7 @@ void efi_add_handle(efi_handle_t obj);
 /* Create handle */
 efi_status_t efi_create_handle(efi_handle_t *handle);
 /* Delete handle */
-void efi_delete_handle(efi_handle_t obj);
+efi_status_t efi_delete_handle(efi_handle_t obj);
 /* Call this to validate a handle and find the EFI object for it */
 struct efi_object *efi_search_obj(const efi_handle_t handle);
 /* Locate device_path handle */
@@ -651,10 +662,6 @@ efi_status_t efi_protocol_open(struct efi_handler *handler,
 			       void **protocol_interface, void *agent_handle,
 			       void *controller_handle, uint32_t attributes);
 
-/* Delete protocol from a handle */
-efi_status_t efi_remove_protocol(const efi_handle_t handle,
-				 const efi_guid_t *protocol,
-				 void *protocol_interface);
 /* Install multiple protocol interfaces */
 efi_status_t EFIAPI
 efi_install_multiple_protocol_interfaces(efi_handle_t *handle, ...);
@@ -689,9 +696,21 @@ void efi_signal_event(struct efi_event *event);
 /* return true if the device is removable */
 bool efi_disk_is_removable(efi_handle_t handle);
 
-/* open file system: */
-struct efi_simple_file_system_protocol *efi_simple_file_system(
-		struct blk_desc *desc, int part, struct efi_device_path *dp);
+/**
+ * efi_create_simple_file_system() - create simple file system protocol
+ *
+ * Create a simple file system protocol for a partition.
+ *
+ * @desc:	block device descriptor
+ * @part:	partition number
+ * @dp:		device path
+ * @fsp:	simple file system protocol
+ * Return:	status code
+ */
+efi_status_t
+efi_create_simple_file_system(struct blk_desc *desc, int part,
+			      struct efi_device_path *dp,
+			      struct efi_simple_file_system_protocol **fsp);
 
 /* open file from device-path: */
 struct efi_file_handle *efi_file_from_path(struct efi_device_path *fp);
@@ -1078,15 +1097,16 @@ struct efi_fw_image {
  * platforms which enable capsule updates
  *
  * @dfu_string:		String used to populate dfu_alt_info
+ * @num_images:		The number of images array entries
  * @images:		Pointer to an array of updatable images
  */
 struct efi_capsule_update_info {
 	const char *dfu_string;
+	int num_images;
 	struct efi_fw_image *images;
 };
 
 extern struct efi_capsule_update_info update_info;
-extern u8 num_image_type_guids;
 
 /**
  * Install the ESRT system table.
diff --git a/include/environment/distro/sf.h b/include/env/distro/sf.h
index ee48a8a4e8..ee48a8a4e8 100644
--- a/include/environment/distro/sf.h
+++ b/include/env/distro/sf.h
diff --git a/include/environment/pg-wcom/common.env b/include/env/pg-wcom/common.env
index 4b660cebd6..4b660cebd6 100644
--- a/include/environment/pg-wcom/common.env
+++ b/include/env/pg-wcom/common.env
diff --git a/include/environment/pg-wcom/ls102xa.env b/include/env/pg-wcom/ls102xa.env
index 5b5bda95e2..abbec42457 100644
--- a/include/environment/pg-wcom/ls102xa.env
+++ b/include/env/pg-wcom/ls102xa.env
@@ -1,6 +1,6 @@
 #define WCOM_UBI_PARTITION_APP
 
-#include <environment/pg-wcom/common.env>
+#include <env/pg-wcom/common.env>
 
 EEprom_ivm=pca9547:70:9
 boot=bootm $load_addr_r - $fdt_addr_r
diff --git a/include/environment/pg-wcom/powerpc.env b/include/env/pg-wcom/powerpc.env
index 744c07388c..744c07388c 100644
--- a/include/environment/pg-wcom/powerpc.env
+++ b/include/env/pg-wcom/powerpc.env
diff --git a/include/environment/ti/dfu.h b/include/env/ti/dfu.h
index 3c90570107..3c90570107 100644
--- a/include/environment/ti/dfu.h
+++ b/include/env/ti/dfu.h
diff --git a/include/environment/ti/k3_dfu.env b/include/env/ti/k3_dfu.env
index 201529636c..201529636c 100644
--- a/include/environment/ti/k3_dfu.env
+++ b/include/env/ti/k3_dfu.env
diff --git a/include/environment/ti/k3_dfu.h b/include/env/ti/k3_dfu.h
index a16a3adeca..a16a3adeca 100644
--- a/include/environment/ti/k3_dfu.h
+++ b/include/env/ti/k3_dfu.h
diff --git a/include/environment/ti/k3_rproc.env b/include/env/ti/k3_rproc.env
index 87d9d76eba..87d9d76eba 100644
--- a/include/environment/ti/k3_rproc.env
+++ b/include/env/ti/k3_rproc.env
diff --git a/include/environment/ti/k3_rproc.h b/include/env/ti/k3_rproc.h
index 3418cb42be..3418cb42be 100644
--- a/include/environment/ti/k3_rproc.h
+++ b/include/env/ti/k3_rproc.h
diff --git a/include/environment/ti/mmc.env b/include/env/ti/mmc.env
index 5677d057d8..6fb47fb266 100644
--- a/include/environment/ti/mmc.env
+++ b/include/env/ti/mmc.env
@@ -13,7 +13,8 @@ importbootenv=echo Importing environment from mmc${mmcdev} ...;
 	env import -t ${loadaddr} ${filesize}
 loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
 loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}
-loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}
+loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/dtb/${fdtfile}
+get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/dtb/${name_fdt}
 envboot=mmc dev ${mmcdev};
 	if mmc rescan; then
 		echo SD/MMC found on device ${mmcdev};
@@ -32,7 +33,7 @@ envboot=mmc dev ${mmcdev};
 	fi;
 mmcloados=
 	if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
-		if run loadfdt; then
+		if run get_fdt_mmc; then
 			bootz ${loadaddr} - ${fdtaddr};
 		else
 			if test ${boot_fdt} = try; then
@@ -59,3 +60,17 @@ mmcboot=mmc dev ${mmcdev};
 		fi;
 fi;
 
+init_mmc=run args_all args_mmc
+get_overlay_mmc=
+	fdt address ${fdtaddr};
+	fdt resize 0x100000;
+	for overlay in $name_overlays;
+	do;
+	load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay} &&
+	fdt apply ${dtboaddr};
+	done;
+get_kern_mmc=load mmc ${bootpart} ${loadaddr}
+	${bootdir}/${name_kern}
+get_fit_mmc=load mmc ${bootpart} ${addr_fit}
+	${bootdir}/${name_fit}
+partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
diff --git a/include/environment/ti/mmc.h b/include/env/ti/mmc.h
index 769ea9d5ef..769ea9d5ef 100644
--- a/include/environment/ti/mmc.h
+++ b/include/env/ti/mmc.h
diff --git a/include/environment/ti/nand.env b/include/env/ti/nand.env
index 4e185c1b5f..4e185c1b5f 100644
--- a/include/environment/ti/nand.env
+++ b/include/env/ti/nand.env
diff --git a/include/environment/ti/nand.h b/include/env/ti/nand.h
index 7d00afa2b1..7d00afa2b1 100644
--- a/include/environment/ti/nand.h
+++ b/include/env/ti/nand.h
diff --git a/include/environment/ti/ti_armv7_common.env b/include/env/ti/ti_armv7_common.env
index 0c0929d862..e87a41a659 100644
--- a/include/environment/ti/ti_armv7_common.env
+++ b/include/env/ti/ti_armv7_common.env
@@ -22,4 +22,13 @@ get_overlaystring=
 	done;
 get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile}
 run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring}
-
+bootcmd_ti_mmc=
+	run findfdt; run init_${boot};
+#if CONFIG_CMD_REMOTEPROC
+	run main_cpsw0_qsgmii_phyinit; run boot_rprocs;
+#endif
+	if test ${boot_fit} -eq 1;
+		then run get_fit_${boot}; run get_overlaystring; run run_fit;
+	else;
+		run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern;
+	fi;
diff --git a/include/env/ti/ti_armv7_keystone2.env b/include/env/ti/ti_armv7_keystone2.env
new file mode 100644
index 0000000000..e0395d302c
--- /dev/null
+++ b/include/env/ti/ti_armv7_keystone2.env
@@ -0,0 +1,61 @@
+name_fw_rd=k2-fw-initrd.cpio.gz
+set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}
+init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; run set_rd_spec
+init_fw_rd_nfs=nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; run set_rd_spec
+init_fw_rd_ramfs=setenv rd_spec -
+init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; run set_rd_spec
+
+dfu_bufsiz=0x10000
+dfu_alt_info_mmc=
+	MLO fat 0 1;
+	u-boot.img fat 0 1;
+	uEnv.txt fat 0 1
+
+bootdir=/boot
+tftp_root=/
+nfs_root=/export
+mem_lpae=1
+uinitrd_fixup=1
+addr_ubi=0x82000000
+addr_secdb_key=0xc000000
+name_kern=zImage
+addr_mon=0x87000000
+addr_non_sec_mon=0x0c097fc0
+addr_load_sec_bm=0x0c09c000
+run_mon=mon_install ${addr_mon}
+run_mon_hs=mon_install ${addr_non_sec_mon} ${addr_load_sec_bm}
+run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}
+init_net=run args_all args_net
+init_nfs=setenv autoload no; dhcp; run args_all args_net
+init_ubi=run args_all args_ubi; ubi part ubifs; ubifsmount ubi:rootfs;
+get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}
+get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}
+get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}
+get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}
+get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern}
+get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}
+get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}
+get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}
+get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}
+get_fit_net=dhcp ${addr_fit} ${tftp_root}/${name_fit}
+get_fit_nfs=nfs ${addr_fit} ${nfs_root}/boot/${name_fit}
+get_fit_ubi=ubifsload ${addr_fit} ${bootdir}/${name_fit}
+get_fit_mmc=load mmc ${bootpart} ${addr_fit} ${bootdir}/${name_fit}
+get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}
+get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}
+burn_uboot_spi=sf probe; sf erase 0 0x100000; sf write ${loadaddr} 0 ${filesize}
+burn_uboot_nand=nand erase 0 0x100000; nand write ${loadaddr} 0 ${filesize}
+args_all=setenv bootargs console=ttyS0,115200n8 rootwait
+args_net=setenv bootargs ${bootargs} rootfstype=nfs root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},${nfs_options} ip=dhcp
+nfs_options=v3,tcp,rsize=4096,wsize=4096
+get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}
+get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}
+get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}
+get_fit_ramfs=dhcp ${addr_fit} ${tftp_root}/${name_fit}
+get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}
+get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}
+get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}
+burn_ubi=nand erase.part ubifs; nand write ${addr_ubi} ubifs ${filesize}
+init_ramfs=run args_all args_ramfs get_fs_ramfs
+args_ramfs=setenv bootargs ${bootargs} rdinit=/sbin/init rw root=/dev/ram0 initrd=0x808080000,80M
+no_post=1
diff --git a/include/environment/ti/ufs.env b/include/env/ti/ufs.env
index 509a87b89e..509a87b89e 100644
--- a/include/environment/ti/ufs.env
+++ b/include/env/ti/ufs.env
diff --git a/include/environment/ti/ufs.h b/include/env/ti/ufs.h
index 6619ec9c88..6619ec9c88 100644
--- a/include/environment/ti/ufs.h
+++ b/include/env/ti/ufs.h
diff --git a/include/env/x86.env b/include/env/x86.env
new file mode 100644
index 0000000000..d00d98f70a
--- /dev/null
+++ b/include/env/x86.env
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com
+ */
+
+pciconfighost=1
+netdev=eth0
+consoledev=ttyS0
+scriptaddr=0x7000000
+kernel_addr_r=0x1000000
+ramdisk_addr_r=0x4000000
+ramdiskfile=initramfs.gz
+
+/* common console settings */
+stdin=serial,i8042-kbd,usbkbd
+stdout=serial,vidconsole
+stderr=serial,vidconsole
diff --git a/include/env_callback.h b/include/env_callback.h
index a9a14f2a84..23bc650c16 100644
--- a/include/env_callback.h
+++ b/include/env_callback.h
@@ -60,8 +60,10 @@
 #define NET6_CALLBACKS
 #endif
 
-#ifdef CONFIG_BOOTSTD
-#define BOOTSTD_CALLBACK	"bootmeths:bootmeths,"
+#ifdef CONFIG_BOOTSTD_FULL
+#define BOOTSTD_CALLBACK \
+	"bootmeths:bootmeths," \
+	"bootargs:bootargs,"
 #else
 #define BOOTSTD_CALLBACK
 #endif
diff --git a/include/environment/ti/spi.h b/include/environment/ti/spi.h
deleted file mode 100644
index 1681dc8635..0000000000
--- a/include/environment/ti/spi.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com
- *
- * Environment variable definitions for SPI on TI boards.
- */
-
-#ifndef __TI_SPI_H
-#define __TI_SPI_H
-
-#define KEYSTONE_SPI0_MTD_PARTS "spi0.0:1m(u-boot-spl)ro,-(misc);\0"
-#define KEYSTONE_SPI1_MTD_PARTS "spi1.0:1m(u-boot-spl)ro,-(misc);\0"
-
-#endif
diff --git a/include/event.h b/include/event.h
index fe41080fa6..daf44bf8a8 100644
--- a/include/event.h
+++ b/include/event.h
@@ -11,6 +11,7 @@
 #define __event_h
 
 #include <dm/ofnode_decl.h>
+#include <linux/types.h>
 
 /**
  * enum event_t - Types of events supported by U-Boot
@@ -31,6 +32,9 @@ enum event_t {
 	/* Init hooks */
 	EVT_MISC_INIT_F,
 
+	/* Fpga load hook */
+	EVT_FPGA_LOAD,
+
 	/* Device tree fixups before booting */
 	EVT_FT_FIXUP,
 
@@ -60,6 +64,19 @@ union event_data {
 	} dm;
 
 	/**
+	 * struct event_fpga_load - fpga load event
+	 *
+	 * @buf: The buffer that was loaded into the fpga
+	 * @bsize: The size of the buffer that was loaded into the fpga
+	 * @result: Result of the load operation
+	 */
+	struct event_fpga_load {
+		const void *buf;
+		size_t bsize;
+		int result;
+	} fpga_load;
+
+	/**
 	 * struct event_ft_fixup - FDT fixup before booting
 	 *
 	 * @tree: tree to update
diff --git a/include/expo.h b/include/expo.h
index d242f48e30..0b1d944a16 100644
--- a/include/expo.h
+++ b/include/expo.h
@@ -7,22 +7,31 @@
 #ifndef __SCENE_H
 #define __SCENE_H
 
+#include <dm/ofnode_decl.h>
 #include <linux/list.h>
 
 struct udevice;
+struct video_priv;
 
 /**
  * enum expoact_type - types of actions reported by the expo
  *
  * @EXPOACT_NONE: no action
- * @EXPOACT_POINT: menu item was highlighted (@id indicates which)
+ * @EXPOACT_POINT_OBJ: object was highlighted (@id indicates which)
+ * @EXPOACT_POINT_ITEM: menu item was highlighted (@id indicates which)
  * @EXPOACT_SELECT: menu item was selected (@id indicates which)
+ * @EXPOACT_OPEN: menu was opened, so an item can be selected (@id indicates
+ * which menu object)
+ * @EXPOACT_CLOSE: menu was closed (@id indicates which menu object)
  * @EXPOACT_QUIT: request to exit the menu
  */
 enum expoact_type {
 	EXPOACT_NONE,
-	EXPOACT_POINT,
+	EXPOACT_POINT_OBJ,
+	EXPOACT_POINT_ITEM,
 	EXPOACT_SELECT,
+	EXPOACT_OPEN,
+	EXPOACT_CLOSE,
 	EXPOACT_QUIT,
 };
 
@@ -30,7 +39,7 @@ enum expoact_type {
  * struct expo_action - an action report by the expo
  *
  * @type: Action type (EXPOACT_NONE if there is no action)
- * @select: Used for EXPOACT_POINT and EXPOACT_SELECT
+ * @select: Used for EXPOACT_POINT_ITEM and EXPOACT_SELECT
  * @id: ID number of the object affected.
  */
 struct expo_action {
@@ -43,6 +52,19 @@ struct expo_action {
 };
 
 /**
+ * struct expo_theme - theme for the expo
+ *
+ * @font_size: Default font size for all text
+ * @menu_inset: Inset width (on each side and top/bottom) for menu items
+ * @menuitem_gap_y: Gap between menu items in pixels
+ */
+struct expo_theme {
+	u32 font_size;
+	u32 menu_inset;
+	u32 menuitem_gap_y;
+};
+
+/**
  * struct expo - information about an expo
  *
  * A group of scenes which can be presented to the user, typically to obtain
@@ -50,23 +72,29 @@ struct expo_action {
  *
  * @name: Name of the expo (allocated)
  * @display: Display to use (`UCLASS_VIDEO`), or NULL to use text mode
+ * @cons: Console to use (`UCLASS_VIDEO_CONSOLE`), or NULL to use text mode
  * @scene_id: Current scene ID (0 if none)
  * @next_id: Next ID number to use, for automatic allocation
  * @action: Action selected by user. At present only one is supported, with the
  * type set to EXPOACT_NONE if there is no action
  * @text_mode: true to use text mode for the menu (no vidconsole)
+ * @popup: true to use popup menus, instead of showing all items
  * @priv: Private data for the controller
+ * @theme: Information about fonts styles, etc.
  * @scene_head: List of scenes
  * @str_head: list of strings
  */
 struct expo {
 	char *name;
 	struct udevice *display;
+	struct udevice *cons;
 	uint scene_id;
 	uint next_id;
 	struct expo_action action;
 	bool text_mode;
+	bool popup;
 	void *priv;
+	struct expo_theme theme;
 	struct list_head scene_head;
 	struct list_head str_head;
 };
@@ -92,7 +120,8 @@ struct expo_string {
  * @expo: Expo this scene is part of
  * @name: Name of the scene (allocated)
  * @id: ID number of the scene
- * @title: Title of the scene (allocated)
+ * @title_id: String ID of title of the scene (allocated)
+ * @highlight_id: ID of highlighted object, if any
  * @sibling: Node to link this scene to its siblings
  * @obj_head: List of objects in the scene
  */
@@ -100,7 +129,8 @@ struct scene {
 	struct expo *expo;
 	char *name;
 	uint id;
-	char *title;
+	uint title_id;
+	uint highlight_id;
 	struct list_head sibling;
 	struct list_head obj_head;
 };
@@ -121,15 +151,43 @@ enum scene_obj_t {
 };
 
 /**
+ * struct scene_dim - Dimensions of an object
+ *
+ * @x: x position, in pixels from left side
+ * @y: y position, in pixels from top
+ * @w: width, in pixels
+ * @h: height, in pixels
+ */
+struct scene_dim {
+	int x;
+	int y;
+	int w;
+	int h;
+};
+
+/**
+ * enum scene_obj_flags_t - flags for objects
+ *
+ * @SCENEOF_HIDE: object should be hidden
+ * @SCENEOF_POINT: object should be highlighted
+ * @SCENEOF_OPEN: object should be opened (e.g. menu is opened so that an option
+ * can be selected)
+ */
+enum scene_obj_flags_t {
+	SCENEOF_HIDE	= 1 << 0,
+	SCENEOF_POINT	= 1 << 1,
+	SCENEOF_OPEN	= 1 << 2,
+};
+
+/**
  * struct scene_obj - information about an object in a scene
  *
  * @scene: Scene that this object relates to
  * @name: Name of the object (allocated)
  * @id: ID number of the object
  * @type: Type of this object
- * @x: x position, in pixels from left side
- * @y: y position, in pixels from top
- * @hide: true if the object should be hidden
+ * @dim: Dimensions for this object
+ * @flags: Flags for this object
  * @sibling: Node to link this object to its siblings
  */
 struct scene_obj {
@@ -137,9 +195,8 @@ struct scene_obj {
 	char *name;
 	uint id;
 	enum scene_obj_t type;
-	int x;
-	int y;
-	bool hide;
+	struct scene_dim dim;
+	int flags;
 	struct list_head sibling;
 };
 
@@ -256,6 +313,25 @@ int expo_new(const char *name, void *priv, struct expo **expp);
 void expo_destroy(struct expo *exp);
 
 /**
+ * expo_set_dynamic_start() - Set the start of the 'dynamic' IDs
+ *
+ * It is common for a set of 'static' IDs to be used to refer to objects in the
+ * expo. These typically use an enum so that they are defined in sequential
+ * order.
+ *
+ * Dynamic IDs (for objects not in the enum) are intended to be used for
+ * objects to which the code does not need to refer. These are ideally located
+ * above the static IDs.
+ *
+ * Use this function to set the start of the dynamic range, making sure that the
+ * value is higher than all the statically allocated IDs.
+ *
+ * @exp: Expo to update
+ * @dyn_start: Start ID that expo should use for dynamic allocation
+ */
+void expo_set_dynamic_start(struct expo *exp, uint dyn_start);
+
+/**
  * expo_str() - add a new string to an expo
  *
  * @exp: Expo to update
@@ -285,6 +361,16 @@ const char *expo_get_str(struct expo *exp, uint id);
 int expo_set_display(struct expo *exp, struct udevice *dev);
 
 /**
+ * expo_calc_dims() - Calculate the dimensions of the objects
+ *
+ * Updates the width and height of all objects based on their contents
+ *
+ * @exp: Expo to update
+ * Returns 0 if OK, -ENOTSUPP if there is no graphical console
+ */
+int expo_calc_dims(struct expo *exp);
+
+/**
  * expo_set_scene_id() - Set the current scene ID
  *
  * @exp: Expo to update
@@ -294,6 +380,14 @@ int expo_set_display(struct expo *exp, struct udevice *dev);
 int expo_set_scene_id(struct expo *exp, uint scene_id);
 
 /**
+ * expo_first_scene_id() - Get the ID of the first scene
+ *
+ * @exp: Expo to check
+ * Returns: Scene ID of first scene, or -ENOENT if there are no scenes
+ */
+int expo_first_scene_id(struct expo *exp);
+
+/**
  * expo_render() - render the expo on the display / console
  *
  * @exp: Expo to render
@@ -304,12 +398,12 @@ int expo_set_scene_id(struct expo *exp, uint scene_id);
 int expo_render(struct expo *exp);
 
 /**
- * exp_set_text_mode() - Controls whether the expo renders in text mode
+ * expo_set_text_mode() - Controls whether the expo renders in text mode
  *
  * @exp: Expo to update
  * @text_mode: true to use text mode, false to use the console
  */
-void exp_set_text_mode(struct expo *exp, bool text_mode);
+void expo_set_text_mode(struct expo *exp, bool text_mode);
 
 /**
  * scene_new() - create a new scene in a expo
@@ -335,13 +429,43 @@ int scene_new(struct expo *exp, const char *name, uint id, struct scene **scnp);
 struct scene *expo_lookup_scene_id(struct expo *exp, uint scene_id);
 
 /**
+ * scene_highlight_first() - Highlight the first item in a scene
+ *
+ * This highlights the first item, so that the user can see that it is pointed
+ * to
+ *
+ * @scn: Scene to update
+ */
+void scene_highlight_first(struct scene *scn);
+
+/**
+ * scene_set_highlight_id() - Set the object which is highlighted
+ *
+ * Sets a new object to highlight in the scene
+ *
+ * @scn: Scene to update
+ * @id: ID of object to highlight
+ */
+void scene_set_highlight_id(struct scene *scn, uint id);
+
+/**
+ * scene_set_open() - Set whether an item is open or not
+ *
+ * @scn: Scene to update
+ * @id: ID of object to update
+ * @open: true to open the object, false to close it
+ * Returns: 0 if OK, -ENOENT if @id is invalid
+ */
+int scene_set_open(struct scene *scn, uint id, bool open);
+
+/**
  * scene_title_set() - set the scene title
  *
  * @scn: Scene to update
- * @title: Title to set, NULL if none (this is allocated by this call)
- * Returns: 0 if OK, -ENOMEM if out of memory
+ * @title_id: Title ID to set
+ * Returns: 0 if OK
  */
-int scene_title_set(struct scene *scn, const char *title);
+int scene_title_set(struct scene *scn, uint title_id);
 
 /**
  * scene_obj_count() - Count the number of objects in a scene
@@ -426,6 +550,17 @@ int scene_txt_set_font(struct scene *scn, uint id, const char *font_name,
 int scene_obj_set_pos(struct scene *scn, uint id, int x, int y);
 
 /**
+ * scene_obj_set_size() - Set the size of an object
+ *
+ * @scn: Scene to update
+ * @id: ID of object to update
+ * @w: width in pixels
+ * @h: height in pixels
+ * Returns: 0 if OK, -ENOENT if @id is invalid
+ */
+int scene_obj_set_size(struct scene *scn, uint id, int w, int h);
+
+/**
  * scene_obj_set_hide() - Set whether an object is hidden
  *
  * The update happens when the expo is next rendered.
@@ -519,4 +654,46 @@ int expo_send_key(struct expo *exp, int key);
  */
 int expo_action_get(struct expo *exp, struct expo_action *act);
 
+/**
+ * expo_apply_theme() - Apply a theme to an expo
+ *
+ * @exp: Expo to update
+ * @node: Node containing the theme
+ */
+int expo_apply_theme(struct expo *exp, ofnode node);
+
+/**
+ * expo_build() - Build an expo from an FDT description
+ *
+ * Build a complete expo from a description in the provided devicetree.
+ *
+ * See doc/developer/expo.rst for a description of the format
+ *
+ * @root: Root node for expo description
+ * @expp: Returns the new expo
+ * Returns: 0 if OK, -ENOMEM if out of memory, -EINVAL if there is a format
+ * error, -ENOENT if there is a references to a non-existent string
+ */
+int expo_build(ofnode root, struct expo **expp);
+
+/**
+ * cedit_arange() - Arrange objects in a configuration-editor scene
+ *
+ * @exp: Expo to update
+ * @vid_priv: Private info of the video device
+ * @scene_id: scene ID to arrange
+ * Returns: 0 if OK, -ve on error
+ */
+int cedit_arange(struct expo *exp, struct video_priv *vid_priv, uint scene_id);
+
+/**
+ * cedit_run() - Run a configuration editor
+ *
+ * This accepts input until the user quits with Escape
+ *
+ * @exp: Expo to use
+ * Returns: 0 if OK, -ve on error
+ */
+int cedit_run(struct expo *exp);
+
 #endif /*__SCENE_H */
diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h
deleted file mode 100644
index 484bd36334..0000000000
--- a/include/exynos_lcd.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * exynos_lcd.h - Exynos LCD Controller structures
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#ifndef _EXYNOS_LCD_H_
-#define _EXYNOS_LCD_H_
-
-enum {
-	FIMD_RGB_INTERFACE = 1,
-	FIMD_CPU_INTERFACE = 2,
-};
-
-enum exynos_fb_rgb_mode_t {
-	MODE_RGB_P = 0,
-	MODE_BGR_P = 1,
-	MODE_RGB_S = 2,
-	MODE_BGR_S = 3,
-};
-
-typedef struct vidinfo {
-	ushort vl_col;		/* Number of columns (i.e. 640) */
-	ushort vl_row;		/* Number of rows (i.e. 480) */
-	ushort vl_rot;		/* Rotation of Display (0, 1, 2, 3) */
-	ushort vl_width;	/* Width of display area in millimeters */
-	ushort vl_height;	/* Height of display area in millimeters */
-
-	/* LCD configuration register */
-	u_char vl_freq;		/* Frequency */
-	u_char vl_clkp;		/* Clock polarity */
-	u_char vl_oep;		/* Output Enable polarity */
-	u_char vl_hsp;		/* Horizontal Sync polarity */
-	u_char vl_vsp;		/* Vertical Sync polarity */
-	u_char vl_dp;		/* Data polarity */
-	u_char vl_bpix;		/* Bits per pixel */
-
-	/* Horizontal control register. Timing from data sheet */
-	u_char vl_hspw;		/* Horz sync pulse width */
-	u_char vl_hfpd;		/* Wait before of line */
-	u_char vl_hbpd;		/* Wait end of line */
-
-	/* Vertical control register. */
-	u_char	vl_vspw;	/* Vertical sync pulse width */
-	u_char	vl_vfpd;	/* Wait before of frame */
-	u_char	vl_vbpd;	/* Wait end of frame */
-	u_char  vl_cmd_allow_len; /* Wait end of frame */
-
-	unsigned int win_id;
-	unsigned int init_delay;
-	unsigned int power_on_delay;
-	unsigned int reset_delay;
-	unsigned int interface_mode;
-	unsigned int mipi_enabled;
-	unsigned int dp_enabled;
-	unsigned int cs_setup;
-	unsigned int wr_setup;
-	unsigned int wr_act;
-	unsigned int wr_hold;
-	unsigned int logo_on;
-	unsigned int logo_width;
-	unsigned int logo_height;
-	int logo_x_offset;
-	int logo_y_offset;
-	unsigned long logo_addr;
-	unsigned int rgb_mode;
-	unsigned int resolution;
-
-	/* parent clock name(MPLL, EPLL or VPLL) */
-	unsigned int pclk_name;
-	/* ratio value for source clock from parent clock. */
-	unsigned int sclk_div;
-
-	unsigned int dual_lcd_enabled;
-	struct exynos_fb *reg;
-	struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
-} vidinfo_t;
-
-#endif
diff --git a/include/faraday/ftahbc020s.h b/include/faraday/ftahbc020s.h
deleted file mode 100644
index e628156c15..0000000000
--- a/include/faraday/ftahbc020s.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
-#ifndef __FTAHBC020S_H
-#define __FTAHBC202S_H
-
-/* Registers Offsets */
-
-/*
- * AHB Slave BSR, offset: n * 4, n=0~31
- */
-#ifndef __ASSEMBLY__
-struct ftahbc02s {
-	unsigned int	s_bsr[32];	/* 0x00-0x7c - Slave n Base/Size Reg */
-	unsigned int	pcr;		/* 0x80	- Priority Ctrl Reg */
-	unsigned int	tcrg;		/* 0x84	- Transfer Ctrl Reg */
-	unsigned int	cr;		/* 0x88	- Ctrl Reg */
-};
-#endif /* __ASSEMBLY__ */
-
-/*
- * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
- */
-#define FTAHBC020S_SLAVE_BSR_BASE(x)	(((x) & 0xfff) << 20)
-#define FTAHBC020S_SLAVE_BSR_SIZE(x)	(((x) & 0xf) << 16)
-/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */
-#define FTAHBC020S_BSR_SIZE(x)		(ffs(x) - 1)	/* size of Addr Space */
-
-/*
- * FTAHBC020S_PCR - Priority Control Register
- */
-#define FTAHBC020S_PCR_PLEVEL_(x)	(1 << (x))	/* x: 1-15 */
-
-/*
- * FTAHBC020S_CR - Interrupt Control Register
- */
-#define FTAHBC020S_CR_INTSTS	(1 << 24)
-#define FTAHBC020S_CR_RESP(x)	(((x) & 0x3) << 20)
-#define FTAHBC020S_CR_INTSMASK	(1 << 16)
-#define FTAHBC020S_CR_REMAP	(1 << 0)
-
-#endif	/* __FTAHBC020S_H */
diff --git a/include/faraday/ftpci100.h b/include/faraday/ftpci100.h
deleted file mode 100644
index 8801bd1350..0000000000
--- a/include/faraday/ftpci100.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
- *
- * Copyright (C) 2010 Andes Technology Corporation
- * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#ifndef __FTPCI100_H
-#define __FTPCI100_H
-
-/* AHB Control Registers */
-#include <linux/bitops.h>
-struct ftpci100_ahbc {
-	unsigned int iosize;		/* 0x00 - I/O Space Size Signal */
-	unsigned int prot;		/* 0x04 - AHB Protection */
-	unsigned int rsved[8];		/* 0x08-0x24 - Reserved */
-	unsigned int conf;		/* 0x28 - PCI Configuration */
-	unsigned int data;		/* 0x2c - PCI Configuration DATA */
-};
-
-/*
- * FTPCI100_IOSIZE_REG's constant definitions
- */
-#define FTPCI100_BASE_IO_SIZE(x)	(ffs(x) - 1)	/* 1M - 2048M */
-
-/*
- * PCI Configuration Register
- */
-#define PCI_INT_MASK			0x4c
-#define PCI_MEM_BASE_SIZE1		0x50
-#define PCI_MEM_BASE_SIZE2		0x54
-#define PCI_MEM_BASE_SIZE3		0x58
-
-/*
- * PCI_INT_MASK's bit definitions
- */
-#define PCI_INTA_ENABLE			(1 << 22)
-#define PCI_INTB_ENABLE			(1 << 23)
-#define PCI_INTC_ENABLE			(1 << 24)
-#define PCI_INTD_ENABLE			(1 << 25)
-
-/*
- * PCI_MEM_BASE_SIZE1's constant definitions
- */
-#define FTPCI100_BASE_ADR_SIZE(x)	((ffs(x) - 1) << 16)	/* 1M - 2048M */
-
-#define FTPCI100_MAX_FUNCTIONS		20
-#define PCI_IRQ_LINES			4
-
-#define MAX_BUS_NUM			256
-#define MAX_DEV_NUM			32
-#define MAX_FUN_NUM			8
-
-#define PCI_MAX_BAR_PER_FUNC		6
-
-/*
- * PCI_MEM_SIZE
- */
-#define FTPCI100_MEM_SIZE(x)		(ffs(x) << 24)
-
-/* This definition is used by pci_ftpci_init() */
-#define FTPCI100_BRIDGE_VENDORID		0x159b
-#define FTPCI100_BRIDGE_DEVICEID		0x4321
-
-void pci_ftpci_init(void);
-
-struct pcibar {
-	unsigned int size;
-	unsigned int addr;
-};
-
-struct pci_config {
-	unsigned int bus;
-	unsigned int dev;				/* device */
-	unsigned int func;
-	unsigned int pin;
-	unsigned short v_id;				/* vendor id */
-	unsigned short d_id;				/* device id */
-	struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1];
-};
-
-#endif
diff --git a/include/faraday/ftsdmc020.h b/include/faraday/ftsdmc020.h
deleted file mode 100644
index d74da16ef2..0000000000
--- a/include/faraday/ftsdmc020.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- */
-
-/*
- * SDRAM Controller
- */
-#ifndef __FTSDMC020_H
-#define __FTSDMC020_H
-
-#define FTSDMC020_OFFSET_TP0		0x00
-#define FTSDMC020_OFFSET_TP1		0x04
-#define FTSDMC020_OFFSET_CR		0x08
-#define FTSDMC020_OFFSET_BANK0_BSR	0x0C
-#define FTSDMC020_OFFSET_BANK1_BSR	0x10
-#define FTSDMC020_OFFSET_BANK2_BSR	0x14
-#define FTSDMC020_OFFSET_BANK3_BSR	0x18
-#define FTSDMC020_OFFSET_BANK4_BSR	0x1C
-#define FTSDMC020_OFFSET_BANK5_BSR	0x20
-#define FTSDMC020_OFFSET_BANK6_BSR	0x24
-#define FTSDMC020_OFFSET_BANK7_BSR	0x28
-#define FTSDMC020_OFFSET_ACR		0x34
-
-/*
- * Timing Parametet 0 Register
- */
-#define FTSDMC020_TP0_TCL(x)	((x) & 0x3)
-#define FTSDMC020_TP0_TWR(x)	(((x) & 0x3) << 4)
-#define FTSDMC020_TP0_TRF(x)	(((x) & 0xf) << 8)
-#define FTSDMC020_TP0_TRCD(x)	(((x) & 0x7) << 12)
-#define FTSDMC020_TP0_TRP(x)	(((x) & 0xf) << 16)
-#define FTSDMC020_TP0_TRAS(x)	(((x) & 0xf) << 20)
-
-/*
- * Timing Parametet 1 Register
- */
-#define FTSDMC020_TP1_REF_INTV(x)	((x) & 0xffff)
-#define FTSDMC020_TP1_INI_REFT(x)	(((x) & 0xf) << 16)
-#define FTSDMC020_TP1_INI_PREC(x)	(((x) & 0xf) << 20)
-
-/*
- * Configuration Register
- */
-#define FTSDMC020_CR_SREF	(1 << 0)
-#define FTSDMC020_CR_PWDN	(1 << 1)
-#define FTSDMC020_CR_ISMR	(1 << 2)
-#define FTSDMC020_CR_IREF	(1 << 3)
-#define FTSDMC020_CR_IPREC	(1 << 4)
-#define FTSDMC020_CR_REFTYPE	(1 << 5)
-
-/*
- * SDRAM External Bank Base/Size Register
- */
-#define FTSDMC020_BANK_ENABLE		(1 << 28)
-
-#define FTSDMC020_BANK_BASE(addr)	(((addr) >> 20) << 16)
-
-#define FTSDMC020_BANK_DDW_X4		(0 << 12)
-#define FTSDMC020_BANK_DDW_X8		(1 << 12)
-#define FTSDMC020_BANK_DDW_X16		(2 << 12)
-#define FTSDMC020_BANK_DDW_X32		(3 << 12)
-
-#define FTSDMC020_BANK_DSZ_16M		(0 << 8)
-#define FTSDMC020_BANK_DSZ_64M		(1 << 8)
-#define FTSDMC020_BANK_DSZ_128M		(2 << 8)
-#define FTSDMC020_BANK_DSZ_256M		(3 << 8)
-
-#define FTSDMC020_BANK_MBW_8		(0 << 4)
-#define FTSDMC020_BANK_MBW_16		(1 << 4)
-#define FTSDMC020_BANK_MBW_32		(2 << 4)
-
-#define FTSDMC020_BANK_SIZE_1M		0x0
-#define FTSDMC020_BANK_SIZE_2M		0x1
-#define FTSDMC020_BANK_SIZE_4M		0x2
-#define FTSDMC020_BANK_SIZE_8M		0x3
-#define FTSDMC020_BANK_SIZE_16M		0x4
-#define FTSDMC020_BANK_SIZE_32M		0x5
-#define FTSDMC020_BANK_SIZE_64M		0x6
-#define FTSDMC020_BANK_SIZE_128M	0x7
-#define FTSDMC020_BANK_SIZE_256M	0x8
-
-/*
- * Arbiter Control Register
- */
-#define FTSDMC020_ACR_TOC(x)	((x) & 0x1f)
-#define FTSDMC020_ACR_TOE	(1 << 8)
-
-#endif	/* __FTSDMC020_H */
diff --git a/include/faraday/ftsdmc021.h b/include/faraday/ftsdmc021.h
deleted file mode 100644
index e0e5eb339e..0000000000
--- a/include/faraday/ftsdmc021.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * (C) Copyright 2011 Andes Technology Corp
- * Macpaul Lin <macpaul@andestech.com>
- */
-
-/*
- * FTSDMC021 - SDRAM Controller
- */
-#ifndef __FTSDMC021_H
-#define __FTSDMC021_H
-
-#ifndef __ASSEMBLY__
-#include <linux/bitops.h>
-struct ftsdmc021 {
-	unsigned int	tp1;		/* 0x00 - SDRAM Timing Parameter 1 */
-	unsigned int	tp2;		/* 0x04 - SDRAM Timing Parameter 2 */
-	unsigned int	cr1;		/* 0x08 - SDRAM Configuration Reg 1 */
-	unsigned int	cr2;		/* 0x0c - SDRAM Configuration Reg 2 */
-	unsigned int	bank0_bsr;	/* 0x10 - Ext. Bank Base/Size Reg 0 */
-	unsigned int	bank1_bsr;	/* 0x14 - Ext. Bank Base/Size Reg 1 */
-	unsigned int	bank2_bsr;	/* 0x18 - Ext. Bank Base/Size Reg 2 */
-	unsigned int	bank3_bsr;	/* 0x1c - Ext. Bank Base/Size Reg 3 */
-	unsigned int	bank4_bsr;	/* 0x20 - Ext. Bank Base/Size Reg 4 */
-	unsigned int	bank5_bsr;	/* 0x24 - Ext. Bank Base/Size Reg 5 */
-	unsigned int	bank6_bsr;	/* 0x28 - Ext. Bank Base/Size Reg 6 */
-	unsigned int	bank7_bsr;	/* 0x2c - Ext. Bank Base/Size Reg 7 */
-	unsigned int	ragr;		/* 0x30 - Read Arbitration Group Reg */
-	unsigned int	frr;		/* 0x34 - Flush Request Register */
-	unsigned int	ebisr;		/* 0x38 - EBI Support Register	*/
-	unsigned int	rsved[25];	/* 0x3c-0x9c - Reserved		*/
-	unsigned int	crr;		/* 0x100 - Controller Revision Reg */
-	unsigned int	cfr;		/* 0x104 - Controller Feature Reg */
-};
-#endif /* __ASSEMBLY__ */
-
-/*
- * Timing Parameter 1 Register
- */
-#define FTSDMC021_TP1_TCL(x)	((x) & 0x3)		/* CAS Latency */
-#define FTSDMC021_TP1_TWR(x)	(((x) & 0x3) << 4)	/* W-Recovery Time */
-#define FTSDMC021_TP1_TRF(x)	(((x) & 0xf) << 8)	/* Auto-Refresh Cycle */
-#define FTSDMC021_TP1_TRCD(x)	(((x) & 0x7) << 12)	/* RAS-to-CAS Delay */
-#define FTSDMC021_TP1_TRP(x)	(((x) & 0xf) << 16)	/* Precharge Cycle */
-#define FTSDMC021_TP1_TRAS(x)	(((x) & 0xf) << 20)
-
-/*
- * Timing Parameter 2 Register
- */
-#define FTSDMC021_TP2_REF_INTV(x)	((x) & 0xffff)	/* Refresh interval */
-/* b(16:19) - Initial Refresh Times */
-#define FTSDMC021_TP2_INI_REFT(x)	(((x) & 0xf) << 16)
-/* b(20:23) - Initial Pre-Charge Times */
-#define FTSDMC021_TP2_INI_PREC(x)	(((x) & 0xf) << 20)
-
-/*
- * SDRAM Configuration Register 1
- */
-#define FTSDMC021_CR1_BNKSIZE(x)	((x) & 0xf)		/* Bank Size  */
-#define FTSDMC021_CR1_MBW(x)		(((x) & 0x3) << 4)	/* Bus Width  */
-#define FTSDMC021_CR1_DSZ(x)		(((x) & 0x7) << 8)	/* SDRAM Size */
-#define FTSDMC021_CR1_DDW(x)		(((x) & 0x3) << 12)	/* Data Width */
-/* b(16) MA2T: Double Memory Address Cycle Enable */
-#define FTSDMC021_CR1_MA2T(x)		(1 << 16)
-/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */
-#define FTSDMC021_BANK_SIZE(x)		(ffs(x) - 1)
-
-/*
- * Configuration Register 2
- */
-#define FTSDMC021_CR2_SREF	(1 << 0)	/* Self-Refresh Mode */
-#define FTSDMC021_CR2_PWDN	(1 << 1)	/* Power Down Operation Mode */
-#define FTSDMC021_CR2_ISMR	(1 << 2)	/* Start Set-Mode-Register */
-#define FTSDMC021_CR2_IREF	(1 << 3)	/* Init Refresh Start Flag */
-#define FTSDMC021_CR2_IPREC	(1 << 4)	/* Init Pre-Charge Start Flag */
-#define FTSDMC021_CR2_REFTYPE	(1 << 5)
-
-/*
- * SDRAM External Bank Base/Size Register
- */
-#define FTSDMC021_BANK_ENABLE		(1 << 12)
-
-/* 12-bit base address of external bank.
- * Default value is 0x800.
- * The 12-bit equals to the haddr[31:20] of AHB address bus. */
-#define FTSDMC021_BANK_BASE(x)		((x) & 0xfff)
-
-/*
- * Read Arbitration Grant Window Register
- */
-#define FTSDMC021_RAGR_CH1GW(x)		(((x) & 0xff) << 0)
-#define FTSDMC021_RAGR_CH2GW(x)		(((x) & 0xff) << 4)
-#define FTSDMC021_RAGR_CH3GW(x)		(((x) & 0xff) << 8)
-#define FTSDMC021_RAGR_CH4GW(x)		(((x) & 0xff) << 12)
-#define FTSDMC021_RAGR_CH5GW(x)		(((x) & 0xff) << 16)
-#define FTSDMC021_RAGR_CH6GW(x)		(((x) & 0xff) << 20)
-#define FTSDMC021_RAGR_CH7GW(x)		(((x) & 0xff) << 24)
-#define FTSDMC021_RAGR_CH8GW(x)		(((x) & 0xff) << 28)
-
-/*
- * Flush Request Register
- */
-#define FTSDMC021_FRR_FLUSHCHN(x)	(((x) & 0x7) << 0)
-#define FTSDMC021_FRR_FLUSHCMPLT	(1 << 3)	/* Flush Req Flag */
-
-/*
- * External Bus Interface Support Register (EBISR)
- */
-#define FTSDMC021_EBISR_MR(x)		((x) & 0xfff)	/* Far-end mode	*/
-#define FTSDMC021_EBISR_PRSMR		(1 << 12)	/* Pre-SMR	*/
-#define FTSDMC021_EBISR_POPREC		(1 << 13)
-#define FTSDMC021_EBISR_POSMR		(1 << 14)	/* Post-SMR	*/
-
-/*
- * Controller Revision Register (CRR, Read Only)
- */
-#define FTSDMC021_CRR_REV_VER		(((x) >> 0) & 0xff)
-#define FTSDMC021_CRR_MINOR_VER		(((x) >> 8) & 0xff)
-#define FTSDMC021_CRR_MAJOR_VER		(((x) >> 16) & 0xff)
-
-/*
- * Controller Feature Register (CFR, Read Only)
- */
-#define FTSDMC021_CFR_EBNK		(((x) >> 0) & 0xf)
-#define FTSDMC021_CFR_CHN		(((x) >> 8) & 0xf)
-#define FTSDMC021_CFR_EBI		(((x) >> 16) & 0x1)
-#define FTSDMC021_CFR_CH1_FDEPTH	(((x) >> 24) & 0x1)
-#define FTSDMC021_CFR_CH2_FDEPTH	(((x) >> 25) & 0x1)
-#define FTSDMC021_CFR_CH3_FDEPTH	(((x) >> 26) & 0x1)
-#define FTSDMC021_CFR_CH4_FDEPTH	(((x) >> 27) & 0x1)
-#define FTSDMC021_CFR_CH5_FDEPTH	(((x) >> 28) & 0x1)
-#define FTSDMC021_CFR_CH6_FDEPTH	(((x) >> 29) & 0x1)
-#define FTSDMC021_CFR_CH7_FDEPTH	(((x) >> 30) & 0x1)
-#define FTSDMC021_CFR_CH8_FDEPTH	(((x) >> 31) & 0x1)
-
-#endif	/* __FTSDMC021_H */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 5638bd4f16..2cd8366898 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -7,7 +7,8 @@
 #ifndef __FDT_SUPPORT_H
 #define __FDT_SUPPORT_H
 
-#if defined(CONFIG_OF_LIBFDT) && !defined(USE_HOSTCC)
+#if (defined(CONFIG_OF_LIBFDT) || defined(CONFIG_OF_CONTROL)) && \
+	!defined(USE_HOSTCC)
 
 #include <asm/u-boot.h>
 #include <linux/libfdt.h>
@@ -255,6 +256,14 @@ static inline void fdt_fixup_mtdparts(void *fdt,
 }
 #endif
 
+/**
+ * copy the fixed-partition nodes from U-Boot device tree to external blob
+ *
+ * @param blob		FDT blob to update
+ * Return: 0 if ok, or non-zero on error
+ */
+int fdt_copy_fixed_partitions(void *blob);
+
 void fdt_del_node_and_alias(void *blob, const char *alias);
 
 /**
diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h
index 39de7f0e3e..85af6f3996 100644
--- a/include/firmware/imx/sci/rpc.h
+++ b/include/firmware/imx/sci/rpc.h
@@ -23,12 +23,12 @@
 #define RPC_FUNC(MSG)           ((MSG)->func)
 #define RPC_R8(MSG)             ((MSG)->func)
 #define RPC_I64(MSG, IDX)       ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
-				  (s64)(RPC_U32((MSG), (IDX) + 4U))
+				(s64)(RPC_U32((MSG), (IDX) + 4U))
 #define RPC_I32(MSG, IDX)       ((MSG)->DATA.i32[(IDX) / 4U])
 #define RPC_I16(MSG, IDX)       ((MSG)->DATA.i16[(IDX) / 2U])
 #define RPC_I8(MSG, IDX)        ((MSG)->DATA.i8[(IDX)])
 #define RPC_U64(MSG, IDX)       ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
-				  (u64)(RPC_U32((MSG), (IDX) + 4U))
+				(u64)(RPC_U32((MSG), (IDX) + 4U))
 #define RPC_U32(MSG, IDX)       ((MSG)->DATA.u32[(IDX) / 4U])
 #define RPC_U16(MSG, IDX)       ((MSG)->DATA.u16[(IDX) / 2U])
 #define RPC_U8(MSG, IDX)        ((MSG)->DATA.u8[(IDX)])
@@ -67,7 +67,9 @@ struct sc_rpc_msg_s {
 #define PM_FUNC_SET_SYS_POWER_MODE		19U
 #define PM_FUNC_SET_PARTITION_POWER_MODE	1U
 #define PM_FUNC_GET_SYS_POWER_MODE		2U
+#define PM_FUNC_PARTITION_WAKE			28U
 #define PM_FUNC_SET_RESOURCE_POWER_MODE		3U
+#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL	22U
 #define PM_FUNC_GET_RESOURCE_POWER_MODE		4U
 #define PM_FUNC_REQ_LOW_POWER_MODE		16U
 #define PM_FUNC_REQ_CPU_LOW_POWER_MODE		20U
@@ -81,13 +83,16 @@ struct sc_rpc_msg_s {
 #define PM_FUNC_GET_CLOCK_PARENT		15U
 #define PM_FUNC_RESET				13U
 #define PM_FUNC_RESET_REASON			10U
+#define PM_FUNC_GET_RESET_PART			26U
 #define PM_FUNC_BOOT				8U
+#define PM_FUNC_SET_BOOT_PARM			27U
 #define PM_FUNC_REBOOT				9U
 #define PM_FUNC_REBOOT_PARTITION		12U
+#define PM_FUNC_REBOOT_CONTINUE			25U
 #define PM_FUNC_CPU_START			11U
 #define PM_FUNC_CPU_RESET			23U
 #define PM_FUNC_RESOURCE_RESET			29U
-#define PM_FUNC_IS_PARTITION_STARTED 24U
+#define PM_FUNC_IS_PARTITION_STARTED		24U
 
 /* MISC RPC */
 #define MISC_FUNC_UNKNOWN			0
@@ -95,16 +100,10 @@ struct sc_rpc_msg_s {
 #define MISC_FUNC_GET_CONTROL			2U
 #define MISC_FUNC_SET_MAX_DMA_GROUP		4U
 #define MISC_FUNC_SET_DMA_GROUP			5U
-#define MISC_FUNC_SECO_IMAGE_LOAD		8U
-#define MISC_FUNC_SECO_AUTHENTICATE		9U
-#define MISC_FUNC_SECO_FUSE_WRITE		20U
-#define MISC_FUNC_SECO_ENABLE_DEBUG		21U
-#define MISC_FUNC_SECO_FORWARD_LIFECYCLE	22U
-#define MISC_FUNC_SECO_RETURN_LIFECYCLE		23U
-#define MISC_FUNC_SECO_BUILD_INFO		24U
 #define MISC_FUNC_DEBUG_OUT			10U
 #define MISC_FUNC_WAVEFORM_CAPTURE		6U
 #define MISC_FUNC_BUILD_INFO			15U
+#define MISC_FUNC_API_VER			35U
 #define MISC_FUNC_UNIQUE_ID			19U
 #define MISC_FUNC_SET_ARI			3U
 #define MISC_FUNC_BOOT_STATUS			7U
@@ -114,8 +113,11 @@ struct sc_rpc_msg_s {
 #define MISC_FUNC_SET_TEMP			12U
 #define MISC_FUNC_GET_TEMP			13U
 #define MISC_FUNC_GET_BOOT_DEV			16U
+#define MISC_FUNC_GET_BOOT_TYPE			33U
+#define MISC_FUNC_GET_BOOT_CONTAINER		36U
 #define MISC_FUNC_GET_BUTTON_STATUS		18U
-#define MISC_FUNC_GET_BOOT_CONTAINER	36U
+#define MISC_FUNC_ROMPATCH_CHECKSUM		26U
+#define MISC_FUNC_BOARD_IOCTL			34U
 
 /* PAD RPC */
 #define PAD_FUNC_UNKNOWN			0
@@ -160,6 +162,7 @@ struct sc_rpc_msg_s {
 #define RM_FUNC_GET_RESOURCE_INFO		16U
 #define RM_FUNC_MEMREG_ALLOC			17U
 #define RM_FUNC_MEMREG_SPLIT			29U
+#define RM_FUNC_MEMREG_FRAG			32U
 #define RM_FUNC_MEMREG_FREE			18U
 #define RM_FUNC_FIND_MEMREG			30U
 #define RM_FUNC_ASSIGN_MEMREG			19U
@@ -190,6 +193,7 @@ struct sc_rpc_msg_s {
 #define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
 #define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
 #define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
+#define SECO_FUNC_V2X_BUILD_INFO 30U /* Index for sc_seco_v2x_build_info() RPC call */
 #define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
 #define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
 #define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
@@ -210,6 +214,7 @@ struct sc_rpc_msg_s {
 #define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
 #define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */
 #define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */
+#define TIMER_FUNC_SET_WDOG_WINDOW 19U /* Index for sc_timer_set_wdog_window() RPC call */
 #define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */
 #define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */
 #define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */
diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h
index 61c8211b44..f832982b3d 100644
--- a/include/firmware/imx/sci/sci.h
+++ b/include/firmware/imx/sci/sci.h
@@ -13,6 +13,7 @@
 #include <firmware/imx/sci/svc/pm/api.h>
 #include <firmware/imx/sci/svc/rm/api.h>
 #include <firmware/imx/sci/svc/seco/api.h>
+#include <firmware/imx/sci/svc/timer/api.h>
 #include <firmware/imx/sci/rpc.h>
 #include <dt-bindings/soc/imx_rsrc.h>
 #include <linux/errno.h>
@@ -73,6 +74,7 @@ int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
 			   sc_pm_clk_parent_t parent);
 int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
 		    sc_faddr_t address);
+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type);
 sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
 int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource);
 
@@ -88,6 +90,7 @@ void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
 int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
 int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
 		     s16 *celsius, s8 *tenths);
+void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status);
 
 /* RM API */
 sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
@@ -117,6 +120,9 @@ int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
 /* SMMU API */
 int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
 
+/* Timer API */
+int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window);
+
 /* SECO API */
 int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
 			 sc_faddr_t addr);
@@ -124,6 +130,7 @@ int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change);
 int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l,
 		      u32 *uid_h);
 void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
+int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
 int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
 int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
 			 sc_faddr_t export_addr, u16 max_size);
@@ -374,6 +381,23 @@ static inline int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, u32 *dat
 	return -EOPNOTSUPP;
 }
 
+static inline void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
+{
+}
+
+static inline int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status)
+{
+}
+
+static inline int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window)
+{
+	return -EOPNOTSUPP;
+}
 #endif
 
 #endif
diff --git a/include/firmware/imx/sci/svc/misc/api.h b/include/firmware/imx/sci/svc/misc/api.h
index 3629eb68d7..a4b92b86cc 100644
--- a/include/firmware/imx/sci/svc/misc/api.h
+++ b/include/firmware/imx/sci/svc/misc/api.h
@@ -5,27 +5,45 @@
 
 #ifndef SC_MISC_API_H
 #define SC_MISC_API_H
+/* Defines for type widths */
+#define SC_MISC_DMA_GRP_W       5U      /* Width of sc_misc_dma_group_t */
 
+/* Max DMA channel priority group */
+#define SC_MISC_DMA_GRP_MAX     31U
 /* Defines for sc_misc_boot_status_t */
 #define SC_MISC_BOOT_STATUS_SUCCESS	0U	/* Success */
 #define SC_MISC_BOOT_STATUS_SECURITY	1U	/* Security violation */
 
-/* Defines for sc_misc_seco_auth_cmd_t */
-#define SC_MISC_SECO_AUTH_SECO_FW	0U   /* SECO Firmware */
-#define SC_MISC_SECO_AUTH_HDMI_TX_FW	1U   /* HDMI TX Firmware */
-#define SC_MISC_SECO_AUTH_HDMI_RX_FW	2U   /* HDMI RX Firmware */
-
 /* Defines for sc_misc_temp_t */
-#define SC_MISC_TEMP			0U	/* Temp sensor */
-#define SC_MISC_TEMP_HIGH		1U	/* Temp high alarm */
-#define SC_MISC_TEMP_LOW		2U	/* Temp low alarm */
+#define SC_MISC_TEMP                    0U   /* Temp sensor */
+#define SC_MISC_TEMP_HIGH               1U   /* Temp high alarm */
+#define SC_MISC_TEMP_LOW                2U   /* Temp low alarm */
+
+/* Defines for sc_misc_bt_t */
+#define SC_MISC_BT_PRIMARY              0U   /* Primary boot */
+#define SC_MISC_BT_SECONDARY            1U   /* Secondary boot */
+#define SC_MISC_BT_RECOVERY             2U   /* Recovery boot */
+#define SC_MISC_BT_MANUFACTURE          3U   /* Manufacture boot */
+#define SC_MISC_BT_SERIAL               4U   /* Serial boot */
+/* Types */
 
-/* Defines for sc_misc_seco_auth_cmd_t */
-#define SC_MISC_AUTH_CONTAINER	0U	/* Authenticate container */
-#define SC_MISC_VERIFY_IMAGE	1U	/* Verify image */
-#define SC_MISC_REL_CONTAINER	2U	/* Release container */
+/*
+ * This type is used to store a DMA channel priority group.
+ */
+typedef u8 sc_misc_dma_group_t;
 
+/*
+ * This type is used report boot status.
+ */
 typedef u8 sc_misc_boot_status_t;
+
+/*
+ * This type is used report boot status.
+ */
 typedef u8 sc_misc_temp_t;
 
+/*
+ * This type is used report the boot type.
+ */
+typedef u8 sc_misc_bt_t;
 #endif /* SC_MISC_API_H */
diff --git a/include/firmware/imx/sci/svc/pm/api.h b/include/firmware/imx/sci/svc/pm/api.h
index 9008b85c6f..d1b085d7f8 100644
--- a/include/firmware/imx/sci/svc/pm/api.h
+++ b/include/firmware/imx/sci/svc/pm/api.h
@@ -6,6 +6,14 @@
 #ifndef SC_PM_API_H
 #define SC_PM_API_H
 
+#include <firmware/imx/sci/types.h>
+/* Defines for type widths */
+#define SC_PM_POWER_MODE_W      2U      /* Width of sc_pm_power_mode_t */
+#define SC_PM_CLOCK_MODE_W      3U      /* Width of sc_pm_clock_mode_t */
+#define SC_PM_RESET_TYPE_W      2U      /* Width of sc_pm_reset_type_t */
+#define SC_PM_RESET_REASON_W    4U      /* Width of sc_pm_reset_reason_t */
+/* Defines for ALL parameters */
+#define SC_PM_CLK_ALL   ((sc_pm_clk_t)UINT8_MAX)   /* All clocks */
 /* Defines for sc_pm_power_mode_t */
 #define SC_PM_PW_MODE_OFF	0U /* Power off */
 #define SC_PM_PW_MODE_STBY	1U /* Power in standby */
@@ -35,10 +43,96 @@
 #define SC_PM_CLK_MODE_AUTOGATE_HW	4U /* Clock is in HW autogate mode */
 #define SC_PM_CLK_MODE_AUTOGATE_SW_HW	5U /* Clock is in SW-HW autogate mode */
 
+/* Defines for sc_pm_clk_parent_t */
+#define SC_PM_PARENT_XTAL              0U    /*!< Parent is XTAL. */
+#define SC_PM_PARENT_PLL0              1U    /*!< Parent is PLL0 */
+#define SC_PM_PARENT_PLL1              2U    /*!< Parent is PLL1 or PLL0/2 */
+#define SC_PM_PARENT_PLL2              3U    /*!< Parent in PLL2 or PLL0/4 */
+#define SC_PM_PARENT_BYPS              4U    /*!< Parent is a bypass clock. */
+
+/* Defines for sc_pm_reset_type_t */
+#define SC_PM_RESET_TYPE_COLD          0U    /* Cold reset */
+#define SC_PM_RESET_TYPE_WARM          1U    /* Warm reset */
+#define SC_PM_RESET_TYPE_BOARD         2U    /* Board reset */
+
+/* Defines for sc_pm_reset_reason_t */
+#define SC_PM_RESET_REASON_POR         0U    /* Power on reset */
+#define SC_PM_RESET_REASON_JTAG        1U    /* JTAG reset */
+#define SC_PM_RESET_REASON_SW          2U    /* Software reset */
+#define SC_PM_RESET_REASON_WDOG        3U    /* Partition watchdog reset */
+#define SC_PM_RESET_REASON_LOCKUP      4U    /* SCU lockup reset */
+#define SC_PM_RESET_REASON_SNVS        5U    /* SNVS reset */
+#define SC_PM_RESET_REASON_TEMP        6U    /* Temp panic reset */
+#define SC_PM_RESET_REASON_MSI         7U    /* MSI reset */
+#define SC_PM_RESET_REASON_UECC        8U    /* ECC reset */
+#define SC_PM_RESET_REASON_SCFW_WDOG   9U    /* SCFW watchdog reset */
+#define SC_PM_RESET_REASON_ROM_WDOG    10U   /* SCU ROM watchdog reset */
+#define SC_PM_RESET_REASON_SECO        11U   /* SECO reset */
+#define SC_PM_RESET_REASON_SCFW_FAULT  12U   /* SCFW fault reset */
+
+/* Defines for sc_pm_sys_if_t */
+#define SC_PM_SYS_IF_INTERCONNECT       0U   /* System interconnect */
+#define SC_PM_SYS_IF_MU                 1U   /* AP -> SCU message units */
+#define SC_PM_SYS_IF_OCMEM              2U   /* On-chip memory (ROM/OCRAM) */
+#define SC_PM_SYS_IF_DDR                3U   /* DDR memory */
+
+/* Defines for sc_pm_wake_src_t */
+/* No wake source, used for self-kill */
+#define SC_PM_WAKE_SRC_NONE             0U
+/* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
+#define SC_PM_WAKE_SRC_SCU              1U
+/* Wakeup from IRQSTEER to resume CPU (GIC powered down) */
+#define SC_PM_WAKE_SRC_IRQSTEER         2U
+/* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */
+#define SC_PM_WAKE_SRC_IRQSTEER_GIC     3U
+/* Wakeup from GIC to wake CPU */
+#define SC_PM_WAKE_SRC_GIC              4U
+/* Types */
+
+/*
+ * This type is used to declare a power mode. Note resources only use
+ * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only
+ * as system power modes.
+ */
 typedef u8 sc_pm_power_mode_t;
+
+/*
+ * This type is used to declare a clock.
+ */
 typedef u8 sc_pm_clk_t;
+
+/*
+ * This type is used to declare a clock mode.
+ */
 typedef u8 sc_pm_clk_mode_t;
+
+/*
+ * This type is used to declare the clock parent.
+ */
 typedef u8 sc_pm_clk_parent_t;
+
+/*
+ * This type is used to declare clock rates.
+ */
 typedef u32 sc_pm_clock_rate_t;
 
+/*
+ * This type is used to declare a desired reset type.
+ */
+typedef u8 sc_pm_reset_type_t;
+
+/*
+ * This type is used to declare a reason for a reset.
+ */
+typedef u8 sc_pm_reset_reason_t;
+
+/*
+ * This type is used to specify a system-level interface to be power managed.
+ */
+typedef u8 sc_pm_sys_if_t;
+
+/*
+ * This type is used to specify a wake source for CPU resources.
+ */
+typedef u8 sc_pm_wake_src_t;
 #endif /* SC_PM_API_H */
diff --git a/include/firmware/imx/sci/svc/rm/api.h b/include/firmware/imx/sci/svc/rm/api.h
index 163d81403c..f4e9abcd9b 100644
--- a/include/firmware/imx/sci/svc/rm/api.h
+++ b/include/firmware/imx/sci/svc/rm/api.h
@@ -38,32 +38,36 @@
 
 /* Types */
 
-/*!
+/*
  * This type is used to declare a resource partition.
  */
 typedef u8 sc_rm_pt_t;
 
-/*!
+/*
  * This type is used to declare a memory region.
  */
 typedef u8 sc_rm_mr_t;
 
-/*!
+/*
  * This type is used to declare a resource domain ID used by the
  * isolation HW.
  */
 typedef u8 sc_rm_did_t;
 
-/*!
+/*
  * This type is used to declare an SMMU StreamID.
  */
 typedef u16 sc_rm_sid_t;
 
-/*!
+/*
  * This type is a used to declare master transaction attributes.
  */
 typedef u8 sc_rm_spa_t;
 
+/*
+ * This type is used to declare a resource/memory region access permission.
+ * Refer to the XRDC2 Block Guide for more information.
+ */
 typedef u8 sc_rm_perm_t;
 
 #endif /* SC_RM_API_H */
diff --git a/include/firmware/imx/sci/svc/seco/api.h b/include/firmware/imx/sci/svc/seco/api.h
index 6e9c302315..7d4b6b92e1 100644
--- a/include/firmware/imx/sci/svc/seco/api.h
+++ b/include/firmware/imx/sci/svc/seco/api.h
@@ -17,6 +17,7 @@
 #define SC_SECO_AUTH_SECO_FW            3U   /* SECO Firmware */
 #define SC_SECO_AUTH_HDMI_TX_FW         4U   /* HDMI TX Firmware */
 #define SC_SECO_AUTH_HDMI_RX_FW         5U   /* HDMI RX Firmware */
+#define SC_SECO_EVERIFY_IMAGE           6U   /* Enhanced verify image */
 
 #define SC_SECO_RNG_STAT_UNAVAILABLE    0U  /* Unable to initialize the RNG */
 #define SC_SECO_RNG_STAT_INPROGRESS     1U  /* Initialization is on-going */
@@ -24,12 +25,12 @@
 
 /* Types */
 
-/*!
+/*
  * This type is used to issue SECO authenticate commands.
  */
 typedef u8 sc_seco_auth_cmd_t;
 
-/*!
+/*
  * This type is used to return the RNG initialization status.
  */
 typedef u32 sc_seco_rng_stat_t;
diff --git a/include/firmware/imx/sci/svc/timer/api.h b/include/firmware/imx/sci/svc/timer/api.h
new file mode 100644
index 0000000000..c2fe34aa75
--- /dev/null
+++ b/include/firmware/imx/sci/svc/timer/api.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef SC_TIMER_API_H
+#define SC_TIMER_API_H
+
+/* Defines */
+
+/* Defines for type widths */
+#define SC_TIMER_ACTION_W   3U      /* Width of sc_timer_wdog_action_t */
+
+/* Defines for sc_timer_wdog_action_t */
+#define SC_TIMER_WDOG_ACTION_PARTITION      0U   /* Reset partition */
+#define SC_TIMER_WDOG_ACTION_WARM           1U   /* Warm reset system */
+#define SC_TIMER_WDOG_ACTION_COLD           2U   /* Cold reset system */
+#define SC_TIMER_WDOG_ACTION_BOARD          3U   /* Reset board */
+#define SC_TIMER_WDOG_ACTION_IRQ            4U   /* Only generate IRQs */
+
+/* Types */
+
+/*
+ * This type is used to configure the watchdog action.
+ */
+typedef u8 sc_timer_wdog_action_t;
+
+/*
+ * This type is used to declare a watchdog time value in milliseconds.
+ */
+typedef u32 sc_timer_wdog_time_t;
+
+#endif /* SC_TIMER_API_H */
diff --git a/include/fs.h b/include/fs.h
index 8370d88cb2..e341a0ed01 100644
--- a/include/fs.h
+++ b/include/fs.h
@@ -300,4 +300,42 @@ int do_fs_type(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
  */
 int do_fs_types(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
 
+/**
+ * fs_read_alloc() - Allocate space for a file and read it
+ *
+ * You must call fs_set_blk_dev() or a similar function before calling this,
+ * since that sets up the block device to use.
+ *
+ * The file is terminated with a nul character
+ *
+ * @fname: Filename to read
+ * @size: Size of file to read (must be correct!)
+ * @align: Alignment to use for memory allocation (0 for default)
+ * @bufp: On success, returns the allocated buffer with the nul-terminated file
+ *	in it
+ * Return: 0 if OK, -ENOMEM if out of memory, -EIO if read failed
+ */
+int fs_read_alloc(const char *fname, ulong size, uint align, void **bufp);
+
+/**
+ * fs_load_alloc() - Load a file into allocated space
+ *
+ * The file is terminated with a nul character
+ *
+ * @ifname: Interface name to read from (e.g. "mmc")
+ * @dev_part_str: Device and partition string (e.g. "1:2")
+ * @fname: Filename to read
+ * @max_size: Maximum allowed size for the file (use 0 for 1GB)
+ * @align: Alignment to use for memory allocation (0 for default)
+ * @bufp: On success, returns the allocated buffer with the nul-terminated file
+ *	in it
+ * @sizep: On success, returns the size of the file
+ * Return: 0 if OK, -ENOMEM if out of memory, -ENOENT if the file does not
+ * exist, -ENOMEDIUM if the device does not exist, -E2BIG if the file is too
+ * large (greater than @max_size), -EIO if read failed
+ */
+int fs_load_alloc(const char *ifname, const char *dev_part_str,
+		  const char *fname, ulong max_size, ulong align, void **bufp,
+		  ulong *sizep);
+
 #endif /* _FS_H */
diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h
index 2278ac952e..3f3e6c4070 100644
--- a/include/fsl-mc/fsl_dpbp.h
+++ b/include/fsl-mc/fsl_dpbp.h
@@ -1,14 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Freescale Layerscape MC I/O wrapper
+ * Data Path Buffer Pool API
+ *  Contains initialization APIs and runtime control APIs for DPBP
  *
  * Copyright 2013-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
- */
-/*!
- *  @file    fsl_dpbp.h
- *  @brief   Data Path Buffer Pool API
+ * Copyright 2017-2023 NXP
  */
+
 #ifndef __FSL_DPBP_H
 #define __FSL_DPBP_H
 
@@ -27,160 +26,50 @@
 #define DPBP_CMDID_DISABLE				0x0031
 #define DPBP_CMDID_GET_ATTR				0x0041
 #define DPBP_CMDID_RESET				0x0051
-#define DPBP_CMDID_IS_ENABLED				0x0061
 
-/*                cmd, param, offset, width, type, arg_name */
-#define DPBP_CMD_OPEN(cmd, dpbp_id) \
-	MC_CMD_OP(cmd, 0, 0,  32, int,	    dpbp_id)
+#pragma pack(push, 1)
+
+struct dpbp_cmd_open {
+	__le32 dpbp_id;
+};
 
-/*                cmd, param, offset, width, type, arg_name */
-#define DPBP_RSP_GET_ATTRIBUTES(cmd, attr) \
-do { \
-	MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->bpid); \
-	MC_RSP_OP(cmd, 0, 32, 32, int,	    attr->id);\
-} while (0)
+struct dpbp_cmd_destroy {
+	__le32 object_id;
+};
 
-/* Data Path Buffer Pool API
- * Contains initialization APIs and runtime control APIs for DPBP
- */
+struct dpbp_rsp_get_attributes {
+	__le16 pad;
+	__le16 bpid;
+	__le32 id;
+};
+
+#pragma pack(pop)
 
 struct fsl_mc_io;
 
-/**
- * dpbp_open() - Open a control session for the specified object.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @dpbp_id:	DPBP unique ID
- * @token:	Returned token; use in subsequent API calls
- *
- * This function can be used to open a control session for an
- * already created object; an object may have been declared in
- * the DPL or by calling the dpbp_create function.
- * This function returns a unique authentication token,
- * associated with the specific object ID and the specific MC
- * portal; this token must be used in all subsequent commands for
- * this specific object
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpbp_open(struct fsl_mc_io	*mc_io,
-	      uint32_t		cmd_flags,
-	      int		dpbp_id,
-	      uint16_t		*token);
+int dpbp_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpbp_id, u16 *token);
 
-/**
- * dpbp_close() - Close the control session of the object
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPBP object
- *
- * After this function is called, no further operations are
- * allowed on the object without opening a new control session.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpbp_close(struct fsl_mc_io	*mc_io,
-	       uint32_t		cmd_flags,
-	       uint16_t	token);
+int dpbp_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
 /**
  * struct dpbp_cfg - Structure representing DPBP configuration
  * @options:	place holder
  */
 struct dpbp_cfg {
-	uint32_t options;
+	u32 options;
 };
 
-/**
- * dpbp_create() - Create the DPBP object.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @cfg:	Configuration structure
- * @token:	Returned token; use in subsequent API calls
- *
- * Create the DPBP object, allocate required resources and
- * perform required initialization.
- *
- * The object can be created either by declaring it in the
- * DPL file, or by calling this function.
- * This function returns a unique authentication token,
- * associated with the specific object ID and the specific MC
- * portal; this token must be used in all subsequent calls to
- * this specific object. For objects that are created using the
- * DPL file, call dpbp_open function to get an authentication
- * token first.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpbp_create(struct fsl_mc_io	*mc_io,
-		uint16_t		dprc_token,
-		uint32_t		cmd_flags,
-		const struct dpbp_cfg	*cfg,
-		uint32_t		*obj_id);
+int dpbp_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		const struct dpbp_cfg *cfg, u32 *obj_id);
 
-/**
- * dpbp_destroy() - Destroy the DPBP object and release all its resources.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPBP object
- *
- * Return:	'0' on Success; error code otherwise.
- */
-int dpbp_destroy(struct fsl_mc_io	*mc_io,
-		 uint16_t		dprc_token,
-		 uint32_t		cmd_flags,
-		 uint32_t		obj_id);
+int dpbp_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		 u32 obj_id);
 
-/**
- * dpbp_enable() - Enable the DPBP.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPBP object
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpbp_enable(struct fsl_mc_io	*mc_io,
-		uint32_t		cmd_flags,
-		uint16_t		token);
+int dpbp_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
-/**
- * dpbp_disable() - Disable the DPBP.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPBP object
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpbp_disable(struct fsl_mc_io	*mc_io,
-		 uint32_t		cmd_flags,
-		 uint16_t		token);
-
-/**
- * dpbp_is_enabled() - Check if the DPBP is enabled.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPBP object
- * @en:		Returns '1' if object is enabled; '0' otherwise
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpbp_is_enabled(struct fsl_mc_io	*mc_io,
-		    uint32_t		cmd_flags,
-		    uint16_t		token,
-		    int		*en);
-
-/**
- * dpbp_reset() - Reset the DPBP, returns the object to initial state.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPBP object
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpbp_reset(struct fsl_mc_io	*mc_io,
-	       uint32_t		cmd_flags,
-	       uint16_t	token);
+int dpbp_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
+int dpbp_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
 /**
  * struct dpbp_attr - Structure representing DPBP attributes
@@ -190,40 +79,14 @@ int dpbp_reset(struct fsl_mc_io	*mc_io,
  *		acquire/release operations on buffers
  */
 struct dpbp_attr {
-	uint32_t id;
-	uint16_t bpid;
+	u32 id;
+	u16 bpid;
 };
 
-/**
- * dpbp_get_attributes - Retrieve DPBP attributes.
- *
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPBP object
- * @attr:	Returned object's attributes
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpbp_get_attributes(struct fsl_mc_io	*mc_io,
-			uint32_t	cmd_flags,
-			uint16_t		token,
-			struct dpbp_attr	*attr);
-
-/**
- * dpbp_get_api_version - Retrieve DPBP Major and Minor version info.
- *
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @major_ver:	DPBP major version
- * @minor_ver:	DPBP minor version
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpbp_get_api_version(struct fsl_mc_io *mc_io,
-			 u32 cmd_flags,
-			 u16 *major_ver,
-			 u16 *minor_ver);
+int dpbp_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			struct dpbp_attr *attr);
 
-/** @} */
+int dpbp_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+			 u16 *major_ver, u16 *minor_ver);
 
 #endif /* __FSL_DPBP_H */
diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h
index 7788e1962e..375590fd97 100644
--- a/include/fsl-mc/fsl_dpio.h
+++ b/include/fsl-mc/fsl_dpio.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2013-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017, 2023 NXP
  */
 
 #ifndef _FSL_DPIO_H
@@ -21,31 +21,53 @@
 #define DPIO_CMDID_ENABLE					0x0021
 #define DPIO_CMDID_DISABLE					0x0031
 #define DPIO_CMDID_GET_ATTR					0x0041
-#define DPIO_CMDID_RESET					0x0051
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPIO_CMD_OPEN(cmd, dpio_id) \
-	MC_CMD_OP(cmd, 0, 0,  32, int,     dpio_id)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPIO_CMD_CREATE(cmd, cfg) \
-do { \
-	MC_CMD_OP(cmd, 0, 16, 2,  enum dpio_channel_mode,	\
-					   cfg->channel_mode);\
-	MC_CMD_OP(cmd, 0, 32, 8,  uint8_t, cfg->num_priorities);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPIO_RSP_GET_ATTR(cmd, attr) \
-do { \
-	MC_RSP_OP(cmd, 0, 0,  32, int,	    attr->id);\
-	MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qbman_portal_id);\
-	MC_RSP_OP(cmd, 0, 48, 8,  uint8_t,  attr->num_priorities);\
-	MC_RSP_OP(cmd, 0, 56, 4,  enum dpio_channel_mode, attr->channel_mode);\
-	MC_RSP_OP(cmd, 1, 0,  64, uint64_t, attr->qbman_portal_ce_offset);\
-	MC_RSP_OP(cmd, 2, 0,  64, uint64_t, attr->qbman_portal_ci_offset);\
-	MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\
-} while (0)
+
+/* Macros for accessing command fields smaller than 1byte */
+#define DPIO_MASK(field)        \
+	GENMASK(DPIO_##field##_SHIFT + DPIO_##field##_SIZE - 1, \
+		DPIO_##field##_SHIFT)
+#define dpio_set_field(var, field, val) \
+	((var) |= (((val) << DPIO_##field##_SHIFT) & DPIO_MASK(field)))
+#define dpio_get_field(var, field)      \
+	(((var) & DPIO_MASK(field)) >> DPIO_##field##_SHIFT)
+
+#pragma pack(push, 1)
+struct dpio_cmd_open {
+	__le32 dpio_id;
+};
+
+#define DPIO_CHANNEL_MODE_SHIFT		0
+#define DPIO_CHANNEL_MODE_SIZE		2
+
+struct dpio_cmd_create {
+	__le16 pad1;
+	/* from LSB: channel_mode:2 */
+	u8 channel_mode;
+	u8 pad2;
+	u8 num_priorities;
+};
+
+struct dpio_cmd_destroy {
+	__le32 dpio_id;
+};
+
+#define DPIO_ATTR_CHANNEL_MODE_SHIFT	0
+#define DPIO_ATTR_CHANNEL_MODE_SIZE	4
+
+struct dpio_rsp_get_attr {
+	__le32 id;
+	__le16 qbman_portal_id;
+	u8 num_priorities;
+	/* from LSB: channel_mode:4 */
+	u8 channel_mode;
+	__le64 qbman_portal_ce_offset;
+	__le64 qbman_portal_ci_offset;
+	__le32 qbman_version;
+	__le32 pad;
+	__le32 clk;
+};
+
+#pragma pack(pop)
 
 /* Data Path I/O Portal API
  * Contains initialization APIs and runtime control APIs for DPIO
@@ -53,44 +75,15 @@ do { \
 
 struct fsl_mc_io;
 
-/**
- * dpio_open() - Open a control session for the specified object
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @dpio_id:	DPIO unique ID
- * @token:	Returned token; use in subsequent API calls
- *
- * This function can be used to open a control session for an
- * already created object; an object may have been declared in
- * the DPL or by calling the dpio_create() function.
- * This function returns a unique authentication token,
- * associated with the specific object ID and the specific MC
- * portal; this token must be used in all subsequent commands for
- * this specific object.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpio_open(struct fsl_mc_io	*mc_io,
-	      uint32_t		cmd_flags,
-	      uint32_t		dpio_id,
-	      uint16_t		*token);
+int dpio_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpio_id,
+	      u16 *token);
 
-/**
- * dpio_close() - Close the control session of the object
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPIO object
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpio_close(struct fsl_mc_io	*mc_io,
-	       uint32_t		cmd_flags,
-	       uint16_t		token);
+int dpio_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
 /**
  * enum dpio_channel_mode - DPIO notification channel mode
- * @DPIO_NO_CHANNEL: No support for notification channel
- * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a
+ * @DPIO_NO_CHANNEL:	No support for notification channel
+ * @DPIO_LOCAL_CHANNEL:	Notifications on data availability can be received by a
  *	dedicated channel in the DPIO; user should point the queue's
  *	destination in the relevant interface to this DPIO
  */
@@ -101,143 +94,52 @@ enum dpio_channel_mode {
 
 /**
  * struct dpio_cfg - Structure representing DPIO configuration
- * @channel_mode: Notification channel mode
- * @num_priorities: Number of priorities for the notification channel (1-8);
+ * @channel_mode:	Notification channel mode
+ * @num_priorities:	Number of priorities for the notification channel (1-8);
  *			relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
  */
 struct dpio_cfg {
-	enum dpio_channel_mode	channel_mode;
-	uint8_t		num_priorities;
+	enum dpio_channel_mode channel_mode;
+	u8 num_priorities;
 };
 
-/**
- * dpio_create() - Create the DPIO object.
- * @mc_io:	Pointer to MC portal's I/O object
- * @token:	Authentication token.
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @cfg:	Configuration structure
- * @obj_id:	Returned obj_id; use in subsequent API calls
- *
- * Create the DPIO object, allocate required resources and
- * perform required initialization.
- *
- * The object can be created either by declaring it in the
- * DPL file, or by calling this function.
- *
- * This function returns a unique authentication token,
- * associated with the specific object ID and the specific MC
- * portal; this token must be used in all subsequent calls to
- * this specific object. For objects that are created using the
- * DPL file, call dpio_open() function to get an authentication
- * token first.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpio_create(struct fsl_mc_io	*mc_io,
-		uint16_t		token,
-		uint32_t		cmd_flags,
-		const struct dpio_cfg	*cfg,
-		uint32_t		*obj_id);
-
-/**
- * dpio_destroy() - Destroy the DPIO object and release all its resources.
- * @mc_io:	Pointer to MC portal's I/O object
- * @token:	Authentication token.
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @obj_id:	Object ID of DPIO
- *
- * Return:	'0' on Success; Error code otherwise
- */
-int dpio_destroy(struct fsl_mc_io	*mc_io,
-		 uint16_t		token,
-		 uint32_t		cmd_flags,
-		 uint32_t		obj_id);
+int dpio_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		const struct dpio_cfg *cfg, u32 *obj_id);
 
-/**
- * dpio_enable() - Enable the DPIO, allow I/O portal operations.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPIO object
- *
- * Return:	'0' on Success; Error code otherwise
- */
-int dpio_enable(struct fsl_mc_io	*mc_io,
-		uint32_t		cmd_flags,
-		uint16_t		token);
+int dpio_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		 u32 object_id);
 
-/**
- * dpio_disable() - Disable the DPIO, stop any I/O portal operation.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPIO object
- *
- * Return:	'0' on Success; Error code otherwise
- */
-int dpio_disable(struct fsl_mc_io	*mc_io,
-		 uint32_t		cmd_flags,
-		 uint16_t		token);
+int dpio_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
-/**
- * dpio_reset() - Reset the DPIO, returns the object to initial state.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPIO object
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpio_reset(struct fsl_mc_io	*mc_io,
-	       uint32_t			cmd_flags,
-	       uint16_t		token);
+int dpio_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
 /**
  * struct dpio_attr - Structure representing DPIO attributes
- * @id: DPIO object ID
- * @version: DPIO version
- * @qbman_portal_ce_offset: offset of the software portal cache-enabled area
- * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area
- * @qbman_portal_id: Software portal ID
- * @channel_mode: Notification channel mode
- * @num_priorities: Number of priorities for the notification channel (1-8);
- *			relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
- * @qbman_version: QBMAN version
+ * @id:				DPIO object ID
+ * @qbman_portal_ce_offset:	Offset of the software portal cache-enabled area
+ * @qbman_portal_ci_offset:	Offset of the software portal
+ *				cache-inhibited area
+ * @qbman_portal_id:		Software portal ID
+ * @channel_mode:		Notification channel mode
+ * @num_priorities:		Number of priorities for the notification
+ *				channel (1-8); relevant only if
+ *				'channel_mode = DPIO_LOCAL_CHANNEL'
+ * @qbman_version:		QBMAN version
  */
 struct dpio_attr {
-	uint32_t id;
-	uint64_t qbman_portal_ce_offset;
-	uint64_t qbman_portal_ci_offset;
-	uint16_t qbman_portal_id;
+	int id;
+	u64 qbman_portal_ce_offset;
+	u64 qbman_portal_ci_offset;
+	u16 qbman_portal_id;
 	enum dpio_channel_mode channel_mode;
-	uint8_t num_priorities;
-	uint32_t		qbman_version;
+	u8 num_priorities;
+	u32 qbman_version;
+	u32 clk;
 };
 
-/**
- * dpio_get_attributes() - Retrieve DPIO attributes
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPIO object
- * @attr:	Returned object's attributes
- *
- * Return:	'0' on Success; Error code otherwise
- */
-int dpio_get_attributes(struct fsl_mc_io	*mc_io,
-			uint32_t		cmd_flags,
-			uint16_t		token,
-			struct dpio_attr	*attr);
-
-/**
- * dpio_get_api_version - Retrieve DPIO Major and Minor version info.
- *
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @major_ver:	DPIO major version
- * @minor_ver:	DPIO minor version
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpio_get_api_version(struct fsl_mc_io *mc_io,
-			 u32 cmd_flags,
-			 u16 *major_ver,
-			 u16 *minor_ver);
+int dpio_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			struct dpio_attr *attr);
 
+int dpio_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+			 u16 *major_ver, u16 *minor_ver);
 #endif /* _FSL_DPIO_H */
diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h
index 1cea123a31..a8e9e4684a 100644
--- a/include/fsl-mc/fsl_dpmac.h
+++ b/include/fsl-mc/fsl_dpmac.h
@@ -21,74 +21,59 @@
 #define DPMAC_CMDID_DESTROY			0x98c1
 #define DPMAC_CMDID_GET_API_VERSION             0xa0c1
 
-#define DPMAC_CMDID_GET_ATTR			0x0041
 #define DPMAC_CMDID_RESET			0x0051
 
-#define DPMAC_CMDID_MDIO_READ			0x0c01
-#define DPMAC_CMDID_MDIO_WRITE			0x0c11
-#define DPMAC_CMDID_GET_LINK_CFG		0x0c21
 #define DPMAC_CMDID_SET_LINK_STATE		0x0c31
 #define DPMAC_CMDID_GET_COUNTER			0x0c41
 
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMAC_CMD_CREATE(cmd, cfg) \
-	MC_CMD_OP(cmd, 0, 0,  16, uint16_t,      cfg->mac_id)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMAC_CMD_OPEN(cmd, dpmac_id) \
-	MC_CMD_OP(cmd, 0, 0,  32, int,	    dpmac_id)
-
-/*                cmd, param, offset, width, type,	arg_name */
-#define DPMAC_RSP_GET_ATTRIBUTES(cmd, attr) \
-do { \
-	MC_RSP_OP(cmd, 0, 0,  32, int,			attr->phy_id);\
-	MC_RSP_OP(cmd, 0, 32, 32, int,			attr->id);\
-	MC_RSP_OP(cmd, 1, 32,  8, enum dpmac_link_type,	attr->link_type);\
-	MC_RSP_OP(cmd, 1, 40,  8, enum dpmac_eth_if,	attr->eth_if);\
-	MC_RSP_OP(cmd, 2, 0,  32, uint32_t,		attr->max_rate);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMAC_CMD_MDIO_READ(cmd, cfg) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  8,  uint8_t,  cfg->phy_addr); \
-	MC_CMD_OP(cmd, 0, 8,  8,  uint8_t,  cfg->reg); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMAC_RSP_MDIO_READ(cmd, data) \
-	MC_RSP_OP(cmd, 0, 16, 16, uint16_t, data)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  8,  uint8_t,  cfg->phy_addr); \
-	MC_CMD_OP(cmd, 0, 8,  8,  uint8_t,  cfg->reg); \
-	MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \
-do { \
-	MC_RSP_OP(cmd, 0, 0,  64, uint64_t, cfg->options); \
-	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, cfg->rate); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  64, uint64_t, cfg->options); \
-	MC_CMD_OP(cmd, 1, 0,  32, uint32_t, cfg->rate); \
-	MC_CMD_OP(cmd, 2, 0,  1,  int,      cfg->up); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMAC_CMD_GET_COUNTER(cmd, type) \
-	MC_CMD_OP(cmd, 1, 0,  64, enum dpmac_counter, type)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPMAC_RSP_GET_COUNTER(cmd, counter) \
-	MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter)
+/* Macros for accessing command fields smaller than 1byte */
+#define DPMAC_MASK(field)        \
+	GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \
+		DPMAC_##field##_SHIFT)
+#define dpmac_set_field(var, field, val) \
+	((var) |= (((val) << DPMAC_##field##_SHIFT) & DPMAC_MASK(field)))
+#define dpmac_get_field(var, field)      \
+	(((var) & DPMAC_MASK(field)) >> DPMAC_##field##_SHIFT)
+
+#pragma pack(push, 1)
+struct dpmac_cmd_open {
+	__le32 dpmac_id;
+};
+
+struct dpmac_cmd_create {
+	__le32 mac_id;
+};
+
+struct dpmac_cmd_destroy {
+	__le32 dpmac_id;
+};
+
+#define DPMAC_STATE_SIZE		1
+#define DPMAC_STATE_SHIFT		0
+#define DPMAC_STATE_VALID_SIZE		1
+#define DPMAC_STATE_VALID_SHIFT		1
+
+struct dpmac_cmd_set_link_state {
+	__le64 options;
+	__le32 rate;
+	__le32 pad;
+	/* only least significant bit is valid */
+	u8 up;
+	u8 pad0[7];
+	__le64 supported;
+	__le64 advertising;
+};
+
+struct dpmac_cmd_get_counter {
+	u8 type;
+};
+
+struct dpmac_rsp_get_counter {
+	__le64 pad;
+	__le64 counter;
+};
+
+#pragma pack(pop)
 
 /* Data Path MAC API
  * Contains initialization APIs and runtime control APIs for DPMAC
@@ -96,42 +81,27 @@ do { \
 
 struct fsl_mc_io;
 
-/**
- * dpmac_open() - Open a control session for the specified object.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @dpmac_id:	DPMAC unique ID
- * @token:	Returned token; use in subsequent API calls
- *
- * This function can be used to open a control session for an
- * already created object; an object may have been declared in
- * the DPL or by calling the dpmac_create function.
- * This function returns a unique authentication token,
- * associated with the specific object ID and the specific MC
- * portal; this token must be used in all subsequent commands for
- * this specific object
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpmac_open(struct fsl_mc_io	*mc_io,
-	       uint32_t		cmd_flags,
-	       int			dpmac_id,
-	       uint16_t		*token);
+int dpmac_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpmac_id, u16 *token);
+
+int dpmac_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
 /**
- * dpmac_close() - Close the control session of the object
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPMAC object
- *
- * After this function is called, no further operations are
- * allowed on the object without opening a new control session.
- *
- * Return:	'0' on Success; Error code otherwise.
+ * struct dpmac_cfg - Structure representing DPMAC configuration
+ * @mac_id:	Represents the Hardware MAC ID; in case of multiple WRIOP,
+ *		the MAC IDs are continuous.
+ *		For example:  2 WRIOPs, 16 MACs in each:
+ *				MAC IDs for the 1st WRIOP: 1-16,
+ *				MAC IDs for the 2nd WRIOP: 17-32.
  */
-int dpmac_close(struct fsl_mc_io	*mc_io,
-		uint32_t		cmd_flags,
-		uint16_t		token);
+struct dpmac_cfg {
+	int mac_id;
+};
+
+int dpmac_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		 const struct dpmac_cfg *cfg, u32 *obj_id);
+
+int dpmac_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		  u32 object_id);
 
 /**
  * enum dpmac_link_type -  DPMAC link type
@@ -171,60 +141,6 @@ enum dpmac_eth_if {
 	DPMAC_ETH_IF_XFI
 };
 
-/**
- * struct dpmac_cfg - Structure representing DPMAC configuration
- * @mac_id:	Represents the Hardware MAC ID; in case of multiple WRIOP,
- *		the MAC IDs are continuous.
- *		For example:  2 WRIOPs, 16 MACs in each:
- *				MAC IDs for the 1st WRIOP: 1-16,
- *				MAC IDs for the 2nd WRIOP: 17-32.
- */
-struct dpmac_cfg {
-	int mac_id;
-};
-
-/**
- * dpmac_create() - Create the DPMAC object.
- * @mc_io:	Pointer to MC portal's I/O object
- * @token:	Authentication token.
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @cfg:	Configuration structure
- * @obj_id:	Returned obj_id; use in subsequent API calls
- *
- * Create the DPMAC object, allocate required resources and
- * perform required initialization.
- *
- * The object can be created either by declaring it in the
- * DPL file, or by calling this function.
- * This function returns a unique authentication token,
- * associated with the specific object ID and the specific MC
- * portal; this token must be used in all subsequent calls to
- * this specific object. For objects that are created using the
- * DPL file, call dpmac_open function to get an authentication
- * token first.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpmac_create(struct fsl_mc_io	*mc_io,
-		 uint16_t		token,
-		 uint32_t		cmd_flags,
-		 const struct dpmac_cfg	*cfg,
-		 uint32_t		*obj_id);
-
-/**
- * dpmac_destroy() - Destroy the DPMAC object and release all its resources.
- * @mc_io:	Pointer to MC portal's I/O object
- * @token:	Authentication token.
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @obj_id:	DPMAC object id
- *
- * Return:	'0' on Success; error code otherwise.
- */
-int dpmac_destroy(struct fsl_mc_io	*mc_io,
-		  uint16_t		token,
-		  uint32_t		cmd_flags,
-		  uint32_t		obj_id);
-
 /* DPMAC IRQ Index and Events */
 
 /* IRQ index */
@@ -248,65 +164,9 @@ struct dpmac_attr {
 	int			phy_id;
 	enum dpmac_link_type	link_type;
 	enum dpmac_eth_if	eth_if;
-	uint32_t		max_rate;
+	u32		max_rate;
 };
 
-/**
- * dpmac_get_attributes - Retrieve DPMAC attributes.
- *
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPMAC object
- * @attr:	Returned object's attributes
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpmac_get_attributes(struct fsl_mc_io	*mc_io,
-			 uint32_t		cmd_flags,
-			 uint16_t		token,
-			 struct dpmac_attr	*attr);
-
-/**
- * struct dpmac_mdio_cfg - DPMAC MDIO read/write parameters
- * @phy_addr: MDIO device address
- * @reg: Address of the register within the Clause 45 PHY device from which data
- *	is to be read
- * @data: Data read/write from/to MDIO
- */
-struct dpmac_mdio_cfg {
-	uint8_t		phy_addr;
-	uint8_t		reg;
-	uint16_t	data;
-};
-
-/**
- * dpmac_mdio_read() - Perform MDIO read transaction
- * @mc_io:	Pointer to opaque I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPMAC object
- * @cfg:	Structure with MDIO transaction parameters
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpmac_mdio_read(struct fsl_mc_io		*mc_io,
-		    uint32_t			cmd_flags,
-		    uint16_t			token,
-		    struct dpmac_mdio_cfg	*cfg);
-
-/**
- * dpmac_mdio_write() - Perform MDIO write transaction
- * @mc_io:	Pointer to opaque I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPMAC object
- * @cfg:	Structure with MDIO transaction parameters
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpmac_mdio_write(struct fsl_mc_io		*mc_io,
-		     uint32_t			cmd_flags,
-		     uint16_t			token,
-		     struct dpmac_mdio_cfg	*cfg);
-
 /* DPMAC link configuration/state options */
 
 /* Enable auto-negotiation */
@@ -319,55 +179,25 @@ int dpmac_mdio_write(struct fsl_mc_io		*mc_io,
 #define DPMAC_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
 
 /**
- * struct dpmac_link_cfg - Structure representing DPMAC link configuration
- * @rate: Link's rate - in Mbps
- * @options: Enable/Disable DPMAC link cfg features (bitmap)
- */
-struct dpmac_link_cfg {
-	uint32_t rate;
-	uint64_t options;
-};
-
-/**
- * dpmac_get_link_cfg() - Get Ethernet link configuration
- * @mc_io:	Pointer to opaque I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPMAC object
- * @cfg:	Returned structure with the link configuration
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpmac_get_link_cfg(struct fsl_mc_io	*mc_io,
-		       uint32_t		cmd_flags,
-		       uint16_t		token,
-		       struct dpmac_link_cfg	*cfg);
-
-/**
  * struct dpmac_link_state - DPMAC link configuration request
  * @rate: Rate in Mbps
  * @options: Enable/Disable DPMAC link cfg features (bitmap)
  * @up: Link state
+ * @state_valid: Ignore/Update the state of the link
+ * @supported: Speeds capability of the phy (bitmap)
+ * @advertising: Speeds that are advertised for autoneg (bitmap)
  */
 struct dpmac_link_state {
-	uint32_t	rate;
-	uint64_t	options;
-	int		up;
+	u32 rate;
+	u64 options;
+	int up;
+	int state_valid;
+	u64 supported;
+	u64 advertising;
 };
 
-/**
- * dpmac_set_link_state() - Set the Ethernet link status
- * @mc_io:	Pointer to opaque I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPMAC object
- * @link_state:	Link state configuration
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpmac_set_link_state(struct fsl_mc_io		*mc_io,
-			 uint32_t			cmd_flags,
-			 uint16_t			token,
-			 struct dpmac_link_state	*link_state);
-
+int dpmac_set_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			 struct dpmac_link_state *link_state);
 /**
  * enum dpni_counter - DPNI counter types
  * @DPMAC_CNT_ING_FRAME_64: counts 64-octet frame, good or bad.
@@ -412,6 +242,8 @@ int dpmac_set_link_state(struct fsl_mc_io		*mc_io,
  * @DPMAC_CNT_EGR_ERR_FRAME: counts frame transmitted with an error
  * @DPMAC_CNT_ING_GOOD_FRAME: counts frame received without error, including
  *			      pause frames.
+ * @DPMAC_CNT_EGR_GOOD_FRAME: counts frames transmitted without error, including
+ *			      pause frames.
  */
 enum dpmac_counter {
 	DPMAC_CNT_ING_FRAME_64,
@@ -440,37 +272,14 @@ enum dpmac_counter {
 	DPMAC_CNT_EGR_BCAST_FRAME,
 	DPMAC_CNT_EGR_UCAST_FRAME,
 	DPMAC_CNT_EGR_ERR_FRAME,
-	DPMAC_CNT_ING_GOOD_FRAME
+	DPMAC_CNT_ING_GOOD_FRAME,
+	DPMAC_CNT_EGR_GOOD_FRAME,
 };
 
-/**
- * dpmac_get_counter() - Read a specific DPMAC counter
- * @mc_io:	Pointer to opaque I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPMAC object
- * @type:	The requested counter
- * @counter:	Returned counter value
- *
- * Return:	The requested counter; '0' otherwise.
- */
-int dpmac_get_counter(struct fsl_mc_io		*mc_io,
-		      uint32_t			cmd_flags,
-		      uint16_t			token,
-		      enum dpmac_counter	 type,
-		      uint64_t			*counter);
-/**
- * dpmac_get_api_version - Retrieve DPMAC Major and Minor version info.
- *
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @major_ver:	DPMAC major version
- * @minor_ver:	DPMAC minor version
- *
- * Return:     '0' on Success; Error code otherwise.
- */
-int dpmac_get_api_version(struct fsl_mc_io *mc_io,
-			  uint32_t cmd_flags,
-			  uint16_t *major_ver,
-			  uint16_t *minor_ver);
+int dpmac_get_counter(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		      enum dpmac_counter type, u64 *counter);
+
+int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+			  u16 *major_ver, u16 *minor_ver);
 
 #endif /* __FSL_DPMAC_H */
diff --git a/include/fsl-mc/fsl_dpmng.h b/include/fsl-mc/fsl_dpmng.h
index 2148601e8a..5dfc9ecc42 100644
--- a/include/fsl-mc/fsl_dpmng.h
+++ b/include/fsl-mc/fsl_dpmng.h
@@ -30,17 +30,6 @@ struct mc_version {
 	uint32_t revision;
 };
 
-/**
- * mc_get_version() - Retrieves the Management Complex firmware
- *			version information
- * @mc_io:		Pointer to opaque I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @mc_ver_info:	Returned version information structure
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int mc_get_version(struct fsl_mc_io	*mc_io,
-		   uint32_t		cmd_flags,
-		   struct mc_version	*mc_ver_info);
+int mc_get_version(struct fsl_mc_io *mc_io, uint32_t cmd_flags, struct mc_version *mc_ver_info);
 
 #endif /* __FSL_DPMNG_H */
diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h
index e5e7338192..9bc475475d 100644
--- a/include/fsl-mc/fsl_dpni.h
+++ b/include/fsl-mc/fsl_dpni.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2013-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017, 2023 NXP
  */
 #ifndef _FSL_DPNI_H
 #define _FSL_DPNI_H
@@ -24,303 +24,243 @@
 
 #define DPNI_CMDID_SET_POOLS			0x2002
 #define DPNI_CMDID_SET_BUFFER_LAYOUT		0x2651
-#define DPNI_CMDID_GET_BUFFER_LAYOUT		0x2641
-#define DPNI_CMDID_SET_ERRORS_BEHAVIOR		0x20B1
 
 #define DPNI_CMDID_GET_QDID			0x2101
 #define DPNI_CMDID_GET_TX_DATA_OFFSET		0x2121
 #define DPNI_CMDID_GET_LINK_STATE		0x2151
 #define DPNI_CMDID_SET_LINK_CFG			0x21A1
 
-#define DPNI_CMDID_SET_PRIM_MAC			0x2241
-#define DPNI_CMDID_GET_PRIM_MAC			0x2251
 #define DPNI_CMDID_ADD_MAC_ADDR			0x2261
-#define DPNI_CMDID_REMOVE_MAC_ADDR		0x2271
 
 #define DPNI_CMDID_GET_STATISTICS		0x25D1
-#define DPNI_CMDID_RESET_STATISTICS		0x25E1
 #define DPNI_CMDID_GET_QUEUE			0x25F1
 #define DPNI_CMDID_SET_QUEUE			0x2601
 #define DPNI_CMDID_SET_TX_CONFIRMATION_MODE	0x2661
 
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_OPEN(cmd, dpni_id) \
-	MC_CMD_OP(cmd,	 0,	0,	32,	int,	dpni_id)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_PREP_CFG(param, cfg) \
-do { \
-	MC_PREP_OP(param, 0, 0,   32, uint16_t, cfg->adv.options); \
-	MC_PREP_OP(param, 0, 32,   8, uint16_t, cfg->adv.num_queues); \
-	MC_PREP_OP(param, 0, 40,   8, uint16_t, cfg->adv.num_tcs); \
-	MC_PREP_OP(param, 0, 48,   8, uint16_t, cfg->adv.mac_entries); \
-	MC_PREP_OP(param, 1, 0,   8, uint16_t, cfg->adv.vlan_entries); \
-	MC_PREP_OP(param, 1, 16,   8, uint16_t, cfg->adv.qos_entries); \
-	MC_PREP_OP(param, 1, 32,   16, uint16_t, cfg->adv.fs_entries); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_EXT_CFG(param, cfg) \
-do { \
-	MC_EXT_OP(param, 0, 0,   32, uint16_t, cfg->adv.options); \
-	MC_EXT_OP(param, 0, 32,   8, uint16_t, cfg->adv.num_queues); \
-	MC_EXT_OP(param, 0, 40,   8, uint16_t, cfg->adv.num_tcs); \
-	MC_EXT_OP(param, 0, 48,   8, uint16_t, cfg->adv.mac_entries); \
-	MC_EXT_OP(param, 1, 0,   8, uint16_t, cfg->adv.vlan_entries); \
-	MC_EXT_OP(param, 1, 16,   8, uint16_t, cfg->adv.qos_entries); \
-	MC_EXT_OP(param, 1, 32,   16, uint16_t, cfg->adv.fs_entries); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_CREATE(cmd, cfg) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,	32,	uint32_t,  cfg->adv.options); \
-	MC_CMD_OP(cmd, 0, 32,	8,	uint8_t,   cfg->adv.num_queues); \
-	MC_CMD_OP(cmd, 0, 40,	8,	uint8_t,   cfg->adv.num_tcs); \
-	MC_CMD_OP(cmd, 0, 48,	8,	uint8_t,   cfg->adv.mac_entries); \
-	MC_CMD_OP(cmd, 1, 0,	8,	uint8_t,   cfg->adv.vlan_entries); \
-	MC_CMD_OP(cmd, 1, 16,	8,	uint8_t,   cfg->adv.qos_entries); \
-	MC_CMD_OP(cmd, 1, 32,	16,	uint8_t,   cfg->adv.fs_entries); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_SET_POOLS(cmd, cfg) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  8,  uint8_t,  cfg->num_dpbp); \
-	MC_CMD_OP(cmd, 0, 8,  1,  int,      cfg->pools[0].backup_pool); \
-	MC_CMD_OP(cmd, 0, 9,  1,  int,      cfg->pools[1].backup_pool); \
-	MC_CMD_OP(cmd, 0, 10, 1,  int,      cfg->pools[2].backup_pool); \
-	MC_CMD_OP(cmd, 0, 11, 1,  int,      cfg->pools[3].backup_pool); \
-	MC_CMD_OP(cmd, 0, 12, 1,  int,      cfg->pools[4].backup_pool); \
-	MC_CMD_OP(cmd, 0, 13, 1,  int,      cfg->pools[5].backup_pool); \
-	MC_CMD_OP(cmd, 0, 14, 1,  int,      cfg->pools[6].backup_pool); \
-	MC_CMD_OP(cmd, 0, 15, 1,  int,      cfg->pools[7].backup_pool); \
-	MC_CMD_OP(cmd, 0, 32, 32, int,      cfg->pools[0].dpbp_id); \
-	MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\
-	MC_CMD_OP(cmd, 1, 0,  32, int,      cfg->pools[1].dpbp_id); \
-	MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\
-	MC_CMD_OP(cmd, 1, 32, 32, int,      cfg->pools[2].dpbp_id); \
-	MC_CMD_OP(cmd, 5, 0,  16, uint16_t, cfg->pools[2].buffer_size);\
-	MC_CMD_OP(cmd, 2, 0,  32, int,      cfg->pools[3].dpbp_id); \
-	MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\
-	MC_CMD_OP(cmd, 2, 32, 32, int,      cfg->pools[4].dpbp_id); \
-	MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\
-	MC_CMD_OP(cmd, 3, 0,  32, int,      cfg->pools[5].dpbp_id); \
-	MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\
-	MC_CMD_OP(cmd, 3, 32, 32, int,      cfg->pools[6].dpbp_id); \
-	MC_CMD_OP(cmd, 6, 0,  16, uint16_t, cfg->pools[6].buffer_size);\
-	MC_CMD_OP(cmd, 4, 0,  32, int,      cfg->pools[7].dpbp_id); \
-	MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_GET_ATTR(cmd, attr) \
-do { \
-	MC_RSP_OP(cmd, 0, 0,  32, int,	    attr->options);\
-	MC_RSP_OP(cmd, 0, 32,  8,  uint8_t,  attr->max_num_queues); \
-	MC_RSP_OP(cmd, 0, 40,  8,  uint8_t,  attr->max_num_tcs); \
-	MC_RSP_OP(cmd, 0, 48,  8,  uint8_t,  attr->max_mac_entries); \
-	MC_RSP_OP(cmd, 1,  0,  8,  uint8_t,  attr->max_vlan_entries); \
-	MC_RSP_OP(cmd, 1, 16,  8,  uint8_t,  attr->max_qos_entries); \
-	MC_RSP_OP(cmd, 1, 32, 16,  uint16_t,  attr->max_fs_entries); \
-	MC_RSP_OP(cmd, 2,  0,  8,  uint8_t,  attr->max_qos_key_size); \
-	MC_RSP_OP(cmd, 2,  8,  8,  uint8_t,  attr->max_fs_key_size); \
-	MC_RSP_OP(cmd, 2, 16, 16,  uint16_t,  attr->wriop_version); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  32, uint32_t, cfg->errors); \
-	MC_CMD_OP(cmd, 0, 32, 4,  enum dpni_error_action, cfg->error_action); \
-	MC_CMD_OP(cmd, 0, 36, 1,  int,      cfg->set_frame_annotation); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, queue) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  8, enum dpni_queue_type, queue); \
-	MC_CMD_OP(cmd, 1, 0,  16, uint16_t, layout->private_data_size); \
-	MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_align); \
-	MC_CMD_OP(cmd, 0, 32, 16, uint16_t, layout->options); \
-	MC_CMD_OP(cmd, 0, 48,  1,  int,	    layout->pass_timestamp); \
-	MC_CMD_OP(cmd, 0, 49,  1,  int,	    layout->pass_parser_result); \
-	MC_CMD_OP(cmd, 0, 50,  1,  int,	    layout->pass_frame_status); \
-	MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_head_room); \
-	MC_CMD_OP(cmd, 1, 48, 16, uint16_t, layout->data_tail_room); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_GET_QDID(cmd, qdid) \
-	MC_RSP_OP(cmd, 0, 0,  16, uint16_t, qdid)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_GET_TX_DATA_OFFSET(cmd, data_offset) \
-	MC_RSP_OP(cmd, 0, 0,  16, uint16_t, data_offset)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \
-do { \
-	MC_CMD_OP(cmd, 1, 0,  32, uint32_t, cfg->rate);\
-	MC_CMD_OP(cmd, 2, 0,  64, uint64_t, cfg->options);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_GET_LINK_STATE(cmd, state) \
-do { \
-	MC_RSP_OP(cmd, 0, 32,  1, int,      state->up);\
-	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, state->rate);\
-	MC_RSP_OP(cmd, 2, 0,  64, uint64_t, state->options);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \
-do { \
-	MC_CMD_OP(cmd, 0, 16, 8,  uint8_t,  mac_addr[5]); \
-	MC_CMD_OP(cmd, 0, 24, 8,  uint8_t,  mac_addr[4]); \
-	MC_CMD_OP(cmd, 0, 32, 8,  uint8_t,  mac_addr[3]); \
-	MC_CMD_OP(cmd, 0, 40, 8,  uint8_t,  mac_addr[2]); \
-	MC_CMD_OP(cmd, 0, 48, 8,  uint8_t,  mac_addr[1]); \
-	MC_CMD_OP(cmd, 0, 56, 8,  uint8_t,  mac_addr[0]); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr) \
-do { \
-	MC_RSP_OP(cmd, 0, 16, 8,  uint8_t,  mac_addr[5]); \
-	MC_RSP_OP(cmd, 0, 24, 8,  uint8_t,  mac_addr[4]); \
-	MC_RSP_OP(cmd, 0, 32, 8,  uint8_t,  mac_addr[3]); \
-	MC_RSP_OP(cmd, 0, 40, 8,  uint8_t,  mac_addr[2]); \
-	MC_RSP_OP(cmd, 0, 48, 8,  uint8_t,  mac_addr[1]); \
-	MC_RSP_OP(cmd, 0, 56, 8,  uint8_t,  mac_addr[0]); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr) \
-do { \
-	MC_CMD_OP(cmd, 0, 16, 8,  uint8_t,  mac_addr[5]); \
-	MC_CMD_OP(cmd, 0, 24, 8,  uint8_t,  mac_addr[4]); \
-	MC_CMD_OP(cmd, 0, 32, 8,  uint8_t,  mac_addr[3]); \
-	MC_CMD_OP(cmd, 0, 40, 8,  uint8_t,  mac_addr[2]); \
-	MC_CMD_OP(cmd, 0, 48, 8,  uint8_t,  mac_addr[1]); \
-	MC_CMD_OP(cmd, 0, 56, 8,  uint8_t,  mac_addr[0]); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr) \
-do { \
-	MC_CMD_OP(cmd, 0, 16, 8,  uint8_t,  mac_addr[5]); \
-	MC_CMD_OP(cmd, 0, 24, 8,  uint8_t,  mac_addr[4]); \
-	MC_CMD_OP(cmd, 0, 32, 8,  uint8_t,  mac_addr[3]); \
-	MC_CMD_OP(cmd, 0, 40, 8,  uint8_t,  mac_addr[2]); \
-	MC_CMD_OP(cmd, 0, 48, 8,  uint8_t,  mac_addr[1]); \
-	MC_CMD_OP(cmd, 0, 56, 8,  uint8_t,  mac_addr[0]); \
-} while (0)
-
-#define DPNI_CMD_GET_QUEUE(cmd, type, tc, index) \
-do { \
-	MC_CMD_OP(cmd, 0,  0,  8, enum dpni_queue_type, type); \
-	MC_CMD_OP(cmd, 0,  8,  8, uint8_t, tc); \
-	MC_CMD_OP(cmd, 0, 16,  8, uint8_t, index); \
-} while (0)
-
-#define DPNI_RSP_GET_QUEUE(cmd, queue) \
-do { \
-	MC_RSP_OP(cmd, 1,  0, 32, uint32_t, (queue)->destination.id); \
-	MC_RSP_OP(cmd, 1, 56,  4, enum dpni_dest, (queue)->destination.type); \
-	MC_RSP_OP(cmd, 1, 62,  1, char, (queue)->destination.stash_ctrl); \
-	MC_RSP_OP(cmd, 1, 63,  1, char, (queue)->destination.hold_active); \
-	MC_RSP_OP(cmd, 2,  0, 64, uint64_t, (queue)->flc); \
-	MC_RSP_OP(cmd, 3,  0, 64, uint64_t, (queue)->user_context); \
-	MC_RSP_OP(cmd, 4,  0, 32, uint32_t, (queue)->fqid); \
-	MC_RSP_OP(cmd, 4, 32, 16, uint16_t, (queue)->qdbin); \
-} while (0)
-
-#define DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue) \
-do { \
-	MC_CMD_OP(cmd, 0,  0,  8, enum dpni_queue_type, type); \
-	MC_CMD_OP(cmd, 0,  8,  8, uint8_t, tc); \
-	MC_CMD_OP(cmd, 0, 16,  8, uint8_t, index); \
-	MC_CMD_OP(cmd, 0, 24,  8, uint8_t, (queue)->options); \
-	MC_CMD_OP(cmd, 1,  0, 32, uint32_t, (queue)->destination.id); \
-	MC_CMD_OP(cmd, 1, 56,  4, enum dpni_dest, (queue)->destination.type); \
-	MC_CMD_OP(cmd, 1, 62,  1, char, (queue)->destination.stash_ctrl); \
-	MC_CMD_OP(cmd, 1, 63,  1, char, (queue)->destination.hold_active); \
-	MC_CMD_OP(cmd, 1,  0, 32, uint32_t, (queue)->destination.id); \
-	MC_CMD_OP(cmd, 2,  0, 64, uint64_t, (queue)->flc); \
-	MC_CMD_OP(cmd, 3,  0, 64, uint64_t, (queue)->user_context); \
-} while (0)
-
-/*			cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_GET_STATISTICS(cmd, page) \
-	MC_CMD_OP(cmd, 0, 0, 8, uint8_t, page)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_GET_STATISTICS(cmd, stat) \
-do { \
-	MC_RSP_OP(cmd, 0, 0, 64, uint64_t, (stat)->counter0); \
-	MC_RSP_OP(cmd, 1, 0, 64, uint64_t, (stat)->counter1); \
-	MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (stat)->counter2); \
-	MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (stat)->counter3); \
-	MC_RSP_OP(cmd, 4, 0, 64, uint64_t, (stat)->counter4); \
-	MC_RSP_OP(cmd, 5, 0, 64, uint64_t, (stat)->counter5); \
-	MC_RSP_OP(cmd, 6, 0, 64, uint64_t, (stat)->counter6); \
-} while (0)
-
-enum net_prot {
-	NET_PROT_NONE = 0,
-	NET_PROT_PAYLOAD,
-	NET_PROT_ETH,
-	NET_PROT_VLAN,
-	NET_PROT_IPV4,
-	NET_PROT_IPV6,
-	NET_PROT_IP,
-	NET_PROT_TCP,
-	NET_PROT_UDP,
-	NET_PROT_UDP_LITE,
-	NET_PROT_IPHC,
-	NET_PROT_SCTP,
-	NET_PROT_SCTP_CHUNK_DATA,
-	NET_PROT_PPPOE,
-	NET_PROT_PPP,
-	NET_PROT_PPPMUX,
-	NET_PROT_PPPMUX_SUBFRM,
-	NET_PROT_L2TPV2,
-	NET_PROT_L2TPV3_CTRL,
-	NET_PROT_L2TPV3_SESS,
-	NET_PROT_LLC,
-	NET_PROT_LLC_SNAP,
-	NET_PROT_NLPID,
-	NET_PROT_SNAP,
-	NET_PROT_MPLS,
-	NET_PROT_IPSEC_AH,
-	NET_PROT_IPSEC_ESP,
-	NET_PROT_UDP_ENC_ESP, /* RFC 3948 */
-	NET_PROT_MACSEC,
-	NET_PROT_GRE,
-	NET_PROT_MINENCAP,
-	NET_PROT_DCCP,
-	NET_PROT_ICMP,
-	NET_PROT_IGMP,
-	NET_PROT_ARP,
-	NET_PROT_CAPWAP_DATA,
-	NET_PROT_CAPWAP_CTRL,
-	NET_PROT_RFC2684,
-	NET_PROT_ICMPV6,
-	NET_PROT_FCOE,
-	NET_PROT_FIP,
-	NET_PROT_ISCSI,
-	NET_PROT_GTP,
-	NET_PROT_USER_DEFINED_L2,
-	NET_PROT_USER_DEFINED_L3,
-	NET_PROT_USER_DEFINED_L4,
-	NET_PROT_USER_DEFINED_L5,
-	NET_PROT_USER_DEFINED_SHIM1,
-	NET_PROT_USER_DEFINED_SHIM2,
-
-	NET_PROT_DUMMY_LAST
+/* Macros for accessing command fields smaller than 1byte */
+#define DPNI_MASK(field)	\
+	GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \
+		DPNI_##field##_SHIFT)
+#define dpni_set_field(var, field, val)	\
+	((var) |= (((val) << DPNI_##field##_SHIFT) & DPNI_MASK(field)))
+#define dpni_get_field(var, field)	\
+	(((var) & DPNI_MASK(field)) >> DPNI_##field##_SHIFT)
+
+#pragma pack(push, 1)
+struct dpni_cmd_open {
+	__le32 dpni_id;
 };
 
+struct dpni_cmd_create {
+	__le32 options;
+	u8 num_queues;
+	u8 num_tcs;
+	u8 mac_filter_entries;
+	u8 num_channels;
+	u8 vlan_filter_entries;
+	u8 pad2;
+	u8 qos_entries;
+	u8 pad3;
+	__le16 fs_entries;
+	u8 num_rx_tcs;
+	u8 pad4;
+	u8  num_cgs;
+	__le16 num_opr;
+	u8 dist_key_size;
+};
+
+struct dpni_cmd_destroy {
+	__le32 dpni_id;
+};
+
+#define DPNI_BACKUP_POOL(val, order)	(((val) & 0x1) << (order))
+
+struct dpni_cmd_pool {
+	__le16 dpbp_id;
+	u8 priority_mask;
+	u8 pad;
+};
+
+struct dpni_cmd_set_pools {
+	u8 num_dpbp;
+	u8 backup_pool_mask;
+	u8 pad;
+	u8 pool_options;
+	struct dpni_cmd_pool pool[8];
+	__le16 buffer_size[8];
+};
+
+struct dpni_rsp_get_attr {
+	/* response word 0 */
+	__le32 options;
+	u8 num_queues;
+	u8 num_rx_tcs;
+	u8 mac_filter_entries;
+	u8 num_tx_tcs;
+	/* response word 1 */
+	u8 vlan_filter_entries;
+	u8 num_channels;
+	u8 qos_entries;
+	u8 pad2;
+	__le16 fs_entries;
+	__le16 num_opr;
+	/* response word 2 */
+	u8 qos_key_size;
+	u8 fs_key_size;
+	__le16 wriop_version;
+	u8 num_cgs;
+};
+
+/* There are 3 separate commands for configuring Rx, Tx and Tx confirmation
+ * buffer layouts, but they all share the same parameters.
+ * If one of the functions changes, below structure needs to be split.
+ */
+
+#define DPNI_PASS_TS_SHIFT		0
+#define DPNI_PASS_TS_SIZE		1
+#define DPNI_PASS_PR_SHIFT		1
+#define DPNI_PASS_PR_SIZE		1
+#define DPNI_PASS_FS_SHIFT		2
+#define DPNI_PASS_FS_SIZE		1
+#define DPNI_PASS_SWO_SHIFT		3
+#define DPNI_PASS_SWO_SIZE		1
+
+struct dpni_cmd_set_buffer_layout {
+	/* cmd word 0 */
+	u8 qtype;
+	u8 pad0[3];
+	__le16 options;
+	/* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */
+	u8 flags;
+	u8 pad1;
+	/* cmd word 1 */
+	__le16 private_data_size;
+	__le16 data_align;
+	__le16 head_room;
+	__le16 tail_room;
+};
+
+struct dpni_cmd_get_qdid {
+	u8 qtype;
+};
+
+struct dpni_rsp_get_qdid {
+	__le16 qdid;
+};
+
+struct dpni_rsp_get_tx_data_offset {
+	__le16 data_offset;
+};
+
+struct dpni_cmd_set_link_cfg {
+	__le64 pad0;
+	__le32 rate;
+	__le32 pad1;
+	__le64 options;
+	__le64 advertising;
+};
+
+#define DPNI_LINK_STATE_SHIFT		0
+#define DPNI_LINK_STATE_SIZE		1
+#define DPNI_STATE_VALID_SHIFT		1
+#define DPNI_STATE_VALID_SIZE		1
+
+struct dpni_rsp_get_link_state {
+	__le32 pad0;
+	/* from LSB: up:1 */
+	u8 flags;
+	u8 pad1[3];
+	__le32 rate;
+	__le32 pad2;
+	__le64 options;
+	__le64 supported;
+	__le64 advertising;
+};
+
+struct dpni_cmd_add_mac_addr {
+	u8 flags;
+	u8 pad;
+	u8 mac_addr[6];
+	u8 tc_id;
+	u8 fq_id;
+};
+
+struct dpni_cmd_get_queue {
+	u8 qtype;
+	u8 tc;
+	u8 index;
+	u8 channel_id;
+};
+
+#define DPNI_DEST_TYPE_SHIFT		0
+#define DPNI_DEST_TYPE_SIZE		4
+#define DPNI_CGID_VALID_SHIFT		5
+#define DPNI_CGID_VALID_SIZE		1
+#define DPNI_STASH_CTRL_SHIFT		6
+#define DPNI_STASH_CTRL_SIZE		1
+#define DPNI_HOLD_ACTIVE_SHIFT		7
+#define DPNI_HOLD_ACTIVE_SIZE		1
+
+struct dpni_rsp_get_queue {
+	/* response word 0 */
+	__le64 pad0;
+	/* response word 1 */
+	__le32 dest_id;
+	__le16 pad1;
+	u8 dest_prio;
+	/* From LSB: dest_type:4, pad:1, cgid_valid:1, flc_stash_ctrl:1, hold_active:1 */
+	u8 flags;
+	/* response word 2 */
+	__le64 flc;
+	/* response word 3 */
+	__le64 user_context;
+	/* response word 4 */
+	__le32 fqid;
+	__le16 qdbin;
+	__le16 pad2;
+	/* response word 5*/
+	u8 cgid;
+};
+
+struct dpni_cmd_set_queue {
+	/* cmd word 0 */
+	u8 qtype;
+	u8 tc;
+	u8 index;
+	u8 options;
+	__le32 pad0;
+	/* cmd word 1 */
+	__le32 dest_id;
+	__le16 pad1;
+	u8 dest_prio;
+	u8 flags;
+	/* cmd word 2 */
+	__le64 flc;
+	/* cmd word 3 */
+	__le64 user_context;
+	/* cmd word 4 */
+	u8 cgid;
+	u8 channel_id;
+};
+
+struct dpni_tx_confirmation_mode {
+	u8 ceetm_ch_idx;
+	u8 pad1;
+	__le16 pad2;
+	u8 confirmation_mode;
+};
+
+struct dpni_cmd_get_statistics {
+	u8 page_number;
+	__le16 param;
+};
+
+struct dpni_rsp_get_statistics {
+	__le64 counter[7];
+};
+
+#pragma pack(pop)
+
 /**
  * Data Path Network Interface API
  * Contains initialization APIs and runtime control APIs for DPNI
@@ -336,50 +276,17 @@ struct fsl_mc_io;
 #define DPNI_MAX_DPBP				8
 
 /* All traffic classes considered; see dpni_set_rx_flow() */
-#define DPNI_ALL_TCS				(uint8_t)(-1)
+#define DPNI_ALL_TCS				(u8)(-1)
 /* All flows within traffic class considered; see dpni_set_rx_flow() */
-#define DPNI_ALL_TC_FLOWS			(uint16_t)(-1)
+#define DPNI_ALL_TC_FLOWS			(u16)(-1)
 /* Generate new flow ID; see dpni_set_tx_flow() */
-#define DPNI_NEW_FLOW_ID			(uint16_t)(-1)
+#define DPNI_NEW_FLOW_ID			(u16)(-1)
 /* use for common tx-conf queue; see dpni_set_tx_conf_<x>() */
-#define DPNI_COMMON_TX_CONF			(uint16_t)(-1)
+#define DPNI_COMMON_TX_CONF			(u16)(-1)
 
-/**
- * dpni_open() - Open a control session for the specified object
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @dpni_id:	DPNI unique ID
- * @token:	Returned token; use in subsequent API calls
- *
- * This function can be used to open a control session for an
- * already created object; an object may have been declared in
- * the DPL or by calling the dpni_create() function.
- * This function returns a unique authentication token,
- * associated with the specific object ID and the specific MC
- * portal; this token must be used in all subsequent commands for
- * this specific object.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_open(struct fsl_mc_io	*mc_io,
-	      uint32_t		cmd_flags,
-	      int		dpni_id,
-	      uint16_t		*token);
+int dpni_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpni_id, u16 *token);
 
-/**
- * dpni_close() - Close the control session of the object
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- *
- * After this function is called, no further operations are
- * allowed on the object without opening a new control session.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_close(struct fsl_mc_io	*mc_io,
-	       uint32_t		cmd_flags,
-	       uint16_t		token);
+int dpni_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
 /* DPNI configuration options */
 
@@ -442,57 +349,84 @@ enum dpni_queue_type {
 	DPNI_QUEUE_RX_ERR,
 };
 
-struct dpni_cfg {
-		uint8_t mac_addr[6];
-	struct {
-		uint32_t		options;
-		uint16_t		fs_entries;
-		uint8_t			num_queues;
-		uint8_t			num_tcs;
-		uint8_t			mac_entries;
-		uint8_t			vlan_entries;
-		uint8_t			qos_entries;
-	} adv;
-};
-
 /**
- * struct dpni_extended_cfg - Structure representing extended DPNI configuration
- * @tc_cfg: TCs configuration
- * @ipr_cfg: IP reassembly configuration
+ * struct dpni_cfg - Structure representing DPNI configuration
+ * @options: Any combination of the following options:
+ *		DPNI_OPT_TX_FRM_RELEASE
+ *		DPNI_OPT_NO_MAC_FILTER
+ *		DPNI_OPT_HAS_POLICING
+ *		DPNI_OPT_SHARED_CONGESTION
+ *		DPNI_OPT_HAS_KEY_MASKING
+ *		DPNI_OPT_NO_FS
+ *		DPNI_OPT_SINGLE_SENDER
+ *		DPNI_OPT_STASHING_DIS
+ * @fs_entries: Number of entries in the flow steering table.
+ *		This table is used to select the ingress queue for
+ *		ingress traffic, targeting a GPP core or another.
+ *		In addition it can be used to discard traffic that
+ *		matches the set rule. It is either an exact match table
+ *		or a TCAM table, depending on DPNI_OPT_ HAS_KEY_MASKING
+ *		bit in OPTIONS field. This field is ignored if
+ *		DPNI_OPT_NO_FS bit is set in OPTIONS field. Otherwise,
+ *		value 0 defaults to 64. Maximum supported value is 1024.
+ *		Note that the total number of entries is limited on the
+ *		SoC to as low as 512 entries if TCAM is used.
+ * @vlan_filter_entries: Number of entries in the VLAN address filtering
+ *		table. This is an exact match table used to filter
+ *		ingress traffic based on VLAN IDs. Value 0 disables VLAN
+ *		filtering. Maximum supported value is 16.
+ * @mac_filter_entries: Number of entries in the MAC address filtering
+ *		table. This is an exact match table and allows both
+ *		unicast and multicast entries. The primary MAC address
+ *		of the network interface is not part of this table,
+ *		this contains only entries in addition to it. This
+ *		field is ignored if DPNI_OPT_ NO_MAC_FILTER is set in
+ *		OPTIONS field. Otherwise, value 0 defaults to 80.
+ *		Maximum supported value is 80.
+ * @num_queues: Number of Tx and Rx queues used for traffic
+ *		distribution. This is orthogonal to QoS and is only
+ *		used to distribute traffic to multiple GPP cores.
+ *		This configuration affects the number of Tx queues
+ *		(logical FQs, all associated with a single CEETM queue),
+ *		Rx queues and Tx confirmation queues, if applicable.
+ *		Value 0 defaults to one queue. Maximum supported value
+ *		is 8.
+ * @num_tcs: Number of traffic classes (TCs), reserved for the DPNI.
+ *		TCs can have different priority levels for the purpose
+ *		of Tx scheduling (see DPNI_SET_TX_PRIORITIES), different
+ *		BPs (DPNI_ SET_POOLS), policers. There are dedicated QM
+ *		queues for traffic classes (including class queues on
+ *		Tx). Value 0 defaults to one TC. Maximum supported value
+ *		is 16. There are maximum 16 TCs for Tx and 8 TCs for Rx.
+ *		When num_tcs>8 Tx will use this value but Rx will have
+ *		only 8 traffic classes.
+ * @num_rx_tcs: if set to other value than zero represents number
+ *		of TCs used for Rx. Maximum value is 8. If set to zero the
+ *		number of Rx TCs will be initialized with the value provided
+ *		in num_tcs parameter.
+ * @qos_entries: Number of entries in the QoS classification table. This
+ *		table is used to select the TC for ingress traffic. It
+ *		is either an exact match or a TCAM table, depending on
+ *		DPNI_OPT_ HAS_KEY_MASKING bit in OPTIONS field. This
+ *		field is ignored if the DPNI has a single TC. Otherwise,
+ *		a value of 0 defaults to 64. Maximum supported value
+ *		is 64.
+ * @num_channels: Number of egress channels used by this dpni object. If
+ *		set to zero the dpni object will use a single CEETM channel.
  */
-struct dpni_extended_cfg {
-	/**
-	 * struct tc_cfg - TC configuration
-	 * @max_dist: Maximum distribution size for Rx traffic class;
-	 *	supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96,
-	 *	112,128,192,224,256,384,448,512,768,896,1024;
-	 *	value '0' will be treated as '1'.
-	 *	other unsupported values will be round down to the nearest
-	 *	supported value.
-	 * @max_fs_entries: Maximum FS entries for Rx traffic class;
-	 *	'0' means no support for this TC;
-	 */
-	struct {
-		uint16_t	max_dist;
-		uint16_t	max_fs_entries;
-	} tc_cfg[DPNI_MAX_TC];
-	/**
-	 * struct ipr_cfg - Structure representing IP reassembly configuration
-	 * @max_reass_frm_size: Maximum size of the reassembled frame
-	 * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments
-	 * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments
-	 * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly
-	 *		process
-	 * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly
-	 *		process
-	 */
-	struct {
-		uint16_t max_reass_frm_size;
-		uint16_t min_frag_size_ipv4;
-		uint16_t min_frag_size_ipv6;
-		uint16_t max_open_frames_ipv4;
-		uint16_t max_open_frames_ipv6;
-	} ipr_cfg;
+struct dpni_cfg {
+	u32 options;
+	u16 fs_entries;
+	u8  vlan_filter_entries;
+	u8  mac_filter_entries;
+	u8  num_queues;
+	u8  num_tcs;
+	u8  num_rx_tcs;
+	u8  qos_entries;
+	u8  num_cgs;
+	u16 num_opr;
+	u8  dist_key_size;
+	u8  num_channels;
 };
 
 /**
@@ -503,249 +437,108 @@ struct dpni_extended_cfg {
  * This function has to be called before dpni_create()
  */
 int dpni_prepare_cfg(const struct dpni_cfg	*cfg,
-		     uint8_t			*cfg_buf);
-/**
- * dpni_create() - Create the DPNI object
- * @mc_io:	Pointer to MC portal's I/O object
- * @token:	Authentication token.
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @cfg:	Configuration structure
- * @obj_id:	Returned obj_id; use in subsequent API calls
- *
- * Create the DPNI object, allocate required resources and
- * perform required initialization.
- *
- * The object can be created either by declaring it in the
- * DPL file, or by calling this function.
- *
- * This function returns a unique authentication token,
- * associated with the specific object ID and the specific MC
- * portal; this token must be used in all subsequent calls to
- * this specific object. For objects that are created using the
- * DPL file, call dpni_open() function to get an authentication
- * token first.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_create(struct fsl_mc_io	*mc_io,
-		uint16_t		token,
-		uint32_t		cmd_flags,
-		const struct dpni_cfg	*cfg,
-		uint32_t		*obj_id);
+		     u8			*cfg_buf);
 
-/**
- * dpni_destroy() - Destroy the DPNI object and release all its resources.
- * @mc_io:	Pointer to MC portal's I/O object
- * @token:	Authentication token.
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @obj_id:	Returned obj_id; use in subsequent API calls
- *
- * Return:	'0' on Success; error code otherwise.
- */
-int dpni_destroy(struct fsl_mc_io	*mc_io,
-		 uint16_t		token,
-		 uint32_t		cmd_flags,
-		 uint32_t		obj_id);
+int dpni_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		const struct dpni_cfg *cfg, u32 *obj_id);
+
+int dpni_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
+		 u32 object_id);
 
 /**
  * struct dpni_pools_cfg - Structure representing buffer pools configuration
- * @num_dpbp: Number of DPBPs
- * @pools: Array of buffer pools parameters; The number of valid entries
- *	must match 'num_dpbp' value
+ * @num_dpbp:	Number of DPBPs
+ * @pool_options: Buffer assignment options
+ *                This field is a combination of DPNI_POOL_ASSOC_flags
+ * @pools:	Array of buffer pools parameters; The number of valid entries
+ *		must match 'num_dpbp' value
+ * @pools.dpbp_id:     DPBP object ID
+ * @pools.priority:    Priority mask that indicates TC's used with this buffer.
+ *		       I set to 0x00 MC will assume value 0xff.
+ * @pools.buffer_size: Buffer size
+ * @pools.backup_pool: Backup pool
  */
+
+#define DPNI_POOL_ASSOC_QPRI	0
+#define DPNI_POOL_ASSOC_QDBIN	1
+
 struct dpni_pools_cfg {
-	uint8_t num_dpbp;
-	/**
-	 * struct pools - Buffer pools parameters
-	 * @dpbp_id: DPBP object ID
-	 * @buffer_size: Buffer size
-	 * @backup_pool: Backup pool
-	 */
+	u8 num_dpbp;
+	u8 pool_options;
 	struct {
 		int		dpbp_id;
-		uint16_t	buffer_size;
+		u8		priority_mask;
+		u16	buffer_size;
 		int		backup_pool;
 	} pools[DPNI_MAX_DPBP];
 };
 
-/**
- * dpni_set_pools() - Set buffer pools configuration
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @cfg:	Buffer pools configuration
- *
- * mandatory for DPNI operation
- * warning:Allowed only when DPNI is disabled
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_set_pools(struct fsl_mc_io		*mc_io,
-		   uint32_t			cmd_flags,
-		   uint16_t			token,
-		   const struct dpni_pools_cfg	*cfg);
+int dpni_set_pools(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		   const struct dpni_pools_cfg *cfg);
 
-/**
- * dpni_enable() - Enable the DPNI, allow sending and receiving frames.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:		Token of DPNI object
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_enable(struct fsl_mc_io	*mc_io,
-		uint32_t		cmd_flags,
-		uint16_t		token);
+int dpni_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
-/**
- * dpni_disable() - Disable the DPNI, stop sending and receiving frames.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_disable(struct fsl_mc_io	*mc_io,
-		 uint32_t		cmd_flags,
-		 uint16_t		token);
+int dpni_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
-
-/**
- * dpni_reset() - Reset the DPNI, returns the object to initial state.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_reset(struct fsl_mc_io	*mc_io,
-	       uint32_t		cmd_flags,
-	       uint16_t		token);
+int dpni_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
 /**
  * struct dpni_attr - Structure representing DPNI attributes
- * @options: Mask of available options; reflects the value as was given in
- *		object's creation
- * @max_num_queues: Number of queues available (for both Tx and Rx)
- * @max_num_tcs: Maximum number of traffic classes (for both Tx and Rx)
- * @max_mac_entries: Maximum number of traffic classes (for both Tx and Rx)
- * @max_unicast_filters: Maximum number of unicast filters
- * @max_multicast_filters: Maximum number of multicast filters
- * @max_vlan_entries: Maximum number of VLAN filters
- * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in QoS table
- * @max_fs_entries: declares the maximum entries in flow steering table
- * @max_qos_key_size: Maximum key size for the QoS look-up
- * @max_fs_key_size: Maximum key size for the flow steering
- * @wriop_version: Indicates revision of WRIOP hardware block
+ * @options: Any combination of the following options:
+ *		DPNI_OPT_TX_FRM_RELEASE
+ *		DPNI_OPT_NO_MAC_FILTER
+ *		DPNI_OPT_HAS_POLICING
+ *		DPNI_OPT_SHARED_CONGESTION
+ *		DPNI_OPT_HAS_KEY_MASKING
+ *		DPNI_OPT_NO_FS
+ *		DPNI_OPT_STASHING_DIS
+ * @num_queues: Number of Tx and Rx queues used for traffic distribution.
+ * @num_rx_tcs: Number of RX traffic classes (TCs), reserved for the DPNI.
+ * @num_tx_tcs: Number of TX traffic classes (TCs), reserved for the DPNI.
+ * @mac_filter_entries: Number of entries in the MAC address filtering
+ *		table.
+ * @vlan_filter_entries: Number of entries in the VLAN address filtering
+ *		table.
+ * @qos_entries: Number of entries in the QoS classification table.
+ * @fs_entries: Number of entries in the flow steering table.
+ * @qos_key_size: Size, in bytes, of the QoS look-up key. Defining a key larger
+ *			than this when adding QoS entries will result
+ *			in an error.
+ * @fs_key_size: Size, in bytes, of the flow steering look-up key. Defining a
+ *			key larger than this when composing the hash + FS key
+ *			will result in an error.
+ * @wriop_version: Version of WRIOP HW block.
+ *			The 3 version values are stored on 6, 5, 5 bits
+ *			respectively.
+ *			Values returned:
+ *			- 0x400 - WRIOP version 1.0.0, used on LS2080 and
+ *			variants,
+ *			- 0x421 - WRIOP version 1.1.1, used on LS2088 and
+ *			variants,
+ *			- 0x422 - WRIOP version 1.1.2, used on LS1088 and
+ *			variants.
+ *			- 0xC00 - WRIOP version 3.0.0, used on LX2160 and
+ *			variants.
  */
 struct dpni_attr {
-	uint32_t id;
-	uint32_t options;
-	uint8_t max_num_queues;
-	uint8_t max_num_tcs;
-	uint8_t max_mac_entries;
-	uint8_t max_vlan_entries;
-	uint8_t max_qos_entries;
-	uint16_t max_fs_entries;
-	uint8_t max_qos_key_size;
-	uint8_t max_fs_key_size;
-	uint16_t wriop_version;
-};
-
-/**
- * dpni_get_attributes() - Retrieve DPNI attributes.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @attr:	Object's attributes
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_get_attributes(struct fsl_mc_io	*mc_io,
-			uint32_t		cmd_flags,
-			uint16_t		token,
-			struct dpni_attr	*attr);
-
-/**
- * dpni_extract_cfg() - extract the parameters
- * @cfg: cfg structure
- * @cfg_buf: 256 bytes of DMA-able memory
- *
- * This function has to be called after dpni_get_attributes()
- */
-int dpni_extract_cfg(struct dpni_cfg	*cfg,
-		     const uint8_t	*cfg_buf);
-
-/**
- * DPNI errors
- */
-
-/**
- * Extract out of frame header error
- */
-#define DPNI_ERROR_EOFHE	0x00020000
-/**
- * Frame length error
- */
-#define DPNI_ERROR_FLE		0x00002000
-/**
- * Frame physical error
- */
-#define DPNI_ERROR_FPE		0x00001000
-/**
- * Parsing header error
- */
-#define DPNI_ERROR_PHE		0x00000020
-/**
- * Parser L3 checksum error
- */
-#define DPNI_ERROR_L3CE		0x00000004
-/**
- * Parser L3 checksum error
- */
-#define DPNI_ERROR_L4CE		0x00000001
-
-/**
- * enum dpni_error_action - Defines DPNI behavior for errors
- * @DPNI_ERROR_ACTION_DISCARD: Discard the frame
- * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow
- * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue
- */
-enum dpni_error_action {
-	DPNI_ERROR_ACTION_DISCARD = 0,
-	DPNI_ERROR_ACTION_CONTINUE = 1,
-	DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2
+	u32 options;
+	u8  num_queues;
+	u8  num_rx_tcs;
+	u8  num_tx_tcs;
+	u8  mac_filter_entries;
+	u8  vlan_filter_entries;
+	u8  qos_entries;
+	u16 fs_entries;
+	u16 num_opr;
+	u8  qos_key_size;
+	u8  fs_key_size;
+	u16 wriop_version;
+	u8  num_cgs;
+	u8  num_channels;
 };
 
-/**
- * struct dpni_error_cfg - Structure representing DPNI errors treatment
- * @errors: Errors mask; use 'DPNI_ERROR__<X>
- * @error_action: The desired action for the errors mask
- * @set_frame_annotation: Set to '1' to mark the errors in frame annotation
- *		status (FAS); relevant only for the non-discard action
- */
-struct dpni_error_cfg {
-	uint32_t		errors;
-	enum dpni_error_action	error_action;
-	int			set_frame_annotation;
-};
-
-/**
- * dpni_set_errors_behavior() - Set errors behavior
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @cfg:	Errors configuration
- *
- * this function may be called numerous times with different
- * error masks
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_set_errors_behavior(struct fsl_mc_io		*mc_io,
-			     uint32_t			cmd_flags,
-			     uint16_t			token,
-			     struct dpni_error_cfg	*cfg);
+int dpni_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			struct dpni_attr *attr);
 
 /* DPNI buffer layout modification options */
 
@@ -763,93 +556,45 @@ int dpni_set_errors_behavior(struct fsl_mc_io		*mc_io,
 #define DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM	0x00000020
 /*!< Select to modify the data-tail-room setting */
 #define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM	0x00000040
+/* Select to modify the sw-opaque value setting */
+#define DPNI_BUF_LAYOUT_OPT_SW_OPAQUE		0x00000080
+/* Select to disable Scatter Gather and use single buffer */
+#define DPNI_BUF_LAYOUT_OPT_NO_SG		0x00000100
 
 /**
  * struct dpni_buffer_layout - Structure representing DPNI buffer layout
- * @options: Flags representing the suggested modifications to the buffer
- *		layout; Use any combination of 'DPNI_BUF_LAYOUT_OPT_<X>' flags
- * @pass_timestamp: Pass timestamp value
- * @pass_parser_result: Pass parser results
- * @pass_frame_status: Pass frame status
- * @private_data_size: Size kept for private data (in bytes)
- * @data_align: Data alignment
- * @data_head_room: Data head room
- * @data_tail_room: Data tail room
+ * @options:		Flags representing the suggested modifications to the
+ *			buffer layout;
+ *			Use any combination of 'DPNI_BUF_LAYOUT_OPT_<X>' flags
+ * @pass_timestamp:	Pass timestamp value
+ * @pass_parser_result:	Pass parser results
+ * @pass_frame_status:	Pass frame status
+ * @private_data_size:	Size kept for private data (in bytes)
+ * @data_align:		Data alignment
+ * @data_head_room:	Data head room
+ * @data_tail_room:	Data tail room
  */
 struct dpni_buffer_layout {
-	uint16_t options;
+	u32 options;
 	int pass_timestamp;
 	int pass_parser_result;
 	int pass_frame_status;
-	uint16_t private_data_size;
-	uint16_t data_align;
-	uint16_t data_head_room;
-	uint16_t data_tail_room;
+	int pass_sw_opaque;
+	u16 private_data_size;
+	u16 data_align;
+	u16 data_head_room;
+	u16 data_tail_room;
 };
 
-/**
- * dpni_get_buffer_layout() - Retrieve buffer layout attributes.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @layout:	Returns buffer layout attributes
- * @type:	DPNI queue type
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_get_buffer_layout(struct fsl_mc_io			*mc_io,
-			   uint32_t				cmd_flags,
-			   uint16_t				token,
-			   const struct dpni_buffer_layout	*layout,
-			   enum dpni_queue_type			type);
-
-/**
- * dpni_set_buffer_layout() - Set buffer layout configuration.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @layout:	Buffer layout configuration
- * @type:	DPNI queue type
- *
- * Return:	'0' on Success; Error code otherwise.
- *
- * @warning	Allowed only when DPNI is disabled
- */
-int dpni_set_buffer_layout(struct fsl_mc_io			*mc_io,
-			   uint32_t				cmd_flags,
-			   uint16_t				token,
-			   const struct dpni_buffer_layout	*layout,
-			   enum dpni_queue_type			type);
+int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			   enum dpni_queue_type qtype,
+			   const struct dpni_buffer_layout *layout);
 
-/**
- * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used
- *			for enqueue operations
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @qdid:	Returned virtual QDID value that should be used as an argument
- *			in all enqueue operations
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_get_qdid(struct fsl_mc_io	*mc_io,
-		  uint32_t		cmd_flags,
-		  uint16_t		token,
-		  uint16_t		*qdid);
+int dpni_get_qdid(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		  enum dpni_queue_type qtype, u16 *qdid);
 
-/**
- * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer)
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @data_offset: Tx data offset (from start of buffer)
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_get_tx_data_offset(struct fsl_mc_io	*mc_io,
-			    uint32_t		cmd_flags,
-			    uint16_t		token,
-			    uint16_t		*data_offset);
+int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			    u16 *data_offset);
 
 /* Enable auto-negotiation */
 #define DPNI_LINK_OPT_AUTONEG		0x0000000000000001ULL
@@ -864,107 +609,44 @@ int dpni_get_tx_data_offset(struct fsl_mc_io	*mc_io,
  * struct - Structure representing DPNI link configuration
  * @rate: Rate
  * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values
+ * @advertising: Speeds that are advertised for autoneg (bitmap)
  */
 struct dpni_link_cfg {
-	uint32_t rate;
-	uint64_t options;
+	u32 rate;
+	u64 options;
+	u64 advertising;
 };
 
-/**
- * dpni_set_link_cfg() - set the link configuration.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @cfg:	Link configuration
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_set_link_cfg(struct fsl_mc_io			*mc_io,
-		      uint32_t				cmd_flags,
-		      uint16_t				token,
-		      const struct dpni_link_cfg	*cfg);
+int dpni_set_link_cfg(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		      const struct dpni_link_cfg *cfg);
 
 /**
  * struct dpni_link_state - Structure representing DPNI link state
- * @rate: Rate
- * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values
- * @up: Link state; '0' for down, '1' for up
+ * @rate:	Rate
+ * @options:	Mask of available options; use 'DPNI_LINK_OPT_<X>' values
+ * @up:		Link state; '0' for down, '1' for up
+ * @state_valid: Ignore/Update the state of the link
+ * @supported: Speeds capability of the phy (bitmap)
+ * @advertising: Speeds that are advertised for autoneg (bitmap)
  */
 struct dpni_link_state {
-	uint32_t rate;
-	uint64_t options;
+	u32 rate;
+	u64 options;
 	int up;
+	int     state_valid;
+	u64 supported;
+	u64 advertising;
 };
 
-/**
- * dpni_get_link_state() - Return the link state (either up or down)
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @state:	Returned link state;
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_get_link_state(struct fsl_mc_io	*mc_io,
-			uint32_t		cmd_flags,
-			uint16_t		token,
-			struct dpni_link_state	*state);
+int dpni_get_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			struct dpni_link_state *state);
 
-/**
- * dpni_set_primary_mac_addr() - Set the primary MAC address
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @mac_addr:	MAC address to set as primary address
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io,
-			      uint32_t		cmd_flags,
-			      uint16_t		token,
-			      const uint8_t	mac_addr[6]);
-
-/**
- * dpni_get_primary_mac_addr() - Get the primary MAC address
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @mac_addr:	Returned MAC address
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_get_primary_mac_addr(struct fsl_mc_io	*mc_io,
-			      uint32_t		cmd_flags,
-			      uint16_t		token,
-			      uint8_t		mac_addr[6]);
+int dpni_add_mac_addr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		      const u8 mac_addr[6], u8 flags,
+		      u8 tc_id, u8 flow_id);
 
-/**
- * dpni_add_mac_addr() - Add MAC address filter
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @mac_addr:	MAC address to add
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_add_mac_addr(struct fsl_mc_io	*mc_io,
-		      uint32_t		cmd_flags,
-		      uint16_t		token,
-		      const uint8_t	mac_addr[6]);
-
-/**
- * dpni_remove_mac_addr() - Remove MAC address filter
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @mac_addr:	MAC address to remove
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_remove_mac_addr(struct fsl_mc_io	*mc_io,
-			 uint32_t		cmd_flags,
-			 uint16_t		token,
-			 const uint8_t		mac_addr[6]);
+int dpni_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+			 u16 *major_ver, u16 *minor_ver);
 
 /**
  * enum dpni_dest - DPNI destination types
@@ -985,137 +667,6 @@ enum dpni_dest {
 	DPNI_DEST_DPCON = 2
 };
 
-/**
- * struct dpni_dest_cfg - Structure representing DPNI destination parameters
- * @dest_type: Destination type
- * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type
- * @priority: Priority selection within the DPIO or DPCON channel; valid values
- *		are 0-1 or 0-7, depending on the number of priorities in that
- *		channel; not relevant for 'DPNI_DEST_NONE' option
- */
-struct dpni_dest_cfg {
-	enum dpni_dest dest_type;
-	int dest_id;
-	uint8_t priority;
-};
-
-/**
- * enum dpni_flc_type - DPNI FLC types
- * @DPNI_FLC_USER_DEFINED: select the FLC to be used for user defined value
- * @DPNI_FLC_STASH: select the FLC to be used for stash control
- */
-enum dpni_flc_type {
-	DPNI_FLC_USER_DEFINED = 0,
-	DPNI_FLC_STASH = 1,
-};
-
-/**
- * enum dpni_stash_size - DPNI FLC stashing size
- * @DPNI_STASH_SIZE_0B: no stash
- * @DPNI_STASH_SIZE_64B: stashes 64 bytes
- * @DPNI_STASH_SIZE_128B: stashes 128 bytes
- * @DPNI_STASH_SIZE_192B: stashes 192 bytes
- */
-enum dpni_stash_size {
-	DPNI_STASH_SIZE_0B = 0,
-	DPNI_STASH_SIZE_64B = 1,
-	DPNI_STASH_SIZE_128B = 2,
-	DPNI_STASH_SIZE_192B = 3,
-};
-
-/* DPNI FLC stash options */
-
-/* stashes the whole annotation area (up to 192 bytes) */
-#define DPNI_FLC_STASH_FRAME_ANNOTATION	0x00000001
-
-/**
- * struct dpni_flc_cfg - Structure representing DPNI FLC configuration
- * @flc_type: FLC type
- * @options: Mask of available options;
- *	use 'DPNI_FLC_STASH_<X>' values
- * @frame_data_size: Size of frame data to be stashed
- * @flow_context_size: Size of flow context to be stashed
- * @flow_context: 1. In case flc_type is 'DPNI_FLC_USER_DEFINED':
- *			this value will be provided in the frame descriptor
- *			(FD[FLC])
- *		  2. In case flc_type is 'DPNI_FLC_STASH':
- *			this value will be I/O virtual address of the
- *			flow-context;
- *			Must be cacheline-aligned and DMA-able memory
- */
-struct dpni_flc_cfg {
-	enum dpni_flc_type flc_type;
-	uint32_t options;
-	enum dpni_stash_size frame_data_size;
-	enum dpni_stash_size flow_context_size;
-	uint64_t flow_context;
-};
-
-/* DPNI queue modification options */
-
-/* Select to modify the user's context associated with the queue */
-#define DPNI_QUEUE_OPT_USER_CTX		0x00000001
-/* Select to modify the queue's destination */
-#define DPNI_QUEUE_OPT_DEST		0x00000002
-/** Select to modify the flow-context parameters;
- * not applicable for Tx-conf/Err queues as the FD comes from the user
- */
-#define DPNI_QUEUE_OPT_FLC		0x00000004
-/* Select to modify the queue's order preservation */
-#define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008
-/* Select to modify the queue's tail-drop threshold */
-#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010
-
-/**
- * struct dpni_queue_cfg - Structure representing queue configuration
- * @options: Flags representing the suggested modifications to the queue;
- *		Use any combination of 'DPNI_QUEUE_OPT_<X>' flags
- * @user_ctx: User context value provided in the frame descriptor of each
- *		dequeued frame; valid only if 'DPNI_QUEUE_OPT_USER_CTX'
- *		is contained in 'options'
- * @dest_cfg: Queue destination parameters;
- *		valid only if 'DPNI_QUEUE_OPT_DEST' is contained in 'options'
- * @flc_cfg: Flow context configuration; in case the TC's distribution
- *		is either NONE or HASH the FLC's settings of flow#0 are used.
- *		in the case of FS (flow-steering) the flow's FLC settings
- *		are used.
- *		valid only if 'DPNI_QUEUE_OPT_FLC' is contained in 'options'
- * @order_preservation_en: enable/disable order preservation;
- *		valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained
- *		in 'options'
- * @tail_drop_threshold: set the queue's tail drop threshold in bytes;
- *		'0' value disable the threshold; maximum value is 0xE000000;
- *		valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained
- *		in 'options'
- */
-struct dpni_queue_cfg {
-	uint32_t options;
-	uint64_t user_ctx;
-	struct dpni_dest_cfg dest_cfg;
-	struct dpni_flc_cfg flc_cfg;
-	int order_preservation_en;
-	uint32_t tail_drop_threshold;
-};
-
-/**
- * struct dpni_queue_attr - Structure representing queue attributes
- * @user_ctx: User context value provided in the frame descriptor of each
- *	dequeued frame
- * @dest_cfg: Queue destination configuration
- * @flc_cfg: Flow context configuration
- * @order_preservation_en: enable/disable order preservation
- * @tail_drop_threshold: queue's tail drop threshold in bytes;
- * @fqid: Virtual fqid value to be used for dequeue operations
- */
-struct dpni_queue_attr {
-	uint64_t user_ctx;
-	struct dpni_dest_cfg dest_cfg;
-	struct dpni_flc_cfg flc_cfg;
-	int order_preservation_en;
-	uint32_t tail_drop_threshold;
-	uint32_t fqid;
-};
-
 /* DPNI Tx flow modification options */
 
 /* Select to modify the settings for dedicate Tx confirmation/error */
@@ -1126,21 +677,6 @@ struct dpni_queue_attr {
 #define DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN	0x00000020
 
 /**
- * dpni_get_api_version - Retrieve DPNI Major and Minor version info.
- *
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @major_ver:	DPNI major version
- * @minor_ver:	DPNI minor version
- *
- * Return:     '0' on Success; Error code otherwise.
- */
-int dpni_get_api_version(struct fsl_mc_io *mc_io,
-			 u32 cmd_flags,
-			 u16 *major_ver,
-			 u16 *minor_ver);
-
-/**
  * enum dpni_confirmation_mode - Defines DPNI options supported for Tx
  * confirmation
  * @DPNI_CONF_AFFINE: For each Tx queue set associated with a sender there is
@@ -1149,7 +685,7 @@ int dpni_get_api_version(struct fsl_mc_io *mc_io,
  * confirmation queue
  * @DPNI_CONF_DISABLE: Tx frames are not confirmed.  This must be associated
  * with proper FD set-up to have buffers release to a Buffer Pool, otherwise
- * buffers will be leaked.
+ * buffers will be leaked
  */
 enum dpni_confirmation_mode {
 	DPNI_CONF_AFFINE,
@@ -1157,168 +693,194 @@ enum dpni_confirmation_mode {
 	DPNI_CONF_DISABLE,
 };
 
-struct dpni_tx_confirmation_mode {
-	uint32_t pad;
-	uint8_t confirmation_mode;
-};
+/**
+ * stashes the whole annotation area (up to 192 bytes)
+ */
+#define DPNI_FLC_STASH_FRAME_ANNOTATION	0x00000001
 
 /**
  * struct dpni_queue - Queue structure
- * @fqid:  FQID used for enqueueing to and/or configuration of this specific FQ
- * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI. Only relevant
- *         for Tx queues.
- * @flc:   FLC value for traffic dequeued from this queue.
- * @user_context:    User data, presented to the user along with any frames
- *                   from this queue. Not relevant for Tx queues.
+ * @destination - Destination structure
+ * @destination.id:	ID of the destination, only relevant if DEST_TYPE is > 0.
+ *	Identifies either a DPIO or a DPCON object.
+ *	Not relevant for Tx queues.
+ * @destination.type:	May be one of the following:
+ *	0 - No destination, queue can be manually
+ *		queried, but will not push traffic or
+ *		notifications to a DPIO;
+ *	1 - The destination is a DPIO. When traffic
+ *		becomes available in the queue a FQDAN
+ *		(FQ data available notification) will be
+ *		generated to selected DPIO;
+ *	2 - The destination is a DPCON. The queue is
+ *		associated with a DPCON object for the
+ *		purpose of scheduling between multiple
+ *		queues. The DPCON may be independently
+ *		configured to generate notifications.
+ *		Not relevant for Tx queues.
+ * @destination.hold_active: Hold active, maintains a queue scheduled for longer
+ *	in a DPIO during dequeue to reduce spread of traffic.
+ *	Only relevant if queues are
+ *	not affined to a single DPIO.
+ * @user_context: User data, presented to the user along with any frames
+ *	from this queue. Not relevant for Tx queues.
+ * @flc: FD FLow Context structure
+ * @flc.value: Default FLC value for traffic dequeued from
+ *      this queue.  Please check description of FD
+ *      structure for more information.
+ *      Note that FLC values set using dpni_add_fs_entry,
+ *      if any, take precedence over values per queue.
+ * @flc.stash_control: Boolean, indicates whether the 6 lowest
+ *      - significant bits are used for stash control.
+ *      significant bits are used for stash control.  If set, the 6
+ *      least significant bits in value are interpreted as follows:
+ *      - bits 0-1: indicates the number of 64 byte units of context
+ *      that are stashed.  FLC value is interpreted as a memory address
+ *      in this case, excluding the 6 LS bits.
+ *      - bits 2-3: indicates the number of 64 byte units of frame
+ *      annotation to be stashed.  Annotation is placed at FD[ADDR].
+ *      - bits 4-5: indicates the number of 64 byte units of frame
+ *      data to be stashed.  Frame data is placed at FD[ADDR] +
+ *      FD[OFFSET].
+ *      For more details check the Frame Descriptor section in the
+ *      hardware documentation.
+ *@cgid :indicate the cgid to set relative to dpni
  */
 struct dpni_queue {
-	/**
-	* struct destination - Destination structure
-	* @id:   ID of the destination, only relevant if DEST_TYPE is > 0.
-	*        Identifies either a DPIO or a DPCON object. Not relevant for Tx
-	*        queues.
-	* @type: May be one of the following:
-	*         0 - No destination, queue can be manually queried, but won't
-	*             push traffic or notifications to a DPIO;
-	*         1 - The destination is DPIO. When traffic becomes available in
-	*             the queue a FQDAN (FQ data available notification) will be
-	*             generated to selected DPIO;
-	*         2 - The destination is a DPCON. The queue is associated with a
-	*             DPCON object for purpose of scheduling between multiple
-	*             queues. The DPCON may be independently configured to
-	*             generate notifications. Not relevant for Tx queues.
-	* @hold_active: Hold active
-	*/
 	struct {
-		uint32_t id;
+		u16 id;
 		enum dpni_dest type;
 		char hold_active;
-		char stash_ctrl;
+		u8 priority;
 	} destination;
-	uint8_t  options;
-	uint32_t fqid;
-	uint16_t qdbin;
-	uint64_t flc;
-	uint64_t user_context;
+	u64 user_context;
+	struct {
+		u64 value;
+		char stash_control;
+	} flc;
+	int cgid;
 };
 
 /**
- * dpni_set_queue() - Set queue parameters
- * @mc_io:      Pointer to MC portal's I/O object
- * @cmd_flags:  Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:      Token of DPNI object
- * @type:       Type of queue
- * @tc:         Traffic class, in range 0 to NUM_TCS - 1
- * @index:      Selects the specific queue out of the set allocated for the same
- *              TC. Value must be in range 0 to NUM_QUEUES - 1
- * @queue:      Queue structure
- *
- * Return:     '0' on Success; Error code otherwise.
- */
-int dpni_set_queue(struct fsl_mc_io		*mc_io,
-		   uint32_t			cmd_flags,
-		   uint16_t			token,
-		   enum dpni_queue_type		type,
-		   uint8_t			tc,
-		   uint8_t			index,
-		   const struct dpni_queue	*queue);
-
-/**
- * dpni_get_queue() - Get queue parameters
- * @mc_io:      Pointer to MC portal's I/O object
- * @cmd_flags:  Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:      Token of DPNI object
- * @type:       Type of queue
- * @tc:         Traffic class, in range 0 to NUM_TCS - 1
- * @index:      Selects the specific queue out of the set allocated for the same
- *              TC. Value must be in range 0 to NUM_QUEUES - 1
- * @queue:      Queue structure
- *
- * Return:      '0' on Success; Error code otherwise.
+ * struct dpni_queue_id - Queue identification, used for enqueue commands
+ *				or queue control
+ * @fqid:	FQID used for enqueueing to and/or configuration of this
+ *			specific FQ
+ * @qdbin:	Queueing bin, used to enqueue using QDID, DQBIN, QPRI.
+ *			Only relevant for Tx queues.
  */
-int dpni_get_queue(struct fsl_mc_io		*mc_io,
-		   uint32_t			cmd_flags,
-		   uint16_t			token,
-		   enum dpni_queue_type		type,
-		   uint8_t			tc,
-		   uint8_t			index,
-		   struct dpni_queue		*queue);
-
-/**
- * dpni_set_tx_confirmation_mode() - Set TX conf mode
- * @mc_io:      Pointer to MC portal's I/O object
- * @cmd_flags:  Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:      Token of DPNI object
- * @mode:       DPNI confirmation mode type
- *
- * Return:      '0' on Success; Error code otherwise.
- */
-int dpni_set_tx_confirmation_mode(struct fsl_mc_io	*mc_io,
-				  uint32_t		cmd_flags,
-				  uint16_t		token,
-				  enum dpni_confirmation_mode mode);
-struct dpni_statistics {
-	/**
-	 * Page_0 statistics structure
-	 * @ingress_all_frames: Ingress frame count
-	 * @ingress_all_bytes: Ingress byte count
-	 * @ingress_multicast_frames: Ingress multicast frame count
-	 * @ingress_multicast_bytes: Ingress multicast byte count
-	 * @ingress_broadcast_frames: Ingress broadcast frame count
-	 * @ingress_broadcast_bytes: Ingress broadcast byte count
-	 *
-	 * Page_1 statistics structure
-	 * @egress_all_frames: Egress frame count
-	 * @egress_all_bytes: Egress byte count
-	 * @egress_multicast_frames: Egress multicast frame count
-	 * @egress_multicast_bytes: Egress multicast byte count
-	 * @egress_broadcast_frames: Egress broadcast frame count
-	 * @egress_broadcast_bytes: Egress broadcast byte count
-	 *
-	 * Page_2 statistics structure
-	 * @ingress_filtered_frames: Ingress filtered frame count
-	 * @ingress_discarded_frames: Ingress discarded frame count
-	 * @ingress_nobuffer_discards: Ingress discarded frame count due to
-	 *  lack of buffers.
-	 * @egress_discarded_frames: Egress discarded frame count
-	 * @egress_confirmed_frames: Egress confirmed frame count
-	 */
-
-	uint64_t counter0;
-	uint64_t counter1;
-	uint64_t counter2;
-	uint64_t counter3;
-	uint64_t counter4;
-	uint64_t counter5;
-	uint64_t counter6;
+struct dpni_queue_id {
+	u32 fqid;
+	u16 qdbin;
 };
 
-/**
- * dpni_get_statistics() - Get DPNI statistics
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- * @page:	Selects the statistics page to retrieve, see DPNI_GET_STATISTICS
- *		output. Pages are numbered 0 to 2.
- * @stat:	Structure containing the statistics
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_get_statistics(struct fsl_mc_io *mc_io,
-			uint32_t cmd_flags,
-			uint16_t token,
-			uint8_t page,
-			struct dpni_statistics *stat);
+int dpni_set_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		   enum dpni_queue_type qtype, u16 param, u8 index,
+		   u8 options, const struct dpni_queue *queue);
+
+int dpni_get_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		   enum dpni_queue_type qtype, u16 param, u8 index,
+		   struct dpni_queue *queue, struct dpni_queue_id *qid);
+
+int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+				  u8 ceetm_ch_idx, enum dpni_confirmation_mode mode);
+
+#define DPNI_STATISTICS_CNT		7
+
+/**
+ * union dpni_statistics - Union describing the DPNI statistics
+ * @page_0: Page_0 statistics structure
+ * @page_0.ingress_all_frames: Ingress frame count
+ * @page_0.ingress_all_bytes: Ingress byte count
+ * @page_0.ingress_multicast_frames: Ingress multicast frame count
+ * @page_0.ingress_multicast_bytes: Ingress multicast byte count
+ * @page_0.ingress_broadcast_frames: Ingress broadcast frame count
+ * @page_0.ingress_broadcast_bytes: Ingress broadcast byte count
+ * @page_1: Page_1 statistics structure
+ * @page_1.egress_all_frames: Egress frame count
+ * @page_1.egress_all_bytes: Egress byte count
+ * @page_1.egress_multicast_frames: Egress multicast frame count
+ * @page_1.egress_multicast_bytes: Egress multicast byte count
+ * @page_1.egress_broadcast_frames: Egress broadcast frame count
+ * @page_1.egress_broadcast_bytes: Egress broadcast byte count
+ * @page_2: Page_2 statistics structure
+ * @page_2.ingress_filtered_frames: Ingress filtered frame count
+ * @page_2.ingress_discarded_frames: Ingress discarded frame count
+ * @page_2.ingress_nobuffer_discards: Ingress discarded frame count due to
+ *	lack of buffers
+ * @page_2.egress_discarded_frames: Egress discarded frame count
+ * @page_2.egress_confirmed_frames: Egress confirmed frame count
+ * @page_3: Page_3 statistics structure
+ * @page_3.egress_dequeue_bytes: Cumulative count of the number of bytes
+ *	dequeued from egress FQs
+ * @page_3.egress_dequeue_frames: Cumulative count of the number of frames
+ *	dequeued from egress FQs
+ * @page_3.egress_reject_bytes: Cumulative count of the number of bytes in
+ *	egress frames whose enqueue was rejected
+ * @page_3.egress_reject_frames: Cumulative count of the number of egress
+ *	frames whose enqueue was rejected
+ * @page_4: Page_4 statistics structure: congestion points
+ * @page_4.cgr_reject_frames: number of rejected frames due to congestion point
+ * @page_4.cgr_reject_bytes: number of rejected bytes due to congestion point
+ * @page_5: Page_5 statistics structure: policer
+ * @page_5.policer_cnt_red: NUmber of red colored frames
+ * @page_5.policer_cnt_yellow: number of yellow colored frames
+ * @page_5.policer_cnt_green: number of green colored frames
+ * @page_5.policer_cnt_re_red: number of recolored red frames
+ * @page_5.policer_cnt_re_yellow: number of recolored yellow frames
+ * @page_6: Page_6 statistics structure
+ * @page_6.tx_pending_frames: total number of frames pending in egress FQs
+ * @raw: raw statistics structure, used to index counters
+ */
+union dpni_statistics {
+	struct {
+		u64 ingress_all_frames;
+		u64 ingress_all_bytes;
+		u64 ingress_multicast_frames;
+		u64 ingress_multicast_bytes;
+		u64 ingress_broadcast_frames;
+		u64 ingress_broadcast_bytes;
+	} page_0;
+	struct {
+		u64 egress_all_frames;
+		u64 egress_all_bytes;
+		u64 egress_multicast_frames;
+		u64 egress_multicast_bytes;
+		u64 egress_broadcast_frames;
+		u64 egress_broadcast_bytes;
+	} page_1;
+	struct {
+		u64 ingress_filtered_frames;
+		u64 ingress_discarded_frames;
+		u64 ingress_nobuffer_discards;
+		u64 egress_discarded_frames;
+		u64 egress_confirmed_frames;
+	} page_2;
+	struct {
+		u64 egress_dequeue_bytes;
+		u64 egress_dequeue_frames;
+		u64 egress_reject_bytes;
+		u64 egress_reject_frames;
+	} page_3;
+	struct {
+		u64 cgr_reject_frames;
+		u64 cgr_reject_bytes;
+	} page_4;
+	struct {
+		u64 policer_cnt_red;
+		u64 policer_cnt_yellow;
+		u64 policer_cnt_green;
+		u64 policer_cnt_re_red;
+		u64 policer_cnt_re_yellow;
+	} page_5;
+	struct {
+		u64 tx_pending_frames;
+	} page_6;
+	struct {
+		u64 counter[DPNI_STATISTICS_CNT];
+	} raw;
+};
 
-/**
- * dpni_reset_statistics() - Clears DPNI statistics
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPNI object
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpni_reset_statistics(struct fsl_mc_io *mc_io,
-			  uint32_t cmd_flags,
-			  uint16_t token);
+int dpni_get_statistics(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			u8 page, u16 param, union dpni_statistics *stat);
 #endif /* _FSL_DPNI_H */
diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h
index 950ecb0756..fb95ac544a 100644
--- a/include/fsl-mc/fsl_dprc.h
+++ b/include/fsl-mc/fsl_dprc.h
@@ -3,7 +3,7 @@
  * Freescale Layerscape MC I/O wrapper
  *
  * Copyright 2013-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017, 2023 NXP
  */
 #ifndef _FSL_DPRC_H
 #define _FSL_DPRC_H
@@ -15,442 +15,82 @@
 /* Command IDs */
 #define DPRC_CMDID_CLOSE			0x8001
 #define DPRC_CMDID_OPEN				0x8051
-#define DPRC_CMDID_CREATE			0x9051
 
-#define DPRC_CMDID_GET_ATTR			0x0041
-#define DPRC_CMDID_RESET_CONT			0x0051
 #define DPRC_CMDID_GET_API_VERSION              0xa051
 
 #define DPRC_CMDID_CREATE_CONT			0x1511
 #define DPRC_CMDID_DESTROY_CONT			0x1521
 #define DPRC_CMDID_GET_CONT_ID			0x8301
-#define DPRC_CMDID_GET_OBJ_COUNT		0x1591
-#define DPRC_CMDID_GET_OBJ			0x15A1
-#define DPRC_CMDID_GET_RES_COUNT		0x15B1
-#define DPRC_CMDID_GET_RES_IDS			0x15C1
-#define DPRC_CMDID_GET_OBJ_REG			0x15E1
 
 #define DPRC_CMDID_CONNECT			0x1671
 #define DPRC_CMDID_DISCONNECT			0x1681
 #define DPRC_CMDID_GET_CONNECTION		0x16C1
 
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_RSP_GET_CONTAINER_ID(cmd, container_id) \
-	MC_RSP_OP(cmd, 0, 0,  32,  int,	    container_id)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_OPEN(cmd, container_id) \
-	MC_CMD_OP(cmd, 0, 0,  32, int,	    container_id)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_CREATE_CONTAINER(cmd, cfg) \
-do { \
-	MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \
-	MC_CMD_OP(cmd, 0, 0,  32, uint32_t, cfg->options); \
-	MC_CMD_OP(cmd, 1, 32, 32, int,	    cfg->portal_id); \
-	MC_CMD_OP(cmd, 2, 0,  8,  char,	    cfg->label[0]);\
-	MC_CMD_OP(cmd, 2, 8,  8,  char,	    cfg->label[1]);\
-	MC_CMD_OP(cmd, 2, 16, 8,  char,	    cfg->label[2]);\
-	MC_CMD_OP(cmd, 2, 24, 8,  char,	    cfg->label[3]);\
-	MC_CMD_OP(cmd, 2, 32, 8,  char,	    cfg->label[4]);\
-	MC_CMD_OP(cmd, 2, 40, 8,  char,	    cfg->label[5]);\
-	MC_CMD_OP(cmd, 2, 48, 8,  char,	    cfg->label[6]);\
-	MC_CMD_OP(cmd, 2, 56, 8,  char,	    cfg->label[7]);\
-	MC_CMD_OP(cmd, 3, 0,  8,  char,	    cfg->label[8]);\
-	MC_CMD_OP(cmd, 3, 8,  8,  char,	    cfg->label[9]);\
-	MC_CMD_OP(cmd, 3, 16, 8,  char,	    cfg->label[10]);\
-	MC_CMD_OP(cmd, 3, 24, 8,  char,	    cfg->label[11]);\
-	MC_CMD_OP(cmd, 3, 32, 8,  char,	    cfg->label[12]);\
-	MC_CMD_OP(cmd, 3, 40, 8,  char,	    cfg->label[13]);\
-	MC_CMD_OP(cmd, 3, 48, 8,  char,	    cfg->label[14]);\
-	MC_CMD_OP(cmd, 3, 56, 8,  char,	    cfg->label[15]);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_RSP_CREATE_CONTAINER(cmd, child_container_id, child_portal_offset)\
-do { \
-	MC_RSP_OP(cmd, 1, 0,  32, int,	   child_container_id); \
-	MC_RSP_OP(cmd, 2, 0,  64, uint64_t, child_portal_offset);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id) \
-	MC_CMD_OP(cmd, 0, 0,  32, int,	    child_container_id)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_RESET_CONTAINER(cmd, child_container_id) \
-	MC_CMD_OP(cmd, 0, 0,  32, int,	    child_container_id)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_RSP_GET_ATTRIBUTES(cmd, attr) \
-do { \
-	MC_RSP_OP(cmd, 0, 0,  32, int,	    attr->container_id); \
-	MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->icid); \
-	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, attr->options);\
-	MC_RSP_OP(cmd, 1, 32, 32, int,      attr->portal_id); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_RSP_GET_OBJ_COUNT(cmd, obj_count) \
-	MC_RSP_OP(cmd, 0, 32, 32, int,      obj_count)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_GET_OBJ(cmd, obj_index) \
-	MC_CMD_OP(cmd, 0, 0,  32, int,	    obj_index)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_RSP_GET_OBJ(cmd, obj_desc) \
-do { \
-	MC_RSP_OP(cmd, 0, 32, 32, int,	    obj_desc->id); \
-	MC_RSP_OP(cmd, 1, 0,  16, uint16_t, obj_desc->vendor); \
-	MC_RSP_OP(cmd, 1, 16, 8,  uint8_t,  obj_desc->irq_count); \
-	MC_RSP_OP(cmd, 1, 24, 8,  uint8_t,  obj_desc->region_count); \
-	MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\
-	MC_RSP_OP(cmd, 2, 0,  16, uint16_t, obj_desc->ver_major);\
-	MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\
-	MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \
-	MC_RSP_OP(cmd, 3, 0,  8,  char,	    obj_desc->type[0]);\
-	MC_RSP_OP(cmd, 3, 8,  8,  char,	    obj_desc->type[1]);\
-	MC_RSP_OP(cmd, 3, 16, 8,  char,	    obj_desc->type[2]);\
-	MC_RSP_OP(cmd, 3, 24, 8,  char,	    obj_desc->type[3]);\
-	MC_RSP_OP(cmd, 3, 32, 8,  char,	    obj_desc->type[4]);\
-	MC_RSP_OP(cmd, 3, 40, 8,  char,	    obj_desc->type[5]);\
-	MC_RSP_OP(cmd, 3, 48, 8,  char,	    obj_desc->type[6]);\
-	MC_RSP_OP(cmd, 3, 56, 8,  char,	    obj_desc->type[7]);\
-	MC_RSP_OP(cmd, 4, 0,  8,  char,	    obj_desc->type[8]);\
-	MC_RSP_OP(cmd, 4, 8,  8,  char,	    obj_desc->type[9]);\
-	MC_RSP_OP(cmd, 4, 16, 8,  char,	    obj_desc->type[10]);\
-	MC_RSP_OP(cmd, 4, 24, 8,  char,	    obj_desc->type[11]);\
-	MC_RSP_OP(cmd, 4, 32, 8,  char,	    obj_desc->type[12]);\
-	MC_RSP_OP(cmd, 4, 40, 8,  char,	    obj_desc->type[13]);\
-	MC_RSP_OP(cmd, 4, 48, 8,  char,	    obj_desc->type[14]);\
-	MC_RSP_OP(cmd, 4, 56, 8,  char,	    obj_desc->type[15]);\
-	MC_RSP_OP(cmd, 5, 0,  8,  char,	    obj_desc->label[0]);\
-	MC_RSP_OP(cmd, 5, 8,  8,  char,	    obj_desc->label[1]);\
-	MC_RSP_OP(cmd, 5, 16, 8,  char,	    obj_desc->label[2]);\
-	MC_RSP_OP(cmd, 5, 24, 8,  char,	    obj_desc->label[3]);\
-	MC_RSP_OP(cmd, 5, 32, 8,  char,	    obj_desc->label[4]);\
-	MC_RSP_OP(cmd, 5, 40, 8,  char,	    obj_desc->label[5]);\
-	MC_RSP_OP(cmd, 5, 48, 8,  char,	    obj_desc->label[6]);\
-	MC_RSP_OP(cmd, 5, 56, 8,  char,	    obj_desc->label[7]);\
-	MC_RSP_OP(cmd, 6, 0,  8,  char,	    obj_desc->label[8]);\
-	MC_RSP_OP(cmd, 6, 8,  8,  char,	    obj_desc->label[9]);\
-	MC_RSP_OP(cmd, 6, 16, 8,  char,	    obj_desc->label[10]);\
-	MC_RSP_OP(cmd, 6, 24, 8,  char,	    obj_desc->label[11]);\
-	MC_RSP_OP(cmd, 6, 32, 8,  char,	    obj_desc->label[12]);\
-	MC_RSP_OP(cmd, 6, 40, 8,  char,	    obj_desc->label[13]);\
-	MC_RSP_OP(cmd, 6, 48, 8,  char,	    obj_desc->label[14]);\
-	MC_RSP_OP(cmd, 6, 56, 8,  char,	    obj_desc->label[15]);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_GET_OBJ_DESC(cmd, obj_type, obj_id) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  32, int,	    obj_id);\
-	MC_CMD_OP(cmd, 1, 0,  8,  char,     obj_type[0]);\
-	MC_CMD_OP(cmd, 1, 8,  8,  char,	    obj_type[1]);\
-	MC_CMD_OP(cmd, 1, 16, 8,  char,	    obj_type[2]);\
-	MC_CMD_OP(cmd, 1, 24, 8,  char,	    obj_type[3]);\
-	MC_CMD_OP(cmd, 1, 32, 8,  char,	    obj_type[4]);\
-	MC_CMD_OP(cmd, 1, 40, 8,  char,	    obj_type[5]);\
-	MC_CMD_OP(cmd, 1, 48, 8,  char,	    obj_type[6]);\
-	MC_CMD_OP(cmd, 1, 56, 8,  char,	    obj_type[7]);\
-	MC_CMD_OP(cmd, 2, 0,  8,  char,	    obj_type[8]);\
-	MC_CMD_OP(cmd, 2, 8,  8,  char,	    obj_type[9]);\
-	MC_CMD_OP(cmd, 2, 16, 8,  char,	    obj_type[10]);\
-	MC_CMD_OP(cmd, 2, 24, 8,  char,	    obj_type[11]);\
-	MC_CMD_OP(cmd, 2, 32, 8,  char,	    obj_type[12]);\
-	MC_CMD_OP(cmd, 2, 40, 8,  char,	    obj_type[13]);\
-	MC_CMD_OP(cmd, 2, 48, 8,  char,     obj_type[14]);\
-	MC_CMD_OP(cmd, 2, 56, 8,  char,	    obj_type[15]);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_RSP_GET_OBJ_DESC(cmd, obj_desc) \
-do { \
-	MC_RSP_OP(cmd, 0, 32, 32, int,	    obj_desc->id); \
-	MC_RSP_OP(cmd, 1, 0,  16, uint16_t, obj_desc->vendor); \
-	MC_RSP_OP(cmd, 1, 16, 8,  uint8_t,  obj_desc->irq_count); \
-	MC_RSP_OP(cmd, 1, 24, 8,  uint8_t,  obj_desc->region_count); \
-	MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\
-	MC_RSP_OP(cmd, 2, 0,  16, uint16_t, obj_desc->ver_major);\
-	MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\
-	MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \
-	MC_RSP_OP(cmd, 3, 0,  8,  char,	    obj_desc->type[0]);\
-	MC_RSP_OP(cmd, 3, 8,  8,  char,	    obj_desc->type[1]);\
-	MC_RSP_OP(cmd, 3, 16, 8,  char,	    obj_desc->type[2]);\
-	MC_RSP_OP(cmd, 3, 24, 8,  char,	    obj_desc->type[3]);\
-	MC_RSP_OP(cmd, 3, 32, 8,  char,	    obj_desc->type[4]);\
-	MC_RSP_OP(cmd, 3, 40, 8,  char,	    obj_desc->type[5]);\
-	MC_RSP_OP(cmd, 3, 48, 8,  char,	    obj_desc->type[6]);\
-	MC_RSP_OP(cmd, 3, 56, 8,  char,	    obj_desc->type[7]);\
-	MC_RSP_OP(cmd, 4, 0,  8,  char,	    obj_desc->type[8]);\
-	MC_RSP_OP(cmd, 4, 8,  8,  char,	    obj_desc->type[9]);\
-	MC_RSP_OP(cmd, 4, 16, 8,  char,	    obj_desc->type[10]);\
-	MC_RSP_OP(cmd, 4, 24, 8,  char,	    obj_desc->type[11]);\
-	MC_RSP_OP(cmd, 4, 32, 8,  char,	    obj_desc->type[12]);\
-	MC_RSP_OP(cmd, 4, 40, 8,  char,	    obj_desc->type[13]);\
-	MC_RSP_OP(cmd, 4, 48, 8,  char,	    obj_desc->type[14]);\
-	MC_RSP_OP(cmd, 4, 56, 8,  char,	    obj_desc->type[15]);\
-	MC_RSP_OP(cmd, 5, 0,  8,  char,	    obj_desc->label[0]);\
-	MC_RSP_OP(cmd, 5, 8,  8,  char,	    obj_desc->label[1]);\
-	MC_RSP_OP(cmd, 5, 16, 8,  char,	    obj_desc->label[2]);\
-	MC_RSP_OP(cmd, 5, 24, 8,  char,	    obj_desc->label[3]);\
-	MC_RSP_OP(cmd, 5, 32, 8,  char,	    obj_desc->label[4]);\
-	MC_RSP_OP(cmd, 5, 40, 8,  char,	    obj_desc->label[5]);\
-	MC_RSP_OP(cmd, 5, 48, 8,  char,	    obj_desc->label[6]);\
-	MC_RSP_OP(cmd, 5, 56, 8,  char,	    obj_desc->label[7]);\
-	MC_RSP_OP(cmd, 6, 0,  8,  char,	    obj_desc->label[8]);\
-	MC_RSP_OP(cmd, 6, 8,  8,  char,	    obj_desc->label[9]);\
-	MC_RSP_OP(cmd, 6, 16, 8,  char,	    obj_desc->label[10]);\
-	MC_RSP_OP(cmd, 6, 24, 8,  char,	    obj_desc->label[11]);\
-	MC_RSP_OP(cmd, 6, 32, 8,  char,	    obj_desc->label[12]);\
-	MC_RSP_OP(cmd, 6, 40, 8,  char,	    obj_desc->label[13]);\
-	MC_RSP_OP(cmd, 6, 48, 8,  char,	    obj_desc->label[14]);\
-	MC_RSP_OP(cmd, 6, 56, 8,  char,	    obj_desc->label[15]);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_GET_RES_COUNT(cmd, type) \
-do { \
-	MC_CMD_OP(cmd, 1, 0,  8,  char,	    type[0]);\
-	MC_CMD_OP(cmd, 1, 8,  8,  char,	    type[1]);\
-	MC_CMD_OP(cmd, 1, 16, 8,  char,	    type[2]);\
-	MC_CMD_OP(cmd, 1, 24, 8,  char,	    type[3]);\
-	MC_CMD_OP(cmd, 1, 32, 8,  char,	    type[4]);\
-	MC_CMD_OP(cmd, 1, 40, 8,  char,	    type[5]);\
-	MC_CMD_OP(cmd, 1, 48, 8,  char,	    type[6]);\
-	MC_CMD_OP(cmd, 1, 56, 8,  char,	    type[7]);\
-	MC_CMD_OP(cmd, 2, 0,  8,  char,	    type[8]);\
-	MC_CMD_OP(cmd, 2, 8,  8,  char,	    type[9]);\
-	MC_CMD_OP(cmd, 2, 16, 8,  char,	    type[10]);\
-	MC_CMD_OP(cmd, 2, 24, 8,  char,	    type[11]);\
-	MC_CMD_OP(cmd, 2, 32, 8,  char,	    type[12]);\
-	MC_CMD_OP(cmd, 2, 40, 8,  char,	    type[13]);\
-	MC_CMD_OP(cmd, 2, 48, 8,  char,	    type[14]);\
-	MC_CMD_OP(cmd, 2, 56, 8,  char,	    type[15]);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_RSP_GET_RES_COUNT(cmd, res_count) \
-	MC_RSP_OP(cmd, 0, 0,  32, int,	    res_count)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_GET_RES_IDS(cmd, range_desc, type) \
-do { \
-	MC_CMD_OP(cmd, 0, 42, 7,  enum dprc_iter_status, \
-					    range_desc->iter_status); \
-	MC_CMD_OP(cmd, 1, 0,  32, int,	    range_desc->base_id); \
-	MC_CMD_OP(cmd, 1, 32, 32, int,	    range_desc->last_id);\
-	MC_CMD_OP(cmd, 2, 0,  8,  char,	    type[0]);\
-	MC_CMD_OP(cmd, 2, 8,  8,  char,	    type[1]);\
-	MC_CMD_OP(cmd, 2, 16, 8,  char,	    type[2]);\
-	MC_CMD_OP(cmd, 2, 24, 8,  char,	    type[3]);\
-	MC_CMD_OP(cmd, 2, 32, 8,  char,	    type[4]);\
-	MC_CMD_OP(cmd, 2, 40, 8,  char,     type[5]);\
-	MC_CMD_OP(cmd, 2, 48, 8,  char,	    type[6]);\
-	MC_CMD_OP(cmd, 2, 56, 8,  char,	    type[7]);\
-	MC_CMD_OP(cmd, 3, 0,  8,  char,	    type[8]);\
-	MC_CMD_OP(cmd, 3, 8,  8,  char,	    type[9]);\
-	MC_CMD_OP(cmd, 3, 16, 8,  char,	    type[10]);\
-	MC_CMD_OP(cmd, 3, 24, 8,  char,	    type[11]);\
-	MC_CMD_OP(cmd, 3, 32, 8,  char,	    type[12]);\
-	MC_CMD_OP(cmd, 3, 40, 8,  char,	    type[13]);\
-	MC_CMD_OP(cmd, 3, 48, 8,  char,	    type[14]);\
-	MC_CMD_OP(cmd, 3, 56, 8,  char,	    type[15]);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_RSP_GET_RES_IDS(cmd, range_desc) \
-do { \
-	MC_RSP_OP(cmd, 0, 42, 7,  enum dprc_iter_status, \
-					    range_desc->iter_status);\
-	MC_RSP_OP(cmd, 1, 0,  32, int,	    range_desc->base_id); \
-	MC_RSP_OP(cmd, 1, 32, 32, int,	    range_desc->last_id);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  32, int,	    obj_id); \
-	MC_CMD_OP(cmd, 0, 48, 8,  uint8_t,  region_index);\
-	MC_CMD_OP(cmd, 3, 0,  8,  char,	    obj_type[0]);\
-	MC_CMD_OP(cmd, 3, 8,  8,  char,	    obj_type[1]);\
-	MC_CMD_OP(cmd, 3, 16, 8,  char,	    obj_type[2]);\
-	MC_CMD_OP(cmd, 3, 24, 8,  char,	    obj_type[3]);\
-	MC_CMD_OP(cmd, 3, 32, 8,  char,	    obj_type[4]);\
-	MC_CMD_OP(cmd, 3, 40, 8,  char,	    obj_type[5]);\
-	MC_CMD_OP(cmd, 3, 48, 8,  char,	    obj_type[6]);\
-	MC_CMD_OP(cmd, 3, 56, 8,  char,	    obj_type[7]);\
-	MC_CMD_OP(cmd, 4, 0,  8,  char,	    obj_type[8]);\
-	MC_CMD_OP(cmd, 4, 8,  8,  char,	    obj_type[9]);\
-	MC_CMD_OP(cmd, 4, 16, 8,  char,	    obj_type[10]);\
-	MC_CMD_OP(cmd, 4, 24, 8,  char,	    obj_type[11]);\
-	MC_CMD_OP(cmd, 4, 32, 8,  char,	    obj_type[12]);\
-	MC_CMD_OP(cmd, 4, 40, 8,  char,	    obj_type[13]);\
-	MC_CMD_OP(cmd, 4, 48, 8,  char,	    obj_type[14]);\
-	MC_CMD_OP(cmd, 4, 56, 8,  char,	    obj_type[15]);\
-} while (0)
-
-/*	param, offset, width,	type,		arg_name */
-#define DPRC_RSP_GET_OBJ_REGION(cmd, region_desc) \
-do { \
-	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, region_desc->base_offset);\
-	MC_RSP_OP(cmd, 2, 0,  32, uint32_t, region_desc->size); \
-	MC_RSP_OP(cmd, 2, 32, 4,  enum dprc_region_type, region_desc->type);\
-	MC_RSP_OP(cmd, 3, 0,  32, uint32_t, region_desc->flags);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_SET_OBJ_LABEL(cmd, obj_type, obj_id, label) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  32, int,      obj_id); \
-	MC_CMD_OP(cmd, 1, 0,  8,  char,	    label[0]);\
-	MC_CMD_OP(cmd, 1, 8,  8,  char,	    label[1]);\
-	MC_CMD_OP(cmd, 1, 16, 8,  char,	    label[2]);\
-	MC_CMD_OP(cmd, 1, 24, 8,  char,	    label[3]);\
-	MC_CMD_OP(cmd, 1, 32, 8,  char,	    label[4]);\
-	MC_CMD_OP(cmd, 1, 40, 8,  char,	    label[5]);\
-	MC_CMD_OP(cmd, 1, 48, 8,  char,	    label[6]);\
-	MC_CMD_OP(cmd, 1, 56, 8,  char,	    label[7]);\
-	MC_CMD_OP(cmd, 2, 0,  8,  char,	    label[8]);\
-	MC_CMD_OP(cmd, 2, 8,  8,  char,	    label[9]);\
-	MC_CMD_OP(cmd, 2, 16, 8,  char,	    label[10]);\
-	MC_CMD_OP(cmd, 2, 24, 8,  char,	    label[11]);\
-	MC_CMD_OP(cmd, 2, 32, 8,  char,	    label[12]);\
-	MC_CMD_OP(cmd, 2, 40, 8,  char,	    label[13]);\
-	MC_CMD_OP(cmd, 2, 48, 8,  char,	    label[14]);\
-	MC_CMD_OP(cmd, 2, 56, 8,  char,	    label[15]);\
-	MC_CMD_OP(cmd, 3, 0,  8,  char,	    obj_type[0]);\
-	MC_CMD_OP(cmd, 3, 8,  8,  char,	    obj_type[1]);\
-	MC_CMD_OP(cmd, 3, 16, 8,  char,	    obj_type[2]);\
-	MC_CMD_OP(cmd, 3, 24, 8,  char,	    obj_type[3]);\
-	MC_CMD_OP(cmd, 3, 32, 8,  char,	    obj_type[4]);\
-	MC_CMD_OP(cmd, 3, 40, 8,  char,	    obj_type[5]);\
-	MC_CMD_OP(cmd, 3, 48, 8,  char,	    obj_type[6]);\
-	MC_CMD_OP(cmd, 3, 56, 8,  char,	    obj_type[7]);\
-	MC_CMD_OP(cmd, 4, 0,  8,  char,	    obj_type[8]);\
-	MC_CMD_OP(cmd, 4, 8,  8,  char,	    obj_type[9]);\
-	MC_CMD_OP(cmd, 4, 16, 8,  char,	    obj_type[10]);\
-	MC_CMD_OP(cmd, 4, 24, 8,  char,	    obj_type[11]);\
-	MC_CMD_OP(cmd, 4, 32, 8,  char,	    obj_type[12]);\
-	MC_CMD_OP(cmd, 4, 40, 8,  char,	    obj_type[13]);\
-	MC_CMD_OP(cmd, 4, 48, 8,  char,	    obj_type[14]);\
-	MC_CMD_OP(cmd, 4, 56, 8,  char,	    obj_type[15]);\
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  32, int,      endpoint1->id); \
-	MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \
-	MC_CMD_OP(cmd, 1, 0,  32, int,	    endpoint2->id); \
-	MC_CMD_OP(cmd, 1, 32, 32, int, endpoint2->if_id); \
-	MC_CMD_OP(cmd, 2, 0,  8,  char,     endpoint1->type[0]); \
-	MC_CMD_OP(cmd, 2, 8,  8,  char,	    endpoint1->type[1]); \
-	MC_CMD_OP(cmd, 2, 16, 8,  char,	    endpoint1->type[2]); \
-	MC_CMD_OP(cmd, 2, 24, 8,  char,	    endpoint1->type[3]); \
-	MC_CMD_OP(cmd, 2, 32, 8,  char,	    endpoint1->type[4]); \
-	MC_CMD_OP(cmd, 2, 40, 8,  char,	    endpoint1->type[5]); \
-	MC_CMD_OP(cmd, 2, 48, 8,  char,	    endpoint1->type[6]); \
-	MC_CMD_OP(cmd, 2, 56, 8,  char,	    endpoint1->type[7]); \
-	MC_CMD_OP(cmd, 3, 0,  8,  char,	    endpoint1->type[8]); \
-	MC_CMD_OP(cmd, 3, 8,  8,  char,	    endpoint1->type[9]); \
-	MC_CMD_OP(cmd, 3, 16, 8,  char,	    endpoint1->type[10]); \
-	MC_CMD_OP(cmd, 3, 24, 8,  char,	    endpoint1->type[11]); \
-	MC_CMD_OP(cmd, 3, 32, 8,  char,     endpoint1->type[12]); \
-	MC_CMD_OP(cmd, 3, 40, 8,  char,	    endpoint1->type[13]); \
-	MC_CMD_OP(cmd, 3, 48, 8,  char,	    endpoint1->type[14]); \
-	MC_CMD_OP(cmd, 3, 56, 8,  char,	    endpoint1->type[15]); \
-	MC_CMD_OP(cmd, 4, 0,  32, uint32_t, cfg->max_rate); \
-	MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->committed_rate); \
-	MC_CMD_OP(cmd, 5, 0,  8,  char,	    endpoint2->type[0]); \
-	MC_CMD_OP(cmd, 5, 8,  8,  char,	    endpoint2->type[1]); \
-	MC_CMD_OP(cmd, 5, 16, 8,  char,	    endpoint2->type[2]); \
-	MC_CMD_OP(cmd, 5, 24, 8,  char,	    endpoint2->type[3]); \
-	MC_CMD_OP(cmd, 5, 32, 8,  char,	    endpoint2->type[4]); \
-	MC_CMD_OP(cmd, 5, 40, 8,  char,	    endpoint2->type[5]); \
-	MC_CMD_OP(cmd, 5, 48, 8,  char,	    endpoint2->type[6]); \
-	MC_CMD_OP(cmd, 5, 56, 8,  char,	    endpoint2->type[7]); \
-	MC_CMD_OP(cmd, 6, 0,  8,  char,	    endpoint2->type[8]); \
-	MC_CMD_OP(cmd, 6, 8,  8,  char,	    endpoint2->type[9]); \
-	MC_CMD_OP(cmd, 6, 16, 8,  char,	    endpoint2->type[10]); \
-	MC_CMD_OP(cmd, 6, 24, 8,  char,	    endpoint2->type[11]); \
-	MC_CMD_OP(cmd, 6, 32, 8,  char,	    endpoint2->type[12]); \
-	MC_CMD_OP(cmd, 6, 40, 8,  char,	    endpoint2->type[13]); \
-	MC_CMD_OP(cmd, 6, 48, 8,  char,	    endpoint2->type[14]); \
-	MC_CMD_OP(cmd, 6, 56, 8,  char,	    endpoint2->type[15]); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_DISCONNECT(cmd, endpoint) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  32, int,	    endpoint->id); \
-	MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint->if_id); \
-	MC_CMD_OP(cmd, 1, 0,  8,  char,	    endpoint->type[0]); \
-	MC_CMD_OP(cmd, 1, 8,  8,  char,	    endpoint->type[1]); \
-	MC_CMD_OP(cmd, 1, 16, 8,  char,	    endpoint->type[2]); \
-	MC_CMD_OP(cmd, 1, 24, 8,  char,	    endpoint->type[3]); \
-	MC_CMD_OP(cmd, 1, 32, 8,  char,	    endpoint->type[4]); \
-	MC_CMD_OP(cmd, 1, 40, 8,  char,	    endpoint->type[5]); \
-	MC_CMD_OP(cmd, 1, 48, 8,  char,	    endpoint->type[6]); \
-	MC_CMD_OP(cmd, 1, 56, 8,  char,	    endpoint->type[7]); \
-	MC_CMD_OP(cmd, 2, 0,  8,  char,	    endpoint->type[8]); \
-	MC_CMD_OP(cmd, 2, 8,  8,  char,	    endpoint->type[9]); \
-	MC_CMD_OP(cmd, 2, 16, 8,  char,	    endpoint->type[10]); \
-	MC_CMD_OP(cmd, 2, 24, 8,  char,	    endpoint->type[11]); \
-	MC_CMD_OP(cmd, 2, 32, 8,  char,	    endpoint->type[12]); \
-	MC_CMD_OP(cmd, 2, 40, 8,  char,	    endpoint->type[13]); \
-	MC_CMD_OP(cmd, 2, 48, 8,  char,	    endpoint->type[14]); \
-	MC_CMD_OP(cmd, 2, 56, 8,  char,	    endpoint->type[15]); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_CMD_GET_CONNECTION(cmd, endpoint1) \
-do { \
-	MC_CMD_OP(cmd, 0, 0,  32, int,	    endpoint1->id); \
-	MC_CMD_OP(cmd, 0, 32, 32, int,	    endpoint1->if_id); \
-	MC_CMD_OP(cmd, 1, 0,  8,  char,     endpoint1->type[0]); \
-	MC_CMD_OP(cmd, 1, 8,  8,  char,	    endpoint1->type[1]); \
-	MC_CMD_OP(cmd, 1, 16, 8,  char,	    endpoint1->type[2]); \
-	MC_CMD_OP(cmd, 1, 24, 8,  char,	    endpoint1->type[3]); \
-	MC_CMD_OP(cmd, 1, 32, 8,  char,	    endpoint1->type[4]); \
-	MC_CMD_OP(cmd, 1, 40, 8,  char,	    endpoint1->type[5]); \
-	MC_CMD_OP(cmd, 1, 48, 8,  char,	    endpoint1->type[6]); \
-	MC_CMD_OP(cmd, 1, 56, 8,  char,	    endpoint1->type[7]); \
-	MC_CMD_OP(cmd, 2, 0,  8,  char,	    endpoint1->type[8]); \
-	MC_CMD_OP(cmd, 2, 8,  8,  char,	    endpoint1->type[9]); \
-	MC_CMD_OP(cmd, 2, 16, 8,  char,	    endpoint1->type[10]); \
-	MC_CMD_OP(cmd, 2, 24, 8,  char,	    endpoint1->type[11]); \
-	MC_CMD_OP(cmd, 2, 32, 8,  char,     endpoint1->type[12]); \
-	MC_CMD_OP(cmd, 2, 40, 8,  char,	    endpoint1->type[13]); \
-	MC_CMD_OP(cmd, 2, 48, 8,  char,	    endpoint1->type[14]); \
-	MC_CMD_OP(cmd, 2, 56, 8,  char,	    endpoint1->type[15]); \
-} while (0)
-
-/*                cmd, param, offset, width, type, arg_name */
-#define DPRC_RSP_GET_CONNECTION(cmd, endpoint2, state) \
-do { \
-	MC_RSP_OP(cmd, 3, 0,  32, int,	    endpoint2->id); \
-	MC_RSP_OP(cmd, 3, 32, 16, uint16_t, endpoint2->if_id); \
-	MC_RSP_OP(cmd, 4, 0,  8,  char,	    endpoint2->type[0]); \
-	MC_RSP_OP(cmd, 4, 8,  8,  char,	    endpoint2->type[1]); \
-	MC_RSP_OP(cmd, 4, 16, 8,  char,	    endpoint2->type[2]); \
-	MC_RSP_OP(cmd, 4, 24, 8,  char,	    endpoint2->type[3]); \
-	MC_RSP_OP(cmd, 4, 32, 8,  char,	    endpoint2->type[4]); \
-	MC_RSP_OP(cmd, 4, 40, 8,  char,	    endpoint2->type[5]); \
-	MC_RSP_OP(cmd, 4, 48, 8,  char,	    endpoint2->type[6]); \
-	MC_RSP_OP(cmd, 4, 56, 8,  char,	    endpoint2->type[7]); \
-	MC_RSP_OP(cmd, 5, 0,  8,  char,	    endpoint2->type[8]); \
-	MC_RSP_OP(cmd, 5, 8,  8,  char,	    endpoint2->type[9]); \
-	MC_RSP_OP(cmd, 5, 16, 8,  char,	    endpoint2->type[10]); \
-	MC_RSP_OP(cmd, 5, 24, 8,  char,	    endpoint2->type[11]); \
-	MC_RSP_OP(cmd, 5, 32, 8,  char,	    endpoint2->type[12]); \
-	MC_RSP_OP(cmd, 5, 40, 8,  char,	    endpoint2->type[13]); \
-	MC_RSP_OP(cmd, 5, 48, 8,  char,	    endpoint2->type[14]); \
-	MC_RSP_OP(cmd, 5, 56, 8,  char,	    endpoint2->type[15]); \
-	MC_RSP_OP(cmd, 6, 0,  32, int,	    state); \
-} while (0)
+#pragma pack(push, 1)
+struct dprc_cmd_open {
+	__le32 container_id;
+};
+
+struct dprc_cmd_create_container {
+	__le32 options;
+	__le32 icid;
+	__le32 pad1;
+	__le32 portal_id;
+	u8 label[16];
+};
+
+struct dprc_rsp_create_container {
+	__le64 pad0;
+	__le32 child_container_id;
+	__le32 pad1;
+	__le64 child_portal_addr;
+};
+
+struct dprc_cmd_destroy_container {
+	__le32 child_container_id;
+};
+
+struct dprc_cmd_connect {
+	__le32 ep1_id;
+	__le16 ep1_interface_id;
+	__le16 pad0;
+
+	__le32 ep2_id;
+	__le16 ep2_interface_id;
+	__le16 pad1;
+
+	u8 ep1_type[16];
+
+	__le32 max_rate;
+	__le32 committed_rate;
+
+	u8 ep2_type[16];
+};
+
+struct dprc_cmd_disconnect {
+	__le32 id;
+	__le32 interface_id;
+	u8 type[16];
+};
+
+struct dprc_cmd_get_connection {
+	__le32 ep1_id;
+	__le16 ep1_interface_id;
+	__le16 pad;
+
+	u8 ep1_type[16];
+};
+
+struct dprc_rsp_get_connection {
+	__le64 pad[3];
+	__le32 ep2_id;
+	__le16 ep2_interface_id;
+	__le16 pad1;
+	u8 ep2_type[16];
+	__le32 state;
+};
+
+#pragma pack(pop)
 
 /* Data Path Resource Container API
  * Contains DPRC API for managing and querying DPAA resources
@@ -463,7 +103,7 @@ struct fsl_mc_io;
  * container, in case the ICID is not selected by the user and should be
  * allocated by the DPRC from the pool of ICIDs.
  */
-#define DPRC_GET_ICID_FROM_POOL			(uint16_t)(~(0))
+#define DPRC_GET_ICID_FROM_POOL			(u16)(~(0))
 
 /**
  * Set this value as the portal_id value in dprc_cfg structure when creating a
@@ -472,48 +112,11 @@ struct fsl_mc_io;
  */
 #define DPRC_GET_PORTAL_ID_FROM_POOL	(int)(~(0))
 
-/**
- * dprc_get_container_id() - Get container ID associated with a given portal.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @container_id:	Requested container ID
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dprc_get_container_id(struct fsl_mc_io	*mc_io,
-			  uint32_t		cmd_flags,
-			  int			*container_id);
+int dprc_get_container_id(struct fsl_mc_io *mc_io, u32 cmd_flags, int *container_id);
 
-/**
- * dprc_open() - Open DPRC object for use
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @container_id: Container ID to open
- * @token:	Returned token of DPRC object
- *
- * Return:	'0' on Success; Error code otherwise.
- *
- * @warning	Required before any operation on the object.
- */
-int dprc_open(struct fsl_mc_io	*mc_io,
-	      uint32_t		cmd_flags,
-	      int		container_id,
-	      uint16_t		*token);
+int dprc_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int container_id, u16 *token);
 
-/**
- * dprc_close() - Close the control session of the object
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPRC object
- *
- * After this function is called, no further operations are
- * allowed on the object without opening a new control session.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dprc_close(struct fsl_mc_io	*mc_io,
-	       uint32_t		cmd_flags,
-	       uint16_t		token);
+int dprc_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
 
 /**
  * Container general options
@@ -563,395 +166,57 @@ int dprc_close(struct fsl_mc_io	*mc_io,
  * @label: Object's label
  */
 struct dprc_cfg {
-	uint16_t icid;
-	int portal_id;
-	uint64_t options;
-	char label[16];
-};
-
-/**
- * dprc_create_container() - Create child container
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPRC object
- * @cfg:	Child container configuration
- * @child_container_id:	Returned child container ID
- * @child_portal_offset: Returned child portal offset from MC portal base
- *
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dprc_create_container(struct fsl_mc_io	*mc_io,
-			  uint32_t		cmd_flags,
-			  uint16_t		token,
-			  struct dprc_cfg	*cfg,
-			  int			*child_container_id,
-			  uint64_t		*child_portal_offset);
-
-/**
- * dprc_destroy_container() - Destroy child container.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPRC object
- * @child_container_id:	ID of the container to destroy
- *
- * This function terminates the child container, so following this call the
- * child container ID becomes invalid.
- *
- * Notes:
- * - All resources and objects of the destroyed container are returned to the
- * parent container or destroyed if were created be the destroyed container.
- * - This function destroy all the child containers of the specified
- *   container prior to destroying the container itself.
- *
- * warning: Only the parent container is allowed to destroy a child policy
- *		Container 0 can't be destroyed
- *
- * Return:	'0' on Success; Error code otherwise.
- *
- */
-int dprc_destroy_container(struct fsl_mc_io	*mc_io,
-			   uint32_t		cmd_flags,
-			   uint16_t		token,
-			   int			child_container_id);
-
-/**
- * dprc_reset_container - Reset child container.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPRC object
- * @child_container_id:	ID of the container to reset
- *
- * In case a software context crashes or becomes non-responsive, the parent
- * may wish to reset its resources container before the software context is
- * restarted.
- *
- * This routine informs all objects assigned to the child container that the
- * container is being reset, so they may perform any cleanup operations that are
- * needed. All objects handles that were owned by the child container shall be
- * closed.
- *
- * Note that such request may be submitted even if the child software context
- * has not crashed, but the resulting object cleanup operations will not be
- * aware of that.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dprc_reset_container(struct fsl_mc_io	*mc_io,
-			 uint32_t		cmd_flags,
-			 uint16_t		token,
-			 int			child_container_id);
-
-/**
- * struct dprc_attributes - Container attributes
- * @container_id: Container's ID
- * @icid: Container's ICID
- * @portal_id: Container's portal ID
- * @options: Container's options as set at container's creation
- * @version: DPRC version
- */
-struct dprc_attributes {
-	int container_id;
-	uint16_t icid;
+	u16 icid;
 	int portal_id;
 	uint64_t options;
-};
-
-/**
- * dprc_get_attributes() - Obtains container attributes
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPRC object
- * @attributes:	Returned container attributes
- *
- * Return:     '0' on Success; Error code otherwise.
- */
-int dprc_get_attributes(struct fsl_mc_io	*mc_io,
-			uint32_t		cmd_flags,
-			uint16_t		token,
-			struct dprc_attributes	*attributes);
-
-/**
- * dprc_get_obj_count() - Obtains the number of objects in the DPRC
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPRC object
- * @obj_count:	Number of objects assigned to the DPRC
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dprc_get_obj_count(struct fsl_mc_io	*mc_io,
-		       uint32_t		cmd_flags,
-		       uint16_t		token,
-		       int			*obj_count);
-
-/* Objects Attributes Flags */
-
-/* Opened state - Indicates that an object is open by at least one owner */
-#define DPRC_OBJ_STATE_OPEN		0x00000001
-/* Plugged state - Indicates that the object is plugged */
-#define DPRC_OBJ_STATE_PLUGGED		0x00000002
-
-/**
- * Shareability flag - Object flag indicating no memory shareability.
- *  the object generates memory accesses that are non coherent with other
- *  masters;
- *  user is responsible for proper memory handling through IOMMU configuration.
- */
-#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY		0x0001
-
-/**
- * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj()
- * @type: Type of object: NULL terminated string
- * @id: ID of logical object resource
- * @vendor: Object vendor identifier
- * @ver_major: Major version number
- * @ver_minor:  Minor version number
- * @irq_count: Number of interrupts supported by the object
- * @region_count: Number of mappable regions supported by the object
- * @state: Object state: combination of DPRC_OBJ_STATE_ states
- * @label: Object label
- * @flags: Object's flags
- */
-struct dprc_obj_desc {
-	char type[16];
-	int id;
-	uint16_t vendor;
-	uint16_t ver_major;
-	uint16_t ver_minor;
-	uint8_t irq_count;
-	uint8_t region_count;
-	uint32_t state;
 	char label[16];
-	uint16_t	flags;
 };
 
-/**
- * dprc_get_obj() - Get general information on an object
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPRC object
- * @obj_index:	Index of the object to be queried (< obj_count)
- * @obj_desc:	Returns the requested object descriptor
- *
- * The object descriptors are retrieved one by one by incrementing
- * obj_index up to (not including) the value of obj_count returned
- * from dprc_get_obj_count(). dprc_get_obj_count() must
- * be called prior to dprc_get_obj().
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dprc_get_obj(struct fsl_mc_io	*mc_io,
-		 uint32_t		cmd_flags,
-		 uint16_t		token,
-		 int			obj_index,
-		 struct dprc_obj_desc	*obj_desc);
-
-/**
- * dprc_get_res_count() - Obtains the number of free resources that are
- *		assigned to this container, by pool type
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPRC object
- * @type:	pool type
- * @res_count:	Returned number of free resources of the given
- *			resource type that are assigned to this DPRC
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dprc_get_res_count(struct fsl_mc_io *mc_io,
-		       uint32_t	cmd_flags,
-		       uint16_t		token,
-		       char		*type,
-		       int		*res_count);
-
-/**
- * enum dprc_iter_status - Iteration status
- * @DPRC_ITER_STATUS_FIRST: Perform first iteration
- * @DPRC_ITER_STATUS_MORE: Indicates more/next iteration is needed
- * @DPRC_ITER_STATUS_LAST: Indicates last iteration
- */
-enum dprc_iter_status {
-	DPRC_ITER_STATUS_FIRST = 0,
-	DPRC_ITER_STATUS_MORE = 1,
-	DPRC_ITER_STATUS_LAST = 2
-};
-
-/**
- * struct dprc_res_ids_range_desc - Resource ID range descriptor
- * @base_id: Base resource ID of this range
- * @last_id: Last resource ID of this range
- * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at
- *	first iteration; while the returned marker is DPRC_ITER_STATUS_MORE,
- *	additional iterations are needed, until the returned marker is
- *	DPRC_ITER_STATUS_LAST
- */
-struct dprc_res_ids_range_desc {
-	int base_id;
-	int last_id;
-	enum dprc_iter_status iter_status;
-};
-
-/**
- * dprc_get_res_ids() - Obtains IDs of free resources in the container
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPRC object
- * @type:	pool type
- * @range_desc:	range descriptor
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dprc_get_res_ids(struct fsl_mc_io			*mc_io,
-		     uint32_t				cmd_flags,
-		     uint16_t				token,
-		     char				*type,
-		     struct dprc_res_ids_range_desc	*range_desc);
-
-/* Region flags */
-/* Cacheable - Indicates that region should be mapped as cacheable */
-#define DPRC_REGION_CACHEABLE	0x00000001
+int dprc_create_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			  struct dprc_cfg *cfg, int *child_container_id,
+			  uint64_t *child_portal_offset);
 
-/**
- * enum dprc_region_type - Region type
- * @DPRC_REGION_TYPE_MC_PORTAL: MC portal region
- * @DPRC_REGION_TYPE_QBMAN_PORTAL: Qbman portal region
- */
-enum dprc_region_type {
-	DPRC_REGION_TYPE_MC_PORTAL,
-	DPRC_REGION_TYPE_QBMAN_PORTAL
-};
+int dprc_destroy_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			   int child_container_id);
 
 /**
- * struct dprc_region_desc - Mappable region descriptor
- * @base_offset: Region offset from region's base address.
- *	For DPMCP and DPRC objects, region base is offset from SoC MC portals
- *	base address; For DPIO, region base is offset from SoC QMan portals
- *	base address
- * @size: Region size (in bytes)
- * @flags: Region attributes
- * @type: Portal region type
+ * struct dprc_connection_cfg - Connection configuration.
+ *				Used for virtual connections only
+ * @committed_rate: Committed rate (Mbits/s)
+ * @max_rate: Maximum rate (Mbits/s)
  */
-struct dprc_region_desc {
-	uint32_t base_offset;
-	uint32_t size;
-	uint32_t flags;
-	enum dprc_region_type type;
+struct dprc_connection_cfg {
+	u32 committed_rate;
+	u32 max_rate;
 };
 
 /**
- * dprc_get_obj_region() - Get region information for a specified object.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPRC object
- * @obj_type:	Object type as returned in dprc_get_obj()
- * @obj_id:	Unique object instance as returned in dprc_get_obj()
- * @region_index: The specific region to query
- * @region_desc:  Returns the requested region descriptor
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dprc_get_obj_region(struct fsl_mc_io	*mc_io,
-			uint32_t		cmd_flags,
-			uint16_t		token,
-			char			*obj_type,
-			int			obj_id,
-			uint8_t			region_index,
-			struct dprc_region_desc	*region_desc);
-/**
  * struct dprc_endpoint - Endpoint description for link connect/disconnect
  *			operations
- * @type: Endpoint object type: NULL terminated string
- * @id: Endpoint object ID
- * @if_id: Interface ID; should be set for endpoints with multiple
+ * @type:	Endpoint object type: NULL terminated string
+ * @id:		Endpoint object ID
+ * @if_id:	Interface ID; should be set for endpoints with multiple
  *		interfaces ("dpsw", "dpdmux"); for others, always set to 0
  */
 struct dprc_endpoint {
-	char		type[16];
-	int		id;
-	uint16_t	if_id;
-};
-
-/**
- * struct dprc_connection_cfg - Connection configuration.
- *				Used for virtual connections only
- * @committed_rate: Committed rate (Mbits/s)
- * @max_rate: Maximum rate (Mbits/s)
- */
-struct dprc_connection_cfg {
-	uint32_t committed_rate;
-	uint32_t max_rate;
+	char type[16];
+	int id;
+	u16 if_id;
 };
 
-/**
- * dprc_connect() - Connect two endpoints to create a network link between them
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPRC object
- * @endpoint1:	Endpoint 1 configuration parameters
- * @endpoint2:	Endpoint 2 configuration parameters
- * @cfg: Connection configuration. The connection configuration is ignored for
- *	connections made to DPMAC objects, where rate is retrieved from the
- *	MAC configuration.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dprc_connect(struct fsl_mc_io			*mc_io,
-		 uint32_t				cmd_flags,
-		 uint16_t				token,
-		 const struct dprc_endpoint		*endpoint1,
-		 const struct dprc_endpoint		*endpoint2,
-		 const struct dprc_connection_cfg	*cfg);
+int dprc_connect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		 const struct dprc_endpoint *endpoint1,
+		 const struct dprc_endpoint *endpoint2,
+		 const struct dprc_connection_cfg *cfg);
 
-/**
- * dprc_disconnect() - Disconnect one endpoint to remove its network connection
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPRC object
- * @endpoint:	Endpoint configuration parameters
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dprc_disconnect(struct fsl_mc_io		*mc_io,
-		    uint32_t			cmd_flags,
-		    uint16_t			token,
-		    const struct dprc_endpoint	*endpoint);
+int dprc_disconnect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+		    const struct dprc_endpoint *endpoint);
 
-/**
-* dprc_get_connection() - Get connected endpoint and link status if connection
-*			exists.
-* @mc_io:	Pointer to MC portal's I/O object
-* @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-* @token:	Token of DPRC object
-* @endpoint1:	Endpoint 1 configuration parameters
-* @endpoint2:	Returned endpoint 2 configuration parameters
-* @state:	Returned link state:
-*           1 - link is up;
-*           0 - link is down;
-*           -1 - no connection (endpoint2 information is irrelevant)
-*
-* Return:     '0' on Success; -ENAVAIL if connection does not exist.
-*/
-int dprc_get_connection(struct fsl_mc_io		*mc_io,
-			uint32_t			cmd_flags,
-			uint16_t			token,
-			const struct dprc_endpoint	*endpoint1,
-			struct dprc_endpoint		*endpoint2,
-			int				*state);
+int dprc_get_connection(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			const struct dprc_endpoint *endpoint1,
+			struct dprc_endpoint *endpoint2, int *state);
 
-/**
- * dprc_get_api_version - Retrieve DPRC Major and Minor version info.
- *
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @major_ver:	DPRC major version
- * @minor_ver:	DPRC minor version
- *
- * Return:     '0' on Success; Error code otherwise.
- */
-int dprc_get_api_version(struct fsl_mc_io *mc_io,
-			 u32 cmd_flags,
-			 u16 *major_ver,
-			 u16 *minor_ver);
+int dprc_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+			 u16 *major_ver, u16 *minor_ver);
 
 #endif /* _FSL_DPRC_H */
diff --git a/include/fsl-mc/fsl_dpsparser.h b/include/fsl-mc/fsl_dpsparser.h
index 48fb495059..9619bb1413 100644
--- a/include/fsl-mc/fsl_dpsparser.h
+++ b/include/fsl-mc/fsl_dpsparser.h
@@ -2,7 +2,7 @@
 /*
  * Data Path Soft Parser API
  *
- * Copyright 2018 NXP
+ * Copyright 2018, 2023 NXP
  */
 #ifndef _FSL_DPSPARSER_H
 #define _FSL_DPSPARSER_H
@@ -20,13 +20,26 @@
 
 #define DPSPARSER_CMDID_APPLY_SPB			0x1181
 
-/*                cmd, param, offset, width, type, arg_name */
-#define DPSPARSER_CMD_BLOB_SET_ADDR(cmd, addr) \
-	MC_CMD_OP(cmd, 0, 0,  64, u64,	    addr)
+#pragma pack(push, 1)
 
-/*                cmd, param, offset, width, type,	arg_name */
-#define DPSPARSER_CMD_BLOB_REPORT_ERROR(cmd, err) \
-	MC_RSP_OP(cmd, 0, 0, 16, u16, err)
+struct dpsparser_cmd_destroy {
+	__le32 dpsparser_id;
+};
+
+struct dpsparser_cmd_blob_set_address {
+	__le64 blob_addr;
+};
+
+struct dpsparser_rsp_blob_report_error {
+	__le16 error;
+};
+
+struct dpsparser_rsp_get_api_version {
+	__le16 major;
+	__le16 minor;
+};
+
+#pragma pack(pop)
 
 /* Data Path Soft Parser API
  * Contains initialization APIs and runtime control APIs for DPSPARSER
@@ -99,110 +112,20 @@ struct fsl_mc_io;
 	NULL, \
 }
 
-/**
- * dpsparser_open() - Open a control session for the specified object.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Returned token; use in subsequent API calls
- *
- * This function can be used to open a control session for an
- * already created object; an object may have been declared in
- * the DPL or by calling the dpsparser_create function.
- * This function returns a unique authentication token,
- * associated with the specific object ID and the specific MC
- * portal; this token must be used in all subsequent commands for
- * this specific object
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpsparser_open(struct fsl_mc_io	*mc_io,
-		   u32 cmd_flags,
-		   u16 *token);
-
-/**
- * dpsparser_close() - Close the control session of the object
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPSPARSER object
- *
- * After this function is called, no further operations are
- * allowed on the object without opening a new control session.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpsparser_close(struct fsl_mc_io *mc_io,
-		    u32 cmd_flags,
-		    u16	token);
-
-/**
- * dpsparser_create() - Create the DPSPARSER object.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Returned token; use in subsequent API calls
- *
- * Create the DPSPARSER object, allocate required resources and
- * perform required initialization.
- *
- * The object can be created either by declaring it in the
- * DPL file, or by calling this function.
- * This function returns a unique authentication token,
- * associated with the specific object ID and the specific MC
- * portal; this token must be used in all subsequent calls to
- * this specific object. For objects that are created using the
- * DPL file, call dpsparser_open function to get an authentication
- * token first.
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpsparser_create(struct fsl_mc_io *mc_io,
-		     u16 token,
-		     u32 cmd_flags,
+int dpsparser_open(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 *token);
+
+int dpsparser_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
+
+int dpsparser_create(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags,
 		     u32 *obj_id);
 
-/**
- * dpsparser_destroy() - Destroy the DPSPARSER object and release all its
- * resources.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPSPARSER object
- *
- * Return:	'0' on Success; error code otherwise.
- */
-int dpsparser_destroy(struct fsl_mc_io *mc_io,
-		      u16 token,
-		      u32 cmd_flags,
+int dpsparser_destroy(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags,
 		      u32 obj_id);
 
-/**
- * dpsparser_apply_spb() - Applies the Soft Parser Blob loaded at specified
- * address.
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @token:	Token of DPSPARSER object
- * @blob_addr:	Blob loading address
- * @error: Error reported by MC related to SP Blob parsing and apply
- *
- * Return:	'0' on Success; error code otherwise.
- */
-int dpsparser_apply_spb(struct fsl_mc_io *mc_io,
-			u32 cmd_flags,
-			u16 token,
-			u64 blob_addr,
-			u16 *error);
-
-/**
- * dpsparser_get_api_version - Retrieve DPSPARSER Major and Minor version info.
- *
- * @mc_io:	Pointer to MC portal's I/O object
- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
- * @major_ver:	DPSPARSER major version
- * @minor_ver:	DPSPARSER minor version
- *
- * Return:	'0' on Success; Error code otherwise.
- */
-int dpsparser_get_api_version(struct fsl_mc_io *mc_io,
-			      u32 cmd_flags,
-			      u16 *major_ver,
-			      u16 *minor_ver);
+int dpsparser_apply_spb(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+			u64 blob_addr, u16 *error);
+
+int dpsparser_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+			      u16 *major_ver, u16 *minor_ver);
 
 #endif /* _FSL_DPSPARSER_H */
diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h
index 591cda9685..c239595ed5 100644
--- a/include/fsl-mc/fsl_mc_cmd.h
+++ b/include/fsl-mc/fsl_mc_cmd.h
@@ -19,6 +19,15 @@ static inline uint64_t mc_dec(uint64_t val, int lsoffset, int width)
 	return (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width));
 }
 
+struct mc_cmd_header {
+	u8 src_id;
+	u8 flags_hw;
+	u8 status;
+	u8 flags_sw;
+	__le16 token;
+	__le16 cmd_id;
+};
+
 struct mc_command {
 	uint64_t header;
 	uint64_t params[MC_CMD_NUM_OF_PARAMS];
@@ -74,29 +83,6 @@ enum mc_cmd_status {
 	((enum mc_cmd_status)mc_dec((_hdr), \
 		MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S))
 
-#define MC_CMD_HDR_READ_TOKEN(_hdr) \
-	((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S))
-
-#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \
-	((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg)))
-
-#define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \
-	(_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width)))
-
-#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \
-	((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
-
-#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \
-	(_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width)))
-
-/*                cmd, param, offset, width, type, arg_name */
-#define MC_CMD_READ_OBJ_ID(cmd, obj_id) \
-	MC_RSP_OP(cmd, 0, 0,  32,  uint32_t,	    obj_id)
-
-/* cmd, param, offset, width, type, arg_name */
-#define CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id) \
-	MC_CMD_OP(cmd, 0, 0,  32,  uint32_t,  object_id)
-
 static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id,
 					    uint32_t cmd_flags,
 					    uint16_t token)
@@ -179,4 +165,19 @@ static inline void mc_cmd_read_api_version(struct mc_command *cmd,
 	*minor_ver = le16_to_cpu(rsp_params->minor_ver);
 }
 
+static inline uint16_t mc_cmd_hdr_read_token(struct mc_command *cmd)
+{
+	struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
+	u16 token = le16_to_cpu(hdr->token);
+
+	return token;
+}
+
+static inline uint32_t mc_cmd_read_object_id(struct mc_command *cmd)
+{
+	struct mc_rsp_create *rsp_params;
+
+	rsp_params = (struct mc_rsp_create *)cmd->params;
+	return le32_to_cpu(rsp_params->object_id);
+}
 #endif /* __FSL_MC_CMD_H */
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index d8861d1d0b..9dad1d1ec4 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -13,8 +13,8 @@
 #include <asm/io.h>
 
 #ifdef CONFIG_SYS_FSL_SEC_LE
-#define sec_in32(a)       in_le32((ulong *)(ulong)a)
-#define sec_out32(a, v)   out_le32((ulong *)(ulong)a, v)
+#define sec_in32(a)       in_le32((ulong *)(ulong)(a))
+#define sec_out32(a, v)   out_le32((ulong *)(ulong)(a), v)
 #define sec_in16(a)       in_le16(a)
 #define sec_clrbits32     clrbits_le32
 #define sec_setbits32     setbits_le32
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index fbcbd42496..66a5883f1f 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -275,9 +275,9 @@ int fsl_check_boot_mode_secure(void);
 int fsl_setenv_chain_of_trust(void);
 
 /*
- * This function is used to validate the main U-boot binary from
+ * This function is used to validate the main U-Boot binary from
  * SPL just before passing control to it using QorIQ Trust
- * Architecture header (appended to U-boot image).
+ * Architecture header (appended to U-Boot image).
  */
 void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr);
 
diff --git a/include/fwu.h b/include/fwu.h
index 0919ced812..ac5c5de870 100644
--- a/include/fwu.h
+++ b/include/fwu.h
@@ -8,6 +8,8 @@
 
 #include <blk.h>
 #include <efi.h>
+#include <mtd.h>
+#include <uuid.h>
 
 #include <linux/types.h>
 
@@ -18,83 +20,32 @@ struct fwu_mdata_gpt_blk_priv {
 	struct udevice *blk_dev;
 };
 
-/**
- * @mdata_check: check the validity of the FWU metadata partitions
- * @get_mdata() - Get a FWU metadata copy
- * @update_mdata() - Update the FWU metadata copy
- */
-struct fwu_mdata_ops {
-	/**
-	 * check_mdata() - Check if the FWU metadata is valid
-	 * @dev:	FWU device
-	 *
-	 * Validate both copies of the FWU metadata. If one of the copies
-	 * has gone bad, restore it from the other copy.
-	 *
-	 * Return: 0 if OK, -ve on error
-	 */
-	int (*check_mdata)(struct udevice *dev);
-
-	/**
-	 * get_mdata() - Get a FWU metadata copy
-	 * @dev:	FWU device
-	 * @mdata:	Pointer to FWU metadata
-	 *
-	 * Get a valid copy of the FWU metadata.
-	 *
-	 * Return: 0 if OK, -ve on error
-	 */
-	int (*get_mdata)(struct udevice *dev, struct fwu_mdata *mdata);
-
-	/**
-	 * update_mdata() - Update the FWU metadata
-	 * @dev:	FWU device
-	 * @mdata:	Copy of the FWU metadata
-	 *
-	 * Update the FWU metadata structure by writing to the
-	 * FWU metadata partitions.
-	 *
-	 * Return: 0 if OK, -ve on error
-	 */
-	int (*update_mdata)(struct udevice *dev, struct fwu_mdata *mdata);
-
-	/**
-	 * get_mdata_part_num() - Get the FWU metadata partition numbers
-	 * @dev:		FWU metadata device
-	 * @mdata_parts:	 array for storing the metadata partition numbers
-	 *
-	 * Get the partition numbers on the storage device on which the
-	 * FWU metadata is stored. Two partition numbers will be returned.
-	 *
-	 * Return: 0 if OK, -ve on error
-	 */
-	int (*get_mdata_part_num)(struct udevice *dev, uint *mdata_parts);
+struct fwu_mtd_image_info {
+	u32 start, size;
+	int bank_num, image_num;
+	char uuidbuf[UUID_STR_LEN + 1];
+};
 
+struct fwu_mdata_ops {
 	/**
-	 * read_mdata_partition() - Read the FWU metadata from a partition
-	 * @dev:	FWU metadata device
-	 * @mdata:	Copy of the FWU metadata
-	 * @part_num:	Partition number from which FWU metadata is to be read
-	 *
-	 * Read the FWU metadata from the specified partition number
+	 * read_mdata() - Populate the asked FWU metadata copy
+	 * @dev: FWU metadata device
+	 * @mdata: Output FWU mdata read
+	 * @primary: If primary or secondary copy of metadata is to be read
 	 *
 	 * Return: 0 if OK, -ve on error
 	 */
-	int (*read_mdata_partition)(struct udevice *dev,
-				    struct fwu_mdata *mdata, uint part_num);
+	int (*read_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
 
 	/**
-	 * write_mdata_partition() - Write the FWU metadata to a partition
-	 * @dev:	FWU metadata device
-	 * @mdata:	Copy of the FWU metadata
-	 * @part_num:	Partition number to which FWU metadata is to be written
-	 *
-	 * Write the FWU metadata to the specified partition number
+	 * write_mdata() - Write the given FWU metadata copy
+	 * @dev: FWU metadata device
+	 * @mdata: Copy of the FWU metadata to write
+	 * @primary: If primary or secondary copy of metadata is to be written
 	 *
 	 * Return: 0 if OK, -ve on error
 	 */
-	int (*write_mdata_partition)(struct udevice *dev,
-				     struct fwu_mdata *mdata, uint part_num);
+	int (*write_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
 };
 
 #define FWU_MDATA_VERSION	0x1
@@ -127,100 +78,25 @@ struct fwu_mdata_ops {
 		 0xe1, 0xfc, 0xed, 0xf1, 0xc6, 0xf8)
 
 /**
- * fwu_check_mdata_validity() - Check for validity of the FWU metadata copies
- *
- * Read both the metadata copies from the storage media, verify their
- * checksum, and ascertain that both copies match. If one of the copies
- * has gone bad, restore it from the good copy.
- *
- * Return: 0 if OK, -ve on error
- *
+ * fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata()
  */
-int fwu_check_mdata_validity(void);
+int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
 
 /**
- * fwu_get_mdata_part_num() - Get the FWU metadata partition numbers
- * @dev: FWU metadata device
- * @mdata_parts: array for storing the metadata partition numbers
- *
- * Get the partition numbers on the storage device on which the
- * FWU metadata is stored. Two partition numbers will be returned
- * through the array.
- *
- * Return: 0 if OK, -ve on error
- *
+ * fwu_write_mdata() - Wrapper around fwu_mdata_ops.write_mdata()
  */
-int fwu_get_mdata_part_num(struct udevice *dev, uint *mdata_parts);
+int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
 
 /**
- * fwu_read_mdata_partition() - Read the FWU metadata from a partition
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- * @part_num: Partition number from which FWU metadata is to be read
+ * fwu_get_mdata() - Read, verify and return the FWU metadata
  *
- * Read the FWU metadata from the specified partition number
+ * Read both the metadata copies from the storage media, verify their checksum,
+ * and ascertain that both copies match. If one of the copies has gone bad,
+ * restore it from the good copy.
  *
  * Return: 0 if OK, -ve on error
- *
- */
-int fwu_read_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata,
-			     uint part_num);
-
-/**
- * fwu_write_mdata_partition() - Write the FWU metadata to a partition
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- * @part_num: Partition number to which FWU metadata is to be written
- *
- * Write the FWU metadata to the specified partition number
- *
- * Return: 0 if OK, -ve on error
- *
  */
-int fwu_write_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata,
-			      uint part_num);
-
-/**
- * fwu_get_mdata() - Get a FWU metadata copy
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- *
- * Get a valid copy of the FWU metadata.
- *
- * Note: This function is to be called first when modifying any fields
- * in the metadata. The sequence of calls to modify any field in the
- * metadata would  be 1) fwu_get_mdata 2) Modify metadata, followed by
- * 3) fwu_update_mdata
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_get_mdata(struct udevice *dev, struct fwu_mdata *mdata);
-
-/**
- * fwu_update_mdata() - Update the FWU metadata
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- *
- * Update the FWU metadata structure by writing to the
- * FWU metadata partitions.
- *
- * Note: This function is not to be called directly to update the
- * metadata fields. The sequence of function calls should be
- * 1) fwu_get_mdata() 2) Modify the medata fields 3) fwu_update_mdata()
- *
- * The sequence of updating the partitions should be, update the
- * primary metadata partition (first partition encountered), followed
- * by updating the secondary partition. With this update sequence, in
- * the rare scenario that the two metadata partitions are valid but do
- * not match, maybe due to power outage at the time of updating the
- * metadata copies, the secondary partition can be updated from the
- * primary.
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_update_mdata(struct udevice *dev, struct fwu_mdata *mdata);
+int fwu_get_mdata(struct fwu_mdata *mdata);
 
 /**
  * fwu_get_active_index() - Get active_index from the FWU metadata
@@ -263,18 +139,6 @@ int fwu_set_active_index(uint active_idx);
 int fwu_get_image_index(u8 *image_index);
 
 /**
- * fwu_mdata_check() - Check if the FWU metadata is valid
- * @dev: FWU metadata device
- *
- * Validate both copies of the FWU metadata. If one of the copies
- * has gone bad, restore it from the other copy.
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_mdata_check(struct udevice *dev);
-
-/**
  * fwu_revert_boot_index() - Revert the active index in the FWU metadata
  *
  * Revert the active_index value in the FWU metadata, by swapping the values
@@ -287,20 +151,6 @@ int fwu_mdata_check(struct udevice *dev);
 int fwu_revert_boot_index(void);
 
 /**
- * fwu_verify_mdata() - Verify the FWU metadata
- * @mdata: FWU metadata structure
- * @pri_part: FWU metadata partition is primary or secondary
- *
- * Verify the FWU metadata by computing the CRC32 for the metadata
- * structure and comparing it against the CRC32 value stored as part
- * of the structure.
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_verify_mdata(struct fwu_mdata *mdata, bool pri_part);
-
-/**
  * fwu_accept_image() - Set the Acceptance bit for the image
  * @img_type_id: GUID of the image type for which the accepted bit is to be
  *               cleared
@@ -409,4 +259,28 @@ u8 fwu_empty_capsule_checks_pass(void);
  */
 int fwu_trial_state_ctr_start(void);
 
+/**
+ * fwu_gen_alt_info_from_mtd() - Parse dfu_alt_info from metadata in mtd
+ * @buf: Buffer into which the dfu_alt_info is filled
+ * @len: Maximum characters that can be written in buf
+ * @mtd: Pointer to underlying MTD device
+ *
+ * Parse dfu_alt_info from metadata in mtd. Used for setting the env.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd);
+
+/**
+ * fwu_mtd_get_alt_num() - Mapping of fwu_plat_get_alt_num for MTD device
+ * @image_guid: Image GUID for which DFU alt number needs to be retrieved
+ * @alt_num: Pointer to the alt_num
+ * @mtd_dev: Name of mtd device instance
+ *
+ * To map fwu_plat_get_alt_num onto mtd based metadata implementation.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_mtd_get_alt_num(efi_guid_t *image_guid, u8 *alt_num, const char *mtd_dev);
+
 #endif /* _FWU_H_ */
diff --git a/include/fwu_mdata.h b/include/fwu_mdata.h
index 8fda4f4ac2..56189e2f40 100644
--- a/include/fwu_mdata.h
+++ b/include/fwu_mdata.h
@@ -6,6 +6,7 @@
 #if !defined _FWU_MDATA_H_
 #define _FWU_MDATA_H_
 
+#include <linux/compiler_attributes.h>
 #include <efi.h>
 
 /**
@@ -22,7 +23,7 @@ struct fwu_image_bank_info {
 	efi_guid_t  image_uuid;
 	uint32_t accepted;
 	uint32_t reserved;
-};
+} __packed;
 
 /**
  * struct fwu_image_entry - information for a particular type of image
@@ -38,7 +39,7 @@ struct fwu_image_entry {
 	efi_guid_t image_type_uuid;
 	efi_guid_t location_uuid;
 	struct fwu_image_bank_info img_bank_info[CONFIG_FWU_NUM_BANKS];
-};
+} __packed;
 
 /**
  * struct fwu_mdata - FWU metadata structure for multi-bank updates
@@ -62,6 +63,6 @@ struct fwu_mdata {
 	uint32_t previous_active_index;
 
 	struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK];
-};
+} __packed;
 
 #endif /* _FWU_MDATA_H_ */
diff --git a/include/image-sparse.h b/include/image-sparse.h
index 0572dbd0a2..282a0b2564 100644
--- a/include/image-sparse.h
+++ b/include/image-sparse.h
@@ -7,6 +7,8 @@
 #include <part.h>
 #include <sparse_format.h>
 
+#define FASTBOOT_MAX_BLK_WRITE 16384
+
 #define ROUNDUP(x, y)	(((x) + ((y) - 1)) & ~((y) - 1))
 
 struct sparse_storage {
diff --git a/include/imx_sip.h b/include/imx_sip.h
index 1b873f231b..8a5ca34f39 100644
--- a/include/imx_sip.h
+++ b/include/imx_sip.h
@@ -4,7 +4,7 @@
  */
 
 #ifndef _IMX_SIP_H__
-#define _IMX_SIP_H_
+#define _IMX_SIP_H__
 
 #define IMX_SIP_GPC		0xC2000000
 #define IMX_SIP_GPC_PM_DOMAIN	0x03
@@ -13,8 +13,8 @@
 #define IMX_SIP_BUILDINFO_GET_COMMITHASH	0x00
 
 #define IMX_SIP_SRC		0xC2000005
-#define IMX_SIP_SRC_M4_START	0x00
-#define IMX_SIP_SRC_M4_STARTED	0x01
-#define	IMX_SIP_SRC_M4_STOP	0x02
+#define IMX_SIP_SRC_MCU_START	0x00
+#define IMX_SIP_SRC_MCU_STARTED	0x01
+#define	IMX_SIP_SRC_MCU_STOP	0x02
 
 #endif
diff --git a/include/init.h b/include/init.h
index 8873081685..3bf30476a2 100644
--- a/include/init.h
+++ b/include/init.h
@@ -296,15 +296,20 @@ int checkboard(void);
 int show_board_info(void);
 
 /**
- * Get the uppermost pointer that is valid to access
+ * board_get_usable_ram_top() - get uppermost address for U-Boot relocation
  *
- * Some systems may not map all of their address space. This function allows
- * boards to indicate what their highest support pointer value is for DRAM
- * access.
+ * Some systems have reserved memory areas in high memory. By implementing this
+ * function boards can indicate the highest address value to be used when
+ * relocating U-Boot. The returned address is exclusive (i.e. 1 byte above the
+ * last usable address).
  *
- * @param total_size	Size of U-Boot (unused?)
+ * Due to overflow on systems with 32bit phys_addr_t a value 0 is used instead
+ * of 4GiB.
+ *
+ * @total_size:	monitor length in bytes (size of U-Boot code)
+ * Return:	uppermost address for U-Boot relocation
  */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size);
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size);
 
 int board_early_init_f(void);
 
diff --git a/include/lcd_console.h b/include/lcd_console.h
deleted file mode 100644
index 061a6a41bb..0000000000
--- a/include/lcd_console.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
- */
-
-/* By default we scroll by a single line */
-
-struct console_t {
-	short curr_col, curr_row;
-	short cols, rows;
-	void *fbbase;
-	u32 lcdsizex, lcdsizey, lcdrot;
-	void (*fp_putc_xy)(struct console_t *pcons, ushort x, ushort y, char c);
-	void (*fp_console_moverow)(struct console_t *pcons,
-				   u32 rowdst, u32 rowsrc);
-	void (*fp_console_setrow)(struct console_t *pcons, u32 row, int clr);
-};
-
-/**
- * console_calc_rowcol() - calculate available rows / columns wihtin a given
- * screen-size based on used VIDEO_FONT.
- *
- * @pcons: Pointer to struct console_t
- * @sizex: size X of the screen in pixel
- * @sizey: size Y of the screen in pixel
- */
-void console_calc_rowcol(struct console_t *pcons, u32 sizex, u32 sizey);
-/**
- * lcd_init_console() - Initialize lcd console parameters
- *
- * Setup the address of console base, and the number of rows and columns the
- * console has.
- *
- * @address: Console base address
- * @vl_rows: Number of rows in the console
- * @vl_cols: Number of columns in the console
- * @vl_rot: Rotation of display in degree (0 - 90 - 180 - 270) counterlockwise
- */
-void lcd_init_console(void *address, int vl_cols, int vl_rows, int vl_rot);
-/**
- * lcd_set_col() - Set the number of the current lcd console column
- *
- * Set the number of the console column where the cursor is.
- *
- * @col: Column number
- */
-void lcd_set_col(short col);
-
-/**
- * lcd_set_row() - Set the number of the current lcd console row
- *
- * Set the number of the console row where the cursor is.
- *
- * @row: Row number
- */
-void lcd_set_row(short row);
-
-/**
- * lcd_position_cursor() - Position the cursor on the screen
- *
- * Position the cursor at the given coordinates on the screen.
- *
- * @col: Column number
- * @row: Row number
- */
-void lcd_position_cursor(unsigned col, unsigned row);
-
-/**
- * lcd_get_screen_rows() - Get the total number of screen rows
- *
- * @return: Number of screen rows
- */
-int lcd_get_screen_rows(void);
-
-/**
- * lcd_get_screen_columns() - Get the total number of screen columns
- *
- * @return: Number of screen columns
- */
-int lcd_get_screen_columns(void);
-
-/**
- * lcd_putc() - Print to screen a single character at the location of the cursor
- *
- * @c: The character to print
- */
-void lcd_putc(const char c);
-
-/**
- * lcd_puts() - Print to screen a string at the location of the cursor
- *
- * @s: The string to print
- */
-void lcd_puts(const char *s);
-
-/**
- * lcd_printf() - Print to screen a formatted string at location of the cursor
- *
- * @fmt: The formatted string to print
- * @...: The arguments for the formatted string
- */
-void lcd_printf(const char *fmt, ...);
diff --git a/include/lcdvideo.h b/include/lcdvideo.h
deleted file mode 100644
index f0640a5385..0000000000
--- a/include/lcdvideo.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * MPC823 LCD and Video Controller
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- */
-#ifndef __LCDVIDEO_H__
-#define __LCDVIDEO_H__
-
-
-/* LCD Controller Configuration Register.
-*/
-#define LCCR_BNUM	((uint)0xfffe0000)
-#define LCCR_EIEN	((uint)0x00010000)
-#define LCCR_IEN	((uint)0x00008000)
-#define LCCR_IRQL	((uint)0x00007000)
-#define LCCR_CLKP	((uint)0x00000800)
-#define LCCR_OEP	((uint)0x00000400)
-#define LCCR_HSP	((uint)0x00000200)
-#define LCCR_VSP	((uint)0x00000100)
-#define LCCR_DP		((uint)0x00000080)
-#define LCCR_BPIX	((uint)0x00000060)
-#define LCCR_LBW	((uint)0x00000010)
-#define LCCR_SPLT	((uint)0x00000008)
-#define LCCR_CLOR	((uint)0x00000004)
-#define LCCR_TFT	((uint)0x00000002)
-#define LCCR_PON	((uint)0x00000001)
-
-/* Define the bit shifts to load values into the register.
-*/
-#define LCDBIT(BIT, VAL)	((VAL) << (31 - BIT))
-
-#define LCCR_BNUM_BIT	((uint)14)
-#define LCCR_EIEN_BIT	((uint)15)
-#define LCCR_IEN_BIT	((uint)16)
-#define LCCR_IROL_BIT	((uint)19)
-#define LCCR_CLKP_BIT	((uint)20)
-#define LCCR_OEP_BIT	((uint)21)
-#define LCCR_HSP_BIT	((uint)22)
-#define LCCR_VSP_BIT	((uint)23)
-#define LCCR_DP_BIT	((uint)24)
-#define LCCR_BPIX_BIT	((uint)26)
-#define LCCR_LBW_BIT	((uint)27)
-#define LCCR_SPLT_BIT	((uint)28)
-#define LCCR_CLOR_BIT	((uint)29)
-#define LCCR_TFT_BIT	((uint)30)
-#define LCCR_PON_BIT	((uint)31)
-
-/* LCD Horizontal control register.
-*/
-#define LCHCR_BO	((uint)0x01000000)
-#define LCHCR_AT	((uint)0x00e00000)
-#define LCHCR_HPC	((uint)0x001ffc00)
-#define LCHCR_WBL	((uint)0x000003ff)
-
-#define LCHCR_AT_BIT	((uint)10)
-#define LCHCR_HPC_BIT	((uint)21)
-#define LCHCR_WBL_BIT	((uint)31)
-
-/* LCD Vertical control register.
-*/
-#define LCVCR_VPW	((uint)0xf0000000)
-#define LCVCR_LCD_AC	((uint)0x01e00000)
-#define LCVCR_VPC	((uint)0x001ff800)
-#define LCVCR_WBF	((uint)0x000003ff)
-
-#define LCVCR_VPW_BIT	((uint)3)
-#define LCVCR_LCD_AC_BIT ((uint)10)
-#define LCVCR_VPC_BIT	((uint)20)
-
-#endif /* __LCDVIDEO_H__ */
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
index e1d09884a1..f44e9e8f93 100644
--- a/include/linux/arm-smccc.h
+++ b/include/linux/arm-smccc.h
@@ -1,6 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2015, Linaro Limited
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
  */
 #ifndef __LINUX_ARM_SMCCC_H
 #define __LINUX_ARM_SMCCC_H
@@ -70,6 +74,47 @@ struct arm_smccc_res {
 	unsigned long a3;
 };
 
+#ifdef CONFIG_ARM64
+/**
+ * struct arm_smccc_1_2_regs - Arguments for or Results from SMC call
+ * @a0-a17 argument values from registers 0 to 17
+ */
+struct arm_smccc_1_2_regs {
+	unsigned long a0;
+	unsigned long a1;
+	unsigned long a2;
+	unsigned long a3;
+	unsigned long a4;
+	unsigned long a5;
+	unsigned long a6;
+	unsigned long a7;
+	unsigned long a8;
+	unsigned long a9;
+	unsigned long a10;
+	unsigned long a11;
+	unsigned long a12;
+	unsigned long a13;
+	unsigned long a14;
+	unsigned long a15;
+	unsigned long a16;
+	unsigned long a17;
+};
+
+/**
+ * arm_smccc_1_2_smc() - make SMC calls
+ * @args: arguments passed via struct arm_smccc_1_2_regs
+ * @res: result values via struct arm_smccc_1_2_regs
+ *
+ * This function is used to make SMC calls following SMC Calling Convention
+ * v1.2 or above. The content of the supplied param are copied from the
+ * structure to registers prior to the SMC instruction. The return values
+ * are updated with the content from registers on return from the SMC
+ * instruction.
+ */
+asmlinkage void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
+				  struct arm_smccc_1_2_regs *res);
+#endif
+
 /**
  * struct arm_smccc_quirk - Contains quirk information
  * @id: quirk identification
diff --git a/include/linux/build_bug.h b/include/linux/build_bug.h
index 9c7088bafa..20c2dc7f4b 100644
--- a/include/linux/build_bug.h
+++ b/include/linux/build_bug.h
@@ -4,15 +4,16 @@
 #include <linux/compiler.h>
 
 #ifdef __CHECKER__
-#define __BUILD_BUG_ON_NOT_POWER_OF_2(n) (0)
-#define BUILD_BUG_ON_NOT_POWER_OF_2(n) (0)
 #define BUILD_BUG_ON_ZERO(e) (0)
-#define BUILD_BUG_ON_NULL(e) ((void *)0)
-#define BUILD_BUG_ON_INVALID(e) (0)
-#define BUILD_BUG_ON_MSG(cond, msg) (0)
-#define BUILD_BUG_ON(condition) (0)
-#define BUILD_BUG() (0)
 #else /* __CHECKER__ */
+/*
+ * Force a compilation error if condition is true, but also produce a
+ * result (of value 0 and type int), so the expression can be used
+ * e.g. in a structure initializer (or where-ever else comma expressions
+ * aren't permitted).
+ */
+#define BUILD_BUG_ON_ZERO(e) ((int)sizeof(struct { int:(-!!(e)); }))
+#endif	/* __CHECKER__ */
 
 /* Force a compilation error if a constant expression is not a power of 2 */
 #define __BUILD_BUG_ON_NOT_POWER_OF_2(n)	\
@@ -21,15 +22,6 @@
 	BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0))
 
 /*
- * Force a compilation error if condition is true, but also produce a
- * result (of value 0 and type size_t), so the expression can be used
- * e.g. in a structure initializer (or where-ever else comma expressions
- * aren't permitted).
- */
-#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:(-!!(e)); }))
-#define BUILD_BUG_ON_NULL(e) ((void *)sizeof(struct { int:(-!!(e)); }))
-
-/*
  * BUILD_BUG_ON_INVALID() permits the compiler to check the validity of the
  * expression but avoids the generation of any code, even if that expression
  * has side-effects.
@@ -52,23 +44,9 @@
  * If you have some code which relies on certain constants being equal, or
  * some other compile-time-evaluated condition, you should use BUILD_BUG_ON to
  * detect if someone changes it.
- *
- * The implementation uses gcc's reluctance to create a negative array, but gcc
- * (as of 4.4) only emits that error for obvious cases (e.g. not arguments to
- * inline functions).  Luckily, in 4.3 they added the "error" function
- * attribute just for this type of case.  Thus, we use a negative sized array
- * (should always create an error on gcc versions older than 4.4) and then call
- * an undefined function with the error attribute (should always create an
- * error on gcc 4.3 and later).  If for some reason, neither creates a
- * compile-time error, we'll still have a link-time error, which is harder to
- * track down.
  */
-#ifndef __OPTIMIZE__
-#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
-#else
 #define BUILD_BUG_ON(condition) \
 	BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
-#endif
 
 /**
  * BUILD_BUG - break compile if used.
@@ -98,6 +76,4 @@
 #define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr)
 #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
 
-#endif	/* __CHECKER__ */
-
 #endif	/* _LINUX_BUILD_BUG_H */
diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h
deleted file mode 100644
index 0644d92b3c..0000000000
--- a/include/linux/mc146818rtc.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
- * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
- * derived from Data Sheet, Copyright Motorola 1984 (!).
- * It was written to be part of the Linux operating system.
- */
-/* permission is hereby granted to copy, modify and redistribute this code
- * in terms of the GNU Library General Public License, Version 2 or later,
- * at your option.
- */
-
-#ifndef _MC146818RTC_H
-#define _MC146818RTC_H
-
-#include <asm/io.h>
-#include <linux/rtc.h>          /* get the user-level API */
-#include <asm/mc146818rtc.h>        /* register access macros */
-
-/**********************************************************************
- * register summary
- **********************************************************************/
-#define RTC_SECONDS     0
-#define RTC_SECONDS_ALARM   1
-#define RTC_MINUTES     2
-#define RTC_MINUTES_ALARM   3
-#define RTC_HOURS       4
-#define RTC_HOURS_ALARM     5
-/* RTC_*_alarm is always true if 2 MSBs are set */
-# define RTC_ALARM_DONT_CARE    0xC0
-
-#define RTC_DAY_OF_WEEK     6
-#define RTC_DAY_OF_MONTH    7
-#define RTC_MONTH       8
-#define RTC_YEAR        9
-
-/* control registers - Moto names
- */
-#define RTC_REG_A       10
-#define RTC_REG_B       11
-#define RTC_REG_C       12
-#define RTC_REG_D       13
-
-/**********************************************************************
- * register details
- **********************************************************************/
-#define RTC_FREQ_SELECT RTC_REG_A
-
-/* update-in-progress  - set to "1" 244 microsecs before RTC goes off the bus,
- * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
- * totalling to a max high interval of 2.228 ms.
- */
-# define RTC_UIP        0x80
-# define RTC_DIV_CTL        0x70
-   /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
-#  define RTC_REF_CLCK_4MHZ 0x00
-#  define RTC_REF_CLCK_1MHZ 0x10
-#  define RTC_REF_CLCK_32KHZ    0x20
-   /* 2 values for divider stage reset, others for "testing purposes only" */
-#  define RTC_DIV_RESET1    0x60
-#  define RTC_DIV_RESET2    0x70
-  /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
-# define RTC_RATE_SELECT    0x0F
-
-/**********************************************************************/
-#define RTC_CONTROL RTC_REG_B
-# define RTC_SET 0x80       /* disable updates for clock setting */
-# define RTC_PIE 0x40       /* periodic interrupt enable */
-# define RTC_AIE 0x20       /* alarm interrupt enable */
-# define RTC_UIE 0x10       /* update-finished interrupt enable */
-# define RTC_SQWE 0x08      /* enable square-wave output */
-# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
-# define RTC_24H 0x02       /* 24 hour mode - else hours bit 7 means pm */
-# define RTC_DST_EN 0x01    /* auto switch DST - works f. USA only */
-
-/**********************************************************************/
-#define RTC_INTR_FLAGS  RTC_REG_C
-/* caution - cleared by read */
-# define RTC_IRQF 0x80      /* any of the following 3 is active */
-# define RTC_PF 0x40
-# define RTC_AF 0x20
-# define RTC_UF 0x10
-
-/**********************************************************************/
-#define RTC_VALID   RTC_REG_D
-# define RTC_VRT 0x80       /* valid RAM and time */
-/**********************************************************************/
-#endif /* _MC146818RTC_H */
diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
deleted file mode 100644
index a72cb7d20b..0000000000
--- a/include/linux/mtd/doc2000.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Linux driver for Disk-On-Chip devices
- *
- * Copyright © 1999 Machine Vision Holdings, Inc.
- * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
- * Copyright © 2002-2003 Greg Ungerer <gerg@snapgear.com>
- * Copyright © 2002-2003 SnapGear Inc
- *
- */
-
-#ifndef __MTD_DOC2000_H__
-#define __MTD_DOC2000_H__
-
-#include <linux/mtd/mtd.h>
-#if 0
-#include <linux/mutex.h>
-#endif
-
-#define DoC_Sig1 0
-#define DoC_Sig2 1
-
-#define DoC_ChipID		0x1000
-#define DoC_DOCStatus		0x1001
-#define DoC_DOCControl		0x1002
-#define DoC_FloorSelect		0x1003
-#define DoC_CDSNControl		0x1004
-#define DoC_CDSNDeviceSelect	0x1005
-#define DoC_ECCConf		0x1006
-#define DoC_2k_ECCStatus	0x1007
-
-#define DoC_CDSNSlowIO		0x100d
-#define DoC_ECCSyndrome0	0x1010
-#define DoC_ECCSyndrome1	0x1011
-#define DoC_ECCSyndrome2	0x1012
-#define DoC_ECCSyndrome3	0x1013
-#define DoC_ECCSyndrome4	0x1014
-#define DoC_ECCSyndrome5	0x1015
-#define DoC_AliasResolution	0x101b
-#define DoC_ConfigInput		0x101c
-#define DoC_ReadPipeInit	0x101d
-#define DoC_WritePipeTerm	0x101e
-#define DoC_LastDataRead	0x101f
-#define DoC_NOP			0x1020
-
-#define DoC_Mil_CDSN_IO		0x0800
-#define DoC_2k_CDSN_IO		0x1800
-
-#define DoC_Mplus_NOP			0x1002
-#define DoC_Mplus_AliasResolution	0x1004
-#define DoC_Mplus_DOCControl		0x1006
-#define DoC_Mplus_AccessStatus		0x1008
-#define DoC_Mplus_DeviceSelect		0x1008
-#define DoC_Mplus_Configuration		0x100a
-#define DoC_Mplus_OutputControl		0x100c
-#define DoC_Mplus_FlashControl		0x1020
-#define DoC_Mplus_FlashSelect		0x1022
-#define DoC_Mplus_FlashCmd		0x1024
-#define DoC_Mplus_FlashAddress		0x1026
-#define DoC_Mplus_FlashData0		0x1028
-#define DoC_Mplus_FlashData1		0x1029
-#define DoC_Mplus_ReadPipeInit		0x102a
-#define DoC_Mplus_LastDataRead		0x102c
-#define DoC_Mplus_LastDataRead1		0x102d
-#define DoC_Mplus_WritePipeTerm		0x102e
-#define DoC_Mplus_ECCSyndrome0		0x1040
-#define DoC_Mplus_ECCSyndrome1		0x1041
-#define DoC_Mplus_ECCSyndrome2		0x1042
-#define DoC_Mplus_ECCSyndrome3		0x1043
-#define DoC_Mplus_ECCSyndrome4		0x1044
-#define DoC_Mplus_ECCSyndrome5		0x1045
-#define DoC_Mplus_ECCConf		0x1046
-#define DoC_Mplus_Toggle		0x1046
-#define DoC_Mplus_DownloadStatus	0x1074
-#define DoC_Mplus_CtrlConfirm		0x1076
-#define DoC_Mplus_Power			0x1fff
-
-/* How to access the device?
- * On ARM, it'll be mmap'd directly with 32-bit wide accesses.
- * On PPC, it's mmap'd and 16-bit wide.
- * Others use readb/writeb
- */
-#if defined(__arm__)
-#define ReadDOC_(adr, reg)      ((unsigned char)(*(volatile __u32 *)(((unsigned long)adr)+((reg)<<2))))
-#define WriteDOC_(d, adr, reg)  do{ *(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)) = (__u32)d; wmb();} while(0)
-#define DOC_IOREMAP_LEN 0x8000
-#elif defined(__ppc__)
-#define ReadDOC_(adr, reg)      ((unsigned char)(*(volatile __u16 *)(((unsigned long)adr)+((reg)<<1))))
-#define WriteDOC_(d, adr, reg)  do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0)
-#define DOC_IOREMAP_LEN 0x4000
-#else
-#define ReadDOC_(adr, reg)      readb((void __iomem *)(adr) + (reg))
-#define WriteDOC_(d, adr, reg)  writeb(d, (void __iomem *)(adr) + (reg))
-#define DOC_IOREMAP_LEN 0x2000
-
-#endif
-
-#if defined(__i386__) || defined(__x86_64__)
-#define USE_MEMCPY
-#endif
-
-/* These are provided to directly use the DoC_xxx defines */
-#define ReadDOC(adr, reg)      ReadDOC_(adr,DoC_##reg)
-#define WriteDOC(d, adr, reg)  WriteDOC_(d,adr,DoC_##reg)
-
-#define DOC_MODE_RESET		0
-#define DOC_MODE_NORMAL		1
-#define DOC_MODE_RESERVED1	2
-#define DOC_MODE_RESERVED2	3
-
-#define DOC_MODE_CLR_ERR	0x80
-#define	DOC_MODE_RST_LAT	0x10
-#define	DOC_MODE_BDECT		0x08
-#define DOC_MODE_MDWREN	0x04
-
-#define DOC_ChipID_Doc2k	0x20
-#define DOC_ChipID_Doc2kTSOP	0x21	/* internal number for MTD */
-#define DOC_ChipID_DocMil	0x30
-#define DOC_ChipID_DocMilPlus32	0x40
-#define DOC_ChipID_DocMilPlus16	0x41
-
-#define CDSN_CTRL_FR_B		0x80
-#define CDSN_CTRL_FR_B0		0x40
-#define CDSN_CTRL_FR_B1		0x80
-
-#define CDSN_CTRL_ECC_IO	0x20
-#define CDSN_CTRL_FLASH_IO	0x10
-#define CDSN_CTRL_WP		0x08
-#define CDSN_CTRL_ALE		0x04
-#define CDSN_CTRL_CLE		0x02
-#define CDSN_CTRL_CE		0x01
-
-#define DOC_ECC_RESET		0
-#define DOC_ECC_ERROR		0x80
-#define DOC_ECC_RW		0x20
-#define DOC_ECC__EN		0x08
-#define DOC_TOGGLE_BIT		0x04
-#define DOC_ECC_RESV		0x02
-#define DOC_ECC_IGNORE		0x01
-
-#define DOC_FLASH_CE		0x80
-#define DOC_FLASH_WP		0x40
-#define DOC_FLASH_BANK		0x02
-
-/* We have to also set the reserved bit 1 for enable */
-#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV)
-#define DOC_ECC_DIS (DOC_ECC_RESV)
-
-struct Nand {
-	char floor, chip;
-	unsigned long curadr;
-	unsigned char curmode;
-	/* Also some erase/write/pipeline info when we get that far */
-};
-
-#define MAX_FLOORS 4
-#define MAX_CHIPS 4
-
-#define MAX_FLOORS_MIL 1
-#define MAX_CHIPS_MIL 1
-
-#define MAX_FLOORS_MPLUS 2
-#define MAX_CHIPS_MPLUS 1
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-struct DiskOnChip {
-	unsigned long physadr;
-	void __iomem *virtadr;
-	unsigned long totlen;
-	unsigned char ChipID; /* Type of DiskOnChip */
-	int ioreg;
-
-	unsigned long mfr; /* Flash IDs - only one type of flash per device */
-	unsigned long id;
-	int chipshift;
-	char page256;
-	char pageadrlen;
-	char interleave; /* Internal interleaving - Millennium Plus style */
-	unsigned long erasesize;
-
-	int curfloor;
-	int curchip;
-
-	int numchips;
-	struct Nand *chips;
-	struct mtd_info *nextdoc;
-/* XXX U-BOOT XXX */
-#if 0
-	struct mutex lock;
-#endif
-};
-
-int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]);
-
-/* XXX U-BOOT XXX */
-#if 1
-/*
- * NAND Flash Manufacturer ID Codes
- */
-#define NAND_MFR_TOSHIBA   0x98
-#define NAND_MFR_SAMSUNG   0xec
-#endif
-
-#endif /* __MTD_DOC2000_H__ */
diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h
deleted file mode 100644
index d0558a9826..0000000000
--- a/include/linux/mtd/ndfc.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *  linux/include/linux/mtd/ndfc.h
- *
- *  Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Info:
- *   Contains defines, datastructures for ndfc nand controller
- *
- */
-#ifndef __LINUX_MTD_NDFC_H
-#define __LINUX_MTD_NDFC_H
-
-/* NDFC Register definitions */
-#define NDFC_CMD		0x00
-#define NDFC_ALE		0x04
-#define NDFC_DATA		0x08
-#define NDFC_ECC		0x10
-#define NDFC_BCFG0		0x30
-#define NDFC_BCFG1		0x34
-#define NDFC_BCFG2		0x38
-#define NDFC_BCFG3		0x3c
-#define NDFC_CCR		0x40
-#define NDFC_STAT		0x44
-#define NDFC_HWCTL		0x48
-#define NDFC_REVID		0x50
-
-#define NDFC_STAT_IS_READY	0x01000000
-
-#define NDFC_CCR_RESET_CE	0x80000000 /* CE Reset */
-#define NDFC_CCR_RESET_ECC	0x40000000 /* ECC Reset */
-#define NDFC_CCR_RIE		0x20000000 /* Interrupt Enable on Device Rdy */
-#define NDFC_CCR_REN		0x10000000 /* Enable wait for Rdy in LinearR */
-#define NDFC_CCR_ROMEN		0x08000000 /* Enable ROM In LinearR */
-#define NDFC_CCR_ARE		0x04000000 /* Auto-Read Enable */
-#define NDFC_CCR_BS(x)		(((x) & 0x3) << 24) /* Select Bank on CE[x] */
-#define NDFC_CCR_BS_MASK	0x03000000 /* Select Bank */
-#define NDFC_CCR_ARAC0		0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
-#define NDFC_CCR_ARAC1		0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
-#define NDFC_CCR_ARAC2		0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
-#define NDFC_CCR_ARAC3		0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
-#define NDFC_CCR_ARAC_MASK	0x00003000 /* Auto-Read mode Addr Cycles */
-#define NDFC_CCR_RPG		0x0000C000 /* Auto-Read Page */
-#define NDFC_CCR_EBCC		0x00000004 /* EBC Configuration Completed */
-#define NDFC_CCR_DHC		0x00000002 /* Direct Hardware Control Enable */
-
-#define NDFC_BxCFG_EN		0x80000000 /* Bank Enable */
-#define NDFC_BxCFG_CED		0x40000000 /* nCE Style */
-#define NDFC_BxCFG_SZ_MASK	0x08000000 /* Bank Size */
-#define NDFC_BxCFG_SZ_8BIT	0x00000000 /* 8bit */
-#define NDFC_BxCFG_SZ_16BIT	0x08000000 /* 16bit */
-
-#define NDFC_MAX_BANKS		4
-
-struct ndfc_controller_settings {
-	uint32_t	ccr_settings;
-	uint64_t	ndfc_erpn;
-};
-
-struct ndfc_chip_settings {
-	uint32_t	bank_settings;
-};
-
-#endif
diff --git a/include/linux/stddef.h b/include/linux/stddef.h
index a7f546fdfe..c732eef65a 100644
--- a/include/linux/stddef.h
+++ b/include/linux/stddef.h
@@ -14,13 +14,7 @@
 #include <linux/types.h>
 #endif
 
-#ifndef __CHECKER__
 #undef offsetof
-#ifdef __compiler_offsetof
-#define offsetof(TYPE, MEMBER)	__compiler_offsetof(TYPE, MEMBER)
-#else
-#define offsetof(TYPE, MEMBER)	((size_t)&((TYPE *)0)->MEMBER)
-#endif
-#endif
+#define offsetof(TYPE, MEMBER)	__builtin_offsetof(TYPE, MEMBER)
 
 #endif
diff --git a/include/linux/types.h b/include/linux/types.h
index baa2c491ea..9df930afd1 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -65,7 +65,7 @@ typedef __kernel_ptrdiff_t	ptrdiff_t;
 
 #ifndef _TIME_T
 #define _TIME_T
-typedef __kernel_time_t		time_t;
+typedef long long		time_t;
 #endif
 
 #ifndef _CLOCK_T
diff --git a/include/linux/unaligned/access_ok.h b/include/linux/unaligned/access_ok.h
deleted file mode 100644
index 5f46eee23c..0000000000
--- a/include/linux/unaligned/access_ok.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef _LINUX_UNALIGNED_ACCESS_OK_H
-#define _LINUX_UNALIGNED_ACCESS_OK_H
-
-#include <asm/byteorder.h>
-
-static inline u16 get_unaligned_le16(const void *p)
-{
-	return le16_to_cpup((__le16 *)p);
-}
-
-static inline u32 get_unaligned_le32(const void *p)
-{
-	return le32_to_cpup((__le32 *)p);
-}
-
-static inline u64 get_unaligned_le64(const void *p)
-{
-	return le64_to_cpup((__le64 *)p);
-}
-
-static inline u16 get_unaligned_be16(const void *p)
-{
-	return be16_to_cpup((__be16 *)p);
-}
-
-static inline u32 get_unaligned_be32(const void *p)
-{
-	return be32_to_cpup((__be32 *)p);
-}
-
-static inline u64 get_unaligned_be64(const void *p)
-{
-	return be64_to_cpup((__be64 *)p);
-}
-
-static inline void put_unaligned_le16(u16 val, void *p)
-{
-	*((__le16 *)p) = cpu_to_le16(val);
-}
-
-static inline void put_unaligned_le32(u32 val, void *p)
-{
-	*((__le32 *)p) = cpu_to_le32(val);
-}
-
-static inline void put_unaligned_le64(u64 val, void *p)
-{
-	*((__le64 *)p) = cpu_to_le64(val);
-}
-
-static inline void put_unaligned_be16(u16 val, void *p)
-{
-	*((__be16 *)p) = cpu_to_be16(val);
-}
-
-static inline void put_unaligned_be32(u32 val, void *p)
-{
-	*((__be32 *)p) = cpu_to_be32(val);
-}
-
-static inline void put_unaligned_be64(u64 val, void *p)
-{
-	*((__be64 *)p) = cpu_to_be64(val);
-}
-
-#endif /* _LINUX_UNALIGNED_ACCESS_OK_H */
diff --git a/include/linux/usb/phy-rockchip-usbdp.h b/include/linux/usb/phy-rockchip-usbdp.h
new file mode 100644
index 0000000000..8acfa6ddf5
--- /dev/null
+++ b/include/linux/usb/phy-rockchip-usbdp.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Rockchip USBDP Combo PHY with Samsung IP block driver
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __PHY_ROCKCHIP_USBDP_H_
+#define __PHY_ROCKCHIP_USBDP_H_
+
+#include <linux/bitops.h>
+
+/* RK3588 USBDP PHY Register Definitions */
+
+#define UDPHY_PCS				0x4000
+#define UDPHY_PMA				0x8000
+
+/* VO0 GRF Registers */
+#define RK3588_GRF_VO0_CON0			0x0000
+#define RK3588_GRF_VO0_CON2			0x0008
+#define DP_SINK_HPD_CFG				BIT(11)
+#define DP_SINK_HPD_SEL				BIT(10)
+#define DP_AUX_DIN_SEL				BIT(9)
+#define DP_AUX_DOUT_SEL				BIT(8)
+#define DP_LANE_SEL_N(n)			GENMASK(2 * (n) + 1, 2 * (n))
+#define DP_LANE_SEL_ALL				GENMASK(7, 0)
+#define PHY_AUX_DP_DATA_POL_NORMAL		0
+#define PHY_AUX_DP_DATA_POL_INVERT		1
+
+/* PMA CMN Registers */
+#define CMN_LANE_MUX_AND_EN_OFFSET		0x0288	/* cmn_reg00A2 */
+#define CMN_DP_LANE_MUX_N(n)			BIT((n) + 4)
+#define CMN_DP_LANE_EN_N(n)			BIT(n)
+#define CMN_DP_LANE_MUX_ALL			GENMASK(7, 4)
+#define CMN_DP_LANE_EN_ALL			GENMASK(3, 0)
+#define PHY_LANE_MUX_USB			0
+#define PHY_LANE_MUX_DP				1
+
+#define CMN_DP_LINK_OFFSET			0x28c	/*cmn_reg00A3 */
+#define CMN_DP_TX_LINK_BW			GENMASK(6, 5)
+#define CMN_DP_TX_LANE_SWAP_EN			BIT(2)
+
+#define CMN_SSC_EN_OFFSET			0x2d0	/* cmn_reg00B4 */
+#define CMN_ROPLL_SSC_EN			BIT(1)
+#define CMN_LCPLL_SSC_EN			BIT(0)
+
+#define CMN_ANA_LCPLL_DONE_OFFSET		0x0350	/* cmn_reg00D4 */
+#define CMN_ANA_LCPLL_LOCK_DONE			BIT(7)
+#define CMN_ANA_LCPLL_AFC_DONE			BIT(6)
+
+#define CMN_ANA_ROPLL_DONE_OFFSET		0x0354	/* cmn_reg00D5 */
+#define CMN_ANA_ROPLL_LOCK_DONE			BIT(1)
+#define CMN_ANA_ROPLL_AFC_DONE			BIT(0)
+
+#define CMN_DP_RSTN_OFFSET			0x038c	/* cmn_reg00E3 */
+#define CMN_DP_INIT_RSTN			BIT(3)
+#define CMN_DP_CMN_RSTN				BIT(2)
+#define CMN_CDR_WTCHDG_EN			BIT(1)
+#define CMN_CDR_WTCHDG_MSK_CDR_EN		BIT(0)
+
+#define TRSV_ANA_TX_CLK_OFFSET_N(n)		(0x854 + (n) * 0x800)	/* trsv_reg0215 */
+#define LN_ANA_TX_SER_TXCLK_INV			BIT(1)
+
+#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET		0x0b84	/* trsv_reg02E1 */
+#define TRSV_LN0_MON_RX_CDR_LOCK_DONE		BIT(0)
+
+#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET		0x1b84	/* trsv_reg06E1 */
+#define TRSV_LN2_MON_RX_CDR_LOCK_DONE		BIT(0)
+
+#endif
diff --git a/include/linux_logo.h b/include/linux_logo.h
deleted file mode 100644
index 9aa712eb4e..0000000000
--- a/include/linux_logo.h
+++ /dev/null
@@ -1,1445 +0,0 @@
-/* $Id: linux_logo.h,v 1.5 1998/07/30 16:30:58 jj Exp $
- * include/linux/linux_logo.h: This is a linux logo
- *                             to be displayed on boot.
- *
- * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu)
- * Copyright (C) 1996,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- *
- * You can put anything here, but:
- * LINUX_LOGO_COLORS has to be less than 224
- * image size has to be 80x80
- * values have to start from 0x20
- * (i.e. RGB(linux_logo_red[0],
- *           linux_logo_green[0],
- *           linux_logo_blue[0]) is color 0x20)
- * BW image has to be 80x80 as well, with MS bit
- * on the left
- * Serial_console ascii image can be any size,
- * but should contain %s to display the version
- */
-
-#if LINUX_LOGO_COLORS == 214
-
-unsigned char linux_logo_red[] __initdata = {
-  0x02, 0x9E, 0xE9, 0xC4, 0x50, 0xC9, 0xC4, 0xE9,
-  0x65, 0xE3, 0xC2, 0x25, 0xA4, 0xEC, 0x90, 0xA6,
-  0xC4, 0x6A, 0xD1, 0xF3, 0x12, 0xED, 0xA0, 0xC2,
-  0xB8, 0xD5, 0xDB, 0xD2, 0x3E, 0x16, 0xEB, 0x54,
-  0xA9, 0xCD, 0xF5, 0x0A, 0xBA, 0xB3, 0xDC, 0x74,
-  0xCE, 0xF6, 0xD3, 0xC5, 0xEA, 0xB8, 0xED, 0x5E,
-  0xE5, 0x26, 0xF4, 0xA9, 0x82, 0x94, 0xE6, 0x38,
-  0xF2, 0x0F, 0x7F, 0x49, 0xE5, 0xF4, 0xD3, 0xC3,
-  0xC2, 0x1E, 0xD5, 0xC6, 0xA4, 0xFA, 0x0A, 0xBA,
-  0xD4, 0xEB, 0xEA, 0xEC, 0xA8, 0xBC, 0xB4, 0xDC,
-  0x84, 0xE4, 0xCE, 0xEC, 0x92, 0xCD, 0xDC, 0x8B,
-  0xCC, 0x1E, 0xF6, 0xB2, 0x60, 0x2A, 0x96, 0x52,
-  0x0F, 0xBD, 0xFA, 0xCC, 0xB8, 0x7A, 0x4C, 0xD2,
-  0x06, 0xEF, 0x44, 0x64, 0xF4, 0xBA, 0xCE, 0xE6,
-  0x8A, 0x6F, 0x3C, 0x70, 0x7C, 0x9C, 0xBA, 0xDF,
-  0x2C, 0x4D, 0x3B, 0xCA, 0xDE, 0xCE, 0xEE, 0x46,
-  0x6A, 0xAC, 0x96, 0xE5, 0x96, 0x7A, 0xBA, 0xB6,
-  0xE2, 0x7E, 0xAA, 0xC5, 0x96, 0x9E, 0xC2, 0xAA,
-  0xDA, 0x35, 0xB6, 0x82, 0x88, 0xBE, 0xC2, 0x9E,
-  0xB4, 0xD5, 0xDA, 0x9C, 0xA0, 0xD0, 0xA8, 0xC7,
-  0x72, 0xF2, 0xDB, 0x76, 0xDC, 0xBE, 0xAA, 0xF4,
-  0x87, 0x2F, 0x53, 0x8E, 0x36, 0xCE, 0xE6, 0xCA,
-  0xCB, 0xE4, 0xD6, 0xAA, 0x42, 0x5D, 0xB4, 0x59,
-  0x1C, 0xC8, 0x96, 0x6C, 0xDA, 0xCE, 0xE6, 0xCB,
-  0x96, 0x16, 0xFA, 0xBE, 0xAE, 0xFE, 0x6E, 0xD6,
-  0xCE, 0xB6, 0xE5, 0xED, 0xDB, 0xDC, 0xF4, 0x72,
-  0x1F, 0xAE, 0xE6, 0xC2, 0xCA, 0xC4
-};
-
-unsigned char linux_logo_green[] __initdata = {
-  0x02, 0x88, 0xC4, 0x85, 0x44, 0xA2, 0xA8, 0xE5,
-  0x65, 0xA6, 0xC2, 0x24, 0xA4, 0xB4, 0x62, 0x86,
-  0x94, 0x44, 0xD2, 0xB6, 0x12, 0xD4, 0x73, 0x96,
-  0x92, 0x95, 0xB2, 0xC2, 0x36, 0x0E, 0xBC, 0x54,
-  0x75, 0xA5, 0xF5, 0x0A, 0xB2, 0x83, 0xC2, 0x74,
-  0x9B, 0xBD, 0xA2, 0xCA, 0xDA, 0x8C, 0xCB, 0x42,
-  0xAC, 0x12, 0xDA, 0x7B, 0x54, 0x94, 0xD2, 0x24,
-  0xBE, 0x06, 0x65, 0x33, 0xBB, 0xBC, 0xAB, 0x8C,
-  0x92, 0x1E, 0x9B, 0xB6, 0x6E, 0xFB, 0x04, 0xA2,
-  0xC8, 0xBD, 0xAD, 0xEC, 0x92, 0xBC, 0x7B, 0x9D,
-  0x84, 0xC4, 0xC4, 0xB4, 0x6C, 0x93, 0xA3, 0x5E,
-  0x8D, 0x13, 0xD6, 0x82, 0x4C, 0x2A, 0x7A, 0x5A,
-  0x0D, 0x82, 0xBB, 0xCC, 0x8B, 0x6A, 0x3C, 0xBE,
-  0x06, 0xC4, 0x44, 0x45, 0xDB, 0x96, 0xB6, 0xDE,
-  0x8A, 0x4D, 0x3C, 0x5A, 0x7C, 0x9C, 0xAA, 0xCB,
-  0x1C, 0x4D, 0x2E, 0xB2, 0xBE, 0xAA, 0xDE, 0x3E,
-  0x6A, 0xAC, 0x82, 0xE5, 0x72, 0x62, 0x92, 0x9E,
-  0xCA, 0x4A, 0x8E, 0xBE, 0x86, 0x6B, 0xAA, 0x9A,
-  0xBE, 0x34, 0xAB, 0x76, 0x6E, 0x9A, 0x9E, 0x62,
-  0x76, 0xCE, 0xD3, 0x92, 0x7C, 0xB8, 0x7E, 0xC6,
-  0x5E, 0xE2, 0xC3, 0x54, 0xAA, 0x9E, 0x8A, 0xCA,
-  0x63, 0x2D, 0x3B, 0x8E, 0x1A, 0x9E, 0xC2, 0xA6,
-  0xCB, 0xDC, 0xD6, 0x8E, 0x26, 0x5C, 0xB4, 0x45,
-  0x1C, 0xB8, 0x6E, 0x4C, 0xBC, 0xAE, 0xD6, 0x92,
-  0x63, 0x16, 0xF6, 0x8C, 0x7A, 0xFE, 0x6E, 0xBA,
-  0xC6, 0x86, 0xAA, 0xAE, 0xDB, 0xA4, 0xD4, 0x56,
-  0x0E, 0x6E, 0xB6, 0xB2, 0xBE, 0xBE
-};
-
-unsigned char linux_logo_blue[] __initdata = {
-  0x04, 0x28, 0x10, 0x0B, 0x14, 0x14, 0x74, 0xC7,
-  0x64, 0x0E, 0xC3, 0x24, 0xA4, 0x0C, 0x10, 0x20,
-  0x0D, 0x04, 0xD1, 0x0D, 0x13, 0x22, 0x0A, 0x40,
-  0x14, 0x0C, 0x11, 0x94, 0x0C, 0x08, 0x0B, 0x56,
-  0x09, 0x47, 0xF4, 0x0B, 0x9C, 0x07, 0x54, 0x74,
-  0x0F, 0x0C, 0x0F, 0xC7, 0x6C, 0x14, 0x14, 0x11,
-  0x0B, 0x04, 0x12, 0x0C, 0x05, 0x94, 0x94, 0x0A,
-  0x34, 0x09, 0x14, 0x08, 0x2F, 0x15, 0x19, 0x11,
-  0x28, 0x0C, 0x0B, 0x94, 0x08, 0xFA, 0x08, 0x7C,
-  0xBC, 0x15, 0x0A, 0xEC, 0x64, 0xBB, 0x0A, 0x0C,
-  0x84, 0x2C, 0xA0, 0x15, 0x10, 0x0D, 0x0B, 0x0E,
-  0x0A, 0x07, 0x10, 0x3C, 0x24, 0x2C, 0x28, 0x5C,
-  0x0A, 0x0D, 0x0A, 0xC1, 0x22, 0x4C, 0x10, 0x94,
-  0x04, 0x0F, 0x45, 0x08, 0x31, 0x54, 0x3C, 0xBC,
-  0x8C, 0x09, 0x3C, 0x18, 0x7C, 0x9C, 0x7C, 0x91,
-  0x0C, 0x4D, 0x17, 0x74, 0x0C, 0x48, 0x9C, 0x3C,
-  0x6A, 0xAC, 0x5C, 0xE3, 0x29, 0x3C, 0x2C, 0x7C,
-  0x6C, 0x04, 0x14, 0xA9, 0x74, 0x07, 0x2C, 0x74,
-  0x4C, 0x34, 0x97, 0x5C, 0x38, 0x0C, 0x5C, 0x04,
-  0x0C, 0xBA, 0xBC, 0x78, 0x18, 0x88, 0x24, 0xC2,
-  0x3C, 0xB4, 0x87, 0x0C, 0x14, 0x4C, 0x3C, 0x10,
-  0x17, 0x2C, 0x0A, 0x8C, 0x04, 0x1C, 0x44, 0x2C,
-  0xCD, 0xD8, 0xD4, 0x34, 0x0C, 0x5B, 0xB4, 0x1E,
-  0x1D, 0xAC, 0x24, 0x18, 0x20, 0x5C, 0xB4, 0x1C,
-  0x09, 0x14, 0xFC, 0x0C, 0x10, 0xFC, 0x6C, 0x7C,
-  0xB4, 0x1C, 0x15, 0x17, 0xDB, 0x18, 0x21, 0x24,
-  0x04, 0x04, 0x44, 0x8C, 0x8C, 0xB7
-};
-
-unsigned char linux_logo[] __initdata = {
-  0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, 0x2C, 0x2C,
-  0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, 0x2C, 0x95,
-  0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, 0xD6, 0x2C,
-  0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, 0x6D, 0xD6,
-  0xA1, 0x2C, 0x55, 0x95, 0x2C, 0x2C, 0x55, 0x55,
-  0x95, 0xA1, 0xA1, 0xA1, 0x6D, 0xBF, 0x2A, 0x2A,
-  0xBF, 0x83, 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1,
-  0x2C, 0x2C, 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95,
-  0x2C, 0x95, 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6,
-  0xD6, 0x2C, 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A,
-  0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, 0x2C, 0x95,
-  0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0xCB,
-  0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, 0xA1, 0x2C,
-  0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, 0xA1, 0x2C,
-  0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x2C, 0x2C,
-  0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xD6, 0xD6, 0xD6,
-  0xD6, 0xD6, 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C,
-  0x2C, 0x95, 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55,
-  0x55, 0xCB, 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6,
-  0xA1, 0x2C, 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6,
-  0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1, 0x2C, 0x95,
-  0x55, 0x55, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x70,
-  0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
-  0x95, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C,
-  0x95, 0x55, 0xCB, 0x95, 0xD6, 0xA1, 0x2C, 0x95,
-  0xA1, 0xD6, 0xD6, 0xA1, 0xA1, 0xD6, 0xA1, 0xA1,
-  0xA1, 0x2C, 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1,
-  0x2C, 0x95, 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55,
-  0x55, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6,
-  0xA1, 0x2C, 0x95, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
-  0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
-  0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0xCB,
-  0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
-  0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x95,
-  0x55, 0x55, 0x2C, 0x3F, 0x80, 0x20, 0x88, 0x88,
-  0x88, 0x20, 0x88, 0xB1, 0x2C, 0xA1, 0x2C, 0x2C,
-  0x95, 0xCB, 0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6,
-  0xA1, 0x95, 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55,
-  0xCB, 0xCB, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6,
-  0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
-  0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C,
-  0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55,
-  0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x95,
-  0x55, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
-  0x2C, 0x94, 0x80, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x88, 0x92, 0xA1, 0x95,
-  0x55, 0x90, 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6,
-  0xA1, 0x2C, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55,
-  0x55, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1,
-  0x2C, 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95,
-  0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0x95,
-  0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, 0x2C, 0x2C,
-  0xA1, 0xD6, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, 0x55,
-  0x55, 0x55, 0x95, 0x95, 0x2C, 0x95, 0x95, 0xD6,
-  0xB1, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x80, 0x34, 0x88, 0x43, 0x47,
-  0x95, 0xCB, 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
-  0xA1, 0x95, 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55,
-  0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0x2C,
-  0x55, 0x55, 0x55, 0x55, 0x2C, 0x95, 0x2C, 0x2C,
-  0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x55,
-  0x90, 0x70, 0x90, 0x55, 0x95, 0x95, 0xA1, 0xA1,
-  0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x95,
-  0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD5,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x88, 0x7D, 0x3F, 0xB1, 0x80, 0x20,
-  0x99, 0x2C, 0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1,
-  0x2C, 0x55, 0x90, 0x70, 0x90, 0x55, 0x95, 0x95,
-  0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
-  0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
-  0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1, 0x95, 0xCB,
-  0x70, 0x94, 0x90, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
-  0x2C, 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95,
-  0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0xA1, 0x88,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xB1, 0x47, 0xD5, 0x7D, 0x43,
-  0x20, 0x70, 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
-  0x95, 0xCB, 0x70, 0x94, 0x90, 0x55, 0x95, 0xA1,
-  0xA1, 0xA1, 0x2C, 0x95, 0x2C, 0x2C, 0x95, 0x95,
-  0x95, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95,
-  0x95, 0x90, 0x55, 0x2C, 0xD6, 0xD6, 0x2C, 0x90,
-  0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
-  0x95, 0x95, 0x95, 0x2C, 0x2C, 0x95, 0x55, 0x55,
-  0xCB, 0xCB, 0xCB, 0x55, 0xCB, 0x55, 0x47, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x88, 0xB1, 0x3F, 0x92, 0x2B, 0x80,
-  0x20, 0x80, 0xD6, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
-  0x2C, 0x90, 0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6,
-  0xD6, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x95,
-  0x95, 0x55, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x55,
-  0xD6, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x55, 0x70,
-  0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x95,
-  0x55, 0x55, 0x55, 0x95, 0x55, 0x55, 0xCB, 0x90,
-  0x70, 0x90, 0xCB, 0x55, 0x55, 0xA1, 0xD8, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x88, 0xD8, 0xE1, 0x88, 0x20, 0x20,
-  0x88, 0x88, 0xE6, 0x55, 0x2C, 0xA1, 0xD6, 0xA1,
-  0x55, 0x70, 0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
-  0xA1, 0x95, 0x55, 0x55, 0x95, 0x95, 0x55, 0x55,
-  0x90, 0x90, 0x90, 0x90, 0xCB, 0x55, 0x55, 0x55,
-  0xD6, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0xCB, 0x70,
-  0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x55,
-  0xCB, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
-  0x55, 0x95, 0x2C, 0x95, 0x2C, 0xD6, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x80, 0xD6, 0xA1, 0xD6, 0xD6, 0xA1,
-  0xCB, 0x70, 0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C,
-  0x2C, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0x55, 0x55,
-  0x55, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x94,
-  0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95, 0xCB, 0x55,
-  0x90, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x95, 0xA1,
-  0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x95, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x88, 0x95, 0xA1, 0xA1, 0xA1, 0x55,
-  0x70, 0x94, 0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95,
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-  0xD6, 0x2C, 0x70, 0x95, 0xAC, 0xC0, 0xDB, 0xEF,
-  0xEF, 0xA2, 0xE8, 0x95, 0x95, 0xA1, 0xD6, 0xA1,
-  0x95, 0x55, 0x2C, 0x95, 0x55, 0x70, 0x70, 0x70,
-  0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55,
-  0x70, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
-  0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x55,
-  0x55, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55, 0x95,
-  0xA1, 0xF5, 0xBF, 0xBF, 0xA1, 0x95, 0x95, 0x95,
-  0x95, 0x55, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x95,
-  0x95, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1,
-  0x2C, 0x55, 0x70, 0x94, 0x90, 0x2C, 0x6D, 0x6D,
-  0x6D, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1,
-  0x2C, 0x55, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55,
-  0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB,
-  0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
-  0xA1, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x95,
-  0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
-  0x6D, 0xBF, 0x6D, 0x2C, 0x55, 0x55, 0x95, 0x95,
-  0xCB, 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x95,
-  0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
-  0xA1, 0x95, 0xCB, 0xCB, 0x95, 0x95, 0x2C, 0x2C,
-  0x2C, 0xA1, 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C,
-  0x2C, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
-  0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55,
-  0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
-  0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x95,
-  0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6,
-  0x6D, 0x6D, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0x55,
-  0x90, 0x70, 0xCB, 0xCB, 0x90, 0xCB, 0x95, 0x95,
-  0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0xA1,
-  0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
-  0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C,
-  0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1,
-  0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55
-};
-
-#endif
-
-#ifdef INCLUDE_LINUX_LOGOBW
-
-unsigned char linux_logo_bw[] __initdata = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x3F,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F,
-  0xFE, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFE, 0x3F, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xC7, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xC3,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF,
-  0xFB, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFD, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF,
-  0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xF9, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xF9, 0xCF, 0xC3, 0xF8, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x87, 0x81, 0xF9,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xA7,
-  0x99, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xF9, 0xF3, 0xBC, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xF9, 0xE3, 0xBC, 0xF9, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, 0x3C, 0xF9,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0,
-  0x19, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xF9, 0xC0, 0x03, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80,
-  0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xF9, 0xC0, 0x21, 0xD8, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xF9, 0xB1, 0x80, 0xEC, 0xC0, 0x1F,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x90, 0x00, 0xE4,
-  0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x8C,
-  0xC0, 0x7C, 0x04, 0x81, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xE3, 0x80, 0x00, 0x7C, 0x40, 0x11, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xE3, 0x80, 0x00, 0x7F, 0xD2, 0x29,
-  0xFF, 0xFF, 0xFF, 0xFF, 0x87, 0x00, 0x00, 0x3F,
-  0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0x0E, 0x00,
-  0x00, 0x3F, 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF,
-  0x1E, 0x00, 0x00, 0x1F, 0x80, 0x19, 0xFF, 0xFF,
-  0xFF, 0xFE, 0x1C, 0x00, 0x00, 0x1E, 0x80, 0x19,
-  0xFF, 0xFF, 0xFF, 0xFE, 0x3C, 0x00, 0x00, 0x1E,
-  0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, 0x7C, 0x00,
-  0x00, 0x0F, 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC,
-  0xF8, 0x00, 0x00, 0x0E, 0x80, 0x11, 0xFF, 0xFF,
-  0xFF, 0xFC, 0xF8, 0x00, 0x00, 0x06, 0x00, 0x11,
-  0xFF, 0xFF, 0xFF, 0xF8, 0xF8, 0x00, 0x00, 0x06,
-  0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xF9, 0xF0, 0x00,
-  0x00, 0x02, 0x00, 0x09, 0xFF, 0xFF, 0xFF, 0xF1,
-  0xF0, 0x00, 0x00, 0x02, 0x80, 0x10, 0xFF, 0xFF,
-  0xFF, 0xF1, 0xE0, 0x00, 0x00, 0x00, 0x97, 0x10,
-  0xFF, 0xFF, 0xFF, 0xE3, 0xE0, 0x00, 0x00, 0x00,
-  0xDF, 0xF0, 0xFF, 0xFF, 0xFF, 0xE3, 0xC0, 0x00,
-  0x00, 0x00, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xC7,
-  0xC0, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
-  0xFF, 0xC7, 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8,
-  0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00, 0x00, 0x01,
-  0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00,
-  0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x9F,
-  0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
-  0xFF, 0x9F, 0x80, 0x00, 0x00, 0x01, 0x80, 0x18,
-  0xFF, 0xFF, 0xFF, 0x9E, 0x80, 0x00, 0x00, 0x03,
-  0xA8, 0x11, 0xFF, 0xFF, 0xFF, 0x9F, 0x80, 0x00,
-  0x00, 0x02, 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0x99,
-  0x80, 0x00, 0x00, 0x00, 0x00, 0x09, 0xFF, 0xFF,
-  0xFF, 0x00, 0x80, 0x00, 0x00, 0x01, 0xC0, 0x01,
-  0xFF, 0xFF, 0xFE, 0x20, 0x60, 0x00, 0x00, 0x00,
-  0xFF, 0xC3, 0xFF, 0xFF, 0xF8, 0x00, 0x30, 0x00,
-  0x00, 0x00, 0xFF, 0x0F, 0xFF, 0xFF, 0xC0, 0x40,
-  0x38, 0x00, 0x00, 0x00, 0xFE, 0x47, 0xFF, 0xFF,
-  0x81, 0x00, 0x1C, 0x00, 0x00, 0x00, 0xFC, 0x23,
-  0xFF, 0xFF, 0x90, 0x00, 0x1E, 0x00, 0x00, 0x00,
-  0x78, 0x11, 0xFF, 0xFF, 0x80, 0x00, 0x0F, 0x80,
-  0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x00,
-  0x07, 0xC0, 0x00, 0x00, 0x00, 0x08, 0xFF, 0xFF,
-  0xC0, 0x00, 0x07, 0xC0, 0x00, 0x00, 0x00, 0x04,
-  0x7F, 0xFF, 0x80, 0x00, 0x03, 0xC0, 0x00, 0x10,
-  0x00, 0x00, 0x1F, 0xFF, 0x80, 0x00, 0x01, 0x80,
-  0x00, 0x30, 0x00, 0x00, 0x0F, 0xFF, 0x80, 0x00,
-  0x00, 0x00, 0x00, 0x70, 0x00, 0x01, 0x4F, 0xFF,
-  0x80, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00,
-  0x0F, 0xFF, 0xC0, 0x00, 0x00, 0x80, 0x03, 0xF0,
-  0x00, 0x00, 0x8F, 0xFF, 0x80, 0x00, 0x00, 0x40,
-  0x0F, 0xF0, 0x00, 0x04, 0x1F, 0xFF, 0x80, 0x00,
-  0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x10, 0x1F, 0xFF,
-  0xC0, 0x00, 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x40,
-  0xFF, 0xFF, 0x98, 0x00, 0x00, 0xFF, 0xFF, 0xF0,
-  0x00, 0x83, 0xFF, 0xFF, 0x81, 0xE0, 0x01, 0xFF,
-  0xFF, 0xF8, 0x02, 0x07, 0xFF, 0xFF, 0x80, 0x3F,
-  0x07, 0xE0, 0x00, 0x1C, 0x0C, 0x1F, 0xFF, 0xFF,
-  0xF8, 0x03, 0xFF, 0x80, 0x00, 0x1F, 0x78, 0x1F,
-  0xFF, 0xFF, 0xFF, 0x80, 0x7F, 0x00, 0x07, 0x0F,
-  0xF0, 0x7F, 0xFF, 0xFF, 0xFF, 0xFE, 0x0C, 0x07,
-  0xFF, 0x83, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0x00, 0x1F, 0xFF, 0xC0, 0x03, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x07, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-};
-
-#endif
-
-#ifdef INCLUDE_LINUX_LOGO16
-
-unsigned char linux_logo16_red[] __initdata = {
-    0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x35, 0x83, 0xa5,
-    0x65, 0x8f, 0x98, 0xc9, 0xdb, 0xe1, 0xe7, 0xf8
-};
-
-unsigned char linux_logo16_green[] __initdata = {
-    0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x2e, 0x83, 0xa5,
-    0x65, 0x6e, 0x98, 0x89, 0xbf, 0xac, 0xda, 0xf8
-};
-
-unsigned char linux_logo16_blue[] __initdata = {
-    0x00, 0x90, 0xaf, 0x9c, 0xf7, 0x2b, 0x82, 0xa5,
-    0x65, 0x41, 0x97, 0x1e, 0x60, 0x29, 0xa5, 0xf8
-};
-
-unsigned char linux_logo16[] __initdata = {
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa1, 0x11, 0x11,
-    0x61, 0x16, 0x66, 0x66, 0x11, 0x11, 0x11, 0x11,
-    0x11, 0x11, 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0xa8, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x87, 0x77, 0x77, 0x77, 0x77,
-    0x77, 0x77, 0x73, 0x33, 0x33, 0x3a, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x77, 0x77, 0x77, 0x77,
-    0x77, 0x27, 0x77, 0x77, 0x77, 0x33, 0x3a, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xa3, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x55, 0x50, 0x08, 0x33, 0x77, 0x77,
-    0x77, 0x72, 0x72, 0x27, 0x77, 0x77, 0x33, 0x33,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xa3, 0x33, 0x33, 0x77, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x58, 0x85, 0x00, 0x11, 0x11, 0xaa,
-    0xa3, 0x37, 0x77, 0x72, 0x22, 0x22, 0x77, 0x73,
-    0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3,
-    0x33, 0x37, 0x77, 0x33, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x56, 0x85, 0x00, 0x06, 0x66, 0x11,
-    0x11, 0x1a, 0xa3, 0x37, 0x77, 0x72, 0x22, 0x77,
-    0x73, 0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
-    0x33, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x55, 0x00, 0x00, 0x06, 0x66, 0x66,
-    0x66, 0x66, 0x11, 0x1a, 0xa3, 0x77, 0x72, 0x22,
-    0x77, 0x73, 0x3a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33,
-    0x33, 0x33, 0x33, 0xa0, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x11,
-    0x66, 0x66, 0x66, 0x66, 0x11, 0xa3, 0x77, 0x22,
-    0x22, 0x77, 0x33, 0x33, 0xaa, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33,
-    0x33, 0x3a, 0xa1, 0x10, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x33,
-    0xaa, 0x11, 0x16, 0x66, 0x66, 0x61, 0x1a, 0x37,
-    0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x33,
-    0x3a, 0xa1, 0x11, 0x10, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x22,
-    0x22, 0x77, 0x3a, 0x11, 0x66, 0x66, 0x66, 0x1a,
-    0x37, 0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33, 0x3a,
-    0xa1, 0x11, 0x11, 0x10, 0x00, 0x00, 0x50, 0x00,
-    0x00, 0x05, 0x80, 0x50, 0x00, 0x00, 0x07, 0x72,
-    0x22, 0x22, 0x22, 0x73, 0xa1, 0x66, 0x66, 0x61,
-    0x1a, 0x77, 0x22, 0x27, 0x73, 0x33, 0xaa, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x3a, 0xaa,
-    0x11, 0x11, 0x1a, 0xa0, 0x08, 0x71, 0x05, 0x00,
-    0x00, 0x12, 0x22, 0x50, 0x00, 0x00, 0x07, 0x77,
-    0x77, 0x72, 0x22, 0x22, 0x27, 0x31, 0x16, 0x66,
-    0x61, 0x13, 0x77, 0x22, 0x77, 0x33, 0x3a, 0xaa,
-    0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xa1,
-    0x11, 0x1a, 0x33, 0x70, 0x07, 0x2e, 0x70, 0x00,
-    0x01, 0x44, 0x42, 0x60, 0x00, 0x00, 0x02, 0x22,
-    0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x31, 0x66,
-    0x66, 0x61, 0xa3, 0x72, 0x22, 0x77, 0x33, 0xaa,
-    0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xaa, 0x11,
-    0x1a, 0x33, 0x77, 0x30, 0x04, 0x82, 0x40, 0x00,
-    0x54, 0x48, 0x54, 0x40, 0x00, 0x00, 0x01, 0xaa,
-    0x32, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x31,
-    0x66, 0x66, 0x11, 0x37, 0x22, 0x27, 0x73, 0x3a,
-    0xaa, 0xaa, 0xa3, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
-    0xa3, 0x77, 0xaa, 0x10, 0x50, 0x08, 0x46, 0x05,
-    0x54, 0x80, 0x50, 0x42, 0x00, 0x00, 0x08, 0x66,
-    0x66, 0x1a, 0x32, 0x22, 0x22, 0x22, 0x22, 0x27,
-    0x31, 0x66, 0x66, 0x13, 0x72, 0x22, 0x77, 0x33,
-    0xaa, 0xaa, 0xaa, 0x33, 0xaa, 0xa1, 0xaa, 0xa3,
-    0x37, 0xa1, 0x1a, 0x30, 0x50, 0x06, 0x26, 0x00,
-    0x54, 0x00, 0x00, 0x44, 0x00, 0x00, 0x08, 0xe2,
-    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22, 0x22,
-    0x27, 0xa6, 0x66, 0x61, 0xa7, 0x72, 0x27, 0x73,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
-    0x31, 0x11, 0x37, 0x70, 0x02, 0x00, 0xab, 0xbb,
-    0xb6, 0x00, 0x00, 0xf4, 0x00, 0x00, 0xee, 0xee,
-    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22,
-    0x22, 0x23, 0x16, 0x66, 0x1a, 0x37, 0x22, 0x77,
-    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x3a,
-    0x11, 0xa7, 0x33, 0x10, 0x04, 0x09, 0xbd, 0xdd,
-    0xbd, 0xd0, 0x04, 0x45, 0x00, 0x0e, 0xee, 0xee,
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-    0xff, 0xf4, 0xf4, 0xff, 0x44, 0x00, 0xbb, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
-    0xa7, 0x73, 0x26, 0x88, 0x86, 0x7a, 0x72, 0x27,
-    0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdb, 0x44, 0xff, 0x4f, 0x4f,
-    0xff, 0xf4, 0xf4, 0x44, 0x40, 0x05, 0xbb, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
-    0x13, 0x23, 0x21, 0x68, 0x86, 0x17, 0x72, 0x22,
-    0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdb, 0x44, 0x4f, 0x4f, 0x4f,
-    0xff, 0xff, 0x44, 0x42, 0x00, 0x05, 0xbd, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
-    0x87, 0x27, 0x27, 0x16, 0x66, 0x67, 0x22, 0x22,
-    0x72, 0x7b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdd, 0x94, 0x44, 0x44, 0x44,
-    0x44, 0x44, 0x44, 0x00, 0x00, 0x05, 0xbb, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xb8,
-    0x86, 0x22, 0x22, 0x7a, 0x68, 0x81, 0x22, 0x22,
-    0x37, 0x7b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdb, 0xb5, 0x44, 0x44, 0x44,
-    0x44, 0x47, 0x00, 0x00, 0x00, 0x05, 0xbd, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0x68,
-    0x58, 0x72, 0x22, 0x27, 0x18, 0x86, 0x72, 0x22,
-    0x1a, 0xbb, 0xbd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdb, 0xb5, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xbb, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xb9, 0x18, 0x85,
-    0x58, 0x12, 0x22, 0x36, 0x18, 0x88, 0x32, 0x22,
-    0x61, 0x3b, 0xbb, 0xbb, 0xbd, 0xdd, 0xdd, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdb, 0xb9, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xbb, 0xdd,
-    0xdd, 0xdd, 0xdd, 0xdd, 0xb9, 0x7a, 0x68, 0x85,
-    0x88, 0x62, 0x27, 0x16, 0x18, 0x88, 0x12, 0x27,
-    0x86, 0x18, 0x9b, 0xbb, 0xbb, 0xbb, 0xbb, 0xbd,
-    0xdd, 0xdd, 0xdd, 0xbb, 0xb5, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0xbb, 0xbd,
-    0xdd, 0xdd, 0xdb, 0xbb, 0x87, 0x31, 0x68, 0x65,
-    0x88, 0x82, 0x23, 0x16, 0x18, 0x88, 0x12, 0x23,
-    0x88, 0x67, 0x27, 0xa8, 0x9b, 0xbb, 0xbb, 0xbb,
-    0xbd, 0xdd, 0xbb, 0xbb, 0x95, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x9b, 0xbb,
-    0xbb, 0xbb, 0xbb, 0x96, 0x87, 0x16, 0x68, 0x18,
-    0x88, 0x62, 0x31, 0x66, 0x18, 0x88, 0x62, 0x73,
-    0x88, 0x63, 0x27, 0x33, 0x65, 0x55, 0x99, 0x9b,
-    0xbb, 0xbb, 0xbb, 0x99, 0x55, 0x0a, 0xa1, 0x86,
-    0x81, 0x68, 0x88, 0x55, 0x58, 0x85, 0x9b, 0xbb,
-    0xbb, 0xbb, 0x95, 0x88, 0x83, 0x66, 0x66, 0x18,
-    0x66, 0x82, 0xa1, 0x66, 0x18, 0x88, 0x62, 0x33,
-    0x88, 0x81, 0x27, 0x7a, 0x18, 0x58, 0x86, 0x85,
-    0x99, 0x99, 0x99, 0x95, 0x53, 0x2a, 0xaa, 0x88,
-    0x67, 0x31, 0x68, 0x55, 0x58, 0x85, 0x59, 0xbb,
-    0xbb, 0xb9, 0x58, 0x68, 0x83, 0x66, 0x61, 0x16,
-    0x66, 0x62, 0x16, 0x66, 0x68, 0x88, 0x62, 0xaa,
-    0x88, 0x86, 0x27, 0x77, 0x78, 0x55, 0x88, 0x22,
-    0x25, 0x55, 0x95, 0x55, 0x6a, 0xa2, 0x2a, 0x88,
-    0x62, 0x27, 0x37, 0x38, 0x88, 0x87, 0x55, 0x59,
-    0x95, 0x58, 0x16, 0x88, 0x8a, 0x66, 0x63, 0x68,
-    0x86, 0x67, 0x66, 0x66, 0x68, 0x88, 0x12, 0x11,
-    0x88, 0x88, 0x72, 0x77, 0x78, 0x85, 0x58, 0x17,
-    0x23, 0x32, 0x55, 0x55, 0x81, 0x13, 0x73, 0x66,
-    0x62, 0x7a, 0xaa, 0x38, 0x88, 0x58, 0x27, 0x55,
-    0x58, 0x32, 0x38, 0x88, 0x81, 0x66, 0xa2, 0x88,
-    0x86, 0x61, 0x66, 0x61, 0x66, 0x68, 0x13, 0x11,
-    0x88, 0x88, 0x12, 0x22, 0x71, 0x85, 0x58, 0x62,
-    0x23, 0xa2, 0x68, 0x88, 0x81, 0x66, 0x88, 0x88,
-    0x63, 0x2a, 0xaa, 0x28, 0x88, 0x55, 0x86, 0x61,
-    0x66, 0x66, 0x68, 0x88, 0x66, 0x66, 0x77, 0x88,
-    0x68, 0x16, 0x66, 0x62, 0x66, 0x68, 0xa1, 0x61,
-    0x88, 0x88, 0x62, 0x22, 0x22, 0x85, 0x55, 0x83,
-    0x72, 0x37, 0xa8, 0x88, 0x61, 0x66, 0x85, 0x55,
-    0x86, 0x23, 0xaa, 0x71, 0x88, 0x85, 0x88, 0x66,
-    0x88, 0x86, 0x88, 0x88, 0x16, 0x61, 0x21, 0x88,
-    0x66, 0xa6, 0x86, 0x17, 0x66, 0x66, 0x31, 0x61,
-    0x88, 0x88, 0x87, 0x72, 0x22, 0x68, 0x55, 0x86,
-    0x77, 0x77, 0x36, 0x88, 0x13, 0x68, 0x85, 0x55,
-    0x58, 0x12, 0x73, 0x72, 0x76, 0x88, 0x88, 0x68,
-    0x88, 0x88, 0x88, 0x66, 0x36, 0x63, 0x26, 0x86,
-    0x86, 0x36, 0x86, 0x11, 0x66, 0x66, 0x76, 0x61,
-    0x88, 0x88, 0x81, 0x22, 0x22, 0x38, 0x85, 0x58,
-    0x37, 0x22, 0x21, 0x68, 0xa2, 0x31, 0x68, 0x55,
-    0x55, 0x81, 0x22, 0x22, 0xa8, 0x88, 0x88, 0x68,
-    0x86, 0x88, 0x68, 0x81, 0x36, 0x17, 0x21, 0x68,
-    0x86, 0x16, 0x66, 0x26, 0x66, 0x61, 0x36, 0x66,
-    0x68, 0x88, 0x86, 0x27, 0x22, 0x28, 0x88, 0x88,
-    0x17, 0x72, 0x2a, 0x66, 0xa2, 0x22, 0x36, 0x55,
-    0x55, 0x58, 0x37, 0x3a, 0x16, 0x66, 0x66, 0x66,
-    0x66, 0x18, 0x88, 0x67, 0x16, 0x12, 0x71, 0x68,
-    0x81, 0x68, 0x61, 0x76, 0x66, 0x6a, 0x16, 0x66,
-    0x88, 0x88, 0x86, 0x77, 0x22, 0x26, 0x88, 0x88,
-    0x13, 0x37, 0x71, 0x66, 0xa2, 0x33, 0x2a, 0x85,
-    0x55, 0x55, 0x17, 0x73, 0x16, 0x66, 0x66, 0x68,
-    0x63, 0x88, 0x88, 0xa2, 0x66, 0xa2, 0xa6, 0x88,
-    0x61, 0x68, 0x6a, 0x76, 0x66, 0x6a, 0x66, 0x6a
-};
-
-#endif
diff --git a/include/lmb.h b/include/lmb.h
index 07bf22144e..231b68b27d 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -116,16 +116,31 @@ phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
 			     phys_addr_t max_addr);
 phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size);
 phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr);
+
+/**
+ * lmb_is_reserved() - test if address is in reserved region
+ *
+ * The function checks if a reserved region comprising @addr exists.
+ *
+ * @lmb:	the logical memory block struct
+ * @addr:	address to be tested
+ * Return:	1 if reservation exists, 0 otherwise
+ */
 int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
+
 /**
- * lmb_is_reserved_flags - test if tha address is in reserved region with a bitfield flag
+ * lmb_is_reserved_flags() - test if address is in reserved region with flag bits set
+ *
+ * The function checks if a reserved region comprising @addr exists which has
+ * all flag bits set which are set in @flags.
  *
  * @lmb:	the logical memory block struct
  * @addr:	address to be tested
- * @flags:	flags bitfied to be tested
- * Return:	if not reserved or reserved without the requested flag else 1
+ * @flags:	bitmap with bits to be tested
+ * Return:	1 if matching reservation exists, 0 otherwise
  */
 int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags);
+
 long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
 
 void lmb_dump_all(struct lmb *lmb);
diff --git a/include/log.h b/include/log.h
index 3bab40b617..6e84f080ef 100644
--- a/include/log.h
+++ b/include/log.h
@@ -102,6 +102,8 @@ enum log_category_t {
 	LOGC_EVENT,
 	/** @LOGC_FS: Related to filesystems */
 	LOGC_FS,
+	/** @LOGC_EXPO: Related to expo handling */
+	LOGC_EXPO,
 	/** @LOGC_COUNT: Number of log categories */
 	LOGC_COUNT,
 	/** @LOGC_END: Sentinel value for lists of log categories */
diff --git a/include/lxt971a.h b/include/lxt971a.h
deleted file mode 100644
index a5dd82b62a..0000000000
--- a/include/lxt971a.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
- * @Author: Markus Pietrek
- * @References: [1] NS9750 Hardware Reference, December 2003
- *              [2] Intel LXT971 Datasheet #249414 Rev. 02
- *              [3] NS7520 Linux Ethernet Driver
- */
-
-#ifndef __LXT971A_H__
-#define __LXT971A_H__
-
-/* PHY definitions (LXT971A) [2] */
-#define PHY_LXT971_PORT_CFG		(0x10)
-#define PHY_LXT971_STAT2		(0x11)
-#define PHY_LXT971_INT_ENABLE		(0x12)
-#define PHY_LXT971_INT_STATUS		(0x13)
-#define PHY_LXT971_LED_CFG		(0x14)
-#define PHY_LXT971_DIG_CFG		(0x1A)
-#define PHY_LXT971_TX_CTRL		(0x1E)
-
-/* PORT_CFG Port Configuration Register Bit Fields */
-#define PHY_LXT971_PORT_CFG_RES1        (0x8000)
-#define PHY_LXT971_PORT_CFG_FORCE_LNK   (0x4000)
-#define PHY_LXT971_PORT_CFG_TX_DISABLE  (0x2000)
-#define PHY_LXT971_PORT_CFG_BYPASS_SCR  (0x1000)
-#define PHY_LXT971_PORT_CFG_RES2        (0x0800)
-#define PHY_LXT971_PORT_CFG_JABBER      (0x0400)
-#define PHY_LXT971_PORT_CFG_SQE	        (0x0200)
-#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
-#define PHY_LXT971_PORT_CFG_CRS_SEL     (0x0080)
-#define PHY_LXT971_PORT_CFG_SLEEP_MODE  (0x0040)
-#define PHY_LXT971_PORT_CFG_PRE_EN      (0x0020)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_MA  (0x0018)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
-#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
-#define PHY_LXT971_PORT_CFG_ALT_NP      (0x0002)
-#define PHY_LXT971_PORT_CFG_FIBER_SEL   (0x0001)
-
-/* STAT2 Status Register #2 Bit Fields */
-#define PHY_LXT971_STAT2_RES1		(0x8000)
-#define PHY_LXT971_STAT2_100BTX		(0x4000)
-#define PHY_LXT971_STAT2_TX_STATUS	(0x2000)
-#define PHY_LXT971_STAT2_RX_STATUS	(0x1000)
-#define PHY_LXT971_STAT2_COL_STATUS	(0x0800)
-#define PHY_LXT971_STAT2_LINK		(0x0400)
-#define PHY_LXT971_STAT2_DUPLEX_MODE	(0x0200)
-#define PHY_LXT971_STAT2_AUTO_NEG	(0x0100)
-#define PHY_LXT971_STAT2_AUTO_NEG_COMP	(0x0080)
-#define PHY_LXT971_STAT2_RES2		(0x0040)
-#define PHY_LXT971_STAT2_POLARITY	(0x0020)
-#define PHY_LXT971_STAT2_PAUSE		(0x0010)
-#define PHY_LXT971_STAT2_ERROR		(0x0008)
-#define PHY_LXT971_STAT2_RES3		(0x0007)
-
-/* INT_ENABLE Interrupt Enable Register Bit Fields */
-#define PHY_LXT971_INT_ENABLE_RES1      (0xFF00)
-#define PHY_LXT971_INT_ENABLE_ANMSK     (0x0080)
-#define PHY_LXT971_INT_ENABLE_SPEEDMSK  (0x0040)
-#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
-#define PHY_LXT971_INT_ENABLE_LINKMSK   (0x0010)
-#define PHY_LXT971_INT_ENABLE_RES2      (0x000C)
-#define PHY_LXT971_INT_ENABLE_INTEN     (0x0002)
-#define PHY_LXT971_INT_ENABLE_TINT      (0x0001)
-
-/* INT_STATUS Interrupt Status Register Bit Fields */
-#define PHY_LXT971_INT_STATUS_RES1      (0xFF00)
-#define PHY_LXT971_INT_STATUS_ANDONE    (0x0080)
-#define PHY_LXT971_INT_STATUS_SPEEDCHG  (0x0040)
-#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
-#define PHY_LXT971_INT_STATUS_LINKCHG   (0x0010)
-#define PHY_LXT971_INT_STATUS_RES2      (0x0008)
-#define PHY_LXT971_INT_STATUS_MDINT     (0x0004)
-#define PHY_LXT971_INT_STATUS_RES3      (0x0003)
-
-/* LED_CFG Interrupt LED Configuration Register Bit Fields */
-#define PHY_LXT971_LED_CFG_SHIFT_LED1   (0x000C)
-#define PHY_LXT971_LED_CFG_SHIFT_LED2   (0x0008)
-#define PHY_LXT971_LED_CFG_SHIFT_LED3   (0x0004)
-#define PHY_LXT971_LED_CFG_LEDFREQ_MA	(0x000C)
-#define PHY_LXT971_LED_CFG_LEDFREQ_RES	(0x000C)
-#define PHY_LXT971_LED_CFG_LEDFREQ_100	(0x0008)
-#define PHY_LXT971_LED_CFG_LEDFREQ_60	(0x0004)
-#define PHY_LXT971_LED_CFG_LEDFREQ_30	(0x0000)
-#define PHY_LXT971_LED_CFG_PULSE_STR    (0x0002)
-#define PHY_LXT971_LED_CFG_RES1         (0x0001)
-
-/* only one of these values must be shifted for each SHIFT_LED?  */
-#define PHY_LXT971_LED_CFG_UNUSED1      (0x000F)
-#define PHY_LXT971_LED_CFG_DUPLEX_COL   (0x000E)
-#define PHY_LXT971_LED_CFG_LINK_ACT     (0x000D)
-#define PHY_LXT971_LED_CFG_LINK_RX      (0x000C)
-#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
-#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
-#define PHY_LXT971_LED_CFG_TEST_OFF     (0x0009)
-#define PHY_LXT971_LED_CFG_TEST_ON      (0x0008)
-#define PHY_LXT971_LED_CFG_RX_OR_TX     (0x0007)
-#define PHY_LXT971_LED_CFG_UNUSED2      (0x0006)
-#define PHY_LXT971_LED_CFG_DUPLEX       (0x0005)
-#define PHY_LXT971_LED_CFG_LINK	        (0x0004)
-#define PHY_LXT971_LED_CFG_COLLISION    (0x0003)
-#define PHY_LXT971_LED_CFG_RECEIVE      (0x0002)
-#define PHY_LXT971_LED_CFG_TRANSMIT     (0x0001)
-#define PHY_LXT971_LED_CFG_SPEED        (0x0000)
-
-/* DIG_CFG Digitial Configuration Register Bit Fields */
-#define PHY_LXT971_DIG_CFG_RES1		(0xF000)
-#define PHY_LXT971_DIG_CFG_MII_DRIVE	(0x0800)
-#define PHY_LXT971_DIG_CFG_RES2		(0x0400)
-#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL	(0x0200)
-#define PHY_LXT971_DIG_CFG_RES3		(0x01FF)
-
-#define PHY_LXT971_MDIO_MAX_CLK		(8000000)
-#define PHY_MDIO_MAX_CLK		(2500000)
-
-/* TX_CTRL Transmit Control Register Bit Fields
-   documentation is buggy for this register, therefore setting not included */
-
-typedef enum
-{
-	PHY_NONE    = 0x0000, /* no PHY detected yet */
-	PHY_LXT971A = 0x0013
-} PhyType;
-
-#endif /* __LXT971A_H__ */
diff --git a/include/mc13783.h b/include/mc13783.h
deleted file mode 100644
index c7ee03b0f9..0000000000
--- a/include/mc13783.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at
- */
-
-
-#ifndef __MC13783_H__
-#define __MC13783_H__
-
-/* REG_MODE_0 */
-#define VAUDIOEN	(1 << 0)
-#define VAUDIOSTBY	(1 << 1)
-#define VAUDIOMODE	(1 << 2)
-#define VIOHIEN		(1 << 3)
-#define VIOHISTBY	(1 << 4)
-#define VIOHIMODE	(1 << 5)
-#define VIOLOEN		(1 << 6)
-#define VIOLOSTBY	(1 << 7)
-#define VIOLOMODE	(1 << 8)
-#define VDIGEN		(1 << 9)
-#define VDIGSTBY	(1 << 10)
-#define VDIGMODE	(1 << 11)
-#define VGENEN		(1 << 12)
-#define VGENSTBY	(1 << 13)
-#define VGENMODE	(1 << 14)
-#define VRFDIGEN	(1 << 15)
-#define VRFDIGSTBY	(1 << 16)
-#define VRFDIGMODE	(1 << 17)
-#define VRFREFEN	(1 << 18)
-#define VRFREFSTBY	(1 << 19)
-#define VRFREFMODE	(1 << 20)
-#define VRFCPEN		(1 << 21)
-#define VRFCPSTBY	(1 << 22)
-#define VRFCPMODE	(1 << 23)
-
-/* REG_MODE_1 */
-#define VSIMEN		(1 << 0)
-#define VSIMSTBY	(1 << 1)
-#define VSIMMODE	(1 << 2)
-#define VESIMEN		(1 << 3)
-#define VESIMSTBY	(1 << 4)
-#define VESIMMODE	(1 << 5)
-#define VCAMEN		(1 << 6)
-#define VCAMSTBY	(1 << 7)
-#define VCAMMODE	(1 << 8)
-#define VRFBGEN		(1 << 9)
-#define VRFBGSTBY	(1 << 10)
-#define VVIBEN		(1 << 11)
-#define VRF1EN		(1 << 12)
-#define VRF1STBY	(1 << 13)
-#define VRF1MODE	(1 << 14)
-#define VRF2EN		(1 << 15)
-#define VRF2STBY	(1 << 16)
-#define VRF2MODE	(1 << 17)
-#define VMMC1EN		(1 << 18)
-#define VMMC1STBY	(1 << 19)
-#define VMMC1MODE	(1 << 20)
-#define VMMC2EN		(1 << 21)
-#define VMMC2STBY	(1 << 22)
-#define VMMC2MODE	(1 << 23)
-
-#endif
diff --git a/include/mc34704.h b/include/mc34704.h
deleted file mode 100644
index b837ddaa1d..0000000000
--- a/include/mc34704.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __MC34704_H__
-#define __MC34704_H__
-
-enum {
-	MC34704_RESERVED0_REG = 0,	/* 0x00 */
-	MC34704_GENERAL1_REG,		/* 0x01 */
-	MC34704_GENERAL2_REG,		/* 0x02 */
-	MC34704_GENERAL3_REG,		/* 0x03 */
-	MC34704_RESERVED4_REG,		/* 0x04 */
-	MC34704_VGSET2_REG,		/* 0x05 */
-	MC34704_REG2SET1_REG,		/* 0x06 */
-	MC34704_REG2SET2_REG,		/* 0x07 */
-	MC34704_REG3SET1_REG,		/* 0x08 */
-	MC34704_REG3SET2_REG,		/* 0x09 */
-	MC34704_REG4SET1_REG,		/* 0x0a */
-	MC34704_REG4SET2_REG,		/* 0x0b */
-	MC34704_REG5SET1_REG,		/* 0x0c */
-	MC34704_REG5SET2_REG,		/* 0x0d */
-	MC34704_REG5SET3_REG,		/* 0x0e */
-	MC34704_RESERVEDF_REG,		/* 0x0f */
-	MC34704_RESERVED10_REG,		/* 0x10 */
-	MC34704_RESERVED11_REG,		/* 0x11 */
-	MC34704_RESERVED12_REG,		/* 0x12 */
-	MC34704_FSW2SET_REG,		/* 0x13 */
-	MC34704_RESERVED14_REG,		/* 0x14 */
-	MC34704_REG8SET1_REG,		/* 0x15 */
-	MC34704_REG8SET2_REG,		/* 0x16 */
-	MC34704_REG8SET3_REG,		/* 0x17 */
-	MC34704_FAULTS_REG,		/* 0x18 */
-	MC34704_I2CSET1,		/* 0x19 */
-	MC34704_NUM_OF_REGS,
-};
-
-/* GENERAL2 register fields */
-#define ONOFFE		(1 << 0)
-#define ONOFFD		(1 << 1)
-#define ONOFFA		(1 << 3)
-#define ALLOFF		(1 << 4)
-
-#endif /* __MC34704_H__ */
diff --git a/include/mc9sdz60.h b/include/mc9sdz60.h
deleted file mode 100644
index ffe376bf50..0000000000
--- a/include/mc9sdz60.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de>
- *
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-#ifndef __ASM_ARCH_MC9SDZ60_H
-#define __ASM_ARCH_MC9SDZ60_H
-
-/**
- * Register addresses for the MC9SDZ60
- *
- * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h
- * but not include/linux/mfd/mc9s08dz60/pmic.h
- *
- */
-enum mc9sdz60_reg {
-	MC9SDZ60_REG_VERSION		= 0x00,
-	/* reserved                       0x01 */
-	MC9SDZ60_REG_SECS		= 0x02,
-	MC9SDZ60_REG_MINS		= 0x03,
-	MC9SDZ60_REG_HRS		= 0x04,
-	MC9SDZ60_REG_DAY		= 0x05,
-	MC9SDZ60_REG_DATE		= 0x06,
-	MC9SDZ60_REG_MONTH		= 0x07,
-	MC9SDZ60_REG_YEAR		= 0x08,
-	MC9SDZ60_REG_ALARM_SECS		= 0x09,
-	MC9SDZ60_REG_ALARM_MINS		= 0x0a,
-	MC9SDZ60_REG_ALARM_HRS		= 0x0b,
-	/* reserved                       0x0c */
-	/* reserved                       0x0d */
-	MC9SDZ60_REG_TS_CONTROL		= 0x0e,
-	MC9SDZ60_REG_X_LOW		= 0x0f,
-	MC9SDZ60_REG_Y_LOW		= 0x10,
-	MC9SDZ60_REG_XY_HIGH		= 0x11,
-	MC9SDZ60_REG_X_LEFT_LOW		= 0x12,
-	MC9SDZ60_REG_X_LEFT_HIGH	= 0x13,
-	MC9SDZ60_REG_X_RIGHT		= 0x14,
-	MC9SDZ60_REG_Y_TOP_LOW		= 0x15,
-	MC9SDZ60_REG_Y_TOP_HIGH		= 0x16,
-	MC9SDZ60_REG_Y_BOTTOM		= 0x17,
-	/* reserved                       0x18 */
-	/* reserved                       0x19 */
-	MC9SDZ60_REG_RESET_1		= 0x1a,
-	MC9SDZ60_REG_RESET_2		= 0x1b,
-	MC9SDZ60_REG_POWER_CTL		= 0x1c,
-	MC9SDZ60_REG_DELAY_CONFIG	= 0x1d,
-	/* reserved                       0x1e */
-	/* reserved                       0x1f */
-	MC9SDZ60_REG_GPIO_1		= 0x20,
-	MC9SDZ60_REG_GPIO_2		= 0x21,
-	MC9SDZ60_REG_KPD_1		= 0x22,
-	MC9SDZ60_REG_KPD_2		= 0x23,
-	MC9SDZ60_REG_KPD_CONTROL	= 0x24,
-	MC9SDZ60_REG_INT_ENABLE_1	= 0x25,
-	MC9SDZ60_REG_INT_ENABLE_2	= 0x26,
-	MC9SDZ60_REG_INT_FLAG_1		= 0x27,
-	MC9SDZ60_REG_INT_FLAG_2		= 0x28,
-	MC9SDZ60_REG_DES_FLAG		= 0x29,
-};
-
-extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg);
-extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val);
-
-#endif /* __ASM_ARCH_MC9SDZ60_H */
diff --git a/include/mii_phy.h b/include/mii_phy.h
deleted file mode 100644
index f0d3e62823..0000000000
--- a/include/mii_phy.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _MII_PHY_H_
-#define _MII_PHY_H_
-
-void mii_discover_phy(void);
-unsigned short mii_phy_read(unsigned short reg);
-void mii_phy_write(unsigned short reg, unsigned short val);
-
-#endif
diff --git a/include/mk48t59.h b/include/mk48t59.h
deleted file mode 100644
index f95d349c17..0000000000
--- a/include/mk48t59.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Andreas Heppel <aheppel@sysgo.de>
- */
-
-/*
- * Date & Time support for the MK48T59 RTC
- */
-
-
-#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE)
-
-#define RTC_PORT_ADDR0		0x70
-#define RTC_PORT_ADDR1		RTC_PORT_ADDR0 +  0x1
-#define RTC_PORT_DATA		0x76
-
-/* RTC Offsets */
-#define RTC_SECONDS             0x1FF9
-#define RTC_MINUTES             0x1FFA
-#define RTC_HOURS               0x1FFB
-#define RTC_DAY_OF_WEEK         0x1FFC
-#define RTC_DAY_OF_MONTH        0x1FFD
-#define RTC_MONTH               0x1FFE
-#define RTC_YEAR                0x1FFF
-
-#define RTC_CONTROLA            0x1FF8
-#define RTC_CA_WRITE            0x80
-#define RTC_CA_READ             0x40
-#define RTC_CA_CALIB_SIGN       0x20
-#define RTC_CA_CALIB_MASK       0x1f
-
-#define RTC_CONTROLB            0x1FF9
-#define RTC_CB_STOP             0x80
-
-#define RTC_WATCHDOG			0x1FF7
-#define RTC_WDS					0x80
-#define RTC_WD_RB_16TH			0x0
-#define RTC_WD_RB_4TH			0x1
-#define RTC_WD_RB_1				0x2
-#define RTC_WD_RB_4				0x3
-
-void rtc_set_watchdog(short multi, short res);
-void *nvram_read(void *dest, const short src, size_t count);
-void nvram_write(short dest, const void *src, size_t count);
-
-#endif
diff --git a/include/mm_communication.h b/include/mm_communication.h
index e65fbde60d..f38f1a5344 100644
--- a/include/mm_communication.h
+++ b/include/mm_communication.h
@@ -6,6 +6,9 @@
  *  Copyright (c) 2017, Intel Corporation. All rights reserved.
  *  Copyright (C) 2020 Linaro Ltd. <sughosh.ganu@linaro.org>
  *  Copyright (C) 2020 Linaro Ltd. <ilias.apalodimas@linaro.org>
+ *  Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *    Authors:
+ *      Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
  */
 
 #ifndef _MM_COMMUNICATION_H_
@@ -13,6 +16,11 @@
 
 #include <part_efi.h>
 
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+/* MM service UUID string (big-endian format). This UUID is  common across all MM SPs */
+#define MM_SP_UUID	"33d532ed-e699-0942-c09c-a798d9cd722d"
+#endif
+
 /*
  * Interface to the pseudo Trusted Application (TA), which provides a
  * communication channel with the Standalone MM (Management Mode)
@@ -248,4 +256,13 @@ struct smm_variable_var_check_property {
 	u16                       name[];
 };
 
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+/* supported MM transports */
+enum mm_comms_select {
+	MM_COMMS_UNDEFINED,
+	MM_COMMS_FFA,
+	MM_COMMS_OPTEE
+};
+#endif
+
 #endif /* _MM_COMMUNICATION_H_ */
diff --git a/include/mmc.h b/include/mmc.h
index b8fbff150d..1022db3ffa 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -558,6 +558,8 @@ int mmc_deferred_probe(struct mmc *mmc);
 int mmc_reinit(struct mmc *mmc);
 int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
 int mmc_hs400_prepare_ddr(struct mmc *mmc);
+int mmc_send_stop_transmission(struct mmc *mmc, bool write);
+
 #else
 struct mmc_ops {
 	int (*send_cmd)(struct mmc *mmc,
diff --git a/include/mpc106.h b/include/mpc106.h
deleted file mode 100644
index 2157b32407..0000000000
--- a/include/mpc106.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Andreas Heppel <aheppel@sysgo.de>
- */
-
-#ifndef _MPC106_PCI_H
-#define _MPC106_PCI_H
-
-/*
- * Defines for the MPC106 PCI Config address and data registers followed by
- * defines for the standard PCI device configuration header.
- */
-#define PCIDEVID_MPC106			0x0
-
-/*
- * MPC106 Registers
- */
-#define	MPC106_REG			0x80000000
-
-#ifdef CONFIG_SYS_ADDRESS_MAP_A
-#define MPC106_REG_ADDR			0x80000cf8
-#define	MPC106_REG_DATA			0x80000cfc
-#define MPC106_ISA_IO_PHYS		0x80000000
-#define MPC106_ISA_IO_BUS		0x00000000
-#define MPC106_ISA_IO_SIZE		0x00800000
-#define MPC106_PCI_IO_PHYS		0x81000000
-#define MPC106_PCI_IO_BUS		0x01000000
-#define MPC106_PCI_IO_SIZE		0x3e800000
-#define MPC106_PCI_MEM_PHYS		0xc0000000
-#define MPC106_PCI_MEM_BUS		0x00000000
-#define MPC106_PCI_MEM_SIZE		0x3f000000
-#define	MPC106_PCI_MEMORY_PHYS		0x00000000
-#define	MPC106_PCI_MEMORY_BUS		0x80000000
-#define	MPC106_PCI_MEMORY_SIZE		0x80000000
-#else
-#define MPC106_REG_ADDR			0xfec00cf8
-#define	MPC106_REG_DATA			0xfee00cfc
-#define MPC106_ISA_MEM_PHYS		0xfd000000
-#define MPC106_ISA_MEM_BUS		0x00000000
-#define MPC106_ISA_MEM_SIZE		0x01000000
-#define MPC106_ISA_IO_PHYS		0xfe000000
-#define MPC106_ISA_IO_BUS		0x00000000
-#define MPC106_ISA_IO_SIZE		0x00800000
-#define MPC106_PCI_IO_PHYS		0xfe800000
-#define MPC106_PCI_IO_BUS		0x00800000
-#define MPC106_PCI_IO_SIZE		0x00400000
-#define MPC106_PCI_MEM_PHYS		0x80000000
-#define MPC106_PCI_MEM_BUS		0x80000000
-#define MPC106_PCI_MEM_SIZE		0x7d000000
-#define	MPC106_PCI_MEMORY_PHYS		0x00000000
-#define	MPC106_PCI_MEMORY_BUS		0x00000000
-#define MPC106_PCI_MEMORY_SIZE		0x40000000
-#endif
-
-#define CMD_SERR			0x0100
-#define PCI_CMD_MASTER			0x0004
-#define PCI_CMD_MEMEN			0x0002
-#define PCI_CMD_IOEN			0x0001
-
-#define PCI_STAT_NO_RSV_BITS		0xffff
-
-#define PCI_BUSNUM			0x40
-#define PCI_SUBBUSNUM			0x41
-#define PCI_DISCOUNT			0x42
-
-#define PCI_PICR1			0xA8
-#define PICR1_CF_CBA(value)		((value & 0xff) << 24)
-#define PICR1_CF_BREAD_WS(value)	((value & 0x3) << 22)
-#define PICR1_PROC_TYPE_603		0x40000
-#define PICR1_PROC_TYPE_604		0x60000
-#define PICR1_MCP_EN			0x800
-#define PICR1_CF_DPARK			0x200
-#define PICR1_CF_LOOP_SNOOP		0x10
-#define PICR1_CF_L2_COPY_BACK		0x2
-#define PICR1_CF_L2_CACHE_MASK		0x3
-#define PICR1_CF_APARK			0x8
-#define PICR1_ADDRESS_MAP		0x10000
-#define PICR1_XIO_MODE			0x80000
-#define PICR1_CF_CACHE_1G		0x200000
-
-#define PCI_PICR2			0xAC
-#define PICR2_CF_SNOOP_WS(value)	((value & 0x3) << 18)
-#define PICR2_CF_FLUSH_L2		0x10000000
-#define PICR2_CF_L2_HIT_DELAY(value)	((value & 0x3) << 9)
-#define PICR2_CF_APHASE_WS(value)	((value & 0x3) << 2)
-#define PICR2_CF_INV_MODE		0x00001000
-#define PICR2_CF_MOD_HIGH		0x00020000
-#define PICR2_CF_HIT_HIGH		0x00010000
-#define PICR2_L2_SIZE_256K		0x00000000
-#define PICR2_L2_SIZE_512K		0x00000010
-#define PICR2_L2_SIZE_1MB		0x00000020
-#define PICR2_L2_EN			0x40000000
-#define PICR2_L2_UPDATE_EN		0x80000000
-#define PICR2_CF_ADDR_ONLY_DISABLE	0x00004000
-#define PICR2_CF_FAST_CASTOUT		0x00000080
-#define PICR2_CF_WDATA			0x00000001
-#define PICR2_CF_DATA_RAM_PBURST	0x00400000
-
-/*
- * Memory controller
- */
-#define MPC106_MCCR1			0xF0
-#define MCCR1_TYPE_EDO			0x00020000
-#define MCCR1_BK0_9BITS			0x0
-#define MCCR1_BK0_10BITS		0x1
-#define MCCR1_BK0_11BITS		0x2
-#define MCCR1_BK0_12BITS		0x3
-#define MCCR1_BK1_9BITS			0x0
-#define MCCR1_BK1_10BITS		0x4
-#define MCCR1_BK1_11BITS		0x8
-#define MCCR1_BK1_12BITS		0xC
-#define MCCR1_BK2_9BITS			0x00
-#define MCCR1_BK2_10BITS		0x10
-#define MCCR1_BK2_11BITS		0x20
-#define MCCR1_BK2_12BITS		0x30
-#define MCCR1_BK3_9BITS			0x00
-#define MCCR1_BK3_10BITS		0x40
-#define MCCR1_BK3_11BITS		0x80
-#define MCCR1_BK3_12BITS		0xC0
-#define MCCR1_MEMGO			0x00080000
-
-#define MPC106_MCCR2			0xF4
-#define MPC106_MCCR3			0xF8
-#define MPC106_MCCR4			0xFC
-
-#define MPC106_MSAR1			0x80
-#define MPC106_EMSAR1			0x88
-#define MPC106_EMSAR2			0x8C
-#define MPC106_MEAR1			0x90
-#define MPC106_EMEAR1			0x98
-#define MPC106_EMEAR2			0x9C
-
-#define MPC106_MBER			0xA0
-#define MBER_BANK0			0x1
-#define MBER_BANK1			0x2
-#define MBER_BANK2			0x4
-#define MBER_BANK3			0x8
-
-#endif
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
deleted file mode 100644
index ea8d17d557..0000000000
--- a/include/mpc86xx.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright 2006 Freescale Semiconductor.
- * Jeffrey Brown
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
- */
-
-#ifndef	__MPC86xx_H__
-#define __MPC86xx_H__
-
-#include <asm/fsl_lbc.h>
-
-#define EXC_OFF_SYS_RESET	0x0100	/* System reset	offset */
-#define _START_OFFSET		EXC_OFF_SYS_RESET
-
-/*
- * platform register addresses
- */
-
-#define GUTS_SVR	(CFG_SYS_CCSRBAR + 0xE00A4)
-#define MCM_ABCR	(CFG_SYS_CCSRBAR + 0x01000)
-#define MCM_DBCR	(CFG_SYS_CCSRBAR + 0x01008)
-
-/*
- * l2cr values.  Look in config_<BOARD>.h for the actual setup
- */
-#define l2cr		 1017
-
-#define L2CR_L2E         0x80000000 /* bit 0 - enable */
-#define L2CR_L2PE        0x40000000 /* bit 1 - data parity */
-#define L2CR_L2I         0x00200000 /* bit 10 - global invalidate bit */
-#define L2CR_L2CTL       0x00100000 /* bit 11 - l2 ram control */
-#define L2CR_L2DO        0x00010000 /* bit 15 - data-only mode */
-#define L2CR_REP         0x00001000 /* bit 19 - l2 replacement alg */
-#define L2CR_HWF         0x00000800 /* bit 20 - hardware flush */
-#define L2CR_L2IP        0x00000001 /* global invalidate in progress */
-
-#define HID0_XBSEN              0x00000100
-#define HID0_HIGH_BAT_EN        0x00800000
-#define HID0_XAEN               0x00020000
-
-#ifndef __ASSEMBLY__
-
-typedef struct {
-	unsigned long freq_processor;
-	unsigned long freq_systembus;
-	unsigned long freq_localbus;
-} MPC86xx_SYS_INFO;
-
-#define l1icache_enable	icache_enable
-
-void l2cache_enable(void);
-void l1dcache_enable(void);
-
-static __inline__ unsigned long get_hid0 (void)
-{
-	unsigned long hid0;
-	asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
-	return hid0;
-}
-
-static __inline__ unsigned long get_hid1 (void)
-{
-	unsigned long hid1;
-	asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
-	return hid1;
-}
-
-static __inline__ void set_hid0 (unsigned long hid0)
-{
-	asm volatile("mtspr 1008, %0" : : "r" (hid0));
-}
-
-static __inline__ void set_hid1 (unsigned long hid1)
-{
-	asm volatile("mtspr 1009, %0" : : "r" (hid1));
-}
-
-
-static __inline__ unsigned long get_l2cr (void)
-{
-   unsigned long l2cr_val;
-   asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
-   return l2cr_val;
-}
-
-void setup_ddr_bat(phys_addr_t dram_size);
-extern void setup_bats(void);
-
-#endif  /* _ASMLANGUAGE */
-#endif	/* __MPC86xx_H__ */
diff --git a/include/mvmfp.h b/include/mvmfp.h
deleted file mode 100644
index de86ffd5e2..0000000000
--- a/include/mvmfp.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef __MVMFP_H
-#define __MVMFP_H
-
-/*
- * Header file for MultiFunctionPin (MFP) Configururation framework
- *
- * Processors Supported:
- * 1. Marvell ARMADA100 Processors
- *
- * processor to be supported should be added here
- */
-
-/*
- * MFP configuration is represented by a 32-bit unsigned integer
- */
-#ifdef CONFIG_MVMFP_V2
-#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \
-	/* bits 31..16 - MFP Register Offset */	(((_off) & 0xffff) << 16) | \
-	/* bits 15..13 - Run Mode Pull State */	(((_pull) & 0x7) << 13) | \
-	/* bit  12..11 - Driver Strength */	(((_drv) & 0x3) << 11) | \
-	/* bits 10     - pad driver */		(((_slp) & 0x1) << 10) | \
-	/* bit  09..07 - sleep mode */		(((_sleep) & 0xe) << 6) | \
-	/* bits 06..04 - Edge Detection */	(((_edge) & 0x7) << 4) | \
-	/* bits 03     - sleep mode */		(((_sleep) & 0x1) << 3) | \
-	/* bits 02..00 - Alt-fun select */	((_afn) & 0x7))
-#else
-#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \
-	/* bits 31..16 - MFP Register Offset */	(((_off) & 0xffff) << 16) | \
-	/* bits 15..13 - Run Mode Pull State */	(((_pull) & 0x7) << 13) | \
-	/* bit  12     - Unused */ \
-	/* bits 11..10 - Driver Strength */	(((_drv) & 0x3) << 10) | \
-	/* bit  09..07 - sleep mode */		(((_sleep) & 0xe) << 6) | \
-	/* bits 06..04 - Edge Detection */	(((_edge) & 0x7) << 4) | \
-	/* bits 03     - sleep mode */		(((_sleep) & 0x1) << 3) | \
-	/* bits 02..00 - Alt-fun select */	((_afn) & 0x7))
-#endif
-
-/*
- * to facilitate the definition, the following macros are provided
- *
- *				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-#define MFP_OFFSET_MASK		MFP(0xffff,    0,    0,   0,   0,   0,   0)
-#define MFP_REG(x)		MFP(x,         0,    0,   0,   0,   0,   0)
-#define MFP_REG_GET_OFFSET(x)	((x & MFP_OFFSET_MASK) >> 16)
-
-#define MFP_AF0			MFP(0x0000,    0,    0,   0,   0,   0,   0)
-#define MFP_AF1			MFP(0x0000,    0,    0,   0,   0,   0,   1)
-#define MFP_AF2			MFP(0x0000,    0,    0,   0,   0,   0,   2)
-#define MFP_AF3			MFP(0x0000,    0,    0,   0,   0,   0,   3)
-#define MFP_AF4			MFP(0x0000,    0,    0,   0,   0,   0,   4)
-#define MFP_AF5			MFP(0x0000,    0,    0,   0,   0,   0,   5)
-#define MFP_AF6			MFP(0x0000,    0,    0,   0,   0,   0,   6)
-#define MFP_AF7			MFP(0x0000,    0,    0,   0,   0,   0,   7)
-#define MFP_AF_MASK		MFP(0x0000,    0,    0,   0,   0,   0,   7)
-
-#define MFP_SLEEP_CTRL2		MFP(0x0000,    0,    0,   0,   0,   1,   0)
-#define MFP_SLEEP_DIR		MFP(0x0000,    0,    0,   0,   0,   2,   0)
-#define MFP_SLEEP_DATA		MFP(0x0000,    0,    0,   0,   0,   4,   0)
-#define MFP_SLEEP_CTRL		MFP(0x0000,    0,    0,   0,   0,   8,   0)
-#define MFP_SLEEP_MASK		MFP(0x0000,    0,    0,   0,   0, 0xf,   0)
-
-#define MFP_LPM_EDGE_NONE	MFP(0x0000,    0,    0,   0,   4,   0,   0)
-#define MFP_LPM_EDGE_RISE	MFP(0x0000,    0,    0,   0,   1,   0,   0)
-#define MFP_LPM_EDGE_FALL	MFP(0x0000,    0,    0,   0,   2,   0,   0)
-#define MFP_LPM_EDGE_BOTH	MFP(0x0000,    0,    0,   0,   3,   0,   0)
-#define MFP_LPM_EDGE_MASK	MFP(0x0000,    0,    0,   0,   7,   0,   0)
-
-#define MFP_SLP_DI		MFP(0x0000,    0,    0,   1,   0,   0,   0)
-
-#define MFP_DRIVE_VERY_SLOW	MFP(0x0000,    0,    0,   0,   0,   0,   0)
-#define MFP_DRIVE_SLOW		MFP(0x0000,    0,    1,   0,   0,   0,   0)
-#define MFP_DRIVE_MEDIUM	MFP(0x0000,    0,    2,   0,   0,   0,   0)
-#define MFP_DRIVE_FAST		MFP(0x0000,    0,    3,   0,   0,   0,   0)
-#define MFP_DRIVE_MASK		MFP(0x0000,    0,    3,   0,   0,   0,   0)
-
-#define MFP_PULL_NONE		MFP(0x0000,    0,    0,   0,   0,   0,   0)
-#define MFP_PULL_LOW		MFP(0x0000,    5,    0,   0,   0,   0,   0)
-#define MFP_PULL_HIGH		MFP(0x0000,    6,    0,   0,   0,   0,   0)
-#define MFP_PULL_BOTH		MFP(0x0000,    7,    0,   0,   0,   0,   0)
-#define MFP_PULL_FLOAT		MFP(0x0000,    4,    0,   0,   0,   0,   0)
-#define MFP_PULL_MASK		MFP(0x0000,    7,    0,   0,   0,   0,   0)
-
-#define MFP_VALUE_MASK		(MFP_PULL_MASK | MFP_DRIVE_MASK | MFP_SLP_DI \
-				| MFP_LPM_EDGE_MASK | MFP_SLEEP_MASK \
-				| MFP_AF_MASK)
-#define MFP_EOC			0xffffffff	/* indicates end-of-conf */
-
-/* Functions */
-void mfp_config(u32 *mfp_cfgs);
-
-#endif /* __MVMFP_H */
diff --git a/include/net.h b/include/net.h
index 785cb1059e..e254df7d7f 100644
--- a/include/net.h
+++ b/include/net.h
@@ -167,6 +167,9 @@ enum eth_recv_flags {
  *		    to the network stack. This function should fill in the
  *		    eth_pdata::enetaddr field - optional
  * set_promisc: Enable or Disable promiscuous mode
+ * get_sset_count: Number of statistics counters
+ * get_string: Names of the statistic counters
+ * get_stats: The values of the statistic counters
  */
 struct eth_ops {
 	int (*start)(struct udevice *dev);
@@ -178,6 +181,9 @@ struct eth_ops {
 	int (*write_hwaddr)(struct udevice *dev);
 	int (*read_rom_hwaddr)(struct udevice *dev);
 	int (*set_promisc)(struct udevice *dev, bool enable);
+	int (*get_sset_count)(struct udevice *dev);
+	void (*get_strings)(struct udevice *dev, u8 *data);
+	void (*get_stats)(struct udevice *dev, u64 *data);
 };
 
 #define eth_get_ops(dev) ((struct eth_ops *)(dev)->driver->ops)
diff --git a/include/net6.h b/include/net6.h
index beafc05338..1e766aa720 100644
--- a/include/net6.h
+++ b/include/net6.h
@@ -204,7 +204,7 @@ struct icmp6_ra_prefix_info {
 	 * be initialized to zero by the sender and ignored by the receiver.
 	 */
 	struct in6_addr prefix;
-};
+} __packed;
 
 extern struct in6_addr const net_null_addr_ip6;	/* NULL IPv6 address */
 extern struct in6_addr net_gateway6;	/* Our gateways IPv6 address */
diff --git a/drivers/mtd/nvmxip/nvmxip.h b/include/nvmxip.h
index f4ef37725d..f4ef37725d 100644
--- a/drivers/mtd/nvmxip/nvmxip.h
+++ b/include/nvmxip.h
diff --git a/include/of_live.h b/include/of_live.h
index f59d6af335..05e86ac06b 100644
--- a/include/of_live.h
+++ b/include/of_live.h
@@ -36,4 +36,14 @@ int of_live_build(const void *fdt_blob, struct device_node **rootp);
  */
 int unflatten_device_tree(const void *blob, struct device_node **mynodes);
 
+/**
+ * of_live_free() - Dispose of a livetree
+ *
+ * This frees memory used by the tree, after which @root becomes invalid and
+ * cannot be used
+ *
+ * @root: Tree to dispose
+ */
+void of_live_free(struct device_node *root);
+
 #endif
diff --git a/include/omap3_spi.h b/include/omap3_spi.h
index cae3770583..5381431d43 100644
--- a/include/omap3_spi.h
+++ b/include/omap3_spi.h
@@ -46,6 +46,8 @@
 
 #define OMAP4_MCSPI_REG_OFFSET	0x100
 
+#define OMAP4_MCSPI_CHAN_NB	4
+
 /* OMAP3 McSPI registers */
 struct mcspi_channel {
 	unsigned int chconf;		/* 0x2C, 0x40, 0x54, 0x68 */
@@ -64,7 +66,7 @@ struct mcspi {
 	unsigned int wakeupenable;	/* 0x20 */
 	unsigned int syst;		/* 0x24 */
 	unsigned int modulctrl;		/* 0x28 */
-	struct mcspi_channel channel[4];
+	struct mcspi_channel channel[OMAP4_MCSPI_CHAN_NB];
 	/* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
 	/* channel1: 0x40 - 0x50, bus 0 & 1 */
 	/* channel2: 0x54 - 0x64, bus 0 & 1 */
diff --git a/include/part.h b/include/part.h
index be75c73549..8e451bbdff 100644
--- a/include/part.h
+++ b/include/part.h
@@ -98,19 +98,40 @@ struct disk_part {
  * @ifname:	Interface name (e.g. "ide", "scsi")
  * @dev:	Device number (0 for first device on that interface, 1 for
  *		second, etc.
- * Return: pointer to the block device, or NULL if not available, or an
- *	   error occurred.
+ * Return:
+ * pointer to the block device, or NULL if not available, or an error occurred.
  */
 struct blk_desc *blk_get_dev(const char *ifname, int dev);
 
 struct blk_desc *mg_disk_get_dev(int dev);
 
-/* disk/part.c */
+/**
+ * part_get_info_by_type() - Get partitions from a block device using a specific
+ * partition driver
+ *
+ * Each interface allocates its own devices and typically struct blk_desc is
+ * contained with the interface's data structure. There is no global
+ * numbering for block devices, so the interface name must be provided.
+ *
+ * @dev_desc:	Block device descriptor
+ * @part:	Partition number to read
+ * @part_type:	Partition driver to use, or PART_TYPE_UNKNOWN to automatically
+ *		choose a driver
+ * @info:	Returned partition information
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int part_get_info_by_type(struct blk_desc *dev_desc, int part, int part_type,
+			  struct disk_partition *info);
 int part_get_info(struct blk_desc *dev_desc, int part,
 		  struct disk_partition *info);
 /**
  * part_get_info_whole_disk() - get partition info for the special case of
  * a partition occupying the entire disk.
+ *
+ * @dev_desc:	block device descriptor
+ * @info:	returned partition information
+ * Return:	0 on success
  */
 int part_get_info_whole_disk(struct blk_desc *dev_desc,
 			     struct disk_partition *info);
@@ -153,15 +174,18 @@ int blk_get_device_by_str(const char *ifname, const char *dev_str,
  * This calls blk_get_device_by_str() to look up a device. It also looks up
  * a partition and returns information about it.
  *
- * @dev_part_str is in the format:
- *	<dev>.<hw_part>:<part> where <dev> is the device number,
- *	<hw_part> is the optional hardware partition number and
- *	<part> is the partition number
+ * @dev_part_str is in the format <dev>.<hw_part>:<part> where
  *
- * If ifname is "hostfs" then this function returns the sandbox host block
+ * * <dev> is the device number,
+ *
+ * * <hw_part> is the optional hardware partition number and
+ *
+ * * <part> is the partition number.
+ *
+ * If @ifname is "hostfs", then this function returns the sandbox host block
  * device.
  *
- * If ifname is ubi, then this function returns 0, with @info set to a
+ * If @ifname is "ubi", then this function returns 0, with @info set to a
  * special UBI device.
  *
  * If @dev_part_str is NULL or empty or "-", then this function looks up
@@ -170,13 +194,13 @@ int blk_get_device_by_str(const char *ifname, const char *dev_str,
  * If the partition string is empty then the first partition is used. If the
  * partition string is "auto" then the first bootable partition is used.
  *
- * @ifname:	Interface name (e.g. "ide", "scsi")
+ * @ifname:		Interface name (e.g. "ide", "scsi")
  * @dev_part_str:	Device and partition string
- * @dev_desc:	Returns a pointer to the block device on success
- * @info:	Returns partition information
+ * @dev_desc:		Returns a pointer to the block device on success
+ * @info:		Returns partition information
  * @allow_whole_dev:	true to allow the user to select partition 0
- *		(which means the whole device), false to require a valid
- *		partition number >= 1
+ *			(which means the whole device), false to require a valid
+ *			partition number >= 1
  * Return: partition number, or -1 on error
  *
  */
@@ -185,36 +209,23 @@ int blk_get_device_part_str(const char *ifname, const char *dev_part_str,
 			    struct disk_partition *info, int allow_whole_dev);
 
 /**
- * part_get_info_by_name_type() - Search for a partition by name
- *                                for only specified partition type
- *
- * @param dev_desc - block device descriptor
- * @param gpt_name - the specified table entry name
- * @param info - returns the disk partition info
- * @param part_type - only search in partitions of this type
- *
- * Return: - the partition number on match (starting on 1), -1 on no match,
- * otherwise error
- */
-int part_get_info_by_name_type(struct blk_desc *dev_desc, const char *name,
-			       struct disk_partition *info, int part_type);
-
-/**
  * part_get_info_by_name() - Search for a partition by name
  *                           among all available registered partitions
  *
- * @param dev_desc - block device descriptor
- * @param gpt_name - the specified table entry name
- * @param info - returns the disk partition info
+ * @dev_desc:	block device descriptor
+ * @name:	the specified table entry name
+ * @info:	returns the disk partition info
  *
- * Return: - the partition number on match (starting on 1), -1 on no match,
+ * Return: the partition number on match (starting on 1), -1 on no match,
  * otherwise error
  */
 int part_get_info_by_name(struct blk_desc *dev_desc,
 			      const char *name, struct disk_partition *info);
 
 /**
- * Get partition info from dev number + part name, or dev number + part number.
+ * part_get_info_by_dev_and_name_or_num() - Get partition info from dev number
+ *					    and part name, or dev number and
+ *					    part number.
  *
  * Parse a device number and partition description (either name or number)
  * in the form of device number plus partition name separated by a "#"
@@ -223,14 +234,14 @@ int part_get_info_by_name(struct blk_desc *dev_desc,
  * partition descriptions for a given interface. If the partition is found, sets
  * dev_desc and part_info accordingly with the information of the partition.
  *
- * @param[in] dev_iface	Device interface
- * @param[in] dev_part_str Input partition description, like "0#misc" or "0:1"
- * @param[out] dev_desc	Place to store the device description pointer
- * @param[out] part_info Place to store the partition information
- * @param[in] allow_whole_dev true to allow the user to select partition 0
- *		(which means the whole device), false to require a valid
- *		partition number >= 1
- * Return: the partition number on success, or negative errno on error
+ * @dev_iface:		Device interface
+ * @dev_part_str:	Input partition description, like "0#misc" or "0:1"
+ * @dev_desc:		Place to store the device description pointer
+ * @part_info:		Place to store the partition information
+ * @allow_whole_dev:	true to allow the user to select partition 0
+ *			(which means the whole device), false to require a valid
+ *			partition number >= 1
+ * Return:	the partition number on success, or negative errno on error
  */
 int part_get_info_by_dev_and_name_or_num(const char *dev_iface,
 					 const char *dev_part_str,
@@ -276,14 +287,6 @@ static inline int blk_get_device_part_str(const char *ifname,
 					  int allow_whole_dev)
 { *dev_desc = NULL; return -1; }
 
-static inline int part_get_info_by_name_type(struct blk_desc *dev_desc,
-					     const char *name,
-					     struct disk_partition *info,
-					     int part_type)
-{
-	return -ENOENT;
-}
-
 static inline int part_get_info_by_name(struct blk_desc *dev_desc,
 					const char *name,
 					struct disk_partition *info)
@@ -328,7 +331,7 @@ int part_create_block_devices(struct udevice *blk_dev);
  * @start:	Start block number to read in the partition (0=first)
  * @blkcnt:	Number of blocks to read
  * @buffer:	Destination buffer for data read
- * Returns: number of blocks read, or -ve error number (see the
+ * Return:	number of blocks read, or -ve error number (see the
  * IS_ERR_VALUE() macro
  */
 ulong disk_blk_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
@@ -341,7 +344,7 @@ ulong disk_blk_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
  * @start:	Start block number to write in the partition (0=first)
  * @blkcnt:	Number of blocks to write
  * @buffer:	Source buffer for data to write
- * Returns: number of blocks written, or -ve error number (see the
+ * Return:	number of blocks written, or -ve error number (see the
  * IS_ERR_VALUE() macro
  */
 ulong disk_blk_write(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
@@ -353,7 +356,7 @@ ulong disk_blk_write(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
  * @dev:	Device to (partially) erase (UCLASS_PARTITION)
  * @start:	Start block number to erase in the partition (0=first)
  * @blkcnt:	Number of blocks to erase
- * Returns: number of blocks erased, or -ve error number (see the
+ * Return:	number of blocks erased, or -ve error number (see the
  * IS_ERR_VALUE() macro
  */
 ulong disk_blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt);
@@ -375,35 +378,40 @@ ulong disk_blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt);
 #define part_get_info_ptr(x)	x
 #endif
 
-
+/**
+ * struct part_driver - partition driver
+ */
 struct part_driver {
+	/** @name:	partition name */
 	const char *name;
+	/** @part_type:	(MBR) partition type */
 	int part_type;
-	const int max_entries;	/* maximum number of entries to search */
-
+	/** @max_entries:	maximum number of partition table entries */
+	const int max_entries;
 	/**
-	 * get_info() - Get information about a partition
+	 * @get_info:		Get information about a partition
 	 *
-	 * @dev_desc:	Block device descriptor
-	 * @part:	Partition number (1 = first)
-	 * @info:	Returns partition information
+	 * @get_info.dev_desc:	Block device descriptor
+	 * @get_info.part:	Partition number (1 = first)
+	 * @get_info.info:	Returns partition information
 	 */
 	int (*get_info)(struct blk_desc *dev_desc, int part,
 			struct disk_partition *info);
 
 	/**
-	 * print() - Print partition information
+	 * @print:		Print partition information
 	 *
-	 * @dev_desc:	Block device descriptor
+	 * @print.dev_desc:	Block device descriptor
 	 */
 	void (*print)(struct blk_desc *dev_desc);
 
 	/**
-	 * test() - Test if a device contains this partition type
+	 * @test:		Test if a device contains this partition type
 	 *
-	 * @dev_desc:	Block device descriptor
-	 * @return 0 if the block device appears to contain this partition
-	 *	   type, -ve if not
+	 * @test.dev_desc:	Block device descriptor
+	 * @test.Return:
+	 * 0 if the block device appears to contain this partition type,
+	 * -ve if not
 	 */
 	int (*test)(struct blk_desc *dev_desc);
 };
@@ -419,52 +427,52 @@ struct part_driver {
 /**
  * write_gpt_table() - Write the GUID Partition Table to disk
  *
- * @param dev_desc - block device descriptor
- * @param gpt_h - pointer to GPT header representation
- * @param gpt_e - pointer to GPT partition table entries
+ * @dev_desc:	block device descriptor
+ * @gpt_h:	pointer to GPT header representation
+ * @gpt_e:	pointer to GPT partition table entries
  *
- * Return: - zero on success, otherwise error
+ * Return:	zero on success, otherwise error
  */
 int write_gpt_table(struct blk_desc *dev_desc,
 		  gpt_header *gpt_h, gpt_entry *gpt_e);
 
 /**
- * gpt_fill_pte(): Fill the GPT partition table entry
+ * gpt_fill_pte() - Fill the GPT partition table entry
  *
- * @param dev_desc - block device descriptor
- * @param gpt_h - GPT header representation
- * @param gpt_e - GPT partition table entries
- * @param partitions - list of partitions
- * @param parts - number of partitions
+ * @dev_desc:	block device descriptor
+ * @gpt_h:	GPT header representation
+ * @gpt_e:	GPT partition table entries
+ * @partitions:	list of partitions
+ * @parts:	number of partitions
  *
- * Return: zero on success
+ * Return:	zero on success
  */
 int gpt_fill_pte(struct blk_desc *dev_desc,
 		 gpt_header *gpt_h, gpt_entry *gpt_e,
 		 struct disk_partition *partitions, int parts);
 
 /**
- * gpt_fill_header(): Fill the GPT header
+ * gpt_fill_header() - Fill the GPT header
  *
- * @param dev_desc - block device descriptor
- * @param gpt_h - GPT header representation
- * @param str_guid - disk guid string representation
- * @param parts_count - number of partitions
+ * @dev_desc:		block device descriptor
+ * @gpt_h:		GPT header representation
+ * @str_guid:		disk guid string representation
+ * @parts_count:	number of partitions
  *
- * Return: - error on str_guid conversion error
+ * Return:		error on str_guid conversion error
  */
 int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
 		char *str_guid, int parts_count);
 
 /**
- * gpt_restore(): Restore GPT partition table
+ * gpt_restore() - Restore GPT partition table
  *
- * @param dev_desc - block device descriptor
- * @param str_disk_guid - disk GUID
- * @param partitions - list of partitions
- * @param parts - number of partitions
+ * @dev_desc:		block device descriptor
+ * @str_disk_guid:	disk GUID
+ * @partitions:		list of partitions
+ * @parts_count:	number of partitions
  *
- * Return: zero on success
+ * Return:		0 on success
  */
 int gpt_restore(struct blk_desc *dev_desc, char *str_disk_guid,
 		struct disk_partition *partitions, const int parts_count);
@@ -472,34 +480,34 @@ int gpt_restore(struct blk_desc *dev_desc, char *str_disk_guid,
 /**
  * is_valid_gpt_buf() - Ensure that the Primary GPT information is valid
  *
- * @param dev_desc - block device descriptor
- * @param buf - buffer which contains the MBR and Primary GPT info
+ * @dev_desc:	block device descriptor
+ * @buf:	buffer which contains the MBR and Primary GPT info
  *
- * Return: - '0' on success, otherwise error
+ * Return:	0 on success, otherwise error
  */
 int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf);
 
 /**
  * write_mbr_and_gpt_partitions() - write MBR, Primary GPT and Backup GPT
  *
- * @param dev_desc - block device descriptor
- * @param buf - buffer which contains the MBR and Primary GPT info
+ * @dev_desc:	block device descriptor
+ * @buf:	buffer which contains the MBR and Primary GPT info
  *
- * Return: - '0' on success, otherwise error
+ * Return:	0 on success, otherwise error
  */
 int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf);
 
 /**
- * gpt_verify_headers() - Function to read and CRC32 check of the GPT's header
+ * gpt_verify_headers() - Read and check CRC32 of the GPT's header
  *                        and partition table entries (PTE)
  *
  * As a side effect if sets gpt_head and gpt_pte so they point to GPT data.
  *
- * @param dev_desc - block device descriptor
- * @param gpt_head - pointer to GPT header data read from medium
- * @param gpt_pte - pointer to GPT partition table enties read from medium
+ * @dev_desc:	block device descriptor
+ * @gpt_head:	pointer to GPT header data read from medium
+ * @gpt_pte:	pointer to GPT partition table enties read from medium
  *
- * Return: - '0' on success, otherwise error
+ * Return:	0 on success, otherwise error
  */
 int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head,
 		       gpt_entry **gpt_pte);
@@ -508,9 +516,9 @@ int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head,
  * gpt_repair_headers() - Function to repair the GPT's header
  *                        and partition table entries (PTE)
  *
- * @param dev_desc - block device descriptor
+ * @dev_desc:	block device descriptor
  *
- * Return: - '0' on success, otherwise error
+ * Return:	0 on success, otherwise error
  */
 int gpt_repair_headers(struct blk_desc *dev_desc);
 
@@ -522,13 +530,13 @@ int gpt_repair_headers(struct blk_desc *dev_desc);
  * provided in '$partitions' environment variable. Specificially, name, start
  * and size of the partition is checked.
  *
- * @param dev_desc - block device descriptor
- * @param partitions - partition data read from '$partitions' env variable
- * @param parts - number of partitions read from '$partitions' env variable
- * @param gpt_head - pointer to GPT header data read from medium
- * @param gpt_pte - pointer to GPT partition table enties read from medium
+ * @dev_desc:	block device descriptor
+ * @partitions:	partition data read from '$partitions' env variable
+ * @parts:	number of partitions read from '$partitions' env variable
+ * @gpt_head:	pointer to GPT header data read from medium
+ * @gpt_pte:	pointer to GPT partition table enties read from medium
  *
- * Return: - '0' on success, otherwise error
+ * Return:	0 on success, otherwise error
  */
 int gpt_verify_partitions(struct blk_desc *dev_desc,
 			  struct disk_partition *partitions, int parts,
@@ -536,15 +544,15 @@ int gpt_verify_partitions(struct blk_desc *dev_desc,
 
 
 /**
- * get_disk_guid() - Function to read the GUID string from a device's GPT
+ * get_disk_guid() - Read the GUID string from a device's GPT
  *
  * This function reads the GUID string from a block device whose descriptor
  * is provided.
  *
- * @param dev_desc - block device descriptor
- * @param guid - pre-allocated string in which to return the GUID
+ * @dev_desc:	block device descriptor
+ * @guid:	pre-allocated string in which to return the GUID
  *
- * Return: - '0' on success, otherwise error
+ * Return:	0 on success, otherwise error
  */
 int get_disk_guid(struct blk_desc *dev_desc, char *guid);
 
@@ -554,19 +562,19 @@ int get_disk_guid(struct blk_desc *dev_desc, char *guid);
 /**
  * is_valid_dos_buf() - Ensure that a DOS MBR image is valid
  *
- * @param buf - buffer which contains the MBR
+ * @buf:	buffer which contains the MBR
  *
- * Return: - '0' on success, otherwise error
+ * Return:	0 on success, otherwise error
  */
 int is_valid_dos_buf(void *buf);
 
 /**
  * write_mbr_sector() - write DOS MBR
  *
- * @param dev_desc - block device descriptor
- * @param buf - buffer which contains the MBR
+ * @dev_desc:	block device descriptor
+ * @buf:	buffer which contains the MBR
  *
- * Return: - '0' on success, otherwise error
+ * Return:	0 on success, otherwise error
  */
 int write_mbr_sector(struct blk_desc *dev_desc, void *buf);
 
@@ -581,7 +589,7 @@ int layout_mbr_partitions(struct disk_partition *p, int count,
 /**
  * part_driver_get_count() - get partition driver count
  *
- * Return: - number of partition drivers
+ * Return:	number of partition drivers
  */
 static inline int part_driver_get_count(void)
 {
@@ -591,13 +599,22 @@ static inline int part_driver_get_count(void)
 /**
  * part_driver_get_first() - get first partition driver
  *
- * Return: - pointer to first partition driver on success, otherwise NULL
+ * Return:	pointer to first partition driver on success, otherwise NULL
  */
 static inline struct part_driver *part_driver_get_first(void)
 {
 	return ll_entry_start(struct part_driver, part_driver);
 }
 
+/**
+ * part_get_type_by_name() - Get partition type by name
+ *
+ * @name:	Name of partition type to look up (not case-sensitive)
+ * Return:
+ * Corresponding partition type (PART\_TYPE\_...) or PART\_TYPE\_UNKNOWN
+ */
+int part_get_type_by_name(const char *name);
+
 #else
 static inline int part_driver_get_count(void)
 { return 0; }
diff --git a/include/pca9564.h b/include/pca9564.h
deleted file mode 100644
index 99e8bcd9ad..0000000000
--- a/include/pca9564.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * File:         include/pca9564.h
- * Author:
- *
- * Created:      2009-06-23
- * Description:  PCA9564 i2c bridge driver
- *
- * Modified:
- *               Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
- *
- * Bugs:
- */
-
-#ifndef _PCA9564_H
-#define _PCA9564_H
-
-/* Clock speeds for the bus */
-#define PCA_CON_330kHz      0x00
-#define PCA_CON_288kHz      0x01
-#define PCA_CON_217kHz      0x02
-#define PCA_CON_146kHz      0x03
-#define PCA_CON_88kHz       0x04
-#define PCA_CON_59kHz       0x05
-#define PCA_CON_44kHz       0x06
-#define PCA_CON_36kHz       0x07
-
-#define PCA_CON_AA          0x80 /* Assert Acknowledge */
-#define PCA_CON_ENSIO       0x40 /* Enable */
-#define PCA_CON_STA         0x20 /* Start */
-#define PCA_CON_STO         0x10 /* Stop */
-#define PCA_CON_SI          0x08 /* Serial Interrupt */
-#define PCA_CON_CR          0x07 /* Clock Rate (MASK) */
-
-#endif
diff --git a/include/phy.h b/include/phy.h
index 247223d92b..f023a3c268 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -224,15 +224,6 @@ static inline struct phy_device *fixed_phy_create(ofnode node)
 #endif
 
 /**
- * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
- * @phydev:	PHY device
- * @dev:	Ethernet device
- * @interface:	type of MAC-PHY interface
- */
-void phy_connect_dev(struct phy_device *phydev, struct udevice *dev,
-		     phy_interface_t interface);
-
-/**
  * phy_connect() - Creates a PHY device for the Ethernet interface
  * Creates a PHY device for the PHY at the given address, if one doesn't exist
  * already, and associates it with the Ethernet device.
diff --git a/include/power/pmic.h b/include/power/pmic.h
index 70f2709bd0..636221692d 100644
--- a/include/power/pmic.h
+++ b/include/power/pmic.h
@@ -86,7 +86,7 @@ struct pmic {
 #endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */
 
 /* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */
-#ifdef CONFIG_DM_PMIC
+#if defined(CONFIG_DM_PMIC) || !CONFIG_IS_ENABLED(POWER_LEGACY)
 /**
  * U-Boot PMIC Framework
  * =====================
diff --git a/include/sja1000.h b/include/sja1000.h
deleted file mode 100644
index 6ceb6f4d48..0000000000
--- a/include/sja1000.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu>
- *
- * SJA1000 register layout for basic CAN mode
- */
-
-#ifndef _SJA1000_H_
-#define _SJA1000_H_
-
-/*
- * SJA1000 register layout in basic can mode
- */
-struct sja1000_basic_s {
-	u8 cr;
-	u8 cmr;
-	u8 sr;
-	u8 ir;
-	u8 ac;
-	u8 am;
-	u8 btr0;
-	u8 btr1;
-	u8 oc;
-	u8 txb[10];
-	u8 rxb[10];
-	u8 unused;
-	u8 cdr;
-};
-
-/* control register */
-#define CR_RR		0x01
-
-/* output control register */
-#define OC_MODE0	0x01
-#define OC_MODE1	0x02
-#define OC_POL0		0x04
-#define OC_TN0		0x08
-#define OC_TP0		0x10
-#define OC_POL1		0x20
-#define OC_TN1		0x40
-#define OC_TP1		0x80
-
-#endif
diff --git a/include/spl.h b/include/spl.h
index 7e0f5ac63b..92bcaa90a4 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -31,6 +31,7 @@ struct legacy_img_hdr;
 struct blk_desc;
 struct legacy_img_hdr;
 struct spl_boot_device;
+enum boot_device;
 
 /*
  * u_boot_first_phase() - check if this is the first U-Boot phase
@@ -525,7 +526,7 @@ void spl_board_prepare_for_linux(void);
 void spl_board_prepare_for_optee(void *fdt);
 void spl_board_prepare_for_boot(void);
 int spl_board_ubi_load_image(u32 boot_device);
-int spl_board_boot_device(u32 boot_device);
+int spl_board_boot_device(enum boot_device boot_dev_spl);
 
 /**
  * spl_board_loader_name() - Return a name for the loader
@@ -672,6 +673,9 @@ int spl_load_image_ext(struct spl_image_info *spl_image,
 int spl_load_image_ext_os(struct spl_image_info *spl_image,
 			  struct spl_boot_device *bootdev,
 			  struct blk_desc *block_dev, int partition);
+int spl_blk_load_image(struct spl_image_info *spl_image,
+		       struct spl_boot_device *bootdev,
+		       enum uclass_id uclass_id, int devnum, int partnum);
 
 /**
  * spl_early_init() - Set up device tree and driver model in SPL if enabled
@@ -872,12 +876,6 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
 			    struct spl_boot_device *bootdev);
 
 /**
- * board_spl_fit_post_load - allow process images after loading finished
- * @fit: Pointer to a valid Flattened Image Tree blob
- */
-void board_spl_fit_post_load(const void *fit);
-
-/**
  * board_spl_fit_size_align - specific size align before processing payload
  *
  */
diff --git a/include/stdio_dev.h b/include/stdio_dev.h
index 3105928970..7f18102052 100644
--- a/include/stdio_dev.h
+++ b/include/stdio_dev.h
@@ -85,15 +85,6 @@ int stdio_init_tables(void);
 int stdio_add_devices(void);
 
 /**
- * stdio_init() - Sets up stdio ready for use
- *
- * This calls stdio_init_tables() and stdio_add_devices()
- */
-int stdio_init(void);
-
-void stdio_print_current_devices(void);
-
-/**
  * stdio_deregister_dev() - deregister the device "devname".
  *
  * @dev: Stdio device to deregister
diff --git a/include/sym53c8xx.h b/include/sym53c8xx.h
deleted file mode 100644
index 7628c33195..0000000000
--- a/include/sym53c8xx.h
+++ /dev/null
@@ -1,552 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
- *
- * Most of these definitions are derived from
- * linux/drivers/scsi/sym53c8xx_defs.h
- */
-
-#ifndef _SYM53C8XX_DEFS_H
-#define _SYM53C8XX_DEFS_H
-
-
-#define SCNTL0		0x00    /* full arb., ena parity, par->ATN  */
-
-#define SCNTL1		0x01    /* no reset                         */
-  #define   ISCON   0x10  /* connected to scsi						*/
-  #define   CRST    0x08  /* force reset                      */
-  #define   IARB    0x02  /* immediate arbitration            */
-
-#define SCNTL2		0x02    /* no disconnect expected           */
-	#define   SDU     0x80  /* cmd: disconnect will raise error */
-	#define   CHM     0x40  /* sta: chained mode                */
-	#define   WSS     0x08  /* sta: wide scsi send           [W]*/
-	#define   WSR     0x01  /* sta: wide scsi received       [W]*/
-
-#define SCNTL3		0x03    /* cnf system clock dependent       */
-	#define   EWS     0x08  /* cmd: enable wide scsi         [W]*/
-	#define   ULTRA   0x80  /* cmd: ULTRA enable                */
-				/* bits 0-2, 7 rsvd for C1010       */
-
-#define SCID			0x04		/* cnf host adapter scsi address    */
-	#define   RRE     0x40  /* r/w:e enable response to resel.  */
-	#define   SRE     0x20  /* r/w:e enable response to select  */
-
-#define SXFER			0x05		/* ### Sync speed and count         */
-				/* bits 6-7 rsvd for C1010          */
-
-#define SDID			0x06	/* ### Destination-ID               */
-
-#define GPREG			0x07	/* ??? IO-Pins                      */
-
-#define SFBR			0x08	/* ### First byte in phase          */
-
-#define SOCL			0x09
-	#define   CREQ	  0x80	/* r/w: SCSI-REQ                    */
-	#define   CACK	  0x40	/* r/w: SCSI-ACK                    */
-	#define   CBSY	  0x20	/* r/w: SCSI-BSY                    */
-	#define   CSEL	  0x10	/* r/w: SCSI-SEL                    */
-	#define   CATN	  0x08	/* r/w: SCSI-ATN                    */
-	#define   CMSG	  0x04	/* r/w: SCSI-MSG                    */
-	#define   CC_D	  0x02	/* r/w: SCSI-C_D                    */
-	#define   CI_O	  0x01	/* r/w: SCSI-I_O                    */
-
-#define SSID			0x0a
-
-#define SBCL			0x0b
-
-#define DSTAT			0x0c
-  #define   DFE     0x80  /* sta: dma fifo empty              */
-  #define   MDPE    0x40  /* int: master data parity error    */
-  #define   BF      0x20  /* int: script: bus fault           */
-  #define   ABRT    0x10  /* int: script: command aborted     */
-  #define   SSI     0x08  /* int: script: single step         */
-  #define   SIR     0x04  /* int: script: interrupt instruct. */
-  #define   IID     0x01  /* int: script: illegal instruct.   */
-
-#define SSTAT0		0x0d
-  #define   ILF     0x80  /* sta: data in SIDL register lsb   */
-  #define   ORF     0x40  /* sta: data in SODR register lsb   */
-  #define   OLF     0x20  /* sta: data in SODL register lsb   */
-  #define   AIP     0x10  /* sta: arbitration in progress     */
-  #define   LOA     0x08  /* sta: arbitration lost            */
-  #define   WOA     0x04  /* sta: arbitration won             */
-  #define   IRST    0x02  /* sta: scsi reset signal           */
-  #define   SDP     0x01  /* sta: scsi parity signal          */
-
-#define SSTAT1		0x0e
-	#define   FF3210  0xf0	/* sta: bytes in the scsi fifo      */
-
-#define SSTAT2		0x0f
-  #define   ILF1    0x80  /* sta: data in SIDL register msb[W]*/
-  #define   ORF1    0x40  /* sta: data in SODR register msb[W]*/
-  #define   OLF1    0x20  /* sta: data in SODL register msb[W]*/
-  #define   DM      0x04  /* sta: DIFFSENS mismatch (895/6 only) */
-  #define   LDSC    0x02  /* sta: disconnect & reconnect      */
-
-#define DSA				0x10		/* --> Base page                    */
-#define DSA1			0x11
-#define DSA2			0x12
-#define DSA3			0x13
-
-#define ISTAT			0x14	/* --> Main Command and status      */
-  #define   CABRT   0x80  /* cmd: abort current operation     */
-  #define   SRST    0x40  /* mod: reset chip                  */
-  #define   SIGP    0x20  /* r/w: message from host to ncr    */
-  #define   SEM     0x10  /* r/w: message between host + ncr  */
-  #define   CON     0x08  /* sta: connected to scsi           */
-  #define   INTF    0x04  /* sta: int on the fly (reset by wr)*/
-  #define   SIP     0x02  /* sta: scsi-interrupt              */
-  #define   DIP     0x01  /* sta: host/script interrupt       */
-
-
-#define CTEST0		0x18
-#define CTEST1		0x19
-#define CTEST2		0x1a
-	#define   CSIGP   0x40
-				/* bits 0-2,7 rsvd for C1010        */
-
-#define CTEST3		0x1b
-	#define   FLF     0x08  /* cmd: flush dma fifo              */
-	#define   CLF		0x04	/* cmd: clear dma fifo		    */
-	#define   FM      0x02  /* mod: fetch pin mode              */
-	#define   WRIE    0x01  /* mod: write and invalidate enable */
-				/* bits 4-7 rsvd for C1010          */
-
-#define DFIFO			0x20
-#define CTEST4		0x21
-	#define   BDIS    0x80  /* mod: burst disable               */
-	#define   MPEE    0x08  /* mod: master parity error enable  */
-
-#define CTEST5		0x22
-	#define   DFS     0x20  /* mod: dma fifo size               */
-				/* bits 0-1, 3-7 rsvd for C1010          */
-#define CTEST6		0x23
-
-#define DBC				0x24	/* ### Byte count and command       */
-#define DNAD			0x28	/* ### Next command register        */
-#define DSP				0x2c	/* --> Script Pointer               */
-#define DSPS			0x30	/* --> Script pointer save/opcode#2 */
-
-#define SCRATCHA	0x34  /* Temporary register a            */
-#define SCRATCHA1	0x35
-#define SCRATCHA2	0x36
-#define SCRATCHA3	0x37
-
-#define DMODE			0x38
-	#define   BL_2    0x80  /* mod: burst length shift value +2 */
-	#define   BL_1    0x40  /* mod: burst length shift value +1 */
-	#define   ERL     0x08  /* mod: enable read line            */
-	#define   ERMP    0x04  /* mod: enable read multiple        */
-	#define   BOF     0x02  /* mod: burst op code fetch         */
-	#define   MAN     0x01  /* mod: manual start				         */
-
-#define DIEN		0x39
-#define SBR			0x3a
-
-#define DCNTL		0x3b			/* --> Script execution control     */
-	#define   CLSE    0x80  /* mod: cache line size enable      */
-	#define   PFF     0x40  /* cmd: pre-fetch flush             */
-	#define   PFEN    0x20  /* mod: pre-fetch enable            */
-	#define   SSM     0x10  /* mod: single step mode            */
-	#define   IRQM    0x08  /* mod: irq mode (1 = totem pole !) */
-	#define   STD     0x04  /* cmd: start dma mode              */
-	#define   IRQD    0x02  /* mod: irq disable                 */
-	#define	  NOCOM   0x01	/* cmd: protect sfbr while reselect */
-				/* bits 0-1 rsvd for C1010          */
-
-#define ADDER			0x3c
-
-#define SIEN			0x40	/* -->: interrupt enable            */
-#define SIST			0x42	/* <--: interrupt status            */
-  #define   SBMC    0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
-  #define   STO     0x0400/* sta: timeout (select)            */
-  #define   GEN     0x0200/* sta: timeout (general)           */
-  #define   HTH     0x0100/* sta: timeout (handshake)         */
-  #define   MA      0x80  /* sta: phase mismatch              */
-  #define   CMP     0x40  /* sta: arbitration complete        */
-  #define   SEL     0x20  /* sta: selected by another device  */
-  #define   RSL     0x10  /* sta: reselected by another device*/
-  #define   SGE     0x08  /* sta: gross error (over/underflow)*/
-  #define   UDC     0x04  /* sta: unexpected disconnect       */
-  #define   RST     0x02  /* sta: scsi bus reset detected     */
-  #define   PAR     0x01  /* sta: scsi parity error           */
-
-#define SLPAR				0x44
-#define SWIDE				0x45
-#define MACNTL			0x46
-#define GPCNTL			0x47
-#define STIME0			0x48    /* cmd: timeout for select&handshake*/
-#define STIME1			0x49    /* cmd: timeout user defined        */
-#define RESPID			0x4a    /* sta: Reselect-IDs                */
-
-#define STEST0			0x4c
-
-#define STEST1			0x4d
-	#define   SCLK    0x80	/* Use the PCI clock as SCSI clock	*/
-	#define   DBLEN   0x08	/* clock doubler running		*/
-	#define   DBLSEL  0x04	/* clock doubler selected		*/
-
-
-#define STEST2			0x4e
-	#define   ROF     0x40	/* reset scsi offset (after gross error!) */
-	#define   EXT     0x02  /* extended filtering                     */
-
-#define STEST3			0x4f
-	#define   TE     0x80	/* c: tolerAnt enable */
-	#define   HSC    0x20	/* c: Halt SCSI Clock */
-	#define   CSF    0x02	/* c: clear scsi fifo */
-
-#define SIDL			0x50	/* Lowlevel: latched from scsi data */
-#define STEST4		0x52
-	#define SMODE	0xc0	/* SCSI bus mode      (895/6 only) */
-	#define SMODE_HVD 0x40	/* High Voltage Differential       */
-	#define SMODE_SE  0x80	/* Single Ended                    */
-	#define SMODE_LVD 0xc0	/* Low Voltage Differential        */
-	#define LCKFRQ 0x20	/* Frequency Lock (895/6 only)     */
-				/* bits 0-5 rsvd for C1010          */
-
-#define SODL			0x54	/* Lowlevel: data out to scsi data  */
-
-#define SBDL			0x58	/* Lowlevel: data from scsi data    */
-
-
-/*-----------------------------------------------------------
-**
-**	Utility macros for the script.
-**
-**-----------------------------------------------------------
-*/
-
-#define REG(r) (r)
-
-/*-----------------------------------------------------------
-**
-**	SCSI phases
-**
-**	DT phases illegal for ncr driver.
-**
-**-----------------------------------------------------------
-*/
-
-#define	SCR_DATA_OUT	0x00000000
-#define	SCR_DATA_IN	0x01000000
-#define	SCR_COMMAND	0x02000000
-#define	SCR_STATUS	0x03000000
-#define SCR_DT_DATA_OUT	0x04000000
-#define SCR_DT_DATA_IN	0x05000000
-#define SCR_MSG_OUT	0x06000000
-#define SCR_MSG_IN      0x07000000
-
-#define SCR_ILG_OUT	0x04000000
-#define SCR_ILG_IN	0x05000000
-
-/*-----------------------------------------------------------
-**
-**	Data transfer via SCSI.
-**
-**-----------------------------------------------------------
-**
-**	MOVE_ABS (LEN)
-**	<<start address>>
-**
-**	MOVE_IND (LEN)
-**	<<dnad_offset>>
-**
-**	MOVE_TBL
-**	<<dnad_offset>>
-**
-**-----------------------------------------------------------
-*/
-
-#define OPC_MOVE          0x08000000
-
-#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
-#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
-#define SCR_MOVE_TBL     (0x10000000 | OPC_MOVE)
-
-#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
-#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
-#define SCR_CHMOV_TBL     (0x10000000)
-
-
-/*-----------------------------------------------------------
-**
-**	Selection
-**
-**-----------------------------------------------------------
-**
-**	SEL_ABS | SCR_ID (0..15)    [ | REL_JMP]
-**	<<alternate_address>>
-**
-**	SEL_TBL | << dnad_offset>>  [ | REL_JMP]
-**	<<alternate_address>>
-**
-**-----------------------------------------------------------
-*/
-
-#define	SCR_SEL_ABS	0x40000000
-#define	SCR_SEL_ABS_ATN	0x41000000
-#define	SCR_SEL_TBL	0x42000000
-#define	SCR_SEL_TBL_ATN	0x43000000
-
-
-#define SCR_JMP_REL     0x04000000
-#define SCR_ID(id)	(((unsigned long)(id)) << 16)
-
-/*-----------------------------------------------------------
-**
-**	Waiting for Disconnect or Reselect
-**
-**-----------------------------------------------------------
-**
-**	WAIT_DISC
-**	dummy: <<alternate_address>>
-**
-**	WAIT_RESEL
-**	<<alternate_address>>
-**
-**-----------------------------------------------------------
-*/
-
-#define	SCR_WAIT_DISC	0x48000000
-#define SCR_WAIT_RESEL  0x50000000
-
-/*-----------------------------------------------------------
-**
-**	Bit Set / Reset
-**
-**-----------------------------------------------------------
-**
-**	SET (flags {|.. })
-**
-**	CLR (flags {|.. })
-**
-**-----------------------------------------------------------
-*/
-
-#define SCR_SET(f)     (0x58000000 | (f))
-#define SCR_CLR(f)     (0x60000000 | (f))
-
-#define	SCR_CARRY	0x00000400
-#define	SCR_TRG		0x00000200
-#define	SCR_ACK		0x00000040
-#define	SCR_ATN		0x00000008
-
-
-/*-----------------------------------------------------------
-**
-**	Memory to memory move
-**
-**-----------------------------------------------------------
-**
-**	COPY (bytecount)
-**	<< source_address >>
-**	<< destination_address >>
-**
-**	SCR_COPY   sets the NO FLUSH option by default.
-**	SCR_COPY_F does not set this option.
-**
-**	For chips which do not support this option,
-**	ncr_copy_and_bind() will remove this bit.
-**-----------------------------------------------------------
-*/
-
-#define SCR_NO_FLUSH 0x01000000
-
-#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
-#define SCR_COPY_F(n) (0xc0000000 | (n))
-
-/*-----------------------------------------------------------
-**
-**	Register move and binary operations
-**
-**-----------------------------------------------------------
-**
-**	SFBR_REG (reg, op, data)        reg  = SFBR op data
-**	<< 0 >>
-**
-**	REG_SFBR (reg, op, data)        SFBR = reg op data
-**	<< 0 >>
-**
-**	REG_REG  (reg, op, data)        reg  = reg op data
-**	<< 0 >>
-**
-**-----------------------------------------------------------
-**	On 810A, 860, 825A, 875, 895 and 896 chips the content
-**	of SFBR register can be used as data (SCR_SFBR_DATA).
-**	The 896 has additionnal IO registers starting at
-**	offset 0x80. Bit 7 of register offset is stored in
-**	bit 7 of the SCRIPTS instruction first DWORD.
-**-----------------------------------------------------------
-*/
-
-#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */
-
-#define SCR_SFBR_REG(reg,op,data) \
-	(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
-
-#define SCR_REG_SFBR(reg,op,data) \
-	(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
-
-#define SCR_REG_REG(reg,op,data) \
-	(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
-
-
-#define      SCR_LOAD   0x00000000
-#define      SCR_SHL    0x01000000
-#define      SCR_OR     0x02000000
-#define      SCR_XOR    0x03000000
-#define      SCR_AND    0x04000000
-#define      SCR_SHR    0x05000000
-#define      SCR_ADD    0x06000000
-#define      SCR_ADDC   0x07000000
-
-#define      SCR_SFBR_DATA   (0x00800000>>8ul)	/* Use SFBR as data */
-
-/*-----------------------------------------------------------
-**
-**	FROM_REG (reg)		  SFBR = reg
-**	<< 0 >>
-**
-**	TO_REG	 (reg)		  reg  = SFBR
-**	<< 0 >>
-**
-**	LOAD_REG (reg, data)	  reg  = <data>
-**	<< 0 >>
-**
-**	LOAD_SFBR(data)		  SFBR = <data>
-**	<< 0 >>
-**
-**-----------------------------------------------------------
-*/
-
-#define	SCR_FROM_REG(reg) \
-	SCR_REG_SFBR(reg,SCR_OR,0)
-
-#define	SCR_TO_REG(reg) \
-	SCR_SFBR_REG(reg,SCR_OR,0)
-
-#define	SCR_LOAD_REG(reg,data) \
-	SCR_REG_REG(reg,SCR_LOAD,data)
-
-#define SCR_LOAD_SFBR(data) \
-	(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
-
-/*-----------------------------------------------------------
-**
-**	LOAD  from memory   to register.
-**	STORE from register to memory.
-**
-**	Only supported by 810A, 860, 825A, 875, 895 and 896.
-**
-**-----------------------------------------------------------
-**
-**	LOAD_ABS (LEN)
-**	<<start address>>
-**
-**	LOAD_REL (LEN)        (DSA relative)
-**	<<dsa_offset>>
-**
-**-----------------------------------------------------------
-*/
-
-#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
-#define SCR_NO_FLUSH2	0x02000000
-#define SCR_DSA_REL2	0x10000000
-
-#define SCR_LOAD_R(reg, how, n) \
-	(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
-
-#define SCR_STORE_R(reg, how, n) \
-	(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
-
-#define SCR_LOAD_ABS(reg, n)	SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
-#define SCR_LOAD_REL(reg, n)	SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
-#define SCR_LOAD_ABS_F(reg, n)	SCR_LOAD_R(reg, 0, n)
-#define SCR_LOAD_REL_F(reg, n)	SCR_LOAD_R(reg, SCR_DSA_REL2, n)
-
-#define SCR_STORE_ABS(reg, n)	SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
-#define SCR_STORE_REL(reg, n)	SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
-#define SCR_STORE_ABS_F(reg, n)	SCR_STORE_R(reg, 0, n)
-#define SCR_STORE_REL_F(reg, n)	SCR_STORE_R(reg, SCR_DSA_REL2, n)
-
-
-/*-----------------------------------------------------------
-**
-**	Waiting for Disconnect or Reselect
-**
-**-----------------------------------------------------------
-**
-**	JUMP            [ | IFTRUE/IFFALSE ( ... ) ]
-**	<<address>>
-**
-**	JUMPR           [ | IFTRUE/IFFALSE ( ... ) ]
-**	<<distance>>
-**
-**	CALL            [ | IFTRUE/IFFALSE ( ... ) ]
-**	<<address>>
-**
-**	CALLR           [ | IFTRUE/IFFALSE ( ... ) ]
-**	<<distance>>
-**
-**	RETURN          [ | IFTRUE/IFFALSE ( ... ) ]
-**	<<dummy>>
-**
-**	INT             [ | IFTRUE/IFFALSE ( ... ) ]
-**	<<ident>>
-**
-**	INT_FLY         [ | IFTRUE/IFFALSE ( ... ) ]
-**	<<ident>>
-**
-**	Conditions:
-**	     WHEN (phase)
-**	     IF   (phase)
-**	     CARRYSET
-**	     DATA (data, mask)
-**
-**-----------------------------------------------------------
-*/
-
-#define SCR_NO_OP       0x80000000
-#define SCR_JUMP        0x80080000
-#define SCR_JUMP64      0x80480000
-#define SCR_JUMPR       0x80880000
-#define SCR_CALL        0x88080000
-#define SCR_CALLR       0x88880000
-#define SCR_RETURN      0x90080000
-#define SCR_INT         0x98080000
-#define SCR_INT_FLY     0x98180000
-
-#define IFFALSE(arg)   (0x00080000 | (arg))
-#define IFTRUE(arg)    (0x00000000 | (arg))
-
-#define WHEN(phase)    (0x00030000 | (phase))
-#define IF(phase)      (0x00020000 | (phase))
-
-#define DATA(D)        (0x00040000 | ((D) & 0xff))
-#define MASK(D,M)      (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
-
-#define CARRYSET       (0x00200000)
-
-
-#define SIR_COMPLETE					 0x10000000
-/* script errors */
-#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001
-#define SIR_CMD_OUT_ILL_PH     0x00000002
-#define SIR_STATUS_ILL_PH			 0x00000003
-#define SIR_MSG_RECEIVED			 0x00000004
-#define SIR_DATA_IN_ERR        0x00000005
-#define SIR_DATA_OUT_ERR			 0x00000006
-#define SIR_SCRIPT_ERROR			 0x00000007
-#define SIR_MSG_OUT_NO_CMD		 0x00000008
-#define SIR_MSG_OVER7					 0x00000009
-/* Fly interrupt */
-#define INT_ON_FY							 0x00000080
-
-/* Hardware errors  are defined in scsi.h */
-
-#define SCSI_IDENTIFY					0xC0
-
-#endif
diff --git a/include/synopsys/dwcddr21mctl.h b/include/synopsys/dwcddr21mctl.h
deleted file mode 100644
index 6bb5cff305..0000000000
--- a/include/synopsys/dwcddr21mctl.h
+++ /dev/null
@@ -1,324 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011 Andes Technology Corp
- * Macpaul Lin <macpaul@andestech.com>
- */
-
-/*
- * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
- */
-#ifndef __DWCDDR21MCTL_H
-#define __DWCDDR21MCTL_H
-
-#ifndef __ASSEMBLY__
-struct dwcddr21mctl {
-	unsigned int	ccr;		/* Controller Configuration */
-	unsigned int	dcr;		/* DRAM Configuration */
-	unsigned int	iocr;		/* I/O Configuration */
-	unsigned int	csr;		/* Controller Status */
-	unsigned int	drr;		/* DRAM refresh */
-	unsigned int	tpr0;		/* SDRAM Timing Parameters 0 */
-	unsigned int	tpr1;		/* SDRAM Timing Parameters 1 */
-	unsigned int	tpr2;		/* SDRAM Timing Parameters 2 */
-	unsigned int	gdllcr;		/* Global DLL Control */
-	unsigned int	dllcr[10];	/* DLL Control */
-	unsigned int	rslr[4];	/* Rank System Lantency */
-	unsigned int	rdgr[4];	/* Rank DQS Gating */
-	unsigned int	dqtr[9];	/* DQ Timing */
-	unsigned int	dqstr;		/* DQS Timing */
-	unsigned int	dqsbtr;		/* DQS_b Timing */
-	unsigned int	odtcr;		/* ODT Configuration */
-	unsigned int	dtr[2];		/* Data Training */
-	unsigned int	dtar;		/* Data Training Address */
-	unsigned int	rsved[82];	/* Reserved */
-	unsigned int	mr;		/* Mode Register */
-	unsigned int	emr;		/* Extended Mode Register */
-	unsigned int	emr2;		/* Extended Mode Register 2 */
-	unsigned int	emr3;		/* Extended Mode Register 3 */
-	unsigned int	hpcr[32];	/* Host Port Configurarion */
-	unsigned int	pqcr[8];	/* Priority Queue Configuration */
-	unsigned int	mmgcr;		/* Memory Manager General Config */
-};
-#endif /* __ASSEMBLY__ */
-
-/*
- * Control Configuration Register
- */
-#define DWCDDR21MCTL_CCR_ECCEN(x)	((x) << 0)
-#define DWCDDR21MCTL_CCR_NOMRWR(x)	((x) << 1)
-#define DWCDDR21MCTL_CCR_HOSTEN(x)	((x) << 2)
-#define DWCDDR21MCTL_CCR_XBISC(x)	((x) << 3)
-#define DWCDDR21MCTL_CCR_NOAPD(x)	((x) << 4)
-#define DWCDDR21MCTL_CCR_RRB(x)		((x) << 13)
-#define DWCDDR21MCTL_CCR_DQSCFG(x)	((x) << 14)
-#define DWCDDR21MCTL_CCR_DFTLM(x)	(((x) & 0x3) << 15)
-#define DWCDDR21MCTL_CCR_DFTCMP(x)	((x) << 17)
-#define DWCDDR21MCTL_CCR_FLUSH(x)	((x) << 27)
-#define DWCDDR21MCTL_CCR_ITMRST(x)	((x) << 28)
-#define DWCDDR21MCTL_CCR_IB(x)		((x) << 29)
-#define DWCDDR21MCTL_CCR_DTT(x)		((x) << 30)
-#define DWCDDR21MCTL_CCR_IT(x)		((x) << 31)
-
-/*
- * DRAM Configuration Register
- */
-#define DWCDDR21MCTL_DCR_DDRMD(x)	((x) << 0)
-#define DWCDDR21MCTL_DCR_DIO(x)		(((x) & 0x3) << 1)
-#define DWCDDR21MCTL_DCR_DSIZE(x)	(((x) & 0x7) << 3)
-#define DWCDDR21MCTL_DCR_SIO(x)		(((x) & 0x7) << 6)
-#define DWCDDR21MCTL_DCR_PIO(x)		((x) << 9)
-#define DWCDDR21MCTL_DCR_RANKS(x)	(((x) & 0x3) << 10)
-#define DWCDDR21MCTL_DCR_RNKALL(x)	((x) << 12)
-#define DWCDDR21MCTL_DCR_AMAP(x)	(((x) & 0x3) << 13)
-#define DWCDDR21MCTL_DCR_RANK(x)	(((x) & 0x3) << 25)
-#define DWCDDR21MCTL_DCR_CMD(x)		(((x) & 0xf) << 27)
-#define DWCDDR21MCTL_DCR_EXE(x)		((x) << 31)
-
-/*
- * I/O Configuration Register
- */
-#define DWCDDR21MCTL_IOCR_RTT(x)	(((x) & 0xf) << 0)
-#define DWCDDR21MCTL_IOCR_DS(x)		(((x) & 0xf) << 4)
-#define DWCDDR21MCTL_IOCR_TESTEN(x)	((x) << 0x8)
-#define DWCDDR21MCTL_IOCR_RTTOH(x)	(((x) & 0x7) << 26)
-#define DWCDDR21MCTL_IOCR_RTTOE(x)	((x) << 29)
-#define DWCDDR21MCTL_IOCR_DQRTT(x)	((x) << 30)
-#define DWCDDR21MCTL_IOCR_DQSRTT(x)	((x) << 31)
-
-/*
- * Controller Status Register
- */
-#define DWCDDR21MCTL_CSR_DRIFT(x)	(((x) & 0x3ff) << 0)
-#define DWCDDR21MCTL_CSR_DFTERR(x)	((x) << 18)
-#define DWCDDR21MCTL_CSR_ECCERR(x)	((x) << 19)
-#define DWCDDR21MCTL_CSR_DTERR(x)	((x) << 20)
-#define DWCDDR21MCTL_CSR_DTIERR(x)	((x) << 21)
-#define DWCDDR21MCTL_CSR_ECCSEC(x)	((x) << 22)
-
-/*
- * DRAM Refresh Register
- */
-#define DWCDDR21MCTL_DRR_TRFC(x)	(((x) & 0xff) << 0)
-#define DWCDDR21MCTL_DRR_TRFPRD(x)	(((x) & 0xffff) << 8)
-#define DWCDDR21MCTL_DRR_RFBURST(x)	(((x) & 0xf) << 24)
-#define DWCDDR21MCTL_DRR_RD(x)		((x) << 31)
-
-/*
- * SDRAM Timing Parameters Register 0
- */
-#define DWCDDR21MCTL_TPR0_TMRD(x)	(((x) & 0x3) << 0)
-#define DWCDDR21MCTL_TPR0_TRTP(x)	(((x) & 0x7) << 2)
-#define DWCDDR21MCTL_TPR0_TWTR(x)	(((x) & 0x7) << 5)
-#define DWCDDR21MCTL_TPR0_TRP(x)	(((x) & 0xf) << 8)
-#define DWCDDR21MCTL_TPR0_TRCD(x)	(((x) & 0xf) << 12)
-#define DWCDDR21MCTL_TPR0_TRAS(x)	(((x) & 0x1f) << 16)
-#define DWCDDR21MCTL_TPR0_TRRD(x)	(((x) & 0xf) << 21)
-#define DWCDDR21MCTL_TPR0_TRC(x)	(((x) & 0x3f) << 25)
-#define DWCDDR21MCTL_TPR0_TCCD(x)	((x) << 31)
-
-/*
- * SDRAM Timing Parameters Register 1
- */
-#define DWCDDR21MCTL_TPR1_TAOND(x)	(((x) & 0x3) << 0)
-#define DWCDDR21MCTL_TPR1_TRTW(x)	((x) << 2)
-#define DWCDDR21MCTL_TPR1_TFAW(x)	(((x) & 0x3f) << 3)
-#define DWCDDR21MCTL_TPR1_TRNKRTR(x)	(((x) & 0x3) << 12)
-#define DWCDDR21MCTL_TPR1_TRNKWTW(x)	(((x) & 0x3) << 14)
-#define DWCDDR21MCTL_TPR1_XCL(x)	(((x) & 0xf) << 23)
-#define DWCDDR21MCTL_TPR1_XWR(x)	(((x) & 0xf) << 27)
-#define DWCDDR21MCTL_TPR1_XTP(x)	((x) << 31)
-
-/*
- * SDRAM Timing Parameters Register 2
- */
-#define DWCDDR21MCTL_TPR2_TXS(x)	(((x) & 0x3ff) << 0)
-#define DWCDDR21MCTL_TPR2_TXP(x)	(((x) & 0x1f) << 10)
-#define DWCDDR21MCTL_TPR2_TCKE(x)	(((x) & 0xf) << 15)
-
-/*
- * Global DLL Control Register
- */
-#define DWCDDR21MCTL_GDLLCR_DRES(x)	(((x) & 0x3) << 0)
-#define DWCDDR21MCTL_GDLLCR_IPUMP(x)	(((x) & 0x7) << 2)
-#define DWCDDR21MCTL_GDLLCR_TESTEN(x)	((x) << 5)
-#define DWCDDR21MCTL_GDLLCR_DTC(x)	(((x) & 0x7) << 6)
-#define DWCDDR21MCTL_GDLLCR_ATC(x)	(((x) & 0x3) << 9)
-#define DWCDDR21MCTL_GDLLCR_TESTSW(x)	((x) << 11)
-#define DWCDDR21MCTL_GDLLCR_MBIAS(x)	(((x) & 0xff) << 12)
-#define DWCDDR21MCTL_GDLLCR_SBIAS(x)	(((x) & 0xff) << 20)
-#define DWCDDR21MCTL_GDLLCR_LOCKDET(x)	((x) << 29)
-
-/*
- * DLL Control Register 0-9
- */
-#define DWCDDR21MCTL_DLLCR_SFBDLY(x)	(((x) & 0x7) << 0)
-#define DWCDDR21MCTL_DLLCR_SFWDLY(x)	(((x) & 0x7) << 3)
-#define DWCDDR21MCTL_DLLCR_MFBDLY(x)	(((x) & 0x7) << 6)
-#define DWCDDR21MCTL_DLLCR_MFWDLY(x)	(((x) & 0x7) << 9)
-#define DWCDDR21MCTL_DLLCR_SSTART(x)	(((x) & 0x3) << 12)
-#define DWCDDR21MCTL_DLLCR_PHASE(x)	(((x) & 0xf) << 14)
-#define DWCDDR21MCTL_DLLCR_ATESTEN(x)	((x) << 18)
-#define DWCDDR21MCTL_DLLCR_DRSVD(x)	((x) << 19)
-#define DWCDDR21MCTL_DLLCR_DD(x)	((x) << 31)
-
-/*
- * Rank System Lantency Register
- */
-#define DWCDDR21MCTL_RSLR_SL0(x)	(((x) & 0x7) << 0)
-#define DWCDDR21MCTL_RSLR_SL1(x)	(((x) & 0x7) << 3)
-#define DWCDDR21MCTL_RSLR_SL2(x)	(((x) & 0x7) << 6)
-#define DWCDDR21MCTL_RSLR_SL3(x)	(((x) & 0x7) << 9)
-#define DWCDDR21MCTL_RSLR_SL4(x)	(((x) & 0x7) << 12)
-#define DWCDDR21MCTL_RSLR_SL5(x)	(((x) & 0x7) << 15)
-#define DWCDDR21MCTL_RSLR_SL6(x)	(((x) & 0x7) << 18)
-#define DWCDDR21MCTL_RSLR_SL7(x)	(((x) & 0x7) << 21)
-#define DWCDDR21MCTL_RSLR_SL8(x)	(((x) & 0x7) << 24)
-
-/*
- * Rank DQS Gating Register
- */
-#define DWCDDR21MCTL_RDGR_DQSSEL0(x)	(((x) & 0x3) << 0)
-#define DWCDDR21MCTL_RDGR_DQSSEL1(x)	(((x) & 0x3) << 2)
-#define DWCDDR21MCTL_RDGR_DQSSEL2(x)	(((x) & 0x3) << 4)
-#define DWCDDR21MCTL_RDGR_DQSSEL3(x)	(((x) & 0x3) << 6)
-#define DWCDDR21MCTL_RDGR_DQSSEL4(x)	(((x) & 0x3) << 8)
-#define DWCDDR21MCTL_RDGR_DQSSEL5(x)	(((x) & 0x3) << 10)
-#define DWCDDR21MCTL_RDGR_DQSSEL6(x)	(((x) & 0x3) << 12)
-#define DWCDDR21MCTL_RDGR_DQSSEL7(x)	(((x) & 0x3) << 14)
-#define DWCDDR21MCTL_RDGR_DQSSEL8(x)	(((x) & 0x3) << 16)
-
-/*
- * DQ Timing Register
- */
-#define DWCDDR21MCTL_DQTR_DQDLY0(x)	(((x) & 0xf) << 0)
-#define DWCDDR21MCTL_DQTR_DQDLY1(x)	(((x) & 0xf) << 4)
-#define DWCDDR21MCTL_DQTR_DQDLY2(x)	(((x) & 0xf) << 8)
-#define DWCDDR21MCTL_DQTR_DQDLY3(x)	(((x) & 0xf) << 12)
-#define DWCDDR21MCTL_DQTR_DQDLY4(x)	(((x) & 0xf) << 16)
-#define DWCDDR21MCTL_DQTR_DQDLY5(x)	(((x) & 0xf) << 20)
-#define DWCDDR21MCTL_DQTR_DQDLY6(x)	(((x) & 0xf) << 24)
-#define DWCDDR21MCTL_DQTR_DQDLY7(x)	(((x) & 0xf) << 28)
-
-/*
- * DQS Timing Register
- */
-#define DWCDDR21MCTL_DQSTR_DQSDLY0(x)	(((x) & 0x7) << 0)
-#define DWCDDR21MCTL_DQSTR_DQSDLY1(x)	(((x) & 0x7) << 3)
-#define DWCDDR21MCTL_DQSTR_DQSDLY2(x)	(((x) & 0x7) << 6)
-#define DWCDDR21MCTL_DQSTR_DQSDLY3(x)	(((x) & 0x7) << 9)
-#define DWCDDR21MCTL_DQSTR_DQSDLY4(x)	(((x) & 0x7) << 12)
-#define DWCDDR21MCTL_DQSTR_DQSDLY5(x)	(((x) & 0x7) << 15)
-#define DWCDDR21MCTL_DQSTR_DQSDLY6(x)	(((x) & 0x7) << 18)
-#define DWCDDR21MCTL_DQSTR_DQSDLY7(x)	(((x) & 0x7) << 21)
-#define DWCDDR21MCTL_DQSTR_DQSDLY8(x)	(((x) & 0x7) << 24)
-
-/*
- * DQS_b (DQSBTR) Timing Register
- */
-#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x)	(((x) & 0x7) << 0)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x)	(((x) & 0x7) << 3)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x)	(((x) & 0x7) << 6)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x)	(((x) & 0x7) << 9)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x)	(((x) & 0x7) << 12)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x)	(((x) & 0x7) << 15)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x)	(((x) & 0x7) << 18)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x)	(((x) & 0x7) << 21)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x)	(((x) & 0x7) << 24)
-
-/*
- * ODT Configuration Register
- */
-#define DWCDDR21MCTL_ODTCR_RDODT0(x)	(((x) & 0xf) << 0)
-#define DWCDDR21MCTL_ODTCR_RDODT1(x)	(((x) & 0xf) << 4)
-#define DWCDDR21MCTL_ODTCR_RDODT2(x)	(((x) & 0xf) << 8)
-#define DWCDDR21MCTL_ODTCR_RDODT3(x)	(((x) & 0xf) << 12)
-#define DWCDDR21MCTL_ODTCR_WDODT0(x)	(((x) & 0xf) << 16)
-#define DWCDDR21MCTL_ODTCR_WDODT1(x)	(((x) & 0xf) << 20)
-#define DWCDDR21MCTL_ODTCR_WDODT2(x)	(((x) & 0xf) << 24)
-#define DWCDDR21MCTL_ODTCR_WDODT3(x)	(((x) & 0xf) << 28)
-
-/*
- * Data Training Register
- */
-#define DWCDDR21MCTL_DTR0_DTBYTE0(x)	(((x) & 0xff) << 0)	/* def: 0x11 */
-#define DWCDDR21MCTL_DTR0_DTBYTE1(x)	(((x) & 0xff) << 8)	/* def: 0xee */
-#define DWCDDR21MCTL_DTR0_DTBYTE2(x)	(((x) & 0xff) << 16)	/* def: 0x22 */
-#define DWCDDR21MCTL_DTR0_DTBYTE3(x)	(((x) & 0xff) << 24)	/* def: 0xdd */
-
-#define DWCDDR21MCTL_DTR1_DTBYTE4(x)	(((x) & 0xff) << 0)	/* def: 0x44 */
-#define DWCDDR21MCTL_DTR1_DTBYTE5(x)	(((x) & 0xff) << 8)	/* def: 0xbb */
-#define DWCDDR21MCTL_DTR1_DTBYTE6(x)	(((x) & 0xff) << 16)	/* def: 0x88 */
-#define DWCDDR21MCTL_DTR1_DTBYTE7(x)	(((x) & 0xff) << 24)	/* def: 0x77 */
-
-/*
- * Data Training Address Register
- */
-#define DWCDDR21MCTL_DTAR_DTCOL(x)	(((x) & 0xfff) << 0)
-#define DWCDDR21MCTL_DTAR_DTROW(x)	(((x) & 0xffff) << 12)
-#define DWCDDR21MCTL_DTAR_DTBANK(x)	(((x) & 0x7) << 28)
-
-/*
- * Mode Register
- */
-#define DWCDDR21MCTL_MR_BL(x)		(((x) & 0x7) << 0)
-#define DWCDDR21MCTL_MR_BT(x)		((x) << 3)
-#define DWCDDR21MCTL_MR_CL(x)		(((x) & 0x7) << 4)
-#define DWCDDR21MCTL_MR_TM(x)		((x) << 7)
-#define DWCDDR21MCTL_MR_DR(x)		((x) << 8)
-#define DWCDDR21MCTL_MR_WR(x)		(((x) & 0x7) << 9)
-#define DWCDDR21MCTL_MR_PD(x)		((x) << 12)
-
-/*
- * Extended Mode register
- */
-#define DWCDDR21MCTL_EMR_DE(x)		((x) << 0)
-#define DWCDDR21MCTL_EMR_ODS(x)		((x) << 1)
-#define DWCDDR21MCTL_EMR_RTT2(x)	((x) << 2)
-#define DWCDDR21MCTL_EMR_AL(x)		(((x) & 0x7) << 3)
-#define DWCDDR21MCTL_EMR_RTT6(x)	((x) << 6)
-#define DWCDDR21MCTL_EMR_OCD(x)		(((x) & 0x7) << 7)
-#define DWCDDR21MCTL_EMR_DQS(x)		((x) << 10)
-#define DWCDDR21MCTL_EMR_RDQS(x)	((x) << 11)
-#define DWCDDR21MCTL_EMR_OE(x)		((x) << 12)
-
-#define EMR_RTT2(x)			DWCDDR21MCTL_EMR_RTT2(x)
-#define EMR_RTT6(x)			DWCDDR21MCTL_EMR_RTT6(x)
-
-#define DWCDDR21MCTL_EMR_RTT_DISABLED	(EMR_RTT6(0) | EMR_RTT2(0))
-#define DWCDDR21MCTL_EMR_RTT_75		(EMR_RTT6(0) | EMR_RTT2(1))
-#define DWCDDR21MCTL_EMR_RTT_150	(EMR_RTT6(1) | EMR_RTT2(0))
-#define DWCDDR21MCTL_EMR_RTT_50		(EMR_RTT6(1) | EMR_RTT2(1))
-
-/*
- * Extended Mode register 2
- */
-#define DWCDDR21MCTL_EMR2_PASR(x)	(((x) & 0x7) << 0)
-#define DWCDDR21MCTL_EMR2_DCC(x)	((x) << 3)
-#define DWCDDR21MCTL_EMR2_SRF(x)	((x) << 7)
-
-/*
- * Extended Mode register 3: [15:0] reserved for JEDEC.
- */
-
-/*
- * Host port Configuration register 0-31
- */
-#define DWCDDR21MCTL_HPCR_HPBL(x)	(((x) & 0xf) << 0)
-
-/*
- * Priority Queue Configuration register 0-7
- */
-#define DWCDDR21MCTL_HPCR_TOUT(x)	(((x) & 0xf) << 0)
-#define DWCDDR21MCTL_HPCR_TOUTX(x)	(((x) & 0x3) << 8)
-#define DWCDDR21MCTL_HPCR_LPQS(x)	(((x) & 0x3) << 10)
-#define DWCDDR21MCTL_HPCR_PQBL(x)	(((x) & 0xff) << 12)
-#define DWCDDR21MCTL_HPCR_SWAIT(x)	(((x) & 0x1f) << 20)
-#define DWCDDR21MCTL_HPCR_INTRPT(x)	(((x) & 0x7) << 25)
-#define DWCDDR21MCTL_HPCR_APQS(x)	((x) << 28)
-
-/*
- * Memory Manager General Configuration register
- */
-#define DWCDDR21MCTL_MMGCR_UHPP(x)	(((x) & 0x3) << 0)
-
-#endif	/* __DWCDDR21MCTL_H */
diff --git a/include/test/cedit-test.h b/include/test/cedit-test.h
new file mode 100644
index 0000000000..349df75b16
--- /dev/null
+++ b/include/test/cedit-test.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Binding shared between cedit.dtsi and test/boot/expo.c
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __cedit_test_h
+#define __cedit_test_h
+
+#define ID_PROMPT		1
+#define ID_SCENE1		2
+#define ID_SCENE1_TITLE		3
+
+#define ID_CPU_SPEED		4
+#define ID_CPU_SPEED_TITLE	5
+#define ID_CPU_SPEED_1		6
+#define ID_CPU_SPEED_2		7
+#define ID_CPU_SPEED_3		8
+
+#define ID_POWER_LOSS		9
+#define ID_AC_OFF		10
+#define ID_AC_ON		11
+#define ID_AC_MEMORY		12
+
+#define ID_DYNAMIC_START	13
+
+#endif
diff --git a/include/test/suites.h b/include/test/suites.h
index 7349ce5aa6..1c7dc65966 100644
--- a/include/test/suites.h
+++ b/include/test/suites.h
@@ -28,6 +28,7 @@ int cmd_ut_category(const char *name, const char *prefix,
 
 int do_ut_addrmap(struct cmd_tbl *cmdtp, int flag, int argc,
 		  char *const argv[]);
+int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
 int do_ut_bootm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
 int do_ut_bootstd(struct cmd_tbl *cmdtp, int flag, int argc,
 		  char *const argv[]);
diff --git a/include/test/ut.h b/include/test/ut.h
index dddf9ad241..ea6ee95d73 100644
--- a/include/test/ut.h
+++ b/include/test/ut.h
@@ -130,7 +130,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 									\
 	if (!(cond)) {							\
 		ut_fail(uts, __FILE__, __LINE__, __func__, #cond);	\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -142,7 +142,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 	if (!(cond)) {							\
 		ut_failf(uts, __FILE__, __LINE__, __func__, #cond,	\
 			 fmt, ##args);					\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -157,7 +157,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 			 #expr1 " == " #expr2,				\
 			 "Expected %#x (%d), got %#x (%d)",		\
 			 _val1, _val1, _val2, _val2);			\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -175,7 +175,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 			 (unsigned long long)_val1,			\
 			 (unsigned long long)_val2,			\
 			 (unsigned long long)_val2);			\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -189,7 +189,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 		ut_failf(uts, __FILE__, __LINE__, __func__,		\
 			 #expr1 " = " #expr2,				\
 			 "Expected \"%s\", got \"%s\"", _val1, _val2);	\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -208,7 +208,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 			 #expr1 " = " #expr2,				\
 			 "Expected \"%.*s\", got \"%.*s\"",		\
 			 _len, _val1, _len, _val2);			\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -228,7 +228,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 			 #expr1 " = " #expr2,				\
 			 "Expected \"%s\", got \"%s\"",			\
 			 __buf1, __buf2);				\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -242,7 +242,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 		ut_failf(uts, __FILE__, __LINE__, __func__,		\
 			 #expr1 " = " #expr2,				\
 			 "Expected %p, got %p", _val1, _val2);		\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -257,7 +257,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 		ut_failf(uts, __FILE__, __LINE__, __func__,		\
 			 #expr1 " = " #expr2,				\
 			 "Expected %lx, got %lx", _val1, _val2);	\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -271,7 +271,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 		ut_failf(uts, __FILE__, __LINE__, __func__,		\
 			 #expr " != NULL",				\
 			 "Expected NULL, got %p", _val);		\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -285,7 +285,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 		ut_failf(uts, __FILE__, __LINE__, __func__,		\
 			 #expr " = NULL",				\
 			 "Expected non-null, got NULL");		\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -300,7 +300,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 			 #expr " = NULL",				\
 			 "Expected pointer, got error %ld",		\
 			 PTR_ERR(_val));				\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -316,7 +316,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 		ut_failf(uts, __FILE__, __LINE__, __func__,		\
 			 "console", "\nExpected '%s',\n     got '%s'",	\
 			 uts->expect_str, uts->actual_str);		\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -329,7 +329,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 		ut_failf(uts, __FILE__, __LINE__, __func__,		\
 			 "console", "\nExpected '%s',\n     got '%s'",	\
 			 uts->expect_str, uts->actual_str);		\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -341,7 +341,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 	if (ut_check_skipline(uts)) {					\
 		ut_failf(uts, __FILE__, __LINE__, __func__,		\
 			 "console", "\nExpected a line, got end");	\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -354,7 +354,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 		ut_failf(uts, __FILE__, __LINE__, __func__,		\
 			 "console", "\nExpected '%s',\n     got to '%s'", \
 			 uts->expect_str, uts->actual_str);		\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -367,7 +367,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 		ut_failf(uts, __FILE__, __LINE__, __func__,		\
 			 "console", "Expected no more output, got '%s'",\
 			 uts->actual_str);				\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
@@ -381,7 +381,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes);
 			 "console",					\
 			"Expected dump of length %x bytes, got '%s'",	\
 			 total_bytes, uts->actual_str);			\
-		__ret = CMD_RET_FAILURE;				\
+		return CMD_RET_FAILURE;					\
 	}								\
 	__ret;								\
 })
diff --git a/include/usb.h b/include/usb.h
index 42b001c3dd..09e3f0cb30 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -257,7 +257,14 @@ int usb_kbd_deregister(int force);
 
 #endif
 /* routines */
-int usb_init(void); /* initialize the USB Controller */
+
+/*
+ * usb_init() - initialize the USB Controllers
+ *
+ * Returns: 0 if OK, -ENOENT if there are no USB devices
+ */
+int usb_init(void);
+
 int usb_stop(void); /* stop the USB Controller */
 int usb_detect_change(void); /* detect if a USB device has been (un)plugged */
 
diff --git a/include/uuid.h b/include/uuid.h
index 4a4883d3b5..89b93e642b 100644
--- a/include/uuid.h
+++ b/include/uuid.h
@@ -2,6 +2,10 @@
 /*
  * Copyright (C) 2014 Samsung Electronics
  * Przemyslaw Marczak <p.marczak@samsung.com>
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
  */
 #ifndef __UUID_H__
 #define __UUID_H__
@@ -44,4 +48,15 @@ int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin);
 const char *uuid_guid_get_str(const unsigned char *guid_bin);
 void gen_rand_uuid(unsigned char *uuid_bin);
 void gen_rand_uuid_str(char *uuid_str, int str_format);
+
+/**
+ * uuid_str_to_le_bin() - Convert string UUID to little endian binary data.
+ * @uuid_str:	pointer to UUID string
+ * @uuid_bin:	pointer to allocated array for little endian output [16B]
+ * Return:
+ *    uuid_bin filled with little endian UUID data
+ *    On success 0 is returned. Otherwise, failure code.
+ */
+int uuid_str_to_le_bin(const char *uuid_str, unsigned char *uuid_bin);
+
 #endif
diff --git a/include/versalpl.h b/include/versalpl.h
index 0cc101be2f..7dae56b236 100644
--- a/include/versalpl.h
+++ b/include/versalpl.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * (C) Copyright 2019 Xilinx, Inc,
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 #ifndef _VERSALPL_H_
diff --git a/include/version_string.h b/include/version_string.h
index a89a6e4370..a7d07e4cc7 100644
--- a/include/version_string.h
+++ b/include/version_string.h
@@ -4,5 +4,7 @@
 #define	__VERSION_STRING_H__
 
 extern const char version_string[];
+extern const unsigned short version_num;
+extern const unsigned char version_num_patch;
 
 #endif	/* __VERSION_STRING_H__ */
diff --git a/include/video.h b/include/video.h
index 29c4f51efb..269915160b 100644
--- a/include/video.h
+++ b/include/video.h
@@ -64,6 +64,7 @@ enum video_log2_bpp {
 
 enum video_format {
 	VIDEO_UNKNOWN,
+	VIDEO_RGBA8888,
 	VIDEO_X8B8G8R8,
 	VIDEO_X8R8G8B8,
 	VIDEO_X2R10G10B10,
@@ -133,6 +134,30 @@ struct video_ops {
 
 #define video_get_ops(dev)        ((struct video_ops *)(dev)->driver->ops)
 
+/**
+ * struct video_handoff - video information passed from SPL
+ *
+ * This is used when video is set up by SPL, to provide the details to U-Boot
+ * proper.
+ *
+ * @fb: Base address of frame buffer, 0 if not yet known
+ * @size: Frame-buffer size, in bytes
+ * @xsize:	Number of pixel columns (e.g. 1366)
+ * @ysize:	Number of pixels rows (e.g.. 768)
+ * @line_length:	Length of each frame buffer line, in bytes. This can be
+ *		set by the driver, but if not, the uclass will set it after
+ *		probing
+ * @bpix:	Encoded bits per pixel (enum video_log2_bpp)
+ */
+struct video_handoff {
+	u64 fb;
+	u32 size;
+	u16 xsize;
+	u16 ysize;
+	u32 line_length;
+	u8 bpix;
+};
+
 /** enum colour_idx - the 16 colors supported by consoles */
 enum colour_idx {
 	VID_BLACK = 0,
@@ -162,11 +187,11 @@ enum colour_idx {
  * The caller has to guarantee that the color index is less than
  * VID_COLOR_COUNT.
  *
- * @priv	private data of the console device
- * @idx		color index
+ * @priv	private data of the video device (UCLASS_VIDEO)
+ * @idx		color index (e.g. VID_YELLOW)
  * Return:	color value
  */
-u32 video_index_to_colour(struct video_priv *priv, unsigned int idx);
+u32 video_index_to_colour(struct video_priv *priv, enum colour_idx idx);
 
 /**
  * video_reserve() - Reserve frame-buffer memory for video devices
@@ -204,6 +229,22 @@ int video_clear(struct udevice *dev);
 int video_fill(struct udevice *dev, u32 colour);
 
 /**
+ * video_fill_part() - Erase a region
+ *
+ * Erase a rectangle of the display within the given bounds.
+ *
+ * @dev:	Device to update
+ * @xstart:	X start position in pixels from the left
+ * @ystart:	Y start position in pixels from the top
+ * @xend:	X end position in pixels from the left
+ * @yend:	Y end position  in pixels from the top
+ * @colour:	Value to write
+ * Return: 0 if OK, -ENOSYS if the display depth is not supported
+ */
+int video_fill_part(struct udevice *dev, int xstart, int ystart, int xend,
+		    int yend, u32 colour);
+
+/**
  * video_sync() - Sync a device's frame buffer with its hardware
  *
  * @vid:	Device to sync
@@ -365,4 +406,13 @@ int bmp_display(ulong addr, int x, int y);
  */
 int bmp_info(ulong addr);
 
+/*
+ * video_reserve_from_bloblist()- Reserve frame-buffer memory for video devices
+ * using blobs.
+ *
+ * @ho: video information passed from SPL
+ * Returns: 0 (always)
+ */
+int video_reserve_from_bloblist(struct video_handoff *ho);
+
 #endif
diff --git a/include/video_console.h b/include/video_console.h
index 3db9a7e1fb..2694e44f6e 100644
--- a/include/video_console.h
+++ b/include/video_console.h
@@ -72,6 +72,38 @@ struct vidfont_info {
 };
 
 /**
+ * struct vidconsole_colour - Holds colour information
+ *
+ * @colour_fg:	Foreground colour (pixel value)
+ * @colour_bg:	Background colour (pixel value)
+ */
+struct vidconsole_colour {
+	u32 colour_fg;
+	u32 colour_bg;
+};
+
+/**
+ * struct vidconsole_bbox - Bounding box of text
+ *
+ * This describes the bounding box of something, measured in pixels. The x0/y0
+ * pair is inclusive; the x1/y2 pair is exclusive, meaning that it is one pixel
+ * beyond the extent of the object
+ *
+ * @valid: Values are valid (bounding box is known)
+ * @x0: left x position, in pixels from left side
+ * @y0: top y position, in pixels from top
+ * @x1: right x position + 1
+ * @y1: botton y position + 1
+ */
+struct vidconsole_bbox {
+	bool valid;
+	int x0;
+	int y0;
+	int x1;
+	int y1;
+};
+
+/**
  * struct vidconsole_ops - Video console operations
  *
  * These operations work on either an absolute console position (measured
@@ -178,6 +210,20 @@ struct vidconsole_ops {
 	 * Returns: 0 on success, -ENOENT if no such font
 	 */
 	int (*select_font)(struct udevice *dev, const char *name, uint size);
+
+	/**
+	 * measure() - Measure the bounds of some text
+	 *
+	 * @dev:	Device to adjust
+	 * @name:	Font name to use (NULL to use default)
+	 * @size:	Font size to use (0 to use default)
+	 * @text:	Text to measure
+	 * @bbox:	Returns bounding box of text, assuming it is positioned
+	 *		at 0,0
+	 * Returns: 0 on success, -ENOENT if no such font
+	 */
+	int (*measure)(struct udevice *dev, const char *name, uint size,
+		       const char *text, struct vidconsole_bbox *bbox);
 };
 
 /* Get a pointer to the driver operations for a video console device */
@@ -204,6 +250,38 @@ int vidconsole_get_font(struct udevice *dev, int seq,
  */
 int vidconsole_select_font(struct udevice *dev, const char *name, uint size);
 
+/*
+ * vidconsole_measure() - Measuring the bounding box of some text
+ *
+ * @dev: Console device to use
+ * @name: Font name, NULL for default
+ * @size: Font size, ignored if @name is NULL
+ * @text: Text to measure
+ * @bbox: Returns nounding box of text
+ * Returns: 0 if OK, -ve on error
+ */
+int vidconsole_measure(struct udevice *dev, const char *name, uint size,
+		       const char *text, struct vidconsole_bbox *bbox);
+
+/**
+ * vidconsole_push_colour() - Temporarily change the font colour
+ *
+ * @dev:	Device to adjust
+ * @fg:		Foreground colour to select
+ * @bg:		Background colour to select
+ * @old:	Place to store the current colour, so it can be restored
+ */
+void vidconsole_push_colour(struct udevice *dev, enum colour_idx fg,
+			    enum colour_idx bg, struct vidconsole_colour *old);
+
+/**
+ * vidconsole_pop_colour() - Restore the original colour
+ *
+ * @dev:	Device to adjust
+ * @old:	Old colour to be restored
+ */
+void vidconsole_pop_colour(struct udevice *dev, struct vidconsole_colour *old);
+
 /**
  * vidconsole_putc_xy() - write a single character to a position
  *
diff --git a/include/video_easylogo.h b/include/video_easylogo.h
deleted file mode 100644
index ce93868da0..0000000000
--- a/include/video_easylogo.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
-** video easylogo
-** ==============
-** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
-** AIRVENT SAM s.p.a - RIMINI(ITALY)
-**
-** This utility is still under construction!
-*/
-
-#ifndef _EASYLOGO_H_
-#define _EASYLOGO_H_
-
-#if 0
-#define ENABLE_ASCII_BANNERS
-#endif
-
-typedef struct {
-	unsigned char	*data;
-	int		width;
-	int		height;
-	int		bpp;
-	int		pixel_size;
-	int		size;
-} fastimage_t ;
-
-#endif	/* _EASYLOGO_H_ */
diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
index f7a4a39d35..18a87d2749 100644
--- a/include/zynqmp_firmware.h
+++ b/include/zynqmp_firmware.h
@@ -35,7 +35,7 @@ enum pm_api_id {
 	PM_FPGA_LOAD = 22,
 	PM_FPGA_GET_STATUS = 23,
 	PM_GET_CHIPID = 24,
-	/* ID 25 is been used by U-boot to process secure boot images */
+	/* ID 25 is been used by U-Boot to process secure boot images */
 	/* Secure library generic API functions */
 	PM_SECURE_SHA = 26,
 	PM_SECURE_RSA = 27,
@@ -454,6 +454,8 @@ int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
 			     u32 value);
 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
+int zynqmp_mmio_read(const u32 address, u32 *value);
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
 
 /* Type of Config Object */
 #define PM_CONFIG_OBJECT_TYPE_BASE	0x1U
diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index acf75a8f07..3fd334a54d 100644
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * (C) Copyright 2015 Xilinx, Inc,
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
  */
 
 #ifndef _ZYNQMPPL_H_
diff --git a/lib/Kconfig b/lib/Kconfig
index c8b3ec1ec9..07e61de5b6 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -508,6 +508,7 @@ config SHA256
 
 config SHA512
 	bool "Enable SHA512 support"
+	default y if TI_SECURE_DEVICE && FIT_SIGNATURE
 	help
 	  This option enables support of hashing using SHA512 algorithm.
 	  The hash is calculated in software.
@@ -533,6 +534,17 @@ config SHA_HW_ACCEL
 
 if SPL
 
+config SPL_CRC32
+	bool "Enable CRC32 support in SPL"
+	default y if SPL_LEGACY_IMAGE_SUPPORT || SPL_EFI_PARTITION
+	default y if SPL_ENV_SUPPORT || TPL_BLOBLIST
+	help
+	  This option enables support of hashing using CRC32 algorithm.
+	  The CRC32 algorithm produces 32-bit checksum value. For FIT
+	  images, this is the least secure type of checksum, suitable for
+	  detected accidental image corruption. For secure applications you
+	  should consider SHA256 or SHA384.
+
 config SPL_SHA1
 	bool "Enable SHA1 support in SPL"
 	default y if SHA1
diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c
index 7c4189e243..a8d4b47000 100644
--- a/lib/acpi/acpi_table.c
+++ b/lib/acpi/acpi_table.c
@@ -11,8 +11,7 @@
 #include <log.h>
 #include <mapmem.h>
 #include <tables_csum.h>
-#include <timestamp.h>
-#include <version.h>
+#include <version_string.h>
 #include <acpi/acpi_table.h>
 #include <asm/global_data.h>
 #include <dm/acpi.h>
@@ -25,12 +24,12 @@
  * to have valid date. So for U-Boot version 2021.04 OEM_REVISION is set to
  * value 0x20210401.
  */
-#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \
-		      (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \
-		      (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \
-		      ((U_BOOT_VERSION_NUM % 10) << 16) | \
-		      (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \
-		      ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \
+#define OEM_REVISION ((((version_num / 1000) % 10) << 28) | \
+		      (((version_num / 100) % 10) << 24) | \
+		      (((version_num / 10) % 10) << 20) | \
+		      ((version_num % 10) << 16) | \
+		      (((version_num_patch / 10) % 10) << 12) | \
+		      ((version_num_patch % 10) << 8) | \
 		      0x01)
 
 int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags)
diff --git a/lib/ecdsa/ecdsa-libcrypto.c b/lib/ecdsa/ecdsa-libcrypto.c
index d5939af2c5..5fa9be10b4 100644
--- a/lib/ecdsa/ecdsa-libcrypto.c
+++ b/lib/ecdsa/ecdsa-libcrypto.c
@@ -111,16 +111,30 @@ static size_t ecdsa_key_size_bytes(const EC_KEY *key)
 	return EC_GROUP_order_bits(group) / 8;
 }
 
+static int default_password(char *buf, int size, int rwflag, void *u)
+{
+	strncpy(buf, (char *)u, size);
+	buf[size - 1] = '\0';
+	return strlen(buf);
+}
+
 static int read_key(struct signer *ctx, const char *key_name)
 {
 	FILE *f = fopen(key_name, "r");
+	const char *key_pass;
 
 	if (!f) {
 		fprintf(stderr, "Can not get key file '%s'\n", key_name);
 		return -ENOENT;
 	}
 
-	ctx->evp_key = PEM_read_PrivateKey(f, NULL, NULL, NULL);
+	key_pass = getenv("MKIMAGE_SIGN_PASSWORD");
+	if (key_pass) {
+		ctx->evp_key = PEM_read_PrivateKey(f, NULL, default_password, (void *)key_pass);
+
+	} else {
+		ctx->evp_key = PEM_read_PrivateKey(f, NULL, NULL, NULL);
+	}
 	fclose(f);
 	if (!ctx->evp_key) {
 		fprintf(stderr, "Can not read key from '%s'\n", key_name);
diff --git a/lib/efi_driver/efi_block_device.c b/lib/efi_driver/efi_block_device.c
index add00eeebb..e3abd90275 100644
--- a/lib/efi_driver/efi_block_device.c
+++ b/lib/efi_driver/efi_block_device.c
@@ -124,10 +124,8 @@ efi_bl_create_block_device(efi_handle_t handle, void *interface)
 	struct efi_block_io *io = interface;
 	struct efi_blk_plat *plat;
 
-	devnum = blk_find_max_devnum(UCLASS_EFI_LOADER);
-	if (devnum == -ENODEV)
-		devnum = 0;
-	else if (devnum < 0)
+	devnum = blk_next_free_devnum(UCLASS_EFI_LOADER);
+	if (devnum < 0)
 		return EFI_OUT_OF_RESOURCES;
 
 	name = calloc(1, 18); /* strlen("efiblk#2147483648") + 1 */
diff --git a/lib/efi_driver/efi_uclass.c b/lib/efi_driver/efi_uclass.c
index 45f9351988..66a45e156d 100644
--- a/lib/efi_driver/efi_uclass.c
+++ b/lib/efi_driver/efi_uclass.c
@@ -285,10 +285,8 @@ static efi_status_t efi_add_driver(struct driver *drv)
 	bp->ops = ops;
 
 	ret = efi_create_handle(&bp->bp.driver_binding_handle);
-	if (ret != EFI_SUCCESS) {
-		free(bp);
-		goto out;
-	}
+	if (ret != EFI_SUCCESS)
+		goto err;
 	bp->bp.image_handle = bp->bp.driver_binding_handle;
 	ret = efi_add_protocol(bp->bp.driver_binding_handle,
 			       &efi_guid_driver_binding_protocol, bp);
@@ -299,11 +297,11 @@ static efi_status_t efi_add_driver(struct driver *drv)
 		if (ret != EFI_SUCCESS)
 			goto err;
 	}
-out:
-	return ret;
 
+	return ret;
 err:
-	efi_delete_handle(bp->bp.driver_binding_handle);
+	if (bp->bp.driver_binding_handle)
+		efi_delete_handle(bp->bp.driver_binding_handle);
 	free(bp);
 	return ret;
 }
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index c5835e6ef6..9989e3f384 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -55,13 +55,50 @@ config EFI_VARIABLE_FILE_STORE
 	  stored as file /ubootefi.var on the EFI system partition.
 
 config EFI_MM_COMM_TEE
-	bool "UEFI variables storage service via OP-TEE"
+	bool "UEFI variables storage service via the trusted world"
 	depends on OPTEE
 	help
+	  Allowing access to the MM SP services (SPs such as  StandAlonneMM, smm-gateway).
+	  When using the u-boot OP-TEE driver, StandAlonneMM is supported.
+	  When using the u-boot FF-A  driver any MM SP is supported.
+
 	  If OP-TEE is present and running StandAloneMM, dispatch all UEFI
 	  variable related operations to that. The application will verify,
 	  authenticate and store the variables on an RPMB.
 
+	  When ARM_FFA_TRANSPORT is used, dispatch all UEFI variable related
+	  operations to the MM SP running in the secure world.
+	  A door bell mechanism is used to notify the SP when there is data in the shared
+	  MM buffer. The data is copied by u-boot to the shared buffer before issuing
+	  the door bell event.
+
+config FFA_SHARED_MM_BUF_SIZE
+	int "Memory size of the shared MM communication buffer"
+	depends on EFI_MM_COMM_TEE && ARM_FFA_TRANSPORT
+	help
+	  This defines the size in bytes of the memory area reserved for the shared
+	  buffer used for communication between the MM feature in U-Boot and
+	  the MM SP in secure world.
+	  The size of the memory region must be a multiple of the size of the maximum
+	  translation granule size that is specified in the ID_AA64MMFR0_EL1 System register.
+	  It is assumed that the MM SP knows the size of the shared MM communication buffer.
+
+config FFA_SHARED_MM_BUF_OFFSET
+	int "Data offset in the shared MM communication buffer"
+	depends on EFI_MM_COMM_TEE && ARM_FFA_TRANSPORT
+	help
+	  This defines the offset in bytes of the data read or written to in the shared
+	  buffer by the MM SP.
+
+config FFA_SHARED_MM_BUF_ADDR
+	hex "Define the address of the shared MM communication buffer"
+	depends on EFI_MM_COMM_TEE && ARM_FFA_TRANSPORT
+	help
+	  This defines the address of the shared MM communication buffer
+	  used for communication between the MM feature in U-Boot and
+	  the MM SP in secure world.
+	  It is assumed that the MM SP knows the address of the shared MM communication buffer.
+
 config EFI_VARIABLE_NO_STORE
 	bool "Don't persist non-volatile UEFI variables"
 	help
@@ -96,7 +133,8 @@ endif
 
 config EFI_VAR_BUF_SIZE
 	int "Memory size of the UEFI variable store"
-	default 16384
+	default 16384 if EFI_MM_COMM_TEE
+	default 65536
 	range 4096 2147483647
 	help
 	  This defines the size in bytes of the memory area reserved for keeping
@@ -106,7 +144,7 @@ config EFI_VAR_BUF_SIZE
 	  match the value of PcdFlashNvStorageVariableSize used to compile the
 	  StandAloneMM module.
 
-	  Minimum 4096, default 16384.
+	  Minimum 4096, default 65536, or 16384 when using StandAloneMM.
 
 config EFI_GET_TIME
 	bool "GetTime() runtime service"
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 13a35eae6c..1a8c8d7cab 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -23,6 +23,7 @@ CFLAGS_REMOVE_initrddump.o := $(CFLAGS_NON_EFI)
 
 ifdef CONFIG_RISCV
 always += boothart.efi
+targets += boothart.o
 endif
 
 ifneq ($(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
@@ -32,10 +33,12 @@ endif
 
 ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
 always += dtbdump.efi
+targets += dtbdump.o
 endif
 
 ifdef CONFIG_EFI_LOAD_FILE2_INITRD
 always += initrddump.efi
+targets += initrddump.o
 endif
 
 obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
diff --git a/lib/efi_loader/efi_acpi.c b/lib/efi_loader/efi_acpi.c
index 2ddc3502b5..f755af76f8 100644
--- a/lib/efi_loader/efi_acpi.c
+++ b/lib/efi_loader/efi_acpi.c
@@ -10,6 +10,9 @@
 #include <log.h>
 #include <mapmem.h>
 #include <acpi/acpi_table.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID;
 
@@ -20,26 +23,28 @@ static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID;
  */
 efi_status_t efi_acpi_register(void)
 {
-	/* Map within the low 32 bits, to allow for 32bit ACPI tables */
-	u64 acpi = U32_MAX;
+	ulong addr, start, end;
 	efi_status_t ret;
-	ulong addr;
 
-	/* Reserve 64kiB page for ACPI */
-	ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
-				 EFI_ACPI_RECLAIM_MEMORY, 16, &acpi);
+	/* Mark space used for tables */
+	start = ALIGN_DOWN(gd->arch.table_start, EFI_PAGE_MASK);
+	end = ALIGN(gd->arch.table_end, EFI_PAGE_MASK);
+	ret = efi_add_memory_map(start, end - start, EFI_ACPI_RECLAIM_MEMORY);
 	if (ret != EFI_SUCCESS)
 		return ret;
+	if (gd->arch.table_start_high) {
+		start = ALIGN_DOWN(gd->arch.table_start_high, EFI_PAGE_MASK);
+		end = ALIGN(gd->arch.table_end_high, EFI_PAGE_MASK);
+		ret = efi_add_memory_map(start, end - start,
+					 EFI_ACPI_RECLAIM_MEMORY);
+		if (ret != EFI_SUCCESS)
+			return ret;
+	}
 
-	/*
-	 * Generate ACPI tables - we know that efi_allocate_pages() returns
-	 * a 4k-aligned address, so it is safe to assume that
-	 * write_acpi_tables() will write the table at that address.
-	 */
-	addr = map_to_sysmem((void *)(ulong)acpi);
-	write_acpi_tables(addr);
+	addr = gd_acpi_start();
+	printf("EFI using ACPI tables at %lx\n", addr);
 
 	/* And expose them to our EFI payload */
 	return efi_install_configuration_table(&acpi_guid,
-					       (void *)(uintptr_t)acpi);
+					       (void *)(ulong)addr);
 }
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 7ac5f89f76..a40762c74c 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -344,3 +344,388 @@ efi_status_t efi_bootmgr_load(efi_handle_t *handle, void **load_options)
 error:
 	return ret;
 }
+
+/**
+ * efi_bootmgr_enumerate_boot_option() - enumerate the possible bootable media
+ *
+ * @opt:		pointer to the media boot option structure
+ * @volume_handles:	pointer to the efi handles
+ * @count:		number of efi handle
+ * Return:		status code
+ */
+static efi_status_t efi_bootmgr_enumerate_boot_option(struct eficonfig_media_boot_option *opt,
+						      efi_handle_t *volume_handles,
+						      efi_status_t count)
+{
+	u32 i;
+	struct efi_handler *handler;
+	efi_status_t ret = EFI_SUCCESS;
+
+	for (i = 0; i < count; i++) {
+		u16 *p;
+		u16 dev_name[BOOTMENU_DEVICE_NAME_MAX];
+		char *optional_data;
+		struct efi_load_option lo;
+		char buf[BOOTMENU_DEVICE_NAME_MAX];
+		struct efi_device_path *device_path;
+		struct efi_device_path *short_dp;
+
+		ret = efi_search_protocol(volume_handles[i], &efi_guid_device_path, &handler);
+		if (ret != EFI_SUCCESS)
+			continue;
+		ret = efi_protocol_open(handler, (void **)&device_path,
+					efi_root, NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+		if (ret != EFI_SUCCESS)
+			continue;
+
+		ret = efi_disk_get_device_name(volume_handles[i], buf, BOOTMENU_DEVICE_NAME_MAX);
+		if (ret != EFI_SUCCESS)
+			continue;
+
+		p = dev_name;
+		utf8_utf16_strncpy(&p, buf, strlen(buf));
+
+		/* prefer to short form device path */
+		short_dp = efi_dp_shorten(device_path);
+		if (short_dp)
+			device_path = short_dp;
+
+		lo.label = dev_name;
+		lo.attributes = LOAD_OPTION_ACTIVE;
+		lo.file_path = device_path;
+		lo.file_path_length = efi_dp_size(device_path) + sizeof(END);
+		/*
+		 * Set the dedicated guid to optional_data, it is used to identify
+		 * the boot option that automatically generated by the bootmenu.
+		 * efi_serialize_load_option() expects optional_data is null-terminated
+		 * utf8 string, so set the "1234567" string to allocate enough space
+		 * to store guid, instead of realloc the load_option.
+		 */
+		lo.optional_data = "1234567";
+		opt[i].size = efi_serialize_load_option(&lo, (u8 **)&opt[i].lo);
+		if (!opt[i].size) {
+			ret = EFI_OUT_OF_RESOURCES;
+			goto out;
+		}
+		/* set the guid */
+		optional_data = (char *)opt[i].lo + (opt[i].size - u16_strsize(u"1234567"));
+		memcpy(optional_data, &efi_guid_bootmenu_auto_generated, sizeof(efi_guid_t));
+	}
+
+out:
+	return ret;
+}
+
+/**
+ * efi_bootmgr_delete_invalid_boot_option() - delete non-existing boot option
+ *
+ * @opt:		pointer to the media boot option structure
+ * @count:		number of media boot option structure
+ * Return:		status code
+ */
+static efi_status_t efi_bootmgr_delete_invalid_boot_option(struct eficonfig_media_boot_option *opt,
+							   efi_status_t count)
+{
+	efi_uintn_t size;
+	void *load_option;
+	u32 i, list_size = 0;
+	struct efi_load_option lo;
+	u16 *var_name16 = NULL;
+	u16 varname[] = u"Boot####";
+	efi_status_t ret = EFI_SUCCESS;
+	u16 *delete_index_list = NULL, *p;
+	efi_uintn_t buf_size;
+
+	buf_size = 128;
+	var_name16 = malloc(buf_size);
+	if (!var_name16)
+		return EFI_OUT_OF_RESOURCES;
+
+	var_name16[0] = 0;
+	for (;;) {
+		int index;
+		efi_guid_t guid;
+		efi_uintn_t tmp;
+
+		ret = efi_next_variable_name(&buf_size, &var_name16, &guid);
+		if (ret == EFI_NOT_FOUND) {
+			/*
+			 * EFI_NOT_FOUND indicates we retrieved all EFI variables.
+			 * This should be treated as success.
+			 */
+			ret = EFI_SUCCESS;
+			break;
+		}
+
+		if (ret != EFI_SUCCESS)
+			goto out;
+
+		if (!efi_varname_is_load_option(var_name16, &index))
+			continue;
+
+		efi_create_indexed_name(varname, sizeof(varname), "Boot", index);
+		load_option = efi_get_var(varname, &efi_global_variable_guid, &size);
+		if (!load_option)
+			continue;
+
+		tmp = size;
+		ret = efi_deserialize_load_option(&lo, load_option, &size);
+		if (ret != EFI_SUCCESS)
+			goto next;
+
+		if (size >= sizeof(efi_guid_bootmenu_auto_generated) &&
+		    !guidcmp(lo.optional_data, &efi_guid_bootmenu_auto_generated)) {
+			for (i = 0; i < count; i++) {
+				if (opt[i].size == tmp &&
+				    memcmp(opt[i].lo, load_option, tmp) == 0) {
+					opt[i].exist = true;
+					break;
+				}
+			}
+
+			/*
+			 * The entire list of variables must be retrieved by
+			 * efi_get_next_variable_name_int() before deleting the invalid
+			 * boot option, just save the index here.
+			 */
+			if (i == count) {
+				p = realloc(delete_index_list, sizeof(u32) *
+					    (list_size + 1));
+				if (!p) {
+					ret = EFI_OUT_OF_RESOURCES;
+					goto out;
+				}
+				delete_index_list = p;
+				delete_index_list[list_size++] = index;
+			}
+		}
+next:
+		free(load_option);
+	}
+
+	/* delete all invalid boot options */
+	for (i = 0; i < list_size; i++) {
+		ret = efi_bootmgr_delete_boot_option(delete_index_list[i]);
+		if (ret != EFI_SUCCESS)
+			goto out;
+	}
+
+out:
+	free(var_name16);
+	free(delete_index_list);
+
+	return ret;
+}
+
+/**
+ * efi_bootmgr_get_unused_bootoption() - get unused "Boot####" index
+ *
+ * @buf:	pointer to the buffer to store boot option variable name
+ * @buf_size:	buffer size
+ * @index:	pointer to store the index in the BootOrder variable
+ * Return:	status code
+ */
+efi_status_t efi_bootmgr_get_unused_bootoption(u16 *buf, efi_uintn_t buf_size,
+					       unsigned int *index)
+{
+	u32 i;
+	efi_status_t ret;
+	efi_uintn_t size;
+
+	if (buf_size < u16_strsize(u"Boot####"))
+		return EFI_BUFFER_TOO_SMALL;
+
+	for (i = 0; i <= 0xFFFF; i++) {
+		size = 0;
+		efi_create_indexed_name(buf, buf_size, "Boot", i);
+		ret = efi_get_variable_int(buf, &efi_global_variable_guid,
+					   NULL, &size, NULL, NULL);
+		if (ret == EFI_BUFFER_TOO_SMALL)
+			continue;
+		else
+			break;
+	}
+
+	if (i > 0xFFFF)
+		return EFI_OUT_OF_RESOURCES;
+
+	*index = i;
+
+	return EFI_SUCCESS;
+}
+
+/**
+ * efi_bootmgr_append_bootorder() - append new boot option in BootOrder variable
+ *
+ * @index:	"Boot####" index to append to BootOrder variable
+ * Return:	status code
+ */
+efi_status_t efi_bootmgr_append_bootorder(u16 index)
+{
+	u16 *bootorder;
+	efi_status_t ret;
+	u16 *new_bootorder = NULL;
+	efi_uintn_t last, size, new_size;
+
+	/* append new boot option */
+	bootorder = efi_get_var(u"BootOrder", &efi_global_variable_guid, &size);
+	last = size / sizeof(u16);
+	new_size = size + sizeof(u16);
+	new_bootorder = calloc(1, new_size);
+	if (!new_bootorder) {
+		ret = EFI_OUT_OF_RESOURCES;
+		goto out;
+	}
+	memcpy(new_bootorder, bootorder, size);
+	new_bootorder[last] = index;
+
+	ret = efi_set_variable_int(u"BootOrder", &efi_global_variable_guid,
+				   EFI_VARIABLE_NON_VOLATILE |
+				   EFI_VARIABLE_BOOTSERVICE_ACCESS |
+				   EFI_VARIABLE_RUNTIME_ACCESS,
+				   new_size, new_bootorder, false);
+	if (ret != EFI_SUCCESS)
+		goto out;
+
+out:
+	free(bootorder);
+	free(new_bootorder);
+
+	return ret;
+}
+
+/**
+ * efi_bootmgr_delete_boot_option() - delete selected boot option
+ *
+ * @boot_index:	boot option index to delete
+ * Return:	status code
+ */
+efi_status_t efi_bootmgr_delete_boot_option(u16 boot_index)
+{
+	u16 *bootorder;
+	u16 varname[9];
+	efi_status_t ret;
+	unsigned int index;
+	efi_uintn_t num, size;
+
+	efi_create_indexed_name(varname, sizeof(varname),
+				"Boot", boot_index);
+	ret = efi_set_variable_int(varname, &efi_global_variable_guid,
+				   0, 0, NULL, false);
+	if (ret != EFI_SUCCESS) {
+		log_err("delete boot option(%ls) failed\n", varname);
+		return ret;
+	}
+
+	/* update BootOrder if necessary */
+	bootorder = efi_get_var(u"BootOrder", &efi_global_variable_guid, &size);
+	if (!bootorder)
+		return EFI_SUCCESS;
+
+	num = size / sizeof(u16);
+	if (!efi_search_bootorder(bootorder, num, boot_index, &index))
+		return EFI_SUCCESS;
+
+	memmove(&bootorder[index], &bootorder[index + 1],
+		(num - index - 1) * sizeof(u16));
+	size -= sizeof(u16);
+	ret = efi_set_variable_int(u"BootOrder", &efi_global_variable_guid,
+				   EFI_VARIABLE_NON_VOLATILE |
+				   EFI_VARIABLE_BOOTSERVICE_ACCESS |
+				   EFI_VARIABLE_RUNTIME_ACCESS,
+				   size, bootorder, false);
+
+	return ret;
+}
+
+/**
+ * efi_bootmgr_update_media_device_boot_option() - generate the media device boot option
+ *
+ * This function enumerates all devices supporting EFI_SIMPLE_FILE_SYSTEM_PROTOCOL
+ * and generate the bootmenu entries.
+ * This function also provide the BOOT#### variable maintenance for
+ * the media device entries.
+ * - Automatically create the BOOT#### variable for the newly detected device,
+ * this BOOT#### variable is distinguished by the special GUID
+ * stored in the EFI_LOAD_OPTION.optional_data
+ * - If the device is not attached to the system, the associated BOOT#### variable
+ * is automatically deleted.
+ *
+ * Return:	status code
+ */
+efi_status_t efi_bootmgr_update_media_device_boot_option(void)
+{
+	u32 i;
+	efi_status_t ret;
+	efi_uintn_t count;
+	efi_handle_t *volume_handles = NULL;
+	struct eficonfig_media_boot_option *opt = NULL;
+
+	ret = efi_locate_handle_buffer_int(BY_PROTOCOL,
+					   &efi_simple_file_system_protocol_guid,
+					   NULL, &count,
+					   (efi_handle_t **)&volume_handles);
+	if (ret != EFI_SUCCESS)
+		goto out;
+
+	opt = calloc(count, sizeof(struct eficonfig_media_boot_option));
+	if (!opt) {
+		ret = EFI_OUT_OF_RESOURCES;
+		goto out;
+	}
+
+	/* enumerate all devices supporting EFI_SIMPLE_FILE_SYSTEM_PROTOCOL */
+	ret = efi_bootmgr_enumerate_boot_option(opt, volume_handles, count);
+	if (ret != EFI_SUCCESS)
+		goto out;
+
+	/*
+	 * System hardware configuration may vary depending on the user setup.
+	 * The boot option is automatically added by the bootmenu.
+	 * If the device is not attached to the system, the boot option needs
+	 * to be deleted.
+	 */
+	ret = efi_bootmgr_delete_invalid_boot_option(opt, count);
+	if (ret != EFI_SUCCESS)
+		goto out;
+
+	/* add non-existent boot option */
+	for (i = 0; i < count; i++) {
+		u32 boot_index;
+		u16 var_name[9];
+
+		if (!opt[i].exist) {
+			ret = efi_bootmgr_get_unused_bootoption(var_name, sizeof(var_name),
+								&boot_index);
+			if (ret != EFI_SUCCESS)
+				goto out;
+
+			ret = efi_set_variable_int(var_name, &efi_global_variable_guid,
+						   EFI_VARIABLE_NON_VOLATILE |
+						   EFI_VARIABLE_BOOTSERVICE_ACCESS |
+						   EFI_VARIABLE_RUNTIME_ACCESS,
+						   opt[i].size, opt[i].lo, false);
+			if (ret != EFI_SUCCESS)
+				goto out;
+
+			ret = efi_bootmgr_append_bootorder(boot_index);
+			if (ret != EFI_SUCCESS) {
+				efi_set_variable_int(var_name, &efi_global_variable_guid,
+						     0, 0, NULL, false);
+				goto out;
+			}
+		}
+	}
+
+out:
+	if (opt) {
+		for (i = 0; i < count; i++)
+			free(opt[i].lo);
+	}
+	free(opt);
+	efi_free_pool(volume_handles);
+
+	if (ret == EFI_NOT_FOUND)
+		return EFI_SUCCESS;
+	return ret;
+}
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index d5065f296a..0e89c8505b 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -59,6 +59,10 @@ static efi_handle_t current_image;
 static volatile gd_t *efi_gd, *app_gd;
 #endif
 
+static efi_status_t efi_uninstall_protocol
+			(efi_handle_t handle, const efi_guid_t *protocol,
+			 void *protocol_interface);
+
 /* 1 if inside U-Boot code, 0 if inside EFI payload code */
 static int entry_count = 1;
 static int nesting_level;
@@ -97,6 +101,12 @@ static efi_status_t EFIAPI efi_disconnect_controller(
 					efi_handle_t driver_image_handle,
 					efi_handle_t child_handle);
 
+static
+efi_status_t EFIAPI efi_connect_controller(efi_handle_t controller_handle,
+					   efi_handle_t *driver_image_handle,
+					   struct efi_device_path *remain_device_path,
+					   bool recursive);
+
 /* Called on every callback entry */
 int __efi_entry_check(void)
 {
@@ -569,9 +579,9 @@ efi_status_t efi_search_protocol(const efi_handle_t handle,
  *
  * Return: status code
  */
-efi_status_t efi_remove_protocol(const efi_handle_t handle,
-				 const efi_guid_t *protocol,
-				 void *protocol_interface)
+static efi_status_t efi_remove_protocol(const efi_handle_t handle,
+					const efi_guid_t *protocol,
+					void *protocol_interface)
 {
 	struct efi_handler *handler;
 	efi_status_t ret;
@@ -604,8 +614,8 @@ static efi_status_t efi_remove_all_protocols(const efi_handle_t handle)
 	list_for_each_entry_safe(protocol, pos, &efiobj->protocols, link) {
 		efi_status_t ret;
 
-		ret = efi_remove_protocol(handle, &protocol->guid,
-					  protocol->protocol_interface);
+		ret = efi_uninstall_protocol(handle, &protocol->guid,
+					     protocol->protocol_interface);
 		if (ret != EFI_SUCCESS)
 			return ret;
 	}
@@ -616,19 +626,23 @@ static efi_status_t efi_remove_all_protocols(const efi_handle_t handle)
  * efi_delete_handle() - delete handle
  *
  * @handle: handle to delete
+ *
+ * Return: status code
  */
-void efi_delete_handle(efi_handle_t handle)
+efi_status_t efi_delete_handle(efi_handle_t handle)
 {
 	efi_status_t ret;
 
 	ret = efi_remove_all_protocols(handle);
-	if (ret == EFI_INVALID_PARAMETER) {
-		log_err("Can't remove invalid handle %p\n", handle);
-		return;
+	if (ret != EFI_SUCCESS) {
+		log_err("Handle %p has protocols installed. Unable to delete\n", handle);
+		return ret;
 	}
 
 	list_del(&handle->link);
 	free(handle);
+
+	return ret;
 }
 
 /**
@@ -1298,7 +1312,7 @@ static efi_status_t efi_disconnect_all_drivers
 				 const efi_guid_t *protocol,
 				 efi_handle_t child_handle)
 {
-	efi_uintn_t number_of_drivers;
+	efi_uintn_t number_of_drivers, tmp;
 	efi_handle_t *driver_handle_buffer;
 	efi_status_t r, ret;
 
@@ -1308,15 +1322,30 @@ static efi_status_t efi_disconnect_all_drivers
 		return ret;
 	if (!number_of_drivers)
 		return EFI_SUCCESS;
-	ret = EFI_NOT_FOUND;
+
+	tmp = number_of_drivers;
 	while (number_of_drivers) {
-		r = EFI_CALL(efi_disconnect_controller(
+		ret = EFI_CALL(efi_disconnect_controller(
 				handle,
 				driver_handle_buffer[--number_of_drivers],
 				child_handle));
-		if (r == EFI_SUCCESS)
-			ret = r;
+		if (ret != EFI_SUCCESS)
+			goto reconnect;
 	}
+
+	free(driver_handle_buffer);
+	return ret;
+
+reconnect:
+	/* Reconnect all disconnected drivers */
+	for (; number_of_drivers < tmp; number_of_drivers++) {
+		r = EFI_CALL(efi_connect_controller(handle,
+						    &driver_handle_buffer[number_of_drivers],
+						    NULL, true));
+		if (r != EFI_SUCCESS)
+			EFI_PRINT("Failed to reconnect controller\n");
+	}
+
 	free(driver_handle_buffer);
 	return ret;
 }
@@ -1336,34 +1365,35 @@ static efi_status_t efi_uninstall_protocol
 			(efi_handle_t handle, const efi_guid_t *protocol,
 			 void *protocol_interface)
 {
-	struct efi_object *efiobj;
 	struct efi_handler *handler;
 	struct efi_open_protocol_info_item *item;
 	struct efi_open_protocol_info_item *pos;
 	efi_status_t r;
 
-	/* Check handle */
-	efiobj = efi_search_obj(handle);
-	if (!efiobj) {
-		r = EFI_INVALID_PARAMETER;
-		goto out;
-	}
 	/* Find the protocol on the handle */
 	r = efi_search_protocol(handle, protocol, &handler);
 	if (r != EFI_SUCCESS)
 		goto out;
+	if (handler->protocol_interface != protocol_interface)
+		return EFI_NOT_FOUND;
 	/* Disconnect controllers */
-	efi_disconnect_all_drivers(efiobj, protocol, NULL);
+	r = efi_disconnect_all_drivers(handle, protocol, NULL);
+	if (r != EFI_SUCCESS) {
+		r = EFI_ACCESS_DENIED;
+		goto out;
+	}
 	/* Close protocol */
 	list_for_each_entry_safe(item, pos, &handler->open_infos, link) {
 		if (item->info.attributes ==
 			EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL ||
 		    item->info.attributes == EFI_OPEN_PROTOCOL_GET_PROTOCOL ||
 		    item->info.attributes == EFI_OPEN_PROTOCOL_TEST_PROTOCOL)
-			list_del(&item->link);
+			efi_delete_open_info(item);
 	}
+	/* if agents didn't close the protocols properly */
 	if (!list_empty(&handler->open_infos)) {
 		r =  EFI_ACCESS_DENIED;
+		EFI_CALL(efi_connect_controller(handle, NULL, NULL, true));
 		goto out;
 	}
 	r = efi_remove_protocol(handle, protocol, protocol_interface);
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 7a6f195cbc..af8a2ee940 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -368,9 +368,8 @@ efi_status_t efi_capsule_authenticate(const void *capsule, efi_uintn_t capsule_s
 					     auth_hdr->auth_info.hdr.dwLength
 					     - sizeof(auth_hdr->auth_info),
 					     &buf);
-	if (IS_ERR(capsule_sig)) {
+	if (!capsule_sig) {
 		debug("Parsing variable's pkcs7 header failed\n");
-		capsule_sig = NULL;
 		goto out;
 	}
 
@@ -581,6 +580,13 @@ static efi_status_t efi_capsule_update_firmware(
 		fw_accept_os = capsule_data->flags & FW_ACCEPT_OS ? 0x1 : 0x0;
 	}
 
+	if (guidcmp(&capsule_data->capsule_guid,
+		    &efi_guid_firmware_management_capsule_id)) {
+		log_err("Unsupported capsule type: %pUs\n",
+			&capsule_data->capsule_guid);
+		return EFI_UNSUPPORTED;
+	}
+
 	/* sanity check */
 	if (capsule_data->header_size < sizeof(*capsule) ||
 	    capsule_data->header_size >= capsule_data->capsule_image_size)
@@ -751,15 +757,7 @@ efi_status_t EFIAPI efi_update_capsule(
 
 		log_debug("Capsule[%d] (guid:%pUs)\n",
 			  i, &capsule->capsule_guid);
-		if (!guidcmp(&capsule->capsule_guid,
-			     &efi_guid_firmware_management_capsule_id)) {
-			ret  = efi_capsule_update_firmware(capsule);
-		} else {
-			log_err("Unsupported capsule type: %pUs\n",
-				&capsule->capsule_guid);
-			ret = EFI_UNSUPPORTED;
-		}
-
+		ret  = efi_capsule_update_firmware(capsule);
 		if (ret != EFI_SUCCESS)
 			goto out;
 	}
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 04ebb449ca..ed7214f3a3 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -10,6 +10,7 @@
 #include <common.h>
 #include <blk.h>
 #include <dm.h>
+#include <dm/root.h>
 #include <log.h>
 #include <net.h>
 #include <usb.h>
@@ -21,16 +22,6 @@
 #include <asm-generic/unaligned.h>
 #include <linux/compat.h> /* U16_MAX */
 
-#ifdef CONFIG_BLKMAP
-const efi_guid_t efi_guid_blkmap_dev = U_BOOT_BLKMAP_DEV_GUID;
-#endif
-#ifdef CONFIG_SANDBOX
-const efi_guid_t efi_guid_host_dev = U_BOOT_HOST_DEV_GUID;
-#endif
-#ifdef CONFIG_VIRTIO_BLK
-const efi_guid_t efi_guid_virtio_dev = U_BOOT_VIRTIO_DEV_GUID;
-#endif
-
 /* template END node: */
 const struct efi_device_path END = {
 	.type     = DEVICE_PATH_TYPE_END,
@@ -38,16 +29,6 @@ const struct efi_device_path END = {
 	.length   = sizeof(END),
 };
 
-/* template ROOT node: */
-static const struct efi_device_path_vendor ROOT = {
-	.dp = {
-		.type     = DEVICE_PATH_TYPE_HARDWARE_DEVICE,
-		.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR,
-		.length   = sizeof(ROOT),
-	},
-	.guid = U_BOOT_GUID,
-};
-
 #if defined(CONFIG_MMC)
 /*
  * Determine if an MMC device is an SD card.
@@ -497,13 +478,12 @@ bool efi_dp_is_multi_instance(const struct efi_device_path *dp)
 __maybe_unused static unsigned int dp_size(struct udevice *dev)
 {
 	if (!dev || !dev->driver)
-		return sizeof(ROOT);
+		return sizeof(struct efi_device_path_udevice);
 
 	switch (device_get_uclass_id(dev)) {
 	case UCLASS_ROOT:
-	case UCLASS_SIMPLE_BUS:
 		/* stop traversing parents at this point: */
-		return sizeof(ROOT);
+		return sizeof(struct efi_device_path_udevice);
 	case UCLASS_ETH:
 		return dp_size(dev->parent) +
 			sizeof(struct efi_device_path_mac_addr);
@@ -534,43 +514,15 @@ __maybe_unused static unsigned int dp_size(struct udevice *dev)
 			return dp_size(dev->parent) +
 				sizeof(struct efi_device_path_nvme);
 #endif
-#ifdef CONFIG_SANDBOX
-		case UCLASS_HOST:
-			 /*
-			  * Sandbox's host device will be represented
-			  * as vendor device with extra one byte for
-			  * device number
-			  */
-			return dp_size(dev->parent)
-				+ sizeof(struct efi_device_path_vendor) + 1;
-#endif
 #ifdef CONFIG_USB
 		case UCLASS_MASS_STORAGE:
 			return dp_size(dev->parent)
 				+ sizeof(struct efi_device_path_controller);
 #endif
-#ifdef CONFIG_VIRTIO_BLK
-		case UCLASS_VIRTIO:
-			 /*
-			  * Virtio devices will be represented as a vendor
-			  * device node with an extra byte for the device
-			  * number.
-			  */
-			return dp_size(dev->parent)
-				+ sizeof(struct efi_device_path_vendor) + 1;
-#endif
-#ifdef CONFIG_BLKMAP
-		case UCLASS_BLKMAP:
-			 /*
-			  * blkmap devices will be represented as a vendor
-			  * device node with an extra byte for the device
-			  * number.
-			  */
-			return dp_size(dev->parent)
-				+ sizeof(struct efi_device_path_vendor) + 1;
-#endif
 		default:
-			return dp_size(dev->parent);
+			/* UCLASS_BLKMAP, UCLASS_HOST, UCLASS_VIRTIO */
+			return dp_size(dev->parent) +
+				sizeof(struct efi_device_path_udevice);
 		}
 #if defined(CONFIG_MMC)
 	case UCLASS_MMC:
@@ -582,8 +534,8 @@ __maybe_unused static unsigned int dp_size(struct udevice *dev)
 		return dp_size(dev->parent) +
 			sizeof(struct efi_device_path_usb);
 	default:
-		/* just skip over unknown classes: */
-		return dp_size(dev->parent);
+		return dp_size(dev->parent) +
+			sizeof(struct efi_device_path_udevice);
 	}
 }
 
@@ -596,21 +548,19 @@ __maybe_unused static unsigned int dp_size(struct udevice *dev)
  */
 __maybe_unused static void *dp_fill(void *buf, struct udevice *dev)
 {
+	enum uclass_id uclass_id;
+
 	if (!dev || !dev->driver)
 		return buf;
 
-	switch (device_get_uclass_id(dev)) {
-	case UCLASS_ROOT:
-	case UCLASS_SIMPLE_BUS: {
-		/* stop traversing parents at this point: */
-		struct efi_device_path_vendor *vdp = buf;
-		*vdp = ROOT;
-		return &vdp[1];
-	}
+	uclass_id = device_get_uclass_id(dev);
+	if (uclass_id != UCLASS_ROOT)
+		buf = dp_fill(buf, dev->parent);
+
+	switch (uclass_id) {
 #ifdef CONFIG_NETDEVICES
 	case UCLASS_ETH: {
-		struct efi_device_path_mac_addr *dp =
-			dp_fill(buf, dev->parent);
+		struct efi_device_path_mac_addr *dp = buf;
 		struct eth_pdata *pdata = dev_get_plat(dev);
 
 		dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
@@ -625,63 +575,10 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev)
 	}
 #endif
 	case UCLASS_BLK:
-		switch (dev->parent->uclass->uc_drv->id) {
-#ifdef CONFIG_BLKMAP
-		case UCLASS_BLKMAP: {
-			struct efi_device_path_vendor *dp;
-			struct blk_desc *desc = dev_get_uclass_plat(dev);
-
-			dp_fill(buf, dev->parent);
-			dp = buf;
-			++dp;
-			dp->dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
-			dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR;
-			dp->dp.length = sizeof(*dp) + 1;
-			memcpy(&dp->guid, &efi_guid_blkmap_dev,
-			       sizeof(efi_guid_t));
-			dp->vendor_data[0] = desc->devnum;
-			return &dp->vendor_data[1];
-			}
-#endif
-#ifdef CONFIG_SANDBOX
-		case UCLASS_HOST: {
-			/* stop traversing parents at this point: */
-			struct efi_device_path_vendor *dp;
-			struct blk_desc *desc = dev_get_uclass_plat(dev);
-
-			dp_fill(buf, dev->parent);
-			dp = buf;
-			++dp;
-			dp->dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
-			dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR;
-			dp->dp.length = sizeof(*dp) + 1;
-			memcpy(&dp->guid, &efi_guid_host_dev,
-			       sizeof(efi_guid_t));
-			dp->vendor_data[0] = desc->devnum;
-			return &dp->vendor_data[1];
-			}
-#endif
-#ifdef CONFIG_VIRTIO_BLK
-		case UCLASS_VIRTIO: {
-			struct efi_device_path_vendor *dp;
-			struct blk_desc *desc = dev_get_uclass_plat(dev);
-
-			dp_fill(buf, dev->parent);
-			dp = buf;
-			++dp;
-			dp->dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
-			dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR;
-			dp->dp.length = sizeof(*dp) + 1;
-			memcpy(&dp->guid, &efi_guid_virtio_dev,
-			       sizeof(efi_guid_t));
-			dp->vendor_data[0] = desc->devnum;
-			return &dp->vendor_data[1];
-			}
-#endif
+		switch (device_get_uclass_id(dev->parent)) {
 #ifdef CONFIG_IDE
 		case UCLASS_IDE: {
-			struct efi_device_path_atapi *dp =
-			dp_fill(buf, dev->parent);
+			struct efi_device_path_atapi *dp = buf;
 			struct blk_desc *desc = dev_get_uclass_plat(dev);
 
 			dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
@@ -697,8 +594,7 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev)
 #endif
 #if defined(CONFIG_SCSI)
 		case UCLASS_SCSI: {
-			struct efi_device_path_scsi *dp =
-				dp_fill(buf, dev->parent);
+			struct efi_device_path_scsi *dp = buf;
 			struct blk_desc *desc = dev_get_uclass_plat(dev);
 
 			dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
@@ -711,8 +607,7 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev)
 #endif
 #if defined(CONFIG_MMC)
 		case UCLASS_MMC: {
-			struct efi_device_path_sd_mmc_path *sddp =
-				dp_fill(buf, dev->parent);
+			struct efi_device_path_sd_mmc_path *sddp = buf;
 			struct blk_desc *desc = dev_get_uclass_plat(dev);
 
 			sddp->dp.type     = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
@@ -726,8 +621,7 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev)
 #endif
 #if defined(CONFIG_AHCI) || defined(CONFIG_SATA)
 		case UCLASS_AHCI: {
-			struct efi_device_path_sata *dp =
-				dp_fill(buf, dev->parent);
+			struct efi_device_path_sata *dp = buf;
 			struct blk_desc *desc = dev_get_uclass_plat(dev);
 
 			dp->dp.type     = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
@@ -742,8 +636,7 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev)
 #endif
 #if defined(CONFIG_NVME)
 		case UCLASS_NVME: {
-			struct efi_device_path_nvme *dp =
-				dp_fill(buf, dev->parent);
+			struct efi_device_path_nvme *dp = buf;
 			u32 ns_id;
 
 			dp->dp.type     = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
@@ -757,8 +650,7 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev)
 #if defined(CONFIG_USB)
 		case UCLASS_MASS_STORAGE: {
 			struct blk_desc *desc = dev_get_uclass_plat(dev);
-			struct efi_device_path_controller *dp =
-				dp_fill(buf, dev->parent);
+			struct efi_device_path_controller *dp = buf;
 
 			dp->dp.type	= DEVICE_PATH_TYPE_HARDWARE_DEVICE;
 			dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_CONTROLLER;
@@ -767,16 +659,26 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev)
 			return &dp[1];
 		}
 #endif
-		default:
-			debug("%s(%u) %s: unhandled parent class: %s (%u)\n",
-			      __FILE__, __LINE__, __func__,
-			      dev->name, dev->parent->uclass->uc_drv->id);
-			return dp_fill(buf, dev->parent);
+		default: {
+			/* UCLASS_BLKMAP, UCLASS_HOST, UCLASS_VIRTIO */
+			struct efi_device_path_udevice *dp = buf;
+			struct blk_desc *desc = dev_get_uclass_plat(dev);
+
+			dp->dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
+			dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR;
+			dp->dp.length = sizeof(*dp);
+			memcpy(&dp->guid, &efi_u_boot_guid,
+			       sizeof(efi_guid_t));
+			dp->uclass_id = (UCLASS_BLK & 0xffff) |
+					(desc->uclass_id << 16);
+			dp->dev_number = desc->devnum;
+
+			return &dp[1];
 		}
+	}
 #if defined(CONFIG_MMC)
 	case UCLASS_MMC: {
-		struct efi_device_path_sd_mmc_path *sddp =
-			dp_fill(buf, dev->parent);
+		struct efi_device_path_sd_mmc_path *sddp = buf;
 		struct mmc *mmc = mmc_get_mmc_dev(dev);
 		struct blk_desc *desc = mmc_get_blk_desc(mmc);
 
@@ -792,7 +694,7 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev)
 #endif
 	case UCLASS_MASS_STORAGE:
 	case UCLASS_USB_HUB: {
-		struct efi_device_path_usb *udp = dp_fill(buf, dev->parent);
+		struct efi_device_path_usb *udp = buf;
 
 		switch (device_get_uclass_id(dev->parent)) {
 		case UCLASS_USB_HUB: {
@@ -811,11 +713,18 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev)
 
 		return &udp[1];
 	}
-	default:
-		/* If the uclass driver is missing, this will show NULL */
-		log_debug("unhandled device class: %s (%s)\n", dev->name,
-			  dev_get_uclass_name(dev));
-		return dp_fill(buf, dev->parent);
+	default: {
+		struct efi_device_path_udevice *vdp = buf;
+
+		vdp->dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
+		vdp->dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR;
+		vdp->dp.length = sizeof(*vdp);
+		memcpy(&vdp->guid, &efi_u_boot_guid, sizeof(efi_guid_t));
+		vdp->uclass_id = uclass_id;
+		vdp->dev_number = dev->seq_;
+
+		return &vdp[1];
+	    }
 	}
 }
 
@@ -1052,14 +961,12 @@ struct efi_device_path *efi_dp_from_uart(void)
 {
 	void *buf, *pos;
 	struct efi_device_path_uart *uart;
-	size_t dpsize = sizeof(ROOT) + sizeof(*uart) + sizeof(END);
+	size_t dpsize = dp_size(dm_root()) + sizeof(*uart) + sizeof(END);
 
 	buf = efi_alloc(dpsize);
 	if (!buf)
 		return NULL;
-	pos = buf;
-	memcpy(pos, &ROOT, sizeof(ROOT));
-	pos += sizeof(ROOT);
+	pos = dp_fill(buf, dm_root());
 	uart = pos;
 	uart->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
 	uart->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_UART;
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 28c8cdf710..f0d76113b0 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -487,15 +487,16 @@ static efi_status_t efi_disk_add_dev(
 	 */
 	if ((part || desc->part_type == PART_TYPE_UNKNOWN) &&
 	    efi_fs_exists(desc, part)) {
-		diskobj->volume = efi_simple_file_system(desc, part,
-							 diskobj->dp);
+		ret = efi_create_simple_file_system(desc, part, diskobj->dp,
+						    &diskobj->volume);
+		if (ret != EFI_SUCCESS)
+			goto error;
+
 		ret = efi_add_protocol(&diskobj->header,
 				       &efi_simple_file_system_protocol_guid,
 				       diskobj->volume);
-		if (ret != EFI_SUCCESS) {
-			log_debug("simple FS failed\n");
-			return ret;
-		}
+		if (ret != EFI_SUCCESS)
+			goto error;
 	}
 	diskobj->ops = block_io_disk_template;
 	diskobj->dev_index = dev_index;
@@ -538,6 +539,8 @@ static efi_status_t efi_disk_add_dev(
 	return EFI_SUCCESS;
 error:
 	efi_delete_handle(&diskobj->header);
+	free(diskobj->volume);
+	free(diskobj);
 	return ret;
 }
 
@@ -708,6 +711,7 @@ int efi_disk_remove(void *ctx, struct event *event)
 	efi_handle_t handle;
 	struct blk_desc *desc;
 	struct efi_disk_obj *diskobj = NULL;
+	efi_status_t ret;
 
 	if (dev_tag_get_ptr(dev, DM_TAG_EFI, (void **)&handle))
 		return 0;
@@ -727,10 +731,14 @@ int efi_disk_remove(void *ctx, struct event *event)
 		return 0;
 	}
 
+	ret = efi_delete_handle(handle);
+	/* Do not delete DM device if there are still EFI drivers attached. */
+	if (ret != EFI_SUCCESS)
+		return -1;
+
 	if (diskobj)
 		efi_free_pool(diskobj->dp);
 
-	efi_delete_handle(handle);
 	dev_tag_del(dev, DM_TAG_EFI);
 
 	return 0;
diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
index 520c730220..3c56cebf96 100644
--- a/lib/efi_loader/efi_file.c
+++ b/lib/efi_loader/efi_file.c
@@ -195,6 +195,8 @@ static struct efi_file_handle *file_open(struct file_system *fs,
 
 	/* +2 is for null and '/' */
 	fh = calloc(1, sizeof(*fh) + plen + (flen * MAX_UTF8_PER_UTF16) + 2);
+	if (!fh)
+		return NULL;
 
 	fh->open_mode = open_mode;
 	fh->base = efi_file_handle_protocol;
@@ -1192,18 +1194,22 @@ efi_open_volume(struct efi_simple_file_system_protocol *this,
 	return EFI_EXIT(efi_open_volume_int(this, root));
 }
 
-struct efi_simple_file_system_protocol *
-efi_simple_file_system(struct blk_desc *desc, int part,
-		       struct efi_device_path *dp)
+efi_status_t
+efi_create_simple_file_system(struct blk_desc *desc, int part,
+			      struct efi_device_path *dp,
+			      struct efi_simple_file_system_protocol **fsp)
 {
 	struct file_system *fs;
 
 	fs = calloc(1, sizeof(*fs));
+	if (!fs)
+		return EFI_OUT_OF_RESOURCES;
 	fs->base.rev = EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION;
 	fs->base.open_volume = efi_open_volume;
 	fs->desc = desc;
 	fs->part = part;
 	fs->dp = dp;
+	*fsp = &fs->base;
 
-	return &fs->base;
+	return EFI_SUCCESS;
 }
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index 93e2b01c07..9abb29f1df 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -10,6 +10,7 @@
 #include <charset.h>
 #include <dfu.h>
 #include <efi_loader.h>
+#include <efi_variable.h>
 #include <fwu.h>
 #include <image.h>
 #include <signatures.h>
@@ -36,11 +37,52 @@ struct fmp_payload_header {
 	u32 lowest_supported_version;
 };
 
+/**
+ * struct fmp_state - fmp firmware update state
+ *
+ * This structure describes the state of the firmware update
+ * through FMP protocol.
+ *
+ * @fw_version:			Firmware versions used
+ * @lowest_supported_version:	Lowest supported version
+ * @last_attempt_version:	Last attempt version
+ * @last_attempt_status:	Last attempt status
+ */
+struct fmp_state {
+	u32 fw_version;
+	u32 lowest_supported_version; /* not used */
+	u32 last_attempt_version; /* not used */
+	u32 last_attempt_status; /* not used */
+};
+
 __weak void set_dfu_alt_info(char *interface, char *devstr)
 {
 	env_set("dfu_alt_info", update_info.dfu_string);
 }
 
+/**
+ * efi_firmware_get_image_type_id - get image_type_id
+ * @image_index:	image index
+ *
+ * Return the image_type_id identified by the image index.
+ *
+ * Return:		pointer to the image_type_id, NULL if image_index is invalid
+ */
+static
+efi_guid_t *efi_firmware_get_image_type_id(u8 image_index)
+{
+	int i;
+	struct efi_fw_image *fw_array;
+
+	fw_array = update_info.images;
+	for (i = 0; i < update_info.num_images; i++) {
+		if (fw_array[i].image_index == image_index)
+			return &fw_array[i].image_type_id;
+	}
+
+	return NULL;
+}
+
 /* Place holder; not supported */
 static
 efi_status_t EFIAPI efi_firmware_get_image_unsupported(
@@ -103,6 +145,91 @@ efi_status_t EFIAPI efi_firmware_set_package_info_unsupported(
 }
 
 /**
+ * efi_firmware_get_lsv_from_dtb - get lowest supported version from dtb
+ * @image_index:	Image index
+ * @image_type_id:	Image type id
+ * @lsv:		Pointer to store the lowest supported version
+ *
+ * Read the firmware version information from dtb.
+ */
+static void efi_firmware_get_lsv_from_dtb(u8 image_index,
+					  efi_guid_t *image_type_id, u32 *lsv)
+{
+	const void *fdt = gd->fdt_blob;
+	const fdt32_t *val;
+	const char *guid_str;
+	int len, offset, index;
+	int parent, ret;
+
+	*lsv = 0;
+
+	parent = fdt_subnode_offset(fdt, 0, "firmware-version");
+	if (parent < 0)
+		return;
+
+	fdt_for_each_subnode(offset, fdt, parent) {
+		efi_guid_t guid;
+
+		guid_str = fdt_getprop(fdt, offset, "image-type-id", &len);
+		if (!guid_str)
+			continue;
+		ret = uuid_str_to_bin(guid_str, guid.b, UUID_STR_FORMAT_GUID);
+		if (ret < 0) {
+			log_warning("Wrong image-type-id format.\n");
+			continue;
+		}
+
+		val = fdt_getprop(fdt, offset, "image-index", &len);
+		if (!val)
+			continue;
+		index = fdt32_to_cpu(*val);
+
+		if (!guidcmp(&guid, image_type_id) && index == image_index) {
+			val = fdt_getprop(fdt, offset,
+					  "lowest-supported-version", &len);
+			if (val)
+				*lsv = fdt32_to_cpu(*val);
+		}
+	}
+}
+
+/**
+ * efi_firmware_fill_version_info - fill the version information
+ * @image_info:		Image information
+ * @fw_array:		Pointer to size of new image
+ *
+ * Fill the version information into image_info strucrure.
+ *
+ */
+static
+void efi_firmware_fill_version_info(struct efi_firmware_image_descriptor *image_info,
+				    struct efi_fw_image *fw_array)
+{
+	u16 varname[13]; /* u"FmpStateXXXX" */
+	efi_status_t ret;
+	efi_uintn_t size;
+	struct fmp_state var_state = { 0 };
+
+	efi_create_indexed_name(varname, sizeof(varname), "FmpState",
+				fw_array->image_index);
+	size = sizeof(var_state);
+	ret = efi_get_variable_int(varname, &fw_array->image_type_id,
+				   NULL, &size, &var_state, NULL);
+	if (ret == EFI_SUCCESS)
+		image_info->version = var_state.fw_version;
+	else
+		image_info->version = 0;
+
+	efi_firmware_get_lsv_from_dtb(fw_array->image_index,
+				      &fw_array->image_type_id,
+				      &image_info->lowest_supported_image_version);
+
+	image_info->version_name = NULL; /* not supported */
+	image_info->last_attempt_version = 0;
+	image_info->last_attempt_status = LAST_ATTEMPT_STATUS_SUCCESS;
+}
+
+/**
  * efi_fill_image_desc_array - populate image descriptor array
  * @image_info_size:		Size of @image_info
  * @image_info:			Image information
@@ -131,7 +258,7 @@ static efi_status_t efi_fill_image_desc_array(
 	struct efi_fw_image *fw_array;
 	int i;
 
-	total_size = sizeof(*image_info) * num_image_type_guids;
+	total_size = sizeof(*image_info) * update_info.num_images;
 
 	if (*image_info_size < total_size) {
 		*image_info_size = total_size;
@@ -141,21 +268,20 @@ static efi_status_t efi_fill_image_desc_array(
 	*image_info_size = total_size;
 
 	fw_array = update_info.images;
-	*descriptor_count = num_image_type_guids;
+	*descriptor_count = update_info.num_images;
 	*descriptor_version = EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION;
 	*descriptor_size = sizeof(*image_info);
 	*package_version = 0xffffffff; /* not supported */
 	*package_version_name = NULL; /* not supported */
 
-	for (i = 0; i < num_image_type_guids; i++) {
+	for (i = 0; i < update_info.num_images; i++) {
 		image_info[i].image_index = fw_array[i].image_index;
 		image_info[i].image_type_id = fw_array[i].image_type_id;
 		image_info[i].image_id = fw_array[i].image_index;
-
 		image_info[i].image_id_name = fw_array[i].fw_name;
 
-		image_info[i].version = 0; /* not supported */
-		image_info[i].version_name = NULL; /* not supported */
+		efi_firmware_fill_version_info(&image_info[i], &fw_array[i]);
+
 		image_info[i].size = 0;
 		image_info[i].attributes_supported =
 			IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
@@ -168,9 +294,6 @@ static efi_status_t efi_fill_image_desc_array(
 			image_info[0].attributes_setting |=
 				IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED;
 
-		image_info[i].lowest_supported_image_version = 0;
-		image_info[i].last_attempt_version = 0;
-		image_info[i].last_attempt_status = LAST_ATTEMPT_STATUS_SUCCESS;
 		image_info[i].hardware_instance = 1;
 		image_info[i].dependencies = NULL;
 	}
@@ -194,8 +317,6 @@ efi_status_t efi_firmware_capsule_authenticate(const void **p_image,
 {
 	const void *image = *p_image;
 	efi_uintn_t image_size = *p_image_size;
-	u32 fmp_hdr_signature;
-	struct fmp_payload_header *header;
 	void *capsule_payload;
 	efi_status_t status;
 	efi_uintn_t capsule_payload_size;
@@ -222,27 +343,122 @@ efi_status_t efi_firmware_capsule_authenticate(const void **p_image,
 		debug("Updating capsule without authenticating.\n");
 	}
 
-	fmp_hdr_signature = FMP_PAYLOAD_HDR_SIGNATURE;
-	header = (void *)image;
-
-	if (!memcmp(&header->signature, &fmp_hdr_signature,
-		    sizeof(fmp_hdr_signature))) {
-		/*
-		 * When building the capsule with the scripts in
-		 * edk2, a FMP header is inserted above the capsule
-		 * payload. Compensate for this header to get the
-		 * actual payload that is to be updated.
-		 */
-		image += header->header_size;
-		image_size -= header->header_size;
-	}
-
 	*p_image = image;
 	*p_image_size = image_size;
 	return EFI_SUCCESS;
 }
 
 /**
+ * efi_firmware_set_fmp_state_var - set FmpStateXXXX variable
+ * @state:		Pointer to fmp state
+ * @image_index:	image index
+ *
+ * Update the FmpStateXXXX variable with the firmware update state.
+ *
+ * Return:		status code
+ */
+static
+efi_status_t efi_firmware_set_fmp_state_var(struct fmp_state *state, u8 image_index)
+{
+	u16 varname[13]; /* u"FmpStateXXXX" */
+	efi_status_t ret;
+	efi_guid_t *image_type_id;
+	struct fmp_state var_state = { 0 };
+
+	image_type_id = efi_firmware_get_image_type_id(image_index);
+	if (!image_type_id)
+		return EFI_INVALID_PARAMETER;
+
+	efi_create_indexed_name(varname, sizeof(varname), "FmpState",
+				image_index);
+
+	/*
+	 * Only the fw_version is set here.
+	 * lowest_supported_version in FmpState variable is ignored since
+	 * it can be tampered if the file based EFI variable storage is used.
+	 */
+	var_state.fw_version = state->fw_version;
+
+	ret = efi_set_variable_int(varname, image_type_id,
+				   EFI_VARIABLE_READ_ONLY |
+				   EFI_VARIABLE_NON_VOLATILE |
+				   EFI_VARIABLE_BOOTSERVICE_ACCESS |
+				   EFI_VARIABLE_RUNTIME_ACCESS,
+				   sizeof(var_state), &var_state, false);
+
+	return ret;
+}
+
+/**
+ * efi_firmware_get_fw_version - get fw_version from FMP payload header
+ * @p_image:		Pointer to new image
+ * @p_image_size:	Pointer to size of new image
+ * @state:		Pointer to fmp state
+ *
+ * Parse the FMP payload header and fill the fmp_state structure.
+ * If no FMP payload header is found, fmp_state structure is not updated.
+ *
+ */
+static void efi_firmware_get_fw_version(const void **p_image,
+					efi_uintn_t *p_image_size,
+					struct fmp_state *state)
+{
+	const struct fmp_payload_header *header;
+	u32 fmp_hdr_signature = FMP_PAYLOAD_HDR_SIGNATURE;
+
+	header = *p_image;
+	if (header->signature == fmp_hdr_signature) {
+		/* FMP header is inserted above the capsule payload */
+		state->fw_version = header->fw_version;
+
+		*p_image += header->header_size;
+		*p_image_size -= header->header_size;
+	}
+}
+
+/**
+ * efi_firmware_verify_image - verify image
+ * @p_image:		Pointer to new image
+ * @p_image_size:	Pointer to size of new image
+ * @image_index:	Image index
+ * @state:		Pointer to fmp state
+ *
+ * Verify the capsule authentication and check if the fw_version
+ * is equal or greater than the lowest supported version.
+ *
+ * Return:		status code
+ */
+static
+efi_status_t efi_firmware_verify_image(const void **p_image,
+				       efi_uintn_t *p_image_size,
+				       u8 image_index,
+				       struct fmp_state *state)
+{
+	u32 lsv;
+	efi_status_t ret;
+	efi_guid_t *image_type_id;
+
+	ret = efi_firmware_capsule_authenticate(p_image, p_image_size);
+	if (ret != EFI_SUCCESS)
+		return ret;
+
+	efi_firmware_get_fw_version(p_image, p_image_size, state);
+
+	image_type_id = efi_firmware_get_image_type_id(image_index);
+	if (!image_type_id)
+		return EFI_INVALID_PARAMETER;
+
+	efi_firmware_get_lsv_from_dtb(image_index, image_type_id, &lsv);
+	if (state->fw_version < lsv) {
+		log_err("Firmware version %u too low. Expecting >= %u. Aborting update\n",
+			state->fw_version, lsv);
+		return EFI_INVALID_PARAMETER;
+	}
+
+	return ret;
+}
+
+/**
  * efi_firmware_get_image_info - return information about the current
  *				     firmware image
  * @this:			Protocol instance
@@ -331,6 +547,7 @@ efi_status_t EFIAPI efi_firmware_fit_set_image(
 	u16 **abort_reason)
 {
 	efi_status_t status;
+	struct fmp_state state = { 0 };
 
 	EFI_ENTRY("%p %d %p %zu %p %p %p\n", this, image_index, image,
 		  image_size, vendor_code, progress, abort_reason);
@@ -338,13 +555,16 @@ efi_status_t EFIAPI efi_firmware_fit_set_image(
 	if (!image || image_index != 1)
 		return EFI_EXIT(EFI_INVALID_PARAMETER);
 
-	status = efi_firmware_capsule_authenticate(&image, &image_size);
+	status = efi_firmware_verify_image(&image, &image_size, image_index,
+					   &state);
 	if (status != EFI_SUCCESS)
 		return EFI_EXIT(status);
 
 	if (fit_update(image))
 		return EFI_EXIT(EFI_DEVICE_ERROR);
 
+	efi_firmware_set_fmp_state_var(&state, image_index);
+
 	return EFI_EXIT(EFI_SUCCESS);
 }
 
@@ -392,6 +612,7 @@ efi_status_t EFIAPI efi_firmware_raw_set_image(
 {
 	int ret;
 	efi_status_t status;
+	struct fmp_state state = { 0 };
 
 	EFI_ENTRY("%p %d %p %zu %p %p %p\n", this, image_index, image,
 		  image_size, vendor_code, progress, abort_reason);
@@ -399,7 +620,8 @@ efi_status_t EFIAPI efi_firmware_raw_set_image(
 	if (!image)
 		return EFI_EXIT(EFI_INVALID_PARAMETER);
 
-	status = efi_firmware_capsule_authenticate(&image, &image_size);
+	status = efi_firmware_verify_image(&image, &image_size, image_index,
+					   &state);
 	if (status != EFI_SUCCESS)
 		return EFI_EXIT(status);
 
@@ -419,6 +641,8 @@ efi_status_t EFIAPI efi_firmware_raw_set_image(
 			     NULL, NULL))
 		return EFI_EXIT(EFI_DEVICE_ERROR);
 
+	efi_firmware_set_fmp_state_var(&state, image_index);
+
 	return EFI_EXIT(EFI_SUCCESS);
 }
 
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index 1f4ab2b419..cdfd16ea77 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -257,3 +257,28 @@ efi_status_t efi_next_variable_name(efi_uintn_t *size, u16 **buf, efi_guid_t *gu
 
 	return ret;
 }
+
+/**
+ * efi_search_bootorder() - search the boot option index in BootOrder
+ *
+ * @bootorder:	pointer to the BootOrder variable
+ * @num:	number of BootOrder entry
+ * @target:	target boot option index to search
+ * @index:	pointer to store the index of BootOrder variable
+ * Return:	true if exists, false otherwise
+ */
+bool efi_search_bootorder(u16 *bootorder, efi_uintn_t num, u32 target, u32 *index)
+{
+	u32 i;
+
+	for (i = 0; i < num; i++) {
+		if (target == bootorder[i]) {
+			if (index)
+				*index = i;
+
+			return true;
+		}
+	}
+
+	return false;
+}
diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c
index 26df0da16c..97547571ce 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -592,6 +592,7 @@ static bool efi_image_authenticate(void *efi, size_t efi_size)
 	struct efi_signature_store *db = NULL, *dbx = NULL;
 	void *new_efi = NULL;
 	u8 *auth, *wincerts_end;
+	u64 new_efi_size = efi_size;
 	size_t auth_size;
 	bool ret = false;
 
@@ -600,11 +601,11 @@ static bool efi_image_authenticate(void *efi, size_t efi_size)
 	if (!efi_secure_boot_enabled())
 		return true;
 
-	new_efi = efi_prepare_aligned_image(efi, (u64 *)&efi_size);
+	new_efi = efi_prepare_aligned_image(efi, &new_efi_size);
 	if (!new_efi)
 		return false;
 
-	if (!efi_image_parse(new_efi, efi_size, &regs, &wincerts,
+	if (!efi_image_parse(new_efi, new_efi_size, &regs, &wincerts,
 			     &wincerts_len)) {
 		log_err("Parsing PE executable image failed\n");
 		goto out;
diff --git a/lib/efi_loader/efi_load_options.c b/lib/efi_loader/efi_load_options.c
index 3cfddee014..5f62184da1 100644
--- a/lib/efi_loader/efi_load_options.c
+++ b/lib/efi_loader/efi_load_options.c
@@ -31,10 +31,10 @@ efi_status_t efi_set_load_options(efi_handle_t handle,
 	efi_status_t ret;
 
 	ret = efi_search_protocol(handle, &efi_guid_loaded_image, &handler);
-	loaded_image_info = handler->protocol_interface;
 	if (ret != EFI_SUCCESS)
 		return EFI_INVALID_PARAMETER;
 
+	loaded_image_info = handler->protocol_interface;
 	loaded_image_info->load_options = load_options;
 	loaded_image_info->load_options_size = load_options_size;
 
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index e2ca78d935..f752703b43 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -34,6 +34,7 @@ struct efi_mem_list {
 #define EFI_CARVE_NO_OVERLAP		-1
 #define EFI_CARVE_LOOP_AGAIN		-2
 #define EFI_CARVE_OVERLAPS_NONRAM	-3
+#define EFI_CARVE_OUT_OF_RESOURCES	-4
 
 /* This list contains all memory map items */
 static LIST_HEAD(efi_mem);
@@ -239,6 +240,8 @@ static s64 efi_mem_carve_out(struct efi_mem_list *map,
 
 	/* Create a new map from [ carve_start ... map_end ] */
 	newmap = calloc(1, sizeof(*newmap));
+	if (!newmap)
+		return EFI_CARVE_OUT_OF_RESOURCES;
 	newmap->desc = map->desc;
 	newmap->desc.physical_start = carve_start;
 	newmap->desc.virtual_start = carve_start;
@@ -282,6 +285,8 @@ static efi_status_t efi_add_memory_map_pg(u64 start, u64 pages,
 
 	++efi_memory_map_key;
 	newlist = calloc(1, sizeof(*newlist));
+	if (!newlist)
+		return EFI_OUT_OF_RESOURCES;
 	newlist->desc.type = memory_type;
 	newlist->desc.physical_start = start;
 	newlist->desc.virtual_start = start;
@@ -311,11 +316,15 @@ static efi_status_t efi_add_memory_map_pg(u64 start, u64 pages,
 			r = efi_mem_carve_out(lmem, &newlist->desc,
 					      overlap_only_ram);
 			switch (r) {
+			case EFI_CARVE_OUT_OF_RESOURCES:
+				free(newlist);
+				return EFI_OUT_OF_RESOURCES;
 			case EFI_CARVE_OVERLAPS_NONRAM:
 				/*
 				 * The user requested to only have RAM overlaps,
 				 * but we hit a non-RAM region. Error out.
 				 */
+				free(newlist);
 				return EFI_NO_MAPPING;
 			case EFI_CARVE_NO_OVERLAP:
 				/* Just ignore this list entry */
@@ -346,6 +355,7 @@ static efi_status_t efi_add_memory_map_pg(u64 start, u64 pages,
 		 * The payload wanted to have RAM overlaps, but we overlapped
 		 * with an unallocated region. Error out.
 		 */
+		free(newlist);
 		return EFI_NO_MAPPING;
 	}
 
@@ -487,7 +497,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type,
 				enum efi_memory_type memory_type,
 				efi_uintn_t pages, uint64_t *memory)
 {
-	u64 len = pages << EFI_PAGE_SHIFT;
+	u64 len;
 	efi_status_t ret;
 	uint64_t addr;
 
@@ -497,6 +507,11 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type,
 		return EFI_INVALID_PARAMETER;
 	if (!memory)
 		return EFI_INVALID_PARAMETER;
+	len = (u64)pages << EFI_PAGE_SHIFT;
+	/* Catch possible overflow on 64bit systems */
+	if (sizeof(efi_uintn_t) == sizeof(u64) &&
+	    (len >> EFI_PAGE_SHIFT) != (u64)pages)
+		return EFI_OUT_OF_RESOURCES;
 
 	switch (type) {
 	case EFI_ALLOCATE_ANY_PAGES:
@@ -862,7 +877,7 @@ efi_status_t efi_add_conventional_memory_map(u64 ram_start, u64 ram_end,
  */
 __weak void efi_add_known_memory(void)
 {
-	u64 ram_top = board_get_usable_ram_top(0) & ~EFI_PAGE_MASK;
+	u64 ram_top = gd->ram_top & ~EFI_PAGE_MASK;
 	int i;
 
 	/*
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index a83ae7a46c..7b7926a0d4 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -706,8 +706,7 @@ static efi_status_t tcg2_create_digest(const u8 *input, u32 length,
 			sha512_finish(&ctx_512, final);
 			break;
 		default:
-			EFI_PRINT("Unsupported algorithm %x\n", hash_alg);
-			return EFI_INVALID_PARAMETER;
+			continue;
 		}
 		digest_list->digests[digest_list->count].hash_alg = hash_alg;
 		memcpy(&digest_list->digests[digest_list->count].digest, final,
@@ -930,8 +929,7 @@ static efi_status_t tcg2_hash_pe_image(void *efi, u64 efi_size,
 			hash_calculate("sha512", regs->reg, regs->num, hash);
 			break;
 		default:
-			EFI_PRINT("Unsupported algorithm %x\n", hash_alg);
-			return EFI_INVALID_PARAMETER;
+			continue;
 		}
 		digest_list->digests[digest_list->count].hash_alg = hash_alg;
 		memcpy(&digest_list->digests[digest_list->count].digest, hash,
@@ -1680,8 +1678,8 @@ void tcg2_uninit(void)
 	if (!is_tcg2_protocol_installed())
 		return;
 
-	ret = efi_remove_protocol(efi_root, &efi_guid_tcg2_protocol,
-				  (void *)&efi_tcg2_protocol);
+	ret = efi_uninstall_multiple_protocol_interfaces(efi_root, &efi_guid_tcg2_protocol,
+							 &efi_tcg2_protocol, NULL);
 	if (ret != EFI_SUCCESS)
 		log_err("Failed to remove EFI TCG2 protocol\n");
 }
@@ -2507,8 +2505,8 @@ efi_status_t efi_tcg2_register(void)
 		goto fail;
 	}
 
-	ret = efi_add_protocol(efi_root, &efi_guid_tcg2_protocol,
-			       (void *)&efi_tcg2_protocol);
+	ret = efi_install_multiple_protocol_interfaces(&efi_root, &efi_guid_tcg2_protocol,
+						       &efi_tcg2_protocol, NULL);
 	if (ret != EFI_SUCCESS) {
 		tcg2_uninit();
 		goto fail;
diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c
index d6b65aed12..5fa7dcb8d3 100644
--- a/lib/efi_loader/efi_var_mem.c
+++ b/lib/efi_loader/efi_var_mem.c
@@ -177,6 +177,10 @@ efi_status_t __efi_runtime efi_var_mem_ins(
 
 u64 __efi_runtime efi_var_mem_free(void)
 {
+	if (efi_var_buf->length + sizeof(struct efi_var_entry) >=
+	    EFI_VAR_BUF_SIZE)
+		return 0;
+
 	return EFI_VAR_BUF_SIZE - efi_var_buf->length -
 	       sizeof(struct efi_var_entry);
 }
diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c
index dfef18435d..09d03c0eee 100644
--- a/lib/efi_loader/efi_variable_tee.c
+++ b/lib/efi_loader/efi_variable_tee.c
@@ -4,16 +4,38 @@
  *
  *  Copyright (C) 2019 Linaro Ltd. <sughosh.ganu@linaro.org>
  *  Copyright (C) 2019 Linaro Ltd. <ilias.apalodimas@linaro.org>
+ *  Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ *  Authors:
+ *    Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
  */
 
 #include <common.h>
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+#include <arm_ffa.h>
+#endif
+#include <cpu_func.h>
+#include <dm.h>
 #include <efi.h>
 #include <efi_api.h>
 #include <efi_loader.h>
 #include <efi_variable.h>
-#include <tee.h>
 #include <malloc.h>
+#include <mapmem.h>
 #include <mm_communication.h>
+#include <tee.h>
+
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+/* MM return codes */
+#define MM_SUCCESS (0)
+#define MM_NOT_SUPPORTED (-1)
+#define MM_INVALID_PARAMETER (-2)
+#define MM_DENIED (-3)
+#define MM_NO_MEMORY (-5)
+
+static const char *mm_sp_svc_uuid = MM_SP_UUID;
+static u16 mm_sp_id;
+#endif
 
 extern struct efi_var_file __efi_runtime_data *efi_var_buf;
 static efi_uintn_t max_buffer_size;	/* comm + var + func + data */
@@ -144,12 +166,238 @@ static efi_status_t optee_mm_communicate(void *comm_buf, ulong dsize)
 	return ret;
 }
 
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+/**
+ * ffa_notify_mm_sp() - Announce there is data in the shared buffer
+ *
+ * Notify the MM partition in the trusted world that
+ * data is available in the shared buffer.
+ * This is a blocking call during which trusted world has exclusive access
+ * to the MM shared buffer.
+ *
+ * Return:
+ *
+ * 0 on success
+ */
+static int ffa_notify_mm_sp(void)
+{
+	struct ffa_send_direct_data msg = {0};
+	int ret;
+	int sp_event_ret;
+	struct udevice *dev;
+
+	ret = uclass_first_device_err(UCLASS_FFA, &dev);
+	if (ret) {
+		log_err("EFI: Cannot find FF-A bus device, notify MM SP failure\n");
+		return ret;
+	}
+
+	msg.data0 = CONFIG_FFA_SHARED_MM_BUF_OFFSET; /* x3 */
+
+	ret = ffa_sync_send_receive(dev, mm_sp_id, &msg, 1);
+	if (ret)
+		return ret;
+
+	sp_event_ret = msg.data0; /* x3 */
+
+	switch (sp_event_ret) {
+	case MM_SUCCESS:
+		ret = 0;
+		break;
+	case MM_NOT_SUPPORTED:
+		ret = -EINVAL;
+		break;
+	case MM_INVALID_PARAMETER:
+		ret = -EPERM;
+		break;
+	case MM_DENIED:
+		ret = -EACCES;
+		break;
+	case MM_NO_MEMORY:
+		ret = -EBUSY;
+		break;
+	default:
+		ret = -EACCES;
+	}
+
+	return ret;
+}
+
+/**
+ * ffa_discover_mm_sp_id() - Query the MM partition ID
+ *
+ * Use the FF-A driver to get the MM partition ID.
+ * If multiple partitions are found, use the first one.
+ * This is a boot time function.
+ *
+ * Return:
+ *
+ * 0 on success
+ */
+static int ffa_discover_mm_sp_id(void)
+{
+	u32 count = 0;
+	int ret;
+	struct ffa_partition_desc *descs;
+	struct udevice *dev;
+
+	ret = uclass_first_device_err(UCLASS_FFA, &dev);
+	if (ret) {
+		log_err("EFI: Cannot find FF-A bus device, MM SP discovery failure\n");
+		return ret;
+	}
+
+	/* Ask the driver to fill the buffer with the SPs info */
+	ret = ffa_partition_info_get(dev, mm_sp_svc_uuid, &count, &descs);
+	if (ret) {
+		log_err("EFI: Failure in querying SPs info (%d), MM SP discovery failure\n", ret);
+		return ret;
+	}
+
+	/* MM SPs found , use the first one */
+
+	mm_sp_id = descs[0].info.id;
+
+	log_info("EFI: MM partition ID 0x%x\n", mm_sp_id);
+
+	return 0;
+}
+
 /**
- * mm_communicate() - Adjust the cmonnucation buffer to StandAlonneMM and send
+ * ffa_mm_communicate() - Exchange EFI services data with  the MM partition using FF-A
+ * @comm_buf:		locally allocated communication buffer used for rx/tx
+ * @dsize:				communication buffer size
+ *
+ * Issue a door bell event to notify the MM partition (SP) running in OP-TEE
+ * that there is data to read from the shared buffer.
+ * Communication with the MM SP is performed using FF-A transport.
+ * On the event, MM SP can read the data from the buffer and
+ * update the MM shared buffer with response data.
+ * The response data is copied back to the communication buffer.
+ *
+ * Return:
+ *
+ * EFI status code
+ */
+static efi_status_t ffa_mm_communicate(void *comm_buf, ulong comm_buf_size)
+{
+	ulong tx_data_size;
+	int ffa_ret;
+	efi_status_t efi_ret;
+	struct efi_mm_communicate_header *mm_hdr;
+	void *virt_shared_buf;
+
+	if (!comm_buf)
+		return EFI_INVALID_PARAMETER;
+
+	/* Discover MM partition ID at boot time */
+	if (!mm_sp_id && ffa_discover_mm_sp_id()) {
+		log_err("EFI: Failure to discover MM SP ID at boot time, FF-A MM comms failure\n");
+		return EFI_UNSUPPORTED;
+	}
+
+	mm_hdr = (struct efi_mm_communicate_header *)comm_buf;
+	tx_data_size = mm_hdr->message_len + sizeof(efi_guid_t) + sizeof(size_t);
+
+	if (comm_buf_size != tx_data_size || tx_data_size > CONFIG_FFA_SHARED_MM_BUF_SIZE)
+		return EFI_INVALID_PARAMETER;
+
+	/* Copy the data to the shared buffer */
+
+	virt_shared_buf = map_sysmem((phys_addr_t)CONFIG_FFA_SHARED_MM_BUF_ADDR, 0);
+	memcpy(virt_shared_buf, comm_buf, tx_data_size);
+
+	/*
+	 * The secure world might have cache disabled for
+	 * the device region used for shared buffer (which is the case for Optee).
+	 * In this case, the secure world reads the data from DRAM.
+	 * Let's flush the cache so the DRAM is updated with the latest data.
+	 */
+#ifdef CONFIG_ARM64
+	invalidate_dcache_all();
+#endif
+
+	/* Announce there is data in the shared buffer */
+
+	ffa_ret = ffa_notify_mm_sp();
+
+	switch (ffa_ret) {
+	case 0: {
+		ulong rx_data_size;
+		/* Copy the MM SP response from the shared buffer to the communication buffer */
+		rx_data_size = ((struct efi_mm_communicate_header *)virt_shared_buf)->message_len +
+			sizeof(efi_guid_t) +
+			sizeof(size_t);
+
+		if (rx_data_size > comm_buf_size) {
+			efi_ret = EFI_OUT_OF_RESOURCES;
+			break;
+		}
+
+		memcpy(comm_buf, virt_shared_buf, rx_data_size);
+		efi_ret = EFI_SUCCESS;
+		break;
+	}
+	case -EINVAL:
+		efi_ret = EFI_DEVICE_ERROR;
+		break;
+	case -EPERM:
+		efi_ret = EFI_INVALID_PARAMETER;
+		break;
+	case -EACCES:
+		efi_ret = EFI_ACCESS_DENIED;
+		break;
+	case -EBUSY:
+		efi_ret = EFI_OUT_OF_RESOURCES;
+		break;
+	default:
+		efi_ret = EFI_ACCESS_DENIED;
+	}
+
+	unmap_sysmem(virt_shared_buf);
+	return efi_ret;
+}
+
+/**
+ * get_mm_comms() - detect the available MM transport
+ *
+ * Make sure the FF-A bus is probed successfully
+ * which means FF-A communication with secure world works and ready
+ * for use.
+ *
+ * If FF-A bus is not ready, use OPTEE comms.
+ *
+ * Return:
+ *
+ * MM_COMMS_FFA or MM_COMMS_OPTEE
+ */
+static enum mm_comms_select get_mm_comms(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_FFA, &dev);
+	if (ret) {
+		log_debug("EFI: Cannot find FF-A bus device, trying Optee comms\n");
+		return MM_COMMS_OPTEE;
+	}
+
+	return MM_COMMS_FFA;
+}
+#endif
+
+/**
+ * mm_communicate() - Adjust the communication buffer to the MM SP and send
  * it to OP-TEE
  *
- * @comm_buf:		locally allocted communcation buffer
+ * @comm_buf:		locally allocated communication buffer
  * @dsize:		buffer size
+ *
+ * The SP (also called partition) can be any MM SP such as  StandAlonneMM or smm-gateway.
+ * The comm_buf format is the same for both partitions.
+ * When using the u-boot OP-TEE driver, StandAlonneMM is supported.
+ * When using the u-boot FF-A  driver, any MM SP is supported.
+ *
  * Return:		status code
  */
 static efi_status_t mm_communicate(u8 *comm_buf, efi_uintn_t dsize)
@@ -157,12 +405,24 @@ static efi_status_t mm_communicate(u8 *comm_buf, efi_uintn_t dsize)
 	efi_status_t ret;
 	struct efi_mm_communicate_header *mm_hdr;
 	struct smm_variable_communicate_header *var_hdr;
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+	enum mm_comms_select mm_comms;
+#endif
 
 	dsize += MM_COMMUNICATE_HEADER_SIZE + MM_VARIABLE_COMMUNICATE_SIZE;
 	mm_hdr = (struct efi_mm_communicate_header *)comm_buf;
 	var_hdr = (struct smm_variable_communicate_header *)mm_hdr->data;
 
-	ret = optee_mm_communicate(comm_buf, dsize);
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+	mm_comms = get_mm_comms();
+	if (mm_comms == MM_COMMS_FFA)
+		ret = ffa_mm_communicate(comm_buf, dsize);
+	else
+		ret = optee_mm_communicate(comm_buf, dsize);
+#else
+		ret = optee_mm_communicate(comm_buf, dsize);
+#endif
+
 	if (ret != EFI_SUCCESS) {
 		log_err("%s failed!\n", __func__);
 		return ret;
@@ -697,7 +957,7 @@ void efi_variables_boot_exit_notify(void)
 		ret = EFI_NOT_FOUND;
 
 	if (ret != EFI_SUCCESS)
-		log_err("Unable to notify StMM for ExitBootServices\n");
+		log_err("Unable to notify the MM partition for ExitBootServices\n");
 	free(comm_buf);
 
 	/*
diff --git a/lib/efi_selftest/efi_selftest_controllers.c b/lib/efi_selftest/efi_selftest_controllers.c
index 63e674bedc..02f19574f8 100644
--- a/lib/efi_selftest/efi_selftest_controllers.c
+++ b/lib/efi_selftest/efi_selftest_controllers.c
@@ -28,6 +28,7 @@ static efi_guid_t guid_child_controller =
 static efi_handle_t handle_controller;
 static efi_handle_t handle_child_controller[NUMBER_OF_CHILD_CONTROLLERS];
 static efi_handle_t handle_driver;
+static bool allow_removal;
 
 /*
  * Count child controllers
@@ -85,8 +86,8 @@ static efi_status_t EFIAPI supported(
 			controller_handle, EFI_OPEN_PROTOCOL_BY_DRIVER);
 	switch (ret) {
 	case EFI_ACCESS_DENIED:
-	case EFI_ALREADY_STARTED:
 		return ret;
+	case EFI_ALREADY_STARTED:
 	case EFI_SUCCESS:
 		break;
 	default:
@@ -124,8 +125,8 @@ static efi_status_t EFIAPI start(
 			controller_handle, EFI_OPEN_PROTOCOL_BY_DRIVER);
 	switch (ret) {
 	case EFI_ACCESS_DENIED:
-	case EFI_ALREADY_STARTED:
 		return ret;
+	case EFI_ALREADY_STARTED:
 	case EFI_SUCCESS:
 		break;
 	default:
@@ -238,6 +239,9 @@ static efi_status_t EFIAPI stop(
 	if (ret != EFI_SUCCESS)
 		efi_st_error("Cannot free buffer\n");
 
+	if (!allow_removal)
+		return EFI_DEVICE_ERROR;
+
 	/* Detach driver from controller */
 	ret = boottime->close_protocol(
 			controller_handle, &guid_controller,
@@ -342,6 +346,7 @@ static int execute(void)
 		return EFI_ST_FAILURE;
 	}
 	/* Destroy remaining child controllers and disconnect controller */
+	allow_removal = true;
 	ret = boottime->disconnect_controller(handle_controller, NULL, NULL);
 	if (ret != EFI_SUCCESS) {
 		efi_st_error("Failed to disconnect controller\n");
@@ -393,7 +398,40 @@ static int execute(void)
 		efi_st_error("Number of children %u != %u\n",
 			     (unsigned int)count, NUMBER_OF_CHILD_CONTROLLERS);
 	}
-	/* Uninstall controller protocol */
+
+	allow_removal = false;
+	/* Try to uninstall controller protocol using the wrong interface */
+	ret = boottime->uninstall_protocol_interface(handle_controller,
+						     &guid_controller,
+						     &interface1);
+	if (ret != EFI_NOT_FOUND) {
+		efi_st_error("Interface not checked when uninstalling protocol\n");
+		return EFI_ST_FAILURE;
+	}
+
+	/*
+	 * Uninstall a protocol while Disconnect controller won't
+	 * allow it.
+	 */
+	ret = boottime->uninstall_protocol_interface(handle_controller,
+						     &guid_controller,
+						     &interface2);
+	if (ret != EFI_ACCESS_DENIED) {
+		efi_st_error("Uninstall protocol interface failed\n");
+		return EFI_ST_FAILURE;
+	}
+	/*
+	 * Check number of child controllers and make sure children have
+	 * been reconnected
+	 */
+	ret = count_child_controllers(handle_controller, &guid_controller,
+				      &count);
+	if (ret != EFI_SUCCESS || count != NUMBER_OF_CHILD_CONTROLLERS) {
+		efi_st_error("Number of children %u != %u\n",
+			     (unsigned int)count, NUMBER_OF_CHILD_CONTROLLERS);
+	}
+
+	allow_removal = true;
 	ret = boottime->uninstall_protocol_interface(handle_controller,
 						     &guid_controller,
 						     &interface2);
diff --git a/lib/efi_selftest/efi_selftest_hii.c b/lib/efi_selftest/efi_selftest_hii.c
index f4b55889e2..f219c0120a 100644
--- a/lib/efi_selftest/efi_selftest_hii.c
+++ b/lib/efi_selftest/efi_selftest_hii.c
@@ -220,14 +220,12 @@ static int test_hii_database_list_package_lists(void)
 	if (ret != EFI_BUFFER_TOO_SMALL) {
 		efi_st_error("list_package_lists returned %u\n",
 			     (unsigned int)ret);
-		ret = EFI_ST_FAILURE;
 		goto out;
 	}
 	ret = boottime->allocate_pool(EFI_LOADER_DATA, handles_size,
 				      (void **)&handles);
 	if (ret != EFI_SUCCESS) {
 		efi_st_error("AllocatePool failed\n");
-		ret = EFI_ST_FAILURE;
 		goto out;
 	}
 	ret = hii_database_protocol->list_package_lists(hii_database_protocol,
@@ -236,7 +234,6 @@ static int test_hii_database_list_package_lists(void)
 	if (ret != EFI_SUCCESS) {
 		efi_st_error("list_package_lists returned %u\n",
 			     (unsigned int)ret);
-		ret = EFI_ST_FAILURE;
 		goto out;
 	}
 	ret = boottime->free_pool(handles);
@@ -254,14 +251,12 @@ static int test_hii_database_list_package_lists(void)
 	if (ret != EFI_BUFFER_TOO_SMALL) {
 		efi_st_error("list_package_lists returned %u\n",
 			     (unsigned int)ret);
-		ret = EFI_ST_FAILURE;
 		goto out;
 	}
 	ret = boottime->allocate_pool(EFI_LOADER_DATA, handles_size,
 				      (void **)&handles);
 	if (ret != EFI_SUCCESS) {
 		efi_st_error("AllocatePool failed\n");
-		ret = EFI_ST_FAILURE;
 		goto out;
 	}
 	ret = hii_database_protocol->list_package_lists(hii_database_protocol,
@@ -270,13 +265,11 @@ static int test_hii_database_list_package_lists(void)
 	if (ret != EFI_SUCCESS) {
 		efi_st_error("list_package_lists returned %u\n",
 			     (unsigned int)ret);
-		ret = EFI_ST_FAILURE;
 		goto out;
 	}
 	ret = boottime->free_pool(handles);
 	if (ret != EFI_SUCCESS) {
 		efi_st_error("FreePool failed\n");
-		ret = EFI_ST_FAILURE;
 		goto out;
 	}
 
@@ -289,14 +282,12 @@ static int test_hii_database_list_package_lists(void)
 	if (ret != EFI_BUFFER_TOO_SMALL) {
 		efi_st_error("list_package_lists returned %u\n",
 			     (unsigned int)ret);
-		ret = EFI_ST_FAILURE;
 		goto out;
 	}
 	ret = boottime->allocate_pool(EFI_LOADER_DATA, handles_size,
 				      (void **)&handles);
 	if (ret != EFI_SUCCESS) {
 		efi_st_error("AllocatePool failed\n");
-		ret = EFI_ST_FAILURE;
 		goto out;
 	}
 	ret = hii_database_protocol->list_package_lists(hii_database_protocol,
@@ -305,13 +296,11 @@ static int test_hii_database_list_package_lists(void)
 	if (ret != EFI_SUCCESS) {
 		efi_st_error("list_package_lists returned %u\n",
 			     (unsigned int)ret);
-		ret = EFI_ST_FAILURE;
 		goto out;
 	}
 	ret = boottime->free_pool(handles);
 	if (ret != EFI_SUCCESS) {
 		efi_st_error("FreePool failed\n");
-		ret = EFI_ST_FAILURE;
 		goto out;
 	}
 
diff --git a/lib/fwu_updates/Makefile b/lib/fwu_updates/Makefile
index 1993088e5b..c9e3c06b48 100644
--- a/lib/fwu_updates/Makefile
+++ b/lib/fwu_updates/Makefile
@@ -5,3 +5,4 @@
 
 obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += fwu.o
 obj-$(CONFIG_FWU_MDATA_GPT_BLK) += fwu_gpt.o
+obj-$(CONFIG_FWU_MDATA_MTD) += fwu_mtd.o
diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c
index 5313d07302..4d0c8b84b9 100644
--- a/lib/fwu_updates/fwu.c
+++ b/lib/fwu_updates/fwu.c
@@ -15,13 +15,13 @@
 #include <linux/errno.h>
 #include <linux/types.h>
 
+#include <u-boot/crc.h>
+
+static struct fwu_mdata g_mdata; /* = {0} makes uninit crc32 always invalid */
+static struct udevice *g_dev;
 static u8 in_trial;
 static u8 boottime_check;
 
-#include <linux/errno.h>
-#include <linux/types.h>
-#include <u-boot/crc.h>
-
 enum {
 	IMAGE_ACCEPT_SET = 1,
 	IMAGE_ACCEPT_CLEAR,
@@ -33,26 +33,6 @@ enum {
 	BOTH_PARTS,
 };
 
-static int fwu_get_dev_mdata(struct udevice **dev, struct fwu_mdata *mdata)
-{
-	int ret;
-
-	ret = uclass_first_device_err(UCLASS_FWU_MDATA, dev);
-	if (ret) {
-		log_debug("Cannot find fwu device\n");
-		return ret;
-	}
-
-	if (!mdata)
-		return 0;
-
-	ret = fwu_get_mdata(*dev, mdata);
-	if (ret < 0)
-		log_debug("Unable to get valid FWU metadata\n");
-
-	return ret;
-}
-
 static int trial_counter_update(u16 *trial_state_ctr)
 {
 	bool delete;
@@ -115,6 +95,8 @@ static int fwu_trial_count_update(void)
 			log_err("Unable to revert active_index\n");
 		ret = 1;
 	} else {
+		log_info("Trial State count: attempt %d out of %d\n",
+			 trial_state_ctr, CONFIG_FWU_TRIAL_STATE_CNT);
 		ret = trial_counter_update(&trial_state_ctr);
 		if (ret)
 			log_err("Unable to increment TrialStateCtr variable\n");
@@ -151,7 +133,7 @@ static int fwu_get_image_type_id(u8 *image_index, efi_guid_t *image_type_id)
 
 	index = *image_index;
 	image = update_info.images;
-	for (i = 0; i < num_image_type_guids; i++) {
+	for (i = 0; i < update_info.num_images; i++) {
 		if (index == image[i].image_index) {
 			guidcpy(image_type_id, &image[i].image_type_id);
 			return 0;
@@ -162,133 +144,124 @@ static int fwu_get_image_type_id(u8 *image_index, efi_guid_t *image_type_id)
 }
 
 /**
- * fwu_verify_mdata() - Verify the FWU metadata
+ * fwu_sync_mdata() - Update given meta-data partition(s) with the copy provided
  * @mdata: FWU metadata structure
- * @pri_part: FWU metadata partition is primary or secondary
- *
- * Verify the FWU metadata by computing the CRC32 for the metadata
- * structure and comparing it against the CRC32 value stored as part
- * of the structure.
+ * @part: Bitmask of FWU metadata partitions to be written to
  *
  * Return: 0 if OK, -ve on error
- *
  */
-int fwu_verify_mdata(struct fwu_mdata *mdata, bool pri_part)
+static int fwu_sync_mdata(struct fwu_mdata *mdata, int part)
 {
-	u32 calc_crc32;
-	void *buf;
+	void *buf = &mdata->version;
+	int err;
+
+	if (part == BOTH_PARTS) {
+		err = fwu_sync_mdata(mdata, SECONDARY_PART);
+		if (err)
+			return err;
+		part = PRIMARY_PART;
+	}
 
-	buf = &mdata->version;
-	calc_crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32));
+	/*
+	 * Calculate the crc32 for the updated FWU metadata
+	 * and put the updated value in the FWU metadata crc32
+	 * field
+	 */
+	mdata->crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32));
 
-	if (calc_crc32 != mdata->crc32) {
-		log_debug("crc32 check failed for %s FWU metadata partition\n",
-			  pri_part ? "primary" : "secondary");
-		return -EINVAL;
+	err = fwu_write_mdata(g_dev, mdata, part == PRIMARY_PART);
+	if (err) {
+		log_err("Unable to write %s mdata\n",
+			part == PRIMARY_PART ?  "primary" : "secondary");
+		return err;
 	}
 
+	/* update the cached copy of meta-data */
+	memcpy(&g_mdata, mdata, sizeof(struct fwu_mdata));
+
 	return 0;
 }
 
+static inline int mdata_crc_check(struct fwu_mdata *mdata)
+{
+	void *buf = &mdata->version;
+	u32 calc_crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32));
+
+	return calc_crc32 == mdata->crc32 ? 0 : -EINVAL;
+}
+
 /**
- * fwu_check_mdata_validity() - Check for validity of the FWU metadata copies
+ * fwu_get_mdata() - Read, verify and return the FWU metadata
+ * @mdata: Output FWU metadata read or NULL
  *
  * Read both the metadata copies from the storage media, verify their checksum,
  * and ascertain that both copies match. If one of the copies has gone bad,
  * restore it from the good copy.
  *
  * Return: 0 if OK, -ve on error
- *
  */
-int fwu_check_mdata_validity(void)
+int fwu_get_mdata(struct fwu_mdata *mdata)
 {
-	int ret;
-	struct udevice *dev;
-	struct fwu_mdata pri_mdata;
-	struct fwu_mdata secondary_mdata;
-	uint mdata_parts[2];
-	uint valid_partitions, invalid_partitions;
-
-	ret = fwu_get_dev_mdata(&dev, NULL);
-	if (ret)
-		return ret;
-
-	/*
-	 * Check if the platform has defined its own
-	 * function to check the metadata partitions'
-	 * validity. If so, that takes precedence.
-	 */
-	ret = fwu_mdata_check(dev);
-	if (!ret || ret != -ENOSYS)
-		return ret;
-
-	/*
-	 * Two FWU metadata partitions are expected.
-	 * If we don't have two, user needs to create
-	 * them first
-	 */
-	valid_partitions = 0;
-	ret = fwu_get_mdata_part_num(dev, mdata_parts);
-	if (ret < 0) {
-		log_debug("Error getting the FWU metadata partitions\n");
-		return -ENOENT;
-	}
-
-	ret = fwu_read_mdata_partition(dev, &pri_mdata, mdata_parts[0]);
-	if (!ret) {
-		ret = fwu_verify_mdata(&pri_mdata, 1);
-		if (!ret)
-			valid_partitions |= PRIMARY_PART;
-	}
-
-	ret = fwu_read_mdata_partition(dev, &secondary_mdata, mdata_parts[1]);
-	if (!ret) {
-		ret = fwu_verify_mdata(&secondary_mdata, 0);
-		if (!ret)
-			valid_partitions |= SECONDARY_PART;
+	int err;
+	bool parts_ok[2] = { false };
+	struct fwu_mdata s, *parts_mdata[2];
+
+	parts_mdata[0] = &g_mdata;
+	parts_mdata[1] = &s;
+
+	/* if mdata already read and ready */
+	err = mdata_crc_check(parts_mdata[0]);
+	if (!err)
+		goto ret_mdata;
+	/* else read, verify and, if needed, fix mdata */
+
+	for (int i = 0; i < 2; i++) {
+		parts_ok[i] = false;
+		err = fwu_read_mdata(g_dev, parts_mdata[i], !i);
+		if (!err) {
+			err = mdata_crc_check(parts_mdata[i]);
+			if (!err)
+				parts_ok[i] = true;
+			else
+				log_debug("mdata : %s crc32 failed\n", i ? "secondary" : "primary");
+		}
 	}
 
-	if (valid_partitions == (PRIMARY_PART | SECONDARY_PART)) {
+	if (parts_ok[0] && parts_ok[1]) {
 		/*
 		 * Before returning, check that both the
-		 * FWU metadata copies are the same. If not,
-		 * populate the secondary partition from the
+		 * FWU metadata copies are the same.
+		 */
+		err = memcmp(parts_mdata[0], parts_mdata[1], sizeof(struct fwu_mdata));
+		if (!err)
+			goto ret_mdata;
+
+		/*
+		 * If not, populate the secondary partition from the
 		 * primary partition copy.
 		 */
-		if (!memcmp(&pri_mdata, &secondary_mdata,
-			    sizeof(struct fwu_mdata))) {
-			ret = 0;
-		} else {
-			log_info("Both FWU metadata copies are valid but do not match.");
-			log_info(" Restoring the secondary partition from the primary\n");
-			ret = fwu_write_mdata_partition(dev, &pri_mdata,
-							mdata_parts[1]);
-			if (ret)
-				log_debug("Restoring secondary FWU metadata partition failed\n");
-		}
-		goto out;
+		log_info("Both FWU metadata copies are valid but do not match.");
+		log_info(" Restoring the secondary partition from the primary\n");
+		parts_ok[1] = false;
 	}
 
-	if (!(valid_partitions & BOTH_PARTS)) {
-		log_info("Both FWU metadata partitions invalid\n");
-		ret = -EBADMSG;
-		goto out;
-	}
+	for (int i = 0; i < 2; i++) {
+		if (parts_ok[i])
+			continue;
 
-	invalid_partitions = valid_partitions ^ BOTH_PARTS;
-	ret = fwu_write_mdata_partition(dev,
-					(invalid_partitions == PRIMARY_PART) ?
-					&secondary_mdata : &pri_mdata,
-					(invalid_partitions == PRIMARY_PART) ?
-					mdata_parts[0] : mdata_parts[1]);
+		memcpy(parts_mdata[i], parts_mdata[1 - i], sizeof(struct fwu_mdata));
+		err = fwu_sync_mdata(parts_mdata[i], i ? SECONDARY_PART : PRIMARY_PART);
+		if (err) {
+			log_debug("mdata : %s write failed\n", i ? "secondary" : "primary");
+			return err;
+		}
+	}
 
-	if (ret)
-		log_debug("Restoring %s FWU metadata partition failed\n",
-			  (invalid_partitions == PRIMARY_PART) ?
-			  "primary" : "secondary");
+ret_mdata:
+	if (!err && mdata)
+		memcpy(mdata, parts_mdata[0], sizeof(struct fwu_mdata));
 
-out:
-	return ret;
+	return err;
 }
 
 /**
@@ -303,19 +276,14 @@ out:
  */
 int fwu_get_active_index(uint *active_idx)
 {
-	int ret;
-	struct udevice *dev;
-	struct fwu_mdata mdata = { 0 };
-
-	ret = fwu_get_dev_mdata(&dev, &mdata);
-	if (ret)
-		return ret;
+	int ret = 0;
+	struct fwu_mdata *mdata = &g_mdata;
 
 	/*
 	 * Found the FWU metadata partition, now read the active_index
 	 * value
 	 */
-	*active_idx = mdata.active_index;
+	*active_idx = mdata->active_index;
 	if (*active_idx >= CONFIG_FWU_NUM_BANKS) {
 		log_debug("Active index value read is incorrect\n");
 		ret = -EINVAL;
@@ -336,30 +304,25 @@ int fwu_get_active_index(uint *active_idx)
 int fwu_set_active_index(uint active_idx)
 {
 	int ret;
-	struct udevice *dev;
-	struct fwu_mdata mdata = { 0 };
+	struct fwu_mdata *mdata = &g_mdata;
 
 	if (active_idx >= CONFIG_FWU_NUM_BANKS) {
 		log_debug("Invalid active index value\n");
 		return -EINVAL;
 	}
 
-	ret = fwu_get_dev_mdata(&dev, &mdata);
-	if (ret)
-		return ret;
-
 	/*
 	 * Update the active index and previous_active_index fields
 	 * in the FWU metadata
 	 */
-	mdata.previous_active_index = mdata.active_index;
-	mdata.active_index = active_idx;
+	mdata->previous_active_index = mdata->active_index;
+	mdata->active_index = active_idx;
 
 	/*
 	 * Now write this updated FWU metadata to both the
 	 * FWU metadata partitions
 	 */
-	ret = fwu_update_mdata(dev, &mdata);
+	ret = fwu_sync_mdata(mdata, BOTH_PARTS);
 	if (ret) {
 		log_debug("Failed to update FWU metadata partitions\n");
 		ret = -EIO;
@@ -389,15 +352,10 @@ int fwu_get_image_index(u8 *image_index)
 	u8 alt_num;
 	uint update_bank;
 	efi_guid_t *image_guid, image_type_id;
-	struct udevice *dev;
-	struct fwu_mdata mdata = { 0 };
+	struct fwu_mdata *mdata = &g_mdata;
 	struct fwu_image_entry *img_entry;
 	struct fwu_image_bank_info *img_bank_info;
 
-	ret = fwu_get_dev_mdata(&dev, &mdata);
-	if (ret)
-		return ret;
-
 	ret = fwu_plat_get_update_index(&update_bank);
 	if (ret) {
 		log_debug("Failed to get the FWU update bank\n");
@@ -418,11 +376,11 @@ int fwu_get_image_index(u8 *image_index)
 	 */
 	for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
 		if (!guidcmp(&image_type_id,
-			     &mdata.img_entry[i].image_type_uuid)) {
-			img_entry = &mdata.img_entry[i];
+			     &mdata->img_entry[i].image_type_uuid)) {
+			img_entry = &mdata->img_entry[i];
 			img_bank_info = &img_entry->img_bank_info[update_bank];
 			image_guid = &img_bank_info->image_uuid;
-			ret = fwu_plat_get_alt_num(dev, image_guid, &alt_num);
+			ret = fwu_plat_get_alt_num(g_dev, image_guid, &alt_num);
 			if (ret) {
 				log_debug("alt_num not found for partition with GUID %pUs\n",
 					  image_guid);
@@ -436,8 +394,8 @@ int fwu_get_image_index(u8 *image_index)
 		}
 	}
 
-	log_debug("Partition with the image type %pUs not found\n",
-		  &image_type_id);
+	log_err("Partition with the image type %pUs not found\n",
+		&image_type_id);
 
 out:
 	return ret;
@@ -457,26 +415,21 @@ int fwu_revert_boot_index(void)
 {
 	int ret;
 	u32 cur_active_index;
-	struct udevice *dev;
-	struct fwu_mdata mdata = { 0 };
-
-	ret = fwu_get_dev_mdata(&dev, &mdata);
-	if (ret)
-		return ret;
+	struct fwu_mdata *mdata = &g_mdata;
 
 	/*
 	 * Swap the active index and previous_active_index fields
 	 * in the FWU metadata
 	 */
-	cur_active_index = mdata.active_index;
-	mdata.active_index = mdata.previous_active_index;
-	mdata.previous_active_index = cur_active_index;
+	cur_active_index = mdata->active_index;
+	mdata->active_index = mdata->previous_active_index;
+	mdata->previous_active_index = cur_active_index;
 
 	/*
 	 * Now write this updated FWU metadata to both the
 	 * FWU metadata partitions
 	 */
-	ret = fwu_update_mdata(dev, &mdata);
+	ret = fwu_sync_mdata(mdata, BOTH_PARTS);
 	if (ret) {
 		log_debug("Failed to update FWU metadata partitions\n");
 		ret = -EIO;
@@ -503,16 +456,11 @@ int fwu_revert_boot_index(void)
 static int fwu_clrset_image_accept(efi_guid_t *img_type_id, u32 bank, u8 action)
 {
 	int ret, i;
-	struct udevice *dev;
-	struct fwu_mdata mdata = { 0 };
+	struct fwu_mdata *mdata = &g_mdata;
 	struct fwu_image_entry *img_entry;
 	struct fwu_image_bank_info *img_bank_info;
 
-	ret = fwu_get_dev_mdata(&dev, &mdata);
-	if (ret)
-		return ret;
-
-	img_entry = &mdata.img_entry[0];
+	img_entry = &mdata->img_entry[0];
 	for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
 		if (!guidcmp(&img_entry[i].image_type_uuid, img_type_id)) {
 			img_bank_info = &img_entry[i].img_bank_info[bank];
@@ -521,7 +469,7 @@ static int fwu_clrset_image_accept(efi_guid_t *img_type_id, u32 bank, u8 action)
 			else
 				img_bank_info->accepted = 0;
 
-			ret = fwu_update_mdata(dev, &mdata);
+			ret = fwu_sync_mdata(mdata, BOTH_PARTS);
 			goto out;
 		}
 	}
@@ -600,6 +548,24 @@ __weak int fwu_plat_get_update_index(uint *update_idx)
 }
 
 /**
+ * fwu_plat_get_bootidx() - Get the value of the boot index
+ * @boot_idx: Boot index value
+ *
+ * Get the value of the bank(partition) from which the platform
+ * has booted. This value is passed to U-Boot from the earlier
+ * stage bootloader which loads and boots all the relevant
+ * firmware images
+ */
+__weak void fwu_plat_get_bootidx(uint *boot_idx)
+{
+	int ret;
+
+	ret = fwu_get_active_index(boot_idx);
+	if (ret < 0)
+		*boot_idx = 0; /* Dummy value */
+}
+
+/**
  * fwu_update_checks_pass() - Check if FWU update can be done
  *
  * Check if the FWU update can be executed. The updates are
@@ -656,8 +622,6 @@ static int fwu_boottime_checks(void *ctx, struct event *event)
 {
 	int ret;
 	u32 boot_idx, active_idx;
-	struct udevice *dev;
-	struct fwu_mdata mdata = { 0 };
 
 	/* Don't have boot time checks on sandbox */
 	if (IS_ENABLED(CONFIG_SANDBOX)) {
@@ -665,9 +629,17 @@ static int fwu_boottime_checks(void *ctx, struct event *event)
 		return 0;
 	}
 
-	ret = fwu_check_mdata_validity();
-	if (ret)
-		return 0;
+	ret = uclass_first_device_err(UCLASS_FWU_MDATA, &g_dev);
+	if (ret) {
+		log_debug("Cannot find fwu device\n");
+		return ret;
+	}
+
+	ret = fwu_get_mdata(NULL);
+	if (ret) {
+		log_debug("Unable to read meta-data\n");
+		return ret;
+	}
 
 	/*
 	 * Get the Boot Index, i.e. the bank from
@@ -696,18 +668,12 @@ static int fwu_boottime_checks(void *ctx, struct event *event)
 		ret = fwu_set_active_index(boot_idx);
 		if (!ret)
 			boottime_check = 1;
-
-		return 0;
 	}
 
 	if (efi_init_obj_list() != EFI_SUCCESS)
 		return 0;
 
-	ret = fwu_get_dev_mdata(&dev, &mdata);
-	if (ret)
-		return ret;
-
-	in_trial = in_trial_state(&mdata);
+	in_trial = in_trial_state(&g_mdata);
 	if (!in_trial || (ret = fwu_trial_count_update()) > 0)
 		ret = trial_counter_update(NULL);
 
diff --git a/lib/fwu_updates/fwu_mtd.c b/lib/fwu_updates/fwu_mtd.c
new file mode 100644
index 0000000000..69cd3d7001
--- /dev/null
+++ b/lib/fwu_updates/fwu_mtd.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <dm.h>
+#include <dfu.h>
+#include <fwu.h>
+#include <fwu_mdata.h>
+#include <log.h>
+#include <malloc.h>
+#include <mtd.h>
+#include <uuid.h>
+#include <vsprintf.h>
+
+#include <dm/ofnode.h>
+
+struct fwu_mtd_image_info
+fwu_mtd_images[CONFIG_FWU_NUM_BANKS * CONFIG_FWU_NUM_IMAGES_PER_BANK];
+
+static struct fwu_mtd_image_info *mtd_img_by_uuid(const char *uuidbuf)
+{
+	int num_images = ARRAY_SIZE(fwu_mtd_images);
+
+	for (int i = 0; i < num_images; i++)
+		if (!strcmp(uuidbuf, fwu_mtd_images[i].uuidbuf))
+			return &fwu_mtd_images[i];
+
+	return NULL;
+}
+
+int fwu_mtd_get_alt_num(efi_guid_t *image_id, u8 *alt_num,
+			const char *mtd_dev)
+{
+	struct fwu_mtd_image_info *mtd_img_info;
+	char uuidbuf[UUID_STR_LEN + 1];
+	fdt_addr_t offset, size = 0;
+	struct dfu_entity *dfu;
+	int i, nalt, ret;
+
+	mtd_probe_devices();
+
+	uuid_bin_to_str(image_id->b, uuidbuf, UUID_STR_FORMAT_STD);
+
+	mtd_img_info = mtd_img_by_uuid(uuidbuf);
+	if (!mtd_img_info) {
+		log_err("%s: Not found partition for image %s\n", __func__, uuidbuf);
+		return -ENOENT;
+	}
+
+	offset = mtd_img_info->start;
+	size = mtd_img_info->size;
+
+	ret = dfu_init_env_entities(NULL, NULL);
+	if (ret)
+		return -ENOENT;
+
+	nalt = 0;
+	list_for_each_entry(dfu, &dfu_list, list)
+		nalt++;
+
+	if (!nalt) {
+		log_warning("No entities in dfu_alt_info\n");
+		dfu_free_entities();
+		return -ENOENT;
+	}
+
+	ret = -ENOENT;
+	for (i = 0; i < nalt; i++) {
+		dfu = dfu_get_entity(i);
+
+		/* Only MTD RAW access */
+		if (!dfu || dfu->dev_type != DFU_DEV_MTD ||
+		    dfu->layout != DFU_RAW_ADDR ||
+			dfu->data.mtd.start != offset ||
+			dfu->data.mtd.size != size)
+			continue;
+
+		*alt_num = dfu->alt;
+		ret = 0;
+		break;
+	}
+
+	dfu_free_entities();
+
+	log_debug("%s: %s -> %d\n", __func__, uuidbuf, *alt_num);
+	return ret;
+}
+
+/**
+ * fwu_plat_get_alt_num() - Get the DFU Alt Num for the image from the platform
+ * @dev: FWU device
+ * @image_id: Image GUID for which DFU alt number needs to be retrieved
+ * @alt_num: Pointer to the alt_num
+ *
+ * Get the DFU alt number from the platform for the image specified by the
+ * image GUID.
+ *
+ * Note: This is a weak function and platforms can override this with
+ * their own implementation for obtaining the alt number value.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+__weak int fwu_plat_get_alt_num(struct udevice *dev, efi_guid_t *image_id,
+				u8 *alt_num)
+{
+	return fwu_mtd_get_alt_num(image_id, alt_num, "nor1");
+}
+
+static int gen_image_alt_info(char *buf, size_t len, int sidx,
+			      struct fwu_image_entry *img, struct mtd_info *mtd)
+{
+	char *p = buf, *end = buf + len;
+	int i;
+
+	p += snprintf(p, end - p, "mtd %s", mtd->name);
+	if (end < p) {
+		log_err("%s:%d Run out of buffer\n", __func__, __LINE__);
+		return -E2BIG;
+	}
+
+	/*
+	 * List the image banks in the FWU mdata and search the corresponding
+	 * partition based on partition's uuid.
+	 */
+	for (i = 0; i < CONFIG_FWU_NUM_BANKS; i++) {
+		struct fwu_mtd_image_info *mtd_img_info;
+		struct fwu_image_bank_info *bank;
+		char uuidbuf[UUID_STR_LEN + 1];
+		u32 offset, size;
+
+		/* Query a partition by image UUID */
+		bank = &img->img_bank_info[i];
+		uuid_bin_to_str(bank->image_uuid.b, uuidbuf, UUID_STR_FORMAT_STD);
+
+		mtd_img_info = mtd_img_by_uuid(uuidbuf);
+		if (!mtd_img_info) {
+			log_err("%s: Not found partition for image %s\n", __func__, uuidbuf);
+			break;
+		}
+
+		offset = mtd_img_info->start;
+		size = mtd_img_info->size;
+
+		p += snprintf(p, end - p, "%sbank%d raw %x %x",
+			      i == 0 ? "=" : ";", i, offset, size);
+		if (end < p) {
+			log_err("%s:%d Run out of buffer\n", __func__, __LINE__);
+			return -E2BIG;
+		}
+	}
+
+	if (i == CONFIG_FWU_NUM_BANKS)
+		return 0;
+
+	return -ENOENT;
+}
+
+int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd)
+{
+	struct fwu_mdata mdata;
+	int i, l, ret;
+
+	ret = fwu_get_mdata(&mdata);
+	if (ret < 0) {
+		log_err("Failed to get the FWU mdata.\n");
+		return ret;
+	}
+
+	for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
+		ret = gen_image_alt_info(buf, len, i * CONFIG_FWU_NUM_BANKS,
+					 &mdata.img_entry[i], mtd);
+		if (ret)
+			break;
+
+		l = strlen(buf);
+		/* Replace the last ';' with '&' if there is another image. */
+		if (i != CONFIG_FWU_NUM_IMAGES_PER_BANK - 1 && l) {
+			buf[l] = '&';
+			buf++;
+		}
+		len -= l;
+		buf += l;
+	}
+
+	return ret;
+}
diff --git a/lib/image-sparse.c b/lib/image-sparse.c
index 5ec0f94ab3..8f8a67e158 100644
--- a/lib/image-sparse.c
+++ b/lib/image-sparse.c
@@ -55,7 +55,8 @@ static lbaint_t write_sparse_chunk_raw(struct sparse_storage *info,
 				       void *data,
 				       char *response)
 {
-	lbaint_t n = blkcnt, write_blks, blks = 0, aligned_buf_blks = 100;
+	lbaint_t n = blkcnt, write_blks, blks = 0;
+	lbaint_t aligned_buf_blks = FASTBOOT_MAX_BLK_WRITE;
 	uint32_t *aligned_buf = NULL;
 
 	if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
diff --git a/lib/lzma/LzmaDec.c b/lib/lzma/LzmaDec.c
index 341149f766..a90b35c6a9 100644
--- a/lib/lzma/LzmaDec.c
+++ b/lib/lzma/LzmaDec.c
@@ -152,8 +152,7 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
   const Byte *buf = p->buf;
   UInt32 range = p->range;
   UInt32 code = p->code;
-
-  schedule();
+  unsigned int loop = 0;
 
   do
   {
@@ -162,6 +161,9 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
     unsigned ttt;
     unsigned posState = processedPos & pbMask;
 
+    if (!(loop++ & 1023))
+	    schedule();
+
     prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;
     IF_BIT_0(prob)
     {
@@ -177,8 +179,6 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
         state -= (state < 4) ? state : 3;
         symbol = 1;
 
-        schedule();
-
         do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100);
       }
       else
@@ -188,8 +188,6 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
         state -= (state < 10) ? 3 : 6;
         symbol = 1;
 
-        schedule();
-
         do
         {
           unsigned bit;
@@ -321,8 +319,6 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
               UInt32 mask = 1;
               unsigned i = 1;
 
-              schedule();
-
               do
               {
                 GET_BIT2(prob + i, i, ; , distance |= mask);
@@ -335,8 +331,6 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
           {
             numDirectBits -= kNumAlignBits;
 
-            schedule();
-
             do
             {
               NORMALIZE
@@ -409,8 +403,6 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
           const Byte *lim = dest + curLen;
           dicPos += curLen;
 
-          schedule();
-
           do
             *(dest) = (Byte)*(dest + src);
           while (++dest != lim);
@@ -418,8 +410,6 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
         else
         {
 
-          schedule();
-
           do
           {
             dic[dicPos++] = dic[pos];
diff --git a/lib/of_live.c b/lib/of_live.c
index 1b5964d09a..25f7af6106 100644
--- a/lib/of_live.c
+++ b/lib/of_live.c
@@ -287,9 +287,12 @@ int unflatten_device_tree(const void *blob, struct device_node **mynodes)
 	debug("  size is %lx, allocating...\n", size);
 
 	/* Allocate memory for the expanded device tree */
-	mem = malloc(size + 4);
+	mem = memalign(__alignof__(struct device_node), size + 4);
 	memset(mem, '\0', size);
 
+	/* Set up value for dm_test_livetree_align() */
+	*(u32 *)mem = BAD_OF_ROOT;
+
 	*(__be32 *)(mem + size) = cpu_to_be32(0xdeadbeef);
 
 	debug("  unflattening %p...\n", mem);
@@ -327,3 +330,9 @@ int of_live_build(const void *fdt_blob, struct device_node **rootp)
 
 	return ret;
 }
+
+void of_live_free(struct device_node *root)
+{
+	/* the tree is stored as a contiguous block of memory */
+	free(root);
+}
diff --git a/lib/uuid.c b/lib/uuid.c
index 96e1af3c8b..d0187007d0 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -1,6 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2011 Calxeda, Inc.
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
  */
 
 #include <common.h>
@@ -255,7 +259,7 @@ static const struct {
 		EFI_CERT_TYPE_PKCS7_GUID,
 	},
 #endif
-#ifdef CONFIG_EFI
+#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI)
 	{ "EFI_LZMA_COMPRESSED", EFI_LZMA_COMPRESSED },
 	{ "EFI_DXE_SERVICES", EFI_DXE_SERVICES },
 	{ "EFI_HOB_LIST", EFI_HOB_LIST },
@@ -354,6 +358,50 @@ int uuid_str_to_bin(const char *uuid_str, unsigned char *uuid_bin,
 	return 0;
 }
 
+/**
+ * uuid_str_to_le_bin() - Convert string UUID to little endian binary data.
+ * @uuid_str:	pointer to UUID string
+ * @uuid_bin:	pointer to allocated array for little endian output [16B]
+ *
+ * UUID string is 36 characters (36 bytes):
+ *
+ * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+ *
+ * where x is a hexadecimal character. Fields are separated by '-'s.
+ * When converting to a little endian binary UUID, the string fields are reversed.
+ *
+ * Return:
+ *
+ *    uuid_bin filled with little endian UUID data
+ *    On success 0 is returned. Otherwise, failure code.
+ */
+int uuid_str_to_le_bin(const char *uuid_str, unsigned char *uuid_bin)
+{
+	u16 tmp16;
+	u32 tmp32;
+	u64 tmp64;
+
+	if (!uuid_str_valid(uuid_str) || !uuid_bin)
+		return -EINVAL;
+
+	tmp32 = cpu_to_le32(hextoul(uuid_str, NULL));
+	memcpy(uuid_bin, &tmp32, 4);
+
+	tmp16 = cpu_to_le16(hextoul(uuid_str + 9, NULL));
+	memcpy(uuid_bin + 4, &tmp16, 2);
+
+	tmp16 = cpu_to_le16(hextoul(uuid_str + 14, NULL));
+	memcpy(uuid_bin + 6, &tmp16, 2);
+
+	tmp16 = cpu_to_le16(hextoul(uuid_str + 19, NULL));
+	memcpy(uuid_bin + 8, &tmp16, 2);
+
+	tmp64 = cpu_to_le64(simple_strtoull(uuid_str + 24, NULL, 16));
+	memcpy(uuid_bin + 10, &tmp64, 6);
+
+	return 0;
+}
+
 /*
  * uuid_bin_to_str() - convert big endian binary data to string UUID or GUID.
  *
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index e87503e41a..e14c6ca9f9 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -680,8 +680,10 @@ repeat:
 			break;
 
 		case 'd':
-			if (fmt[1] == 'E')
+			if (fmt[1] == 'E') {
 				flags |= ERRSTR;
+				fmt++;
+			}
 		/* fallthrough */
 		case 'i':
 			flags |= SIGN;
@@ -725,7 +727,6 @@ repeat:
 			ADDCH(str, ' ');
 			for (p = errno_str(num); *p; p++)
 				ADDCH(str, *p);
-			fmt++;
 		}
 	}
 
diff --git a/lib/zlib/inflate.c b/lib/zlib/inflate.c
index 30dfe15599..8f767b7b9d 100644
--- a/lib/zlib/inflate.c
+++ b/lib/zlib/inflate.c
@@ -455,8 +455,9 @@ int ZEXPORT inflate(z_streamp strm, int flush)
                 if (copy > have) copy = have;
                 if (copy) {
                     if (state->head != Z_NULL &&
-                        state->head->extra != Z_NULL) {
-                        len = state->head->extra_len - state->length;
+                        state->head->extra != Z_NULL &&
+                        (len = state->head->extra_len - state->length) <
+                            state->head->extra_max) {
                         zmemcpy(state->head->extra + len, next,
                                 len + copy > state->head->extra_max ?
                                 state->head->extra_max - len : copy);
diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c
index dd78e5744d..f64c68e340 100644
--- a/net/dsa-uclass.c
+++ b/net/dsa-uclass.c
@@ -381,7 +381,7 @@ static int dsa_post_bind(struct udevice *dev)
 
 	node = ofnode_find_subnode(node, "ports");
 	if (!ofnode_valid(node))
-		node = ofnode_find_subnode(node, "ethernet-ports");
+		node = ofnode_find_subnode(dev_ofnode(dev), "ethernet-ports");
 	if (!ofnode_valid(node)) {
 		dev_err(dev, "ports node is missing under DSA device!\n");
 		return -EINVAL;
diff --git a/net/eth_bootdev.c b/net/eth_bootdev.c
index f7b4196f78..869adf8cbb 100644
--- a/net/eth_bootdev.c
+++ b/net/eth_bootdev.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Bootdevice for ethernet (uses PXE)
+ * Bootdev for ethernet (uses PXE)
  *
  * Copyright 2021 Google LLC
  * Written by Simon Glass <sjg@chromium.org>
diff --git a/net/ndisc.c b/net/ndisc.c
index 0b27779ce5..d1cec0601c 100644
--- a/net/ndisc.c
+++ b/net/ndisc.c
@@ -382,6 +382,8 @@ int process_ra(struct ip6_hdr *ip6, int len)
 	unsigned char type = 0;
 	struct icmp6_ra_prefix_info *prefix = NULL;
 
+	if (len > ETH_MAX_MTU)
+		return -EMSGSIZE;
 	/* Ignore the packet if router lifetime is 0. */
 	if (!icmp->icmp6_rt_lifetime)
 		return -EOPNOTSUPP;
diff --git a/py/travis-ci/u_boot_boardenv_M5208EVBE_qemu.py b/py/travis-ci/u_boot_boardenv_M5208EVBE_qemu.py
deleted file mode 100644
index 4e100cd410..0000000000
--- a/py/travis-ci/u_boot_boardenv_M5208EVBE_qemu.py
+++ /dev/null
@@ -1,6 +0,0 @@
-import os
-import travis_tftp
-
-env__net_uses_pci = False
-env__net_dhcp_server = True
-env__net_tftp_readable_file = travis_tftp.file2env('u-boot')
diff --git a/scripts/Makefile.dts b/scripts/Makefile.dts
index 2561025da8..5e2429c617 100644
--- a/scripts/Makefile.dts
+++ b/scripts/Makefile.dts
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_$(SPL_)OF_LIST)))
+dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE) $(CONFIG_OF_LIST) $(CONFIG_SPL_OF_LIST)))
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 7b27224b5d..f5ab7af0f4 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -186,7 +186,7 @@ u_boot_dtsi = $(strip $(u_boot_dtsi_options_debug) \
 # Modified for U-Boot
 dtc_cpp_flags  = -Wp,-MD,$(depfile).pre.tmp -nostdinc                    \
 		 $(UBOOTINCLUDE)                                         \
-		 -I$(srctree)/arch/$(ARCH)/dts                           \
+		 -I$(dir $<)                                             \
 		 -I$(srctree)/arch/$(ARCH)/dts/include                   \
 		 -I$(srctree)/include                                    \
 		 -D__ASSEMBLY__                                          \
@@ -331,7 +331,7 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
 		; \
 	sed "s:$(pre-tmp):$(<):" $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
 
-$(obj)/%.dtb: $(src)/%.dts FORCE
+$(obj)/%.dtb: $(src)/%.dts $(DTC) FORCE
 	$(call if_changed_dep,dtc)
 
 pre-tmp = $(subst $(comma),_,$(dot-target).pre.tmp)
@@ -351,7 +351,10 @@ cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \
 		-d $(depfile).dtc.tmp $(dtc-tmp) ; \
 	cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
 
-$(obj)/%.dtbo: $(src)/%.dts FORCE
+$(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE
+	$(call if_changed_dep,dtco)
+
+$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
 	$(call if_changed_dep,dtco)
 
 # Fonts
diff --git a/scripts/dtc-version.sh b/scripts/dtc-version.sh
index bfb514e179..53ff868bcd 100755
--- a/scripts/dtc-version.sh
+++ b/scripts/dtc-version.sh
@@ -20,7 +20,7 @@ if ! which $dtc >/dev/null ; then
 	exit 1
 fi
 
-MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1)
+MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1 | tr -d v)
 MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2)
 PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1)
 
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index 2b5f87d7f0..8a4e090e9b 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -226,6 +226,7 @@ static int bootflow_cmd_info(struct unit_test_state *uts)
 	ut_assert_nextlinen("Buffer:    ");
 	ut_assert_nextline("Size:      253 (595 bytes)");
 	ut_assert_nextline("OS:        Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)");
+	ut_assert_nextline("Cmdline:   (none)");
 	ut_assert_nextline("Logo:      (none)");
 	ut_assert_nextline("FDT:       <NULL>");
 	ut_assert_nextline("Error:     0");
@@ -682,3 +683,265 @@ static int bootflow_menu_theme(struct unit_test_state *uts)
 	return 0;
 }
 BOOTSTD_TEST(bootflow_menu_theme, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+
+/**
+ * check_arg() - Check both the normal case and the buffer-overflow case
+ *
+ * @uts: Unit-test state
+ * @expect_ret: Expected return value (i.e. buffer length)
+ * @expect_str: String expected to be returned
+ * @buf: Buffer to use
+ * @from: Original cmdline to update
+ * @arg: Argument to update (e.g. "console")
+ * @val: Value to set (e.g. "ttyS2") or NULL to delete the argument if present,
+ * "" to set it to an empty value (e.g. "console=") and BOOTFLOWCL_EMPTY to add
+ * it without any value ("initrd")
+ */
+static int check_arg(struct unit_test_state *uts, int expect_ret,
+		     const char *expect_str, char *buf, const char *from,
+		     const char *arg, const char *val)
+{
+	/* check for writing outside the reported bounds */
+	buf[expect_ret] = '[';
+	ut_asserteq(expect_ret,
+		    cmdline_set_arg(buf, expect_ret, from, arg, val, NULL));
+	ut_asserteq_str(expect_str, buf);
+	ut_asserteq('[', buf[expect_ret]);
+
+	/* do the test again but with one less byte in the buffer */
+	ut_asserteq(-E2BIG, cmdline_set_arg(buf, expect_ret - 1, from, arg,
+					    val, NULL));
+
+	return 0;
+}
+
+/* Test of bootflow_cmdline_set_arg() */
+static int test_bootflow_cmdline_set(struct unit_test_state *uts)
+{
+	char buf[50];
+	const int size = sizeof(buf);
+
+	/*
+	 * note that buffer-overflow tests are immediately each test case, just
+	 * top keep the code together
+	 */
+
+	/* add an arg that doesn't already exist, starting from empty */
+	ut_asserteq(-ENOENT, cmdline_set_arg(buf, size, NULL, "me", NULL,
+					     NULL));
+
+	ut_assertok(check_arg(uts, 3, "me", buf, NULL, "me", BOOTFLOWCL_EMPTY));
+	ut_assertok(check_arg(uts, 4, "me=", buf, NULL, "me", ""));
+	ut_assertok(check_arg(uts, 8, "me=fred", buf, NULL, "me", "fred"));
+
+	/* add an arg that doesn't already exist, starting from non-empty */
+	ut_assertok(check_arg(uts, 11, "arg=123 me", buf, "arg=123", "me",
+			      BOOTFLOWCL_EMPTY));
+	ut_assertok(check_arg(uts, 12, "arg=123 me=", buf, "arg=123", "me",
+			      ""));
+	ut_assertok(check_arg(uts, 16, "arg=123 me=fred", buf, "arg=123", "me",
+			      "fred"));
+
+	/* update an arg at the start */
+	ut_assertok(check_arg(uts, 1, "", buf, "arg=123", "arg", NULL));
+	ut_assertok(check_arg(uts, 4, "arg", buf, "arg=123", "arg",
+			      BOOTFLOWCL_EMPTY));
+	ut_assertok(check_arg(uts, 5, "arg=", buf, "arg=123", "arg", ""));
+	ut_assertok(check_arg(uts, 6, "arg=1", buf, "arg=123", "arg", "1"));
+	ut_assertok(check_arg(uts, 9, "arg=1234", buf, "arg=123", "arg",
+			      "1234"));
+
+	/* update an arg at the end */
+	ut_assertok(check_arg(uts, 5, "mary", buf, "mary arg=123", "arg",
+			      NULL));
+	ut_assertok(check_arg(uts, 9, "mary arg", buf, "mary arg=123", "arg",
+			      BOOTFLOWCL_EMPTY));
+	ut_assertok(check_arg(uts, 10, "mary arg=", buf, "mary arg=123", "arg",
+			      ""));
+	ut_assertok(check_arg(uts, 11, "mary arg=1", buf, "mary arg=123", "arg",
+			      "1"));
+	ut_assertok(check_arg(uts, 14, "mary arg=1234", buf, "mary arg=123",
+			      "arg", "1234"));
+
+	/* update an arg in the middle */
+	ut_assertok(check_arg(uts, 16, "mary=abc john=2", buf,
+			      "mary=abc arg=123 john=2", "arg", NULL));
+	ut_assertok(check_arg(uts, 20, "mary=abc arg john=2", buf,
+			      "mary=abc arg=123 john=2", "arg",
+			      BOOTFLOWCL_EMPTY));
+	ut_assertok(check_arg(uts, 21, "mary=abc arg= john=2", buf,
+			      "mary=abc arg=123 john=2", "arg", ""));
+	ut_assertok(check_arg(uts, 22, "mary=abc arg=1 john=2", buf,
+			      "mary=abc arg=123 john=2", "arg", "1"));
+	ut_assertok(check_arg(uts, 25, "mary=abc arg=1234 john=2", buf,
+			      "mary=abc arg=123 john=2", "arg", "1234"));
+
+	/* handle existing args with quotes */
+	ut_assertok(check_arg(uts, 16, "mary=\"abc\" john", buf,
+			      "mary=\"abc\" arg=123 john", "arg", NULL));
+
+	/* handle existing args with quoted spaces */
+	ut_assertok(check_arg(uts, 20, "mary=\"abc def\" john", buf,
+			      "mary=\"abc def\" arg=123 john", "arg", NULL));
+
+	ut_assertok(check_arg(uts, 34, "mary=\"abc def\" arg=123 john def=4",
+			      buf, "mary=\"abc def\" arg=123 john", "def",
+			      "4"));
+
+	/* quote at the start */
+	ut_asserteq(-EBADF, cmdline_set_arg(buf, size,
+					    "mary=\"abc def\" arg=\"123 456\"",
+					    "arg", "\"4 5 6", NULL));
+
+	/* quote at the end */
+	ut_asserteq(-EBADF, cmdline_set_arg(buf, size,
+					    "mary=\"abc def\" arg=\"123 456\"",
+					    "arg", "4 5 6\"", NULL));
+
+	/* quote in the middle */
+	ut_asserteq(-EBADF, cmdline_set_arg(buf, size,
+					    "mary=\"abc def\" arg=\"123 456\"",
+					    "arg", "\"4 \"5 6\"", NULL));
+
+	/* handle updating a quoted arg */
+	ut_assertok(check_arg(uts, 27, "mary=\"abc def\" arg=\"4 5 6\"", buf,
+			      "mary=\"abc def\" arg=\"123 456\"", "arg",
+			      "4 5 6"));
+
+	/* changing a quoted arg to a non-quoted arg */
+	ut_assertok(check_arg(uts, 23, "mary=\"abc def\" arg=789", buf,
+			      "mary=\"abc def\" arg=\"123 456\"", "arg",
+			      "789"));
+
+	/* changing a non-quoted arg to a quoted arg */
+	ut_assertok(check_arg(uts, 29, "mary=\"abc def\" arg=\"456 789\"", buf,
+			      "mary=\"abc def\" arg=123", "arg", "456 789"));
+
+	/* handling of spaces */
+	ut_assertok(check_arg(uts, 8, "arg=123", buf, " ", "arg", "123"));
+	ut_assertok(check_arg(uts, 8, "arg=123", buf, "   ", "arg", "123"));
+	ut_assertok(check_arg(uts, 13, "john arg=123", buf, " john  ", "arg",
+			      "123"));
+	ut_assertok(check_arg(uts, 13, "john arg=123", buf, " john  arg=123  ",
+			      "arg", "123"));
+	ut_assertok(check_arg(uts, 18, "john arg=123 mary", buf,
+			      " john  arg=123 mary ", "arg", "123"));
+
+	/* unchanged arg */
+	ut_assertok(check_arg(uts, 3, "me", buf, "me", "me", BOOTFLOWCL_EMPTY));
+
+	/* arg which starts with the same name */
+	ut_assertok(check_arg(uts, 28, "mary=abc johnathon=2 john=3", buf,
+			      "mary=abc johnathon=2 john=1", "john", "3"));
+
+	return 0;
+}
+BOOTSTD_TEST(test_bootflow_cmdline_set, 0);
+
+/* Test of bootflow_cmdline_set_arg() */
+static int bootflow_set_arg(struct unit_test_state *uts)
+{
+	struct bootflow s_bflow, *bflow = &s_bflow;
+	ulong mem_start;
+
+	ut_assertok(env_set("bootargs", NULL));
+
+	mem_start = ut_check_delta(0);
+
+	/* Do a simple sanity check. Rely on bootflow_cmdline() for the rest */
+	bflow->cmdline = NULL;
+	ut_assertok(bootflow_cmdline_set_arg(bflow, "fred", "123", false));
+	ut_asserteq_str(bflow->cmdline, "fred=123");
+
+	ut_assertok(bootflow_cmdline_set_arg(bflow, "mary", "and here", false));
+	ut_asserteq_str(bflow->cmdline, "fred=123 mary=\"and here\"");
+
+	ut_assertok(bootflow_cmdline_set_arg(bflow, "mary", NULL, false));
+	ut_asserteq_str(bflow->cmdline, "fred=123");
+	ut_assertok(bootflow_cmdline_set_arg(bflow, "fred", NULL, false));
+	ut_asserteq_ptr(bflow->cmdline, NULL);
+
+	ut_asserteq(0, ut_check_delta(mem_start));
+
+	ut_assertok(bootflow_cmdline_set_arg(bflow, "mary", "here", true));
+	ut_asserteq_str("mary=here", env_get("bootargs"));
+	ut_assertok(env_set("bootargs", NULL));
+
+	return 0;
+}
+BOOTSTD_TEST(bootflow_set_arg, 0);
+
+/* Test of bootflow_cmdline_get_arg() */
+static int bootflow_cmdline_get(struct unit_test_state *uts)
+{
+	int pos;
+
+	/* empty string */
+	ut_asserteq(-ENOENT, cmdline_get_arg("", "fred", &pos));
+
+	/* arg with empty value */
+	ut_asserteq(0, cmdline_get_arg("fred= mary", "fred", &pos));
+	ut_asserteq(5, pos);
+
+	/* arg with a value */
+	ut_asserteq(2, cmdline_get_arg("fred=23", "fred", &pos));
+	ut_asserteq(5, pos);
+
+	/* arg with a value */
+	ut_asserteq(3, cmdline_get_arg("mary=1 fred=234", "fred", &pos));
+	ut_asserteq(12, pos);
+
+	/* arg with a value, after quoted arg */
+	ut_asserteq(3, cmdline_get_arg("mary=\"1 2\" fred=234", "fred", &pos));
+	ut_asserteq(16, pos);
+
+	/* arg in the middle */
+	ut_asserteq(0, cmdline_get_arg("mary=\"1 2\" fred john=23", "fred",
+				       &pos));
+	ut_asserteq(15, pos);
+
+	/* quoted arg */
+	ut_asserteq(3, cmdline_get_arg("mary=\"1 2\" fred=\"3 4\" john=23",
+				       "fred", &pos));
+	ut_asserteq(17, pos);
+
+	/* args starting with the same prefix */
+	ut_asserteq(1, cmdline_get_arg("mary=abc johnathon=3 john=1", "john",
+				       &pos));
+	ut_asserteq(26, pos);
+
+	return 0;
+}
+BOOTSTD_TEST(bootflow_cmdline_get, 0);
+
+static int bootflow_cmdline(struct unit_test_state *uts)
+{
+	ut_assertok(run_command("bootflow scan mmc", 0));
+	ut_assertok(run_command("bootflow sel 0", 0));
+	console_record_reset_enable();
+
+	ut_asserteq(1, run_command("bootflow cmdline get fred", 0));
+	ut_assert_nextline("Argument not found");
+	ut_assert_console_end();
+
+	ut_asserteq(0, run_command("bootflow cmdline set fred 123", 0));
+	ut_asserteq(0, run_command("bootflow cmdline get fred", 0));
+	ut_assert_nextline("123");
+
+	ut_asserteq(0, run_command("bootflow cmdline set mary abc", 0));
+	ut_asserteq(0, run_command("bootflow cmdline get mary", 0));
+	ut_assert_nextline("abc");
+
+	ut_asserteq(0, run_command("bootflow cmdline delete fred", 0));
+	ut_asserteq(1, run_command("bootflow cmdline get fred", 0));
+	ut_assert_nextline("Argument not found");
+
+	ut_asserteq(0, run_command("bootflow cmdline clear mary", 0));
+	ut_asserteq(0, run_command("bootflow cmdline get mary", 0));
+	ut_assert_nextline_empty();
+
+	ut_assert_console_end();
+
+	return 0;
+}
+BOOTSTD_TEST(bootflow_cmdline, 0);
diff --git a/test/boot/expo.c b/test/boot/expo.c
index 7104dff05e..3898f853a7 100644
--- a/test/boot/expo.c
+++ b/test/boot/expo.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <command.h>
 #include <dm.h>
 #include <expo.h>
 #include <menu.h>
@@ -13,6 +14,7 @@
 #include <test/suites.h>
 #include <test/ut.h>
 #include "bootstd_common.h"
+#include <test/cedit-test.h>
 #include "../../boot/scene_internal.h"
 
 enum {
@@ -28,6 +30,8 @@ enum {
 	OBJ_MENU_TITLE,
 
 	/* strings */
+	STR_SCENE_TITLE,
+
 	STR_TEXT,
 	STR_TEXT2,
 	STR_MENU_TITLE,
@@ -120,7 +124,7 @@ static int expo_scene(struct unit_test_state *uts)
 	struct expo *exp;
 	ulong start_mem;
 	char name[100];
-	int id;
+	int id, title_id;
 
 	start_mem = ut_check_free();
 
@@ -141,21 +145,20 @@ static int expo_scene(struct unit_test_state *uts)
 	ut_asserteq_str(SCENE_NAME1, scn->name);
 
 	/* Set the title */
-	strcpy(name, SCENE_TITLE);
-	ut_assertok(scene_title_set(scn, name));
-	*name = '\0';
-	ut_assertnonnull(scn->title);
-	ut_asserteq_str(SCENE_TITLE, scn->title);
+	title_id = expo_str(exp, "title", STR_SCENE_TITLE, SCENE_TITLE);
+	ut_assert(title_id >= 0);
 
-	/* Use an allocated ID */
+	/* Use an allocated ID - this will be allocated after the title str */
 	scn = NULL;
 	id = scene_new(exp, SCENE_NAME2, 0, &scn);
 	ut_assertnonnull(scn);
-	ut_asserteq(SCENE2, id);
-	ut_asserteq(SCENE2 + 1, exp->next_id);
+	ut_assertok(scene_title_set(scn, title_id));
+	ut_asserteq(STR_SCENE_TITLE + 1, id);
+	ut_asserteq(STR_SCENE_TITLE + 2, exp->next_id);
 	ut_asserteq_ptr(exp, scn->expo);
 
 	ut_asserteq_str(SCENE_NAME2, scn->name);
+	ut_asserteq(title_id, scn->title_id);
 
 	expo_destroy(exp);
 
@@ -225,7 +228,7 @@ static int expo_object(struct unit_test_state *uts)
 }
 BOOTSTD_TEST(expo_object, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
 
-/* Check setting object attributes */
+/* Check setting object attributes and using themes */
 static int expo_object_attr(struct unit_test_state *uts)
 {
 	struct scene_obj_menu *menu;
@@ -235,6 +238,7 @@ static int expo_object_attr(struct unit_test_state *uts)
 	struct expo *exp;
 	ulong start_mem;
 	char name[100];
+	ofnode node;
 	char *data;
 	int id;
 
@@ -249,8 +253,8 @@ static int expo_object_attr(struct unit_test_state *uts)
 	ut_assert(id > 0);
 
 	ut_assertok(scene_obj_set_pos(scn, OBJ_LOGO, 123, 456));
-	ut_asserteq(123, img->obj.x);
-	ut_asserteq(456, img->obj.y);
+	ut_asserteq(123, img->obj.dim.x);
+	ut_asserteq(456, img->obj.dim.y);
 
 	ut_asserteq(-ENOENT, scene_obj_set_pos(scn, OBJ_TEXT2, 0, 0));
 
@@ -272,6 +276,11 @@ static int expo_object_attr(struct unit_test_state *uts)
 	ut_asserteq(-ENOENT, scene_menu_set_title(scn, OBJ_TEXT2, OBJ_TEXT));
 	ut_asserteq(-EINVAL, scene_menu_set_title(scn, OBJ_MENU, OBJ_TEXT2));
 
+	node = ofnode_path("/bootstd/theme");
+	ut_assert(ofnode_valid(node));
+	ut_assertok(expo_apply_theme(exp, node));
+	ut_asserteq(30, txt->font_size);
+
 	expo_destroy(exp);
 
 	ut_assertok(ut_check_delta(start_mem));
@@ -306,8 +315,8 @@ static int expo_object_menu(struct unit_test_state *uts)
 	ut_asserteq(0, menu->pointer_id);
 
 	ut_assertok(scene_obj_set_pos(scn, OBJ_MENU, 50, 400));
-	ut_asserteq(50, menu->obj.x);
-	ut_asserteq(400, menu->obj.y);
+	ut_asserteq(50, menu->obj.dim.x);
+	ut_asserteq(400, menu->obj.dim.y);
 
 	id = scene_txt_str(scn, "title", OBJ_MENU_TITLE, STR_MENU_TITLE,
 			   "Main Menu", &tit);
@@ -347,29 +356,31 @@ static int expo_object_menu(struct unit_test_state *uts)
 	ut_asserteq(desc_id, item->desc_id);
 	ut_asserteq(preview_id, item->preview_id);
 
-	/* adding an item should cause the first item to become current */
+	ut_assertok(scene_arrange(scn));
+
+	/* arranging the scene should cause the first item to become current */
 	ut_asserteq(id, menu->cur_item_id);
 
 	/* the title should be at the top */
-	ut_asserteq(menu->obj.x, tit->obj.x);
-	ut_asserteq(menu->obj.y, tit->obj.y);
+	ut_asserteq(menu->obj.dim.x, tit->obj.dim.x);
+	ut_asserteq(menu->obj.dim.y, tit->obj.dim.y);
 
 	/* the first item should be next */
-	ut_asserteq(menu->obj.x, name1->obj.x);
-	ut_asserteq(menu->obj.y + 32, name1->obj.y);
+	ut_asserteq(menu->obj.dim.x, name1->obj.dim.x);
+	ut_asserteq(menu->obj.dim.y + 32, name1->obj.dim.y);
 
-	ut_asserteq(menu->obj.x + 230, key1->obj.x);
-	ut_asserteq(menu->obj.y + 32, key1->obj.y);
+	ut_asserteq(menu->obj.dim.x + 230, key1->obj.dim.x);
+	ut_asserteq(menu->obj.dim.y + 32, key1->obj.dim.y);
 
-	ut_asserteq(menu->obj.x + 200, ptr->obj.x);
-	ut_asserteq(menu->obj.y + 32, ptr->obj.y);
+	ut_asserteq(menu->obj.dim.x + 200, ptr->obj.dim.x);
+	ut_asserteq(menu->obj.dim.y + 32, ptr->obj.dim.y);
 
-	ut_asserteq(menu->obj.x + 280, desc1->obj.x);
-	ut_asserteq(menu->obj.y + 32, desc1->obj.y);
+	ut_asserteq(menu->obj.dim.x + 280, desc1->obj.dim.x);
+	ut_asserteq(menu->obj.dim.y + 32, desc1->obj.dim.y);
 
-	ut_asserteq(-4, prev1->obj.x);
-	ut_asserteq(menu->obj.y + 32, prev1->obj.y);
-	ut_asserteq(false, prev1->obj.hide);
+	ut_asserteq(-4, prev1->obj.dim.x);
+	ut_asserteq(menu->obj.dim.y + 32, prev1->obj.dim.y);
+	ut_asserteq(true, prev1->obj.flags & SCENEOF_HIDE);
 
 	expo_destroy(exp);
 
@@ -470,6 +481,48 @@ static int expo_render_image(struct unit_test_state *uts)
 	/* render without a scene */
 	ut_asserteq(-ECHILD, expo_render(exp));
 
+	ut_assertok(expo_calc_dims(exp));
+	ut_assertok(scene_arrange(scn));
+
+	/* check dimensions of text */
+	obj = scene_obj_find(scn, OBJ_TEXT, SCENEOBJT_NONE);
+	ut_assertnonnull(obj);
+	ut_asserteq(400, obj->dim.x);
+	ut_asserteq(100, obj->dim.y);
+	ut_asserteq(126, obj->dim.w);
+	ut_asserteq(40, obj->dim.h);
+
+	/* check dimensions of image */
+	obj = scene_obj_find(scn, OBJ_LOGO, SCENEOBJT_NONE);
+	ut_assertnonnull(obj);
+	ut_asserteq(50, obj->dim.x);
+	ut_asserteq(20, obj->dim.y);
+	ut_asserteq(160, obj->dim.w);
+	ut_asserteq(160, obj->dim.h);
+
+	/* check dimensions of menu labels - both should be the same width */
+	obj = scene_obj_find(scn, ITEM1_LABEL, SCENEOBJT_NONE);
+	ut_assertnonnull(obj);
+	ut_asserteq(50, obj->dim.x);
+	ut_asserteq(436, obj->dim.y);
+	ut_asserteq(29, obj->dim.w);
+	ut_asserteq(18, obj->dim.h);
+
+	obj = scene_obj_find(scn, ITEM2_LABEL, SCENEOBJT_NONE);
+	ut_assertnonnull(obj);
+	ut_asserteq(50, obj->dim.x);
+	ut_asserteq(454, obj->dim.y);
+	ut_asserteq(29, obj->dim.w);
+	ut_asserteq(18, obj->dim.h);
+
+	/* check dimensions of menu */
+	obj = scene_obj_find(scn, OBJ_MENU, SCENEOBJT_NONE);
+	ut_assertnonnull(obj);
+	ut_asserteq(50, obj->dim.x);
+	ut_asserteq(400, obj->dim.y);
+	ut_asserteq(160, obj->dim.w);
+	ut_asserteq(160, obj->dim.h);
+
 	/* render it */
 	expo_set_scene_id(exp, SCENE1);
 	ut_assertok(expo_render(exp));
@@ -479,16 +532,16 @@ static int expo_render_image(struct unit_test_state *uts)
 
 	ut_assertok(expo_action_get(exp, &act));
 
-	ut_asserteq(EXPOACT_POINT, act.type);
+	ut_asserteq(EXPOACT_POINT_ITEM, act.type);
 	ut_asserteq(ITEM2, act.select.id);
 	ut_assertok(expo_render(exp));
 
 	/* make sure only the preview for the second item is shown */
 	obj = scene_obj_find(scn, ITEM1_PREVIEW, SCENEOBJT_NONE);
-	ut_asserteq(true, obj->hide);
+	ut_asserteq(true, obj->flags & SCENEOF_HIDE);
 
 	obj = scene_obj_find(scn, ITEM2_PREVIEW, SCENEOBJT_NONE);
-	ut_asserteq(false, obj->hide);
+	ut_asserteq(false, obj->flags & SCENEOF_HIDE);
 
 	/* select it */
 	ut_assertok(expo_send_key(exp, BKEY_SELECT));
@@ -504,7 +557,7 @@ static int expo_render_image(struct unit_test_state *uts)
 	ut_assert_console_end();
 
 	/* now try in text mode */
-	exp_set_text_mode(exp, true);
+	expo_set_text_mode(exp, true);
 	ut_assertok(expo_render(exp));
 
 	ut_assert_nextline("U-Boot    :    Boot Menu");
@@ -519,7 +572,7 @@ static int expo_render_image(struct unit_test_state *uts)
 
 	ut_assertok(expo_action_get(exp, &act));
 
-	ut_asserteq(EXPOACT_POINT, act.type);
+	ut_asserteq(EXPOACT_POINT_ITEM, act.type);
 	ut_asserteq(ITEM1, act.select.id);
 
 	ut_assertok(expo_render(exp));
@@ -537,3 +590,125 @@ static int expo_render_image(struct unit_test_state *uts)
 	return 0;
 }
 BOOTSTD_TEST(expo_render_image, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+
+/* Check building an expo from a devicetree description */
+static int expo_test_build(struct unit_test_state *uts)
+{
+	struct scene_obj_menu *menu;
+	struct scene_menitem *item;
+	struct scene_obj_txt *txt;
+	struct scene_obj *obj;
+	struct scene *scn;
+	struct expo *exp;
+	int count;
+	ofnode node;
+
+	node = ofnode_path("/cedit");
+	ut_assert(ofnode_valid(node));
+	ut_assertok(expo_build(node, &exp));
+
+	ut_asserteq_str("name", exp->name);
+	ut_asserteq(0, exp->scene_id);
+	ut_asserteq(ID_DYNAMIC_START + 20, exp->next_id);
+	ut_asserteq(false, exp->popup);
+
+	/* check the scene */
+	scn = expo_lookup_scene_id(exp, ID_SCENE1);
+	ut_assertnonnull(scn);
+	ut_asserteq_str("main", scn->name);
+	ut_asserteq(ID_SCENE1, scn->id);
+	ut_asserteq(ID_DYNAMIC_START + 1, scn->title_id);
+	ut_asserteq(0, scn->highlight_id);
+
+	/* check the title */
+	txt = scene_obj_find(scn, scn->title_id, SCENEOBJT_NONE);
+	ut_assertnonnull(txt);
+	obj = &txt->obj;
+	ut_asserteq_ptr(scn, obj->scene);
+	ut_asserteq_str("title", obj->name);
+	ut_asserteq(scn->title_id, obj->id);
+	ut_asserteq(SCENEOBJT_TEXT, obj->type);
+	ut_asserteq(0, obj->flags);
+	ut_asserteq_str("Test Configuration", expo_get_str(exp, txt->str_id));
+
+	/* check the menu */
+	menu = scene_obj_find(scn, ID_CPU_SPEED, SCENEOBJT_NONE);
+	obj = &menu->obj;
+	ut_asserteq_ptr(scn, obj->scene);
+	ut_asserteq_str("cpu-speed", obj->name);
+	ut_asserteq(ID_CPU_SPEED, obj->id);
+	ut_asserteq(SCENEOBJT_MENU, obj->type);
+	ut_asserteq(0, obj->flags);
+
+	txt = scene_obj_find(scn, menu->title_id, SCENEOBJT_NONE);
+	ut_asserteq_str("CPU speed", expo_get_str(exp, txt->str_id));
+
+	ut_asserteq(0, menu->cur_item_id);
+	ut_asserteq(0, menu->pointer_id);
+
+	/* check the items */
+	item = list_first_entry(&menu->item_head, struct scene_menitem,
+				sibling);
+	ut_asserteq_str("00", item->name);
+	ut_asserteq(ID_CPU_SPEED_1, item->id);
+	ut_asserteq(0, item->key_id);
+	ut_asserteq(0, item->desc_id);
+	ut_asserteq(0, item->preview_id);
+	ut_asserteq(0, item->flags);
+
+	txt = scene_obj_find(scn, item->label_id, SCENEOBJT_NONE);
+	ut_asserteq_str("2 GHz", expo_get_str(exp, txt->str_id));
+
+	count = 0;
+	list_for_each_entry(item, &menu->item_head, sibling)
+		count++;
+	ut_asserteq(3, count);
+
+	expo_destroy(exp);
+
+	return 0;
+}
+BOOTSTD_TEST(expo_test_build, UT_TESTF_DM);
+
+/* Check the cedit command */
+static int expo_cedit(struct unit_test_state *uts)
+{
+	extern struct expo *cur_exp;
+	struct scene_obj_menu *menu;
+	struct scene_obj_txt *txt;
+	struct expo *exp;
+	struct scene *scn;
+
+	if (!IS_ENABLED(CONFIG_CMD_CEDIT))
+		return -EAGAIN;
+
+	ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
+
+	console_record_reset_enable();
+
+	/*
+	 * ^N  Move down to second menu
+	 * ^M  Open menu
+	 * ^N  Move down to second item
+	 * ^M  Select item
+	 * \e  Quit
+	 */
+	console_in_puts("\x0e\x0d\x0e\x0d\e");
+	ut_assertok(run_command("cedit run", 0));
+
+	exp = cur_exp;
+	scn = expo_lookup_scene_id(exp, exp->scene_id);
+	ut_assertnonnull(scn);
+
+	menu = scene_obj_find(scn, scn->highlight_id, SCENEOBJT_NONE);
+	ut_assertnonnull(menu);
+
+	txt = scene_obj_find(scn, menu->title_id, SCENEOBJT_NONE);
+	ut_assertnonnull(txt);
+	ut_asserteq_str("AC Power", expo_get_str(exp, txt->str_id));
+
+	ut_asserteq(ID_AC_ON, menu->cur_item_id);
+
+	return 0;
+}
+BOOTSTD_TEST(expo_cedit, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
diff --git a/test/boot/files/expo_layout.dts b/test/boot/files/expo_layout.dts
new file mode 100644
index 0000000000..55d5c910dd
--- /dev/null
+++ b/test/boot/files/expo_layout.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Sample expo screen layout
+ */
+
+/dts-v1/;
+
+/*
+enum {
+	ZERO,
+	ID_PROMPT,
+
+	ID_SCENE1,
+	ID_SCENE1_TITLE,
+
+	ID_CPU_SPEED,
+	ID_CPU_SPEED_TITLE,
+	ID_CPU_SPEED_1,
+	ID_CPU_SPEED_2,
+	ID_CPU_SPEED_3,
+
+	ID_POWER_LOSS,
+	ID_AC_OFF,
+	ID_AC_ON,
+	ID_AC_MEMORY,
+
+	ID_DYNAMIC_START,
+};
+*/
+
+/ {
+	dynamic-start = <ID_DYNAMIC_START>;
+
+	scenes {
+		main {
+			id = <ID_SCENE1>;
+
+			/* value refers to the matching id in /strings */
+			title-id = <ID_SCENE1_TITLE>;
+
+			/* simple string is used as it is */
+			prompt = "UP and DOWN to choose, ENTER to select";
+
+			/* defines a menu within the scene */
+			cpu-speed {
+				type = "menu";
+				id = <ID_CPU_SPEED>;
+
+				/*
+				 * has both string and ID. The string is ignored
+				 * if the ID is present and points to a string
+				 */
+				title = "CPU speed";
+				title-id = <ID_CPU_SPEED_TITLE>;
+
+				/* menu items as simple strings */
+				item-label = "2 GHz", "2.5 GHz", "3 GHz";
+
+				/* IDs for the menu items */
+				item-id = <ID_CPU_SPEED_1 ID_CPU_SPEED_2
+					ID_CPU_SPEED_3>;
+			};
+
+			power-loss {
+				type = "menu";
+				id = <ID_POWER_LOSS>;
+
+				title = "AC Power";
+				item-label = "Always Off", "Always On",
+					"Memory";
+
+				item-id = <ID_AC_OFF ID_AC_ON ID_AC_MEMORY>;
+			};
+		};
+	};
+
+	strings {
+		title {
+			id = <ID_SCENE1_TITLE>;
+			value = "Test Configuration";
+			value-es = "configuración de prueba";
+		};
+	};
+};
diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index 055adc65a2..6e3d7e919e 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # Copyright (c) 2013 Google, Inc
+# Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
 
 ifdef CONFIG_HUSH_PARSER
 obj-$(CONFIG_CONSOLE_RECORD) += test_echo.o
@@ -10,6 +11,7 @@ obj-$(CONFIG_CMD_PAUSE) += test_pause.o
 endif
 obj-y += exit.o mem.o
 obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o
+obj-$(CONFIG_CMD_BDI) += bdinfo.o
 obj-$(CONFIG_CMD_FDT) += fdt.o
 obj-$(CONFIG_CONSOLE_TRUETYPE) += font.o
 obj-$(CONFIG_CMD_LOADM) += loadm.o
@@ -23,6 +25,7 @@ obj-$(CONFIG_CMD_SEAMA) += seama.o
 ifdef CONFIG_SANDBOX
 obj-$(CONFIG_CMD_READ) += rw.o
 obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
+obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o
 endif
 obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o
 obj-$(CONFIG_CMD_WGET) += wget.o
diff --git a/test/cmd/armffa.c b/test/cmd/armffa.c
new file mode 100644
index 0000000000..9a44a397e8
--- /dev/null
+++ b/test/cmd/armffa.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for armffa command
+ *
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <string.h>
+#include <asm/sandbox_arm_ffa.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+/* Basic test of 'armffa' command */
+static int dm_test_armffa_cmd(struct unit_test_state *uts)
+{
+	/* armffa getpart <UUID> */
+	ut_assertok(run_command("armffa getpart " SANDBOX_SERVICE1_UUID, 0));
+
+	/* armffa ping <ID> */
+	ut_assertok(run_commandf("armffa ping 0x%x", SANDBOX_SP1_ID));
+
+	/* armffa devlist */
+	ut_assertok(run_command("armffa devlist", 0));
+
+	return 0;
+}
+
+DM_TEST(dm_test_armffa_cmd, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c
new file mode 100644
index 0000000000..8c09281cac
--- /dev/null
+++ b/test/cmd/bdinfo.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Tests for bdinfo command
+ *
+ * Copyright 2023 Marek Vasut <marek.vasut+renesas@mailbox.org>
+ */
+
+#include <common.h>
+#include <console.h>
+#include <mapmem.h>
+#include <asm/global_data.h>
+#include <dm/uclass.h>
+#include <test/suites.h>
+#include <test/ut.h>
+#include <dm.h>
+#include <env.h>
+#include <lmb.h>
+#include <net.h>
+#include <serial.h>
+#include <video.h>
+#include <vsprintf.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <display_options.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Declare a new bdinfo test */
+#define BDINFO_TEST(_name, _flags)	UNIT_TEST(_name, _flags, bdinfo_test)
+
+static int test_num_l(struct unit_test_state *uts, const char *name,
+		      ulong value)
+{
+	ut_assert_nextline("%-12s= 0x%0*lx", name, 2 * (int)sizeof(value),
+			   value);
+
+	return 0;
+}
+
+static int test_num_ll(struct unit_test_state *uts, const char *name,
+		       unsigned long long value)
+{
+	ut_assert_nextline("%-12s= 0x%.*llx", name, 2 * (int)sizeof(ulong),
+			   value);
+
+	return 0;
+}
+
+static int test_eth(struct unit_test_state *uts)
+{
+	const int idx = eth_get_dev_index();
+	uchar enetaddr[6];
+	char name[10];
+	int ret;
+
+	if (idx)
+		sprintf(name, "eth%iaddr", idx);
+	else
+		strcpy(name, "ethaddr");
+
+	ret = eth_env_get_enetaddr_by_index("eth", idx, enetaddr);
+
+	ut_assert_nextline("current eth = %s", eth_get_name());
+	if (!ret)
+		ut_assert_nextline("%-12s= (not set)", name);
+	else
+		ut_assert_nextline("%-12s= %pM", name, enetaddr);
+	ut_assert_nextline("IP addr     = %s", env_get("ipaddr"));
+
+	return 0;
+}
+
+static int test_video_info(struct unit_test_state *uts)
+{
+	const struct udevice *dev;
+	struct uclass *uc;
+
+	uclass_id_foreach_dev(UCLASS_VIDEO, dev, uc) {
+		ut_assert_nextline("%-12s= %s %sactive", "Video", dev->name,
+				   device_active(dev) ? "" : "in");
+		if (device_active(dev)) {
+			struct video_priv *upriv = dev_get_uclass_priv(dev);
+			struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+
+			ut_assertok(test_num_ll(uts, "FB base",
+						(ulong)upriv->fb));
+			if (upriv->copy_fb) {
+				ut_assertok(test_num_ll(uts, "FB copy",
+							(ulong)upriv->copy_fb));
+				ut_assertok(test_num_l(uts, " copy size",
+						       plat->copy_size));
+			}
+			ut_assert_nextline("%-12s= %dx%dx%d", "FB size",
+					   upriv->xsize, upriv->ysize,
+					   1 << upriv->bpix);
+		}
+	}
+
+	return 0;
+}
+
+static int lmb_test_dump_region(struct unit_test_state *uts,
+				struct lmb_region *rgn, char *name)
+{
+	unsigned long long base, size, end;
+	enum lmb_flags flags;
+	int i;
+
+	ut_assert_nextline(" %s.cnt = 0x%lx / max = 0x%lx", name, rgn->cnt, rgn->max);
+
+	for (i = 0; i < rgn->cnt; i++) {
+		base = rgn->region[i].base;
+		size = rgn->region[i].size;
+		end = base + size - 1;
+		flags = rgn->region[i].flags;
+
+		ut_assert_nextline(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x",
+				   name, i, base, end, size, flags);
+	}
+
+	return 0;
+}
+
+static int lmb_test_dump_all(struct unit_test_state *uts, struct lmb *lmb)
+{
+	ut_assert_nextline("lmb_dump_all:");
+	lmb_test_dump_region(uts, &lmb->memory, "memory");
+	lmb_test_dump_region(uts, &lmb->reserved, "reserved");
+
+	return 0;
+}
+
+static int bdinfo_test_move(struct unit_test_state *uts)
+{
+	struct bd_info *bd = gd->bd;
+	int i;
+
+	/* Test moving the working BDINFO to a new location */
+	ut_assertok(console_record_reset_enable());
+	ut_assertok(run_commandf("bdinfo"));
+
+	ut_assertok(test_num_l(uts, "boot_params", 0));
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		if (bd->bi_dram[i].size) {
+			ut_assertok(test_num_l(uts, "DRAM bank", i));
+			ut_assertok(test_num_ll(uts, "-> start",
+						bd->bi_dram[i].start));
+			ut_assertok(test_num_ll(uts, "-> size",
+						bd->bi_dram[i].size));
+		}
+	}
+
+	/* CONFIG_SYS_HAS_SRAM testing not supported */
+	ut_assertok(test_num_l(uts, "flashstart", 0));
+	ut_assertok(test_num_l(uts, "flashsize", 0));
+	ut_assertok(test_num_l(uts, "flashoffset", 0));
+	ut_assert_nextline("baudrate    = %lu bps",
+			   env_get_ulong("baudrate", 10, 1234));
+	ut_assertok(test_num_l(uts, "relocaddr", gd->relocaddr));
+	ut_assertok(test_num_l(uts, "reloc off", gd->reloc_off));
+	ut_assert_nextline("%-12s= %u-bit", "Build", (uint)sizeof(void *) * 8);
+
+	if (IS_ENABLED(CONFIG_CMD_NET))
+		ut_assertok(test_eth(uts));
+
+	/*
+	 * Make sure environment variable "fdtcontroladdr" address
+	 * matches mapped control DT address.
+	 */
+	ut_assert(map_to_sysmem(gd->fdt_blob) == env_get_hex("fdtcontroladdr", 0x1234));
+	ut_assertok(test_num_l(uts, "fdt_blob",
+			       (ulong)map_to_sysmem(gd->fdt_blob)));
+	ut_assertok(test_num_l(uts, "new_fdt",
+			       (ulong)map_to_sysmem(gd->new_fdt)));
+	ut_assertok(test_num_l(uts, "fdt_size", (ulong)gd->fdt_size));
+
+	if (IS_ENABLED(CONFIG_VIDEO))
+		test_video_info(uts);
+
+	/* The gd->multi_dtb_fit may not be available, hence, #if below. */
+#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
+	ut_assertok(test_num_l(uts, "multi_dtb_fit", (ulong)gd->multi_dtb_fit));
+#endif
+
+	if (IS_ENABLED(CONFIG_LMB) && gd->fdt_blob) {
+		struct lmb lmb;
+
+		lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
+		lmb_test_dump_all(uts, &lmb);
+		if (IS_ENABLED(CONFIG_OF_REAL))
+			ut_assert_nextline("devicetree  = %s", fdtdec_get_srcname());
+	}
+
+	if (IS_ENABLED(CONFIG_DM_SERIAL)) {
+		struct serial_device_info info;
+
+		ut_assertnonnull(gd->cur_serial_dev);
+		ut_assertok(serial_getinfo(gd->cur_serial_dev, &info));
+
+		ut_assertok(test_num_l(uts, "serial addr", info.addr));
+		ut_assertok(test_num_l(uts, " width", info.reg_width));
+		ut_assertok(test_num_l(uts, " shift", info.reg_shift));
+		ut_assertok(test_num_l(uts, " offset", info.reg_offset));
+		ut_assertok(test_num_l(uts, " clock", info.clock));
+	}
+
+	if (IS_ENABLED(CONFIG_CMD_BDINFO_EXTRA)) {
+		ut_assert_nextlinen("stack ptr");
+		ut_assertok(test_num_ll(uts, "ram_top ptr",
+					(unsigned long long)gd->ram_top));
+		ut_assertok(test_num_l(uts, "malloc base", gd_malloc_start()));
+	}
+
+	ut_assertok(ut_check_console_end(uts));
+
+	return 0;
+}
+
+BDINFO_TEST(bdinfo_test_move, UT_TESTF_CONSOLE_REC);
+
+int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	struct unit_test *tests = UNIT_TEST_SUITE_START(bdinfo_test);
+	const int n_ents = UNIT_TEST_SUITE_COUNT(bdinfo_test);
+
+	return cmd_ut_category("bdinfo", "bdinfo_test_", tests, n_ents, argc, argv);
+}
diff --git a/test/cmd_ut.c b/test/cmd_ut.c
index d440da833a..0cb514490b 100644
--- a/test/cmd_ut.c
+++ b/test/cmd_ut.c
@@ -54,6 +54,9 @@ int cmd_ut_category(const char *name, const char *prefix,
 static struct cmd_tbl cmd_ut_sub[] = {
 	U_BOOT_CMD_MKENT(all, CONFIG_SYS_MAXARGS, 1, do_ut_all, "", ""),
 	U_BOOT_CMD_MKENT(info, 1, 1, do_ut_info, "", ""),
+#ifdef CONFIG_CMD_BDI
+	U_BOOT_CMD_MKENT(bdinfo, CONFIG_SYS_MAXARGS, 1, do_ut_bdinfo, "", ""),
+#endif
 #ifdef CONFIG_BOOTSTD
 	U_BOOT_CMD_MKENT(bootstd, CONFIG_SYS_MAXARGS, 1, do_ut_bootstd,
 			 "", ""),
@@ -176,6 +179,9 @@ static char ut_help_text[] =
 #ifdef CONFIG_CMD_ADDRMAP
 	"\naddrmap - very basic test of addrmap command"
 #endif
+#ifdef CONFIG_CMD_BDI
+	"\nbdinfo - bdinfo command"
+#endif
 #ifdef CONFIG_SANDBOX
 	"\nbloblist - bloblist implementation"
 #endif
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 3799b1ae8f..7ed00733c1 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # Copyright (c) 2013 Google, Inc
-# Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
 
 obj-$(CONFIG_UT_DM) += test-dm.o
 
@@ -92,6 +92,7 @@ obj-$(CONFIG_POWER_DOMAIN) += power-domain.o
 obj-$(CONFIG_ACPI_PMC) += pmc.o
 obj-$(CONFIG_DM_PMIC) += pmic.o
 obj-$(CONFIG_DM_PWM) += pwm.o
+obj-$(CONFIG_ARM_FFA_TRANSPORT) += ffa.o
 obj-$(CONFIG_QFW) += qfw.o
 obj-$(CONFIG_RAM) += ram.o
 obj-y += regmap.o
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 9634fc2e90..77eb524b59 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -11,10 +11,8 @@
 #include <dm.h>
 #include <malloc.h>
 #include <mapmem.h>
-#include <timestamp.h>
-#include <version.h>
 #include <tables_csum.h>
-#include <version.h>
+#include <version_string.h>
 #include <acpi/acpigen.h>
 #include <acpi/acpi_device.h>
 #include <acpi/acpi_table.h>
@@ -26,12 +24,12 @@
 
 #define BUF_SIZE		4096
 
-#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \
-		      (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \
-		      (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \
-		      ((U_BOOT_VERSION_NUM % 10) << 16) | \
-		      (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \
-		      ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \
+#define OEM_REVISION ((((version_num / 1000) % 10) << 28) | \
+		      (((version_num / 100) % 10) << 24) | \
+		      (((version_num / 10) % 10) << 20) | \
+		      ((version_num % 10) << 16) | \
+		      (((version_num_patch / 10) % 10) << 12) | \
+		      ((version_num_patch % 10) << 8) | \
 		      0x01)
 
 /**
@@ -611,3 +609,41 @@ static int dm_test_acpi_cmd_items(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_acpi_cmd_items, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/* Test 'acpi set' command */
+static int dm_test_acpi_cmd_set(struct unit_test_state *uts)
+{
+	struct acpi_ctx ctx;
+	ulong addr;
+	void *buf;
+
+	gd_set_acpi_start(0);
+
+	console_record_reset();
+	ut_asserteq(0, gd_acpi_start());
+	ut_assertok(run_command("acpi set", 0));
+	ut_assert_nextline("ACPI pointer: 0");
+
+	buf = memalign(16, BUF_SIZE);
+	ut_assertnonnull(buf);
+	addr = map_to_sysmem(buf);
+	ut_assertok(setup_ctx_and_base_tables(uts, &ctx, addr));
+
+	ut_assertok(acpi_write_dev_tables(&ctx));
+
+	ut_assertok(run_command("acpi set", 0));
+	ut_assert_nextline("ACPI pointer: %lx", addr);
+
+	ut_assertok(run_command("acpi set 0", 0));
+	ut_assert_nextline("Setting ACPI pointer to 0");
+	ut_asserteq(0, gd_acpi_start());
+
+	ut_assertok(run_commandf("acpi set %lx", addr));
+	ut_assert_nextline("Setting ACPI pointer to %lx", addr);
+	ut_asserteq(addr, gd_acpi_start());
+
+	ut_assert_console_end();
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_cmd_set, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
diff --git a/test/dm/ffa.c b/test/dm/ffa.c
new file mode 100644
index 0000000000..6912666bb4
--- /dev/null
+++ b/test/dm/ffa.c
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Functional tests for UCLASS_FFA  class
+ *
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <console.h>
+#include <dm.h>
+#include <asm/sandbox_arm_ffa.h>
+#include <asm/sandbox_arm_ffa_priv.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+/* Functional tests for the UCLASS_FFA */
+
+static int check_fwk_version(struct ffa_priv *uc_priv, struct unit_test_state *uts)
+{
+	struct ffa_sandbox_data func_data;
+	u32 fwk_version = 0;
+
+	func_data.data0 = &fwk_version;
+	func_data.data0_size = sizeof(fwk_version);
+	ut_assertok(sandbox_query_ffa_emul_state(FFA_VERSION, &func_data));
+	ut_asserteq(uc_priv->fwk_version, fwk_version);
+
+	return 0;
+}
+
+static int check_endpoint_id(struct ffa_priv *uc_priv, struct unit_test_state *uts)
+{
+	ut_asserteq(0, uc_priv->id);
+
+	return 0;
+}
+
+static int check_rxtxbuf(struct ffa_priv *uc_priv, struct unit_test_state *uts)
+{
+	ut_assertnonnull(uc_priv->pair.rxbuf);
+	ut_assertnonnull(uc_priv->pair.txbuf);
+
+	return 0;
+}
+
+static int check_features(struct ffa_priv *uc_priv, struct unit_test_state *uts)
+{
+	ut_assert(uc_priv->pair.rxtx_min_pages == RXTX_4K ||
+		  uc_priv->pair.rxtx_min_pages == RXTX_16K ||
+		  uc_priv->pair.rxtx_min_pages == RXTX_64K);
+
+	return 0;
+}
+
+static int check_rxbuf_mapped_flag(u32 queried_func_id,
+				   u8 rxbuf_mapped,
+				   struct unit_test_state *uts)
+{
+	switch (queried_func_id) {
+	case FFA_RXTX_MAP:
+		ut_asserteq(1, rxbuf_mapped);
+		break;
+	case FFA_RXTX_UNMAP:
+		ut_asserteq(0, rxbuf_mapped);
+		break;
+	default:
+		ut_assert(false);
+	}
+
+	return 0;
+}
+
+static int check_rxbuf_release_flag(u8 rxbuf_owned, struct unit_test_state *uts)
+{
+	ut_asserteq(0, rxbuf_owned);
+
+	return 0;
+}
+
+static int  test_ffa_msg_send_direct_req(u16 part_id, struct unit_test_state *uts)
+{
+	struct ffa_send_direct_data msg;
+	u8 cnt;
+	struct udevice *dev;
+
+	ut_assertok(uclass_first_device_err(UCLASS_FFA, &dev));
+
+	ut_assertok(ffa_sync_send_receive(dev, part_id, &msg, 1));
+
+	for (cnt = 0; cnt < sizeof(struct ffa_send_direct_data) / sizeof(u64); cnt++)
+		ut_asserteq_64(-1UL, ((u64 *)&msg)[cnt]);
+
+	return 0;
+}
+
+static int test_partitions_and_comms(const char *service_uuid,
+				     struct unit_test_state *uts)
+{
+	struct ffa_partition_desc *descs;
+	u32 count, i, j, valid_sps = 0;
+	struct udevice *dev;
+	struct ffa_sandbox_data func_data;
+	struct ffa_partitions *partitions;
+
+	ut_assertok(uclass_first_device_err(UCLASS_FFA, &dev));
+
+	/* Get from the driver the count and information of the SPs matching the UUID */
+	ut_assertok(ffa_partition_info_get(dev, service_uuid, &count, &descs));
+
+	/* Make sure the count is correct */
+	ut_asserteq(SANDBOX_SP_COUNT_PER_VALID_SERVICE, count);
+
+	/* SPs found , verify the partitions information */
+
+	func_data.data0 = &partitions;
+	func_data.data0_size = sizeof(struct ffa_partitions *);
+	ut_assertok(sandbox_query_ffa_emul_state(FFA_PARTITION_INFO_GET, &func_data));
+
+	for (i = 0; i < count ; i++) {
+		for (j = 0;
+		     j < partitions->count;
+		     j++) {
+			if (descs[i].info.id ==
+			   partitions->descs[j].info.id) {
+				valid_sps++;
+				ut_asserteq_mem(&descs[i],
+						&partitions->descs[j],
+						sizeof(struct ffa_partition_desc));
+				/* Send and receive data from the current partition */
+				test_ffa_msg_send_direct_req(descs[i].info.id, uts);
+			}
+		}
+	}
+
+	/* Verify expected partitions found in the emulated secure world */
+	ut_asserteq(SANDBOX_SP_COUNT_PER_VALID_SERVICE, valid_sps);
+
+	return 0;
+}
+
+static int dm_test_ffa_ack(struct unit_test_state *uts)
+{
+	struct ffa_priv *uc_priv;
+	struct ffa_sandbox_data func_data;
+	u8 rxbuf_flag = 0;
+	const char *svc1_uuid = SANDBOX_SERVICE1_UUID;
+	const char *svc2_uuid = SANDBOX_SERVICE2_UUID;
+	struct udevice *dev;
+
+	/* Test probing the sandbox FF-A bus */
+	ut_assertok(uclass_first_device_err(UCLASS_FFA, &dev));
+
+	/* Get a pointer to the sandbox FF-A bus private data */
+	uc_priv = dev_get_uclass_priv(dev);
+
+	/* Make sure the private data pointer is retrieved */
+	ut_assertnonnull(uc_priv);
+
+	/* Test FFA_VERSION */
+	check_fwk_version(uc_priv, uts);
+
+	/* Test FFA_ID_GET */
+	check_endpoint_id(uc_priv, uts);
+
+	/* Test FFA_FEATURES */
+	check_features(uc_priv, uts);
+
+	/*  Test RX/TX buffers */
+	check_rxtxbuf(uc_priv, uts);
+
+	/* Test FFA_RXTX_MAP */
+	func_data.data0 = &rxbuf_flag;
+	func_data.data0_size = sizeof(rxbuf_flag);
+
+	rxbuf_flag = 0;
+	sandbox_query_ffa_emul_state(FFA_RXTX_MAP, &func_data);
+	check_rxbuf_mapped_flag(FFA_RXTX_MAP, rxbuf_flag, uts);
+
+	/* FFA_PARTITION_INFO_GET / FFA_MSG_SEND_DIRECT_REQ */
+	test_partitions_and_comms(svc1_uuid, uts);
+
+	/* Test FFA_RX_RELEASE */
+	rxbuf_flag = 1;
+	sandbox_query_ffa_emul_state(FFA_RX_RELEASE, &func_data);
+	check_rxbuf_release_flag(rxbuf_flag, uts);
+
+	/* FFA_PARTITION_INFO_GET / FFA_MSG_SEND_DIRECT_REQ */
+	test_partitions_and_comms(svc2_uuid, uts);
+
+	/* Test FFA_RX_RELEASE */
+	rxbuf_flag = 1;
+	ut_assertok(sandbox_query_ffa_emul_state(FFA_RX_RELEASE, &func_data));
+	check_rxbuf_release_flag(rxbuf_flag, uts);
+
+	return 0;
+}
+
+DM_TEST(dm_test_ffa_ack, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+
+static int dm_test_ffa_nack(struct unit_test_state *uts)
+{
+	struct ffa_priv *uc_priv;
+	const char *valid_svc_uuid = SANDBOX_SERVICE1_UUID;
+	const char *unvalid_svc_uuid = SANDBOX_SERVICE3_UUID;
+	const char *unvalid_svc_uuid_str = SANDBOX_SERVICE4_UUID;
+	struct ffa_send_direct_data msg;
+	int ret;
+	u32 count;
+	u16 part_id = 0;
+	struct udevice *dev;
+	struct ffa_partition_desc *descs = NULL;
+
+	/* Test probing the sandbox FF-A bus */
+	ut_assertok(uclass_first_device_err(UCLASS_FFA, &dev));
+
+	/* Get a pointer to the sandbox FF-A bus private data */
+	uc_priv = dev_get_uclass_priv(dev);
+
+	/* Make sure the private data pointer is retrieved */
+	ut_assertnonnull(uc_priv);
+
+	/* Query partitions count using  invalid arguments */
+	ret = ffa_partition_info_get(dev, NULL, NULL, NULL);
+	ut_asserteq(-EINVAL, ret);
+	ret = ffa_partition_info_get(dev, unvalid_svc_uuid, NULL, NULL);
+	ut_asserteq(-EINVAL, ret);
+	ret = ffa_partition_info_get(dev, unvalid_svc_uuid, &count, NULL);
+	ut_asserteq(-EINVAL, ret);
+
+	/* Query partitions count using an invalid UUID  string */
+	ret = ffa_partition_info_get(dev, unvalid_svc_uuid_str, &count, &descs);
+	ut_asserteq(-EINVAL, ret);
+
+	/* Query partitions count using an invalid UUID (no matching SP) */
+	count = 0;
+	ret = ffa_partition_info_get(dev, unvalid_svc_uuid, &count, &descs);
+	ut_asserteq(0, count);
+
+	/* Query partitions data using a valid UUID */
+	count = 0;
+	ut_assertok(ffa_partition_info_get(dev, valid_svc_uuid, &count, &descs));
+	/* Make sure partitions are detected */
+	ut_asserteq(SANDBOX_SP_COUNT_PER_VALID_SERVICE, count);
+	ut_assertnonnull(descs);
+
+	/* Send data to an invalid partition */
+	ret = ffa_sync_send_receive(dev, part_id, &msg, 1);
+	ut_asserteq(-EINVAL, ret);
+
+	/* Send data to a valid partition */
+	part_id = uc_priv->partitions.descs[0].info.id;
+	ut_assertok(ffa_sync_send_receive(dev, part_id, &msg, 1));
+
+	return 0;
+}
+
+DM_TEST(dm_test_ffa_nack, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
diff --git a/test/dm/fwu_mdata.c b/test/dm/fwu_mdata.c
index b179a65c15..8b5c83ef4e 100644
--- a/test/dm/fwu_mdata.c
+++ b/test/dm/fwu_mdata.c
@@ -98,7 +98,7 @@ static int dm_test_fwu_mdata_read(struct unit_test_state *uts)
 	ut_assertok(populate_mmc_disk_image(uts));
 	ut_assertok(write_mmc_blk_device(uts));
 
-	ut_assertok(fwu_get_mdata(dev, &mdata));
+	ut_assertok(fwu_get_mdata(&mdata));
 
 	ut_asserteq(mdata.version, 0x1);
 
@@ -118,30 +118,14 @@ static int dm_test_fwu_mdata_write(struct unit_test_state *uts)
 
 	ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev));
 
-	ut_assertok(fwu_get_mdata(dev, &mdata));
+	ut_assertok(fwu_get_mdata(&mdata));
 
 	active_idx = (mdata.active_index + 1) % CONFIG_FWU_NUM_BANKS;
 	ut_assertok(fwu_set_active_index(active_idx));
 
-	ut_assertok(fwu_get_mdata(dev, &mdata));
+	ut_assertok(fwu_get_mdata(&mdata));
 	ut_asserteq(mdata.active_index, active_idx);
 
 	return 0;
 }
 DM_TEST(dm_test_fwu_mdata_write, UT_TESTF_SCAN_FDT);
-
-static int dm_test_fwu_mdata_check(struct unit_test_state *uts)
-{
-	struct udevice *dev;
-
-	ut_assertok(setup_blk_device(uts));
-	ut_assertok(populate_mmc_disk_image(uts));
-	ut_assertok(write_mmc_blk_device(uts));
-
-	ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev));
-
-	ut_assertok(fwu_check_mdata_validity());
-
-	return 0;
-}
-DM_TEST(dm_test_fwu_mdata_check, UT_TESTF_SCAN_FDT);
diff --git a/test/dm/nvmxip.c b/test/dm/nvmxip.c
index e934748eb5..89bf481f61 100644
--- a/test/dm/nvmxip.c
+++ b/test/dm/nvmxip.c
@@ -17,7 +17,7 @@
 #include <linux/bitops.h>
 #include <test/test.h>
 #include <test/ut.h>
-#include "../../drivers/mtd/nvmxip/nvmxip.h"
+#include <nvmxip.h>
 
 /* NVMXIP devices described in the device tree */
 #define SANDBOX_NVMXIP_DEVICES 2
diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
index 473a8cef57..6fbebc7da0 100644
--- a/test/dm/ofnode.c
+++ b/test/dm/ofnode.c
@@ -1240,3 +1240,48 @@ static int dm_test_ofnode_copy_props_ot(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_ofnode_copy_props_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+
+/* check that the livetree is aligned to a structure boundary */
+static int dm_test_livetree_align(struct unit_test_state *uts)
+{
+	const int align = __alignof__(struct unit_test_state);
+	struct device_node *node;
+	u32 *sentinel;
+	ulong start;
+
+	start = (ulong)gd_of_root();
+	ut_asserteq(start, ALIGN(start, align));
+
+	node = gd_of_root();
+	sentinel = (void *)node - sizeof(u32);
+
+	/*
+	 * The sentinel should be overwritten with the root node. If it isn't,
+	 * then the root node is not at the very start of the livetree memory
+	 * area, and free(root) will fail to free the memory used by the
+	 * livetree.
+	 */
+	ut_assert(*sentinel != BAD_OF_ROOT);
+
+	return 0;
+}
+DM_TEST(dm_test_livetree_align, UT_TESTF_LIVE_TREE);
+
+/* check that it is possible to load an arbitrary livetree */
+static int dm_test_livetree_ensure(struct unit_test_state *uts)
+{
+	oftree tree;
+	ofnode node;
+
+	/* read from other.dtb */
+	ut_assertok(test_load_other_fdt(uts));
+	tree = oftree_from_fdt(uts->other_fdt);
+	ut_assert(oftree_valid(tree));
+	node = oftree_path(tree, "/node/subnode");
+	ut_assert(ofnode_valid(node));
+	ut_asserteq_str("sandbox-other2",
+			ofnode_read_string(node, "compatible"));
+
+	return 0;
+}
+DM_TEST(dm_test_livetree_ensure, 0);
diff --git a/test/dm/part.c b/test/dm/part.c
index 35e99eeb01..d6e4345812 100644
--- a/test/dm/part.c
+++ b/test/dm/part.c
@@ -17,10 +17,12 @@ static int do_test(struct unit_test_state *uts, int expected,
 	struct blk_desc *mmc_dev_desc;
 	struct disk_partition part_info;
 
-	ut_asserteq(expected,
-		    part_get_info_by_dev_and_name_or_num("mmc", part_str,
-							 &mmc_dev_desc,
-							 &part_info, whole));
+	int ret = part_get_info_by_dev_and_name_or_num("mmc", part_str,
+						       &mmc_dev_desc,
+						       &part_info, whole);
+
+	ut_assertf(expected == ret, "test(%d, \"%s\", %d) == %d", expected,
+		   part_str, whole, ret);
 	return 0;
 }
 
@@ -76,15 +78,15 @@ static int dm_test_part(struct unit_test_state *uts)
 	test(-EINVAL, "#test1", true);
 	test(1, "2", false);
 	test(1, "2", true);
-	test(-ENOENT, "1:0", false);
-	test(0, "1:0", true);
-	test(1, "1:1", false);
-	test(2, "1:2", false);
-	test(1, "1.0", false);
-	test(0, "1.0:0", true);
-	test(1, "1.0:1", false);
-	test(2, "1.0:2", false);
-	test(-EINVAL, "1#bogus", false);
+	test(-ENOENT, "2:0", false);
+	test(0, "2:0", true);
+	test(1, "2:1", false);
+	test(2, "2:2", false);
+	test(1, "2.0", false);
+	test(0, "2.0:0", true);
+	test(1, "2.0:1", false);
+	test(2, "2.0:2", false);
+	test(-EINVAL, "2#bogus", false);
 	test(1, "2#test1", false);
 	test(2, "2#test2", false);
 	ret = 0;
@@ -106,3 +108,90 @@ static int dm_test_part_bootable(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_part_bootable, UT_TESTF_SCAN_FDT);
+
+static int do_get_info_test(struct unit_test_state *uts,
+			    struct blk_desc *dev_desc, int part, int part_type,
+			    struct disk_partition const *reference)
+{
+	struct disk_partition p;
+	int ret;
+
+	memset(&p, 0, sizeof(p));
+
+	ret = part_get_info_by_type(dev_desc, part, part_type, &p);
+	printf("part_get_info_by_type(%d, 0x%x) = %d\n", part, part_type, ret);
+	if (ut_assertok(ret)) {
+		return 0;
+	}
+
+	ut_asserteq(reference->start, p.start);
+	ut_asserteq(reference->size, p.size);
+	ut_asserteq(reference->sys_ind, p.sys_ind);
+
+	return 0;
+}
+
+static int dm_test_part_get_info_by_type(struct unit_test_state *uts)
+{
+	char str_disk_guid[UUID_STR_LEN + 1];
+	struct blk_desc *mmc_dev_desc;
+	struct disk_partition gpt_parts[] = {
+		{
+			.start = 48, /* GPT data takes up the first 34 blocks or so */
+			.size = 1,
+			.name = "test1",
+			.sys_ind = 0,
+		},
+		{
+			.start = 49,
+			.size = 1,
+			.name = "test2",
+			.sys_ind = 0,
+		},
+	};
+	struct disk_partition mbr_parts[] = {
+		{
+			.start = 1,
+			.size = 33,
+			.name = "gpt",
+			.sys_ind = EFI_PMBR_OSTYPE_EFI_GPT,
+		},
+		{
+			.start = 48,
+			.size = 1,
+			.name = "test1",
+			.sys_ind = 0x83,
+		},
+	};
+
+	ut_asserteq(2, blk_get_device_by_str("mmc", "2", &mmc_dev_desc));
+	if (CONFIG_IS_ENABLED(RANDOM_UUID)) {
+		gen_rand_uuid_str(gpt_parts[0].uuid, UUID_STR_FORMAT_STD);
+		gen_rand_uuid_str(gpt_parts[1].uuid, UUID_STR_FORMAT_STD);
+		gen_rand_uuid_str(str_disk_guid, UUID_STR_FORMAT_STD);
+	}
+	ut_assertok(gpt_restore(mmc_dev_desc, str_disk_guid, gpt_parts,
+				ARRAY_SIZE(gpt_parts)));
+
+	ut_assertok(write_mbr_partitions(mmc_dev_desc, mbr_parts,
+					 ARRAY_SIZE(mbr_parts), 0));
+
+#define get_info_test(_part, _part_type, _reference) \
+	ut_assertok(do_get_info_test(uts, mmc_dev_desc, _part, _part_type, \
+				     _reference))
+
+	for (int i = 0; i < ARRAY_SIZE(gpt_parts); i++) {
+		get_info_test(i + 1, PART_TYPE_UNKNOWN, &gpt_parts[i]);
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(mbr_parts); i++) {
+		get_info_test(i + 1, PART_TYPE_DOS, &mbr_parts[i]);
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(gpt_parts); i++) {
+		get_info_test(i + 1, PART_TYPE_EFI, &gpt_parts[i]);
+	}
+
+	return 0;
+}
+DM_TEST(dm_test_part_get_info_by_type, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
diff --git a/test/dm/video.c b/test/dm/video.c
index 30778157d9..d907f68160 100644
--- a/test/dm/video.c
+++ b/test/dm/video.c
@@ -15,6 +15,7 @@
 #include <video.h>
 #include <video_console.h>
 #include <asm/test.h>
+#include <asm/sdl.h>
 #include <dm/test.h>
 #include <dm/uclass-internal.h>
 #include <test/test.h>
@@ -556,7 +557,7 @@ static int dm_test_video_truetype(struct unit_test_state *uts)
 	ut_assertok(video_get_nologo(uts, &dev));
 	ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
 	vidconsole_put_string(con, test_string);
-	ut_asserteq(12237, compress_frame_buffer(uts, dev));
+	ut_asserteq(12174, compress_frame_buffer(uts, dev));
 
 	return 0;
 }
@@ -577,7 +578,7 @@ static int dm_test_video_truetype_scroll(struct unit_test_state *uts)
 	ut_assertok(video_get_nologo(uts, &dev));
 	ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
 	vidconsole_put_string(con, test_string);
-	ut_asserteq(35030, compress_frame_buffer(uts, dev));
+	ut_asserteq(34287, compress_frame_buffer(uts, dev));
 
 	return 0;
 }
@@ -598,7 +599,7 @@ static int dm_test_video_truetype_bs(struct unit_test_state *uts)
 	ut_assertok(video_get_nologo(uts, &dev));
 	ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
 	vidconsole_put_string(con, test_string);
-	ut_asserteq(29018, compress_frame_buffer(uts, dev));
+	ut_asserteq(29471, compress_frame_buffer(uts, dev));
 
 	return 0;
 }
diff --git a/test/lib/Makefile b/test/lib/Makefile
index e0bd9e04e8..e75a263e6a 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_AES) += test_aes.o
 obj-$(CONFIG_GETOPT) += getopt.o
 obj-$(CONFIG_CRC8) += test_crc8.o
 obj-$(CONFIG_UT_LIB_CRYPT) += test_crypt.o
+obj-$(CONFIG_LIB_UUID) += uuid.o
 else
 obj-$(CONFIG_SANDBOX) += kconfig_spl.o
 endif
diff --git a/test/lib/uuid.c b/test/lib/uuid.c
new file mode 100644
index 0000000000..e24331a136
--- /dev/null
+++ b/test/lib/uuid.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Functional tests for UCLASS_FFA  class
+ *
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <uuid.h>
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+/* test UUID */
+#define TEST_SVC_UUID	"ed32d533-4209-99e6-2d72-cdd998a79cc0"
+
+#define UUID_SIZE 16
+
+/* The UUID binary data (little-endian format) */
+static const u8 ref_uuid_bin[UUID_SIZE] = {
+	0x33, 0xd5, 0x32, 0xed,
+	0x09, 0x42, 0xe6, 0x99,
+	0x72, 0x2d, 0xc0, 0x9c,
+	0xa7, 0x98, 0xd9, 0xcd
+};
+
+static int lib_test_uuid_to_le(struct unit_test_state *uts)
+{
+	const char *uuid_str = TEST_SVC_UUID;
+	u8 ret_uuid_bin[UUID_SIZE] = {0};
+
+	ut_assertok(uuid_str_to_le_bin(uuid_str, ret_uuid_bin));
+	ut_asserteq_mem(ref_uuid_bin, ret_uuid_bin, UUID_SIZE);
+
+	return 0;
+}
+
+LIB_TEST(lib_test_uuid_to_le, 0);
diff --git a/test/py/requirements.txt b/test/py/requirements.txt
index 86d6266053..f7e76bdb91 100644
--- a/test/py/requirements.txt
+++ b/test/py/requirements.txt
@@ -20,8 +20,8 @@ pytest==6.2.5
 pytest-xdist==2.5.0
 python-mimeparse==1.6.0
 python-subunit==1.3.0
-requests==2.27.1
-setuptools==58.3.0
+requests==2.31.0
+setuptools==65.5.1
 six==1.16.0
 testtools==2.3.0
 traceback2==1.4.0
diff --git a/test/py/tests/test_android/test_avb.py b/test/py/tests/test_android/test_avb.py
index bc5c5b5582..238b48c90f 100644
--- a/test/py/tests/test_android/test_avb.py
+++ b/test/py/tests/test_android/test_avb.py
@@ -5,7 +5,7 @@
 # Android Verified Boot 2.0 Test
 
 """
-This tests Android Verified Boot 2.0 support in U-boot:
+This tests Android Verified Boot 2.0 support in U-Boot:
 
 For additional details about how to build proper vbmeta partition
 check doc/android/avb2.rst
diff --git a/test/py/tests/test_cat/conftest.py b/test/py/tests/test_cat/conftest.py
index 058fe52352..320e7ebd29 100644
--- a/test/py/tests/test_cat/conftest.py
+++ b/test/py/tests/test_cat/conftest.py
@@ -13,7 +13,7 @@ def cat_data(u_boot_config):
     """Set up a file system to be used in cat tests
 
     Args:
-        u_boot_config -- U-boot configuration.
+        u_boot_config -- U-Boot configuration.
     """
     mnt_point = u_boot_config.persistent_data_dir + '/test_cat'
     image_path = u_boot_config.persistent_data_dir + '/cat.img'
@@ -32,4 +32,5 @@ def cat_data(u_boot_config):
         pytest.skip('Setup failed')
     finally:
         shutil.rmtree(mnt_point)
-        os.remove(image_path)
+        if os.path.exists(image_path):
+            os.remove(image_path)
diff --git a/test/py/tests/test_cleanup_build.py b/test/py/tests/test_cleanup_build.py
new file mode 100644
index 0000000000..5206ff73ec
--- /dev/null
+++ b/test/py/tests/test_cleanup_build.py
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2023 Tobias Deiminger <tdmg@linutronix.de>
+
+"""Test for unexpected leftovers after make clean"""
+
+import itertools
+import os
+import pathlib
+import shutil
+import sys
+
+import pytest
+
+# pylint: disable=redefined-outer-name
+
+
+@pytest.fixture
+def tmp_copy_of_builddir(u_boot_config, tmp_path):
+    """For each test, provide a temporary copy of the initial build directory."""
+    shutil.copytree(
+        u_boot_config.build_dir,
+        tmp_path,
+        symlinks=True,
+        dirs_exist_ok=True,
+    )
+    return tmp_path
+
+
+@pytest.fixture(scope="module")
+def run_make(u_boot_log):
+    """Provide function to run and log make without connecting to u-boot console."""
+    runner = u_boot_log.get_runner("make", sys.stdout)
+
+    def _run_make(build_dir, target):
+        cmd = ["make", f"O={build_dir}", target]
+        runner.run(cmd)
+
+    yield _run_make
+    runner.close()
+
+
+@pytest.fixture(scope="module")
+def most_generated_files():
+    """Path.glob style patterns to describe what should be removed by 'make clean'."""
+    return (
+        "**/*.c",
+        "**/*.dtb",
+        "**/*.dtbo",
+        "**/*.o",
+        "**/*.py",
+        "**/*.pyc",
+        "**/*.so",
+        "**/*.srec",
+        "u-boot*",
+        "[svt]pl/u-boot*",
+    )
+
+
+@pytest.fixture(scope="module")
+def all_generated_files(most_generated_files):
+    """Path.glob style patterns to describe what should be removed by 'make mrproper'."""
+    return most_generated_files + (".config", "**/*.h")
+
+
+def find_files(search_dir, include_patterns, exclude_dirs=None):
+    """Find files matching include_patterns, unless it's in one of exclude_dirs.
+
+    include_patterns -- Path.glob style pattern relative to search dir
+    exclude_dir -- directories to exclude, expected relative to search dir
+    """
+    matches = []
+    exclude_dirs = [] if exclude_dirs is None else exclude_dirs
+    for abs_path in itertools.chain.from_iterable(
+        pathlib.Path(search_dir).glob(pattern) for pattern in include_patterns
+    ):
+        if abs_path.is_dir():
+            continue
+        rel_path = pathlib.Path(os.path.relpath(abs_path, search_dir))
+        if not any(
+            rel_path.is_relative_to(exclude_dir) for exclude_dir in exclude_dirs
+        ):
+            matches.append(rel_path)
+    return matches
+
+
+def test_clean(run_make, tmp_copy_of_builddir, most_generated_files):
+    """Test if 'make clean' deletes most generated files."""
+    run_make(tmp_copy_of_builddir, "clean")
+    leftovers = find_files(
+        tmp_copy_of_builddir,
+        most_generated_files,
+        exclude_dirs=["scripts", "test/overlay"],
+    )
+    assert not leftovers, f"leftovers: {', '.join(map(str, leftovers))}"
+
+
+def test_mrproper(run_make, tmp_copy_of_builddir, all_generated_files):
+    """Test if 'make mrproper' deletes current configuration and all generated files."""
+    run_make(tmp_copy_of_builddir, "mrproper")
+    leftovers = find_files(
+        tmp_copy_of_builddir,
+        all_generated_files,
+        exclude_dirs=["test/overlay"],
+    )
+    assert not leftovers, f"leftovers: {', '.join(map(str, leftovers))}"
diff --git a/test/py/tests/test_efi_bootmgr/conftest.py b/test/py/tests/test_efi_bootmgr/conftest.py
index eabafa5429..0eca025058 100644
--- a/test/py/tests/test_efi_bootmgr/conftest.py
+++ b/test/py/tests/test_efi_bootmgr/conftest.py
@@ -12,7 +12,7 @@ def efi_bootmgr_data(u_boot_config):
     """Set up a file system to be used in UEFI bootmanager tests.
 
     Args:
-        u_boot_config -- U-boot configuration.
+        u_boot_config -- U-Boot configuration.
 
     Return:
         A path to disk image to be used for testing
diff --git a/test/py/tests/test_efi_capsule/capsule_common.py b/test/py/tests/test_efi_capsule/capsule_common.py
new file mode 100644
index 0000000000..fc0d851c61
--- /dev/null
+++ b/test/py/tests/test_efi_capsule/capsule_common.py
@@ -0,0 +1,142 @@
+# SPDX-License-Identifier:      GPL-2.0+
+# Copyright (c) 2023, Linaro Limited
+
+
+"""Common function for UEFI capsule test."""
+
+from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
+
+def capsule_setup(u_boot_console, disk_img, osindications):
+    """setup the test
+
+    Args:
+        u_boot_console -- A console connection to U-Boot.
+        disk_img -- A path to disk image to be used for testing.
+        osindications -- String of osindications value.
+    """
+    u_boot_console.run_command_list([
+        f'host bind 0 {disk_img}',
+        'printenv -e PlatformLangCodes', # workaround for terminal size determination
+        'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
+        'efidebug boot order 1',
+        'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
+        'u-boot-env raw 0x150000 0x200000"'])
+
+    if osindications is None:
+        u_boot_console.run_command('env set -e OsIndications')
+    else:
+        u_boot_console.run_command(f'env set -e -nv -bs -rt OsIndications ={osindications}')
+
+    u_boot_console.run_command('env save')
+
+def init_content(u_boot_console, target, filename, expected):
+    """initialize test content
+
+    Args:
+        u_boot_console -- A console connection to U-Boot.
+        target -- Target address to place the content.
+        filename -- File name of the content.
+        expected -- Expected string of the content.
+    """
+    output = u_boot_console.run_command_list([
+        'sf probe 0:0',
+        f'fatload host 0:1 4000000 {CAPSULE_DATA_DIR}/{filename}',
+        f'sf write 4000000 {target} 10',
+        'sf read 5000000 100000 10',
+        'md.b 5000000 10'])
+    assert expected in ''.join(output)
+
+def place_capsule_file(u_boot_console, filenames):
+    """place the capsule file
+
+    Args:
+        u_boot_console -- A console connection to U-Boot.
+        filenames -- File name array of the target capsule files.
+    """
+    for name in filenames:
+        u_boot_console.run_command_list([
+            f'fatload host 0:1 4000000 {CAPSULE_DATA_DIR}/{name}',
+            f'fatwrite host 0:1 4000000 {CAPSULE_INSTALL_DIR}/{name} $filesize'])
+
+    output = u_boot_console.run_command(f'fatls host 0:1 {CAPSULE_INSTALL_DIR}')
+    for name in filenames:
+        assert name in ''.join(output)
+
+def exec_manual_update(u_boot_console, disk_img, filenames, need_reboot = True):
+    """execute capsule update manually
+
+    Args:
+        u_boot_console -- A console connection to U-Boot.
+        disk_img -- A path to disk image to be used for testing.
+        filenames -- File name array of the target capsule files.
+        need_reboot -- Flag indicates whether system reboot is required.
+    """
+    # make sure that dfu_alt_info exists even persistent variables
+    # are not available.
+    output = u_boot_console.run_command_list([
+        'env set dfu_alt_info '
+                '"sf 0:0=u-boot-bin raw 0x100000 0x50000;'
+                'u-boot-env raw 0x150000 0x200000"',
+        f'host bind 0 {disk_img}',
+        f'fatls host 0:1 {CAPSULE_INSTALL_DIR}'])
+    for name in filenames:
+        assert name in ''.join(output)
+
+    # need to run uefi command to initiate capsule handling
+    u_boot_console.run_command(
+        'env print -e Capsule0000', wait_for_reboot = need_reboot)
+
+def check_file_removed(u_boot_console, disk_img, filenames):
+    """check files are removed
+
+    Args:
+        u_boot_console -- A console connection to U-Boot.
+        disk_img -- A path to disk image to be used for testing.
+        filenames -- File name array of the target capsule files.
+    """
+    output = u_boot_console.run_command_list([
+        f'host bind 0 {disk_img}',
+        f'fatls host 0:1 {CAPSULE_INSTALL_DIR}'])
+    for name in filenames:
+        assert name not in ''.join(output)
+
+def check_file_exist(u_boot_console, disk_img, filenames):
+    """check files exist
+
+    Args:
+        u_boot_console -- A console connection to U-Boot.
+        disk_img -- A path to disk image to be used for testing.
+        filenames -- File name array of the target capsule files.
+    """
+    output = u_boot_console.run_command_list([
+        f'host bind 0 {disk_img}',
+        f'fatls host 0:1 {CAPSULE_INSTALL_DIR}'])
+    for name in filenames:
+        assert name in ''.join(output)
+
+def verify_content(u_boot_console, target, expected):
+    """verify the content
+
+    Args:
+        u_boot_console -- A console connection to U-Boot.
+        target -- Target address to verify.
+        expected -- Expected string of the content.
+    """
+    output = u_boot_console.run_command_list([
+        'sf probe 0:0',
+        f'sf read 4000000 {target} 10',
+        'md.b 4000000 10'])
+    assert expected in ''.join(output)
+
+def do_reboot_dtb_specified(u_boot_config, u_boot_console, dtb_filename):
+    """do reboot with specified DTB
+
+    Args:
+        u_boot_config -- U-boot configuration.
+        u_boot_console -- A console connection to U-Boot.
+        dtb_filename -- DTB file name.
+    """
+    mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
+    u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
+                                + f'/{dtb_filename}'
+    u_boot_console.restart_uboot()
diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py
index a337e62936..054be1ee97 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -17,7 +17,7 @@ def efi_capsule_data(request, u_boot_config):
     for testing.
 
     request -- Pytest request object.
-    u_boot_config -- U-boot configuration.
+    u_boot_config -- U-Boot configuration.
     """
     mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
     data_dir = mnt_point + CAPSULE_DATA_DIR
@@ -62,6 +62,23 @@ def efi_capsule_data(request, u_boot_config):
                             '-out SIGNER2.crt -nodes -days 365'
                        % data_dir, shell=True)
 
+        # Update dtb to add the version information
+        check_call('cd %s; '
+                   'cp %s/test/py/tests/test_efi_capsule/version.dts .'
+                   % (data_dir, u_boot_config.source_dir), shell=True)
+        if capsule_auth_enabled:
+            check_call('cd %s; '
+                       'dtc -@ -I dts -O dtb -o version.dtbo version.dts; '
+                       'fdtoverlay -i test_sig.dtb '
+                            '-o test_ver.dtb version.dtbo'
+                       % (data_dir), shell=True)
+        else:
+            check_call('cd %s; '
+                       'dtc -@ -I dts -O dtb -o version.dtbo version.dts; '
+                       'fdtoverlay -i %s/arch/sandbox/dts/test.dtb '
+                            '-o test_ver.dtb version.dtbo'
+                       % (data_dir, u_boot_config.build_dir), shell=True)
+
         # Create capsule files
         # two regions: one for u-boot.bin and the other for u-boot.env
         check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old > u-boot.env.old; echo -n u-boot-env:New > u-boot.env.new' % data_dir,
@@ -87,6 +104,26 @@ def efi_capsule_data(request, u_boot_config):
         check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid  058B7D83-50D5-4C47-A195-60D86AD341C4 uboot_bin_env.itb Test05' %
                    (data_dir, u_boot_config.build_dir),
                    shell=True)
+        check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 5 '
+                        '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test101' %
+                   (data_dir, u_boot_config.build_dir),
+                   shell=True)
+        check_call('cd %s; %s/tools/mkeficapsule --index 2 --fw-version 10 '
+                        '--guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 u-boot.env.new Test102' %
+                   (data_dir, u_boot_config.build_dir),
+                   shell=True)
+        check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 2 '
+                        '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test103' %
+                   (data_dir, u_boot_config.build_dir),
+                   shell=True)
+        check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 5 '
+                        '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test104' %
+                   (data_dir, u_boot_config.build_dir),
+                   shell=True)
+        check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 2 '
+                        '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test105' %
+                   (data_dir, u_boot_config.build_dir),
+                   shell=True)
 
         if capsule_auth_enabled:
             # raw firmware signed with proper key
@@ -123,6 +160,51 @@ def efi_capsule_data(request, u_boot_config):
                             'uboot_bin_env.itb Test14'
                        % (data_dir, u_boot_config.build_dir),
                        shell=True)
+            # raw firmware signed with proper key with version information
+            check_call('cd %s; '
+                       '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+                            '--fw-version 5 '
+                            '--private-key SIGNER.key --certificate SIGNER.crt '
+                            '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
+                            'u-boot.bin.new Test111'
+                       % (data_dir, u_boot_config.build_dir),
+                       shell=True)
+            # raw firmware signed with proper key with version information
+            check_call('cd %s; '
+                       '%s/tools/mkeficapsule --index 2 --monotonic-count 1 '
+                            '--fw-version 10 '
+                            '--private-key SIGNER.key --certificate SIGNER.crt '
+                            '--guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 '
+                            'u-boot.env.new Test112'
+                       % (data_dir, u_boot_config.build_dir),
+                       shell=True)
+            # raw firmware signed with proper key with lower version information
+            check_call('cd %s; '
+                       '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+                            '--fw-version 2 '
+                            '--private-key SIGNER.key --certificate SIGNER.crt '
+                            '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
+                            'u-boot.bin.new Test113'
+                       % (data_dir, u_boot_config.build_dir),
+                       shell=True)
+            # FIT firmware signed with proper key with version information
+            check_call('cd %s; '
+                       '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+                            '--fw-version 5 '
+                            '--private-key SIGNER.key --certificate SIGNER.crt '
+                            '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 '
+                            'uboot_bin_env.itb Test114'
+                       % (data_dir, u_boot_config.build_dir),
+                       shell=True)
+            # FIT firmware signed with proper key with lower version information
+            check_call('cd %s; '
+                       '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+                            '--fw-version 2 '
+                            '--private-key SIGNER.key --certificate SIGNER.crt '
+                            '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 '
+                            'uboot_bin_env.itb Test115'
+                       % (data_dir, u_boot_config.build_dir),
+                       shell=True)
 
         # Create a disk image with EFI system partition
         check_call('virt-make-fs --partition=gpt --size=+1M --type=vfat %s %s' %
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
index 9ee152818d..11bcdc2bb2 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
@@ -7,8 +7,15 @@ This test verifies capsule-on-disk firmware update for FIT images
 """
 
 import pytest
-from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
-
+from capsule_common import (
+    capsule_setup,
+    init_content,
+    place_capsule_file,
+    exec_manual_update,
+    check_file_removed,
+    verify_content,
+    do_reboot_dtb_specified
+)
 
 @pytest.mark.boardspec('sandbox_flattree')
 @pytest.mark.buildconfigspec('efi_capsule_firmware_fit')
@@ -40,37 +47,12 @@ class TestEfiCapsuleFirmwareFit():
         u_boot_console.restart_uboot()
 
         disk_img = efi_capsule_data
+        capsule_files = ['Test05']
         with u_boot_console.log.section('Test Case 1-a, before reboot'):
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""',
-                'efidebug boot order 1',
-                'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
-                'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
-                'env save'])
-
-            # initialize contents
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR,
-                'sf write 4000000 100000 10',
-                'sf read 5000000 100000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR,
-                'sf write 4000000 150000 10',
-                'sf read 5000000 150000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-
-            # place a capsule file
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test05' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test05 $filesize' % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test05' in ''.join(output)
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
@@ -80,28 +62,13 @@ class TestEfiCapsuleFirmwareFit():
 
         with u_boot_console.log.section('Test Case 1-b, after reboot'):
             if not capsule_early:
-                # make sure that dfu_alt_info exists even persistent variables
-                # are not available.
-                output = u_boot_console.run_command_list([
-                    'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
-                    'host bind 0 %s' % disk_img,
-                    'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-                assert 'Test05' in ''.join(output)
-
-                # need to run uefi command to initiate capsule handling
-                output = u_boot_console.run_command(
-                    'env print -e Capsule0000', wait_for_reboot = True)
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'sf read 4000000 100000 10',
-                'md.b 4000000 10'])
-            assert 'u-boot:Old' in ''.join(output)
+            # deleted anyway
+            check_file_removed(u_boot_console, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
-                'sf read 4000000 150000 10',
-                'md.b 4000000 10'])
-            assert 'u-boot-env:Old' in ''.join(output)
+            verify_content(u_boot_console, '100000', 'u-boot:Old')
+            verify_content(u_boot_console, '150000', 'u-boot-env:Old')
 
     def test_efi_capsule_fw2(
             self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -112,38 +79,12 @@ class TestEfiCapsuleFirmwareFit():
         """
 
         disk_img = efi_capsule_data
+        capsule_files = ['Test04']
         with u_boot_console.log.section('Test Case 2-a, before reboot'):
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'printenv -e PlatformLangCodes', # workaround for terminal size determination
-                'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""',
-                'efidebug boot order 1',
-                'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
-                'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
-                'env save'])
-
-            # initialize contents
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR,
-                'sf write 4000000 100000 10',
-                'sf read 5000000 100000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR,
-                'sf write 4000000 150000 10',
-                'sf read 5000000 150000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-
-            # place a capsule file
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test04' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test04 $filesize' % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test04' in ''.join(output)
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
@@ -155,36 +96,88 @@ class TestEfiCapsuleFirmwareFit():
 
         with u_boot_console.log.section('Test Case 2-b, after reboot'):
             if not capsule_early:
-                # make sure that dfu_alt_info exists even persistent variables
-                # are not available.
-                output = u_boot_console.run_command_list([
-                    'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
-                    'host bind 0 %s' % disk_img,
-                    'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-                assert 'Test04' in ''.join(output)
-
-                # need to run uefi command to initiate capsule handling
-                output = u_boot_console.run_command(
-                    'env print -e Capsule0000', wait_for_reboot = True)
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test04' not in ''.join(output)
+            check_file_removed(u_boot_console, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'sf read 4000000 100000 10',
-                'md.b 4000000 10'])
-            if capsule_auth:
-                assert 'u-boot:Old' in ''.join(output)
-            else:
-                assert 'u-boot:New' in ''.join(output)
+            expected = 'u-boot:Old' if capsule_auth else 'u-boot:New'
+            verify_content(u_boot_console, '100000', expected)
+
+            expected = 'u-boot-env:Old' if capsule_auth else 'u-boot-env:New'
+            verify_content(u_boot_console, '150000', expected)
+
+    def test_efi_capsule_fw3(
+            self, u_boot_config, u_boot_console, efi_capsule_data):
+        """ Test Case 3
+        Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
+        0x100000-0x150000: U-Boot binary (but dummy)
+        0x150000-0x200000: U-Boot environment (but dummy)
+        """
+        disk_img = efi_capsule_data
+        capsule_files = ['Test104']
+        with u_boot_console.log.section('Test Case 3-a, before reboot'):
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        # reboot
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
 
+        capsule_early = u_boot_config.buildconfig.get(
+            'config_efi_capsule_on_disk_early')
+        capsule_auth = u_boot_config.buildconfig.get(
+            'config_efi_capsule_authenticate')
+        with u_boot_console.log.section('Test Case 3-b, after reboot'):
+            if not capsule_early:
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+            # deleted anyway
+            check_file_removed(u_boot_console, disk_img, capsule_files)
+
+            # make sure the dfu_alt_info exists because it is required for making ESRT.
             output = u_boot_console.run_command_list([
-                'sf read 4000000 150000 10',
-                'md.b 4000000 10'])
+                'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
+                'u-boot-env raw 0x150000 0x200000"',
+                'efidebug capsule esrt'])
+
             if capsule_auth:
-                assert 'u-boot-env:Old' in ''.join(output)
+                # capsule authentication failed
+                verify_content(u_boot_console, '100000', 'u-boot:Old')
+                verify_content(u_boot_console, '150000', 'u-boot-env:Old')
             else:
-                assert 'u-boot-env:New' in ''.join(output)
+                # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
+                assert '3673B45D-6A7C-46F3-9E60-ADABB03F7937' in ''.join(output)
+                assert 'ESRT: fw_version=5' in ''.join(output)
+                assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
+
+                verify_content(u_boot_console, '100000', 'u-boot:New')
+                verify_content(u_boot_console, '150000', 'u-boot-env:New')
+
+    def test_efi_capsule_fw4(
+            self, u_boot_config, u_boot_console, efi_capsule_data):
+        """ Test Case 4
+        Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
+        but fw_version is lower than lowest_supported_version
+        No update should happen
+        0x100000-0x150000: U-Boot binary (but dummy)
+        """
+        disk_img = efi_capsule_data
+        capsule_files = ['Test105']
+        with u_boot_console.log.section('Test Case 4-a, before reboot'):
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        # reboot
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+        capsule_early = u_boot_config.buildconfig.get(
+            'config_efi_capsule_on_disk_early')
+        with u_boot_console.log.section('Test Case 4-b, after reboot'):
+            if not capsule_early:
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+            check_file_removed(u_boot_console, disk_img, capsule_files)
+
+            verify_content(u_boot_console, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
index 92bfb14932..a5b5c8a385 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
@@ -7,7 +7,16 @@ This test verifies capsule-on-disk firmware update for raw images
 """
 
 import pytest
-from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
+from capsule_common import (
+    capsule_setup,
+    init_content,
+    place_capsule_file,
+    exec_manual_update,
+    check_file_removed,
+    check_file_exist,
+    verify_content,
+    do_reboot_dtb_specified
+)
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('efi_capsule_firmware_raw')
@@ -40,37 +49,12 @@ class TestEfiCapsuleFirmwareRaw:
         u_boot_console.restart_uboot()
 
         disk_img = efi_capsule_data
+        capsule_files = ['Test03']
         with u_boot_console.log.section('Test Case 1-a, before reboot'):
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""',
-                'efidebug boot order 1',
-                'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
-                'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
-                'env save'])
-
-            # initialize contents
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR,
-                'sf write 4000000 100000 10',
-                'sf read 5000000 100000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR,
-                'sf write 4000000 150000 10',
-                'sf read 5000000 150000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-
-            # place a capsule file
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test03' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test03 $filesize' % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test03' in ''.join(output)
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
 
         # reboot
         u_boot_console.restart_uboot()
@@ -80,28 +64,13 @@ class TestEfiCapsuleFirmwareRaw:
 
         with u_boot_console.log.section('Test Case 1-b, after reboot'):
             if not capsule_early:
-                # make sure that dfu_alt_info exists even persistent variables
-                # are not available.
-                output = u_boot_console.run_command_list([
-                    'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
-                    'host bind 0 %s' % disk_img,
-                    'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-                assert 'Test03' in ''.join(output)
-
-                # need to run uefi command to initiate capsule handling
-                output = u_boot_console.run_command(
-                    'env print -e Capsule0000', wait_for_reboot = True)
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'sf read 4000000 100000 10',
-                'md.b 4000000 10'])
-            assert 'u-boot:Old' in ''.join(output)
+            # deleted anyway
+            check_file_removed(u_boot_console, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
-                'sf read 4000000 150000 10',
-                'md.b 4000000 10'])
-            assert 'u-boot-env:Old' in ''.join(output)
+            verify_content(u_boot_console, '100000', 'u-boot:Old')
+            verify_content(u_boot_console, '150000', 'u-boot-env:Old')
 
     def test_efi_capsule_fw2(
             self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -112,44 +81,12 @@ class TestEfiCapsuleFirmwareRaw:
         0x150000-0x200000: U-Boot environment (but dummy)
         """
         disk_img = efi_capsule_data
+        capsule_files = ['Test01', 'Test02']
         with u_boot_console.log.section('Test Case 2-a, before reboot'):
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'printenv -e PlatformLangCodes', # workaround for terminal size determination
-                'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""',
-                'efidebug boot order 1',
-                'env set -e OsIndications',
-                'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
-                'env save'])
-
-            # initialize contents
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR,
-                'sf write 4000000 100000 10',
-                'sf read 5000000 100000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR,
-                'sf write 4000000 150000 10',
-                'sf read 5000000 150000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-
-            # place the capsule files
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test01' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test01 $filesize' % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test01' in ''.join(output)
-
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test02 $filesize' % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test02' in ''.join(output)
+            capsule_setup(u_boot_console, disk_img, None)
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
 
         # reboot
         u_boot_console.restart_uboot()
@@ -158,35 +95,12 @@ class TestEfiCapsuleFirmwareRaw:
             'config_efi_capsule_on_disk_early')
         with u_boot_console.log.section('Test Case 2-b, after reboot'):
             if not capsule_early:
-                # make sure that dfu_alt_info exists even persistent variables
-                # are not available.
-                output = u_boot_console.run_command_list([
-                    'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
-                    'host bind 0 %s' % disk_img,
-                    'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-                assert 'Test01' in ''.join(output)
-                assert 'Test02' in ''.join(output)
-
-                # need to run uefi command to initiate capsule handling
-                output = u_boot_console.run_command(
-                    'env print -e Capsule0000')
-
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test01' in ''.join(output)
-            assert 'Test02' in ''.join(output)
+                exec_manual_update(u_boot_console, disk_img, capsule_files, False)
 
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'sf read 4000000 100000 10',
-                'md.b 4000000 10'])
-            assert 'u-boot:Old' in ''.join(output)
+            check_file_exist(u_boot_console, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
-                'sf read 4000000 150000 10',
-                'md.b 4000000 10'])
-            assert 'u-boot-env:Old' in ''.join(output)
+            verify_content(u_boot_console, '100000', 'u-boot:Old')
+            verify_content(u_boot_console, '150000', 'u-boot-env:Old')
 
     def test_efi_capsule_fw3(
             self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -195,45 +109,12 @@ class TestEfiCapsuleFirmwareRaw:
         0x100000-0x150000: U-Boot binary (but dummy)
         """
         disk_img = efi_capsule_data
+        capsule_files = ['Test01', 'Test02']
         with u_boot_console.log.section('Test Case 3-a, before reboot'):
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'printenv -e PlatformLangCodes', # workaround for terminal size determination
-                'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""',
-                'efidebug boot order 1',
-                'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
-                'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
-                'env save'])
-
-            # initialize contents
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR,
-                'sf write 4000000 100000 10',
-                'sf read 5000000 100000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR,
-                'sf write 4000000 150000 10',
-                'sf read 5000000 100000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-
-            # place the capsule files
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test01' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test01 $filesize' % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test01' in ''.join(output)
-
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test02 $filesize' % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test02' in ''.join(output)
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
@@ -245,18 +126,7 @@ class TestEfiCapsuleFirmwareRaw:
 
         with u_boot_console.log.section('Test Case 3-b, after reboot'):
             if not capsule_early:
-                # make sure that dfu_alt_info exists even persistent variables
-                # are not available.
-                output = u_boot_console.run_command_list([
-                    'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
-                    'host bind 0 %s' % disk_img,
-                    'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-                assert 'Test01' in ''.join(output)
-                assert 'Test02' in ''.join(output)
-
-                # need to run uefi command to initiate capsule handling
-                output = u_boot_console.run_command(
-                    'env print -e Capsule0000', wait_for_reboot = True)
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
 
             # make sure the dfu_alt_info exists because it is required for making ESRT.
             output = u_boot_console.run_command_list([
@@ -269,26 +139,91 @@ class TestEfiCapsuleFirmwareRaw:
             # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
             assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output)
 
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test01' not in ''.join(output)
-            assert 'Test02' not in ''.join(output)
+            check_file_removed(u_boot_console, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'sf read 4000000 100000 10',
-                'md.b 4000000 10'])
-            if capsule_auth:
-                assert 'u-boot:Old' in ''.join(output)
-            else:
-                assert 'u-boot:New' in ''.join(output)
+            expected = 'u-boot:Old' if capsule_auth else 'u-boot:New'
+            verify_content(u_boot_console, '100000', expected)
+
+            expected = 'u-boot-env:Old' if capsule_auth else 'u-boot-env:New'
+            verify_content(u_boot_console, '150000', expected)
 
+    def test_efi_capsule_fw4(
+            self, u_boot_config, u_boot_console, efi_capsule_data):
+        """ Test Case 4
+        Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
+        0x100000-0x150000: U-Boot binary (but dummy)
+        0x150000-0x200000: U-Boot environment (but dummy)
+        """
+        disk_img = efi_capsule_data
+        capsule_files = ['Test101', 'Test102']
+        with u_boot_console.log.section('Test Case 4-a, before reboot'):
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        # reboot
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+        capsule_early = u_boot_config.buildconfig.get(
+            'config_efi_capsule_on_disk_early')
+        capsule_auth = u_boot_config.buildconfig.get(
+            'config_efi_capsule_authenticate')
+        with u_boot_console.log.section('Test Case 4-b, after reboot'):
+            if not capsule_early:
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+            # deleted anyway
+            check_file_removed(u_boot_console, disk_img, capsule_files)
+
+            # make sure the dfu_alt_info exists because it is required for making ESRT.
             output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'sf read 4000000 150000 10',
-                'md.b 4000000 10'])
+                'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000'
+                'u-boot-env raw 0x150000 0x200000"',
+                'efidebug capsule esrt'])
+
             if capsule_auth:
-                assert 'u-boot-env:Old' in ''.join(output)
+                # capsule authentication failed
+                verify_content(u_boot_console, '100000', 'u-boot:Old')
+                verify_content(u_boot_console, '150000', 'u-boot-env:Old')
             else:
-                assert 'u-boot-env:New' in ''.join(output)
+                # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
+                assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output)
+                assert 'ESRT: fw_version=5' in ''.join(output)
+                assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
+
+                # ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT.
+                assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output)
+                assert 'ESRT: fw_version=10' in ''.join(output)
+                assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output)
+
+                verify_content(u_boot_console, '100000', 'u-boot:New')
+                verify_content(u_boot_console, '150000', 'u-boot-env:New')
+
+    def test_efi_capsule_fw5(
+            self, u_boot_config, u_boot_console, efi_capsule_data):
+        """ Test Case 5
+        Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
+        but fw_version is lower than lowest_supported_version
+        No update should happen
+        0x100000-0x150000: U-Boot binary (but dummy)
+        """
+        disk_img = efi_capsule_data
+        capsule_files = ['Test103']
+        with u_boot_console.log.section('Test Case 5-a, before reboot'):
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        # reboot
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+        capsule_early = u_boot_config.buildconfig.get(
+            'config_efi_capsule_on_disk_early')
+        with u_boot_console.log.section('Test Case 5-b, after reboot'):
+            if not capsule_early:
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+            check_file_removed(u_boot_console, disk_img, capsule_files)
+
+            verify_content(u_boot_console, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
index ba8429e83c..44a58baa31 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
@@ -10,7 +10,15 @@ with signed capsule files containing FIT images
 """
 
 import pytest
-from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
+from capsule_common import (
+    capsule_setup,
+    init_content,
+    place_capsule_file,
+    exec_manual_update,
+    check_file_removed,
+    verify_content,
+    do_reboot_dtb_specified
+)
 
 @pytest.mark.boardspec('sandbox_flattree')
 @pytest.mark.buildconfigspec('efi_capsule_firmware_fit')
@@ -37,70 +45,23 @@ class TestEfiCapsuleFirmwareSignedFit():
         should pass and the firmware be updated.
         """
         disk_img = efi_capsule_data
+        capsule_files = ['Test13']
         with u_boot_console.log.section('Test Case 1-a, before reboot'):
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'printenv -e PlatformLangCodes', # workaround for terminal size determination
-                'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
-                'efidebug boot order 1',
-                'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
-                'env set dfu_alt_info '
-                        '"sf 0:0=u-boot-bin raw 0x100000 '
-                        '0x50000;u-boot-env raw 0x150000 0x200000"',
-                'env save'])
-
-            # initialize content
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.bin.old'
-                        % CAPSULE_DATA_DIR,
-                'sf write 4000000 100000 10',
-                'sf read 5000000 100000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-
-            # place a capsule file
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test13' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test13 $filesize'
-                        % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test13' in ''.join(output)
-
-        # reboot
-        mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
-        u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
-                                    + '/test_sig.dtb'
-        u_boot_console.restart_uboot()
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
         with u_boot_console.log.section('Test Case 1-b, after reboot'):
             if not capsule_early:
-                # make sure that dfu_alt_info exists even persistent variables
-                # are not available.
-                output = u_boot_console.run_command_list([
-                    'env set dfu_alt_info '
-                            '"sf 0:0=u-boot-bin raw 0x100000 '
-                            '0x50000;u-boot-env raw 0x150000 0x200000"',
-                    'host bind 0 %s' % disk_img,
-                    'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-                assert 'Test13' in ''.join(output)
-
-                # need to run uefi command to initiate capsule handling
-                output = u_boot_console.run_command(
-                    'env print -e Capsule0000', wait_for_reboot = True)
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test13' not in ''.join(output)
+            check_file_removed(u_boot_console, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'sf read 4000000 100000 10',
-                'md.b 4000000 10'])
-            assert 'u-boot:New' in ''.join(output)
+            verify_content(u_boot_console, '100000', 'u-boot:New')
 
     def test_efi_capsule_auth2(
             self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -113,73 +74,26 @@ class TestEfiCapsuleFirmwareSignedFit():
         not be updated.
         """
         disk_img = efi_capsule_data
+        capsule_files = ['Test14']
         with u_boot_console.log.section('Test Case 2-a, before reboot'):
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'printenv -e PlatformLangCodes', # workaround for terminal size determination
-                'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
-                'efidebug boot order 1',
-                'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
-                'env set dfu_alt_info '
-                        '"sf 0:0=u-boot-bin raw 0x100000 '
-                        '0x50000;u-boot-env raw 0x150000 0x200000"',
-                'env save'])
-
-            # initialize content
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.bin.old'
-                        % CAPSULE_DATA_DIR,
-                'sf write 4000000 100000 10',
-                'sf read 5000000 100000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-
-            # place a capsule file
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test14' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test14 $filesize'
-                                % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test14' in ''.join(output)
-
-        # reboot
-        mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
-        u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
-                                    + '/test_sig.dtb'
-        u_boot_console.restart_uboot()
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
         with u_boot_console.log.section('Test Case 2-b, after reboot'):
             if not capsule_early:
-                # make sure that dfu_alt_info exists even persistent variables
-                # are not available.
-                output = u_boot_console.run_command_list([
-                    'env set dfu_alt_info '
-                        '"sf 0:0=u-boot-bin raw 0x100000 '
-                        '0x50000;u-boot-env raw 0x150000 0x200000"',
-                    'host bind 0 %s' % disk_img,
-                    'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-                assert 'Test14' in ''.join(output)
-
-                # need to run uefi command to initiate capsule handling
-                output = u_boot_console.run_command(
-                    'env print -e Capsule0000', wait_for_reboot = True)
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
 
             # deleted any way
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test14' not in ''.join(output)
+            check_file_removed(u_boot_console, disk_img, capsule_files)
 
             # TODO: check CapsuleStatus in CapsuleXXXX
 
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'sf read 4000000 100000 10',
-                'md.b 4000000 10'])
-            assert 'u-boot:Old' in ''.join(output)
+            verify_content(u_boot_console, '100000', 'u-boot:Old')
 
     def test_efi_capsule_auth3(
             self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -191,70 +105,89 @@ class TestEfiCapsuleFirmwareSignedFit():
         should fail and the firmware not be updated.
         """
         disk_img = efi_capsule_data
+        capsule_files = ['Test02']
         with u_boot_console.log.section('Test Case 3-a, before reboot'):
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'printenv -e PlatformLangCodes', # workaround for terminal size determination
-                'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
-                'efidebug boot order 1',
-                'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
-                'env set dfu_alt_info '
-                        '"sf 0:0=u-boot-bin raw 0x100000 '
-                        '0x50000;u-boot-env raw 0x150000 0x200000"',
-                'env save'])
-
-            # initialize content
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.bin.old'
-                        % CAPSULE_DATA_DIR,
-                'sf write 4000000 100000 10',
-                'sf read 5000000 100000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-
-            # place a capsule file
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test02 $filesize'
-                            % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test02' in ''.join(output)
-
-        # reboot
-        mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
-        u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
-                                    + '/test_sig.dtb'
-        u_boot_console.restart_uboot()
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
         with u_boot_console.log.section('Test Case 3-b, after reboot'):
             if not capsule_early:
-                # make sure that dfu_alt_info exists even persistent variables
-                # are not available.
-                output = u_boot_console.run_command_list([
-                    'env set dfu_alt_info '
-                            '"sf 0:0=u-boot-bin raw 0x100000 '
-                            '0x50000;u-boot-env raw 0x150000 0x200000"',
-                    'host bind 0 %s' % disk_img,
-                    'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-                assert 'Test02' in ''.join(output)
-
-                # need to run uefi command to initiate capsule handling
-                output = u_boot_console.run_command(
-                    'env print -e Capsule0000', wait_for_reboot = True)
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
 
             # deleted any way
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test02' not in ''.join(output)
+            check_file_removed(u_boot_console, disk_img, capsule_files)
 
             # TODO: check CapsuleStatus in CapsuleXXXX
 
+            verify_content(u_boot_console, '100000', 'u-boot:Old')
+
+    def test_efi_capsule_auth4(
+            self, u_boot_config, u_boot_console, efi_capsule_data):
+        """Test Case 4 - Update U-Boot on SPI Flash, raw image format with version information
+        0x100000-0x150000: U-Boot binary (but dummy)
+
+        If the capsule is properly signed, the authentication
+        should pass and the firmware be updated.
+        """
+        disk_img = efi_capsule_data
+        capsule_files = ['Test114']
+        with u_boot_console.log.section('Test Case 4-a, before reboot'):
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+        capsule_early = u_boot_config.buildconfig.get(
+            'config_efi_capsule_on_disk_early')
+        with u_boot_console.log.section('Test Case 4-b, after reboot'):
+            if not capsule_early:
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+            check_file_removed(u_boot_console, disk_img, capsule_files)
+
             output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'sf read 4000000 100000 10',
-                'md.b 4000000 10'])
-            assert 'u-boot:Old' in ''.join(output)
+                'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
+                'u-boot-env raw 0x150000 0x200000"',
+                'efidebug capsule esrt'])
+
+            # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
+            assert '3673B45D-6A7C-46F3-9E60-ADABB03F7937' in ''.join(output)
+            assert 'ESRT: fw_version=5' in ''.join(output)
+            assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
+
+            verify_content(u_boot_console, '100000', 'u-boot:New')
+            verify_content(u_boot_console, '150000', 'u-boot-env:New')
+
+    def test_efi_capsule_auth5(
+            self, u_boot_config, u_boot_console, efi_capsule_data):
+        """Test Case 5 - Update U-Boot on SPI Flash, raw image format with version information
+        0x100000-0x150000: U-Boot binary (but dummy)
+
+        If the capsule is signed but fw_version is lower than lowest
+        supported version, the authentication should fail and the firmware
+        not be updated.
+        """
+        disk_img = efi_capsule_data
+        capsule_files = ['Test115']
+        with u_boot_console.log.section('Test Case 5-a, before reboot'):
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+        capsule_early = u_boot_config.buildconfig.get(
+            'config_efi_capsule_on_disk_early')
+        with u_boot_console.log.section('Test Case 5-b, after reboot'):
+            if not capsule_early:
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+            check_file_removed(u_boot_console, disk_img, capsule_files)
+
+            verify_content(u_boot_console, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
index 710d9925a3..83a10e160b 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
@@ -8,7 +8,15 @@ with signed capsule files containing raw images
 """
 
 import pytest
-from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
+from capsule_common import (
+    capsule_setup,
+    init_content,
+    place_capsule_file,
+    exec_manual_update,
+    check_file_removed,
+    verify_content,
+    do_reboot_dtb_specified
+)
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('efi_capsule_firmware_raw')
@@ -34,69 +42,23 @@ class TestEfiCapsuleFirmwareSignedRaw():
         should pass and the firmware be updated.
         """
         disk_img = efi_capsule_data
+        capsule_files =  ['Test11']
         with u_boot_console.log.section('Test Case 1-a, before reboot'):
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
-                'efidebug boot order 1',
-                'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
-                'env set dfu_alt_info '
-                        '"sf 0:0=u-boot-bin raw 0x100000 '
-                        '0x50000;u-boot-env raw 0x150000 0x200000"',
-                'env save'])
-
-            # initialize content
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.bin.old'
-                        % CAPSULE_DATA_DIR,
-                'sf write 4000000 100000 10',
-                'sf read 5000000 100000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-
-            # place a capsule file
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test11' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test11 $filesize'
-                        % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test11' in ''.join(output)
-
-        # reboot
-        mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
-        u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
-                                    + '/test_sig.dtb'
-        u_boot_console.restart_uboot()
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
         with u_boot_console.log.section('Test Case 1-b, after reboot'):
             if not capsule_early:
-                # make sure that dfu_alt_info exists even persistent variables
-                # are not available.
-                output = u_boot_console.run_command_list([
-                    'env set dfu_alt_info '
-                            '"sf 0:0=u-boot-bin raw 0x100000 '
-                            '0x50000;u-boot-env raw 0x150000 0x200000"',
-                    'host bind 0 %s' % disk_img,
-                    'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-                assert 'Test11' in ''.join(output)
-
-                # need to run uefi command to initiate capsule handling
-                output = u_boot_console.run_command(
-                    'env print -e Capsule0000', wait_for_reboot = True)
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test11' not in ''.join(output)
+            check_file_removed(u_boot_console, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'sf read 4000000 100000 10',
-                'md.b 4000000 10'])
-            assert 'u-boot:New' in ''.join(output)
+            verify_content(u_boot_console, '100000', 'u-boot:New')
 
     def test_efi_capsule_auth2(
             self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -108,73 +70,25 @@ class TestEfiCapsuleFirmwareSignedRaw():
         not be updated.
         """
         disk_img = efi_capsule_data
+        capsule_files = ['Test12']
         with u_boot_console.log.section('Test Case 2-a, before reboot'):
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'printenv -e PlatformLangCodes', # workaround for terminal size determination
-                'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
-                'efidebug boot order 1',
-                'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
-                'env set dfu_alt_info '
-                        '"sf 0:0=u-boot-bin raw 0x100000 '
-                        '0x50000;u-boot-env raw 0x150000 0x200000"',
-                'env save'])
-
-            # initialize content
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.bin.old'
-                        % CAPSULE_DATA_DIR,
-                'sf write 4000000 100000 10',
-                'sf read 5000000 100000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-
-            # place a capsule file
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test12' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test12 $filesize'
-                                % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test12' in ''.join(output)
-
-        # reboot
-        mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
-        u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
-                                    + '/test_sig.dtb'
-        u_boot_console.restart_uboot()
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
         with u_boot_console.log.section('Test Case 2-b, after reboot'):
             if not capsule_early:
-                # make sure that dfu_alt_info exists even persistent variables
-                # are not available.
-                output = u_boot_console.run_command_list([
-                    'env set dfu_alt_info '
-                        '"sf 0:0=u-boot-bin raw 0x100000 '
-                        '0x50000;u-boot-env raw 0x150000 0x200000"',
-                    'host bind 0 %s' % disk_img,
-                    'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-                assert 'Test12' in ''.join(output)
-
-                # need to run uefi command to initiate capsule handling
-                output = u_boot_console.run_command(
-                    'env print -e Capsule0000', wait_for_reboot = True)
-
-            # deleted any way
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test12' not in ''.join(output)
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+            check_file_removed(u_boot_console, disk_img, capsule_files)
 
             # TODO: check CapsuleStatus in CapsuleXXXX
 
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'sf read 4000000 100000 10',
-                'md.b 4000000 10'])
-            assert 'u-boot:Old' in ''.join(output)
+            verify_content(u_boot_console, '100000', 'u-boot:Old')
 
     def test_efi_capsule_auth3(
             self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -185,70 +99,94 @@ class TestEfiCapsuleFirmwareSignedRaw():
         should fail and the firmware not be updated.
         """
         disk_img = efi_capsule_data
+        capsule_files = ['Test02']
         with u_boot_console.log.section('Test Case 3-a, before reboot'):
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'printenv -e PlatformLangCodes', # workaround for terminal size determination
-                'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
-                'efidebug boot order 1',
-                'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
-                'env set dfu_alt_info '
-                        '"sf 0:0=u-boot-bin raw 0x100000 '
-                        '0x50000;u-boot-env raw 0x150000 0x200000"',
-                'env save'])
-
-            # initialize content
-            output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'fatload host 0:1 4000000 %s/u-boot.bin.old'
-                        % CAPSULE_DATA_DIR,
-                'sf write 4000000 100000 10',
-                'sf read 5000000 100000 10',
-                'md.b 5000000 10'])
-            assert 'Old' in ''.join(output)
-
-            # place a capsule file
-            output = u_boot_console.run_command_list([
-                'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR,
-                'fatwrite host 0:1 4000000 %s/Test02 $filesize'
-                            % CAPSULE_INSTALL_DIR,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test02' in ''.join(output)
-
-        # reboot
-        mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
-        u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
-                                    + '/test_sig.dtb'
-        u_boot_console.restart_uboot()
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
         with u_boot_console.log.section('Test Case 3-b, after reboot'):
             if not capsule_early:
-                # make sure that dfu_alt_info exists even persistent variables
-                # are not available.
-                output = u_boot_console.run_command_list([
-                    'env set dfu_alt_info '
-                            '"sf 0:0=u-boot-bin raw 0x100000 '
-                            '0x50000;u-boot-env raw 0x150000 0x200000"',
-                    'host bind 0 %s' % disk_img,
-                    'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-                assert 'Test02' in ''.join(output)
-
-                # need to run uefi command to initiate capsule handling
-                output = u_boot_console.run_command(
-                    'env print -e Capsule0000', wait_for_reboot = True)
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
 
             # deleted anyway
-            output = u_boot_console.run_command_list([
-                'host bind 0 %s' % disk_img,
-                'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
-            assert 'Test02' not in ''.join(output)
+            check_file_removed(u_boot_console, disk_img, capsule_files)
 
             # TODO: check CapsuleStatus in CapsuleXXXX
 
+            verify_content(u_boot_console, '100000', 'u-boot:Old')
+
+    def test_efi_capsule_auth4(
+            self, u_boot_config, u_boot_console, efi_capsule_data):
+        """Test Case 4 - Update U-Boot on SPI Flash, raw image format with version information
+        0x100000-0x150000: U-Boot binary (but dummy)
+
+        If the capsule is properly signed, the authentication
+        should pass and the firmware be updated.
+        """
+        disk_img = efi_capsule_data
+        capsule_files = ['Test111', 'Test112']
+        with u_boot_console.log.section('Test Case 4-a, before reboot'):
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+        capsule_early = u_boot_config.buildconfig.get(
+            'config_efi_capsule_on_disk_early')
+        with u_boot_console.log.section('Test Case 4-b, after reboot'):
+            if not capsule_early:
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+            check_file_removed(u_boot_console, disk_img, capsule_files)
+
             output = u_boot_console.run_command_list([
-                'sf probe 0:0',
-                'sf read 4000000 100000 10',
-                'md.b 4000000 10'])
-            assert 'u-boot:Old' in ''.join(output)
+                'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
+                'u-boot-env raw 0x150000 0x200000"',
+                'efidebug capsule esrt'])
+
+            # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
+            assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output)
+            assert 'ESRT: fw_version=5' in ''.join(output)
+            assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
+
+            # ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT.
+            assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output)
+            assert 'ESRT: fw_version=10' in ''.join(output)
+            assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output)
+
+            verify_content(u_boot_console, '100000', 'u-boot:New')
+            verify_content(u_boot_console, '150000', 'u-boot-env:New')
+
+    def test_efi_capsule_auth5(
+            self, u_boot_config, u_boot_console, efi_capsule_data):
+        """Test Case 5 - Update U-Boot on SPI Flash, raw image format with version information
+        0x100000-0x150000: U-Boot binary (but dummy)
+
+        If the capsule is signed but fw_version is lower than lowest
+        supported version, the authentication should fail and the firmware
+        not be updated.
+        """
+        disk_img = efi_capsule_data
+        capsule_files = ['Test113']
+        with u_boot_console.log.section('Test Case 5-a, before reboot'):
+            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
+            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(u_boot_console, capsule_files)
+
+        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+        capsule_early = u_boot_config.buildconfig.get(
+            'config_efi_capsule_on_disk_early')
+        with u_boot_console.log.section('Test Case 5-b, after reboot'):
+            if not capsule_early:
+                exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+            check_file_removed(u_boot_console, disk_img, capsule_files)
+
+            verify_content(u_boot_console, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/version.dts b/test/py/tests/test_efi_capsule/version.dts
new file mode 100644
index 0000000000..07850cc606
--- /dev/null
+++ b/test/py/tests/test_efi_capsule/version.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+	firmware-version {
+		image1 {
+			lowest-supported-version = <3>;
+			image-index = <1>;
+			image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8";
+		};
+		image2 {
+			lowest-supported-version = <7>;
+			image-index = <2>;
+			image-type-id = "5A7021F5-FEF2-48B4-AABA-832E777418C0";
+		};
+		image3 {
+			lowest-supported-version = <3>;
+			image-index = <1>;
+			image-type-id = "3673B45D-6A7C-46F3-9E60-ADABB03F7937";
+		};
+	};
+};
diff --git a/test/py/tests/test_efi_secboot/conftest.py b/test/py/tests/test_efi_secboot/conftest.py
index 30ff702943..ff7ac7c810 100644
--- a/test/py/tests/test_efi_secboot/conftest.py
+++ b/test/py/tests/test_efi_secboot/conftest.py
@@ -14,7 +14,7 @@ def efi_boot_env(request, u_boot_config):
 
     Args:
         request: Pytest request object.
-        u_boot_config: U-boot configuration.
+        u_boot_config: U-Boot configuration.
 
     Return:
         A path to disk image to be used for testing
@@ -139,7 +139,7 @@ def efi_boot_env_intca(request, u_boot_config):
 
     Args:
         request: Pytest request object.
-        u_boot_config: U-boot configuration.
+        u_boot_config: U-Boot configuration.
 
     Return:
         A path to disk image to be used for testing
diff --git a/test/py/tests/test_eficonfig/conftest.py b/test/py/tests/test_eficonfig/conftest.py
index f289df0362..0a82fbefd7 100644
--- a/test/py/tests/test_eficonfig/conftest.py
+++ b/test/py/tests/test_eficonfig/conftest.py
@@ -14,7 +14,7 @@ def efi_eficonfig_data(u_boot_config):
        tests
 
     Args:
-        u_boot_config -- U-boot configuration.
+        u_boot_config -- U-Boot configuration.
 
     Return:
         A path to disk image to be used for testing
diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py
index 9329ec6f1b..0d87d180c7 100644
--- a/test/py/tests/test_fs/conftest.py
+++ b/test/py/tests/test_fs/conftest.py
@@ -97,7 +97,7 @@ def pytest_generate_tests(metafunc):
 # Helper functions
 #
 def fstype_to_ubname(fs_type):
-    """Convert a file system type to an U-boot specific string
+    """Convert a file system type to an U-Boot specific string
 
     A generated string can be used as part of file system related commands
     or a config name in u-boot. Currently fat16 and fat32 are handled
@@ -217,7 +217,7 @@ def fs_obj_basic(request, u_boot_config):
 
     Args:
         request: Pytest request object.
-	u_boot_config: U-boot configuration.
+	u_boot_config: U-Boot configuration.
 
     Return:
         A fixture for basic fs test, i.e. a triplet of file system type,
@@ -339,7 +339,7 @@ def fs_obj_ext(request, u_boot_config):
 
     Args:
         request: Pytest request object.
-	u_boot_config: U-boot configuration.
+	u_boot_config: U-Boot configuration.
 
     Return:
         A fixture for extended fs test, i.e. a triplet of file system type,
@@ -440,7 +440,7 @@ def fs_obj_mkdir(request, u_boot_config):
 
     Args:
         request: Pytest request object.
-	u_boot_config: U-boot configuration.
+	u_boot_config: U-Boot configuration.
 
     Return:
         A fixture for mkdir test, i.e. a duplet of file system type and
@@ -471,7 +471,7 @@ def fs_obj_unlink(request, u_boot_config):
 
     Args:
         request: Pytest request object.
-	u_boot_config: U-boot configuration.
+	u_boot_config: U-Boot configuration.
 
     Return:
         A fixture for unlink test, i.e. a duplet of file system type and
@@ -551,7 +551,7 @@ def fs_obj_symlink(request, u_boot_config):
 
     Args:
         request: Pytest request object.
-        u_boot_config: U-boot configuration.
+        u_boot_config: U-Boot configuration.
 
     Return:
         A fixture for basic fs test, i.e. a triplet of file system type,
diff --git a/test/py/tests/test_scp03.py b/test/py/tests/test_scp03.py
index 1f689252dd..1a104b365f 100644
--- a/test/py/tests/test_scp03.py
+++ b/test/py/tests/test_scp03.py
@@ -5,7 +5,7 @@
 # SCP03 command test
 
 """
-This tests SCP03 command in U-boot.
+This tests SCP03 command in U-Boot.
 
 For additional details check doc/usage/scp03.rst
 """
diff --git a/test/py/tests/test_tpm2.py b/test/py/tests/test_tpm2.py
index d2ad6f9e73..fce689cd99 100644
--- a/test/py/tests/test_tpm2.py
+++ b/test/py/tests/test_tpm2.py
@@ -41,11 +41,9 @@ def force_init(u_boot_console, force=False):
     skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
     if skip_test:
         pytest.skip('skip TPM device test')
-    output = u_boot_console.run_command('tpm2 init')
+    output = u_boot_console.run_command('tpm2 autostart')
     if force or not 'Error' in output:
         u_boot_console.run_command('echo --- start of init ---')
-        u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
-        u_boot_console.run_command('tpm2 self_test full')
         u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT')
         output = u_boot_console.run_command('echo $?')
         if not output.endswith('0'):
@@ -83,20 +81,13 @@ def tpm2_sandbox_init(u_boot_console):
     This allows all tests to run in parallel, since no test depends on another.
     """
     u_boot_console.restart_uboot()
-    u_boot_console.run_command('tpm2 init')
+    u_boot_console.run_command('tpm2 autostart')
     output = u_boot_console.run_command('echo $?')
     assert output.endswith('0')
 
     skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
     if skip_test:
         pytest.skip('skip TPM device test')
-    u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
-    output = u_boot_console.run_command('echo $?')
-    assert output.endswith('0')
-
-    u_boot_console.run_command('tpm2 self_test full')
-    output = u_boot_console.run_command('echo $?')
-    assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_tpm_v2')
 def test_tpm2_sandbox_self_test_full(u_boot_console):
@@ -281,6 +272,12 @@ def test_tpm2_pcr_extend(u_boot_console):
     force_init(u_boot_console)
     ram = u_boot_utils.find_ram_base(u_boot_console)
 
+    read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % (ram + 0x20))
+    output = u_boot_console.run_command('echo $?')
+    assert output.endswith('0')
+    str = re.findall(r'\d+ known updates', read_pcr)[0]
+    updates = int(re.findall(r'\d+', str)[0])
+
     u_boot_console.run_command('tpm2 pcr_extend 0 0x%x' % ram)
     output = u_boot_console.run_command('echo $?')
     assert output.endswith('0')
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index 0b45863b43..aa1d477cd5 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -282,6 +282,15 @@ label Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
         copy_prepared_image(cons, mmc_dev, fname)
 
 
+def setup_cedit_file(cons):
+    infname = os.path.join(cons.config.source_dir,
+                           'test/boot/files/expo_layout.dts')
+    expo_tool = os.path.join(cons.config.source_dir, 'tools/expo.py')
+    outfname = 'cedit.dtb'
+    u_boot_utils.run_and_log(
+        cons, f'{expo_tool} -e {infname} -l {infname} -o {outfname}')
+
+
 @pytest.mark.buildconfigspec('ut_dm')
 def test_ut_dm_init(u_boot_console):
     """Initialize data for ut dm tests."""
@@ -319,6 +328,7 @@ def test_ut_dm_init_bootstd(u_boot_console):
 
     setup_bootflow_image(u_boot_console)
     setup_bootmenu_image(u_boot_console)
+    setup_cedit_file(u_boot_console)
 
     # Restart so that the new mmc1.img is picked up
     u_boot_console.restart_uboot()
diff --git a/test/py/tests/test_xxd/conftest.py b/test/py/tests/test_xxd/conftest.py
index 59285aadf4..47c7cce1aa 100644
--- a/test/py/tests/test_xxd/conftest.py
+++ b/test/py/tests/test_xxd/conftest.py
@@ -13,7 +13,7 @@ def xxd_data(u_boot_config):
     """Set up a file system to be used in xxd tests
 
     Args:
-        u_boot_config -- U-boot configuration.
+        u_boot_config -- U-Boot configuration.
     """
     mnt_point = u_boot_config.persistent_data_dir + '/test_xxd'
     image_path = u_boot_config.persistent_data_dir + '/xxd.img'
@@ -32,4 +32,5 @@ def xxd_data(u_boot_config):
         pytest.skip('Setup failed')
     finally:
         shutil.rmtree(mnt_point)
-        os.remove(image_path)
+        if os.path.exists(image_path):
+            os.remove(image_path)
diff --git a/test/test-main.c b/test/test-main.c
index b3c30d9293..778bf0a18a 100644
--- a/test/test-main.c
+++ b/test/test-main.c
@@ -272,7 +272,7 @@ static int dm_test_restore(struct device_node *of_root)
 		return ret;
 	dm_scan_plat(false);
 	if (!CONFIG_IS_ENABLED(OF_PLATDATA))
-		dm_scan_fdt(false);
+		dm_extended_scan(false);
 
 	return 0;
 }
@@ -476,7 +476,8 @@ static int ut_run_test_live_flat(struct unit_test_state *uts,
 	 *   (for sandbox we handle this by copying the tree, but not for other
 	 *    boards)
 	 */
-	if (!(test->flags & UT_TESTF_LIVE_TREE) &&
+	if ((test->flags & UT_TESTF_SCAN_FDT) &&
+	    !(test->flags & UT_TESTF_LIVE_TREE) &&
 	    (CONFIG_IS_ENABLED(OFNODE_MULTI_TREE) ||
 	     !(test->flags & UT_TESTF_OTHER_FDT)) &&
 	    (!runs || ut_test_run_on_flattree(test)) &&
diff --git a/tools/.gitignore b/tools/.gitignore
index cda3ea628c..941d38de21 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -34,6 +34,7 @@
 /relocate-rela
 /spl_size_limit
 /sunxi-spl-image-builder
+/tools/generated/**/*.c
 /update_octeon_header
 /version.h
 /xway-swap-bytes
diff --git a/tools/Kconfig b/tools/Kconfig
index 539708f277..6e23f44d55 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -157,4 +157,13 @@ config LUT_SEQUENCE
 	help
 	  Look Up Table Sequence
 
+config TOOLS_MKFWUMDATA
+	bool "Build mkfwumdata command"
+	default y if FWU_MULTI_BANK_UPDATE
+	help
+	  This command allows users to create a raw image of the FWU
+	  metadata for initial installation of the FWU multi bank
+	  update on the board. The installation method depends on
+	  the platform.
+
 endmenu
diff --git a/tools/Makefile b/tools/Makefile
index d793cf3bec..3d0c4b0dd6 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -48,20 +48,20 @@ hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo
 HOSTCFLAGS_bmp_logo.o := -pedantic
 
 hostprogs-$(BUILD_ENVCRC) += envcrc
-envcrc-objs := envcrc.o lib/crc32.o env/embedded.o lib/sha1.o
+envcrc-objs := envcrc.o generated/lib/crc32.o generated/env/embedded.o generated/lib/sha1.o
 
 hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr
 HOSTCFLAGS_gen_eth_addr.o := -pedantic
 
 hostprogs-$(CONFIG_CMD_NET) += gen_ethaddr_crc
-gen_ethaddr_crc-objs := gen_ethaddr_crc.o lib/crc8.o
+gen_ethaddr_crc-objs := gen_ethaddr_crc.o generated/lib/crc8.o
 HOSTCFLAGS_gen_ethaddr_crc.o := -pedantic
 
 hostprogs-$(CONFIG_CMD_LOADS) += img2srec
 HOSTCFLAGS_img2srec.o := -pedantic
 
 hostprogs-y += mkenvimage
-mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o
+mkenvimage-objs := mkenvimage.o os_support.o generated/lib/crc32.o
 
 hostprogs-y += dumpimage mkimage
 hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += fit_info fit_check_sign
@@ -71,30 +71,30 @@ ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_FWU_MDATA_GPT_BLK),)
 hostprogs-y += file2include
 endif
 
-FIT_OBJS-y := fit_common.o fit_image.o image-host.o boot/image-fit.o
-FIT_SIG_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := image-sig-host.o boot/image-fit-sig.o
-FIT_CIPHER_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := boot/image-cipher.o
+FIT_OBJS-y := fit_common.o fit_image.o image-host.o generated/boot/image-fit.o
+FIT_SIG_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := image-sig-host.o generated/boot/image-fit-sig.o
+FIT_CIPHER_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := generated/boot/image-cipher.o
 
 # The following files are synced with upstream DTC.
 # Use synced versions from scripts/dtc/libfdt/.
 LIBFDT_OBJS := $(addprefix libfdt/, fdt.o fdt_ro.o fdt_wip.o fdt_sw.o fdt_rw.o \
 		fdt_strerror.o fdt_empty_tree.o fdt_addresses.o fdt_overlay.o)
 
-RSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/rsa/, \
+RSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/rsa/, \
 					rsa-sign.o rsa-verify.o \
 					rsa-mod-exp.o)
 
-ECDSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/ecdsa/, ecdsa-libcrypto.o)
+ECDSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/ecdsa/, ecdsa-libcrypto.o)
 
-AES_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/aes/, \
+AES_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/aes/, \
 					aes-encrypt.o aes-decrypt.o)
 
 # Cryptographic helpers and image types that depend on openssl/libcrypto
 LIBCRYPTO_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := \
-			lib/fdt-libcrypto.o \
+			generated/lib/fdt-libcrypto.o \
 			sunxi_toc0.o
 
-ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o
+ROCKCHIP_OBS = generated/lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o
 
 # common objs for dumpimage and mkimage
 dumpimage-mkimage-objs := aisimage.o \
@@ -102,20 +102,20 @@ dumpimage-mkimage-objs := aisimage.o \
 			$(FIT_OBJS-y) \
 			$(FIT_SIG_OBJS-y) \
 			$(FIT_CIPHER_OBJS-y) \
-			boot/fdt_region.o \
-			boot/bootm.o \
-			lib/crc32.o \
+			generated/boot/fdt_region.o \
+			generated/boot/bootm.o \
+			generated/lib/crc32.o \
 			default_image.o \
-			lib/fdtdec_common.o \
-			lib/fdtdec.o \
-			boot/image.o \
-			boot/image-host.o \
+			generated/lib/fdtdec_common.o \
+			generated/lib/fdtdec.o \
+			generated/boot/image.o \
+			generated/boot/image-host.o \
 			imagetool.o \
 			imximage.o \
 			imx8image.o \
 			imx8mimage.o \
 			kwbimage.o \
-			lib/md5.o \
+			generated/lib/md5.o \
 			lpc32xximage.o \
 			mxsimage.o \
 			omapimage.o \
@@ -128,12 +128,12 @@ dumpimage-mkimage-objs := aisimage.o \
 			$(ROCKCHIP_OBS) \
 			socfpgaimage.o \
 			sunxi_egon.o \
-			lib/crc16-ccitt.o \
-			lib/hash-checksum.o \
-			lib/sha1.o \
-			lib/sha256.o \
-			lib/sha512.o \
-			common/hash.o \
+			generated/lib/crc16-ccitt.o \
+			generated/lib/hash-checksum.o \
+			generated/lib/sha1.o \
+			generated/lib/sha256.o \
+			generated/lib/sha512.o \
+			generated/common/hash.o \
 			ublimage.o \
 			zynqimage.o \
 			zynqmpimage.o \
@@ -213,7 +213,7 @@ HOSTCFLAGS_mxsboot.o := -pedantic
 
 hostprogs-$(CONFIG_ARCH_SUNXI) += mksunxiboot
 hostprogs-$(CONFIG_ARCH_SUNXI) += sunxi-spl-image-builder
-sunxi-spl-image-builder-objs := sunxi-spl-image-builder.o lib/bch.o
+sunxi-spl-image-builder-objs := sunxi-spl-image-builder.o generated/lib/bch.o
 
 hostprogs-$(CONFIG_NETCONSOLE) += ncb
 
@@ -221,16 +221,16 @@ hostprogs-$(CONFIG_ARCH_KIRKWOOD) += kwboot
 hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot
 
 hostprogs-y += proftool
-proftool-objs = proftool.o lib/abuf.o
+proftool-objs = proftool.o generated/lib/abuf.o
 
 hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela
 hostprogs-$(CONFIG_RISCV) += prelink-riscv
 
 hostprogs-$(CONFIG_ARCH_OCTEON) += update_octeon_header
-update_octeon_header-objs := update_octeon_header.o lib/crc32.o
+update_octeon_header-objs := update_octeon_header.o generated/lib/crc32.o
 
 hostprogs-y += fdtgrep
-fdtgrep-objs += $(LIBFDT_OBJS) boot/fdt_region.o fdtgrep.o
+fdtgrep-objs += $(LIBFDT_OBJS) generated/boot/fdt_region.o fdtgrep.o
 
 ifneq ($(TOOLS_ONLY),y)
 hostprogs-y += spl_size_limit
@@ -251,6 +251,10 @@ HOSTLDLIBS_mkeficapsule += \
 	$(shell pkg-config --libs uuid 2> /dev/null || echo "-luuid")
 hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
 
+mkfwumdata-objs := mkfwumdata.o generated/lib/crc32.o
+HOSTLDLIBS_mkfwumdata += -luuid
+hostprogs-$(CONFIG_TOOLS_MKFWUMDATA) += mkfwumdata
+
 # We build some files with extra pedantic flags to try to minimize things
 # that won't build on some weird host compiler -- though there are lots of
 # exceptions for files that aren't complaint.
@@ -262,12 +266,12 @@ HOSTCFLAGS_sha256.o := -pedantic
 HOSTCFLAGS_sha512.o := -pedantic -DCONFIG_SHA512 -DCONFIG_SHA384
 
 quiet_cmd_wrap = WRAP    $@
-cmd_wrap = echo "\#include <../$(patsubst $(obj)/%,%,$@)>" >$@
+cmd_wrap = echo "\#include <../$(patsubst $(obj)/generated/%,%,$@)>" >$@
 
-$(obj)/boot/%.c $(obj)/common/%.c $(obj)/env/%.c $(obj)/lib/%.c:
+$(obj)/generated/%.c:
 	$(call cmd,wrap)
 
-clean-dirs := lib common
+clean-dirs := generated
 
 always := $(hostprogs-y)
 
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index 23cbb99b4b..aeea33fddb 100644
--- a/tools/binman/binman.rst
+++ b/tools/binman/binman.rst
@@ -727,6 +727,13 @@ optional:
     Note that missing, optional blobs do not produce a non-zero exit code from
     binman, although it does show a warning about the missing external blob.
 
+insert-template:
+    This is not strictly speaking an entry property, since it is processed early
+    in Binman before the entries are read. It is a list of phandles of nodes to
+    include in the current (target) node. For each node, its subnodes and their
+    properties are brought into the target node. See Templates_ below for
+    more information.
+
 The attributes supported for images and sections are described below. Several
 are similar to those for entries.
 
@@ -831,6 +838,13 @@ write-symbols:
     binman. This is automatic for certain entry types, e.g. `u-boot-spl`. See
     binman_syms_ for more information.
 
+no-write-symbols:
+    Disables symbol writing for this entry. This can be used in entry types
+    where symbol writing is automatic. For example, if `u-boot-spl` refers to
+    the `u_boot_any_image_pos` symbol but U-Boot is not available in the image
+    containing SPL, this can be used to disable the writing. Quite likely this
+    indicates a bug in your setup.
+
 elf-filename:
     Sets the file name of a blob's associated ELF file. For example, if the
     blob is `zephyr.bin` then the ELF file may be `zephyr.elf`. This allows
@@ -1165,6 +1179,110 @@ If you are having trouble figuring out what is going on, you can use
      arch/arm/dts/u-boot.dtsi ... found: "arch/arm/dts/juno-r2-u-boot.dtsi"
 
 
+Templates
+=========
+
+Sometimes multiple images need to be created which have all have a common
+part. For example, a board may generate SPI and eMMC images which both include
+a FIT. Since the FIT includes many entries, it is tedious to repeat them twice
+in the image description.
+
+Templates provide a simple way to handle this::
+
+    binman {
+        multiple-images;
+        common_part: template-1 {
+            some-property;
+            fit {
+                ... lots of entries in here
+            };
+
+            text {
+                text = "base image";
+            };
+        };
+
+        spi-image {
+            filename = "image-spi.bin";
+            insert-template = <&fit>;
+
+            /* things specific to SPI follow */
+            footer {
+            ];
+
+            text {
+                text = "SPI image";
+            };
+        };
+
+        mmc-image {
+            filename = "image-mmc.bin";
+            insert-template = <&fit>;
+
+            /* things specific to MMC follow */
+            footer {
+            ];
+
+            text {
+                text = "MMC image";
+            };
+        };
+    };
+
+The template node name must start with 'template', so it is not considered to be
+an image itself.
+
+The mechanism is very simple. For each phandle in the 'insert-templates'
+property, the source node is looked up. Then the subnodes of that source node
+are copied into the target node, i.e. the one containing the `insert-template`
+property.
+
+If the target node has a node with the same name as a template, its properties
+override corresponding properties in the template. This allows the template to
+be uses as a base, with the node providing updates to the properties as needed.
+The overriding happens recursively.
+
+Template nodes appear first in each node that they are inserted into and
+ordering of template nodes is preserved. Other nodes come afterwards. If a
+template node also appears in the target node, then the template node sets the
+order. Thus the template can be used to set the ordering, even if the target
+node provides all the properties. In the above example, `fit` and `text` appear
+first in the `spi-image` and `mmc-image` images, followed by `footer`.
+
+Where there are multiple template nodes, they are inserted in that order. so
+the first template node appears first, then the second.
+
+Properties in the template node are inserted into the destination node if they
+do not exist there. In the example above, `some-property` is added to each of
+`spi-image` and `mmc-image`.
+
+Note that template nodes are removed from the binman description after
+processing and before binman builds the image descriptions.
+
+The initial devicetree produced by the templating process is written to the
+`u-boot.dtb.tmpl1` file. This can be useful to see what is going on if there is
+a failure before the final `u-boot.dtb.out` file is written. A second
+`u-boot.dtb.tmpl2` file is written when the templates themselves are removed.
+
+Dealing with phandles
+---------------------
+
+Templates can contain phandles and these are copied to the destination node.
+However this should be used with care, since if a template is instantiated twice
+then the phandle will be copied twice, resulting in a devicetree with duplicate
+phandles, i.e. the same phandle used by two different nodes. Binman detects this
+situation and produces an error, for example::
+
+  Duplicate phandle 1 in nodes /binman/image/fit/images/atf/atf-bl31 and
+  /binman/image-2/fit/images/atf/atf-bl31
+
+In this case an atf-bl31 node containing a phandle has been copied into two
+different target nodes, resulting in the same phandle for each. See
+testTemplatePhandleDup() for the test case.
+
+The solution is typically to put the phandles in the corresponding target nodes
+(one for each) and remove the phandle from the template.
+
 Updating an ELF file
 ====================
 
diff --git a/tools/binman/bintool.py b/tools/binman/bintool.py
index 81629683df..0b0f56dbbb 100644
--- a/tools/binman/bintool.py
+++ b/tools/binman/bintool.py
@@ -288,7 +288,7 @@ class Bintool:
         name = os.path.expanduser(self.name)  # Expand paths containing ~
         all_args = (name,) + args
         env = tools.get_env_with_path()
-        tout.detail(f"bintool: {' '.join(all_args)}")
+        tout.debug(f"bintool: {' '.join(all_args)}")
         result = command.run_pipe(
             [all_args], capture=True, capture_stderr=True, env=env,
             raise_on_error=False, binary=binary)
diff --git a/tools/binman/bintools.rst b/tools/binman/bintools.rst
index c30e7eb9ff..1336f4d011 100644
--- a/tools/binman/bintools.rst
+++ b/tools/binman/bintools.rst
@@ -155,6 +155,17 @@ Support is provided for fetching this on Debian-like systems, using apt.
 
 
 
+Bintool: openssl: openssl tool
+------------------------------
+
+This bintool supports creating new openssl certificates.
+
+It also supports fetching a binary openssl
+
+Documentation about openssl is at https://www.openssl.org/
+
+
+
 Bintool: xz: Compression/decompression using the xz algorithm
 -------------------------------------------------------------
 
@@ -183,3 +194,25 @@ Documentation is available via::
 
 
 
+Bintool: fdt_add_pubkey: Add public key to device tree
+------------------------------------------------------
+
+This bintool supports running `fdt_add_pubkey` in order to add a public
+key coming from a certificate to a device-tree.
+
+Normally signing is done using `mkimage` in context of `binman sign`. However,
+in this process the public key is not added to the stage before u-boot proper.
+Using `fdt_add_pubkey` the key can be injected to the SPL independent of
+`mkimage`
+
+
+
+Bintool: bootgen: Sign ZynqMP FSBL image
+----------------------------------------
+
+This bintool supports running `bootgen` in order to sign a SPL for ZynqMP
+devices.
+
+The bintool automatically creates an appropriate input image file (.bif) for
+bootgen based on the passed arguments. The output is a bootable,
+authenticated `boot.bin` file.
diff --git a/tools/binman/btool/bootgen.py b/tools/binman/btool/bootgen.py
new file mode 100644
index 0000000000..f2ca552dc2
--- /dev/null
+++ b/tools/binman/btool/bootgen.py
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2023 Weidmüller Interface GmbH & Co. KG
+# Lukas Funke <lukas.funke@weidmueller.com>
+#
+"""Bintool implementation for bootgen
+
+bootgen allows creating bootable SPL for Zynq(MP)
+
+Documentation is available via:
+https://www.xilinx.com/support/documents/sw_manuals/xilinx2022_1/ug1283-bootgen-user-guide.pdf
+
+Source code is available at:
+https://github.com/Xilinx/bootgen
+
+"""
+
+from binman import bintool
+from u_boot_pylib import tools
+
+# pylint: disable=C0103
+class Bintoolbootgen(bintool.Bintool):
+    """Generate bootable fsbl image for zynq/zynqmp
+
+    This bintools supports running Xilinx "bootgen" in order
+    to generate a bootable, authenticated image form an SPL.
+
+    """
+    def __init__(self, name):
+        super().__init__(name, 'Xilinx Bootgen',
+                         version_regex=r'^\*\*\*\*\*\* *Xilinx Bootgen *(.*)',
+                         version_args='-help')
+
+    # pylint: disable=R0913
+    def sign(self, arch, spl_elf_fname, pmufw_elf_fname,
+             psk_fname, ssk_fname, fsbl_config, auth_params, keysrc_enc,
+             output_fname):
+        """Sign SPL elf file and bundle it with PMU firmware into an image
+
+        The method bundels the SPL together with a 'Platform Management Unit'
+        (PMU)[1] firmware into a single bootable image. The image in turn is
+        signed with the provided 'secondary secret key' (ssk), which in turn is
+        signed with the 'primary secret key' (psk). In order to verify the
+        authenticity of the ppk, it's hash has to be fused into the device
+        itself.
+
+        In Xilinx terms the SPL is usually called 'FSBL'
+        (First Stage Boot Loader). The jobs of the SPL and the FSBL are mostly
+        the same: load bitstream, bootstrap u-boot.
+
+        Args:
+            arch (str): Xilinx SoC architecture. Currently only 'zynqmp' is
+                supported.
+            spl_elf_fname (str): Filename of SPL ELF file. The filename must end
+                with '.elf' in order for bootgen to recognized it as an ELF
+                file. Otherwise the start address field is missinterpreted.
+            pmufw_elf_fname (str): Filename PMU ELF firmware.
+            psk_fname (str): Filename of the primary secret key (psk). The psk
+                is a .pem file which holds the RSA private key used for signing
+                the secondary secret key.
+            ssk_fname (str): Filename of the secondary secret key. The ssk
+                is a .pem file which holds the RSA private key used for signing
+                the actual boot firmware.
+            fsbl_config (str): FSBL config options. A string list of fsbl config
+                options. Valid values according to [2] are:
+                "bh_auth_enable": Boot Header Authentication Enable: RSA
+                    authentication of the bootimage is done
+                    excluding the verification of PPK hash and SPK ID. This is
+                    useful for debugging before bricking a device.
+                "auth_only": Boot image is only RSA signed. FSBL should not be
+                    decrypted. See the
+                    Zynq UltraScale+ Device Technical Reference Manual (UG1085)
+                    for more information.
+                There are more options which relate to PUF (physical unclonable
+                functions). Please refer to Xilinx manuals for further info.
+            auth_params (str): Authentication parameter. A semicolon separated
+                list of authentication parameters. Valid values according to [3]
+                are:
+                "ppk_select=<0|1>" - Select which ppk to use
+                "spk_id=<32-bit spk id>" - Specifies which SPK can be
+                    used or revoked, default is 0x0
+                "spk_select=<spk-efuse/user-efuse>" - To differentiate spk and
+                    user efuses.
+                "auth_header" - To authenticate headers when no partition
+                    is authenticated.
+            keysrc_enc (str): This specifies the Key source for encryption.
+                Valid values according to [3] are:
+                "bbram_red_key" - RED key stored in BBRAM
+                "efuse_red_key" - RED key stored in eFUSE
+                "efuse_gry_key" - Grey (Obfuscated) Key stored in eFUSE.
+                "bh_gry_key" - Grey (Obfuscated) Key stored in boot header
+                "bh_blk_key" - Black Key stored in boot header
+                "efuse_blk_key" - Black Key stored in eFUSE
+                "kup_key" - User Key
+
+            output_fname (str): Filename where bootgen should write the result
+        
+        Returns:
+            str: Bootgen output from stdout
+
+        [1] https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841724/PMU+Firmware
+        [2] https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide/fsbl_config
+        [3] https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide/auth_params
+        [4] https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide/keysrc_encryption
+        """
+
+        _fsbl_config = f"[fsbl_config] {fsbl_config}" if fsbl_config else ""
+        _auth_params = f"[auth_params] {auth_params}" if auth_params else ""
+        _keysrc_enc  = f"[keysrc_encryption] {keysrc_enc}" if keysrc_enc else ""
+
+        bif_template = f"""u_boot_spl_aes_rsa: {{
+            [pskfile] {psk_fname}
+            [sskfile] {ssk_fname}
+            {_keysrc_enc}
+            {_fsbl_config}
+            {_auth_params}
+            [ bootloader,
+              authentication = rsa,
+              destination_cpu=a53-0] {spl_elf_fname}
+            [pmufw_image] {pmufw_elf_fname}
+        }}"""
+        args = ["-arch", arch]
+
+        bif_fname = tools.get_output_filename('bootgen-in.sign.bif')
+        tools.write_file(bif_fname, bif_template, False)
+        args += ["-image", bif_fname, '-w', '-o', output_fname]
+        return self.run_cmd(*args)
+
+    def fetch(self, method):
+        """Fetch bootgen from git"""
+        if method != bintool.FETCH_BUILD:
+            return None
+
+        result = self.build_from_git(
+            'https://github.com/Xilinx/bootgen',
+            'all',
+            'bootgen')
+        return result
diff --git a/tools/binman/btool/fdt_add_pubkey.py b/tools/binman/btool/fdt_add_pubkey.py
new file mode 100644
index 0000000000..a50774200c
--- /dev/null
+++ b/tools/binman/btool/fdt_add_pubkey.py
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2023 Weidmüller Interface GmbH & Co. KG
+# Lukas Funke <lukas.funke@weidmueller.com>
+#
+"""Bintool implementation for fdt_add_pubkey"""
+
+from binman import bintool
+
+class Bintoolfdt_add_pubkey(bintool.Bintool):
+    """Add public key to control dtb (spl or u-boot proper)
+
+    This bintool supports running `fdt_add_pubkey`.
+
+    Normally mkimage adds signature information to the control dtb. However
+    binman images are built independent from each other. Thus it is required
+    to add the public key separately from mkimage.
+    """
+    def __init__(self, name):
+        super().__init__(name, 'Generate image for U-Boot')
+
+    # pylint: disable=R0913
+    def run(self, input_fname, keydir, keyname, required, algo):
+        """Run fdt_add_pubkey
+
+        Args:
+            input_fname (str): dtb file to sign
+            keydir (str): Directory with public key. Optional parameter,
+                default value: '.' (current directory)
+            keyname (str): Public key name. Optional parameter,
+                default value: key
+            required (str): If present this indicates that the key must be
+                verified for the image / configuration to be considered valid.
+            algo (str): Cryptographic algorithm. Optional parameter,
+                default value: sha1,rsa2048
+        """
+        args = []
+        if algo:
+            args += ['-a', algo]
+        if keydir:
+            args += ['-k', keydir]
+        if keyname:
+            args += ['-n', keyname]
+        if required:
+            args += ['-r', required]
+
+        args += [ input_fname ]
+
+        return self.run_cmd(*args)
+
+    def fetch(self, method):
+        """Fetch handler for fdt_add_pubkey
+
+        This installs fdt_add_pubkey using the apt utility.
+
+        Args:
+            method (FETCH_...): Method to use
+
+        Returns:
+            True if the file was fetched and now installed, None if a method
+            other than FETCH_BIN was requested
+
+        Raises:
+            Valuerror: Fetching could not be completed
+        """
+        if method != bintool.FETCH_BIN:
+            return None
+        return self.apt_install('u-boot-tools')
diff --git a/tools/binman/btool/openssl.py b/tools/binman/btool/openssl.py
index 3a4dbdd6d7..aad3b61ae2 100644
--- a/tools/binman/btool/openssl.py
+++ b/tools/binman/btool/openssl.py
@@ -15,6 +15,13 @@ import hashlib
 from binman import bintool
 from u_boot_pylib import tools
 
+
+VALID_SHAS = [256, 384, 512, 224]
+SHA_OIDS = {256:'2.16.840.1.101.3.4.2.1',
+            384:'2.16.840.1.101.3.4.2.2',
+            512:'2.16.840.1.101.3.4.2.3',
+            224:'2.16.840.1.101.3.4.2.4'}
+
 class Bintoolopenssl(bintool.Bintool):
     """openssl tool
 
@@ -74,6 +81,243 @@ imageSize              = INTEGER:{len(indata)}
                 '-sha512']
         return self.run_cmd(*args)
 
+    def x509_cert_sysfw(self, cert_fname, input_fname, key_fname, sw_rev,
+                  config_fname, req_dist_name_dict):
+        """Create a certificate to be booted by system firmware
+
+        Args:
+            cert_fname (str): Filename of certificate to create
+            input_fname (str): Filename containing data to sign
+            key_fname (str): Filename of .pem file
+            sw_rev (int): Software revision
+            config_fname (str): Filename to write fconfig into
+            req_dist_name_dict (dict): Dictionary containing key-value pairs of
+            req_distinguished_name section extensions, must contain extensions for
+            C, ST, L, O, OU, CN and emailAddress
+
+        Returns:
+            str: Tool output
+        """
+        indata = tools.read_file(input_fname)
+        hashval = hashlib.sha512(indata).hexdigest()
+        with open(config_fname, 'w', encoding='utf-8') as outf:
+            print(f'''[ req ]
+distinguished_name     = req_distinguished_name
+x509_extensions        = v3_ca
+prompt                 = no
+dirstring_type         = nobmp
+
+[ req_distinguished_name ]
+C                      = {req_dist_name_dict['C']}
+ST                     = {req_dist_name_dict['ST']}
+L                      = {req_dist_name_dict['L']}
+O                      = {req_dist_name_dict['O']}
+OU                     = {req_dist_name_dict['OU']}
+CN                     = {req_dist_name_dict['CN']}
+emailAddress           = {req_dist_name_dict['emailAddress']}
+
+[ v3_ca ]
+basicConstraints       = CA:true
+1.3.6.1.4.1.294.1.3    = ASN1:SEQUENCE:swrv
+1.3.6.1.4.1.294.1.34   = ASN1:SEQUENCE:sysfw_image_integrity
+1.3.6.1.4.1.294.1.35   = ASN1:SEQUENCE:sysfw_image_load
+
+[ swrv ]
+swrv = INTEGER:{sw_rev}
+
+[ sysfw_image_integrity ]
+shaType                = OID:2.16.840.1.101.3.4.2.3
+shaValue               = FORMAT:HEX,OCT:{hashval}
+imageSize              = INTEGER:{len(indata)}
+
+[ sysfw_image_load ]
+destAddr = FORMAT:HEX,OCT:00000000
+authInPlace = INTEGER:2
+''', file=outf)
+        args = ['req', '-new', '-x509', '-key', key_fname, '-nodes',
+                '-outform', 'DER', '-out', cert_fname, '-config', config_fname,
+                '-sha512']
+        return self.run_cmd(*args)
+
+    def x509_cert_rom(self, cert_fname, input_fname, key_fname, sw_rev,
+                  config_fname, req_dist_name_dict, cert_type, bootcore,
+                  bootcore_opts, load_addr, sha):
+        """Create a certificate
+
+        Args:
+            cert_fname (str): Filename of certificate to create
+            input_fname (str): Filename containing data to sign
+            key_fname (str): Filename of .pem file
+            sw_rev (int): Software revision
+            config_fname (str): Filename to write fconfig into
+            req_dist_name_dict (dict): Dictionary containing key-value pairs of
+            req_distinguished_name section extensions, must contain extensions for
+            C, ST, L, O, OU, CN and emailAddress
+            cert_type (int): Certification type
+            bootcore (int): Booting core
+            load_addr (int): Load address of image
+            sha (int): Hash function
+
+        Returns:
+            str: Tool output
+        """
+        indata = tools.read_file(input_fname)
+        hashval = hashlib.sha512(indata).hexdigest()
+        with open(config_fname, 'w', encoding='utf-8') as outf:
+            print(f'''
+[ req ]
+ distinguished_name     = req_distinguished_name
+ x509_extensions        = v3_ca
+ prompt                 = no
+ dirstring_type         = nobmp
+
+ [ req_distinguished_name ]
+C                      = {req_dist_name_dict['C']}
+ST                     = {req_dist_name_dict['ST']}
+L                      = {req_dist_name_dict['L']}
+O                      = {req_dist_name_dict['O']}
+OU                     = {req_dist_name_dict['OU']}
+CN                     = {req_dist_name_dict['CN']}
+emailAddress           = {req_dist_name_dict['emailAddress']}
+
+ [ v3_ca ]
+ basicConstraints = CA:true
+ 1.3.6.1.4.1.294.1.1 = ASN1:SEQUENCE:boot_seq
+ 1.3.6.1.4.1.294.1.2 = ASN1:SEQUENCE:image_integrity
+ 1.3.6.1.4.1.294.1.3 = ASN1:SEQUENCE:swrv
+# 1.3.6.1.4.1.294.1.4 = ASN1:SEQUENCE:encryption
+ 1.3.6.1.4.1.294.1.8 = ASN1:SEQUENCE:debug
+
+ [ boot_seq ]
+ certType = INTEGER:{cert_type}
+ bootCore = INTEGER:{bootcore}
+ bootCoreOpts = INTEGER:{bootcore_opts}
+ destAddr = FORMAT:HEX,OCT:{load_addr:08x}
+ imageSize = INTEGER:{len(indata)}
+
+ [ image_integrity ]
+ shaType = OID:{SHA_OIDS[sha]}
+ shaValue = FORMAT:HEX,OCT:{hashval}
+
+ [ swrv ]
+ swrv = INTEGER:{sw_rev}
+
+# [ encryption ]
+# initalVector = FORMAT:HEX,OCT:TEST_IMAGE_ENC_IV
+# randomString = FORMAT:HEX,OCT:TEST_IMAGE_ENC_RS
+# iterationCnt = INTEGER:TEST_IMAGE_KEY_DERIVE_INDEX
+# salt = FORMAT:HEX,OCT:TEST_IMAGE_KEY_DERIVE_SALT
+
+ [ debug ]
+ debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000
+ debugType = INTEGER:4
+ coreDbgEn = INTEGER:0
+ coreDbgSecEn = INTEGER:0
+''', file=outf)
+        args = ['req', '-new', '-x509', '-key', key_fname, '-nodes',
+                '-outform', 'DER', '-out', cert_fname, '-config', config_fname,
+                '-sha512']
+        return self.run_cmd(*args)
+
+    def x509_cert_rom_combined(self, cert_fname, input_fname, key_fname, sw_rev,
+                  config_fname, req_dist_name_dict, load_addr, sha, total_size, num_comps,
+                  sysfw_inner_cert_ext_boot_sequence_string, dm_data_ext_boot_sequence_string,
+                  imagesize_sbl, hashval_sbl, load_addr_sysfw, imagesize_sysfw,
+                  hashval_sysfw, load_addr_sysfw_data, imagesize_sysfw_data,
+                  hashval_sysfw_data, sysfw_inner_cert_ext_boot_block,
+                  dm_data_ext_boot_block):
+        """Create a certificate
+
+        Args:
+            cert_fname (str): Filename of certificate to create
+            input_fname (str): Filename containing data to sign
+            key_fname (str): Filename of .pem file
+            sw_rev (int): Software revision
+            config_fname (str): Filename to write fconfig into
+            req_dist_name_dict (dict): Dictionary containing key-value pairs of
+            req_distinguished_name section extensions, must contain extensions for
+            C, ST, L, O, OU, CN and emailAddress
+            cert_type (int): Certification type
+            bootcore (int): Booting core
+            load_addr (int): Load address of image
+            sha (int): Hash function
+
+        Returns:
+            str: Tool output
+        """
+        indata = tools.read_file(input_fname)
+        hashval = hashlib.sha512(indata).hexdigest()
+        sha_type = SHA_OIDS[sha]
+        with open(config_fname, 'w', encoding='utf-8') as outf:
+            print(f'''
+[ req ]
+distinguished_name     = req_distinguished_name
+x509_extensions        = v3_ca
+prompt                 = no
+dirstring_type         = nobmp
+
+[ req_distinguished_name ]
+C                      = {req_dist_name_dict['C']}
+ST                     = {req_dist_name_dict['ST']}
+L                      = {req_dist_name_dict['L']}
+O                      = {req_dist_name_dict['O']}
+OU                     = {req_dist_name_dict['OU']}
+CN                     = {req_dist_name_dict['CN']}
+emailAddress           = {req_dist_name_dict['emailAddress']}
+
+[ v3_ca ]
+basicConstraints = CA:true
+1.3.6.1.4.1.294.1.3=ASN1:SEQUENCE:swrv
+1.3.6.1.4.1.294.1.9=ASN1:SEQUENCE:ext_boot_info
+
+[swrv]
+swrv=INTEGER:{sw_rev}
+
+[ext_boot_info]
+extImgSize=INTEGER:{total_size}
+numComp=INTEGER:{num_comps}
+sbl=SEQUENCE:sbl
+sysfw=SEQUENCE:sysfw
+sysfw_data=SEQUENCE:sysfw_data
+{sysfw_inner_cert_ext_boot_sequence_string}
+{dm_data_ext_boot_sequence_string}
+
+[sbl]
+compType = INTEGER:1
+bootCore = INTEGER:16
+compOpts = INTEGER:0
+destAddr = FORMAT:HEX,OCT:{load_addr:08x}
+compSize = INTEGER:{imagesize_sbl}
+shaType  = OID:{sha_type}
+shaValue = FORMAT:HEX,OCT:{hashval_sbl}
+
+[sysfw]
+compType = INTEGER:2
+bootCore = INTEGER:0
+compOpts = INTEGER:0
+destAddr = FORMAT:HEX,OCT:{load_addr_sysfw:08x}
+compSize = INTEGER:{imagesize_sysfw}
+shaType  = OID:{sha_type}
+shaValue = FORMAT:HEX,OCT:{hashval_sysfw}
+
+[sysfw_data]
+compType = INTEGER:18
+bootCore = INTEGER:0
+compOpts = INTEGER:0
+destAddr = FORMAT:HEX,OCT:{load_addr_sysfw_data:08x}
+compSize = INTEGER:{imagesize_sysfw_data}
+shaType  = OID:{sha_type}
+shaValue = FORMAT:HEX,OCT:{hashval_sysfw_data}
+
+{sysfw_inner_cert_ext_boot_block}
+
+{dm_data_ext_boot_block}
+        ''', file=outf)
+        args = ['req', '-new', '-x509', '-key', key_fname, '-nodes',
+                '-outform', 'DER', '-out', cert_fname, '-config', config_fname,
+                '-sha512']
+        return self.run_cmd(*args)
+
     def fetch(self, method):
         """Fetch handler for openssl
 
diff --git a/tools/binman/cmdline.py b/tools/binman/cmdline.py
index 9632ec115e..39c61c2c03 100644
--- a/tools/binman/cmdline.py
+++ b/tools/binman/cmdline.py
@@ -126,6 +126,8 @@ controlled by a description in the board device tree.'''
             help='Comma-separated list of bintools to consider missing (for testing)')
     build_parser.add_argument('-i', '--image', type=str, action='append',
             help='Image filename to build (if not specified, build all)')
+    build_parser.add_argument('--ignore-dup-phandles', action='store_true',
+            help='Temporary option to ignore duplicate phandles')
     build_parser.add_argument('-I', '--indir', action='append',
             help='Add a path to the list of directories to use for input files')
     build_parser.add_argument('-m', '--map', action='store_true',
diff --git a/tools/binman/control.py b/tools/binman/control.py
index 68597c4e77..4594895581 100644
--- a/tools/binman/control.py
+++ b/tools/binman/control.py
@@ -9,7 +9,7 @@ from collections import OrderedDict
 import glob
 try:
     import importlib.resources
-except ImportError:
+except ImportError:  # pragma: no cover
     # for Python 3.6
     import importlib_resources
 import os
@@ -22,6 +22,8 @@ from binman import bintool
 from binman import cbfs_util
 from binman import elf
 from binman import entry
+from dtoc import fdt
+from dtoc import fdt_util
 from u_boot_pylib import command
 from u_boot_pylib import tools
 from u_boot_pylib import tout
@@ -56,8 +58,9 @@ def _ReadImageDesc(binman_node, use_expanded):
     images = OrderedDict()
     if 'multiple-images' in binman_node.props:
         for node in binman_node.subnodes:
-            images[node.name] = Image(node.name, node,
-                                      use_expanded=use_expanded)
+            if not node.name.startswith('template'):
+                images[node.name] = Image(node.name, node,
+                                          use_expanded=use_expanded)
     else:
         images['image'] = Image('image', binman_node, use_expanded=use_expanded)
     return images
@@ -110,12 +113,13 @@ def _ReadMissingBlobHelp():
     _FinishTag(tag, msg, result)
     return result
 
-def _ShowBlobHelp(path, text):
-    tout.warning('\n%s:' % path)
+def _ShowBlobHelp(level, path, text, fname):
+    tout.do_output(level, '%s (%s):' % (path, fname))
     for line in text.splitlines():
-        tout.warning('   %s' % line)
+        tout.do_output(level, '   %s' % line)
+    tout.do_output(level, '')
 
-def _ShowHelpForMissingBlobs(missing_list):
+def _ShowHelpForMissingBlobs(level, missing_list):
     """Show help for each missing blob to help the user take action
 
     Args:
@@ -130,10 +134,17 @@ def _ShowHelpForMissingBlobs(missing_list):
         tags = entry.GetHelpTags()
 
         # Show the first match help message
+        shown_help = False
         for tag in tags:
             if tag in missing_blob_help:
-                _ShowBlobHelp(entry._node.path, missing_blob_help[tag])
+                _ShowBlobHelp(level, entry._node.path, missing_blob_help[tag],
+                              entry.GetDefaultFilename())
+                shown_help = True
                 break
+        # Or a generic help message
+        if not shown_help:
+            _ShowBlobHelp(level, entry._node.path, "Missing blob",
+                          entry.GetDefaultFilename())
 
 def GetEntryModules(include_testing=True):
     """Get a set of entry class implementations
@@ -306,8 +317,8 @@ def BeforeReplace(image, allow_resize):
         image: Image to prepare
     """
     state.PrepareFromLoadedData(image)
-    image.LoadData()
     image.CollectBintools()
+    image.LoadData(decomp=False)
 
     # If repacking, drop the old offset/size values except for the original
     # ones, so we are only left with the constraints.
@@ -478,6 +489,44 @@ def SignEntries(image_fname, input_fname, privatekey_fname, algo, entry_paths,
 
     AfterReplace(image, allow_resize=True, write_map=write_map)
 
+def _ProcessTemplates(parent):
+    """Handle any templates in the binman description
+
+    Args:
+        parent: Binman node to process (typically /binman)
+
+    Returns:
+        bool: True if any templates were processed
+
+    Search though each target node looking for those with an 'insert-template'
+    property. Use that as a list of references to template nodes to use to
+    adjust the target node.
+
+    Processing involves copying each subnode of the template node into the
+    target node.
+
+    This is done recursively, so templates can be at any level of the binman
+    image, e.g. inside a section.
+
+    See 'Templates' in the Binman documnentation for details.
+    """
+    found = False
+    for node in parent.subnodes:
+        tmpl = fdt_util.GetPhandleList(node, 'insert-template')
+        if tmpl:
+            node.copy_subnodes_from_phandles(tmpl)
+            found = True
+
+        found |= _ProcessTemplates(node)
+    return found
+
+def _RemoveTemplates(parent):
+    """Remove any templates in the binman description
+    """
+    for node in parent.subnodes:
+        if node.name.startswith('template'):
+            node.Delete()
+
 def PrepareImagesAndDtbs(dtb_fname, select_images, update_fdt, use_expanded):
     """Prepare the images to be processed and select the device tree
 
@@ -520,6 +569,20 @@ def PrepareImagesAndDtbs(dtb_fname, select_images, update_fdt, use_expanded):
         raise ValueError("Device tree '%s' does not have a 'binman' "
                             "node" % dtb_fname)
 
+    if _ProcessTemplates(node):
+        dtb.Sync(True)
+        fname = tools.get_output_filename('u-boot.dtb.tmpl1')
+        tools.write_file(fname, dtb.GetContents())
+
+        _RemoveTemplates(node)
+        dtb.Sync(True)
+
+        # Rescan the dtb to pick up the new phandles
+        dtb.Scan()
+        node = _FindBinmanNode(dtb)
+        fname = tools.get_output_filename('u-boot.dtb.tmpl2')
+        tools.write_file(fname, dtb.GetContents())
+
     images = _ReadImageDesc(node, use_expanded)
 
     if select_images:
@@ -630,15 +693,15 @@ def ProcessImage(image, update_fdt, write_map, get_contents=True,
     missing_list = []
     image.CheckMissing(missing_list)
     if missing_list:
-        tout.warning("Image '%s' is missing external blobs and is non-functional: %s" %
-                     (image.name, ' '.join([e.name for e in missing_list])))
-        _ShowHelpForMissingBlobs(missing_list)
+        tout.error("Image '%s' is missing external blobs and is non-functional: %s\n" %
+                   (image.name, ' '.join([e.name for e in missing_list])))
+        _ShowHelpForMissingBlobs(tout.ERROR, missing_list)
 
     faked_list = []
     image.CheckFakedBlobs(faked_list)
     if faked_list:
         tout.warning(
-            "Image '%s' has faked external blobs and is non-functional: %s" %
+            "Image '%s' has faked external blobs and is non-functional: %s\n" %
             (image.name, ' '.join([os.path.basename(e.GetDefaultFilename())
                                    for e in faked_list])))
 
@@ -646,15 +709,15 @@ def ProcessImage(image, update_fdt, write_map, get_contents=True,
     image.CheckOptional(optional_list)
     if optional_list:
         tout.warning(
-            "Image '%s' is missing external blobs but is still functional: %s" %
+            "Image '%s' is missing optional external blobs but is still functional: %s\n" %
             (image.name, ' '.join([e.name for e in optional_list])))
-        _ShowHelpForMissingBlobs(optional_list)
+        _ShowHelpForMissingBlobs(tout.WARNING, optional_list)
 
     missing_bintool_list = []
     image.check_missing_bintools(missing_bintool_list)
     if missing_bintool_list:
         tout.warning(
-            "Image '%s' has missing bintools and is non-functional: %s" %
+            "Image '%s' has missing bintools and is non-functional: %s\n" %
             (image.name, ' '.join([os.path.basename(bintool.name)
                                    for bintool in missing_bintool_list])))
     return any([missing_list, faked_list, missing_bintool_list])
@@ -754,6 +817,10 @@ def Binman(args):
         cbfs_util.VERBOSE = args.verbosity > 2
         state.use_fake_dtb = args.fake_dtb
 
+        # Temporary hack
+        if args.ignore_dup_phandles: # pragma: no cover
+            fdt.IGNORE_DUP_PHANDLES = True
+
         # Normally we replace the 'u-boot' etype with 'u-boot-expanded', etc.
         # When running tests this can be disabled using this flag. When not
         # updating the FDT in image, it is not needed by binman, but we use it
@@ -799,7 +866,7 @@ def Binman(args):
             # This can only be True if -M is provided, since otherwise binman
             # would have raised an error already
             if invalid:
-                msg = '\nSome images are invalid'
+                msg = 'Some images are invalid'
                 if args.ignore_missing:
                     tout.warning(msg)
                 else:
diff --git a/tools/binman/elf.py b/tools/binman/elf.py
index 5816284c32..2ecc95f7eb 100644
--- a/tools/binman/elf.py
+++ b/tools/binman/elf.py
@@ -248,6 +248,9 @@ def LookupAndWriteSymbols(elf_fname, entry, section, is_elf=False,
         entry: Entry to process
         section: Section which can be used to lookup symbol values
         base_sym: Base symbol marking the start of the image
+
+    Returns:
+        int: Number of symbols written
     """
     if not base_sym:
         base_sym = '__image_copy_start'
@@ -269,12 +272,13 @@ def LookupAndWriteSymbols(elf_fname, entry, section, is_elf=False,
 
     if not syms:
         tout.debug('LookupAndWriteSymbols: no syms')
-        return
+        return 0
     base = syms.get(base_sym)
     if not base and not is_elf:
         tout.debug('LookupAndWriteSymbols: no base')
-        return
+        return 0
     base_addr = 0 if is_elf else base.address
+    count = 0
     for name, sym in syms.items():
         if name.startswith('_binman'):
             msg = ("Section '%s': Symbol '%s'\n   in entry '%s'" %
@@ -307,6 +311,11 @@ def LookupAndWriteSymbols(elf_fname, entry, section, is_elf=False,
                        (msg, name, offset, value, len(value_bytes)))
             entry.data = (entry.data[:offset] + value_bytes +
                         entry.data[offset + sym.size:])
+            count += 1
+    if count:
+        tout.detail(
+            f"Section '{section.GetPath()}': entry '{entry.GetPath()}' : {count} symbols")
+    return count
 
 def GetSymbolValue(sym, data, msg):
     """Get the value of a symbol
@@ -438,13 +447,15 @@ def DecodeElf(data, location):
     Returns:
         ElfInfo object containing information about the decoded ELF file
     """
+    if not ELF_TOOLS:
+        raise ValueError("Python: No module named 'elftools'")
     file_size = len(data)
     with io.BytesIO(data) as fd:
         elf = ELFFile(fd)
-        data_start = 0xffffffff;
-        data_end = 0;
-        mem_end = 0;
-        virt_to_phys = 0;
+        data_start = 0xffffffff
+        data_end = 0
+        mem_end = 0
+        virt_to_phys = 0
 
         for i in range(elf.num_segments()):
             segment = elf.get_segment(i)
diff --git a/tools/binman/elf_test.py b/tools/binman/elf_test.py
index c98083961b..e3dee79d06 100644
--- a/tools/binman/elf_test.py
+++ b/tools/binman/elf_test.py
@@ -141,7 +141,8 @@ class TestElf(unittest.TestCase):
         entry = FakeEntry(10)
         section = FakeSection()
         elf_fname = self.ElfTestFile('u_boot_binman_syms_bad')
-        elf.LookupAndWriteSymbols(elf_fname, entry, section)
+        count = elf.LookupAndWriteSymbols(elf_fname, entry, section)
+        self.assertEqual(0, count)
 
     def testBadSymbolSize(self):
         """Test that an attempt to use an 8-bit symbol are detected
@@ -162,7 +163,7 @@ class TestElf(unittest.TestCase):
     def testNoValue(self):
         """Test the case where we have no value for the symbol
 
-        This should produce -1 values for all thress symbols, taking up the
+        This should produce -1 values for all three symbols, taking up the
         first 16 bytes of the image.
         """
         if not elf.ELF_TOOLS:
@@ -170,7 +171,8 @@ class TestElf(unittest.TestCase):
         entry = FakeEntry(28)
         section = FakeSection(sym_value=None)
         elf_fname = self.ElfTestFile('u_boot_binman_syms')
-        elf.LookupAndWriteSymbols(elf_fname, entry, section)
+        count = elf.LookupAndWriteSymbols(elf_fname, entry, section)
+        self.assertEqual(5, count)
         expected = (struct.pack('<L', elf.BINMAN_SYM_MAGIC_VALUE) +
                     tools.get_bytes(255, 20) +
                     tools.get_bytes(ord('a'), 4))
@@ -253,8 +255,20 @@ class TestElf(unittest.TestCase):
             fname = self.ElfTestFile('embed_data')
             with self.assertRaises(ValueError) as e:
                 elf.GetSymbolFileOffset(fname, ['embed_start', 'embed_end'])
-            self.assertIn("Python: No module named 'elftools'",
-                      str(e.exception))
+            with self.assertRaises(ValueError) as e:
+                elf.DecodeElf(tools.read_file(fname), 0xdeadbeef)
+            with self.assertRaises(ValueError) as e:
+                elf.GetFileOffset(fname, 0xdeadbeef)
+            with self.assertRaises(ValueError) as e:
+                elf.GetSymbolFromAddress(fname, 0xdeadbeef)
+            with self.assertRaises(ValueError) as e:
+                entry = FakeEntry(10)
+                section = FakeSection()
+                elf.LookupAndWriteSymbols(fname, entry, section, True)
+
+            self.assertIn(
+                "Section 'section_path': entry 'entry_path': Cannot write symbols to an ELF file without Python elftools",
+                str(e.exception))
         finally:
             elf.ELF_TOOLS = old_val
 
@@ -369,6 +383,11 @@ class TestElf(unittest.TestCase):
             elf.GetSymbolOffset(fname, 'embed')
         self.assertIn('__image_copy_start', str(e.exception))
 
+    def test_get_symbol_address(self):
+        fname = self.ElfTestFile('embed_data')
+        addr = elf.GetSymbolAddress(fname, 'region_size')
+        self.assertEqual(0, addr)
+
 
 if __name__ == '__main__':
     unittest.main()
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index b71af801fd..e7dfe6b2a3 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -468,6 +468,92 @@ updating the EC on startup via software sync.
 
 
 
+.. _etype_encrypted:
+
+Entry: encrypted: Externally built encrypted binary blob
+--------------------------------------------------------
+
+This entry provides the functionality to include information about how to
+decrypt an encrypted binary. This information is added to the
+resulting device tree by adding a new cipher node in the entry's parent
+node (i.e. the binary).
+
+The key that must be used to decrypt the binary is either directly embedded
+in the device tree or indirectly by specifying a key source. The key source
+can be used as an id of a key that is stored in an external device.
+
+Using an embedded key
+~~~~~~~~~~~~~~~~~~~~~
+
+This is an example using an embedded key::
+
+    blob-ext {
+        filename = "encrypted-blob.bin";
+    };
+
+    encrypted {
+        algo = "aes256-gcm";
+        iv-filename = "encrypted-blob.bin.iv";
+        key-filename = "encrypted-blob.bin.key";
+    };
+
+This entry generates the following device tree structure form the example
+above::
+
+    data = [...]
+    cipher {
+        algo = "aes256-gcm";
+        key = <0x...>;
+        iv = <0x...>;
+    };
+
+The data property is generated by the blob-ext etype, the cipher node and
+its content is generated by this etype.
+
+Using an external key
+~~~~~~~~~~~~~~~~~~~~~
+
+Instead of embedding the key itself into the device tree, it is also
+possible to address an externally stored key by specifying a 'key-source'
+instead of the 'key'::
+
+    blob-ext {
+        filename = "encrypted-blob.bin";
+    };
+
+    encrypted {
+        algo = "aes256-gcm";
+        iv-filename = "encrypted-blob.bin.iv";
+        key-source = "external-key-id";
+    };
+
+This entry generates the following device tree structure form the example
+above::
+
+    data = [...]
+    cipher {
+        algo = "aes256-gcm";
+        key-source = "external-key-id";
+        iv = <0x...>;
+    };
+
+Properties
+~~~~~~~~~~
+
+Properties / Entry arguments:
+    - algo: The encryption algorithm. Currently no algorithm is supported
+            out-of-the-box. Certain algorithms will be added in future
+            patches.
+    - iv-filename: The name of the file containing the initialization
+                   vector (in short iv). See
+                   https://en.wikipedia.org/wiki/Initialization_vector
+    - key-filename: The name of the file containing the key. Either
+                    key-filename or key-source must be provided.
+    - key-source: The key that should be used. Either key-filename or
+                  key-source must be provided.
+
+
+
 .. _etype_fdtmap:
 
 Entry: fdtmap: An entry which contains an FDT map
@@ -615,6 +701,12 @@ The top-level 'fit' node supports the following special properties:
         `of-list` meaning that `-a of-list="dtb1 dtb2..."` should be passed
         to binman.
 
+    fit,fdt-list-val
+        As an alternative to fit,fdt-list the list of device tree files
+        can be provided in this property as a string list, e.g.::
+
+            fit,fdt-list-val = "dtb1", "dtb2";
+
 Substitutions
 ~~~~~~~~~~~~~
 
@@ -1658,6 +1750,119 @@ by setting the size of the entry to something larger than the text.
 
 
 
+.. _etype_ti_board_config:
+
+Entry: ti-board-config: An entry containing a TI schema validated board config binary
+-------------------------------------------------------------------------------------
+
+This etype supports generation of two kinds of board configuration
+binaries: singular board config binary as well as combined board config
+binary.
+
+Properties / Entry arguments:
+    - config-file: File containing board configuration data in YAML
+    - schema-file: File containing board configuration YAML schema against
+      which the config file is validated
+
+Output files:
+    - board config binary: File containing board configuration binary
+
+These above parameters are used only when the generated binary is
+intended to be a single board configuration binary. Example::
+
+    my-ti-board-config {
+        ti-board-config {
+            config = "board-config.yaml";
+            schema = "schema.yaml";
+        };
+    };
+
+To generate a combined board configuration binary, we pack the
+needed individual binaries into a ti-board-config binary. In this case,
+the available supported subnode names are board-cfg, pm-cfg, sec-cfg and
+rm-cfg. The final binary is prepended with a header containing details about
+the included board config binaries. Example::
+
+    my-combined-ti-board-config {
+        ti-board-config {
+            board-cfg {
+                config = "board-cfg.yaml";
+                schema = "schema.yaml";
+            };
+            sec-cfg {
+                config = "sec-cfg.yaml";
+                schema = "schema.yaml";
+            };
+        }
+    }
+
+
+
+.. _etype_ti_secure:
+
+Entry: ti-secure: Entry containing a TI x509 certificate binary
+---------------------------------------------------------------
+
+Properties / Entry arguments:
+    - content: List of phandles to entries to sign
+    - keyfile: Filename of file containing key to sign binary with
+    - sha: Hash function to be used for signing
+
+Output files:
+    - input.<unique_name> - input file passed to openssl
+    - config.<unique_name> - input file generated for openssl (which is
+      used as the config file)
+    - cert.<unique_name> - output file generated by openssl (which is
+      used as the entry contents)
+
+openssl signs the provided data, using the TI templated config file and
+writes the signature in this entry. This allows verification that the
+data is genuine.
+
+
+
+.. _etype_ti_secure_rom:
+
+Entry: ti-secure-rom: Entry containing a TI x509 certificate binary for images booted by ROM
+--------------------------------------------------------------------------------------------
+
+Properties / Entry arguments:
+    - keyfile: Filename of file containing key to sign binary with
+    - combined: boolean if device follows combined boot flow
+    - countersign: boolean if device contains countersigned system firmware
+    - load: load address of SPL
+    - sw-rev: software revision
+    - sha: Hash function to be used for signing
+    - core: core on which bootloader runs, valid cores are 'secure' and 'public'
+    - content: phandle of SPL in case of legacy bootflow or phandles of component binaries
+      in case of combined bootflow
+
+The following properties are only for generating a combined bootflow binary:
+    - sysfw-inner-cert: boolean if binary contains sysfw inner certificate
+    - dm-data: boolean if binary contains dm-data binary
+    - content-sbl: phandle of SPL binary
+    - content-sysfw: phandle of sysfw binary
+    - content-sysfw-data: phandle of sysfw-data or tifs-data binary
+    - content-sysfw-inner-cert (optional): phandle of sysfw inner certificate binary
+    - content-dm-data (optional): phandle of dm-data binary
+    - load-sysfw: load address of sysfw binary
+    - load-sysfw-data: load address of sysfw-data or tifs-data binary
+    - load-sysfw-inner-cert (optional): load address of sysfw inner certificate binary
+    - load-dm-data (optional): load address of dm-data binary
+
+Output files:
+    - input.<unique_name> - input file passed to openssl
+    - config.<unique_name> - input file generated for openssl (which is
+      used as the config file)
+    - cert.<unique_name> - output file generated by openssl (which is
+      used as the entry contents)
+
+openssl signs the provided data, using the TI templated config file and
+writes the signature in this entry. This allows verification that the
+data is genuine.
+
+
+
 .. _etype_u_boot:
 
 Entry: u-boot: U-Boot flat binary
@@ -1912,6 +2117,45 @@ binman uses that to look up symbols to write into the SPL binary.
 
 
 
+.. _etype_u_boot_spl_pubkey_dtb:
+
+Entry: u-boot-spl-pubkey-dtb: U-Boot SPL device tree including public key
+-------------------------------------------------------------------------
+
+Properties / Entry arguments:
+    - key-name-hint: Public key name without extension (.crt).
+                Default is determined by underlying
+                bintool (fdt_add_pubkey), usually 'key'.
+    - algo: (Optional) Algorithm used for signing. Default is determined by
+            underlying bintool (fdt_add_pubkey), usually 'sha1,rsa2048'
+    - required: (Optional) If present this indicates that the key must be
+                verified for the image / configuration to be
+                considered valid
+
+The following example shows an image containing an SPL which
+is packed together with the dtb. Binman will add a signature
+node to the dtb.
+
+Example node::
+
+    image {
+    ...
+        spl {
+            filename = "spl.bin"
+
+            u-boot-spl-nodtb {
+            };
+            u-boot-spl-pubkey-dtb {
+                algo = "sha384,rsa4096";
+                required = "conf";
+                key-name-hint = "dev";
+            };
+        };
+    ...
+    }
+
+
+
 .. _etype_u_boot_spl_with_ucode_ptr:
 
 Entry: u-boot-spl-with-ucode-ptr: U-Boot SPL with embedded microcode pointer
@@ -2423,3 +2667,78 @@ may be used instead.
 
 
 
+.. _etype_xilinx_bootgen:
+
+Entry: xilinx-bootgen: Signed SPL boot image for Xilinx ZynqMP devices
+----------------------------------------------------------------------
+
+Properties / Entry arguments:
+    - auth-params: (Optional) Authentication parameters passed to bootgen
+    - fsbl-config: (Optional) FSBL parameters passed to bootgen
+    - keysrc-enc: (Optional) Key source when using decryption engine
+    - pmufw-filename: Filename of PMU firmware. Default: pmu-firmware.elf
+    - psk-key-name-hint: Name of primary secret key to use for signing the
+                         secondardy public key. Format: .pem file
+    - ssk-key-name-hint: Name of secondardy secret key to use for signing
+                         the boot image. Format: .pem file
+
+The etype is used to create a boot image for Xilinx ZynqMP
+devices.
+
+Information for signed images:
+
+In AMD/Xilinx SoCs, two pairs of public and secret keys are used
+- primary and secondary. The function of the primary public/secret key pair
+is to authenticate the secondary public/secret key pair.
+The function of the secondary key is to sign/verify the boot image. [1]
+
+AMD/Xilinx uses the following terms for private/public keys [1]:
+
+    PSK = Primary Secret Key (Used to sign Secondary Public Key)
+    PPK = Primary Public Key (Used to verify Secondary Public Key)
+    SSK = Secondary Secret Key (Used to sign the boot image/partitions)
+    SPK = Used to verify the actual boot image
+
+The following example builds a signed boot image. The fuses of
+the primary public key (ppk) should be fused together with the RSA_EN flag.
+
+Example node::
+
+    spl {
+        filename = "boot.signed.bin";
+
+        xilinx-bootgen {
+            psk-key-name-hint = "psk0";
+            ssk-key-name-hint = "ssk0";
+            auth-params = "ppk_select=0", "spk_id=0x00000000";
+
+            u-boot-spl-nodtb {
+            };
+            u-boot-spl-pubkey-dtb {
+                algo = "sha384,rsa4096";
+                required = "conf";
+                key-name-hint = "dev";
+            };
+        };
+    };
+
+For testing purposes, e.g. if no RSA_EN should be fused, one could add
+the "bh_auth_enable" flag in the fsbl-config field. This will skip the
+verification of the ppk fuses and boot the image, even if ppk hash is
+invalid.
+
+Example node::
+
+    xilinx-bootgen {
+        psk-key-name-hint = "psk0";
+        psk-key-name-hint = "ssk0";
+        ...
+        fsbl-config = "bh_auth_enable";
+        ...
+    };
+
+[1] https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide/Using-Authentication
+
+
+
+
diff --git a/tools/binman/entry.py b/tools/binman/entry.py
index 39456906a4..42e0b7b914 100644
--- a/tools/binman/entry.py
+++ b/tools/binman/entry.py
@@ -158,6 +158,7 @@ class Entry(object):
         self.offset_from_elf = None
         self.preserve = False
         self.build_done = False
+        self.no_write_symbols = False
 
     @staticmethod
     def FindEntryClass(etype, expanded):
@@ -321,6 +322,7 @@ class Entry(object):
                                                              'offset-from-elf')
 
         self.preserve = fdt_util.GetBool(self._node, 'preserve')
+        self.no_write_symbols = fdt_util.GetBool(self._node, 'no-write-symbols')
 
     def GetDefaultFilename(self):
         return None
@@ -472,6 +474,9 @@ class Entry(object):
     def ObtainContents(self, skip_entry=None, fake_size=0):
         """Figure out the contents of an entry.
 
+        For missing blobs (where allow-missing is enabled), the contents are set
+        to b'' and self.missing is set to True.
+
         Args:
             skip_entry (Entry): Entry to skip when obtaining section contents
             fake_size (int): Size of fake file to create if needed
@@ -695,7 +700,7 @@ class Entry(object):
         Args:
           section: Section containing the entry
         """
-        if self.auto_write_symbols:
+        if self.auto_write_symbols and not self.no_write_symbols:
             # Check if we are writing symbols into an ELF file
             is_elf = self.GetDefaultFilename() == self.elf_fname
             elf.LookupAndWriteSymbols(self.elf_fname, self, section.GetImage(),
@@ -1309,10 +1314,6 @@ features to produce new behaviours.
         """
         data = b''
         for entry in entries:
-            # First get the input data and put it in a file. If not available,
-            # try later.
-            if not entry.ObtainContents(fake_size=fake_size):
-                return None, None, None
             data += entry.GetData()
         uniq = self.GetUniqueName()
         fname = tools.get_output_filename(f'{prefix}.{uniq}')
diff --git a/tools/binman/etype/blob_dtb.py b/tools/binman/etype/blob_dtb.py
index 6a3fbc4775..d543de9f75 100644
--- a/tools/binman/etype/blob_dtb.py
+++ b/tools/binman/etype/blob_dtb.py
@@ -38,7 +38,7 @@ class Entry_blob_dtb(Entry_blob):
             self.Raise("Invalid prepend in '%s': '%s'" %
                        (self._node.name, self.prepend))
 
-    def ObtainContents(self):
+    def ObtainContents(self, fake_size=0):
         """Get the device-tree from the list held by the 'state' module"""
         self._filename = self.GetDefaultFilename()
         self._pathname, _ = state.GetFdtContents(self.GetFdtEtype())
diff --git a/tools/binman/etype/blob_phase.py b/tools/binman/etype/blob_phase.py
index b937158756..951d993405 100644
--- a/tools/binman/etype/blob_phase.py
+++ b/tools/binman/etype/blob_phase.py
@@ -52,3 +52,8 @@ class Entry_blob_phase(Entry_section):
 
         # Read entries again, now that we have some
         self.ReadEntries()
+
+        # Propagate the no-write-symbols property
+        if self.no_write_symbols:
+            for entry in self._entries.values():
+                entry.no_write_symbols = True
diff --git a/tools/binman/etype/encrypted.py b/tools/binman/etype/encrypted.py
new file mode 100644
index 0000000000..53d0e76bab
--- /dev/null
+++ b/tools/binman/etype/encrypted.py
@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2023 Weidmüller Interface GmbH & Co. KG
+# Written by Christian Taedcke <christian.taedcke@weidmueller.com>
+#
+# Entry-type module for cipher information of encrypted blobs/binaries
+#
+
+from binman.etype.collection import Entry
+from dtoc import fdt_util
+from u_boot_pylib import tools
+
+# This is imported if needed
+state = None
+
+
+class Entry_encrypted(Entry):
+    """Externally built encrypted binary blob
+
+    This entry provides the functionality to include information about how to
+    decrypt an encrypted binary. This information is added to the
+    resulting device tree by adding a new cipher node in the entry's parent
+    node (i.e. the binary).
+
+    The key that must be used to decrypt the binary is either directly embedded
+    in the device tree or indirectly by specifying a key source. The key source
+    can be used as an id of a key that is stored in an external device.
+
+    Using an embedded key
+    ~~~~~~~~~~~~~~~~~~~~~
+
+    This is an example using an embedded key::
+
+        blob-ext {
+            filename = "encrypted-blob.bin";
+        };
+
+        encrypted {
+            algo = "aes256-gcm";
+            iv-filename = "encrypted-blob.bin.iv";
+            key-filename = "encrypted-blob.bin.key";
+        };
+
+    This entry generates the following device tree structure form the example
+    above::
+
+        data = [...]
+        cipher {
+            algo = "aes256-gcm";
+            key = <0x...>;
+            iv = <0x...>;
+        };
+
+    The data property is generated by the blob-ext etype, the cipher node and
+    its content is generated by this etype.
+
+    Using an external key
+    ~~~~~~~~~~~~~~~~~~~~~
+
+    Instead of embedding the key itself into the device tree, it is also
+    possible to address an externally stored key by specifying a 'key-source'
+    instead of the 'key'::
+
+        blob-ext {
+            filename = "encrypted-blob.bin";
+        };
+
+        encrypted {
+            algo = "aes256-gcm";
+            iv-filename = "encrypted-blob.bin.iv";
+            key-source = "external-key-id";
+        };
+
+    This entry generates the following device tree structure form the example
+    above::
+
+        data = [...]
+        cipher {
+            algo = "aes256-gcm";
+            key-source = "external-key-id";
+            iv = <0x...>;
+        };
+
+    Properties
+    ~~~~~~~~~~
+
+    Properties / Entry arguments:
+        - algo: The encryption algorithm. Currently no algorithm is supported
+                out-of-the-box. Certain algorithms will be added in future
+                patches.
+        - iv-filename: The name of the file containing the initialization
+                       vector (in short iv). See
+                       https://en.wikipedia.org/wiki/Initialization_vector
+        - key-filename: The name of the file containing the key. Either
+                        key-filename or key-source must be provided.
+        - key-source: The key that should be used. Either key-filename or
+                      key-source must be provided.
+    """
+
+    def __init__(self, section, etype, node):
+        # Put this here to allow entry-docs and help to work without libfdt
+        global state
+        from binman import state
+
+        super().__init__(section, etype, node)
+        self.required_props = ['algo', 'iv-filename']
+        self._algo = None
+        self._iv_filename = None
+        self._key_name_hint = None
+        self._key_filename = None
+
+    def ReadNode(self):
+        super().ReadNode()
+
+        self._algo = fdt_util.GetString(self._node, 'algo')
+        self._iv_filename = fdt_util.GetString(self._node, 'iv-filename')
+        self._key_filename = fdt_util.GetString(self._node, 'key-filename')
+        self._key_source = fdt_util.GetString(self._node, 'key-source')
+
+        if self._key_filename is None and self._key_source is None:
+            self.Raise("Provide either 'key-filename' or 'key-source'")
+
+    def gen_entries(self):
+        super().gen_entries()
+
+        iv_filename = tools.get_input_filename(self._iv_filename)
+        iv = tools.read_file(iv_filename, binary=True)
+
+        cipher_node = state.AddSubnode(self._node.parent, "cipher")
+        cipher_node.AddString("algo", self._algo)
+        cipher_node.AddData("iv", iv)
+
+        if self._key_filename:
+            key_filename = tools.get_input_filename(self._key_filename)
+            key = tools.read_file(key_filename, binary=True)
+            cipher_node.AddData("key", key)
+
+        if self._key_source:
+            cipher_node.AddString("key-source", self._key_source)
diff --git a/tools/binman/etype/fit.py b/tools/binman/etype/fit.py
index c395706ece..2c14b15b03 100644
--- a/tools/binman/etype/fit.py
+++ b/tools/binman/etype/fit.py
@@ -81,6 +81,12 @@ class Entry_fit(Entry_section):
             `of-list` meaning that `-a of-list="dtb1 dtb2..."` should be passed
             to binman.
 
+        fit,fdt-list-val
+            As an alternative to fit,fdt-list the list of device tree files
+            can be provided in this property as a string list, e.g.::
+
+                fit,fdt-list-val = "dtb1", "dtb2";
+
     Substitutions
     ~~~~~~~~~~~~~
 
@@ -361,6 +367,9 @@ class Entry_fit(Entry_section):
                 [EntryArg(self._fit_list_prop.value, str)])
             if fdts is not None:
                 self._fdts = fdts.split()
+        else:
+            self._fdts = fdt_util.GetStringList(self._node, 'fit,fdt-list-val')
+
         self._fit_default_dt = self.GetEntryArgsOrProps([EntryArg('default-dt',
                                                                   str)])[0]
 
@@ -833,6 +842,13 @@ class Entry_fit(Entry_section):
         for entry in self._priv_entries.values():
             entry.CheckMissing(missing_list)
 
+    def CheckOptional(self, optional_list):
+        # We must use our private entry list for this since generator nodes
+        # which are removed from self._entries will otherwise not show up as
+        # optional
+        for entry in self._priv_entries.values():
+            entry.CheckOptional(optional_list)
+
     def CheckEntries(self):
         pass
 
diff --git a/tools/binman/etype/mkimage.py b/tools/binman/etype/mkimage.py
index e028c44070..6ae5d0c8a4 100644
--- a/tools/binman/etype/mkimage.py
+++ b/tools/binman/etype/mkimage.py
@@ -8,10 +8,11 @@
 from collections import OrderedDict
 
 from binman.entry import Entry
+from binman.etype.section import Entry_section
 from dtoc import fdt_util
 from u_boot_pylib import tools
 
-class Entry_mkimage(Entry):
+class Entry_mkimage(Entry_section):
     """Binary produced by mkimage
 
     Properties / Entry arguments:
@@ -121,54 +122,67 @@ class Entry_mkimage(Entry):
     """
     def __init__(self, section, etype, node):
         super().__init__(section, etype, node)
-        self._multiple_data_files = fdt_util.GetBool(self._node, 'multiple-data-files')
-        self._mkimage_entries = OrderedDict()
         self._imagename = None
-        self._filename = fdt_util.GetString(self._node, 'filename')
-        self.align_default = None
+        self._multiple_data_files = False
 
     def ReadNode(self):
         super().ReadNode()
+        self._multiple_data_files = fdt_util.GetBool(self._node,
+                                                     'multiple-data-files')
         self._args = fdt_util.GetArgs(self._node, 'args')
         self._data_to_imagename = fdt_util.GetBool(self._node,
                                                    'data-to-imagename')
         if self._data_to_imagename and self._node.FindNode('imagename'):
             self.Raise('Cannot use both imagename node and data-to-imagename')
-        self.ReadEntries()
 
     def ReadEntries(self):
         """Read the subnodes to find out what should go in this image"""
         for node in self._node.subnodes:
-            entry = Entry.Create(self, node)
+            if self.IsSpecialSubnode(node):
+                continue
+            entry = Entry.Create(self, node,
+                                 expanded=self.GetImage().use_expanded,
+                                 missing_etype=self.GetImage().missing_etype)
             entry.ReadNode()
+            entry.SetPrefix(self._name_prefix)
             if entry.name == 'imagename':
                 self._imagename = entry
             else:
-                self._mkimage_entries[entry.name] = entry
+                self._entries[entry.name] = entry
 
-    def ObtainContents(self):
+    def BuildSectionData(self, required):
+        """Build mkimage entry contents
+
+        Runs mkimage to build the entry contents
+
+        Args:
+            required (bool): True if the data must be present, False if it is OK
+                to return None
+
+        Returns:
+            bytes: Contents of the section
+        """
         # Use a non-zero size for any fake files to keep mkimage happy
         # Note that testMkimageImagename() relies on this 'mkimage' parameter
         fake_size = 1024
         if self._multiple_data_files:
             fnames = []
             uniq = self.GetUniqueName()
-            for entry in self._mkimage_entries.values():
-                if not entry.ObtainContents(fake_size=fake_size):
-                    return False
-                if entry._pathname:
-                    fnames.append(entry._pathname)
+            for entry in self._entries.values():
+                # Put the contents in a temporary file
+                ename = f'mkimage-in-{uniq}-{entry.name}'
+                fname = tools.get_output_filename(ename)
+                data = entry.GetData(required)
+                tools.write_file(fname, data)
+                fnames.append(fname)
             input_fname = ":".join(fnames)
+            data = b''
         else:
             data, input_fname, uniq = self.collect_contents_to_file(
-                self._mkimage_entries.values(), 'mkimage', fake_size)
-            if data is None:
-                return False
+                self._entries.values(), 'mkimage', fake_size)
         if self._imagename:
             image_data, imagename_fname, _ = self.collect_contents_to_file(
                 [self._imagename], 'mkimage-n', 1024)
-            if image_data is None:
-                return False
         outfile = self._filename if self._filename else 'mkimage-out.%s' % uniq
         output_fname = tools.get_output_filename(outfile)
 
@@ -176,8 +190,7 @@ class Entry_mkimage(Entry):
         self.CheckMissing(missing_list)
         self.missing = bool(missing_list)
         if self.missing:
-            self.SetContents(b'')
-            return self.allow_missing
+            return b''
 
         args = ['-d', input_fname]
         if self._data_to_imagename:
@@ -186,71 +199,58 @@ class Entry_mkimage(Entry):
             args += ['-n', imagename_fname]
         args += self._args + [output_fname]
         if self.mkimage.run_cmd(*args) is not None:
-            self.SetContents(tools.read_file(output_fname))
+            return tools.read_file(output_fname)
         else:
             # Bintool is missing; just use the input data as the output
             self.record_missing_bintool(self.mkimage)
-            self.SetContents(data)
-
-        return True
+            return data
 
     def GetEntries(self):
         # Make a copy so we don't change the original
-        entries = OrderedDict(self._mkimage_entries)
+        entries = OrderedDict(self._entries)
         if self._imagename:
             entries['imagename'] = self._imagename
         return entries
 
-    def SetAllowMissing(self, allow_missing):
-        """Set whether a section allows missing external blobs
+    def AddBintools(self, btools):
+        super().AddBintools(btools)
+        self.mkimage = self.AddBintool(btools, 'mkimage')
 
-        Args:
-            allow_missing: True if allowed, False if not allowed
-        """
-        self.allow_missing = allow_missing
-        for entry in self._mkimage_entries.values():
-            entry.SetAllowMissing(allow_missing)
-        if self._imagename:
-            self._imagename.SetAllowMissing(allow_missing)
+    def CheckEntries(self):
+        pass
 
-    def SetAllowFakeBlob(self, allow_fake):
-        """Set whether the sub nodes allows to create a fake blob
+    def ProcessContents(self):
+        # The blob may have changed due to WriteSymbols()
+        ok = super().ProcessContents()
+        data = self.BuildSectionData(True)
+        ok2 = self.ProcessContentsUpdate(data)
+        return ok and ok2
 
-        Args:
-            allow_fake: True if allowed, False if not allowed
-        """
-        for entry in self._mkimage_entries.values():
-            entry.SetAllowFakeBlob(allow_fake)
-        if self._imagename:
-            self._imagename.SetAllowFakeBlob(allow_fake)
+    def SetImagePos(self, image_pos):
+        """Set the position in the image
 
-    def CheckMissing(self, missing_list):
-        """Check if any entries in this section have missing external blobs
+        This sets each subentry's offsets, sizes and positions-in-image
+        according to where they ended up in the packed mkimage file.
 
-        If there are missing (non-optional) blobs, the entries are added to the
-        list
+        NOTE: This assumes a legacy mkimage and assumes that the images are
+        written to the output in order. SoC-specific mkimage handling may not
+        conform to this, in which case these values may be wrong.
 
         Args:
-            missing_list: List of Entry objects to be added to
+            image_pos (int): Position of this entry in the image
         """
-        for entry in self._mkimage_entries.values():
-            entry.CheckMissing(missing_list)
-        if self._imagename:
-            self._imagename.CheckMissing(missing_list)
+        # The mkimage header consists of 0x40 bytes, following by a table of
+        # offsets for each file
+        upto = 0x40
 
-    def CheckFakedBlobs(self, faked_blobs_list):
-        """Check if any entries in this section have faked external blobs
+        # Skip the 0-terminated list of offsets (assume a single image)
+        upto += 4 + 4
+        for entry in self.GetEntries().values():
+            entry.SetOffsetSize(upto, None)
 
-        If there are faked blobs, the entries are added to the list
+            # Give up if any entries lack a size
+            if entry.size is None:
+                return
+            upto += entry.size
 
-        Args:
-            faked_blobs_list: List of Entry objects to be added to
-        """
-        for entry in self._mkimage_entries.values():
-            entry.CheckFakedBlobs(faked_blobs_list)
-        if self._imagename:
-            self._imagename.CheckFakedBlobs(faked_blobs_list)
-
-    def AddBintools(self, btools):
-        super().AddBintools(btools)
-        self.mkimage = self.AddBintool(btools, 'mkimage')
+        super().SetImagePos(image_pos)
diff --git a/tools/binman/etype/pre_load.py b/tools/binman/etype/pre_load.py
index bd3545bffc..2e4c72359f 100644
--- a/tools/binman/etype/pre_load.py
+++ b/tools/binman/etype/pre_load.py
@@ -81,7 +81,8 @@ class Entry_pre_load(Entry_collection):
 
     def ReadNode(self):
         super().ReadNode()
-        self.key_path, = self.GetEntryArgsOrProps([EntryArg('pre-load-key-path', str)])
+        self.key_path, = self.GetEntryArgsOrProps(
+            [EntryArg('pre-load-key-path', str)])
         if self.key_path is None:
             self.key_path = ''
 
@@ -98,8 +99,7 @@ class Entry_pre_load(Entry_collection):
             self.Raise(sign_name + " is not supported")
 
         # Read the key
-        with open(key_name, 'rb') as pem:
-            key = RSA.import_key(pem.read())
+        key = RSA.import_key(tools.read_file(key_name))
 
         # Check if the key has the expected size
         if key.size_in_bytes() != RSAS[sign_name]:
diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py
index c36edd1350..fb49e85a76 100644
--- a/tools/binman/etype/section.py
+++ b/tools/binman/etype/section.py
@@ -168,6 +168,7 @@ class Entry_section(Entry):
         self._end_4gb = False
         self._ignore_missing = False
         self._filename = None
+        self.align_default = 0
 
     def IsSpecialSubnode(self, node):
         """Check if a node is a special one used by the section itself
@@ -178,7 +179,8 @@ class Entry_section(Entry):
         Returns:
             bool: True if the node is a special one, else False
         """
-        return node.name.startswith('hash') or node.name.startswith('signature')
+        start_list = ('cipher', 'hash', 'signature', 'template')
+        return any(node.name.startswith(name) for name in start_list)
 
     def ReadNode(self):
         """Read properties from the section node"""
@@ -315,12 +317,15 @@ class Entry_section(Entry):
         This should be overridden by subclasses which want to build their own
         data structure for the section.
 
+        Missing entries will have be given empty (or fake) data, so are
+        processed normally here.
+
         Args:
             required: True if the data must be present, False if it is OK to
                 return None
 
         Returns:
-            Contents of the section (bytes)
+            Contents of the section (bytes), None if not available
         """
         section_data = bytearray()
 
@@ -710,6 +715,33 @@ class Entry_section(Entry):
     def GetEntryContents(self, skip_entry=None):
         """Call ObtainContents() for each entry in the section
 
+        The overall goal of this function is to read in any available data in
+        this entry and any subentries. This includes reading in blobs, setting
+        up objects which have predefined contents, etc.
+
+        Since entry types which contain entries call ObtainContents() on all
+        those entries too, the result is that ObtainContents() is called
+        recursively for the whole tree below this one.
+
+        Entries with subentries are generally not *themselves& processed here,
+        i.e. their ObtainContents() implementation simply obtains contents of
+        their subentries, skipping their own contents. For example, the
+        implementation here (for entry_Section) does not attempt to pack the
+        entries into a final result. That is handled later.
+
+        Generally, calling this results in SetContents() being called for each
+        entry, so that the 'data' and 'contents_size; properties are set, and
+        subsequent calls to GetData() will return value data.
+
+        Where 'allow_missing' is set, this can result in the 'missing' property
+        being set to True if there is no data. This is handled by setting the
+        data to b''. This function will still return success. Future calls to
+        GetData() for this entry will return b'', or in the case where the data
+        is faked, GetData() will return that fake data.
+
+        Args:
+            skip_entry: (single) Entry to skip, or None to process all entries
+
         Note that this may set entry.absent to True if the entry is not
         actually needed
         """
@@ -719,7 +751,7 @@ class Entry_section(Entry):
                     next_todo.append(entry)
             return entry
 
-        todo = self._entries.values()
+        todo = self.GetEntries().values()
         for passnum in range(3):
             threads = state.GetThreads()
             next_todo = []
@@ -892,7 +924,7 @@ class Entry_section(Entry):
             allow_missing: True if allowed, False if not allowed
         """
         self.allow_missing = allow_missing
-        for entry in self._entries.values():
+        for entry in self.GetEntries().values():
             entry.SetAllowMissing(allow_missing)
 
     def SetAllowFakeBlob(self, allow_fake):
@@ -902,7 +934,7 @@ class Entry_section(Entry):
             allow_fake: True if allowed, False if not allowed
         """
         super().SetAllowFakeBlob(allow_fake)
-        for entry in self._entries.values():
+        for entry in self.GetEntries().values():
             entry.SetAllowFakeBlob(allow_fake)
 
     def CheckMissing(self, missing_list):
@@ -914,7 +946,7 @@ class Entry_section(Entry):
         Args:
             missing_list: List of Entry objects to be added to
         """
-        for entry in self._entries.values():
+        for entry in self.GetEntries().values():
             entry.CheckMissing(missing_list)
 
     def CheckFakedBlobs(self, faked_blobs_list):
@@ -925,7 +957,7 @@ class Entry_section(Entry):
         Args:
             faked_blobs_list: List of Entry objects to be added to
         """
-        for entry in self._entries.values():
+        for entry in self.GetEntries().values():
             entry.CheckFakedBlobs(faked_blobs_list)
 
     def CheckOptional(self, optional_list):
@@ -936,7 +968,7 @@ class Entry_section(Entry):
         Args:
             optional_list (list): List of Entry objects to be added to
         """
-        for entry in self._entries.values():
+        for entry in self.GetEntries().values():
             entry.CheckOptional(optional_list)
 
     def check_missing_bintools(self, missing_list):
@@ -948,7 +980,7 @@ class Entry_section(Entry):
             missing_list: List of Bintool objects to be added to
         """
         super().check_missing_bintools(missing_list)
-        for entry in self._entries.values():
+        for entry in self.GetEntries().values():
             entry.check_missing_bintools(missing_list)
 
     def _CollectEntries(self, entries, entries_by_name, add_entry):
@@ -998,12 +1030,12 @@ class Entry_section(Entry):
             entry.Raise(f'Missing required properties/entry args: {missing}')
 
     def CheckAltFormats(self, alt_formats):
-        for entry in self._entries.values():
+        for entry in self.GetEntries().values():
             entry.CheckAltFormats(alt_formats)
 
     def AddBintools(self, btools):
         super().AddBintools(btools)
-        for entry in self._entries.values():
+        for entry in self.GetEntries().values():
             entry.AddBintools(btools)
 
     def read_elf_segments(self):
diff --git a/tools/binman/etype/ti_board_config.py b/tools/binman/etype/ti_board_config.py
new file mode 100644
index 0000000000..94f894c281
--- /dev/null
+++ b/tools/binman/etype/ti_board_config.py
@@ -0,0 +1,259 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Written by Neha Malcom Francis <n-francis@ti.com>
+#
+# Entry-type module for generating schema validated TI board
+# configuration binary
+#
+
+import os
+import struct
+import yaml
+
+from collections import OrderedDict
+from jsonschema import validate
+from shutil import copyfileobj
+
+from binman.entry import Entry
+from binman.etype.section import Entry_section
+from dtoc import fdt_util
+from u_boot_pylib import tools
+
+BOARDCFG = 0xB
+BOARDCFG_SEC = 0xD
+BOARDCFG_PM = 0xE
+BOARDCFG_RM = 0xC
+BOARDCFG_NUM_ELEMS = 4
+
+class Entry_ti_board_config(Entry_section):
+    """An entry containing a TI schema validated board config binary
+
+    This etype supports generation of two kinds of board configuration
+    binaries: singular board config binary as well as combined board config
+    binary.
+
+    Properties / Entry arguments:
+        - config-file: File containing board configuration data in YAML
+        - schema-file: File containing board configuration YAML schema against
+          which the config file is validated
+
+    Output files:
+        - board config binary: File containing board configuration binary
+
+    These above parameters are used only when the generated binary is
+    intended to be a single board configuration binary. Example::
+
+        my-ti-board-config {
+            ti-board-config {
+                config = "board-config.yaml";
+                schema = "schema.yaml";
+            };
+        };
+
+    To generate a combined board configuration binary, we pack the
+    needed individual binaries into a ti-board-config binary. In this case,
+    the available supported subnode names are board-cfg, pm-cfg, sec-cfg and
+    rm-cfg. The final binary is prepended with a header containing details about
+    the included board config binaries. Example::
+
+        my-combined-ti-board-config {
+            ti-board-config {
+                board-cfg {
+                    config = "board-cfg.yaml";
+                    schema = "schema.yaml";
+                };
+                sec-cfg {
+                    config = "sec-cfg.yaml";
+                    schema = "schema.yaml";
+                };
+            }
+        }
+    """
+    def __init__(self, section, etype, node):
+        super().__init__(section, etype, node)
+        self._config = None
+        self._schema = None
+        self._entries = OrderedDict()
+        self._num_elems = BOARDCFG_NUM_ELEMS
+        self._fmt = '<HHHBB'
+        self._index = 0
+        self._binary_offset = 0
+        self._sw_rev = 1
+        self._devgrp = 0
+
+    def ReadNode(self):
+        super().ReadNode()
+        self._config = fdt_util.GetString(self._node, 'config')
+        self._schema = fdt_util.GetString(self._node, 'schema')
+        # Depending on whether config file is present in node, we determine
+        # whether it is a combined board config binary or not
+        if self._config is None:
+            self.ReadEntries()
+        else:
+            self._config_file = tools.get_input_filename(self._config)
+            self._schema_file = tools.get_input_filename(self._schema)
+
+    def ReadEntries(self):
+        """Read the subnodes to find out what should go in this image
+        """
+        for node in self._node.subnodes:
+            if 'type' not in node.props:
+                entry = Entry.Create(self, node, 'ti-board-config')
+                entry.ReadNode()
+                cfg_data = entry.BuildSectionData(True)
+                entry._cfg_data = cfg_data
+                self._entries[entry.name] = entry
+        self._num_elems = len(self._node.subnodes)
+
+    def _convert_to_byte_chunk(self, val, data_type):
+        """Convert value into byte array
+
+        Args:
+            val: value to convert into byte array
+            data_type: data type used in schema, supported data types are u8,
+                u16 and u32
+
+        Returns:
+            array of bytes representing value
+        """
+        size = 0
+        if (data_type == '#/definitions/u8'):
+            size = 1
+        elif (data_type == '#/definitions/u16'):
+            size = 2
+        else:
+            size = 4
+        if type(val) == int:
+            br = val.to_bytes(size, byteorder='little')
+        return br
+
+    def _compile_yaml(self, schema_yaml, file_yaml):
+        """Convert YAML file into byte array based on YAML schema
+
+        Args:
+            schema_yaml: file containing YAML schema
+            file_yaml: file containing config to compile
+
+        Returns:
+            array of bytes repesenting YAML file against YAML schema
+        """
+        br = bytearray()
+        for key, node in file_yaml.items():
+            node_schema = schema_yaml['properties'][key]
+            node_type = node_schema.get('type')
+            if not 'type' in node_schema:
+                br += self._convert_to_byte_chunk(node,
+                                                node_schema.get('$ref'))
+            elif node_type == 'object':
+                br += self._compile_yaml(node_schema, node)
+            elif node_type == 'array':
+                for item in node:
+                    if not isinstance(item, dict):
+                        br += self._convert_to_byte_chunk(
+                            item, schema_yaml['properties'][key]['items']['$ref'])
+                    else:
+                        br += self._compile_yaml(node_schema.get('items'), item)
+        return br
+
+    def _generate_binaries(self):
+        """Generate config binary artifacts from the loaded YAML configuration file
+
+        Returns:
+            byte array containing config binary artifacts
+            or None if generation fails
+        """
+        cfg_binary = bytearray()
+        for key, node in self.file_yaml.items():
+            node_schema = self.schema_yaml['properties'][key]
+            br = self._compile_yaml(node_schema, node)
+            cfg_binary += br
+        return cfg_binary
+
+    def _add_boardcfg(self, bcfgtype, bcfgdata):
+        """Add board config to combined board config binary
+
+        Args:
+            bcfgtype (int): board config type
+            bcfgdata (byte array): board config data
+        """
+        size = len(bcfgdata)
+        desc = struct.pack(self._fmt, bcfgtype,
+                            self._binary_offset, size, self._devgrp, 0)
+        with open(self.descfile, 'ab+') as desc_fh:
+            desc_fh.write(desc)
+        with open(self.bcfgfile, 'ab+') as bcfg_fh:
+            bcfg_fh.write(bcfgdata)
+        self._binary_offset += size
+        self._index += 1
+
+    def _finalize(self):
+        """Generate final combined board config binary
+
+        Returns:
+            byte array containing combined board config data
+            or None if unable to generate
+        """
+        with open(self.descfile, 'rb') as desc_fh:
+            with open(self.bcfgfile, 'rb') as bcfg_fh:
+                with open(self.fh_file, 'ab+') as fh:
+                    copyfileobj(desc_fh, fh)
+                    copyfileobj(bcfg_fh, fh)
+        data = tools.read_file(self.fh_file)
+        return data
+
+    def BuildSectionData(self, required):
+        if self._config is None:
+            self._binary_offset = 0
+            uniq = self.GetUniqueName()
+            self.fh_file = tools.get_output_filename('fh.%s' % uniq)
+            self.descfile = tools.get_output_filename('desc.%s' % uniq)
+            self.bcfgfile = tools.get_output_filename('bcfg.%s' % uniq)
+
+            # when binman runs again make sure we start clean
+            if os.path.exists(self.fh_file):
+                os.remove(self.fh_file)
+            if os.path.exists(self.descfile):
+                os.remove(self.descfile)
+            if os.path.exists(self.bcfgfile):
+                os.remove(self.bcfgfile)
+
+            with open(self.fh_file, 'wb') as f:
+                t_bytes = f.write(struct.pack(
+                    '<BB', self._num_elems, self._sw_rev))
+            self._binary_offset += t_bytes
+            self._binary_offset += self._num_elems * struct.calcsize(self._fmt)
+
+            if 'board-cfg' in self._entries:
+                self._add_boardcfg(BOARDCFG, self._entries['board-cfg']._cfg_data)
+
+            if 'sec-cfg' in self._entries:
+                self._add_boardcfg(BOARDCFG_SEC, self._entries['sec-cfg']._cfg_data)
+
+            if 'pm-cfg' in self._entries:
+                self._add_boardcfg(BOARDCFG_PM, self._entries['pm-cfg']._cfg_data)
+
+            if 'rm-cfg' in self._entries:
+                self._add_boardcfg(BOARDCFG_RM, self._entries['rm-cfg']._cfg_data)
+
+            data = self._finalize()
+            return data
+
+        else:
+            with open(self._config_file, 'r') as f:
+                self.file_yaml = yaml.safe_load(f)
+            with open(self._schema_file, 'r') as sch:
+                self.schema_yaml = yaml.safe_load(sch)
+
+            try:
+                validate(self.file_yaml, self.schema_yaml)
+            except Exception as e:
+                self.Raise(f"Schema validation error: {e}")
+
+            data = self._generate_binaries()
+            return data
+
+    def SetImagePos(self, image_pos):
+        Entry.SetImagePos(self, image_pos)
+
+    def CheckEntries(self):
+        Entry.CheckEntries(self)
diff --git a/tools/binman/etype/ti_secure.py b/tools/binman/etype/ti_secure.py
new file mode 100644
index 0000000000..d939dce571
--- /dev/null
+++ b/tools/binman/etype/ti_secure.py
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Written by Neha Malcom Francis <n-francis@ti.com>
+#
+
+# Support for generation of TI secured binary blobs
+
+from binman.entry import EntryArg
+from binman.etype.x509_cert import Entry_x509_cert
+
+from dtoc import fdt_util
+
+class Entry_ti_secure(Entry_x509_cert):
+    """Entry containing a TI x509 certificate binary
+
+    Properties / Entry arguments:
+        - content: List of phandles to entries to sign
+        - keyfile: Filename of file containing key to sign binary with
+        - sha: Hash function to be used for signing
+
+    Output files:
+        - input.<unique_name> - input file passed to openssl
+        - config.<unique_name> - input file generated for openssl (which is
+          used as the config file)
+        - cert.<unique_name> - output file generated by openssl (which is
+          used as the entry contents)
+
+    openssl signs the provided data, using the TI templated config file and
+    writes the signature in this entry. This allows verification that the
+    data is genuine.
+    """
+    def __init__(self, section, etype, node):
+        super().__init__(section, etype, node)
+        self.openssl = None
+
+    def ReadNode(self):
+        super().ReadNode()
+        self.key_fname = self.GetEntryArgsOrProps([
+            EntryArg('keyfile', str)], required=True)[0]
+        self.sha = fdt_util.GetInt(self._node, 'sha', 512)
+        self.req_dist_name = {'C': 'US',
+                'ST': 'TX',
+                'L': 'Dallas',
+                'O': 'Texas Instruments Incorporated',
+                'OU': 'Processors',
+                'CN': 'TI Support',
+                'emailAddress': 'support@ti.com'}
+
+    def GetCertificate(self, required):
+        """Get the contents of this entry
+
+        Args:
+            required: True if the data must be present, False if it is OK to
+                return None
+
+        Returns:
+            bytes content of the entry, which is the certificate binary for the
+                provided data
+        """
+        return super().GetCertificate(required=required, type='sysfw')
+
+    def ObtainContents(self):
+        data = self.data
+        if data is None:
+            data = self.GetCertificate(False)
+        if data is None:
+            return False
+        self.SetContents(data)
+        return True
+
+    def ProcessContents(self):
+        # The blob may have changed due to WriteSymbols()
+        data = self.data
+        return self.ProcessContentsUpdate(data)
+
+    def AddBintools(self, btools):
+        super().AddBintools(btools)
+        self.openssl = self.AddBintool(btools, 'openssl')
diff --git a/tools/binman/etype/ti_secure_rom.py b/tools/binman/etype/ti_secure_rom.py
new file mode 100644
index 0000000000..9a7ac9e9e0
--- /dev/null
+++ b/tools/binman/etype/ti_secure_rom.py
@@ -0,0 +1,249 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Written by Neha Malcom Francis <n-francis@ti.com>
+#
+
+# Support for generation of TI secured bootloaders booted by ROM
+
+from binman.entry import EntryArg
+from binman.etype.x509_cert import Entry_x509_cert
+
+import hashlib
+
+from dtoc import fdt_util
+from u_boot_pylib  import tools
+
+VALID_SHAS = [256, 384, 512, 224]
+SHA_OIDS = {256:'2.16.840.1.101.3.4.2.1',
+            384:'2.16.840.1.101.3.4.2.2',
+            512:'2.16.840.1.101.3.4.2.3',
+            224:'2.16.840.1.101.3.4.2.4'}
+
+class Entry_ti_secure_rom(Entry_x509_cert):
+    """Entry containing a TI x509 certificate binary for images booted by ROM
+
+    Properties / Entry arguments:
+        - keyfile: Filename of file containing key to sign binary with
+        - combined: boolean if device follows combined boot flow
+        - countersign: boolean if device contains countersigned system firmware
+        - load: load address of SPL
+        - sw-rev: software revision
+        - sha: Hash function to be used for signing
+        - core: core on which bootloader runs, valid cores are 'secure' and 'public'
+        - content: phandle of SPL in case of legacy bootflow or phandles of component binaries
+          in case of combined bootflow
+
+    The following properties are only for generating a combined bootflow binary:
+        - sysfw-inner-cert: boolean if binary contains sysfw inner certificate
+        - dm-data: boolean if binary contains dm-data binary
+        - content-sbl: phandle of SPL binary
+        - content-sysfw: phandle of sysfw binary
+        - content-sysfw-data: phandle of sysfw-data or tifs-data binary
+        - content-sysfw-inner-cert (optional): phandle of sysfw inner certificate binary
+        - content-dm-data (optional): phandle of dm-data binary
+        - load-sysfw: load address of sysfw binary
+        - load-sysfw-data: load address of sysfw-data or tifs-data binary
+        - load-sysfw-inner-cert (optional): load address of sysfw inner certificate binary
+        - load-dm-data (optional): load address of dm-data binary
+
+    Output files:
+        - input.<unique_name> - input file passed to openssl
+        - config.<unique_name> - input file generated for openssl (which is
+          used as the config file)
+        - cert.<unique_name> - output file generated by openssl (which is
+          used as the entry contents)
+
+    openssl signs the provided data, using the TI templated config file and
+    writes the signature in this entry. This allows verification that the
+    data is genuine.
+    """
+    def __init__(self, section, etype, node):
+        super().__init__(section, etype, node)
+        self.openssl = None
+
+    def ReadNode(self):
+        super().ReadNode()
+        self.combined = fdt_util.GetBool(self._node, 'combined', False)
+        self.countersign = fdt_util.GetBool(self._node, 'countersign', False)
+        self.load_addr = fdt_util.GetInt(self._node, 'load', 0x00000000)
+        self.sw_rev = fdt_util.GetInt(self._node, 'sw-rev', 1)
+        self.sha = fdt_util.GetInt(self._node, 'sha', 512)
+        self.core = fdt_util.GetString(self._node, 'core', 'secure')
+        self.key_fname = self.GetEntryArgsOrProps([
+            EntryArg('keyfile', str)], required=True)[0]
+        if self.combined:
+            self.sysfw_inner_cert = fdt_util.GetBool(self._node, 'sysfw-inner-cert', False)
+            self.load_addr_sysfw = fdt_util.GetInt(self._node, 'load-sysfw', 0x00000000)
+            self.load_addr_sysfw_data = fdt_util.GetInt(self._node, 'load-sysfw-data', 0x00000000)
+            self.dm_data = fdt_util.GetBool(self._node, 'dm-data', False)
+            if self.dm_data:
+                self.load_addr_dm_data = fdt_util.GetInt(self._node, 'load-dm-data', 0x00000000)
+        self.req_dist_name = {'C': 'US',
+                    'ST': 'TX',
+                    'L': 'Dallas',
+                    'O': 'Texas Instruments Incorporated',
+                    'OU': 'Processors',
+                    'CN': 'TI Support',
+                    'emailAddress': 'support@ti.com'}
+
+    def NonCombinedGetCertificate(self, required):
+        """Generate certificate for legacy boot flow
+
+        Args:
+            required: True if the data must be present, False if it is OK to
+                return None
+
+        Returns:
+            bytes content of the entry, which is the certificate binary for the
+                provided data
+        """
+        if self.core == 'secure':
+            if self.countersign:
+                self.cert_type = 3
+            else:
+                self.cert_type = 2
+            self.bootcore = 0
+            self.bootcore_opts = 32
+        else:
+            self.cert_type = 1
+            self.bootcore = 16
+            self.bootcore_opts = 0
+        return super().GetCertificate(required=required, type='rom')
+
+    def CombinedGetCertificate(self, required):
+        """Generate certificate for combined boot flow
+
+        Args:
+            required: True if the data must be present, False if it is OK to
+                return None
+
+        Returns:
+            bytes content of the entry, which is the certificate binary for the
+                provided data
+        """
+        uniq = self.GetUniqueName()
+
+        self.num_comps = 3
+        self.sha_type = SHA_OIDS[self.sha]
+
+        # sbl
+        self.content = fdt_util.GetPhandleList(self._node, 'content-sbl')
+        input_data_sbl = self.GetContents(required)
+        if input_data_sbl is None:
+            return None
+
+        input_fname_sbl = tools.get_output_filename('input.%s' % uniq)
+        tools.write_file(input_fname_sbl, input_data_sbl)
+
+        indata_sbl = tools.read_file(input_fname_sbl)
+        self.hashval_sbl = hashlib.sha512(indata_sbl).hexdigest()
+        self.imagesize_sbl = len(indata_sbl)
+
+        # sysfw
+        self.content = fdt_util.GetPhandleList(self._node, 'content-sysfw')
+        input_data_sysfw = self.GetContents(required)
+
+        input_fname_sysfw = tools.get_output_filename('input.%s' % uniq)
+        tools.write_file(input_fname_sysfw, input_data_sysfw)
+
+        indata_sysfw = tools.read_file(input_fname_sysfw)
+        self.hashval_sysfw = hashlib.sha512(indata_sysfw).hexdigest()
+        self.imagesize_sysfw = len(indata_sysfw)
+
+        # sysfw data
+        self.content = fdt_util.GetPhandleList(self._node, 'content-sysfw-data')
+        input_data_sysfw_data = self.GetContents(required)
+
+        input_fname_sysfw_data = tools.get_output_filename('input.%s' % uniq)
+        tools.write_file(input_fname_sysfw_data, input_data_sysfw_data)
+
+        indata_sysfw_data = tools.read_file(input_fname_sysfw_data)
+        self.hashval_sysfw_data = hashlib.sha512(indata_sysfw_data).hexdigest()
+        self.imagesize_sysfw_data = len(indata_sysfw_data)
+
+        # sysfw inner cert
+        self.sysfw_inner_cert_ext_boot_block = ""
+        self.sysfw_inner_cert_ext_boot_sequence_string = ""
+        imagesize_sysfw_inner_cert = 0
+        if self.sysfw_inner_cert:
+            self.content = fdt_util.GetPhandleList(self._node, 'content-sysfw-inner-cert')
+            input_data_sysfw_inner_cert = self.GetContents(required)
+
+            input_fname_sysfw_inner_cert = tools.get_output_filename('input.%s' % uniq)
+            tools.write_file(input_fname_sysfw_inner_cert, input_data_sysfw_inner_cert)
+
+            indata_sysfw_inner_cert = tools.read_file(input_fname_sysfw_inner_cert)
+            hashval_sysfw_inner_cert = hashlib.sha512(indata_sysfw_inner_cert).hexdigest()
+            imagesize_sysfw_inner_cert = len(indata_sysfw_inner_cert)
+            self.num_comps += 1
+            self.sysfw_inner_cert_ext_boot_sequence_string = "sysfw_inner_cert=SEQUENCE:sysfw_inner_cert"
+            self.sysfw_inner_cert_ext_boot_block = f"""[sysfw_inner_cert]
+compType = INTEGER:3
+bootCore = INTEGER:0
+compOpts = INTEGER:0
+destAddr = FORMAT:HEX,OCT:00000000
+compSize = INTEGER:{imagesize_sysfw_inner_cert}
+shaType  = OID:{self.sha_type}
+shaValue = FORMAT:HEX,OCT:{hashval_sysfw_inner_cert}"""
+
+        # dm data
+        self.dm_data_ext_boot_sequence_string = ""
+        self.dm_data_ext_boot_block = ""
+        imagesize_dm_data = 0
+        if self.dm_data:
+            self.content = fdt_util.GetPhandleList(self._node, 'content-dm-data')
+            input_data_dm_data = self.GetContents(required)
+
+            input_fname_dm_data = tools.get_output_filename('input.%s' % uniq)
+            tools.write_file(input_fname_dm_data, input_data_dm_data)
+
+            indata_dm_data = tools.read_file(input_fname_dm_data)
+            hashval_dm_data = hashlib.sha512(indata_dm_data).hexdigest()
+            imagesize_dm_data = len(indata_dm_data)
+            self.num_comps += 1
+            self.dm_data_ext_boot_sequence_string = "dm_data=SEQUENCE:dm_data"
+            self.dm_data_ext_boot_block = f"""[dm_data]
+compType = INTEGER:17
+bootCore = INTEGER:16
+compOpts = INTEGER:0
+destAddr = FORMAT:HEX,OCT:{self.load_addr_dm_data:08x}
+compSize = INTEGER:{imagesize_dm_data}
+shaType  = OID:{self.sha_type}
+shaValue = FORMAT:HEX,OCT:{hashval_dm_data}"""
+
+        self.total_size = self.imagesize_sbl +  self.imagesize_sysfw + self.imagesize_sysfw_data + imagesize_sysfw_inner_cert + imagesize_dm_data
+        return super().GetCertificate(required=required, type='rom-combined')
+
+    def GetCertificate(self, required):
+        """Get the contents of this entry
+
+        Args:
+            required: True if the data must be present, False if it is OK to
+                return None
+
+        Returns:
+            bytes content of the entry, which is the certificate binary for the
+                provided data
+        """
+        if self.combined:
+            return self.CombinedGetCertificate(required)
+        else:
+            return self.NonCombinedGetCertificate(required)
+
+    def ObtainContents(self):
+        data = self.data
+        if data is None:
+            data = self.GetCertificate(False)
+        if data is None:
+            return False
+        self.SetContents(data)
+        return True
+
+    def ProcessContents(self):
+        # The blob may have changed due to WriteSymbols()
+        data = self.data
+        return self.ProcessContentsUpdate(data)
+
+    def AddBintools(self, btools):
+        super().AddBintools(btools)
+        self.openssl = self.AddBintool(btools, 'openssl')
diff --git a/tools/binman/etype/u_boot_spl_bss_pad.py b/tools/binman/etype/u_boot_spl_bss_pad.py
index 1ffeb3911f..4af4045d37 100644
--- a/tools/binman/etype/u_boot_spl_bss_pad.py
+++ b/tools/binman/etype/u_boot_spl_bss_pad.py
@@ -38,7 +38,7 @@ class Entry_u_boot_spl_bss_pad(Entry_blob):
     def ObtainContents(self):
         fname = tools.get_input_filename('spl/u-boot-spl')
         bss_size = elf.GetSymbolAddress(fname, '__bss_size')
-        if not bss_size:
+        if bss_size is None:
             self.Raise('Expected __bss_size symbol in spl/u-boot-spl')
         self.SetContents(tools.get_bytes(0, bss_size))
         return True
diff --git a/tools/binman/etype/u_boot_spl_pubkey_dtb.py b/tools/binman/etype/u_boot_spl_pubkey_dtb.py
new file mode 100644
index 0000000000..cb196061de
--- /dev/null
+++ b/tools/binman/etype/u_boot_spl_pubkey_dtb.py
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2023 Weidmueller GmbH
+# Written by Lukas Funke <lukas.funke@weidmueller.com>
+#
+# Entry-type module for 'u-boot-spl-pubkey.dtb'
+#
+
+import tempfile
+import os
+
+from binman.etype.blob_dtb import Entry_blob_dtb
+
+from dtoc import fdt_util
+
+from u_boot_pylib import tools
+
+# This is imported if needed
+state = None
+
+# pylint: disable=C0103
+class Entry_u_boot_spl_pubkey_dtb(Entry_blob_dtb):
+    """U-Boot SPL device tree including public key
+
+    Properties / Entry arguments:
+        - key-name-hint: Public key name without extension (.crt).
+                    Default is determined by underlying
+                    bintool (fdt_add_pubkey), usually 'key'.
+        - algo: (Optional) Algorithm used for signing. Default is determined by
+                underlying bintool (fdt_add_pubkey), usually 'sha1,rsa2048'
+        - required: (Optional) If present this indicates that the key must be
+                    verified for the image / configuration to be
+                    considered valid
+
+    The following example shows an image containing an SPL which
+    is packed together with the dtb. Binman will add a signature
+    node to the dtb.
+
+    Example node::
+
+        image {
+        ...
+            spl {
+                filename = "spl.bin"
+
+                u-boot-spl-nodtb {
+                };
+                u-boot-spl-pubkey-dtb {
+                    algo = "sha384,rsa4096";
+                    required = "conf";
+                    key-name-hint = "dev";
+                };
+            };
+        ...
+        }
+    """
+
+    def __init__(self, section, etype, node):
+        # Put this here to allow entry-docs and help to work without libfdt
+        global state
+        from binman import state
+
+        super().__init__(section, etype, node)
+        self.required_props = ['key-name-hint']
+        self.fdt_add_pubkey = None
+        self._algo = fdt_util.GetString(self._node, 'algo')
+        self._required = fdt_util.GetString(self._node, 'required')
+        self._key_name_hint = fdt_util.GetString(self._node, 'key-name-hint')
+
+    def ObtainContents(self, fake_size=0):
+        """Add public key to SPL dtb
+
+            Add public key which is pointed out by
+            'key-name-hint' to node 'signature' in the spl-dtb
+
+            This is equivalent to the '-K' option of 'mkimage'
+
+        Args:
+            fake_size (int): unused
+        """
+
+        # We don't pass fake_size upwards because this is currently
+        # not supported by the blob type
+        super().ObtainContents()
+
+        with tempfile.NamedTemporaryFile(prefix=os.path.basename(
+                                         self.GetFdtEtype()),
+                                         dir=tools.get_output_dir())\
+                                              as pubkey_tdb:
+            tools.write_file(pubkey_tdb.name, self.GetData())
+            keyname = tools.get_input_filename(self._key_name_hint + ".crt")
+            self.fdt_add_pubkey.run(pubkey_tdb.name,
+                                    os.path.dirname(keyname),
+                                    self._key_name_hint,
+                                    self._required, self._algo)
+            dtb = tools.read_file(pubkey_tdb.name)
+            self.SetContents(dtb)
+            state.UpdateFdtContents(self.GetFdtEtype(), dtb)
+
+        return True
+
+    # pylint: disable=R0201,C0116
+    def GetDefaultFilename(self):
+        return 'spl/u-boot-spl-pubkey.dtb'
+
+    # pylint: disable=R0201,C0116
+    def GetFdtEtype(self):
+        return 'u-boot-spl-dtb'
+
+    # pylint: disable=R0201,C0116
+    def AddBintools(self, btools):
+        super().AddBintools(btools)
+        self.fdt_add_pubkey = self.AddBintool(btools, 'fdt_add_pubkey')
diff --git a/tools/binman/etype/u_boot_tpl_bss_pad.py b/tools/binman/etype/u_boot_tpl_bss_pad.py
index 29c6a95412..46d2cd58f7 100644
--- a/tools/binman/etype/u_boot_tpl_bss_pad.py
+++ b/tools/binman/etype/u_boot_tpl_bss_pad.py
@@ -38,7 +38,7 @@ class Entry_u_boot_tpl_bss_pad(Entry_blob):
     def ObtainContents(self):
         fname = tools.get_input_filename('tpl/u-boot-tpl')
         bss_size = elf.GetSymbolAddress(fname, '__bss_size')
-        if not bss_size:
+        if bss_size is None:
             self.Raise('Expected __bss_size symbol in tpl/u-boot-tpl')
         self.SetContents(tools.get_bytes(0, bss_size))
         return True
diff --git a/tools/binman/etype/u_boot_vpl_bss_pad.py b/tools/binman/etype/u_boot_vpl_bss_pad.py
index bba38ccf9e..12b286a719 100644
--- a/tools/binman/etype/u_boot_vpl_bss_pad.py
+++ b/tools/binman/etype/u_boot_vpl_bss_pad.py
@@ -38,7 +38,7 @@ class Entry_u_boot_vpl_bss_pad(Entry_blob):
     def ObtainContents(self):
         fname = tools.get_input_filename('vpl/u-boot-vpl')
         bss_size = elf.GetSymbolAddress(fname, '__bss_size')
-        if not bss_size:
+        if bss_size is None:
             self.Raise('Expected __bss_size symbol in vpl/u-boot-vpl')
         self.SetContents(tools.get_bytes(0, bss_size))
         return True
diff --git a/tools/binman/etype/x509_cert.py b/tools/binman/etype/x509_cert.py
index f80a6ec2d1..d028cfe38c 100644
--- a/tools/binman/etype/x509_cert.py
+++ b/tools/binman/etype/x509_cert.py
@@ -31,6 +31,26 @@ class Entry_x509_cert(Entry_collection):
     def __init__(self, section, etype, node):
         super().__init__(section, etype, node)
         self.openssl = None
+        self.req_dist_name =  None
+        self.cert_type = None
+        self.bootcore = None
+        self.bootcore_opts = None
+        self.load_addr = None
+        self.sha = None
+        self.total_size = None
+        self.num_comps = None
+        self.sysfw_inner_cert_ext_boot_sequence_string = None
+        self.dm_data_ext_boot_sequence_string = None
+        self.imagesize_sbl = None
+        self.hashval_sbl = None
+        self.load_addr_sysfw = None
+        self.imagesize_sysfw = None
+        self.hashval_sysfw = None
+        self.load_addr_sysfw_data = None
+        self.imagesize_sysfw_data = None
+        self.hashval_sysfw_data = None
+        self.sysfw_inner_cert_ext_boot_block = None
+        self.dm_data_ext_boot_block = None
 
     def ReadNode(self):
         super().ReadNode()
@@ -38,13 +58,16 @@ class Entry_x509_cert(Entry_collection):
         self._cert_rev = fdt_util.GetInt(self._node, 'cert-revision-int', 0)
         self.key_fname = self.GetEntryArgsOrProps([
             EntryArg('keyfile', str)], required=True)[0]
+        self.sw_rev = fdt_util.GetInt(self._node, 'sw-rev', 1)
 
-    def GetCertificate(self, required):
+    def GetCertificate(self, required, type='generic'):
         """Get the contents of this entry
 
         Args:
             required: True if the data must be present, False if it is OK to
                 return None
+            type: Type of x509 certificate to generate, current supported ones are
+            'generic', 'sysfw', 'rom'
 
         Returns:
             bytes content of the entry, which is the signed vblock for the
@@ -60,13 +83,61 @@ class Entry_x509_cert(Entry_collection):
         input_fname = tools.get_output_filename('input.%s' % uniq)
         config_fname = tools.get_output_filename('config.%s' % uniq)
         tools.write_file(input_fname, input_data)
-        stdout = self.openssl.x509_cert(
-            cert_fname=output_fname,
-            input_fname=input_fname,
-            key_fname=self.key_fname,
-            cn=self._cert_ca,
-            revision=self._cert_rev,
-            config_fname=config_fname)
+        if type == 'generic':
+            stdout = self.openssl.x509_cert(
+                cert_fname=output_fname,
+                input_fname=input_fname,
+                key_fname=self.key_fname,
+                cn=self._cert_ca,
+                revision=self._cert_rev,
+                config_fname=config_fname)
+        elif type == 'sysfw':
+            stdout = self.openssl.x509_cert_sysfw(
+                cert_fname=output_fname,
+                input_fname=input_fname,
+                key_fname=self.key_fname,
+                config_fname=config_fname,
+                sw_rev=self.sw_rev,
+                req_dist_name_dict=self.req_dist_name)
+        elif type == 'rom':
+            stdout = self.openssl.x509_cert_rom(
+                cert_fname=output_fname,
+                input_fname=input_fname,
+                key_fname=self.key_fname,
+                config_fname=config_fname,
+                sw_rev=self.sw_rev,
+                req_dist_name_dict=self.req_dist_name,
+                cert_type=self.cert_type,
+                bootcore=self.bootcore,
+                bootcore_opts=self.bootcore_opts,
+                load_addr=self.load_addr,
+                sha=self.sha
+            )
+        elif type == 'rom-combined':
+            stdout = self.openssl.x509_cert_rom_combined(
+                cert_fname=output_fname,
+                input_fname=input_fname,
+                key_fname=self.key_fname,
+                config_fname=config_fname,
+                sw_rev=self.sw_rev,
+                req_dist_name_dict=self.req_dist_name,
+                load_addr=self.load_addr,
+                sha=self.sha,
+                total_size=self.total_size,
+                num_comps=self.num_comps,
+                sysfw_inner_cert_ext_boot_sequence_string=self.sysfw_inner_cert_ext_boot_sequence_string,
+                dm_data_ext_boot_sequence_string=self.dm_data_ext_boot_sequence_string,
+                imagesize_sbl=self.imagesize_sbl,
+                hashval_sbl=self.hashval_sbl,
+                load_addr_sysfw=self.load_addr_sysfw,
+                imagesize_sysfw=self.imagesize_sysfw,
+                hashval_sysfw=self.hashval_sysfw,
+                load_addr_sysfw_data=self.load_addr_sysfw_data,
+                imagesize_sysfw_data=self.imagesize_sysfw_data,
+                hashval_sysfw_data=self.hashval_sysfw_data,
+                sysfw_inner_cert_ext_boot_block=self.sysfw_inner_cert_ext_boot_block,
+                dm_data_ext_boot_block=self.dm_data_ext_boot_block
+            )
         if stdout is not None:
             data = tools.read_file(output_fname)
         else:
diff --git a/tools/binman/etype/xilinx_bootgen.py b/tools/binman/etype/xilinx_bootgen.py
new file mode 100644
index 0000000000..70a4b2e242
--- /dev/null
+++ b/tools/binman/etype/xilinx_bootgen.py
@@ -0,0 +1,225 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2023 Weidmueller GmbH
+# Written by Lukas Funke <lukas.funke@weidmueller.com>
+#
+# Entry-type module for Zynq(MP) boot images (boot.bin)
+#
+
+import tempfile
+
+from collections import OrderedDict
+
+from binman import elf
+from binman.etype.section import Entry_section
+
+from dtoc import fdt_util
+
+from u_boot_pylib import tools
+from u_boot_pylib import command
+
+# pylint: disable=C0103
+class Entry_xilinx_bootgen(Entry_section):
+    """Signed SPL boot image for Xilinx ZynqMP devices
+
+    Properties / Entry arguments:
+        - auth-params: (Optional) Authentication parameters passed to bootgen
+        - fsbl-config: (Optional) FSBL parameters passed to bootgen
+        - keysrc-enc: (Optional) Key source when using decryption engine
+        - pmufw-filename: Filename of PMU firmware. Default: pmu-firmware.elf
+        - psk-key-name-hint: Name of primary secret key to use for signing the
+                             secondardy public key. Format: .pem file
+        - ssk-key-name-hint: Name of secondardy secret key to use for signing
+                             the boot image. Format: .pem file
+
+    The etype is used to create a boot image for Xilinx ZynqMP
+    devices.
+
+    Information for signed images:
+
+    In AMD/Xilinx SoCs, two pairs of public and secret keys are used
+    - primary and secondary. The function of the primary public/secret key pair
+    is to authenticate the secondary public/secret key pair.
+    The function of the secondary key is to sign/verify the boot image. [1]
+
+    AMD/Xilinx uses the following terms for private/public keys [1]:
+
+        PSK = Primary Secret Key (Used to sign Secondary Public Key)
+        PPK = Primary Public Key (Used to verify Secondary Public Key)
+        SSK = Secondary Secret Key (Used to sign the boot image/partitions)
+        SPK = Used to verify the actual boot image
+
+    The following example builds a signed boot image. The fuses of
+    the primary public key (ppk) should be fused together with the RSA_EN flag.
+
+    Example node::
+
+        spl {
+            filename = "boot.signed.bin";
+
+            xilinx-bootgen {
+                psk-key-name-hint = "psk0";
+                ssk-key-name-hint = "ssk0";
+                auth-params = "ppk_select=0", "spk_id=0x00000000";
+
+                u-boot-spl-nodtb {
+                };
+                u-boot-spl-pubkey-dtb {
+                    algo = "sha384,rsa4096";
+                    required = "conf";
+                    key-name-hint = "dev";
+                };
+            };
+        };
+
+    For testing purposes, e.g. if no RSA_EN should be fused, one could add
+    the "bh_auth_enable" flag in the fsbl-config field. This will skip the
+    verification of the ppk fuses and boot the image, even if ppk hash is
+    invalid.
+
+    Example node::
+
+        xilinx-bootgen {
+            psk-key-name-hint = "psk0";
+            psk-key-name-hint = "ssk0";
+            ...
+            fsbl-config = "bh_auth_enable";
+            ...
+        };
+
+    [1] https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide/Using-Authentication
+
+    """
+    def __init__(self, section, etype, node):
+        super().__init__(section, etype, node)
+        self._auth_params = None
+        self._entries = OrderedDict()
+        self._filename = None
+        self._fsbl_config = None
+        self._keysrc_enc = None
+        self._pmufw_filename = None
+        self._psk_key_name_hint = None
+        self._ssk_key_name_hint = None
+        self.align_default = None
+        self.bootgen = None
+        self.required_props = ['pmufw-filename',
+                               'psk-key-name-hint',
+                               'ssk-key-name-hint']
+
+    def ReadNode(self):
+        """Read properties from the xilinx-bootgen node"""
+        super().ReadNode()
+        self._auth_params = fdt_util.GetStringList(self._node,
+                                                   'auth-params')
+        self._filename = fdt_util.GetString(self._node, 'filename')
+        self._fsbl_config = fdt_util.GetStringList(self._node,
+                                                   'fsbl-config')
+        self._keysrc_enc = fdt_util.GetString(self._node,
+                                                   'keysrc-enc')
+        self._pmufw_filename = fdt_util.GetString(self._node, 'pmufw-filename')
+        self._psk_key_name_hint = fdt_util.GetString(self._node,
+                                                     'psk-key-name-hint')
+        self._ssk_key_name_hint = fdt_util.GetString(self._node,
+                                                   'ssk-key-name-hint')
+        self.ReadEntries()
+
+    @classmethod
+    def _ToElf(cls, data, output_fname):
+        """Convert SPL object file to bootable ELF file
+
+        Args:
+            data (bytearray): u-boot-spl-nodtb + u-boot-spl-pubkey-dtb obj file
+                                data
+            output_fname (str): Filename of converted FSBL ELF file
+        """
+        platform_elfflags = {"aarch64":
+                        ["-B", "aarch64", "-O", "elf64-littleaarch64"],
+                        # amd64 support makes no sense for the target
+                        # platform, but we include it here to enable
+                        # testing on hosts
+                        "x86_64":
+                        ["-B", "i386", "-O", "elf64-x86-64"]
+                        }
+
+        gcc, args = tools.get_target_compile_tool('cc')
+        args += ['-dumpmachine']
+        stdout = command.output(gcc, *args)
+        # split target machine triplet (arch, vendor, os)
+        arch, _, _ = stdout.split('-')
+
+        spl_elf = elf.DecodeElf(tools.read_file(
+            tools.get_input_filename('spl/u-boot-spl')), 0)
+
+        # Obj file to swap data and text section (rename-section)
+        with tempfile.NamedTemporaryFile(prefix="u-boot-spl-pubkey-",
+                                    suffix=".o.tmp",
+                                    dir=tools.get_output_dir())\
+                                    as tmp_obj:
+            input_objcopy_fname = tmp_obj.name
+            # Align packed content to 4 byte boundary
+            pad = bytearray(tools.align(len(data), 4) - len(data))
+            tools.write_file(input_objcopy_fname, data + pad)
+            # Final output elf file which contains a valid start address
+            with tempfile.NamedTemporaryFile(prefix="u-boot-spl-pubkey-elf-",
+                                            suffix=".o.tmp",
+                                            dir=tools.get_output_dir())\
+                                                as tmp_elf_obj:
+                input_ld_fname = tmp_elf_obj.name
+                objcopy, args = tools.get_target_compile_tool('objcopy')
+                args += ["--rename-section", ".data=.text",
+                        "-I", "binary"]
+                args += platform_elfflags[arch]
+                args += [input_objcopy_fname, input_ld_fname]
+                command.run(objcopy, *args)
+
+                ld, args = tools.get_target_compile_tool('ld')
+                args += [input_ld_fname, '-o', output_fname,
+                         "--defsym", f"_start={hex(spl_elf.entry)}",
+                         "-Ttext", hex(spl_elf.entry)]
+                command.run(ld, *args)
+
+    def BuildSectionData(self, required):
+        """Pack node content, and create bootable, signed ZynqMP boot image
+
+        The method collects the content of this node (usually SPL + dtb) and
+        converts them to an ELF file. The ELF file is passed to the
+        Xilinx bootgen tool which packs the SPL ELF file together with
+        Platform Management Unit (PMU) firmware into a bootable image
+        for ZynqMP devices. The image is signed within this step.
+
+        The result is a bootable, signed SPL image for Xilinx ZynqMP devices.
+        """
+        data = super().BuildSectionData(required)
+        bootbin_fname = self._filename if self._filename else \
+                            tools.get_output_filename(
+                            f'boot.{self.GetUniqueName()}.bin')
+
+        pmufw_elf_fname = tools.get_input_filename(self._pmufw_filename)
+        psk_fname = tools.get_input_filename(self._psk_key_name_hint + ".pem")
+        ssk_fname = tools.get_input_filename(self._ssk_key_name_hint + ".pem")
+        fsbl_config = ";".join(self._fsbl_config) if self._fsbl_config else None
+        auth_params = ";".join(self._auth_params) if self._auth_params else None
+
+        spl_elf_fname = tools.get_output_filename('u-boot-spl-pubkey.dtb.elf')
+
+        # We need to convert to node content (see above) into an ELF
+        # file in order to be processed by bootgen.
+        self._ToElf(bytearray(data), spl_elf_fname)
+
+        # Call Bootgen in order to sign the SPL
+        if self.bootgen.sign('zynqmp', spl_elf_fname, pmufw_elf_fname,
+                        psk_fname, ssk_fname, fsbl_config,
+                        auth_params, self._keysrc_enc, bootbin_fname) is None:
+            # Bintool is missing; just use empty data as the output
+            self.record_missing_bintool(self.bootgen)
+            data = tools.get_bytes(0, 1024)
+        else:
+            data = tools.read_file(bootbin_fname)
+
+        self.SetContents(data)
+
+        return data
+
+    # pylint: disable=C0116
+    def AddBintools(self, btools):
+        super().AddBintools(btools)
+        self.bootgen = self.AddBintool(btools, 'bootgen')
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 43b4f850a6..1293e9dbf4 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -94,9 +94,13 @@ ROCKCHIP_TPL_DATA     = b'rockchip-tpl'
 TEST_FDT1_DATA        = b'fdt1'
 TEST_FDT2_DATA        = b'test-fdt2'
 ENV_DATA              = b'var1=1\nvar2="2"'
+ENCRYPTED_IV_DATA     = b'123456'
+ENCRYPTED_KEY_DATA    = b'abcde'
 PRE_LOAD_MAGIC        = b'UBSH'
 PRE_LOAD_VERSION      = 0x11223344.to_bytes(4, 'big')
 PRE_LOAD_HDR_SIZE     = 0x00001000.to_bytes(4, 'big')
+TI_BOARD_CONFIG_DATA  = b'\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'
+TI_UNSECURE_DATA      = b'unsecuredata'
 
 # Subdirectory of the input dir to use to put test FDTs
 TEST_FDT_SUBDIR       = 'fdts'
@@ -199,6 +203,9 @@ class TestFunctional(unittest.TestCase):
         shutil.copytree(cls.TestFile('files'),
                         os.path.join(cls._indir, 'files'))
 
+        shutil.copytree(cls.TestFile('yaml'),
+                        os.path.join(cls._indir, 'yaml'))
+
         TestFunctional._MakeInputFile('compress', COMPRESS_DATA)
         TestFunctional._MakeInputFile('compress_big', COMPRESS_DATA_BIG)
         TestFunctional._MakeInputFile('bl31.bin', ATF_BL31_DATA)
@@ -207,6 +214,7 @@ class TestFunctional(unittest.TestCase):
         TestFunctional._MakeInputFile('fw_dynamic.bin', OPENSBI_DATA)
         TestFunctional._MakeInputFile('scp.bin', SCP_DATA)
         TestFunctional._MakeInputFile('rockchip-tpl.bin', ROCKCHIP_TPL_DATA)
+        TestFunctional._MakeInputFile('ti_unsecure.bin', TI_UNSECURE_DATA)
 
         # Add a few .dtb files for testing
         TestFunctional._MakeInputFile('%s/test-fdt1.dtb' % TEST_FDT_SUBDIR,
@@ -226,6 +234,10 @@ class TestFunctional(unittest.TestCase):
         # Newer OP_TEE file in v1 binary format
         cls.make_tee_bin('tee.bin')
 
+        # test files for encrypted tests
+        TestFunctional._MakeInputFile('encrypted-file.iv', ENCRYPTED_IV_DATA)
+        TestFunctional._MakeInputFile('encrypted-file.key', ENCRYPTED_KEY_DATA)
+
         cls.comp_bintools = {}
         for name in COMP_BINTOOLS:
             cls.comp_bintools[name] = bintool.Bintool.create(name)
@@ -347,7 +359,7 @@ class TestFunctional(unittest.TestCase):
                     use_expanded=False, verbosity=None, allow_missing=False,
                     allow_fake_blobs=False, extra_indirs=None, threads=None,
                     test_section_timeout=False, update_fdt_in_elf=None,
-                    force_missing_bintools='', ignore_missing=False):
+                    force_missing_bintools='', ignore_missing=False, output_dir=None):
         """Run binman with a given test file
 
         Args:
@@ -378,6 +390,7 @@ class TestFunctional(unittest.TestCase):
             update_fdt_in_elf: Value to pass with --update-fdt-in-elf=xxx
             force_missing_tools (str): comma-separated list of bintools to
                 regard as missing
+            output_dir: Specific output directory to use for image using -O
 
         Returns:
             int return code, 0 on success
@@ -424,6 +437,8 @@ class TestFunctional(unittest.TestCase):
         if extra_indirs:
             for indir in extra_indirs:
                 args += ['-I', indir]
+        if output_dir:
+            args += ['-O', output_dir]
         return self._DoBinman(*args)
 
     def _SetupDtb(self, fname, outfile='u-boot.dtb'):
@@ -639,6 +654,16 @@ class TestFunctional(unittest.TestCase):
             tools.read_file(cls.ElfTestFile(src_fname)))
 
     @classmethod
+    def _SetupPmuFwlElf(cls, src_fname='bss_data'):
+        """Set up an ELF file with a '_dt_ucode_base_size' symbol
+
+        Args:
+            Filename of ELF file to use as VPL
+        """
+        TestFunctional._MakeInputFile('pmu-firmware.elf',
+            tools.read_file(cls.ElfTestFile(src_fname)))
+
+    @classmethod
     def _SetupDescriptor(cls):
         with open(cls.TestFile('descriptor.bin'), 'rb') as fd:
             TestFunctional._MakeInputFile('descriptor.bin', fd.read())
@@ -1103,6 +1128,7 @@ class TestFunctional(unittest.TestCase):
 
     def testPackZeroOffset(self):
         """Test that an entry at offset 0 is not given a new offset"""
+        self._SetupSplElf()
         with self.assertRaises(ValueError) as e:
             self._DoTestFile('025_pack_zero_size.dts')
         self.assertIn("Node '/binman/u-boot-spl': Offset 0x0 (0) overlaps "
@@ -1116,6 +1142,7 @@ class TestFunctional(unittest.TestCase):
 
     def testPackX86RomNoSize(self):
         """Test that the end-at-4gb property requires a size property"""
+        self._SetupSplElf()
         with self.assertRaises(ValueError) as e:
             self._DoTestFile('027_pack_4gb_no_size.dts')
         self.assertIn("Image '/binman': Section size must be provided when "
@@ -1124,6 +1151,7 @@ class TestFunctional(unittest.TestCase):
     def test4gbAndSkipAtStartTogether(self):
         """Test that the end-at-4gb and skip-at-size property can't be used
         together"""
+        self._SetupSplElf()
         with self.assertRaises(ValueError) as e:
             self._DoTestFile('098_4gb_and_skip_at_start_together.dts')
         self.assertIn("Image '/binman': Provide either 'end-at-4gb' or "
@@ -1131,6 +1159,7 @@ class TestFunctional(unittest.TestCase):
 
     def testPackX86RomOutside(self):
         """Test that the end-at-4gb property checks for offset boundaries"""
+        self._SetupSplElf()
         with self.assertRaises(ValueError) as e:
             self._DoTestFile('028_pack_4gb_outside.dts')
         self.assertIn("Node '/binman/u-boot': Offset 0x0 (0) size 0x4 (4) "
@@ -1423,6 +1452,7 @@ class TestFunctional(unittest.TestCase):
 
     def testPackUbootSplMicrocode(self):
         """Test that x86 microcode can be handled correctly in SPL"""
+        self._SetupSplElf()
         self._PackUbootSplMicrocode('049_x86_ucode_spl.dts')
 
     def testPackUbootSplMicrocodeReorder(self):
@@ -1442,6 +1472,7 @@ class TestFunctional(unittest.TestCase):
 
     def testSplDtb(self):
         """Test that an image with spl/u-boot-spl.dtb can be created"""
+        self._SetupSplElf()
         data = self._DoReadFile('051_u_boot_spl_dtb.dts')
         self.assertEqual(U_BOOT_SPL_DTB_DATA, data[:len(U_BOOT_SPL_DTB_DATA)])
 
@@ -1452,7 +1483,7 @@ class TestFunctional(unittest.TestCase):
         self.assertEqual(U_BOOT_SPL_NODTB_DATA, data[:len(U_BOOT_SPL_NODTB_DATA)])
 
     def checkSymbols(self, dts, base_data, u_boot_offset, entry_args=None,
-                     use_expanded=False):
+                     use_expanded=False, no_write_symbols=False):
         """Check the image contains the expected symbol values
 
         Args:
@@ -1481,9 +1512,14 @@ class TestFunctional(unittest.TestCase):
         sym_values = struct.pack('<LLQLL', elf.BINMAN_SYM_MAGIC_VALUE,
                                  0x00, u_boot_offset + len(U_BOOT_DATA),
                                  0x10 + u_boot_offset, 0x04)
-        expected = (sym_values + base_data[24:] +
-                    tools.get_bytes(0xff, 1) + U_BOOT_DATA + sym_values +
-                    base_data[24:])
+        if no_write_symbols:
+            expected = (base_data +
+                        tools.get_bytes(0xff, 0x38 - len(base_data)) +
+                        U_BOOT_DATA + base_data)
+        else:
+            expected = (sym_values + base_data[24:] +
+                        tools.get_bytes(0xff, 1) + U_BOOT_DATA + sym_values +
+                        base_data[24:])
         self.assertEqual(expected, data)
 
     def testSymbols(self):
@@ -1957,6 +1993,8 @@ class TestFunctional(unittest.TestCase):
 
     def testUpdateFdtAll(self):
         """Test that all device trees are updated with offset/size info"""
+        self._SetupSplElf()
+        self._SetupTplElf()
         data = self._DoReadFileRealDtb('082_fdt_update_all.dts')
 
         base_expected = {
@@ -3279,6 +3317,8 @@ class TestFunctional(unittest.TestCase):
 
     def testUpdateFdtAllRepack(self):
         """Test that all device trees are updated with offset/size info"""
+        self._SetupSplElf()
+        self._SetupTplElf()
         data = self._DoReadFileRealDtb('134_fdt_update_all_repack.dts')
         SECTION_SIZE = 0x300
         DTB_SIZE = 602
@@ -3732,6 +3772,7 @@ class TestFunctional(unittest.TestCase):
 
     def testMkimage(self):
         """Test using mkimage to build an image"""
+        self._SetupSplElf()
         data = self._DoReadFile('156_mkimage.dts')
 
         # Just check that the data appears in the file somewhere
@@ -3739,6 +3780,7 @@ class TestFunctional(unittest.TestCase):
 
     def testMkimageMissing(self):
         """Test that binman still produces an image if mkimage is missing"""
+        self._SetupSplElf()
         with test_util.capture_sys_output() as (_, stderr):
             self._DoTestFile('156_mkimage.dts',
                              force_missing_bintools='mkimage')
@@ -3764,6 +3806,7 @@ class TestFunctional(unittest.TestCase):
                                    allow_missing=True)
         self.assertEqual(103, ret)
         err = stderr.getvalue()
+        self.assertIn('(missing-file)', err)
         self.assertRegex(err, "Image 'image'.*missing.*: blob-ext")
         self.assertIn('Some images are invalid', err)
 
@@ -3774,6 +3817,7 @@ class TestFunctional(unittest.TestCase):
                                    allow_missing=True, ignore_missing=True)
         self.assertEqual(0, ret)
         err = stderr.getvalue()
+        self.assertIn('(missing-file)', err)
         self.assertRegex(err, "Image 'image'.*missing.*: blob-ext")
         self.assertIn('Some images are invalid', err)
 
@@ -3851,6 +3895,7 @@ class TestFunctional(unittest.TestCase):
 
     def testSimpleFit(self):
         """Test an image with a FIT inside"""
+        self._SetupSplElf()
         data = self._DoReadFile('161_fit.dts')
         self.assertEqual(U_BOOT_DATA, data[:len(U_BOOT_DATA)])
         self.assertEqual(U_BOOT_NODTB_DATA, data[-len(U_BOOT_NODTB_DATA):])
@@ -5370,6 +5415,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
 
     def testFitSubentryHashSubnode(self):
         """Test an image with a FIT inside"""
+        self._SetupSplElf()
         data, _, _, out_dtb_name = self._DoReadFileDtb(
             '221_fit_subentry_hash.dts', use_real_dtb=True, update_dtb=True)
 
@@ -5619,41 +5665,61 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
     def testPreLoad(self):
         """Test an image with a pre-load header"""
         entry_args = {
-            'pre-load-key-path': '.',
+            'pre-load-key-path': os.path.join(self._binman_dir, 'test'),
         }
-        data, _, _, _ = self._DoReadFileDtb('230_pre_load.dts',
-                                            entry_args=entry_args)
-        self.assertEqual(PRE_LOAD_MAGIC, data[:len(PRE_LOAD_MAGIC)])
-        self.assertEqual(PRE_LOAD_VERSION, data[4:4 + len(PRE_LOAD_VERSION)])
-        self.assertEqual(PRE_LOAD_HDR_SIZE, data[8:8 + len(PRE_LOAD_HDR_SIZE)])
-        data = self._DoReadFile('230_pre_load.dts')
+        data = self._DoReadFileDtb(
+            '230_pre_load.dts', entry_args=entry_args,
+            extra_indirs=[os.path.join(self._binman_dir, 'test')])[0]
         self.assertEqual(PRE_LOAD_MAGIC, data[:len(PRE_LOAD_MAGIC)])
         self.assertEqual(PRE_LOAD_VERSION, data[4:4 + len(PRE_LOAD_VERSION)])
         self.assertEqual(PRE_LOAD_HDR_SIZE, data[8:8 + len(PRE_LOAD_HDR_SIZE)])
 
+    def testPreLoadNoKey(self):
+        """Test an image with a pre-load heade0r with missing key"""
+        with self.assertRaises(FileNotFoundError) as exc:
+            self._DoReadFile('230_pre_load.dts')
+        self.assertIn("No such file or directory: 'dev.key'",
+                      str(exc.exception))
+
     def testPreLoadPkcs(self):
         """Test an image with a pre-load header with padding pkcs"""
-        data = self._DoReadFile('231_pre_load_pkcs.dts')
+        entry_args = {
+            'pre-load-key-path': os.path.join(self._binman_dir, 'test'),
+        }
+        data = self._DoReadFileDtb('231_pre_load_pkcs.dts',
+                                   entry_args=entry_args)[0]
         self.assertEqual(PRE_LOAD_MAGIC, data[:len(PRE_LOAD_MAGIC)])
         self.assertEqual(PRE_LOAD_VERSION, data[4:4 + len(PRE_LOAD_VERSION)])
         self.assertEqual(PRE_LOAD_HDR_SIZE, data[8:8 + len(PRE_LOAD_HDR_SIZE)])
 
     def testPreLoadPss(self):
         """Test an image with a pre-load header with padding pss"""
-        data = self._DoReadFile('232_pre_load_pss.dts')
+        entry_args = {
+            'pre-load-key-path': os.path.join(self._binman_dir, 'test'),
+        }
+        data = self._DoReadFileDtb('232_pre_load_pss.dts',
+                                   entry_args=entry_args)[0]
         self.assertEqual(PRE_LOAD_MAGIC, data[:len(PRE_LOAD_MAGIC)])
         self.assertEqual(PRE_LOAD_VERSION, data[4:4 + len(PRE_LOAD_VERSION)])
         self.assertEqual(PRE_LOAD_HDR_SIZE, data[8:8 + len(PRE_LOAD_HDR_SIZE)])
 
     def testPreLoadInvalidPadding(self):
         """Test an image with a pre-load header with an invalid padding"""
+        entry_args = {
+            'pre-load-key-path': os.path.join(self._binman_dir, 'test'),
+        }
         with self.assertRaises(ValueError) as e:
-            data = self._DoReadFile('233_pre_load_invalid_padding.dts')
+            self._DoReadFileDtb('233_pre_load_invalid_padding.dts',
+                                entry_args=entry_args)
 
     def testPreLoadInvalidSha(self):
         """Test an image with a pre-load header with an invalid hash"""
+        entry_args = {
+            'pre-load-key-path': os.path.join(self._binman_dir, 'test'),
+        }
         with self.assertRaises(ValueError) as e:
-            data = self._DoReadFile('234_pre_load_invalid_sha.dts')
+            self._DoReadFileDtb('234_pre_load_invalid_sha.dts',
+                                entry_args=entry_args)
 
     def testPreLoadInvalidAlgo(self):
         """Test an image with a pre-load header with an invalid algo"""
@@ -5662,8 +5728,12 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
 
     def testPreLoadInvalidKey(self):
         """Test an image with a pre-load header with an invalid key"""
+        entry_args = {
+            'pre-load-key-path': os.path.join(self._binman_dir, 'test'),
+        }
         with self.assertRaises(ValueError) as e:
-            data = self._DoReadFile('236_pre_load_invalid_key.dts')
+            data = self._DoReadFileDtb('236_pre_load_invalid_key.dts',
+                                       entry_args=entry_args)
 
     def _CheckSafeUniqueNames(self, *images):
         """Check all entries of given images for unsafe unique names"""
@@ -5888,6 +5958,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
 
     def testMkimageImagename(self):
         """Test using mkimage with -n holding the data too"""
+        self._SetupSplElf()
         data = self._DoReadFile('242_mkimage_name.dts')
 
         # Check that the data appears in the file somewhere
@@ -5905,6 +5976,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
 
     def testMkimageImage(self):
         """Test using mkimage with -n holding the data too"""
+        self._SetupSplElf()
         data = self._DoReadFile('243_mkimage_image.dts')
 
         # Check that the data appears in the file somewhere
@@ -5925,6 +5997,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
 
     def testMkimageImageNoContent(self):
         """Test using mkimage with -n and no data"""
+        self._SetupSplElf()
         with self.assertRaises(ValueError) as exc:
             self._DoReadFile('244_mkimage_image_no_content.dts')
         self.assertIn('Could not complete processing of contents',
@@ -5932,6 +6005,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
 
     def testMkimageImageBad(self):
         """Test using mkimage with imagename node and data-to-imagename"""
+        self._SetupSplElf()
         with self.assertRaises(ValueError) as exc:
             self._DoReadFile('245_mkimage_image_bad.dts')
         self.assertIn('Cannot use both imagename node and data-to-imagename',
@@ -5947,6 +6021,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
 
     def testMkimageCollection(self):
         """Test using a collection referring to an entry in a mkimage entry"""
+        self._SetupSplElf()
         data = self._DoReadFile('247_mkimage_coll.dts')
         expect = U_BOOT_SPL_DATA + U_BOOT_DATA
         self.assertEqual(expect, data[:len(expect)])
@@ -6032,6 +6107,8 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
 
     def testMkimageMultipleDataFiles(self):
         """Test passing multiple files to mkimage in a mkimage entry"""
+        self._SetupSplElf()
+        self._SetupTplElf()
         data = self._DoReadFile('252_mkimage_mult_data.dts')
         # Size of files are packed in their 4B big-endian format
         expect = struct.pack('>I', len(U_BOOT_TPL_DATA))
@@ -6046,8 +6123,42 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
         expect += U_BOOT_SPL_DATA
         self.assertEqual(expect, data[-len(expect):])
 
+    def testMkimageMultipleExpanded(self):
+        """Test passing multiple files to mkimage in a mkimage entry"""
+        self._SetupSplElf()
+        self._SetupTplElf()
+        entry_args = {
+            'spl-bss-pad': 'y',
+            'spl-dtb': 'y',
+        }
+        data = self._DoReadFileDtb('252_mkimage_mult_data.dts',
+                                   use_expanded=True, entry_args=entry_args)[0]
+        pad_len = 10
+        tpl_expect = U_BOOT_TPL_DATA
+        spl_expect = U_BOOT_SPL_NODTB_DATA + tools.get_bytes(0, pad_len)
+        spl_expect += U_BOOT_SPL_DTB_DATA
+
+        content = data[0x40:]
+        lens = struct.unpack('>III', content[:12])
+
+        # Size of files are packed in their 4B big-endian format
+        # Size info is always followed by a 4B zero value.
+        self.assertEqual(len(tpl_expect), lens[0])
+        self.assertEqual(len(spl_expect), lens[1])
+        self.assertEqual(0, lens[2])
+
+        rest = content[12:]
+        self.assertEqual(tpl_expect, rest[:len(tpl_expect)])
+
+        rest = rest[len(tpl_expect):]
+        align_pad = len(tpl_expect) % 4
+        self.assertEqual(tools.get_bytes(0, align_pad), rest[:align_pad])
+        rest = rest[align_pad:]
+        self.assertEqual(spl_expect, rest)
+
     def testMkimageMultipleNoContent(self):
         """Test passing multiple data files to mkimage with one data file having no content"""
+        self._SetupSplElf()
         with self.assertRaises(ValueError) as exc:
             self._DoReadFile('253_mkimage_mult_no_content.dts')
         self.assertIn('Could not complete processing of contents',
@@ -6055,6 +6166,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
 
     def testMkimageFilename(self):
         """Test using mkimage to build a binary with a filename"""
+        self._SetupSplElf()
         retcode = self._DoTestFile('254_mkimage_filename.dts')
         self.assertEqual(0, retcode)
         fname = tools.get_output_filename('mkimage-test.bin')
@@ -6107,7 +6219,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
                       str(e.exception))
 
     def testSymlink(self):
-        """Test that image files can be named"""
+        """Test that image files can be symlinked"""
         retcode = self._DoTestFile('259_symlink.dts', debug=True, map=True)
         self.assertEqual(0, retcode)
         image = control.images['test_image']
@@ -6116,6 +6228,17 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
         self.assertTrue(os.path.islink(sname))
         self.assertEqual(os.readlink(sname), fname)
 
+    def testSymlinkOverwrite(self):
+        """Test that symlinked images can be overwritten"""
+        testdir = TestFunctional._MakeInputDir('symlinktest')
+        self._DoTestFile('259_symlink.dts', debug=True, map=True, output_dir=testdir)
+        # build the same image again in the same directory so that existing symlink is present
+        self._DoTestFile('259_symlink.dts', debug=True, map=True, output_dir=testdir)
+        fname = tools.get_output_filename('test_image.bin')
+        sname = tools.get_output_filename('symlink_to_test.bin')
+        self.assertTrue(os.path.islink(sname))
+        self.assertEqual(os.readlink(sname), fname)
+
     def testSymbolsElf(self):
         """Test binman can assign symbols embedded in an ELF file"""
         if not elf.ELF_TOOLS:
@@ -6237,6 +6360,13 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
                          fdt_util.fdt32_to_cpu(node.props['entry'].value))
         self.assertEqual(U_BOOT_DATA, node.props['data'].bytes)
 
+        with test_util.capture_sys_output() as (stdout, stderr):
+            self.checkFitTee('264_tee_os_opt_fit.dts', '')
+        err = stderr.getvalue()
+        self.assertRegex(
+            err,
+            "Image '.*' is missing optional external blobs but is still functional: tee-os")
+
     def testFitTeeOsOptionalFitBad(self):
         """Test an image with a FIT with an optional OP-TEE binary"""
         with self.assertRaises(ValueError) as exc:
@@ -6269,7 +6399,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
         err = stderr.getvalue()
         self.assertRegex(
             err,
-            "Image '.*' is missing external blobs but is still functional: missing")
+            "Image '.*' is missing optional external blobs but is still functional: missing")
 
     def testSectionInner(self):
         """Test an inner section with a size"""
@@ -6529,6 +6659,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
 
     def testReplaceFitSibling(self):
         """Test an image with a FIT inside where we replace its sibling"""
+        self._SetupSplElf()
         fname = TestFunctional._MakeInputFile('once', b'available once')
         self._DoReadFileRealDtb('277_replace_fit_sibling.dts')
         os.remove(fname)
@@ -6577,18 +6708,18 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
 
     def testPackRockchipTpl(self):
         """Test that an image with a Rockchip TPL binary can be created"""
-        data = self._DoReadFile('277_rockchip_tpl.dts')
+        data = self._DoReadFile('291_rockchip_tpl.dts')
         self.assertEqual(ROCKCHIP_TPL_DATA, data[:len(ROCKCHIP_TPL_DATA)])
 
     def testMkimageMissingBlobMultiple(self):
         """Test missing blob with mkimage entry and multiple-data-files"""
         with test_util.capture_sys_output() as (stdout, stderr):
-            self._DoTestFile('278_mkimage_missing_multiple.dts', allow_missing=True)
+            self._DoTestFile('292_mkimage_missing_multiple.dts', allow_missing=True)
         err = stderr.getvalue()
         self.assertIn("is missing external blobs and is non-functional", err)
 
         with self.assertRaises(ValueError) as e:
-            self._DoTestFile('278_mkimage_missing_multiple.dts', allow_missing=False)
+            self._DoTestFile('292_mkimage_missing_multiple.dts', allow_missing=False)
         self.assertIn("not found in input path", str(e.exception))
 
     def _PrepareSignEnv(self, dts='280_fit_sign.dts'):
@@ -6603,7 +6734,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
                 Private key
                 DTB
         """
-
+        self._SetupSplElf()
         data = self._DoReadFileRealDtb(dts)
         updated_fname = tools.get_output_filename('image-updated.bin')
         tools.write_file(updated_fname, data)
@@ -6676,6 +6807,414 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
                                 ['fit'])
         self.assertIn("Node '/fit': Missing tool: 'mkimage'", str(e.exception))
 
+    def testSymbolNoWrite(self):
+        """Test disabling of symbol writing"""
+        self._SetupSplElf()
+        self.checkSymbols('282_symbols_disable.dts', U_BOOT_SPL_DATA, 0x1c,
+                          no_write_symbols=True)
+
+    def testSymbolNoWriteExpanded(self):
+        """Test disabling of symbol writing in expanded entries"""
+        entry_args = {
+            'spl-dtb': '1',
+        }
+        self.checkSymbols('282_symbols_disable.dts', U_BOOT_SPL_NODTB_DATA +
+                          U_BOOT_SPL_DTB_DATA, 0x38,
+                          entry_args=entry_args, use_expanded=True,
+                          no_write_symbols=True)
+
+    def testMkimageSpecial(self):
+        """Test mkimage ignores special hash-1 node"""
+        data = self._DoReadFile('283_mkimage_special.dts')
+
+        # Just check that the data appears in the file somewhere
+        self.assertIn(U_BOOT_DATA, data)
+
+    def testFitFdtList(self):
+        """Test an image with an FIT with the fit,fdt-list-val option"""
+        entry_args = {
+            'default-dt': 'test-fdt2',
+        }
+        data = self._DoReadFileDtb(
+            '284_fit_fdt_list.dts',
+            entry_args=entry_args,
+            extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0]
+        self.assertEqual(U_BOOT_NODTB_DATA, data[-len(U_BOOT_NODTB_DATA):])
+        fit_data = data[len(U_BOOT_DATA):-len(U_BOOT_NODTB_DATA)]
+
+    def testSplEmptyBss(self):
+        """Test an expanded SPL with a zero-size BSS"""
+        # ELF file with a '__bss_size' symbol
+        self._SetupSplElf(src_fname='bss_data_zero')
+
+        entry_args = {
+            'spl-bss-pad': 'y',
+            'spl-dtb': 'y',
+        }
+        data = self._DoReadFileDtb('285_spl_expand.dts',
+                                   use_expanded=True, entry_args=entry_args)[0]
+
+    def testTemplate(self):
+        """Test using a template"""
+        TestFunctional._MakeInputFile('vga2.bin', b'#' + VGA_DATA)
+        data = self._DoReadFile('286_template.dts')
+        first = U_BOOT_DATA + VGA_DATA + U_BOOT_DTB_DATA
+        second = U_BOOT_DATA + b'#' + VGA_DATA + U_BOOT_DTB_DATA
+        self.assertEqual(U_BOOT_IMG_DATA + first + second, data)
+
+        dtb_fname1 = tools.get_output_filename('u-boot.dtb.tmpl1')
+        self.assertTrue(os.path.exists(dtb_fname1))
+        dtb = fdt.Fdt.FromData(tools.read_file(dtb_fname1))
+        dtb.Scan()
+        node1 = dtb.GetNode('/binman/template')
+        self.assertTrue(node1)
+        vga = dtb.GetNode('/binman/first/intel-vga')
+        self.assertTrue(vga)
+
+        dtb_fname2 = tools.get_output_filename('u-boot.dtb.tmpl2')
+        self.assertTrue(os.path.exists(dtb_fname2))
+        dtb2 = fdt.Fdt.FromData(tools.read_file(dtb_fname2))
+        dtb2.Scan()
+        node2 = dtb2.GetNode('/binman/template')
+        self.assertFalse(node2)
+
+    def testTemplateBlobMulti(self):
+        """Test using a template with 'multiple-images' enabled"""
+        TestFunctional._MakeInputFile('my-blob.bin', b'blob')
+        TestFunctional._MakeInputFile('my-blob2.bin', b'other')
+        retcode = self._DoTestFile('287_template_multi.dts')
+
+        self.assertEqual(0, retcode)
+        image = control.images['image']
+        image_fname = tools.get_output_filename('my-image.bin')
+        data = tools.read_file(image_fname)
+        self.assertEqual(b'blob@@@@other', data)
+
+    def testTemplateFit(self):
+        """Test using a template in a FIT"""
+        fit_data = self._DoReadFile('288_template_fit.dts')
+        fname = os.path.join(self._indir, 'fit_data.fit')
+        tools.write_file(fname, fit_data)
+        out = tools.run('dumpimage', '-l', fname)
+
+    def testTemplateSection(self):
+        """Test using a template in a section (not at top level)"""
+        TestFunctional._MakeInputFile('vga2.bin', b'#' + VGA_DATA)
+        data = self._DoReadFile('289_template_section.dts')
+        first = U_BOOT_DATA + VGA_DATA + U_BOOT_DTB_DATA
+        second = U_BOOT_DATA + b'#' + VGA_DATA + U_BOOT_DTB_DATA
+        self.assertEqual(U_BOOT_IMG_DATA + first + second + first, data)
+
+    def testMkimageSymbols(self):
+        """Test using mkimage to build an image with symbols in it"""
+        self._SetupSplElf('u_boot_binman_syms')
+        data = self._DoReadFile('290_mkimage_sym.dts')
+
+        image = control.images['image']
+        entries = image.GetEntries()
+        self.assertIn('u-boot', entries)
+        u_boot = entries['u-boot']
+
+        mkim = entries['mkimage']
+        mkim_entries = mkim.GetEntries()
+        self.assertIn('u-boot-spl', mkim_entries)
+        spl = mkim_entries['u-boot-spl']
+        self.assertIn('u-boot-spl2', mkim_entries)
+        spl2 = mkim_entries['u-boot-spl2']
+
+        # skip the mkimage header and the area sizes
+        mk_data = data[mkim.offset + 0x40:]
+        size, term = struct.unpack('>LL', mk_data[:8])
+
+        # There should be only one image, so check that the zero terminator is
+        # present
+        self.assertEqual(0, term)
+
+        content = mk_data[8:8 + size]
+
+        # The image should contain the symbols from u_boot_binman_syms.c
+        # Note that image_pos is adjusted by the base address of the image,
+        # which is 0x10 in our test image
+        spl_data = content[:0x18]
+        content = content[0x1b:]
+
+        # After the header is a table of offsets for each image. There should
+        # only be one image, then a 0 terminator, so figure out the real start
+        # of the image data
+        base = 0x40 + 8
+
+        # Check symbols in both u-boot-spl and u-boot-spl2
+        for i in range(2):
+            vals = struct.unpack('<LLQLL', spl_data)
+
+            # The image should contain the symbols from u_boot_binman_syms.c
+            # Note that image_pos is adjusted by the base address of the image,
+            # which is 0x10 in our 'u_boot_binman_syms' test image
+            self.assertEqual(elf.BINMAN_SYM_MAGIC_VALUE, vals[0])
+            self.assertEqual(base, vals[1])
+            self.assertEqual(spl2.offset, vals[2])
+            # figure out the internal positions of its components
+            self.assertEqual(0x10 + u_boot.image_pos, vals[3])
+
+            # Check that spl and spl2 are actually at the indicated positions
+            self.assertEqual(
+                elf.BINMAN_SYM_MAGIC_VALUE,
+                struct.unpack('<I', data[spl.image_pos:spl.image_pos + 4])[0])
+            self.assertEqual(
+                elf.BINMAN_SYM_MAGIC_VALUE,
+                struct.unpack('<I', data[spl2.image_pos:spl2.image_pos + 4])[0])
+
+            self.assertEqual(len(U_BOOT_DATA), vals[4])
+
+            # Move to next
+            spl_data = content[:0x18]
+
+    def testTemplatePhandle(self):
+        """Test using a template in a node containing a phandle"""
+        entry_args = {
+            'atf-bl31-path': 'bl31.elf',
+        }
+        data = self._DoReadFileDtb('309_template_phandle.dts',
+                                   entry_args=entry_args)
+        fname = tools.get_output_filename('image.bin')
+        out = tools.run('dumpimage', '-l', fname)
+
+        # We should see the FIT description and one for each of the two images
+        lines = out.splitlines()
+        descs = [line.split()[-1] for line in lines if 'escription' in line]
+        self.assertEqual(['test-desc', 'atf', 'fdt'], descs)
+
+    def testTemplatePhandleDup(self):
+        """Test using a template in a node containing a phandle"""
+        entry_args = {
+            'atf-bl31-path': 'bl31.elf',
+        }
+        with self.assertRaises(ValueError) as e:
+            self._DoReadFileDtb('310_template_phandle_dup.dts',
+                                entry_args=entry_args)
+        self.assertIn(
+            'Duplicate phandle 1 in nodes /binman/image/fit/images/atf/atf-bl31 and /binman/image-2/fit/images/atf/atf-bl31',
+            str(e.exception))
+
+    def testTIBoardConfig(self):
+        """Test that a schema validated board config file can be generated"""
+        data = self._DoReadFile('293_ti_board_cfg.dts')
+        self.assertEqual(TI_BOARD_CONFIG_DATA, data)
+
+    def testTIBoardConfigCombined(self):
+        """Test that a schema validated combined board config file can be generated"""
+        data = self._DoReadFile('294_ti_board_cfg_combined.dts')
+        configlen_noheader = TI_BOARD_CONFIG_DATA * 4
+        self.assertGreater(data, configlen_noheader)
+
+    def testTIBoardConfigNoDataType(self):
+        """Test that error is thrown when data type is not supported"""
+        with self.assertRaises(ValueError) as e:
+            data = self._DoReadFile('295_ti_board_cfg_no_type.dts')
+        self.assertIn("Schema validation error", str(e.exception))
+
+    def testPackTiSecure(self):
+        """Test that an image with a TI secured binary can be created"""
+        keyfile = self.TestFile('key.key')
+        entry_args = {
+            'keyfile': keyfile,
+        }
+        data = self._DoReadFileDtb('296_ti_secure.dts',
+                                   entry_args=entry_args)[0]
+        self.assertGreater(len(data), len(TI_UNSECURE_DATA))
+
+    def testPackTiSecureMissingTool(self):
+        """Test that an image with a TI secured binary (non-functional) can be created
+        when openssl is missing"""
+        keyfile = self.TestFile('key.key')
+        entry_args = {
+            'keyfile': keyfile,
+        }
+        with test_util.capture_sys_output() as (_, stderr):
+            self._DoTestFile('296_ti_secure.dts',
+                             force_missing_bintools='openssl',
+                             entry_args=entry_args)
+        err = stderr.getvalue()
+        self.assertRegex(err, "Image 'image'.*missing bintools.*: openssl")
+
+    def testPackTiSecureROM(self):
+        """Test that a ROM image with a TI secured binary can be created"""
+        keyfile = self.TestFile('key.key')
+        entry_args = {
+            'keyfile': keyfile,
+        }
+        data = self._DoReadFileDtb('297_ti_secure_rom.dts',
+                                entry_args=entry_args)[0]
+        data_a = self._DoReadFileDtb('299_ti_secure_rom_a.dts',
+                                entry_args=entry_args)[0]
+        data_b = self._DoReadFileDtb('300_ti_secure_rom_b.dts',
+                                entry_args=entry_args)[0]
+        self.assertGreater(len(data), len(TI_UNSECURE_DATA))
+        self.assertGreater(len(data_a), len(TI_UNSECURE_DATA))
+        self.assertGreater(len(data_b), len(TI_UNSECURE_DATA))
+
+    def testPackTiSecureROMCombined(self):
+        """Test that a ROM image with a TI secured binary can be created"""
+        keyfile = self.TestFile('key.key')
+        entry_args = {
+            'keyfile': keyfile,
+        }
+        data = self._DoReadFileDtb('298_ti_secure_rom_combined.dts',
+                                entry_args=entry_args)[0]
+        self.assertGreater(len(data), len(TI_UNSECURE_DATA))
+
+    def testEncryptedNoAlgo(self):
+        """Test encrypted node with missing required properties"""
+        with self.assertRaises(ValueError) as e:
+            self._DoReadFileDtb('301_encrypted_no_algo.dts')
+        self.assertIn(
+            "Node '/binman/fit/images/u-boot/encrypted': 'encrypted' entry is missing properties: algo iv-filename",
+            str(e.exception))
+
+    def testEncryptedInvalidIvfile(self):
+        """Test encrypted node with invalid iv file"""
+        with self.assertRaises(ValueError) as e:
+            self._DoReadFileDtb('302_encrypted_invalid_iv_file.dts')
+        self.assertIn("Filename 'invalid-iv-file' not found in input path",
+                      str(e.exception))
+
+    def testEncryptedMissingKey(self):
+        """Test encrypted node with missing key properties"""
+        with self.assertRaises(ValueError) as e:
+            self._DoReadFileDtb('303_encrypted_missing_key.dts')
+        self.assertIn(
+            "Node '/binman/fit/images/u-boot/encrypted': Provide either 'key-filename' or 'key-source'",
+            str(e.exception))
+
+    def testEncryptedKeySource(self):
+        """Test encrypted node with key-source property"""
+        data = self._DoReadFileDtb('304_encrypted_key_source.dts')[0]
+
+        dtb = fdt.Fdt.FromData(data)
+        dtb.Scan()
+
+        node = dtb.GetNode('/images/u-boot/cipher')
+        self.assertEqual('algo-name', node.props['algo'].value)
+        self.assertEqual('key-source-value', node.props['key-source'].value)
+        self.assertEqual(ENCRYPTED_IV_DATA,
+                         tools.to_bytes(''.join(node.props['iv'].value)))
+        self.assertNotIn('key', node.props)
+
+    def testEncryptedKeyFile(self):
+        """Test encrypted node with key-filename property"""
+        data = self._DoReadFileDtb('305_encrypted_key_file.dts')[0]
+
+        dtb = fdt.Fdt.FromData(data)
+        dtb.Scan()
+
+        node = dtb.GetNode('/images/u-boot/cipher')
+        self.assertEqual('algo-name', node.props['algo'].value)
+        self.assertEqual(ENCRYPTED_IV_DATA,
+                         tools.to_bytes(''.join(node.props['iv'].value)))
+        self.assertEqual(ENCRYPTED_KEY_DATA,
+                         tools.to_bytes(''.join(node.props['key'].value)))
+        self.assertNotIn('key-source', node.props)
+
+
+    def testSplPubkeyDtb(self):
+         """Test u_boot_spl_pubkey_dtb etype"""
+         data = tools.read_file(self.TestFile("key.pem"))
+         self._MakeInputFile("key.crt", data)
+         self._DoReadFileRealDtb('306_spl_pubkey_dtb.dts')
+         image = control.images['image']
+         entries = image.GetEntries()
+         dtb_entry = entries['u-boot-spl-pubkey-dtb']
+         dtb_data = dtb_entry.GetData()
+         dtb = fdt.Fdt.FromData(dtb_data)
+         dtb.Scan()
+
+         signature_node = dtb.GetNode('/signature')
+         self.assertIsNotNone(signature_node)
+         key_node = signature_node.FindNode("key-key")
+         self.assertIsNotNone(key_node)
+         self.assertEqual(fdt_util.GetString(key_node, "required"),
+                          "conf")
+         self.assertEqual(fdt_util.GetString(key_node, "algo"),
+                          "sha384,rsa4096")
+         self.assertEqual(fdt_util.GetString(key_node, "key-name-hint"),
+                          "key")
+
+    def testXilinxBootgenSigning(self):
+        """Test xilinx-bootgen etype"""
+        bootgen = bintool.Bintool.create('bootgen')
+        self._CheckBintool(bootgen)
+        data = tools.read_file(self.TestFile("key.key"))
+        self._MakeInputFile("psk.pem", data)
+        self._MakeInputFile("ssk.pem", data)
+        self._SetupPmuFwlElf()
+        self._SetupSplElf()
+        self._DoReadFileRealDtb('307_xilinx_bootgen_sign.dts')
+        image_fname = tools.get_output_filename('image.bin')
+
+        # Read partition header table and check if authentication is enabled
+        bootgen_out = bootgen.run_cmd("-arch", "zynqmp",
+                                      "-read", image_fname, "pht").splitlines()
+        attributes = {"authentication": None,
+                      "core": None,
+                      "encryption": None}
+
+        for l in bootgen_out:
+            for a in attributes.keys():
+                if a in l:
+                   m = re.match(fr".*{a} \[([^]]+)\]", l)
+                   attributes[a] = m.group(1)
+
+        self.assertTrue(attributes['authentication'] == "rsa")
+        self.assertTrue(attributes['core'] == "a53-0")
+        self.assertTrue(attributes['encryption'] == "no")
+
+    def testXilinxBootgenSigningEncryption(self):
+        """Test xilinx-bootgen etype"""
+        bootgen = bintool.Bintool.create('bootgen')
+        self._CheckBintool(bootgen)
+        data = tools.read_file(self.TestFile("key.key"))
+        self._MakeInputFile("psk.pem", data)
+        self._MakeInputFile("ssk.pem", data)
+        self._SetupPmuFwlElf()
+        self._SetupSplElf()
+        self._DoReadFileRealDtb('308_xilinx_bootgen_sign_enc.dts')
+        image_fname = tools.get_output_filename('image.bin')
+
+        # Read boot header in order to verify encryption source and
+        # encryption parameter
+        bootgen_out = bootgen.run_cmd("-arch", "zynqmp",
+                                      "-read", image_fname, "bh").splitlines()
+        attributes = {"auth_only":
+                        {"re": r".*auth_only \[([^]]+)\]", "value": None},
+                      "encryption_keystore":
+                        {"re": r" *encryption_keystore \(0x28\) : (.*)",
+                            "value": None},
+                     }
+
+        for l in bootgen_out:
+            for a in attributes.keys():
+                if a in l:
+                   m = re.match(attributes[a]['re'], l)
+                   attributes[a] = m.group(1)
+
+        # Check if fsbl-attribute is set correctly
+        self.assertTrue(attributes['auth_only'] == "true")
+        # Check if key is stored in efuse
+        self.assertTrue(attributes['encryption_keystore'] == "0xa5c3c5a3")
+
+    def testXilinxBootgenMissing(self):
+        """Test that binman still produces an image if bootgen is missing"""
+        data = tools.read_file(self.TestFile("key.key"))
+        self._MakeInputFile("psk.pem", data)
+        self._MakeInputFile("ssk.pem", data)
+        self._SetupPmuFwlElf()
+        self._SetupSplElf()
+        with test_util.capture_sys_output() as (_, stderr):
+            self._DoTestFile('307_xilinx_bootgen_sign.dts',
+                             force_missing_bintools='bootgen')
+        err = stderr.getvalue()
+        self.assertRegex(err,
+                         "Image 'image'.*missing bintools.*: bootgen")
 
 if __name__ == "__main__":
     unittest.main()
diff --git a/tools/binman/image.py b/tools/binman/image.py
index 8ebf71d61a..e77b5d0d97 100644
--- a/tools/binman/image.py
+++ b/tools/binman/image.py
@@ -182,6 +182,8 @@ class Image(section.Entry_section):
         # Create symlink to file if symlink given
         if self._symlink is not None:
             sname = tools.get_output_filename(self._symlink)
+            if os.path.islink(sname):
+                os.remove(sname)
             os.symlink(fname, sname)
 
     def WriteMap(self):
diff --git a/tools/binman/missing-blob-help b/tools/binman/missing-blob-help
index f013367ac3..ab0023eb9f 100644
--- a/tools/binman/missing-blob-help
+++ b/tools/binman/missing-blob-help
@@ -43,7 +43,7 @@ for the external TPL binary is https://github.com/rockchip-linux/rkbin.
 
 tee-os:
 See the documentation for your board. You may need to build Open Portable
-Trusted Execution Environment (OP-TEE) with TEE=/path/to/tee.bin
+Trusted Execution Environment (OP-TEE) and build with TEE=/path/to/tee.bin
 
 opensbi:
 See the documentation for your board. The OpenSBI git repo is at
diff --git a/tools/binman/state.py b/tools/binman/state.py
index 3e78cf3430..45bae40c52 100644
--- a/tools/binman/state.py
+++ b/tools/binman/state.py
@@ -385,8 +385,8 @@ def SetInt(node, prop, value, for_repack=False):
         for_repack: True is this property is only needed for repacking
     """
     for n in GetUpdateNodes(node, for_repack):
-        tout.detail("File %s: Update node '%s' prop '%s' to %#x" %
-                    (n.GetFdt().name, n.path, prop, value))
+        tout.debug("File %s: Update node '%s' prop '%s' to %#x" %
+                   (n.GetFdt().name, n.path, prop, value))
         n.SetInt(prop, value)
 
 def CheckAddHashProp(node):
diff --git a/tools/binman/test/230_pre_load.dts b/tools/binman/test/230_pre_load.dts
index c0c24729f8..e6d9ef40c6 100644
--- a/tools/binman/test/230_pre_load.dts
+++ b/tools/binman/test/230_pre_load.dts
@@ -10,7 +10,7 @@
 		pre-load {
 			content = <&image>;
 			 algo-name = "sha256,rsa2048";
-			 key-name = "tools/binman/test/230_dev.key";
+			 key-name = "dev.key";
 			 header-size = <4096>;
 			 version = <0x11223344>;
 		};
diff --git a/tools/binman/test/231_pre_load_pkcs.dts b/tools/binman/test/231_pre_load_pkcs.dts
index 530638c56b..66268cdb21 100644
--- a/tools/binman/test/231_pre_load_pkcs.dts
+++ b/tools/binman/test/231_pre_load_pkcs.dts
@@ -11,7 +11,7 @@
 			content = <&image>;
 			 algo-name = "sha256,rsa2048";
 			 padding-name = "pkcs-1.5";
-			 key-name = "tools/binman/test/230_dev.key";
+			 key-name = "dev.key";
 			 header-size = <4096>;
 			 version = <0x11223344>;
 		};
diff --git a/tools/binman/test/232_pre_load_pss.dts b/tools/binman/test/232_pre_load_pss.dts
index 371e0fdb40..3008d3f464 100644
--- a/tools/binman/test/232_pre_load_pss.dts
+++ b/tools/binman/test/232_pre_load_pss.dts
@@ -11,7 +11,7 @@
 			content = <&image>;
 			 algo-name = "sha256,rsa2048";
 			 padding-name = "pss";
-			 key-name = "tools/binman/test/230_dev.key";
+			 key-name = "dev.key";
 			 header-size = <4096>;
 			 version = <0x11223344>;
 		};
diff --git a/tools/binman/test/233_pre_load_invalid_padding.dts b/tools/binman/test/233_pre_load_invalid_padding.dts
index 9cb4cb570b..bbe2d1ba86 100644
--- a/tools/binman/test/233_pre_load_invalid_padding.dts
+++ b/tools/binman/test/233_pre_load_invalid_padding.dts
@@ -11,7 +11,7 @@
 			content = <&image>;
 			 algo-name = "sha256,rsa2048";
 			 padding-name = "padding";
-			 key-name = "tools/binman/test/230_dev.key";
+			 key-name = "dev.key";
 			 header-size = <4096>;
 			 version = <1>;
 		};
diff --git a/tools/binman/test/234_pre_load_invalid_sha.dts b/tools/binman/test/234_pre_load_invalid_sha.dts
index 8ded98df53..29afd2e37e 100644
--- a/tools/binman/test/234_pre_load_invalid_sha.dts
+++ b/tools/binman/test/234_pre_load_invalid_sha.dts
@@ -11,7 +11,7 @@
 			content = <&image>;
 			 algo-name = "sha2560,rsa2048";
 			 padding-name = "pkcs-1.5";
-			 key-name = "tools/binman/test/230_dev.key";
+			 key-name = "dev.key";
 			 header-size = <4096>;
 			 version = <1>;
 		};
diff --git a/tools/binman/test/235_pre_load_invalid_algo.dts b/tools/binman/test/235_pre_load_invalid_algo.dts
index 145286caa3..d6f6dd20cd 100644
--- a/tools/binman/test/235_pre_load_invalid_algo.dts
+++ b/tools/binman/test/235_pre_load_invalid_algo.dts
@@ -11,7 +11,7 @@
 			content = <&image>;
 			 algo-name = "sha256,rsa20480";
 			 padding-name = "pkcs-1.5";
-			 key-name = "tools/binman/test/230_dev.key";
+			 key-name = "dev.key";
 			 header-size = <4096>;
 			 version = <1>;
 		};
diff --git a/tools/binman/test/236_pre_load_invalid_key.dts b/tools/binman/test/236_pre_load_invalid_key.dts
index df858c3a28..f93bc9792c 100644
--- a/tools/binman/test/236_pre_load_invalid_key.dts
+++ b/tools/binman/test/236_pre_load_invalid_key.dts
@@ -11,7 +11,7 @@
 			content = <&image>;
 			 algo-name = "sha256,rsa4096";
 			 padding-name = "pkcs-1.5";
-			 key-name = "tools/binman/test/230_dev.key";
+			 key-name = "dev.key";
 			 header-size = <4096>;
 			 version = <1>;
 		};
diff --git a/tools/binman/test/264_tee_os_opt_fit.dts b/tools/binman/test/264_tee_os_opt_fit.dts
index ae44b433ed..e9634d3ccd 100644
--- a/tools/binman/test/264_tee_os_opt_fit.dts
+++ b/tools/binman/test/264_tee_os_opt_fit.dts
@@ -25,6 +25,7 @@
 					fit,data;
 
 					tee-os {
+						optional;
 					};
 				};
 			};
diff --git a/tools/binman/test/282_symbols_disable.dts b/tools/binman/test/282_symbols_disable.dts
new file mode 100644
index 0000000000..6efa933504
--- /dev/null
+++ b/tools/binman/test/282_symbols_disable.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		pad-byte = <0xff>;
+		u-boot-spl {
+			no-write-symbols;
+		};
+
+		u-boot {
+			offset = <0x38>;
+			no-expanded;
+		};
+
+		u-boot-spl2 {
+			type = "u-boot-spl";
+			no-write-symbols;
+		};
+	};
+};
diff --git a/tools/binman/test/283_mkimage_special.dts b/tools/binman/test/283_mkimage_special.dts
new file mode 100644
index 0000000000..c234093e6e
--- /dev/null
+++ b/tools/binman/test/283_mkimage_special.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		mkimage {
+			args = "-T script";
+
+			u-boot {
+			};
+
+			hash {
+			};
+
+			imagename {
+				type = "u-boot";
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/284_fit_fdt_list.dts b/tools/binman/test/284_fit_fdt_list.dts
new file mode 100644
index 0000000000..8885313f5b
--- /dev/null
+++ b/tools/binman/test/284_fit_fdt_list.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		u-boot {
+		};
+		fit {
+			description = "test-desc";
+			#address-cells = <1>;
+			fit,fdt-list-val = "test-fdt1", "test-fdt2";
+
+			images {
+				kernel {
+					description = "Vanilla Linux kernel";
+					type = "kernel";
+					arch = "ppc";
+					os = "linux";
+					compression = "gzip";
+					load = <00000000>;
+					entry = <00000000>;
+					hash-1 {
+						algo = "crc32";
+					};
+					hash-2 {
+						algo = "sha1";
+					};
+					u-boot {
+					};
+				};
+				@fdt-SEQ {
+					description = "fdt-NAME.dtb";
+					type = "flat_dt";
+					compression = "none";
+					hash {
+						algo = "sha256";
+					};
+				};
+			};
+
+			configurations {
+				default = "@config-DEFAULT-SEQ";
+				@config-SEQ {
+					description = "conf-NAME.dtb";
+					firmware = "uboot";
+					loadables = "atf";
+					fdt = "fdt-SEQ";
+				};
+			};
+		};
+		u-boot-nodtb {
+		};
+	};
+};
diff --git a/tools/binman/test/285_spl_expand.dts b/tools/binman/test/285_spl_expand.dts
new file mode 100644
index 0000000000..9c88ccb287
--- /dev/null
+++ b/tools/binman/test/285_spl_expand.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		u-boot-spl {
+		};
+	};
+};
diff --git a/tools/binman/test/286_template.dts b/tools/binman/test/286_template.dts
new file mode 100644
index 0000000000..6980dbfafc
--- /dev/null
+++ b/tools/binman/test/286_template.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		u-boot-img {
+		};
+
+		common_part: template {
+			u-boot {
+			};
+
+			intel-vga {
+				filename = "vga.bin";
+			};
+		};
+
+		first {
+			type = "section";
+			insert-template = <&common_part>;
+
+			u-boot-dtb {
+			};
+		};
+
+		second {
+			type = "section";
+			insert-template = <&common_part>;
+
+			u-boot-dtb {
+			};
+
+			intel-vga {
+				filename = "vga2.bin";
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/287_template_multi.dts b/tools/binman/test/287_template_multi.dts
new file mode 100644
index 0000000000..122bfccd56
--- /dev/null
+++ b/tools/binman/test/287_template_multi.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+/ {
+	binman: binman {
+		multiple-images;
+
+		my_template: template {
+			blob-ext@0 {
+				filename = "my-blob.bin";
+				offset = <0>;
+			};
+			blob-ext@8 {
+				offset = <8>;
+			};
+		};
+
+		image {
+			pad-byte = <0x40>;
+			filename = "my-image.bin";
+			insert-template = <&my_template>;
+			blob-ext@8 {
+				filename = "my-blob2.bin";
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/288_template_fit.dts b/tools/binman/test/288_template_fit.dts
new file mode 100644
index 0000000000..d84dca4ea4
--- /dev/null
+++ b/tools/binman/test/288_template_fit.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	binman: binman {
+		multiple-images;
+
+		my_template: template {
+			fit@0 {
+				images {
+					kernel-1 {
+					};
+					kernel-2 {
+					};
+				};
+			};
+		};
+
+		image {
+			filename = "image.bin";
+			insert-template = <&my_template>;
+
+			fit@0 {
+				description = "desc";
+				configurations {
+				};
+				images {
+					kernel-3 {
+					};
+					kernel-4 {
+					};
+				};
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/289_template_section.dts b/tools/binman/test/289_template_section.dts
new file mode 100644
index 0000000000..8a744a0cf6
--- /dev/null
+++ b/tools/binman/test/289_template_section.dts
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		u-boot-img {
+		};
+
+		common_part: template {
+			u-boot {
+			};
+
+			intel-vga {
+				filename = "vga.bin";
+			};
+		};
+
+		first {
+			type = "section";
+			insert-template = <&common_part>;
+
+			u-boot-dtb {
+			};
+		};
+
+		section {
+			second {
+				type = "section";
+				insert-template = <&common_part>;
+
+				u-boot-dtb {
+				};
+
+				intel-vga {
+					filename = "vga2.bin";
+				};
+			};
+		};
+
+		second {
+			type = "section";
+			insert-template = <&common_part>;
+
+			u-boot-dtb {
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/290_mkimage_sym.dts b/tools/binman/test/290_mkimage_sym.dts
new file mode 100644
index 0000000000..2dfd286ad4
--- /dev/null
+++ b/tools/binman/test/290_mkimage_sym.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		u-boot-dtb {
+		};
+
+		mkimage {
+			args = "-n test -T script";
+
+			u-boot-spl {
+			};
+
+			u-boot-spl2 {
+				type = "u-boot-spl";
+			};
+		};
+
+		u-boot {
+		};
+	};
+};
diff --git a/tools/binman/test/277_rockchip_tpl.dts b/tools/binman/test/291_rockchip_tpl.dts
index 269f56e254..269f56e254 100644
--- a/tools/binman/test/277_rockchip_tpl.dts
+++ b/tools/binman/test/291_rockchip_tpl.dts
diff --git a/tools/binman/test/278_mkimage_missing_multiple.dts b/tools/binman/test/292_mkimage_missing_multiple.dts
index f84aea49ea..f84aea49ea 100644
--- a/tools/binman/test/278_mkimage_missing_multiple.dts
+++ b/tools/binman/test/292_mkimage_missing_multiple.dts
diff --git a/tools/binman/test/293_ti_board_cfg.dts b/tools/binman/test/293_ti_board_cfg.dts
new file mode 100644
index 0000000000..cda024c1b8
--- /dev/null
+++ b/tools/binman/test/293_ti_board_cfg.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		ti-board-config {
+			config = "yaml/config.yaml";
+			schema = "yaml/schema.yaml";
+		};
+	};
+};
diff --git a/tools/binman/test/294_ti_board_cfg_combined.dts b/tools/binman/test/294_ti_board_cfg_combined.dts
new file mode 100644
index 0000000000..95ef449cbf
--- /dev/null
+++ b/tools/binman/test/294_ti_board_cfg_combined.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+	binman {
+		ti-board-config {
+			board-cfg {
+				config = "yaml/config.yaml";
+				schema = "yaml/schema.yaml";
+			};
+			sec-cfg {
+				config = "yaml/config.yaml";
+				schema = "yaml/schema.yaml";
+			};
+			rm-cfg {
+				config = "yaml/config.yaml";
+				schema = "yaml/schema.yaml";
+			};
+			pm-cfg {
+				config = "yaml/config.yaml";
+				schema = "yaml/schema.yaml";
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/295_ti_board_cfg_no_type.dts b/tools/binman/test/295_ti_board_cfg_no_type.dts
new file mode 100644
index 0000000000..584b7acc5a
--- /dev/null
+++ b/tools/binman/test/295_ti_board_cfg_no_type.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+	binman {
+		ti-board-config {
+			config = "yaml/config.yaml";
+			schema = "yaml/schema_notype.yaml";
+		};
+	};
+};
diff --git a/tools/binman/test/296_ti_secure.dts b/tools/binman/test/296_ti_secure.dts
new file mode 100644
index 0000000000..941d0ab4ca
--- /dev/null
+++ b/tools/binman/test/296_ti_secure.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		ti-secure {
+			content = <&unsecure_binary>;
+		};
+		unsecure_binary: blob-ext {
+			filename = "ti_unsecure.bin";
+		};
+	};
+};
diff --git a/tools/binman/test/297_ti_secure_rom.dts b/tools/binman/test/297_ti_secure_rom.dts
new file mode 100644
index 0000000000..d1313769f4
--- /dev/null
+++ b/tools/binman/test/297_ti_secure_rom.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		ti-secure-rom {
+			content = <&unsecure_binary>;
+		};
+		unsecure_binary: blob-ext {
+			filename = "ti_unsecure.bin";
+		};
+	};
+};
diff --git a/tools/binman/test/298_ti_secure_rom_combined.dts b/tools/binman/test/298_ti_secure_rom_combined.dts
new file mode 100644
index 0000000000..bf872739bc
--- /dev/null
+++ b/tools/binman/test/298_ti_secure_rom_combined.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		ti-secure-rom {
+			content = <&unsecure_binary>;
+			content-sbl = <&unsecure_binary>;
+			content-sysfw = <&unsecure_binary>;
+			content-sysfw-data = <&unsecure_binary>;
+			content-sysfw-inner-cert = <&unsecure_binary>;
+			content-dm-data = <&unsecure_binary>;
+			combined;
+			sysfw-inner-cert;
+			dm-data;
+		};
+		unsecure_binary: blob-ext {
+			filename = "ti_unsecure.bin";
+		};
+	};
+};
diff --git a/tools/binman/test/299_ti_secure_rom_a.dts b/tools/binman/test/299_ti_secure_rom_a.dts
new file mode 100644
index 0000000000..887138f0e4
--- /dev/null
+++ b/tools/binman/test/299_ti_secure_rom_a.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		ti-secure-rom {
+			content = <&unsecure_binary>;
+			core = "secure";
+			countersign;
+		};
+		unsecure_binary: blob-ext {
+			filename = "ti_unsecure.bin";
+		};
+	};
+};
diff --git a/tools/binman/test/300_ti_secure_rom_b.dts b/tools/binman/test/300_ti_secure_rom_b.dts
new file mode 100644
index 0000000000..c6d6182158
--- /dev/null
+++ b/tools/binman/test/300_ti_secure_rom_b.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		ti-secure-rom {
+			content = <&unsecure_binary>;
+			core = "public";
+		};
+		unsecure_binary: blob-ext {
+			filename = "ti_unsecure.bin";
+		};
+	};
+};
diff --git a/tools/binman/test/301_encrypted_no_algo.dts b/tools/binman/test/301_encrypted_no_algo.dts
new file mode 100644
index 0000000000..03f7ffee90
--- /dev/null
+++ b/tools/binman/test/301_encrypted_no_algo.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+	binman {
+		fit {
+			images {
+				u-boot {
+					encrypted {
+					};
+				};
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/302_encrypted_invalid_iv_file.dts b/tools/binman/test/302_encrypted_invalid_iv_file.dts
new file mode 100644
index 0000000000..388a0a6ad9
--- /dev/null
+++ b/tools/binman/test/302_encrypted_invalid_iv_file.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+	binman {
+		fit {
+			images {
+				u-boot {
+					encrypted {
+						algo = "some-algo";
+						key-source = "key";
+						iv-filename = "invalid-iv-file";
+					};
+				};
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/303_encrypted_missing_key.dts b/tools/binman/test/303_encrypted_missing_key.dts
new file mode 100644
index 0000000000..d1daaa0885
--- /dev/null
+++ b/tools/binman/test/303_encrypted_missing_key.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		fit {
+			description = "test desc";
+
+			images {
+				u-boot {
+					encrypted {
+						algo = "algo-name";
+						iv-filename = "encrypted-file.iv";
+					};
+				};
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/304_encrypted_key_source.dts b/tools/binman/test/304_encrypted_key_source.dts
new file mode 100644
index 0000000000..884ec508db
--- /dev/null
+++ b/tools/binman/test/304_encrypted_key_source.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		fit {
+			description = "test desc";
+
+			images {
+				u-boot {
+					encrypted {
+						algo = "algo-name";
+						key-source = "key-source-value";
+						iv-filename = "encrypted-file.iv";
+					};
+				};
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/305_encrypted_key_file.dts b/tools/binman/test/305_encrypted_key_file.dts
new file mode 100644
index 0000000000..efd7ee5f35
--- /dev/null
+++ b/tools/binman/test/305_encrypted_key_file.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		fit {
+			description = "test desc";
+
+			images {
+				u-boot {
+					encrypted {
+						algo = "algo-name";
+						iv-filename = "encrypted-file.iv";
+						key-filename = "encrypted-file.key";
+					};
+				};
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/306_spl_pubkey_dtb.dts b/tools/binman/test/306_spl_pubkey_dtb.dts
new file mode 100644
index 0000000000..3256ff970c
--- /dev/null
+++ b/tools/binman/test/306_spl_pubkey_dtb.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		u-boot-spl-pubkey-dtb {
+			algo = "sha384,rsa4096";
+			required = "conf";
+			key-name-hint = "key";
+		};
+	};
+};
diff --git a/tools/binman/test/307_xilinx_bootgen_sign.dts b/tools/binman/test/307_xilinx_bootgen_sign.dts
new file mode 100644
index 0000000000..02acf8652a
--- /dev/null
+++ b/tools/binman/test/307_xilinx_bootgen_sign.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		xilinx-bootgen {
+			auth-params = "ppk_select=0", "spk_id=0x00000000";
+			pmufw-filename = "pmu-firmware.elf";
+			psk-key-name-hint = "psk";
+			ssk-key-name-hint = "ssk";
+
+			u-boot-spl-nodtb {
+			};
+			u-boot-spl-dtb {
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/308_xilinx_bootgen_sign_enc.dts b/tools/binman/test/308_xilinx_bootgen_sign_enc.dts
new file mode 100644
index 0000000000..5d7ce4c1f5
--- /dev/null
+++ b/tools/binman/test/308_xilinx_bootgen_sign_enc.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		xilinx-bootgen {
+			auth-params = "ppk_select=0", "spk_id=0x00000000";
+			fsbl-config = "auth_only";
+			keysrc-enc = "efuse_red_key";
+			pmufw-filename = "pmu-firmware.elf";
+			psk-key-name-hint = "psk";
+			ssk-key-name-hint = "ssk";
+
+			u-boot-spl-nodtb {
+			};
+			u-boot-spl-dtb {
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/309_template_phandle.dts b/tools/binman/test/309_template_phandle.dts
new file mode 100644
index 0000000000..c4ec1dd41b
--- /dev/null
+++ b/tools/binman/test/309_template_phandle.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		multiple-images;
+
+		ti_spl_template: template-1 {
+			fit {
+				description = "test-desc";
+				#address-cells = <1>;
+				images {
+					atf {
+						description = "atf";
+						ti-secure {
+							type = "collection";
+							content = <&atf>;
+							keyfile = "key.pem";
+						};
+						atf: atf-bl31 {
+							description = "atf";
+						};
+					};
+				};
+			};
+		};
+
+		image {
+			insert-template = <&ti_spl_template>;
+			fit {
+				images {
+					fdt-0 {
+						description = "fdt";
+						ti-secure {
+							type = "collection";
+							content = <&foo_dtb>;
+							keyfile = "key.pem";
+						};
+						foo_dtb: blob-ext {
+							filename = "vga.bin";
+						};
+					};
+				};
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/310_template_phandle_dup.dts b/tools/binman/test/310_template_phandle_dup.dts
new file mode 100644
index 0000000000..dc86f06463
--- /dev/null
+++ b/tools/binman/test/310_template_phandle_dup.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		multiple-images;
+
+		ti_spl_template: template-1 {
+			fit {
+				description = "test-desc";
+				#address-cells = <1>;
+				images {
+					atf {
+						description = "atf";
+						ti-secure {
+							type = "collection";
+							content = <&atf>;
+							keyfile = "key.pem";
+						};
+						atf: atf-bl31 {
+							description = "atf";
+						};
+					};
+				};
+			};
+		};
+
+		image {
+			insert-template = <&ti_spl_template>;
+			fit {
+				images {
+					fdt-0 {
+						description = "fdt";
+						ti-secure {
+							type = "collection";
+							content = <&foo_dtb>;
+							keyfile = "key.pem";
+						};
+						foo_dtb: blob-ext {
+							filename = "vga.bin";
+						};
+					};
+				};
+			};
+		};
+
+		image-2 {
+			insert-template = <&ti_spl_template>;
+			fit {
+				images {
+					fdt-0 {
+						description = "fdt";
+						blob-ext {
+							filename = "vga.bin";
+						};
+					};
+				};
+			};
+		};
+	};
+};
diff --git a/tools/binman/test/Makefile b/tools/binman/test/Makefile
index cd66a3038b..4d152eee9c 100644
--- a/tools/binman/test/Makefile
+++ b/tools/binman/test/Makefile
@@ -32,7 +32,7 @@ LDS_BINMAN_EMBED := -T $(SRC)u_boot_binman_embed.lds
 LDS_EFL_SECTIONS := -T $(SRC)elf_sections.lds
 LDS_BLOB := -T $(SRC)blob_syms.lds
 
-TARGETS = u_boot_ucode_ptr u_boot_no_ucode_ptr bss_data \
+TARGETS = u_boot_ucode_ptr u_boot_no_ucode_ptr bss_data bss_data_zero \
 	u_boot_binman_syms u_boot_binman_syms.bin u_boot_binman_syms_bad \
 	u_boot_binman_syms_size u_boot_binman_syms_x86 embed_data \
 	u_boot_binman_embed u_boot_binman_embed_sm elf_sections blob_syms.bin
@@ -48,6 +48,9 @@ u_boot_ucode_ptr: u_boot_ucode_ptr.c
 bss_data: CFLAGS += $(SRC)bss_data.lds
 bss_data: bss_data.c
 
+bss_data_zero: CFLAGS += $(SRC)bss_data_zero.lds
+bss_data_zero: bss_data_zero.c
+
 embed_data: CFLAGS += $(SRC)embed_data.lds
 embed_data: embed_data.c
 
diff --git a/tools/binman/test/bss_data.c b/tools/binman/test/bss_data.c
index 4f9b64cef9..7047a3bb01 100644
--- a/tools/binman/test/bss_data.c
+++ b/tools/binman/test/bss_data.c
@@ -7,9 +7,8 @@
  */
 
 int bss_data[10];
-int __bss_size = sizeof(bss_data);
 
-int main()
+int main(void)
 {
 	bss_data[2] = 2;
 
diff --git a/tools/binman/test/bss_data_zero.c b/tools/binman/test/bss_data_zero.c
new file mode 100644
index 0000000000..7047a3bb01
--- /dev/null
+++ b/tools/binman/test/bss_data_zero.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * Simple program to create a bss_data region so the symbol can be read
+ * by binutils. This is used by binman tests.
+ */
+
+int bss_data[10];
+
+int main(void)
+{
+	bss_data[2] = 2;
+
+	return 0;
+}
diff --git a/tools/binman/test/bss_data_zero.lds b/tools/binman/test/bss_data_zero.lds
new file mode 100644
index 0000000000..8fa0210a8f
--- /dev/null
+++ b/tools/binman/test/bss_data_zero.lds
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0xfffffdf0;
+	_start = .;
+	__bss_size = 0;
+}
diff --git a/tools/binman/test/230_dev.key b/tools/binman/test/dev.key
index b36bad2cfb..b36bad2cfb 100644
--- a/tools/binman/test/230_dev.key
+++ b/tools/binman/test/dev.key
diff --git a/tools/binman/test/embed_data.lds b/tools/binman/test/embed_data.lds
index 908bf66c29..d416cb2111 100644
--- a/tools/binman/test/embed_data.lds
+++ b/tools/binman/test/embed_data.lds
@@ -17,6 +17,7 @@ SECTIONS
 		embed_start = .;
 		*(.embed*)
 		embed_end = .;
+		region_size = 0;
 		. = ALIGN(32);
 		*(.data*)
 	}
diff --git a/tools/binman/test/yaml/config.yaml b/tools/binman/test/yaml/config.yaml
new file mode 100644
index 0000000000..5f799a6e3a
--- /dev/null
+++ b/tools/binman/test/yaml/config.yaml
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Test config
+#
+---
+
+main-branch:
+  obj:
+    a: 0x0
+    b: 0
+  arr: [0, 0, 0, 0]
+  another-arr:
+    - #1
+      c: 0
+      d: 0
+    - #2
+      c: 0
+      d: 0
diff --git a/tools/binman/test/yaml/schema.yaml b/tools/binman/test/yaml/schema.yaml
new file mode 100644
index 0000000000..8aa03f3c8e
--- /dev/null
+++ b/tools/binman/test/yaml/schema.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Test schema
+#
+---
+
+definitions:
+    u8:
+        type: integer
+        minimum: 0
+        maximum: 0xff
+    u16:
+        type: integer
+        minimum: 0
+        maximum: 0xffff
+    u32:
+        type: integer
+        minimum: 0
+        maximum: 0xffffffff
+
+type: object
+properties:
+    main-branch:
+        type: object
+        properties:
+            obj:
+                type: object
+                properties:
+                    a:
+                        $ref: "#/definitions/u32"
+                    b:
+                        $ref: "#/definitions/u16"
+            arr:
+                type: array
+                minItems: 4
+                maxItems: 4
+                items:
+                    $ref: "#/definitions/u8"
+            another-arr:
+                type: array
+                minItems: 2
+                maxItems: 2
+                items:
+                    type: object
+                    properties:
+                        c:
+                            $ref: "#/definitions/u8"
+                        d:
+                            $ref: "#/definitions/u8"
diff --git a/tools/binman/test/yaml/schema_notype.yaml b/tools/binman/test/yaml/schema_notype.yaml
new file mode 100644
index 0000000000..6b4d98ffa1
--- /dev/null
+++ b/tools/binman/test/yaml/schema_notype.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Test schema
+#
+---
+
+definitions:
+    u8:
+        type: integer
+        minimum: 0
+        maximum: 0xff
+    u16:
+        type: integer
+        minimum: 0
+        maximum: 0xffff
+    u32:
+        type: integer
+        minimum: 0
+        maximum: 0xffffffff
+
+type: object
+properties:
+    main-branch:
+        type: object
+        properties:
+            obj:
+                type: object
+                properties:
+                    a:
+                        $ref: "#/definitions/u4"
+                    b:
+                        $ref: "#/definitions/u16"
+            arr:
+                type: array
+                minItems: 4
+                maxItems: 4
+                items:
+                    $ref: "#/definitions/u8"
diff --git a/tools/buildman/board.py b/tools/buildman/board.py
index 8ef905b8ce..248d8bfff1 100644
--- a/tools/buildman/board.py
+++ b/tools/buildman/board.py
@@ -17,14 +17,14 @@ class Board:
             vendor: Name of vendor (e.g. armltd)
             board_name: Name of board (e.g. integrator)
             target: Target name (use make <target>_defconfig to configure)
-            cfg_name: Config name
+            cfg_name: Config-file name (in includes/configs/)
         """
         self.target = target
         self.arch = arch
         self.cpu = cpu
-        self.board_name = board_name
-        self.vendor = vendor
         self.soc = soc
+        self.vendor = vendor
+        self.board_name = board_name
         self.cfg_name = cfg_name
         self.props = [self.target, self.arch, self.cpu, self.board_name,
                       self.vendor, self.soc, self.cfg_name]
diff --git a/tools/buildman/boards.py b/tools/buildman/boards.py
index 0bb0723b18..eef3f19f7a 100644
--- a/tools/buildman/boards.py
+++ b/tools/buildman/boards.py
@@ -50,7 +50,7 @@ def try_remove(fname):
             raise
 
 
-def output_is_new(output):
+def output_is_new(output, config_dir, srcdir):
     """Check if the output file is up to date.
 
     Looks at defconfig and Kconfig files to make sure none is newer than the
@@ -59,6 +59,8 @@ def output_is_new(output):
 
     Args:
         output (str): Filename to check
+        config_dir (str): Directory containing defconfig files
+        srcdir (str): Directory containing Kconfig and MAINTAINERS files
 
     Returns:
         True if the given output file exists and is newer than any of
@@ -76,7 +78,7 @@ def output_is_new(output):
             return False
         raise
 
-    for (dirpath, _, filenames) in os.walk(CONFIG_DIR):
+    for (dirpath, _, filenames) in os.walk(config_dir):
         for filename in fnmatch.filter(filenames, '*_defconfig'):
             if fnmatch.fnmatch(filename, '.*'):
                 continue
@@ -84,7 +86,7 @@ def output_is_new(output):
             if ctime < os.path.getctime(filepath):
                 return False
 
-    for (dirpath, _, filenames) in os.walk('.'):
+    for (dirpath, _, filenames) in os.walk(srcdir):
         for filename in filenames:
             if (fnmatch.fnmatch(filename, '*~') or
                 not fnmatch.fnmatch(filename, 'Kconfig*') and
@@ -103,7 +105,7 @@ def output_is_new(output):
             if line[0] == '#' or line == '\n':
                 continue
             defconfig = line.split()[6] + '_defconfig'
-            if not os.path.exists(os.path.join(CONFIG_DIR, defconfig)):
+            if not os.path.exists(os.path.join(config_dir, defconfig)):
                 return False
 
     return True
@@ -191,10 +193,10 @@ class KconfigScanner:
         # 'target' is added later
     }
 
-    def __init__(self):
+    def __init__(self, srctree):
         """Scan all the Kconfig files and create a Kconfig object."""
         # Define environment variables referenced from Kconfig
-        os.environ['srctree'] = os.getcwd()
+        os.environ['srctree'] = srctree
         os.environ['UBOOTVERSION'] = 'dummy'
         os.environ['KCONFIG_OBJDIR'] = ''
         self._tmpfile = None
@@ -211,40 +213,36 @@ class KconfigScanner:
         if self._tmpfile:
             try_remove(self._tmpfile)
 
-    def scan(self, defconfig):
+    def scan(self, defconfig, warn_targets):
         """Load a defconfig file to obtain board parameters.
 
         Args:
             defconfig (str): path to the defconfig file to be processed
+            warn_targets (bool): True to warn about missing or duplicate
+                CONFIG_TARGET options
 
         Returns:
-            A dictionary of board parameters.  It has a form of:
-            {
-                'arch': <arch_name>,
-                'cpu': <cpu_name>,
-                'soc': <soc_name>,
-                'vendor': <vendor_name>,
-                'board': <board_name>,
-                'target': <target_name>,
-                'config': <config_header_name>,
-            }
+            tuple: dictionary of board parameters.  It has a form of:
+                {
+                    'arch': <arch_name>,
+                    'cpu': <cpu_name>,
+                    'soc': <soc_name>,
+                    'vendor': <vendor_name>,
+                    'board': <board_name>,
+                    'target': <target_name>,
+                    'config': <config_header_name>,
+                }
+            warnings (list of str): list of warnings found
         """
-        # strip special prefixes and save it in a temporary file
-        outfd, self._tmpfile = tempfile.mkstemp()
-        with os.fdopen(outfd, 'w') as outf:
-            with open(defconfig, encoding='utf-8') as inf:
-                for line in inf:
-                    colon = line.find(':CONFIG_')
-                    if colon == -1:
-                        outf.write(line)
-                    else:
-                        outf.write(line[colon + 1:])
+        leaf = os.path.basename(defconfig)
+        expect_target, match, rear = leaf.partition('_defconfig')
+        assert match and not rear, f'{leaf} : invalid defconfig'
 
-        self._conf.load_config(self._tmpfile)
-        try_remove(self._tmpfile)
+        self._conf.load_config(defconfig)
         self._tmpfile = None
 
         params = {}
+        warnings = []
 
         # Get the value of CONFIG_SYS_ARCH, CONFIG_SYS_CPU, ... etc.
         # Set '-' if the value is empty.
@@ -255,9 +253,23 @@ class KconfigScanner:
             else:
                 params[key] = '-'
 
-        defconfig = os.path.basename(defconfig)
-        params['target'], match, rear = defconfig.partition('_defconfig')
-        assert match and not rear, f'{defconfig} : invalid defconfig'
+        # Check there is exactly one TARGET_xxx set
+        if warn_targets:
+            target = None
+            for name, sym in self._conf.syms.items():
+                if name.startswith('TARGET_') and sym.str_value == 'y':
+                    tname = name[7:].lower()
+                    if target:
+                        warnings.append(
+                            f'WARNING: {leaf}: Duplicate TARGET_xxx: {target} and {tname}')
+                    else:
+                        target = tname
+
+            if not target:
+                cfg_name = expect_target.replace('-', '_').upper()
+                warnings.append(f'WARNING: {leaf}: No TARGET_{cfg_name} enabled')
+
+        params['target'] = expect_target
 
         # fix-up for aarch64
         if params['arch'] == 'arm' and params['cpu'] == 'armv8':
@@ -274,7 +286,7 @@ class KconfigScanner:
             else:
                 params['arch'] = 'riscv64'
 
-        return params
+        return params, warnings
 
 
 class MaintainersDatabase:
@@ -332,26 +344,48 @@ class MaintainersDatabase:
             str: Maintainers of the board.  If the board has two or more
             maintainers, they are separated with colons.
         """
-        if not target in self.database:
-            self.warnings.append(f"WARNING: no maintainers for '{target}'")
-            return ''
+        entry = self.database.get(target)
+        if entry:
+            status, maint_list = entry
+            if not status.startswith('Orphan'):
+                if len(maint_list) > 1 or (maint_list and maint_list[0] != '-'):
+                    return ':'.join(maint_list)
 
-        return ':'.join(self.database[target][1])
+        self.warnings.append(f"WARNING: no maintainers for '{target}'")
+        return ''
 
-    def parse_file(self, fname):
+    def parse_file(self, srcdir, fname):
         """Parse a MAINTAINERS file.
 
         Parse a MAINTAINERS file and accumulate board status and maintainers
         information in the self.database dict.
 
+        defconfig files are used to specify the target, e.g. xxx_defconfig is
+        used for target 'xxx'. If there is no defconfig file mentioned in the
+        MAINTAINERS file F: entries, then this function does nothing.
+
+        The N: name entries can be used to specify a defconfig file using
+        wildcards.
+
         Args:
+            srcdir (str): Directory containing source code (Kconfig files)
             fname (str): MAINTAINERS file to be parsed
         """
+        def add_targets(linenum):
+            """Add any new targets
+
+            Args:
+                linenum (int): Current line number
+            """
+            if targets:
+                for target in targets:
+                    self.database[target] = (status, maintainers)
+
         targets = []
         maintainers = []
         status = '-'
         with open(fname, encoding="utf-8") as inf:
-            for line in inf:
+            for linenum, line in enumerate(inf):
                 # Check also commented maintainers
                 if line[:3] == '#M:':
                     line = line[1:]
@@ -360,9 +394,12 @@ class MaintainersDatabase:
                     maintainers.append(rest)
                 elif tag == 'F:':
                     # expand wildcard and filter by 'configs/*_defconfig'
-                    for item in glob.glob(rest):
+                    glob_path = os.path.join(srcdir, rest)
+                    for item in glob.glob(glob_path):
                         front, match, rear = item.partition('configs/')
-                        if not front and match:
+                        if front.endswith('/'):
+                            front = front[:-1]
+                        if front == srcdir and match:
                             front, match, rear = rear.rpartition('_defconfig')
                             if match and not rear:
                                 targets.append(front)
@@ -371,23 +408,26 @@ class MaintainersDatabase:
                 elif tag == 'N:':
                     # Just scan the configs directory since that's all we care
                     # about
-                    for dirpath, _, fnames in os.walk('configs'):
-                        for fname in fnames:
-                            path = os.path.join(dirpath, fname)
+                    walk_path = os.walk(os.path.join(srcdir, 'configs'))
+                    for dirpath, _, fnames in walk_path:
+                        for cfg in fnames:
+                            path = os.path.join(dirpath, cfg)[len(srcdir) + 1:]
                             front, match, rear = path.partition('configs/')
-                            if not front and match:
-                                front, match, rear = rear.rpartition('_defconfig')
-                                if match and not rear:
-                                    targets.append(front)
+                            if front or not match:
+                                continue
+                            front, match, rear = rear.rpartition('_defconfig')
+
+                            # Use this entry if it matches the defconfig file
+                            # without the _defconfig suffix. For example
+                            # 'am335x.*' matches am335x_guardian_defconfig
+                            if match and not rear and re.search(rest, front):
+                                targets.append(front)
                 elif line == '\n':
-                    for target in targets:
-                        self.database[target] = (status, maintainers)
+                    add_targets(linenum)
                     targets = []
                     maintainers = []
                     status = '-'
-        if targets:
-            for target in targets:
-                self.database[target] = (status, maintainers)
+        add_targets(linenum)
 
 
 class Boards:
@@ -622,39 +662,63 @@ class Boards:
         return result, warnings
 
     @classmethod
-    def scan_defconfigs_for_multiprocess(cls, queue, defconfigs):
+    def scan_defconfigs_for_multiprocess(cls, srcdir, queue, defconfigs,
+                                         warn_targets):
         """Scan defconfig files and queue their board parameters
 
         This function is intended to be passed to multiprocessing.Process()
         constructor.
 
         Args:
+            srcdir (str): Directory containing source code
             queue (multiprocessing.Queue): The resulting board parameters are
                 written into this.
             defconfigs (sequence of str): A sequence of defconfig files to be
                 scanned.
+            warn_targets (bool): True to warn about missing or duplicate
+                CONFIG_TARGET options
         """
-        kconf_scanner = KconfigScanner()
+        kconf_scanner = KconfigScanner(srcdir)
         for defconfig in defconfigs:
-            queue.put(kconf_scanner.scan(defconfig))
+            queue.put(kconf_scanner.scan(defconfig, warn_targets))
 
     @classmethod
-    def read_queues(cls, queues, params_list):
-        """Read the queues and append the data to the paramers list"""
+    def read_queues(cls, queues, params_list, warnings):
+        """Read the queues and append the data to the paramers list
+
+        Args:
+            queues (list of multiprocessing.Queue): Queues to read
+            params_list (list of dict): List to add params too
+            warnings (set of str): Set to add warnings to
+        """
         for que in queues:
             while not que.empty():
-                params_list.append(que.get())
+                params, warn = que.get()
+                params_list.append(params)
+                warnings.update(warn)
 
-    def scan_defconfigs(self, jobs=1):
+    def scan_defconfigs(self, config_dir, srcdir, jobs=1, warn_targets=False):
         """Collect board parameters for all defconfig files.
 
         This function invokes multiple processes for faster processing.
 
         Args:
+            config_dir (str): Directory containing the defconfig files
+            srcdir (str): Directory containing source code (Kconfig files)
             jobs (int): The number of jobs to run simultaneously
+            warn_targets (bool): True to warn about missing or duplicate
+                CONFIG_TARGET options
+
+        Returns:
+            tuple:
+                list of dict: List of board parameters, each a dict:
+                    key: 'arch', 'cpu', 'soc', 'vendor', 'board', 'target',
+                        'config'
+                    value: string value of the key
+                list of str: List of warnings recorded
         """
         all_defconfigs = []
-        for (dirpath, _, filenames) in os.walk(CONFIG_DIR):
+        for (dirpath, _, filenames) in os.walk(config_dir):
             for filename in fnmatch.filter(filenames, '*_defconfig'):
                 if fnmatch.fnmatch(filename, '.*'):
                     continue
@@ -669,18 +733,19 @@ class Boards:
             que = multiprocessing.Queue(maxsize=-1)
             proc = multiprocessing.Process(
                 target=self.scan_defconfigs_for_multiprocess,
-                args=(que, defconfigs))
+                args=(srcdir, que, defconfigs, warn_targets))
             proc.start()
             processes.append(proc)
             queues.append(que)
 
-        # The resulting data should be accumulated to this list
+        # The resulting data should be accumulated to these lists
         params_list = []
+        warnings = set()
 
         # Data in the queues should be retrieved preriodically.
         # Otherwise, the queues would become full and subprocesses would get stuck.
         while any(p.is_alive() for p in processes):
-            self.read_queues(queues, params_list)
+            self.read_queues(queues, params_list, warnings)
             # sleep for a while until the queues are filled
             time.sleep(SLEEP_TIME)
 
@@ -690,12 +755,12 @@ class Boards:
             proc.join()
 
         # retrieve leftover data
-        self.read_queues(queues, params_list)
+        self.read_queues(queues, params_list, warnings)
 
-        return params_list
+        return params_list, sorted(list(warnings))
 
     @classmethod
-    def insert_maintainers_info(cls, params_list):
+    def insert_maintainers_info(cls, srcdir, params_list):
         """Add Status and Maintainers information to the board parameters list.
 
         Args:
@@ -705,16 +770,21 @@ class Boards:
             list of str: List of warnings collected due to missing status, etc.
         """
         database = MaintainersDatabase()
-        for (dirpath, _, filenames) in os.walk('.'):
-            if 'MAINTAINERS' in filenames:
-                database.parse_file(os.path.join(dirpath, 'MAINTAINERS'))
+        for (dirpath, _, filenames) in os.walk(srcdir):
+            if 'MAINTAINERS' in filenames and 'tools/buildman' not in dirpath:
+                database.parse_file(srcdir,
+                                    os.path.join(dirpath, 'MAINTAINERS'))
 
         for i, params in enumerate(params_list):
             target = params['target']
-            params['status'] = database.get_status(target)
-            params['maintainers'] = database.get_maintainers(target)
+            maintainers = database.get_maintainers(target)
+            params['maintainers'] = maintainers
+            if maintainers:
+                params['status'] = database.get_status(target)
+            else:
+                params['status'] = '-'
             params_list[i] = params
-        return database.warnings
+        return sorted(database.warnings)
 
     @classmethod
     def format_and_output(cls, params_list, output):
@@ -750,9 +820,40 @@ class Boards:
         with open(output, 'w', encoding="utf-8") as outf:
             outf.write(COMMENT_BLOCK + '\n'.join(output_lines) + '\n')
 
+    def build_board_list(self, config_dir=CONFIG_DIR, srcdir='.', jobs=1,
+                         warn_targets=False):
+        """Generate a board-database file
+
+        This works by reading the Kconfig, then loading each board's defconfig
+        in to get the setting for each option. In particular, CONFIG_TARGET_xxx
+        is typically set by the defconfig, where xxx is the target to build.
+
+        Args:
+            config_dir (str): Directory containing the defconfig files
+            srcdir (str): Directory containing source code (Kconfig files)
+            jobs (int): The number of jobs to run simultaneously
+            warn_targets (bool): True to warn about missing or duplicate
+                CONFIG_TARGET options
+
+        Returns:
+            tuple:
+                list of dict: List of board parameters, each a dict:
+                    key: 'arch', 'cpu', 'soc', 'vendor', 'board', 'config',
+                         'target'
+                    value: string value of the key
+                list of str: Warnings that came up
+        """
+        params_list, warnings = self.scan_defconfigs(config_dir, srcdir, jobs,
+                                                     warn_targets)
+        m_warnings = self.insert_maintainers_info(srcdir, params_list)
+        return params_list, warnings + m_warnings
+
     def ensure_board_list(self, output, jobs=1, force=False, quiet=False):
         """Generate a board database file if needed.
 
+        This is intended to check if Kconfig has changed since the boards.cfg
+        files was generated.
+
         Args:
             output (str): The name of the output file
             jobs (int): The number of jobs to run simultaneously
@@ -762,12 +863,11 @@ class Boards:
         Returns:
             bool: True if all is well, False if there were warnings
         """
-        if not force and output_is_new(output):
+        if not force and output_is_new(output, CONFIG_DIR, '.'):
             if not quiet:
                 print(f'{output} is up to date. Nothing to do.')
             return True
-        params_list = self.scan_defconfigs(jobs)
-        warnings = self.insert_maintainers_info(params_list)
+        params_list, warnings = self.build_board_list(CONFIG_DIR, '.', jobs)
         for warn in warnings:
             print(warn, file=sys.stderr)
         self.format_and_output(params_list, output)
diff --git a/tools/buildman/bsettings.py b/tools/buildman/bsettings.py
index 0eb894a558..f7f8276e62 100644
--- a/tools/buildman/bsettings.py
+++ b/tools/buildman/bsettings.py
@@ -7,7 +7,7 @@ import io
 
 config_fname = None
 
-def Setup(fname=''):
+def setup(fname=''):
     """Set up the buildman settings module by reading config files
 
     Args:
@@ -23,15 +23,15 @@ def Setup(fname=''):
             config_fname = '%s/.buildman' % os.getenv('HOME')
         if not os.path.exists(config_fname):
             print('No config file found ~/.buildman\nCreating one...\n')
-            CreateBuildmanConfigFile(config_fname)
+            create_buildman_config_file(config_fname)
             print('To install tool chains, please use the --fetch-arch option')
         if config_fname:
             settings.read(config_fname)
 
-def AddFile(data):
+def add_file(data):
     settings.readfp(io.StringIO(data))
 
-def GetItems(section):
+def get_items(section):
     """Get the items from a section of the config.
 
     Args:
@@ -47,7 +47,7 @@ def GetItems(section):
     except:
         raise
 
-def GetGlobalItemValue(name):
+def get_global_item_value(name):
     """Get an item from the 'global' section of the config.
 
     Args:
@@ -58,7 +58,7 @@ def GetGlobalItemValue(name):
     """
     return settings.get('global', name, fallback=None)
 
-def SetItem(section, tag, value):
+def set_item(section, tag, value):
     """Set an item and write it back to the settings file"""
     global settings
     global config_fname
@@ -68,7 +68,7 @@ def SetItem(section, tag, value):
         with open(config_fname, 'w') as fd:
             settings.write(fd)
 
-def CreateBuildmanConfigFile(config_fname):
+def create_buildman_config_file(config_fname):
     """Creates a new config file with no tool chain information.
 
     Args:
@@ -91,7 +91,6 @@ other = /
 [toolchain-prefix]
 # name = path to prefix
 # e.g. x86 = /opt/gcc-4.6.3-nolibc/x86_64-linux/bin/x86_64-linux-
-# arc = /opt/arc/arc_gnu_2021.03_prebuilt_elf32_le_linux_install/bin/arc-elf32-
 
 [toolchain-alias]
 # arch = alias
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index d81752e994..ecbd368c47 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -134,7 +134,7 @@ class Config:
         for fname in config_filename:
             self.config[fname] = {}
 
-    def Add(self, fname, key, value):
+    def add(self, fname, key, value):
         self.config[fname][key] = value
 
     def __hash__(self):
@@ -151,7 +151,7 @@ class Environment:
         self.target = target
         self.environment = {}
 
-    def Add(self, key, value):
+    def add(self, key, value):
         self.environment[key] = value
 
 class Builder:
@@ -163,7 +163,8 @@ class Builder:
         checkout: True to check out source, False to skip that step.
             This is used for testing.
         col: terminal.Color() object
-        count: Number of commits to build
+        count: Total number of commits to build, which is the number of commits
+            multiplied by the number of boards
         do_make: Method to call to invoke Make
         fail: Number of builds that failed due to error
         force_build: Force building even if a build already exists
@@ -255,7 +256,10 @@ class Builder:
                  config_only=False, squash_config_y=False,
                  warnings_as_errors=False, work_in_output=False,
                  test_thread_exceptions=False, adjust_cfg=None,
-                 allow_missing=False, no_lto=False, reproducible_builds=False):
+                 allow_missing=False, no_lto=False, reproducible_builds=False,
+                 force_build=False, force_build_failures=False,
+                 force_reconfig=False, in_tree=False,
+                 force_config_on_failure=False, make_func=None):
         """Create a new Builder object
 
         Args:
@@ -295,7 +299,14 @@ class Builder:
                         a string Kconfig
             allow_missing: Run build with BINMAN_ALLOW_MISSING=1
             no_lto (bool): True to set the NO_LTO flag when building
-
+            force_build (bool): Rebuild even commits that are already built
+            force_build_failures (bool): Rebuild commits that have not been
+                built, or failed to build
+            force_reconfig (bool): Reconfigure on each commit
+            in_tree (bool): Bulid in tree instead of out-of-tree
+            force_config_on_failure (bool): Reconfigure the build before
+                retrying a failed build
+            make_func (function): Function to call to run 'make'
         """
         self.toolchains = toolchains
         self.base_dir = base_dir
@@ -304,7 +315,7 @@ class Builder:
         else:
             self._working_dir = os.path.join(base_dir, '.bm-work')
         self.threads = []
-        self.do_make = self.Make
+        self.do_make = make_func or self.make
         self.gnu_make = gnu_make
         self.checkout = checkout
         self.num_threads = num_threads
@@ -318,11 +329,7 @@ class Builder:
         self._complete_delay = None
         self._next_delay_update = datetime.now()
         self._start_time = datetime.now()
-        self.force_config_on_failure = True
-        self.force_build_failures = False
-        self.force_reconfig = False
         self._step = step
-        self.in_tree = False
         self._error_lines = 0
         self.no_subdirs = no_subdirs
         self.full_path = full_path
@@ -336,6 +343,11 @@ class Builder:
         self._ide = False
         self.no_lto = no_lto
         self.reproducible_builds = reproducible_builds
+        self.force_build = force_build
+        self.force_build_failures = force_build_failures
+        self.force_reconfig = force_reconfig
+        self.in_tree = in_tree
+        self.force_config_on_failure = force_config_on_failure
 
         if not self.squash_config_y:
             self.config_filenames += EXTRA_CONFIG_FILENAMES
@@ -389,7 +401,7 @@ class Builder:
     def signal_handler(self, signal, frame):
         sys.exit(1)
 
-    def SetDisplayOptions(self, show_errors=False, show_sizes=False,
+    def set_display_options(self, show_errors=False, show_sizes=False,
                           show_detail=False, show_bloat=False,
                           list_error_boards=False, show_config=False,
                           show_environment=False, filter_dtb_warnings=False,
@@ -422,7 +434,7 @@ class Builder:
         self._filter_migration_warnings = filter_migration_warnings
         self._ide = ide
 
-    def _AddTimestamp(self):
+    def _add_timestamp(self):
         """Add a new timestamp to the list and record the build period.
 
         The build period is the length of time taken to perform a single
@@ -451,14 +463,14 @@ class Builder:
             self._timestamps.popleft()
             count -= 1
 
-    def SelectCommit(self, commit, checkout=True):
+    def select_commit(self, commit, checkout=True):
         """Checkout the selected commit for this build
         """
         self.commit = commit
         if checkout and self.checkout:
             gitutil.checkout(commit.hash)
 
-    def Make(self, commit, brd, stage, cwd, *args, **kwargs):
+    def make(self, commit, brd, stage, cwd, *args, **kwargs):
         """Run make
 
         Args:
@@ -503,7 +515,7 @@ class Builder:
             result.combined = '%s\n' % (' '.join(cmd)) + result.combined
         return result
 
-    def ProcessResult(self, result):
+    def process_result(self, result):
         """Process the result of a build, showing progress information
 
         Args:
@@ -524,8 +536,8 @@ class Builder:
             if self._verbose:
                 terminal.print_clear()
                 boards_selected = {target : result.brd}
-                self.ResetResultSummary(boards_selected)
-                self.ProduceResultSummary(result.commit_upto, self.commits,
+                self.reset_result_summary(boards_selected)
+                self.produce_result_summary(result.commit_upto, self.commits,
                                           boards_selected)
         else:
             target = '(starting)'
@@ -544,7 +556,7 @@ class Builder:
             line += ' ' * 8
 
         # Add our current completion time estimate
-        self._AddTimestamp()
+        self._add_timestamp()
         if self._complete_delay:
             line += '%s  : ' % self._complete_delay
 
@@ -553,7 +565,7 @@ class Builder:
             terminal.print_clear()
             tprint(line, newline=False, limit_to_line=True)
 
-    def _GetOutputDir(self, commit_upto):
+    def get_output_dir(self, commit_upto):
         """Get the name of the output directory for a commit number
 
         The output directory is typically .../<branch>/<commit>.
@@ -568,7 +580,7 @@ class Builder:
         if self.commits:
             commit = self.commits[commit_upto]
             subject = commit.subject.translate(trans_valid_chars)
-            # See _GetOutputSpaceRemovals() which parses this name
+            # See _get_output_space_removals() which parses this name
             commit_dir = ('%02d_g%s_%s' % (commit_upto + 1,
                     commit.hash, subject[:20]))
         elif not self.no_subdirs:
@@ -577,7 +589,7 @@ class Builder:
             return self.base_dir
         return os.path.join(self.base_dir, commit_dir)
 
-    def GetBuildDir(self, commit_upto, target):
+    def get_build_dir(self, commit_upto, target):
         """Get the name of the build directory for a commit number
 
         The build directory is typically .../<branch>/<commit>/<target>.
@@ -586,30 +598,30 @@ class Builder:
             commit_upto: Commit number to use (0..self.count-1)
             target: Target name
         """
-        output_dir = self._GetOutputDir(commit_upto)
+        output_dir = self.get_output_dir(commit_upto)
         if self.work_in_output:
             return output_dir
         return os.path.join(output_dir, target)
 
-    def GetDoneFile(self, commit_upto, target):
+    def get_done_file(self, commit_upto, target):
         """Get the name of the done file for a commit number
 
         Args:
             commit_upto: Commit number to use (0..self.count-1)
             target: Target name
         """
-        return os.path.join(self.GetBuildDir(commit_upto, target), 'done')
+        return os.path.join(self.get_build_dir(commit_upto, target), 'done')
 
-    def GetSizesFile(self, commit_upto, target):
+    def get_sizes_file(self, commit_upto, target):
         """Get the name of the sizes file for a commit number
 
         Args:
             commit_upto: Commit number to use (0..self.count-1)
             target: Target name
         """
-        return os.path.join(self.GetBuildDir(commit_upto, target), 'sizes')
+        return os.path.join(self.get_build_dir(commit_upto, target), 'sizes')
 
-    def GetFuncSizesFile(self, commit_upto, target, elf_fname):
+    def get_func_sizes_file(self, commit_upto, target, elf_fname):
         """Get the name of the funcsizes file for a commit number and ELF file
 
         Args:
@@ -617,10 +629,10 @@ class Builder:
             target: Target name
             elf_fname: Filename of elf image
         """
-        return os.path.join(self.GetBuildDir(commit_upto, target),
+        return os.path.join(self.get_build_dir(commit_upto, target),
                             '%s.sizes' % elf_fname.replace('/', '-'))
 
-    def GetObjdumpFile(self, commit_upto, target, elf_fname):
+    def get_objdump_file(self, commit_upto, target, elf_fname):
         """Get the name of the objdump file for a commit number and ELF file
 
         Args:
@@ -628,20 +640,20 @@ class Builder:
             target: Target name
             elf_fname: Filename of elf image
         """
-        return os.path.join(self.GetBuildDir(commit_upto, target),
+        return os.path.join(self.get_build_dir(commit_upto, target),
                             '%s.objdump' % elf_fname.replace('/', '-'))
 
-    def GetErrFile(self, commit_upto, target):
+    def get_err_file(self, commit_upto, target):
         """Get the name of the err file for a commit number
 
         Args:
             commit_upto: Commit number to use (0..self.count-1)
             target: Target name
         """
-        output_dir = self.GetBuildDir(commit_upto, target)
+        output_dir = self.get_build_dir(commit_upto, target)
         return os.path.join(output_dir, 'err')
 
-    def FilterErrors(self, lines):
+    def filter_errors(self, lines):
         """Filter out errors in which we have no interest
 
         We should probably use map().
@@ -664,7 +676,7 @@ class Builder:
             out_lines.append(line)
         return out_lines
 
-    def ReadFuncSizes(self, fname, fd):
+    def read_func_sizes(self, fname, fd):
         """Read function sizes from the output of 'nm'
 
         Args:
@@ -688,7 +700,7 @@ class Builder:
                         sym[name] = sym.get(name, 0) + int(size, 16)
         return sym
 
-    def _ProcessConfig(self, fname):
+    def _process_config(self, fname):
         """Read in a .config, autoconf.mk or autoconf.h file
 
         This function handles all config file types. It ignores comments and
@@ -725,7 +737,7 @@ class Builder:
                     config[key] = value
         return config
 
-    def _ProcessEnvironment(self, fname):
+    def _process_environment(self, fname):
         """Read in a uboot.env file
 
         This function reads in environment variables from a file.
@@ -750,7 +762,7 @@ class Builder:
                         pass
         return environment
 
-    def GetBuildOutcome(self, commit_upto, target, read_func_sizes,
+    def get_build_outcome(self, commit_upto, target, read_func_sizes,
                         read_config, read_environment):
         """Work out the outcome of a build.
 
@@ -764,8 +776,8 @@ class Builder:
         Returns:
             Outcome object
         """
-        done_file = self.GetDoneFile(commit_upto, target)
-        sizes_file = self.GetSizesFile(commit_upto, target)
+        done_file = self.get_done_file(commit_upto, target)
+        sizes_file = self.get_sizes_file(commit_upto, target)
         sizes = {}
         func_sizes = {}
         config = {}
@@ -779,10 +791,10 @@ class Builder:
                     # Try a rebuild
                     return_code = 1
                 err_lines = []
-                err_file = self.GetErrFile(commit_upto, target)
+                err_file = self.get_err_file(commit_upto, target)
                 if os.path.exists(err_file):
                     with open(err_file, 'r') as fd:
-                        err_lines = self.FilterErrors(fd.readlines())
+                        err_lines = self.filter_errors(fd.readlines())
 
                 # Decide whether the build was ok, failed or created warnings
                 if return_code:
@@ -811,30 +823,30 @@ class Builder:
                             sizes[values[5]] = size_dict
 
             if read_func_sizes:
-                pattern = self.GetFuncSizesFile(commit_upto, target, '*')
+                pattern = self.get_func_sizes_file(commit_upto, target, '*')
                 for fname in glob.glob(pattern):
                     with open(fname, 'r') as fd:
                         dict_name = os.path.basename(fname).replace('.sizes',
                                                                     '')
-                        func_sizes[dict_name] = self.ReadFuncSizes(fname, fd)
+                        func_sizes[dict_name] = self.read_func_sizes(fname, fd)
 
             if read_config:
-                output_dir = self.GetBuildDir(commit_upto, target)
+                output_dir = self.get_build_dir(commit_upto, target)
                 for name in self.config_filenames:
                     fname = os.path.join(output_dir, name)
-                    config[name] = self._ProcessConfig(fname)
+                    config[name] = self._process_config(fname)
 
             if read_environment:
-                output_dir = self.GetBuildDir(commit_upto, target)
+                output_dir = self.get_build_dir(commit_upto, target)
                 fname = os.path.join(output_dir, 'uboot.env')
-                environment = self._ProcessEnvironment(fname)
+                environment = self._process_environment(fname)
 
             return Builder.Outcome(rc, err_lines, sizes, func_sizes, config,
                                    environment)
 
         return Builder.Outcome(OUTCOME_UNKNOWN, [], {}, {}, {}, {})
 
-    def GetResultSummary(self, boards_selected, commit_upto, read_func_sizes,
+    def get_result_summary(self, boards_selected, commit_upto, read_func_sizes,
                          read_config, read_environment):
         """Calculate a summary of the results of building a commit.
 
@@ -865,7 +877,7 @@ class Builder:
                     key: environment variable
                     value: value of environment variable
         """
-        def AddLine(lines_summary, lines_boards, line, board):
+        def add_line(lines_summary, lines_boards, line, board):
             line = line.rstrip()
             if line in lines_boards:
                 lines_boards[line].append(board)
@@ -882,7 +894,7 @@ class Builder:
         environment = {}
 
         for brd in boards_selected.values():
-            outcome = self.GetBuildOutcome(commit_upto, brd.target,
+            outcome = self.get_build_outcome(commit_upto, brd.target,
                                            read_func_sizes, read_config,
                                            read_environment)
             board_dict[brd.target] = outcome
@@ -899,15 +911,15 @@ class Builder:
                         is_note = self._re_note.match(line)
                         if is_warning or (last_was_warning and is_note):
                             if last_func:
-                                AddLine(warn_lines_summary, warn_lines_boards,
+                                add_line(warn_lines_summary, warn_lines_boards,
                                         last_func, brd)
-                            AddLine(warn_lines_summary, warn_lines_boards,
+                            add_line(warn_lines_summary, warn_lines_boards,
                                     line, brd)
                         else:
                             if last_func:
-                                AddLine(err_lines_summary, err_lines_boards,
+                                add_line(err_lines_summary, err_lines_boards,
                                         last_func, brd)
-                            AddLine(err_lines_summary, err_lines_boards,
+                            add_line(err_lines_summary, err_lines_boards,
                                     line, brd)
                         last_was_warning = is_warning
                         last_func = None
@@ -915,19 +927,19 @@ class Builder:
             for fname in self.config_filenames:
                 if outcome.config:
                     for key, value in outcome.config[fname].items():
-                        tconfig.Add(fname, key, value)
+                        tconfig.add(fname, key, value)
             config[brd.target] = tconfig
 
             tenvironment = Environment(brd.target)
             if outcome.environment:
                 for key, value in outcome.environment.items():
-                    tenvironment.Add(key, value)
+                    tenvironment.add(key, value)
             environment[brd.target] = tenvironment
 
         return (board_dict, err_lines_summary, err_lines_boards,
                 warn_lines_summary, warn_lines_boards, config, environment)
 
-    def AddOutcome(self, board_dict, arch_list, changes, char, color):
+    def add_outcome(self, board_dict, arch_list, changes, char, color):
         """Add an output to our list of outcomes for each architecture
 
         This simple function adds failing boards (changes) to the
@@ -957,19 +969,19 @@ class Builder:
                 arch_list[arch] += str
 
 
-    def ColourNum(self, num):
+    def colour_num(self, num):
         color = self.col.RED if num > 0 else self.col.GREEN
         if num == 0:
             return '0'
         return self.col.build(color, str(num))
 
-    def ResetResultSummary(self, board_selected):
+    def reset_result_summary(self, board_selected):
         """Reset the results summary ready for use.
 
         Set up the base board list to be all those selected, and set the
         error lines to empty.
 
-        Following this, calls to PrintResultSummary() will use this
+        Following this, calls to print_result_summary() will use this
         information to work out what has changed.
 
         Args:
@@ -986,7 +998,7 @@ class Builder:
         self._base_config = None
         self._base_environment = None
 
-    def PrintFuncSizeDetail(self, fname, old, new):
+    def print_func_size_detail(self, fname, old, new):
         grow, shrink, add, remove, up, down = 0, 0, 0, 0, 0, 0
         delta, common = [], {}
 
@@ -1020,7 +1032,7 @@ class Builder:
         args = [add, -remove, grow, -shrink, up, -down, up - down]
         if max(args) == 0 and min(args) == 0:
             return
-        args = [self.ColourNum(x) for x in args]
+        args = [self.colour_num(x) for x in args]
         indent = ' ' * 15
         tprint('%s%s: add: %s/%s, grow: %s/%s bytes: %s/%s (%s)' %
               tuple([indent, self.col.build(self.col.YELLOW, fname)] + args))
@@ -1034,7 +1046,7 @@ class Builder:
                 tprint(msg, colour=color)
 
 
-    def PrintSizeDetail(self, target_list, show_bloat):
+    def print_size_detail(self, target_list, show_bloat):
         """Show details size information for each board
 
         Args:
@@ -1067,12 +1079,12 @@ class Builder:
                     outcome = result['_outcome']
                     base_outcome = self._base_board_dict[target]
                     for fname in outcome.func_sizes:
-                        self.PrintFuncSizeDetail(fname,
+                        self.print_func_size_detail(fname,
                                                  base_outcome.func_sizes[fname],
                                                  outcome.func_sizes[fname])
 
 
-    def PrintSizeSummary(self, board_selected, board_dict, show_detail,
+    def print_size_summary(self, board_selected, board_dict, show_detail,
                          show_bloat):
         """Print a summary of image sizes broken down by section.
 
@@ -1173,10 +1185,10 @@ class Builder:
             if printed_arch:
                 tprint()
                 if show_detail:
-                    self.PrintSizeDetail(target_list, show_bloat)
+                    self.print_size_detail(target_list, show_bloat)
 
 
-    def PrintResultSummary(self, board_selected, board_dict, err_lines,
+    def print_result_summary(self, board_selected, board_dict, err_lines,
                            err_line_boards, warn_lines, warn_line_boards,
                            config, environment, show_sizes, show_detail,
                            show_bloat, show_config, show_environment):
@@ -1212,7 +1224,7 @@ class Builder:
             show_config: Show config changes
             show_environment: Show environment changes
         """
-        def _BoardList(line, line_boards):
+        def _board_list(line, line_boards):
             """Helper function to get a line of boards containing a line
 
             Args:
@@ -1231,7 +1243,7 @@ class Builder:
                         board_set.add(brd)
             return brds
 
-        def _CalcErrorDelta(base_lines, base_line_boards, lines, line_boards,
+        def _calc_error_delta(base_lines, base_line_boards, lines, line_boards,
                             char):
             """Calculate the required output based on changes in errors
 
@@ -1255,17 +1267,17 @@ class Builder:
             worse_lines = []
             for line in lines:
                 if line not in base_lines:
-                    errline = ErrLine(char + '+', _BoardList(line, line_boards),
+                    errline = ErrLine(char + '+', _board_list(line, line_boards),
                                       line)
                     worse_lines.append(errline)
             for line in base_lines:
                 if line not in lines:
                     errline = ErrLine(char + '-',
-                                      _BoardList(line, base_line_boards), line)
+                                      _board_list(line, base_line_boards), line)
                     better_lines.append(errline)
             return better_lines, worse_lines
 
-        def _CalcConfig(delta, name, config):
+        def _calc_config(delta, name, config):
             """Calculate configuration changes
 
             Args:
@@ -1283,7 +1295,7 @@ class Builder:
                 out += '%s=%s ' % (key, config[key])
             return '%s %s: %s' % (delta, name, out)
 
-        def _AddConfig(lines, name, config_plus, config_minus, config_change):
+        def _add_config(lines, name, config_plus, config_minus, config_change):
             """Add changes in configuration to a list
 
             Args:
@@ -1300,13 +1312,13 @@ class Builder:
                     value: config value
             """
             if config_plus:
-                lines.append(_CalcConfig('+', name, config_plus))
+                lines.append(_calc_config('+', name, config_plus))
             if config_minus:
-                lines.append(_CalcConfig('-', name, config_minus))
+                lines.append(_calc_config('-', name, config_minus))
             if config_change:
-                lines.append(_CalcConfig('c', name, config_change))
+                lines.append(_calc_config('c', name, config_change))
 
-        def _OutputConfigInfo(lines):
+        def _output_config_info(lines):
             for line in lines:
                 if not line:
                     continue
@@ -1318,7 +1330,7 @@ class Builder:
                     col = self.col.YELLOW
                 tprint('   ' + line, newline=True, colour=col)
 
-        def _OutputErrLines(err_lines, colour):
+        def _output_err_lines(err_lines, colour):
             """Output the line of error/warning lines, if not empty
 
             Also increments self._error_lines if err_lines not empty
@@ -1376,9 +1388,9 @@ class Builder:
                 new_boards.append(target)
 
         # Get a list of errors and warnings that have appeared, and disappeared
-        better_err, worse_err = _CalcErrorDelta(self._base_err_lines,
+        better_err, worse_err = _calc_error_delta(self._base_err_lines,
                 self._base_err_line_boards, err_lines, err_line_boards, '')
-        better_warn, worse_warn = _CalcErrorDelta(self._base_warn_lines,
+        better_warn, worse_warn = _calc_error_delta(self._base_warn_lines,
                 self._base_warn_line_boards, warn_lines, warn_line_boards, 'w')
 
         # For the IDE mode, print out all the output
@@ -1391,26 +1403,26 @@ class Builder:
         elif any((ok_boards, warn_boards, err_boards, unknown_boards, new_boards,
                 worse_err, better_err, worse_warn, better_warn)):
             arch_list = {}
-            self.AddOutcome(board_selected, arch_list, ok_boards, '',
+            self.add_outcome(board_selected, arch_list, ok_boards, '',
                     self.col.GREEN)
-            self.AddOutcome(board_selected, arch_list, warn_boards, 'w+',
+            self.add_outcome(board_selected, arch_list, warn_boards, 'w+',
                     self.col.YELLOW)
-            self.AddOutcome(board_selected, arch_list, err_boards, '+',
+            self.add_outcome(board_selected, arch_list, err_boards, '+',
                     self.col.RED)
-            self.AddOutcome(board_selected, arch_list, new_boards, '*', self.col.BLUE)
+            self.add_outcome(board_selected, arch_list, new_boards, '*', self.col.BLUE)
             if self._show_unknown:
-                self.AddOutcome(board_selected, arch_list, unknown_boards, '?',
+                self.add_outcome(board_selected, arch_list, unknown_boards, '?',
                         self.col.MAGENTA)
             for arch, target_list in arch_list.items():
                 tprint('%10s: %s' % (arch, target_list))
                 self._error_lines += 1
-            _OutputErrLines(better_err, colour=self.col.GREEN)
-            _OutputErrLines(worse_err, colour=self.col.RED)
-            _OutputErrLines(better_warn, colour=self.col.CYAN)
-            _OutputErrLines(worse_warn, colour=self.col.YELLOW)
+            _output_err_lines(better_err, colour=self.col.GREEN)
+            _output_err_lines(worse_err, colour=self.col.RED)
+            _output_err_lines(better_warn, colour=self.col.CYAN)
+            _output_err_lines(worse_warn, colour=self.col.YELLOW)
 
         if show_sizes:
-            self.PrintSizeSummary(board_selected, board_dict, show_detail,
+            self.print_size_summary(board_selected, board_dict, show_detail,
                                   show_bloat)
 
         if show_environment and self._base_environment:
@@ -1438,10 +1450,10 @@ class Builder:
                         desc = '%s -> %s' % (value, new_value)
                         environment_change[key] = desc
 
-                _AddConfig(lines, target, environment_plus, environment_minus,
+                _add_config(lines, target, environment_plus, environment_minus,
                            environment_change)
 
-            _OutputConfigInfo(lines)
+            _output_config_info(lines)
 
         if show_config and self._base_config:
             summary = {}
@@ -1504,9 +1516,9 @@ class Builder:
                     arch_config_minus[arch][name].update(config_minus)
                     arch_config_change[arch][name].update(config_change)
 
-                    _AddConfig(lines, name, config_plus, config_minus,
+                    _add_config(lines, name, config_plus, config_minus,
                                config_change)
-                _AddConfig(lines, 'all', all_config_plus, all_config_minus,
+                _add_config(lines, 'all', all_config_plus, all_config_minus,
                            all_config_change)
                 summary[target] = '\n'.join(lines)
 
@@ -1526,20 +1538,20 @@ class Builder:
                     all_plus.update(arch_config_plus[arch][name])
                     all_minus.update(arch_config_minus[arch][name])
                     all_change.update(arch_config_change[arch][name])
-                    _AddConfig(lines, name, arch_config_plus[arch][name],
+                    _add_config(lines, name, arch_config_plus[arch][name],
                                arch_config_minus[arch][name],
                                arch_config_change[arch][name])
-                _AddConfig(lines, 'all', all_plus, all_minus, all_change)
+                _add_config(lines, 'all', all_plus, all_minus, all_change)
                 #arch_summary[target] = '\n'.join(lines)
                 if lines:
                     tprint('%s:' % arch)
-                    _OutputConfigInfo(lines)
+                    _output_config_info(lines)
 
             for lines, targets in lines_by_target.items():
                 if not lines:
                     continue
                 tprint('%s :' % ' '.join(sorted(targets)))
-                _OutputConfigInfo(lines.split('\n'))
+                _output_config_info(lines.split('\n'))
 
 
         # Save our updated information for the next call to this function
@@ -1560,9 +1572,9 @@ class Builder:
             tprint("Boards not built (%d): %s" % (len(not_built),
                   ', '.join(not_built)))
 
-    def ProduceResultSummary(self, commit_upto, commits, board_selected):
+    def produce_result_summary(self, commit_upto, commits, board_selected):
             (board_dict, err_lines, err_line_boards, warn_lines,
-             warn_line_boards, config, environment) = self.GetResultSummary(
+             warn_line_boards, config, environment) = self.get_result_summary(
                     board_selected, commit_upto,
                     read_func_sizes=self._show_bloat,
                     read_config=self._show_config,
@@ -1571,13 +1583,13 @@ class Builder:
                 msg = '%02d: %s' % (commit_upto + 1,
                         commits[commit_upto].subject)
                 tprint(msg, colour=self.col.BLUE)
-            self.PrintResultSummary(board_selected, board_dict,
+            self.print_result_summary(board_selected, board_dict,
                     err_lines if self._show_errors else [], err_line_boards,
                     warn_lines if self._show_errors else [], warn_line_boards,
                     config, environment, self._show_sizes, self._show_detail,
                     self._show_bloat, self._show_config, self._show_environment)
 
-    def ShowSummary(self, commits, board_selected):
+    def show_summary(self, commits, board_selected):
         """Show a build summary for U-Boot for a given board list.
 
         Reset the result summary, then repeatedly call GetResultSummary on
@@ -1589,16 +1601,16 @@ class Builder:
         """
         self.commit_count = len(commits) if commits else 1
         self.commits = commits
-        self.ResetResultSummary(board_selected)
+        self.reset_result_summary(board_selected)
         self._error_lines = 0
 
         for commit_upto in range(0, self.commit_count, self._step):
-            self.ProduceResultSummary(commit_upto, commits, board_selected)
+            self.produce_result_summary(commit_upto, commits, board_selected)
         if not self._error_lines:
             tprint('(no errors to report)', colour=self.col.GREEN)
 
 
-    def SetupBuild(self, board_selected, commits):
+    def setup_build(self, board_selected, commits):
         """Set up ready to start a build.
 
         Args:
@@ -1611,7 +1623,7 @@ class Builder:
         self.upto = self.warned = self.fail = 0
         self._timestamps = collections.deque()
 
-    def GetThreadDir(self, thread_num):
+    def get_thread_dir(self, thread_num):
         """Get the directory path to the working dir for a thread.
 
         Args:
@@ -1622,7 +1634,7 @@ class Builder:
             return self._working_dir
         return os.path.join(self._working_dir, '%02d' % max(thread_num, 0))
 
-    def _PrepareThread(self, thread_num, setup_git):
+    def _prepare_thread(self, thread_num, setup_git):
         """Prepare the working directory for a thread.
 
         This clones or fetches the repo into the thread's work directory.
@@ -1635,8 +1647,8 @@ class Builder:
                'clone' to set up a git clone
                'worktree' to set up a git worktree
         """
-        thread_dir = self.GetThreadDir(thread_num)
-        builderthread.Mkdir(thread_dir)
+        thread_dir = self.get_thread_dir(thread_num)
+        builderthread.mkdir(thread_dir)
         git_dir = os.path.join(thread_dir, '.git')
 
         # Create a worktree or a git repo clone for this thread if it
@@ -1672,7 +1684,7 @@ class Builder:
             else:
                 raise ValueError("Can't setup git repo with %s." % setup_git)
 
-    def _PrepareWorkingSpace(self, max_threads, setup_git):
+    def _prepare_working_space(self, max_threads, setup_git):
         """Prepare the working directory for use.
 
         Set up the git repo for each thread. Creates a linked working tree
@@ -1684,7 +1696,7 @@ class Builder:
                 work
             setup_git: True to set up a git worktree or a git clone
         """
-        builderthread.Mkdir(self._working_dir)
+        builderthread.mkdir(self._working_dir)
         if setup_git and self.git_dir:
             src_dir = os.path.abspath(self.git_dir)
             if gitutil.check_worktree_is_available(src_dir):
@@ -1698,14 +1710,14 @@ class Builder:
 
         # Always do at least one thread
         for thread in range(max(max_threads, 1)):
-            self._PrepareThread(thread, setup_git)
+            self._prepare_thread(thread, setup_git)
 
-    def _GetOutputSpaceRemovals(self):
+    def _get_output_space_removals(self):
         """Get the output directories ready to receive files.
 
         Figure out what needs to be deleted in the output directory before it
         can be used. We only delete old buildman directories which have the
-        expected name pattern. See _GetOutputDir().
+        expected name pattern. See get_output_dir().
 
         Returns:
             List of full paths of directories to remove
@@ -1714,7 +1726,7 @@ class Builder:
             return
         dir_list = []
         for commit_upto in range(self.commit_count):
-            dir_list.append(self._GetOutputDir(commit_upto))
+            dir_list.append(self.get_output_dir(commit_upto))
 
         to_remove = []
         for dirname in glob.glob(os.path.join(self.base_dir, '*')):
@@ -1725,14 +1737,14 @@ class Builder:
                     to_remove.append(dirname)
         return to_remove
 
-    def _PrepareOutputSpace(self):
+    def _prepare_output_space(self):
         """Get the output directories ready to receive files.
 
         We delete any output directories which look like ones we need to
         create. Having left over directories is confusing when the user wants
         to check the output manually.
         """
-        to_remove = self._GetOutputSpaceRemovals()
+        to_remove = self._get_output_space_removals()
         if to_remove:
             tprint('Removing %d old build directories...' % len(to_remove),
                   newline=False)
@@ -1740,7 +1752,7 @@ class Builder:
                 shutil.rmtree(dirname)
             terminal.print_clear()
 
-    def BuildBoards(self, commits, board_selected, keep_outputs, verbose):
+    def build_boards(self, commits, board_selected, keep_outputs, verbose):
         """Build all commits for a list of boards
 
         Args:
@@ -1759,15 +1771,15 @@ class Builder:
         self.commits = commits
         self._verbose = verbose
 
-        self.ResetResultSummary(board_selected)
-        builderthread.Mkdir(self.base_dir, parents = True)
-        self._PrepareWorkingSpace(min(self.num_threads, len(board_selected)),
+        self.reset_result_summary(board_selected)
+        builderthread.mkdir(self.base_dir, parents = True)
+        self._prepare_working_space(min(self.num_threads, len(board_selected)),
                 commits is not None)
-        self._PrepareOutputSpace()
+        self._prepare_output_space()
         if not self._ide:
             tprint('\rStarting build...', newline=False)
-        self.SetupBuild(board_selected, commits)
-        self.ProcessResult(None)
+        self.setup_build(board_selected, commits)
+        self.process_result(None)
         self.thread_exceptions = []
         # Create jobs to build all commits for each board
         for brd in board_selected.values():
@@ -1781,7 +1793,7 @@ class Builder:
             if self.num_threads:
                 self.queue.put(job)
             else:
-                self._single_builder.RunJob(job)
+                self._single_builder.run_job(job)
 
         if self.num_threads:
             term = threading.Thread(target=self.queue.join)
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index 635865c21c..25f460c207 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -2,8 +2,15 @@
 # Copyright (c) 2014 Google, Inc
 #
 
+"""Implementation the bulider threads
+
+This module provides the BuilderThread class, which handles calling the builder
+based on the jobs provided.
+"""
+
 import errno
 import glob
+import io
 import os
 import shutil
 import sys
@@ -16,11 +23,15 @@ from u_boot_pylib import command
 RETURN_CODE_RETRY = -1
 BASE_ELF_FILENAMES = ['u-boot', 'spl/u-boot-spl', 'tpl/u-boot-tpl']
 
-def Mkdir(dirname, parents = False):
+def mkdir(dirname, parents=False):
     """Make a directory if it doesn't already exist.
 
     Args:
-        dirname: Directory to create
+        dirname (str): Directory to create
+        parents (bool): True to also make parent directories
+
+    Raises:
+        OSError: File already exists
     """
     try:
         if parents:
@@ -30,12 +41,51 @@ def Mkdir(dirname, parents = False):
     except OSError as err:
         if err.errno == errno.EEXIST:
             if os.path.realpath('.') == os.path.realpath(dirname):
-                print("Cannot create the current working directory '%s'!" % dirname)
+                print(f"Cannot create the current working directory '{dirname}'!")
                 sys.exit(1)
-            pass
         else:
             raise
 
+
+def _remove_old_outputs(out_dir):
+    """Remove any old output-target files
+
+    Args:
+        out_dir (str): Output directory for the build
+
+    Since we use a build directory that was previously used by another
+    board, it may have produced an SPL image. If we don't remove it (i.e.
+    see do_config and self.mrproper below) then it will appear to be the
+    output of this build, even if it does not produce SPL images.
+    """
+    for elf in BASE_ELF_FILENAMES:
+        fname = os.path.join(out_dir, elf)
+        if os.path.exists(fname):
+            os.remove(fname)
+
+
+def copy_files(out_dir, build_dir, dirname, patterns):
+    """Copy files from the build directory to the output.
+
+    Args:
+        out_dir (str): Path to output directory containing the files
+        build_dir (str): Place to copy the files
+        dirname (str): Source directory, '' for normal U-Boot, 'spl' for SPL
+        patterns (list of str): A list of filenames to copy, each relative
+           to the build directory
+    """
+    for pattern in patterns:
+        file_list = glob.glob(os.path.join(out_dir, dirname, pattern))
+        for fname in file_list:
+            target = os.path.basename(fname)
+            if dirname:
+                base, ext = os.path.splitext(target)
+                if ext:
+                    target = f'{base}-{dirname}{ext}'
+            shutil.copy(fname, os.path.join(build_dir, target))
+
+
+# pylint: disable=R0903
 class BuilderJob:
     """Holds information about a job to be performed by a thread
 
@@ -77,7 +127,7 @@ class ResultThread(threading.Thread):
         """
         while True:
             result = self.builder.out_queue.get()
-            self.builder.ProcessResult(result)
+            self.builder.process_result(result)
             self.builder.out_queue.task_done()
 
 
@@ -107,22 +157,25 @@ class BuilderThread(threading.Thread):
         self.mrproper = mrproper
         self.per_board_out_dir = per_board_out_dir
         self.test_exception = test_exception
+        self.toolchain = None
 
-    def Make(self, commit, brd, stage, cwd, *args, **kwargs):
+    def make(self, commit, brd, stage, cwd, *args, **kwargs):
         """Run 'make' on a particular commit and board.
 
         The source code will already be checked out, so the 'commit'
         argument is only for information.
 
         Args:
-            commit: Commit object that is being built
-            brd: Board object that is being built
-            stage: Stage of the build. Valid stages are:
+            commit (Commit): Commit that is being built
+            brd (Board): Board that is being built
+            stage (str): Stage of the build. Valid stages are:
                         mrproper - can be called to clean source
                         config - called to configure for a board
                         build - the main make invocation - it does the build
-            args: A list of arguments to pass to 'make'
-            kwargs: A list of keyword arguments to pass to command.run_pipe()
+            cwd (str): Working directory to set, or None to leave it alone
+            *args (list of str): Arguments to pass to 'make'
+            **kwargs (dict): A list of keyword arguments to pass to
+                command.run_pipe()
 
         Returns:
             CommandResult object
@@ -130,61 +183,140 @@ class BuilderThread(threading.Thread):
         return self.builder.do_make(commit, brd, stage, cwd, *args,
                 **kwargs)
 
-    def RunCommit(self, commit_upto, brd, work_dir, do_config, config_only,
-                  force_build, force_build_failures, work_in_output,
-                  adjust_cfg):
-        """Build a particular commit.
-
-        If the build is already done, and we are not forcing a build, we skip
-        the build and just return the previously-saved results.
+    def _build_args(self, brd, out_dir, out_rel_dir, work_dir, commit_upto):
+        """Set up arguments to the args list based on the settings
 
         Args:
-            commit_upto: Commit number to build (0...n-1)
-            brd: Board object to build
-            work_dir: Directory to which the source will be checked out
-            do_config: True to run a make <board>_defconfig on the source
-            config_only: Only configure the source, do not build it
-            force_build: Force a build even if one was previously done
-            force_build_failures: Force a bulid if the previous result showed
-                failure
-            work_in_output: Use the output directory as the work directory and
-                don't write to a separate output directory.
-            adjust_cfg (list of str): List of changes to make to .config file
-                before building. Each is one of (where C is either CONFIG_xxx
-                or just xxx):
-                     C to enable C
-                     ~C to disable C
-                     C=val to set the value of C (val must have quotes if C is
-                         a string Kconfig
+            brd (Board): Board to create arguments for
+            out_dir (str): Path to output directory containing the files
+            out_rel_dir (str): Output directory relative to the current dir
+            work_dir (str): Directory to which the source will be checked out
+            commit_upto (int): Commit number to build (0...n-1)
 
         Returns:
-            tuple containing:
-                - CommandResult object containing the results of the build
-                - boolean indicating whether 'make config' is still needed
+            tuple:
+                list of str: Arguments to pass to make
+                str: Current working directory, or None if no commit
+                str: Source directory (typically the work directory)
         """
-        # Create a default result - it will be overwritte by the call to
-        # self.Make() below, in the event that we do a build.
-        result = command.CommandResult()
-        result.return_code = 0
-        if work_in_output or self.builder.in_tree:
-            out_dir = work_dir
-        else:
-            if self.per_board_out_dir:
-                out_rel_dir = os.path.join('..', brd.target)
+        args = []
+        cwd = work_dir
+        src_dir = os.path.realpath(work_dir)
+        if not self.builder.in_tree:
+            if commit_upto is None:
+                # In this case we are building in the original source directory
+                # (i.e. the current directory where buildman is invoked. The
+                # output directory is set to this thread's selected work
+                # directory.
+                #
+                # Symlinks can confuse U-Boot's Makefile since we may use '..'
+                # in our path, so remove them.
+                real_dir = os.path.realpath(out_dir)
+                args.append(f'O={real_dir}')
+                cwd = None
+                src_dir = os.getcwd()
             else:
-                out_rel_dir = 'build'
-            out_dir = os.path.join(work_dir, out_rel_dir)
+                args.append(f'O={out_rel_dir}')
+        if self.builder.verbose_build:
+            args.append('V=1')
+        else:
+            args.append('-s')
+        if self.builder.num_jobs is not None:
+            args.extend(['-j', str(self.builder.num_jobs)])
+        if self.builder.warnings_as_errors:
+            args.append('KCFLAGS=-Werror')
+            args.append('HOSTCFLAGS=-Werror')
+        if self.builder.allow_missing:
+            args.append('BINMAN_ALLOW_MISSING=1')
+        if self.builder.no_lto:
+            args.append('NO_LTO=1')
+        if self.builder.reproducible_builds:
+            args.append('SOURCE_DATE_EPOCH=0')
+        args.extend(self.builder.toolchains.GetMakeArguments(brd))
+        args.extend(self.toolchain.MakeArgs())
+        return args, cwd, src_dir
+
+    def _reconfigure(self, commit, brd, cwd, args, env, config_args, config_out,
+                     cmd_list):
+        """Reconfigure the build
 
-        # Check if the job was already completed last time
-        done_file = self.builder.GetDoneFile(commit_upto, brd.target)
+        Args:
+            commit (Commit): Commit only being built
+            brd (Board): Board being built
+            cwd (str): Current working directory
+            args (list of str): Arguments to pass to make
+            env (dict): Environment strings
+            config_args (list of str): defconfig arg for this board
+            cmd_list (list of str): List to add the commands to, for logging
+
+        Returns:
+            CommandResult object
+        """
+        if self.mrproper:
+            result = self.make(commit, brd, 'mrproper', cwd, 'mrproper', *args,
+                               env=env)
+            config_out.write(result.combined)
+            cmd_list.append([self.builder.gnu_make, 'mrproper', *args])
+        result = self.make(commit, brd, 'config', cwd, *(args + config_args),
+                           env=env)
+        cmd_list.append([self.builder.gnu_make] + args + config_args)
+        config_out.write(result.combined)
+        return result
+
+    def _build(self, commit, brd, cwd, args, env, cmd_list, config_only):
+        """Perform the build
+
+        Args:
+            commit (Commit): Commit only being built
+            brd (Board): Board being built
+            cwd (str): Current working directory
+            args (list of str): Arguments to pass to make
+            env (dict): Environment strings
+            cmd_list (list of str): List to add the commands to, for logging
+            config_only (bool): True if this is a config-only build (using the
+                'make cfg' target)
+
+        Returns:
+            CommandResult object
+        """
+        if config_only:
+            args.append('cfg')
+        result = self.make(commit, brd, 'build', cwd, *args, env=env)
+        cmd_list.append([self.builder.gnu_make] + args)
+        if (result.return_code == 2 and
+            ('Some images are invalid' in result.stderr)):
+            # This is handled later by the check for output in stderr
+            result.return_code = 0
+        return result
+
+    def _read_done_file(self, commit_upto, brd, force_build,
+                        force_build_failures):
+        """Check the 'done' file and see if this commit should be built
+
+        Args:
+            commit (Commit): Commit only being built
+            brd (Board): Board being built
+            force_build (bool): Force a build even if one was previously done
+            force_build_failures (bool): Force a bulid if the previous result
+                showed failure
+
+        Returns:
+            tuple:
+                bool: True if build should be built
+                CommandResult: if there was a previous run:
+                    - already_done set to True
+                    - return_code set to return code
+                    - result.stderr set to 'bad' if stderr output was recorded
+        """
+        result = command.CommandResult()
+        done_file = self.builder.get_done_file(commit_upto, brd.target)
         result.already_done = os.path.exists(done_file)
         will_build = (force_build or force_build_failures or
             not result.already_done)
         if result.already_done:
-            # Get the return code from that build and use it
-            with open(done_file, 'r') as fd:
+            with open(done_file, 'r', encoding='utf-8') as outf:
                 try:
-                    result.return_code = int(fd.readline())
+                    result.return_code = int(outf.readline())
                 except ValueError:
                     # The file may be empty due to running out of disk space.
                     # Try a rebuild
@@ -194,12 +326,155 @@ class BuilderThread(threading.Thread):
             if result.return_code == RETURN_CODE_RETRY:
                 will_build = True
             elif will_build:
-                err_file = self.builder.GetErrFile(commit_upto, brd.target)
+                err_file = self.builder.get_err_file(commit_upto, brd.target)
                 if os.path.exists(err_file) and os.stat(err_file).st_size:
                     result.stderr = 'bad'
                 elif not force_build:
                     # The build passed, so no need to build it again
                     will_build = False
+        return will_build, result
+
+    def _decide_dirs(self, brd, work_dir, work_in_output):
+        """Decide the output directory to use
+
+        Args:
+            work_dir (str): Directory to which the source will be checked out
+            work_in_output (bool): Use the output directory as the work
+                directory and don't write to a separate output directory.
+
+        Returns:
+            tuple:
+                out_dir (str): Output directory for the build
+                out_rel_dir (str): Output directory relatie to the current dir
+        """
+        if work_in_output or self.builder.in_tree:
+            out_rel_dir = None
+            out_dir = work_dir
+        else:
+            if self.per_board_out_dir:
+                out_rel_dir = os.path.join('..', brd.target)
+            else:
+                out_rel_dir = 'build'
+            out_dir = os.path.join(work_dir, out_rel_dir)
+        return out_dir, out_rel_dir
+
+    def _checkout(self, commit_upto, work_dir):
+        """Checkout the right commit
+
+        Args:
+            commit_upto (int): Commit number to build (0...n-1)
+            work_dir (str): Directory to which the source will be checked out
+
+        Returns:
+            Commit: Commit being built, or 'current' for current source
+        """
+        if self.builder.commits:
+            commit = self.builder.commits[commit_upto]
+            if self.builder.checkout:
+                git_dir = os.path.join(work_dir, '.git')
+                gitutil.checkout(commit.hash, git_dir, work_dir, force=True)
+        else:
+            commit = 'current'
+        return commit
+
+    def _config_and_build(self, commit_upto, brd, work_dir, do_config,
+                          config_only, adjust_cfg, commit, out_dir, out_rel_dir,
+                          result):
+        """Do the build, configuring first if necessary
+
+        Args:
+            commit_upto (int): Commit number to build (0...n-1)
+            brd (Board): Board to create arguments for
+            work_dir (str): Directory to which the source will be checked out
+            do_config (bool): True to run a make <board>_defconfig on the source
+            config_only (bool): Only configure the source, do not build it
+            adjust_cfg (list of str): See the cfgutil module and run_commit()
+            commit (Commit): Commit only being built
+            out_dir (str): Output directory for the build
+            out_rel_dir (str): Output directory relatie to the current dir
+            result (CommandResult): Previous result
+
+        Returns:
+            tuple:
+                result (CommandResult): Result of the build
+                do_config (bool): indicates whether 'make config' is needed on
+                    the next incremental build
+        """
+        # Set up the environment and command line
+        env = self.toolchain.MakeEnvironment(self.builder.full_path)
+        mkdir(out_dir)
+
+        args, cwd, src_dir = self._build_args(brd, out_dir, out_rel_dir,
+                                              work_dir, commit_upto)
+        config_args = [f'{brd.target}_defconfig']
+        config_out = io.StringIO()
+
+        _remove_old_outputs(out_dir)
+
+        # If we need to reconfigure, do that now
+        cfg_file = os.path.join(out_dir, '.config')
+        cmd_list = []
+        if do_config or adjust_cfg:
+            result = self._reconfigure(
+                commit, brd, cwd, args, env, config_args, config_out, cmd_list)
+            do_config = False   # No need to configure next time
+            if adjust_cfg:
+                cfgutil.adjust_cfg_file(cfg_file, adjust_cfg)
+
+        # Now do the build, if everything looks OK
+        if result.return_code == 0:
+            result = self._build(commit, brd, cwd, args, env, cmd_list,
+                                 config_only)
+            if adjust_cfg:
+                errs = cfgutil.check_cfg_file(cfg_file, adjust_cfg)
+                if errs:
+                    result.stderr += errs
+                    result.return_code = 1
+        result.stderr = result.stderr.replace(src_dir + '/', '')
+        if self.builder.verbose_build:
+            result.stdout = config_out.getvalue() + result.stdout
+        result.cmd_list = cmd_list
+        return result, do_config
+
+    def run_commit(self, commit_upto, brd, work_dir, do_config, config_only,
+                  force_build, force_build_failures, work_in_output,
+                  adjust_cfg):
+        """Build a particular commit.
+
+        If the build is already done, and we are not forcing a build, we skip
+        the build and just return the previously-saved results.
+
+        Args:
+            commit_upto (int): Commit number to build (0...n-1)
+            brd (Board): Board to build
+            work_dir (str): Directory to which the source will be checked out
+            do_config (bool): True to run a make <board>_defconfig on the source
+            config_only (bool): Only configure the source, do not build it
+            force_build (bool): Force a build even if one was previously done
+            force_build_failures (bool): Force a bulid if the previous result
+                showed failure
+            work_in_output (bool) : Use the output directory as the work
+                directory and don't write to a separate output directory.
+            adjust_cfg (list of str): List of changes to make to .config file
+                before building. Each is one of (where C is either CONFIG_xxx
+                or just xxx):
+                     C to enable C
+                     ~C to disable C
+                     C=val to set the value of C (val must have quotes if C is
+                         a string Kconfig
+
+        Returns:
+            tuple containing:
+                - CommandResult object containing the results of the build
+                - boolean indicating whether 'make config' is still needed
+        """
+        # Create a default result - it will be overwritte by the call to
+        # self.make() below, in the event that we do a build.
+        out_dir, out_rel_dir = self._decide_dirs(brd, work_dir, work_in_output)
+
+        # Check if the job was already completed last time
+        will_build, result = self._read_done_file(commit_upto, brd, force_build,
+                                                  force_build_failures)
 
         if will_build:
             # We are going to have to build it. First, get a toolchain
@@ -209,115 +484,13 @@ class BuilderThread(threading.Thread):
                 except ValueError as err:
                     result.return_code = 10
                     result.stdout = ''
-                    result.stderr = str(err)
-                    # TODO(sjg@chromium.org): This gets swallowed, but needs
-                    # to be reported.
+                    result.stderr = f'Tool chain error for {brd.arch}: {str(err)}'
 
             if self.toolchain:
-                # Checkout the right commit
-                if self.builder.commits:
-                    commit = self.builder.commits[commit_upto]
-                    if self.builder.checkout:
-                        git_dir = os.path.join(work_dir, '.git')
-                        gitutil.checkout(commit.hash, git_dir, work_dir,
-                                         force=True)
-                else:
-                    commit = 'current'
-
-                # Set up the environment and command line
-                env = self.toolchain.MakeEnvironment(self.builder.full_path)
-                Mkdir(out_dir)
-                args = []
-                cwd = work_dir
-                src_dir = os.path.realpath(work_dir)
-                if not self.builder.in_tree:
-                    if commit_upto is None:
-                        # In this case we are building in the original source
-                        # directory (i.e. the current directory where buildman
-                        # is invoked. The output directory is set to this
-                        # thread's selected work directory.
-                        #
-                        # Symlinks can confuse U-Boot's Makefile since
-                        # we may use '..' in our path, so remove them.
-                        out_dir = os.path.realpath(out_dir)
-                        args.append('O=%s' % out_dir)
-                        cwd = None
-                        src_dir = os.getcwd()
-                    else:
-                        args.append('O=%s' % out_rel_dir)
-                if self.builder.verbose_build:
-                    args.append('V=1')
-                else:
-                    args.append('-s')
-                if self.builder.num_jobs is not None:
-                    args.extend(['-j', str(self.builder.num_jobs)])
-                if self.builder.warnings_as_errors:
-                    args.append('KCFLAGS=-Werror')
-                    args.append('HOSTCFLAGS=-Werror')
-                if self.builder.allow_missing:
-                    args.append('BINMAN_ALLOW_MISSING=1')
-                if self.builder.no_lto:
-                    args.append('NO_LTO=1')
-                if self.builder.reproducible_builds:
-                    args.append('SOURCE_DATE_EPOCH=0')
-                config_args = ['%s_defconfig' % brd.target]
-                config_out = ''
-                args.extend(self.builder.toolchains.GetMakeArguments(brd))
-                args.extend(self.toolchain.MakeArgs())
-
-                # Remove any output targets. Since we use a build directory that
-                # was previously used by another board, it may have produced an
-                # SPL image. If we don't remove it (i.e. see do_config and
-                # self.mrproper below) then it will appear to be the output of
-                # this build, even if it does not produce SPL images.
-                build_dir = self.builder.GetBuildDir(commit_upto, brd.target)
-                for elf in BASE_ELF_FILENAMES:
-                    fname = os.path.join(out_dir, elf)
-                    if os.path.exists(fname):
-                        os.remove(fname)
-
-                # If we need to reconfigure, do that now
-                cfg_file = os.path.join(out_dir, '.config')
-                cmd_list = []
-                if do_config or adjust_cfg:
-                    config_out = ''
-                    if self.mrproper:
-                        result = self.Make(commit, brd, 'mrproper', cwd,
-                                'mrproper', *args, env=env)
-                        config_out += result.combined
-                        cmd_list.append([self.builder.gnu_make, 'mrproper',
-                                         *args])
-                    result = self.Make(commit, brd, 'config', cwd,
-                            *(args + config_args), env=env)
-                    cmd_list.append([self.builder.gnu_make] + args +
-                                    config_args)
-                    config_out += result.combined
-                    do_config = False   # No need to configure next time
-                    if adjust_cfg:
-                        cfgutil.adjust_cfg_file(cfg_file, adjust_cfg)
-                if result.return_code == 0:
-                    if config_only:
-                        args.append('cfg')
-                    result = self.Make(commit, brd, 'build', cwd, *args,
-                            env=env)
-                    cmd_list.append([self.builder.gnu_make] + args)
-                    if (result.return_code == 2 and
-                        ('Some images are invalid' in result.stderr)):
-                        # This is handled later by the check for output in
-                        # stderr
-                        result.return_code = 0
-                    if adjust_cfg:
-                        errs = cfgutil.check_cfg_file(cfg_file, adjust_cfg)
-                        if errs:
-                            result.stderr += errs
-                            result.return_code = 1
-                result.stderr = result.stderr.replace(src_dir + '/', '')
-                if self.builder.verbose_build:
-                    result.stdout = config_out + result.stdout
-                result.cmd_list = cmd_list
-            else:
-                result.return_code = 1
-                result.stderr = 'No tool chain for %s\n' % brd.arch
+                commit = self._checkout(commit_upto, work_dir)
+                result, do_config = self._config_and_build(
+                    commit_upto, brd, work_dir, do_config, config_only,
+                    adjust_cfg, commit, out_dir, out_rel_dir, result)
             result.already_done = False
 
         result.toolchain = self.toolchain
@@ -326,15 +499,15 @@ class BuilderThread(threading.Thread):
         result.out_dir = out_dir
         return result, do_config
 
-    def _WriteResult(self, result, keep_outputs, work_in_output):
+    def _write_result(self, result, keep_outputs, work_in_output):
         """Write a built result to the output directory.
 
         Args:
-            result: CommandResult object containing result to write
-            keep_outputs: True to store the output binaries, False
+            result (CommandResult): result to write
+            keep_outputs (bool): True to store the output binaries, False
                 to delete them
-            work_in_output: Use the output directory as the work directory and
-                don't write to a separate output directory.
+            work_in_output (bool): Use the output directory as the work
+                directory and don't write to a separate output directory.
         """
         # If we think this might have been aborted with Ctrl-C, record the
         # failure but not that we are 'done' with this board. A retry may fix
@@ -345,22 +518,22 @@ class BuilderThread(threading.Thread):
             return
 
         # Write the output and stderr
-        output_dir = self.builder._GetOutputDir(result.commit_upto)
-        Mkdir(output_dir)
-        build_dir = self.builder.GetBuildDir(result.commit_upto,
+        output_dir = self.builder.get_output_dir(result.commit_upto)
+        mkdir(output_dir)
+        build_dir = self.builder.get_build_dir(result.commit_upto,
                 result.brd.target)
-        Mkdir(build_dir)
+        mkdir(build_dir)
 
         outfile = os.path.join(build_dir, 'log')
-        with open(outfile, 'w') as fd:
+        with open(outfile, 'w', encoding='utf-8') as outf:
             if result.stdout:
-                fd.write(result.stdout)
+                outf.write(result.stdout)
 
-        errfile = self.builder.GetErrFile(result.commit_upto,
+        errfile = self.builder.get_err_file(result.commit_upto,
                 result.brd.target)
         if result.stderr:
-            with open(errfile, 'w') as fd:
-                fd.write(result.stderr)
+            with open(errfile, 'w', encoding='utf-8') as outf:
+                outf.write(result.stderr)
         elif os.path.exists(errfile):
             os.remove(errfile)
 
@@ -370,60 +543,61 @@ class BuilderThread(threading.Thread):
 
         if result.toolchain:
             # Write the build result and toolchain information.
-            done_file = self.builder.GetDoneFile(result.commit_upto,
+            done_file = self.builder.get_done_file(result.commit_upto,
                     result.brd.target)
-            with open(done_file, 'w') as fd:
+            with open(done_file, 'w', encoding='utf-8') as outf:
                 if maybe_aborted:
                     # Special code to indicate we need to retry
-                    fd.write('%s' % RETURN_CODE_RETRY)
+                    outf.write(f'{RETURN_CODE_RETRY}')
                 else:
-                    fd.write('%s' % result.return_code)
-            with open(os.path.join(build_dir, 'toolchain'), 'w') as fd:
-                print('gcc', result.toolchain.gcc, file=fd)
-                print('path', result.toolchain.path, file=fd)
-                print('cross', result.toolchain.cross, file=fd)
-                print('arch', result.toolchain.arch, file=fd)
-                fd.write('%s' % result.return_code)
+                    outf.write(f'{result.return_code}')
+            with open(os.path.join(build_dir, 'toolchain'), 'w',
+                      encoding='utf-8') as outf:
+                print('gcc', result.toolchain.gcc, file=outf)
+                print('path', result.toolchain.path, file=outf)
+                print('cross', result.toolchain.cross, file=outf)
+                print('arch', result.toolchain.arch, file=outf)
+                outf.write(f'{result.return_code}')
 
             # Write out the image and function size information and an objdump
             env = result.toolchain.MakeEnvironment(self.builder.full_path)
-            with open(os.path.join(build_dir, 'out-env'), 'wb') as fd:
+            with open(os.path.join(build_dir, 'out-env'), 'wb') as outf:
                 for var in sorted(env.keys()):
-                    fd.write(b'%s="%s"' % (var, env[var]))
+                    outf.write(b'%s="%s"' % (var, env[var]))
 
             with open(os.path.join(build_dir, 'out-cmd'), 'w',
-                      encoding='utf-8') as fd:
+                      encoding='utf-8') as outf:
                 for cmd in result.cmd_list:
-                    print(' '.join(cmd), file=fd)
+                    print(' '.join(cmd), file=outf)
 
             lines = []
             for fname in BASE_ELF_FILENAMES:
-                cmd = ['%snm' % self.toolchain.cross, '--size-sort', fname]
+                cmd = [f'{self.toolchain.cross}nm', '--size-sort', fname]
                 nm_result = command.run_pipe([cmd], capture=True,
                         capture_stderr=True, cwd=result.out_dir,
                         raise_on_error=False, env=env)
                 if nm_result.stdout:
-                    nm = self.builder.GetFuncSizesFile(result.commit_upto,
-                                    result.brd.target, fname)
-                    with open(nm, 'w') as fd:
-                        print(nm_result.stdout, end=' ', file=fd)
+                    nm_fname = self.builder.get_func_sizes_file(
+                        result.commit_upto, result.brd.target, fname)
+                    with open(nm_fname, 'w', encoding='utf-8') as outf:
+                        print(nm_result.stdout, end=' ', file=outf)
 
-                cmd = ['%sobjdump' % self.toolchain.cross, '-h', fname]
+                cmd = [f'{self.toolchain.cross}objdump', '-h', fname]
                 dump_result = command.run_pipe([cmd], capture=True,
                         capture_stderr=True, cwd=result.out_dir,
                         raise_on_error=False, env=env)
                 rodata_size = ''
                 if dump_result.stdout:
-                    objdump = self.builder.GetObjdumpFile(result.commit_upto,
+                    objdump = self.builder.get_objdump_file(result.commit_upto,
                                     result.brd.target, fname)
-                    with open(objdump, 'w') as fd:
-                        print(dump_result.stdout, end=' ', file=fd)
+                    with open(objdump, 'w', encoding='utf-8') as outf:
+                        print(dump_result.stdout, end=' ', file=outf)
                     for line in dump_result.stdout.splitlines():
                         fields = line.split()
                         if len(fields) > 5 and fields[1] == '.rodata':
                             rodata_size = fields[2]
 
-                cmd = ['%ssize' % self.toolchain.cross, fname]
+                cmd = [f'{self.toolchain.cross}size', fname]
                 size_result = command.run_pipe([cmd], capture=True,
                         capture_stderr=True, cwd=result.out_dir,
                         raise_on_error=False, env=env)
@@ -432,30 +606,29 @@ class BuilderThread(threading.Thread):
                                  rodata_size)
 
             # Extract the environment from U-Boot and dump it out
-            cmd = ['%sobjcopy' % self.toolchain.cross, '-O', 'binary',
+            cmd = [f'{self.toolchain.cross}objcopy', '-O', 'binary',
                    '-j', '.rodata.default_environment',
                    'env/built-in.o', 'uboot.env']
             command.run_pipe([cmd], capture=True,
                             capture_stderr=True, cwd=result.out_dir,
                             raise_on_error=False, env=env)
-            ubootenv = os.path.join(result.out_dir, 'uboot.env')
             if not work_in_output:
-                self.CopyFiles(result.out_dir, build_dir, '', ['uboot.env'])
+                copy_files(result.out_dir, build_dir, '', ['uboot.env'])
 
             # Write out the image sizes file. This is similar to the output
             # of binutil's 'size' utility, but it omits the header line and
             # adds an additional hex value at the end of each line for the
             # rodata size
-            if len(lines):
-                sizes = self.builder.GetSizesFile(result.commit_upto,
+            if lines:
+                sizes = self.builder.get_sizes_file(result.commit_upto,
                                 result.brd.target)
-                with open(sizes, 'w') as fd:
-                    print('\n'.join(lines), file=fd)
+                with open(sizes, 'w', encoding='utf-8') as outf:
+                    print('\n'.join(lines), file=outf)
 
         if not work_in_output:
             # Write out the configuration files, with a special case for SPL
             for dirname in ['', 'spl', 'tpl']:
-                self.CopyFiles(
+                copy_files(
                     result.out_dir, build_dir, dirname,
                     ['u-boot.cfg', 'spl/u-boot-spl.cfg', 'tpl/u-boot-tpl.cfg',
                      '.config', 'include/autoconf.mk',
@@ -463,60 +636,40 @@ class BuilderThread(threading.Thread):
 
             # Now write the actual build output
             if keep_outputs:
-                self.CopyFiles(
+                copy_files(
                     result.out_dir, build_dir, '',
                     ['u-boot*', '*.bin', '*.map', '*.img', 'MLO', 'SPL',
                      'include/autoconf.mk', 'spl/u-boot-spl*'])
 
-    def CopyFiles(self, out_dir, build_dir, dirname, patterns):
-        """Copy files from the build directory to the output.
-
-        Args:
-            out_dir: Path to output directory containing the files
-            build_dir: Place to copy the files
-            dirname: Source directory, '' for normal U-Boot, 'spl' for SPL
-            patterns: A list of filenames (strings) to copy, each relative
-               to the build directory
-        """
-        for pattern in patterns:
-            file_list = glob.glob(os.path.join(out_dir, dirname, pattern))
-            for fname in file_list:
-                target = os.path.basename(fname)
-                if dirname:
-                    base, ext = os.path.splitext(target)
-                    if ext:
-                        target = '%s-%s%s' % (base, dirname, ext)
-                shutil.copy(fname, os.path.join(build_dir, target))
-
-    def _SendResult(self, result):
+    def _send_result(self, result):
         """Send a result to the builder for processing
 
         Args:
-            result: CommandResult object containing the results of the build
+            result (CommandResult): results of the build
 
         Raises:
-            ValueError if self.test_exception is true (for testing)
+            ValueError: self.test_exception is true (for testing)
         """
         if self.test_exception:
             raise ValueError('test exception')
         if self.thread_num != -1:
             self.builder.out_queue.put(result)
         else:
-            self.builder.ProcessResult(result)
+            self.builder.process_result(result)
 
-    def RunJob(self, job):
+    def run_job(self, job):
         """Run a single job
 
         A job consists of a building a list of commits for a particular board.
 
         Args:
-            job: Job to build
+            job (Job): Job to build
 
-        Returns:
-            List of Result objects
+        Raises:
+            ValueError: Thread was interrupted
         """
         brd = job.brd
-        work_dir = self.builder.GetThreadDir(self.thread_num)
+        work_dir = self.builder.get_thread_dir(self.thread_num)
         self.toolchain = None
         if job.commits:
             # Run 'make board_defconfig' on the first commit
@@ -524,7 +677,7 @@ class BuilderThread(threading.Thread):
             commit_upto  = 0
             force_build = False
             for commit_upto in range(0, len(job.commits), job.step):
-                result, request_config = self.RunCommit(commit_upto, brd,
+                result, request_config = self.run_commit(commit_upto, brd,
                         work_dir, do_config, self.builder.config_only,
                         force_build or self.builder.force_build,
                         self.builder.force_build_failures,
@@ -535,7 +688,7 @@ class BuilderThread(threading.Thread):
                     # If our incremental build failed, try building again
                     # with a reconfig.
                     if self.builder.force_config_on_failure:
-                        result, request_config = self.RunCommit(commit_upto,
+                        result, request_config = self.run_commit(commit_upto,
                             brd, work_dir, True, False, True, False,
                             job.work_in_output, job.adjust_cfg)
                         did_config = True
@@ -576,17 +729,17 @@ class BuilderThread(threading.Thread):
                         raise ValueError('Interrupt')
 
                 # We have the build results, so output the result
-                self._WriteResult(result, job.keep_outputs, job.work_in_output)
-                self._SendResult(result)
+                self._write_result(result, job.keep_outputs, job.work_in_output)
+                self._send_result(result)
         else:
             # Just build the currently checked-out build
-            result, request_config = self.RunCommit(None, brd, work_dir, True,
+            result, request_config = self.run_commit(None, brd, work_dir, True,
                         self.builder.config_only, True,
                         self.builder.force_build_failures, job.work_in_output,
                         job.adjust_cfg)
             result.commit_upto = 0
-            self._WriteResult(result, job.keep_outputs, job.work_in_output)
-            self._SendResult(result)
+            self._write_result(result, job.keep_outputs, job.work_in_output)
+            self._send_result(result)
 
     def run(self):
         """Our thread's run function
@@ -597,8 +750,9 @@ class BuilderThread(threading.Thread):
         while True:
             job = self.builder.queue.get()
             try:
-                self.RunJob(job)
-            except Exception as e:
-                print('Thread exception (use -T0 to run without threads):', e)
-                self.builder.thread_exceptions.append(e)
+                self.run_job(job)
+            except Exception as exc:
+                print('Thread exception (use -T0 to run without threads):',
+                      exc)
+                self.builder.thread_exceptions.append(exc)
             self.builder.queue.task_done()
diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst
index c8b0db3d8b..aae2477b5c 100644
--- a/tools/buildman/buildman.rst
+++ b/tools/buildman/buildman.rst
@@ -159,7 +159,7 @@ on the command line:
 
 .. code-block:: bash
 
-  buildman --boards sandbox,snow --boards
+  buildman --boards sandbox,snow --boards firefly-rk3399
 
 It is convenient to use the -n option to see what will be built based on
 the subset given. Use -v as well to get an actual list of boards.
@@ -475,10 +475,6 @@ Setting up
       sudo mkdir -p /toolchains
       sudo mv ~/.buildman-toolchains/*/* /toolchains/
 
-   For those not available from kernel.org, download from the following links:
-
-   - `Arc Toolchain`_
-
    Buildman should now be set up to use your new toolchain.
 
    At the time of writing, U-Boot has these architectures:
@@ -1066,9 +1062,9 @@ same as 'am335x_evm_usbspl'/
 
 The -K option uses the u-boot.cfg, spl/u-boot-spl.cfg and tpl/u-boot-tpl.cfg
 files which are produced by a build. If all you want is to check the
-configuration you can in fact avoid doing a full build, using -D. This tells
-buildman to configuration U-Boot and create the .cfg files, but not actually
-build the source. This is 5-10 times faster than doing a full build.
+configuration you can in fact avoid doing a full build, using --config-only.
+This tells buildman to configuration U-Boot and create the .cfg files, but not
+actually build the source. This is 5-10 times faster than doing a full build.
 
 By default buildman considers the follow two configuration methods
 equivalent::
@@ -1307,14 +1303,32 @@ Using boards.cfg
 
 This file is no-longer needed by buildman but it is still generated in the
 working directory. This helps avoid a delay on every build, since scanning all
-the Kconfig files takes a few seconds. Use the -R flag to force regeneration
-of the file - in that case buildman exits after writing the file. with exit code
-2 if there was an error in the maintainer files.
+the Kconfig files takes a few seconds. Use the `-R <filename>` flag to force
+regeneration of the file - in that case buildman exits after writing the file
+with exit code 2 if there was an error in the maintainer files. To use the
+default filename, use a hyphen, i.e. `-R -`.
 
 You should use 'buildman -nv <criteria>' instead of greoing the boards.cfg file,
 since it may be dropped altogether in future.
 
 
+Checking maintainers
+--------------------
+
+Sometimes a board is added without a corresponding entry in a MAINTAINERS file.
+Use the `--maintainer-check` option to check this::
+
+   $ buildman --maintainer-check
+   WARNING: board/mikrotik/crs3xx-98dx3236/MAINTAINERS: missing defconfig ending at line 7
+   WARNING: no maintainers for 'clearfog_spi'
+
+Buildman returns with an exit code of 2 if there area any warnings.
+
+An experimental `--full-check option` also checks for boards which don't have a
+CONFIG_TARGET_xxx where xxx corresponds to their defconfig filename. This is
+not strictly necessary, but may be useful information.
+
+
 Checking the command
 --------------------
 
@@ -1342,8 +1356,6 @@ Thanks to Grant Grundler <grundler@chromium.org> for his ideas for improving
 the build speed by building all commits for a board instead of the other
 way around.
 
-.. _`Arc Toolchain`: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2021.03-release/arc_gnu_2021.03_prebuilt_elf32_le_linux_install.tar.gz
-
 .. sectionauthor:: Simon Glass
 .. sectionauthor:: Copyright (c) 2013 The Chromium OS Authors.
 .. sectionauthor:: sjg@chromium.org
diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py
index a9cda24957..03211bd5aa 100644
--- a/tools/buildman/cmdline.py
+++ b/tools/buildman/cmdline.py
@@ -2,148 +2,190 @@
 # Copyright (c) 2014 Google, Inc
 #
 
-from optparse import OptionParser
+"""Handles parsing of buildman arguments
+
+This creates the argument parser and uses it to parse the arguments passed in
+"""
+
+import argparse
 import os
 import pathlib
 
 BUILDMAN_DIR = pathlib.Path(__file__).parent
 HAS_TESTS = os.path.exists(BUILDMAN_DIR / "test.py")
 
-def ParseArgs():
-    """Parse command line arguments from sys.argv[]
+def add_upto_m(parser):
+    """Add arguments up to 'M'
 
-    Returns:
-        tuple containing:
-            options: command line options
-            args: command lin arguments
+    Args:
+        parser (ArgumentParser): Parse to add to
+
+    This is split out to avoid having too many statements in one function
     """
-    parser = OptionParser()
-    parser.add_option('-a', '--adjust-cfg', type=str, action='append',
+    parser.add_argument('-a', '--adjust-cfg', type=str, action='append',
           help='Adjust the Kconfig settings in .config before building')
-    parser.add_option('-A', '--print-prefix', action='store_true',
+    parser.add_argument('-A', '--print-prefix', action='store_true',
           help='Print the tool-chain prefix for a board (CROSS_COMPILE=)')
-    parser.add_option('-b', '--branch', type='string',
+    parser.add_argument('-b', '--branch', type=str,
           help='Branch name to build, or range of commits to build')
-    parser.add_option('-B', '--bloat', dest='show_bloat',
+    parser.add_argument('-B', '--bloat', dest='show_bloat',
           action='store_true', default=False,
           help='Show changes in function code size for each board')
-    parser.add_option('--boards', type='string', action='append',
+    parser.add_argument('--boards', type=str, action='append',
           help='List of board names to build separated by comma')
-    parser.add_option('-c', '--count', dest='count', type='int',
+    parser.add_argument('-c', '--count', dest='count', type=int,
           default=-1, help='Run build on the top n commits')
-    parser.add_option('-C', '--force-reconfig', dest='force_reconfig',
+    parser.add_argument('-C', '--force-reconfig', dest='force_reconfig',
           action='store_true', default=False,
           help='Reconfigure for every commit (disable incremental build)')
-    parser.add_option('-d', '--detail', dest='show_detail',
+    parser.add_argument('--config-only', action='store_true',
+                        default=False,
+                        help="Don't build, just configure each commit")
+    parser.add_argument('-d', '--detail', dest='show_detail',
           action='store_true', default=False,
           help='Show detailed size delta for each board in the -S summary')
-    parser.add_option('-D', '--config-only', action='store_true', default=False,
-          help="Don't build, just configure each commit")
-    parser.add_option('--debug', action='store_true',
+    parser.add_argument('-D', '--debug', action='store_true',
         help='Enabling debugging (provides a full traceback on error)')
-    parser.add_option('-e', '--show_errors', action='store_true',
+    parser.add_argument('-e', '--show_errors', action='store_true',
           default=False, help='Show errors and warnings')
-    parser.add_option('-E', '--warnings-as-errors', action='store_true',
+    parser.add_argument('-E', '--warnings-as-errors', action='store_true',
           default=False, help='Treat all compiler warnings as errors')
-    parser.add_option('-f', '--force-build', dest='force_build',
+    parser.add_argument('-f', '--force-build', dest='force_build',
           action='store_true', default=False,
           help='Force build of boards even if already built')
-    parser.add_option('-F', '--force-build-failures', dest='force_build_failures',
+    parser.add_argument('-F', '--force-build-failures', dest='force_build_failures',
           action='store_true', default=False,
           help='Force build of previously-failed build')
-    parser.add_option('--fetch-arch', type='string',
+    parser.add_argument('--fetch-arch', type=str,
           help="Fetch a toolchain for architecture FETCH_ARCH ('list' to list)."
               ' You can also fetch several toolchains separate by comma, or'
               " 'all' to download all")
-    parser.add_option('-g', '--git', type='string',
+    parser.add_argument(
+          '--full-check', action='store_true',
+          help='Check maintainer entries and TARGET configs')
+    parser.add_argument('-g', '--git', type=str,
           help='Git repo containing branch to build', default='.')
-    parser.add_option('-G', '--config-file', type='string',
+    parser.add_argument('-G', '--config-file', type=str,
           help='Path to buildman config file', default='')
-    parser.add_option('-H', '--full-help', action='store_true', dest='full_help',
+    parser.add_argument('-H', '--full-help', action='store_true', dest='full_help',
           default=False, help='Display the README file')
-    parser.add_option('-i', '--in-tree', dest='in_tree',
+    parser.add_argument('-i', '--in-tree', dest='in_tree',
           action='store_true', default=False,
           help='Build in the source tree instead of a separate directory')
-    parser.add_option('-I', '--ide', action='store_true', default=False,
+    parser.add_argument('-I', '--ide', action='store_true', default=False,
           help='Create build output that can be parsed by an IDE')
-    parser.add_option('-j', '--jobs', dest='jobs', type='int',
+    parser.add_argument('-j', '--jobs', dest='jobs', type=int,
           default=None, help='Number of jobs to run at once (passed to make)')
-    parser.add_option('-k', '--keep-outputs', action='store_true',
+    parser.add_argument('-k', '--keep-outputs', action='store_true',
           default=False, help='Keep all build output files (e.g. binaries)')
-    parser.add_option('-K', '--show-config', action='store_true',
-          default=False, help='Show configuration changes in summary (both board config files and Kconfig)')
-    parser.add_option('--preserve-config-y', action='store_true',
+    parser.add_argument('-K', '--show-config', action='store_true',
+          default=False,
+          help='Show configuration changes in summary (both board config files and Kconfig)')
+    parser.add_argument('--preserve-config-y', action='store_true',
           default=False, help="Don't convert y to 1 in configs")
-    parser.add_option('-l', '--list-error-boards', action='store_true',
+    parser.add_argument('-l', '--list-error-boards', action='store_true',
           default=False, help='Show a list of boards next to each error/warning')
-    parser.add_option('-L', '--no-lto', action='store_true',
+    parser.add_argument('-L', '--no-lto', action='store_true',
           default=False, help='Disable Link-time Optimisation (LTO) for builds')
-    parser.add_option('--list-tool-chains', action='store_true', default=False,
+    parser.add_argument('--list-tool-chains', action='store_true', default=False,
           help='List available tool chains (use -v to see probing detail)')
-    parser.add_option('-m', '--mrproper', action='store_true',
+    parser.add_argument('-m', '--mrproper', action='store_true',
           default=False, help="Run 'make mrproper before reconfiguring")
-    parser.add_option(
+    parser.add_argument(
           '-M', '--allow-missing', action='store_true', default=False,
-          help='Tell binman to allow missing blobs and generate fake ones as needed'),
-    parser.add_option(
+          help='Tell binman to allow missing blobs and generate fake ones as needed')
+    parser.add_argument(
+          '--maintainer-check', action='store_true',
+          help='Check that maintainer entries exist for each board')
+    parser.add_argument(
           '--no-allow-missing', action='store_true', default=False,
-          help='Disable telling binman to allow missing blobs'),
-    parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run',
+          help='Disable telling binman to allow missing blobs')
+    parser.add_argument('-n', '--dry-run', action='store_true', dest='dry_run',
           default=False, help="Do a dry run (describe actions, but do nothing)")
-    parser.add_option('-N', '--no-subdirs', action='store_true', dest='no_subdirs',
-          default=False, help="Don't create subdirectories when building current source for a single board")
-    parser.add_option('-o', '--output-dir', type='string', dest='output_dir',
+    parser.add_argument('-N', '--no-subdirs', action='store_true', dest='no_subdirs',
+          default=False,
+          help="Don't create subdirectories when building current source for a single board")
+
+
+def add_after_m(parser):
+    """Add arguments after 'M'
+
+    Args:
+        parser (ArgumentParser): Parse to add to
+
+    This is split out to avoid having too many statements in one function
+    """
+    parser.add_argument('-o', '--output-dir', type=str, dest='output_dir',
           help='Directory where all builds happen and buildman has its workspace (default is ../)')
-    parser.add_option('-O', '--override-toolchain', type='string',
+    parser.add_argument('-O', '--override-toolchain', type=str,
           help="Override host toochain to use for sandbox (e.g. 'clang-7')")
-    parser.add_option('-Q', '--quick', action='store_true',
+    parser.add_argument('-Q', '--quick', action='store_true',
           default=False, help='Do a rough build, with limited warning resolution')
-    parser.add_option('-p', '--full-path', action='store_true',
+    parser.add_argument('-p', '--full-path', action='store_true',
           default=False, help="Use full toolchain path in CROSS_COMPILE")
-    parser.add_option('-P', '--per-board-out-dir', action='store_true',
+    parser.add_argument('-P', '--per-board-out-dir', action='store_true',
           default=False, help="Use an O= (output) directory per board rather than per thread")
-    parser.add_option('-r', '--reproducible-builds', action='store_true',
+    parser.add_argument('--print-arch', action='store_true',
+          default=False, help="Print the architecture for a board (ARCH=)")
+    parser.add_argument('-r', '--reproducible-builds', action='store_true',
           help='Set SOURCE_DATE_EPOCH=0 to suuport a reproducible build')
-    parser.add_option('-R', '--regen-board-list', action='store_true',
+    parser.add_argument('-R', '--regen-board-list', type=str,
           help='Force regeneration of the list of boards, like the old boards.cfg file')
-    parser.add_option('-s', '--summary', action='store_true',
+    parser.add_argument('-s', '--summary', action='store_true',
           default=False, help='Show a build summary')
-    parser.add_option('-S', '--show-sizes', action='store_true',
+    parser.add_argument('-S', '--show-sizes', action='store_true',
           default=False, help='Show image size variation in summary')
-    parser.add_option('--step', type='int',
+    parser.add_argument('--step', type=int,
           default=1, help='Only build every n commits (0=just first and last)')
     if HAS_TESTS:
-        parser.add_option('--skip-net-tests', action='store_true', default=False,
+        parser.add_argument('--skip-net-tests', action='store_true', default=False,
                           help='Skip tests which need the network')
-        parser.add_option('-t', '--test', action='store_true', dest='test',
+        parser.add_argument('-t', '--test', action='store_true', dest='test',
                           default=False, help='run tests')
-    parser.add_option('-T', '--threads', type='int',
+        parser.add_argument('--coverage', action='store_true',
+                            help='Calculated test coverage')
+    parser.add_argument('-T', '--threads', type=int,
           default=None,
           help='Number of builder threads to use (0=single-thread)')
-    parser.add_option('-u', '--show_unknown', action='store_true',
+    parser.add_argument('-u', '--show_unknown', action='store_true',
           default=False, help='Show boards with unknown build result')
-    parser.add_option('-U', '--show-environment', action='store_true',
+    parser.add_argument('-U', '--show-environment', action='store_true',
           default=False, help='Show environment changes in summary')
-    parser.add_option('-v', '--verbose', action='store_true',
+    parser.add_argument('-v', '--verbose', action='store_true',
           default=False, help='Show build results while the build progresses')
-    parser.add_option('-V', '--verbose-build', action='store_true',
+    parser.add_argument('-V', '--verbose-build', action='store_true',
           default=False, help='Run make with V=1, logging all output')
-    parser.add_option('-w', '--work-in-output', action='store_true',
+    parser.add_argument('-w', '--work-in-output', action='store_true',
           default=False, help='Use the output directory as the work directory')
-    parser.add_option('-W', '--ignore-warnings', action='store_true',
+    parser.add_argument('-W', '--ignore-warnings', action='store_true',
           default=False, help='Return success even if there are warnings')
-    parser.add_option('-x', '--exclude', dest='exclude',
-          type='string', action='append',
+    parser.add_argument('-x', '--exclude', dest='exclude',
+          type=str, action='append',
           help='Specify a list of boards to exclude, separated by comma')
-    parser.add_option('-y', '--filter-dtb-warnings', action='store_true',
+    parser.add_argument('-y', '--filter-dtb-warnings', action='store_true',
           default=False,
           help='Filter out device-tree-compiler warnings from output')
-    parser.add_option('-Y', '--filter-migration-warnings', action='store_true',
+    parser.add_argument('-Y', '--filter-migration-warnings', action='store_true',
           default=False,
           help='Filter out migration warnings from output')
 
-    parser.usage += """ [list of target/arch/cpu/board/vendor/soc to build]
+
+def parse_args():
+    """Parse command line arguments from sys.argv[]
+
+    Returns:
+        tuple containing:
+            options: command line options
+            args: command lin arguments
+    """
+    epilog = """ [list of target/arch/cpu/board/vendor/soc to build]
 
     Build U-Boot for all commits in a branch. Use -n to do a dry run"""
 
+    parser = argparse.ArgumentParser(epilog=epilog)
+    add_upto_m(parser)
+    add_after_m(parser)
+    parser.add_argument('terms', type=str, nargs='*',
+                        help='Board / SoC names to build')
+
     return parser.parse_args()
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 09a11f25b3..f2ffb7f5b4 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -2,15 +2,14 @@
 # Copyright (c) 2013 The Chromium OS Authors.
 #
 
+"""Control module for buildman
+
+This holds the main control logic for buildman, when not running tests.
+"""
+
 import multiprocessing
-try:
-    import importlib.resources
-except ImportError:
-    # for Python 3.6
-    import importlib_resources
 import os
 import shutil
-import subprocess
 import sys
 
 from buildman import boards
@@ -22,34 +21,58 @@ from patman import gitutil
 from patman import patchstream
 from u_boot_pylib import command
 from u_boot_pylib import terminal
-from u_boot_pylib import tools
 from u_boot_pylib.terminal import tprint
 
-def GetPlural(count):
+TEST_BUILDER = None
+
+def get_plural(count):
     """Returns a plural 's' if count is not 1"""
     return 's' if count != 1 else ''
 
-def GetActionSummary(is_summary, commits, selected, options):
-    """Return a string summarising the intended action.
+
+def count_build_commits(commits, step):
+    """Calculate the number of commits to be built
+
+    Args:
+        commits (list of Commit): Commits to build or None
+        step (int): Step value for commits, typically 1
 
     Returns:
-        Summary string.
+        Number of commits that will be built
     """
     if commits:
         count = len(commits)
-        count = (count + options.step - 1) // options.step
-        commit_str = '%d commit%s' % (count, GetPlural(count))
+        return (count + step - 1) // step
+    return 0
+
+
+def get_action_summary(is_summary, commit_count, selected, threads, jobs):
+    """Return a string summarising the intended action.
+
+    Args:
+        is_summary (bool): True if this is a summary (otherwise it is building)
+        commits (list): List of commits being built
+        selected (list of Board): List of Board objects that are marked
+        step (int): Step increment through commits
+        threads (int): Number of processor threads being used
+        jobs (int): Number of jobs to build at once
+
+    Returns:
+        Summary string.
+    """
+    if commit_count:
+        commit_str = f'{commit_count} commit{get_plural(commit_count)}'
     else:
         commit_str = 'current source'
-    str = '%s %s for %d boards' % (
-        'Summary of' if is_summary else 'Building', commit_str,
-        len(selected))
-    str += ' (%d thread%s, %d job%s per thread)' % (options.threads,
-            GetPlural(options.threads), options.jobs, GetPlural(options.jobs))
-    return str
-
-def ShowActions(series, why_selected, boards_selected, builder, options,
-                board_warnings):
+    msg = (f"{'Summary of' if is_summary else 'Building'} "
+           f'{commit_str} for {len(selected)} boards')
+    msg += (f' ({threads} thread{get_plural(threads)}, '
+            f'{jobs} job{get_plural(jobs)} per thread)')
+    return msg
+
+# pylint: disable=R0913
+def show_actions(series, why_selected, boards_selected, output_dir,
+                 board_warnings, step, threads, jobs, verbose):
     """Display a list of actions that we would take, if not a dry run.
 
     Args:
@@ -61,9 +84,12 @@ def ShowActions(series, why_selected, boards_selected, builder, options,
                 the value would be a list of board names.
         boards_selected: Dict of selected boards, key is target name,
                 value is Board object
-        builder: The builder that will be used to build the commits
-        options: Command line options object
+        output_dir (str): Output directory for builder
         board_warnings: List of warnings obtained from board selected
+        step (int): Step increment through commits
+        threads (int): Number of processor threads being used
+        jobs (int): Number of jobs to build at once
+        verbose (bool): True to indicate why each board was selected
     """
     col = terminal.Color()
     print('Dry run, so not doing much. But I would do this:')
@@ -72,27 +98,27 @@ def ShowActions(series, why_selected, boards_selected, builder, options,
         commits = series.commits
     else:
         commits = None
-    print(GetActionSummary(False, commits, boards_selected,
-            options))
-    print('Build directory: %s' % builder.base_dir)
+    print(get_action_summary(False, count_build_commits(commits, step),
+                             boards_selected, threads, jobs))
+    print(f'Build directory: {output_dir}')
     if commits:
-        for upto in range(0, len(series.commits), options.step):
+        for upto in range(0, len(series.commits), step):
             commit = series.commits[upto]
             print('   ', col.build(col.YELLOW, commit.hash[:8], bright=False), end=' ')
             print(commit.subject)
     print()
     for arg in why_selected:
         if arg != 'all':
-            print(arg, ': %d boards' % len(why_selected[arg]))
-            if options.verbose:
-                print('   %s' % ' '.join(why_selected[arg]))
-    print(('Total boards to build for each commit: %d\n' %
-            len(why_selected['all'])))
+            print(arg, f': {len(why_selected[arg])} boards')
+            if verbose:
+                print(f"   {' '.join(why_selected[arg])}")
+    print('Total boards to build for each '
+          f"commit: {len(why_selected['all'])}\n")
     if board_warnings:
         for warning in board_warnings:
             print(col.build(col.YELLOW, warning))
 
-def ShowToolchainPrefix(brds, toolchains):
+def show_toolchain_prefix(brds, toolchains):
     """Show information about a the tool chain used by one or more boards
 
     The function checks that all boards use the same toolchain, then prints
@@ -110,15 +136,48 @@ def ShowToolchainPrefix(brds, toolchains):
     for brd in board_selected.values():
         tc_set.add(toolchains.Select(brd.arch))
     if len(tc_set) != 1:
-        return 'Supplied boards must share one toolchain'
-        return False
-    tc = tc_set.pop()
-    print(tc.GetEnvArgs(toolchain.VAR_CROSS_COMPILE))
-    return None
+        sys.exit('Supplied boards must share one toolchain')
+    tchain = tc_set.pop()
+    print(tchain.GetEnvArgs(toolchain.VAR_CROSS_COMPILE))
+
+def show_arch(brds):
+    """Show information about a the architecture used by one or more boards
+
+    The function checks that all boards use the same architecture, then prints
+    the correct value for ARCH.
+
+    Args:
+        boards: Boards object containing selected boards
+
+    Return:
+        None on success, string error message otherwise
+    """
+    board_selected = brds.get_selected_dict()
+    arch_set = set()
+    for brd in board_selected.values():
+        arch_set.add(brd.arch)
+    if len(arch_set) != 1:
+        sys.exit('Supplied boards must share one arch')
+    print(arch_set.pop())
 
 def get_allow_missing(opt_allow, opt_no_allow, num_selected, has_branch):
+    """Figure out whether to allow external blobs
+
+    Uses the allow-missing setting and the provided arguments to decide whether
+    missing external blobs should be allowed
+
+    Args:
+        opt_allow (bool): True if --allow-missing flag is set
+        opt_no_allow (bool): True if --no-allow-missing flag is set
+        num_selected (int): Number of selected board
+        has_branch (bool): True if a git branch (to build) has been provided
+
+    Returns:
+        bool: True to allow missing external blobs, False to produce an error if
+            external blobs are used
+    """
     allow_missing = False
-    am_setting = bsettings.GetGlobalItemValue('allow-missing')
+    am_setting = bsettings.get_global_item_value('allow-missing')
     if am_setting:
         if am_setting == 'always':
             allow_missing = True
@@ -133,142 +192,82 @@ def get_allow_missing(opt_allow, opt_no_allow, num_selected, has_branch):
         allow_missing = False
     return allow_missing
 
-def DoBuildman(options, args, toolchains=None, make_func=None, brds=None,
-               clean_dir=False, test_thread_exceptions=False):
-    """The main control code for buildman
-
-    Args:
-        options: Command line options object
-        args: Command line arguments (list of strings)
-        toolchains: Toolchains to use - this should be a Toolchains()
-                object. If None, then it will be created and scanned
-        make_func: Make function to use for the builder. This is called
-                to execute 'make'. If this is None, the normal function
-                will be used, which calls the 'make' tool with suitable
-                arguments. This setting is useful for tests.
-        brds: Boards() object to use, containing a list of available
-                boards. If this is None it will be created and scanned.
-        clean_dir: Used for tests only, indicates that the existing output_dir
-            should be removed before starting the build
-        test_thread_exceptions: Uses for tests only, True to make the threads
-            raise an exception instead of reporting their result. This simulates
-            a failure in the code somewhere
-    """
-    global builder
-
-    if options.full_help:
-        with importlib.resources.path('buildman', 'README.rst') as readme:
-            tools.print_full_help(str(readme))
-        return 0
-
-    gitutil.setup()
-    col = terminal.Color()
-
-    options.git_dir = os.path.join(options.git, '.git')
-
-    no_toolchains = toolchains is None
-    if no_toolchains:
-        toolchains = toolchain.Toolchains(options.override_toolchain)
-
-    if options.fetch_arch:
-        if options.fetch_arch == 'list':
-            sorted_list = toolchains.ListArchs()
-            print(col.build(col.BLUE, 'Available architectures: %s\n' %
-                            ' '.join(sorted_list)))
-            return 0
-        else:
-            fetch_arch = options.fetch_arch
-            if fetch_arch == 'all':
-                fetch_arch = ','.join(toolchains.ListArchs())
-                print(col.build(col.CYAN, '\nDownloading toolchains: %s' %
-                                fetch_arch))
-            for arch in fetch_arch.split(','):
-                print()
-                ret = toolchains.FetchAndInstall(arch)
-                if ret:
-                    return ret
-            return 0
-
-    if no_toolchains:
-        toolchains.GetSettings()
-        toolchains.Scan(options.list_tool_chains and options.verbose)
-    if options.list_tool_chains:
-        toolchains.List()
-        print()
-        return 0
-
-    if not options.output_dir:
-        if options.work_in_output:
-            sys.exit(col.build(col.RED, '-w requires that you specify -o'))
-        options.output_dir = '..'
-
-    # Work out what subset of the boards we are building
-    if not brds:
-        if not os.path.exists(options.output_dir):
-            os.makedirs(options.output_dir)
-        board_file = os.path.join(options.output_dir, 'boards.cfg')
-
-        brds = boards.Boards()
-        ok = brds.ensure_board_list(board_file,
-                                    options.threads or multiprocessing.cpu_count(),
-                                    force=options.regen_board_list,
-                                    quiet=not options.verbose)
-        if options.regen_board_list:
-            return 0 if ok else 2
-        brds.read_boards(board_file)
-
-    exclude = []
-    if options.exclude:
-        for arg in options.exclude:
-            exclude += arg.split(',')
 
-    if options.boards:
-        requested_boards = []
-        for b in options.boards:
-            requested_boards += b.split(',')
-    else:
-        requested_boards = None
-    why_selected, board_warnings = brds.select_boards(args, exclude,
-                                                      requested_boards)
-    selected = brds.get_selected()
-    if not len(selected):
-        sys.exit(col.build(col.RED, 'No matching boards found'))
+def count_commits(branch, count, col, git_dir):
+    """Could the number of commits in the branch/ranch being built
 
-    if options.print_prefix:
-        err = ShowToolchainPrefix(brds, toolchains)
-        if err:
-            sys.exit(col.build(col.RED, err))
-        return 0
+    Args:
+        branch (str): Name of branch to build, or None if none
+        count (int): Number of commits to build, or -1 for all
+        col (Terminal.Color): Color object to use
+        git_dir (str): Git directory to use, e.g. './.git'
 
-    # Work out how many commits to build. We want to build everything on the
-    # branch. We also build the upstream commit as a control so we can see
-    # problems introduced by the first commit on the branch.
-    count = options.count
-    has_range = options.branch and '..' in options.branch
+    Returns:
+        tuple:
+            Number of commits being built
+            True if the 'branch' string contains a range rather than a simple
+                name
+    """
+    has_range = branch and '..' in branch
     if count == -1:
-        if not options.branch:
+        if not branch:
             count = 1
         else:
             if has_range:
-                count, msg = gitutil.count_commits_in_range(options.git_dir,
-                                                         options.branch)
+                count, msg = gitutil.count_commits_in_range(git_dir, branch)
             else:
-                count, msg = gitutil.count_commits_in_branch(options.git_dir,
-                                                          options.branch)
+                count, msg = gitutil.count_commits_in_branch(git_dir, branch)
             if count is None:
                 sys.exit(col.build(col.RED, msg))
             elif count == 0:
-                sys.exit(col.build(col.RED, "Range '%s' has no commits" %
-                                   options.branch))
+                sys.exit(col.build(col.RED,
+                                   f"Range '{branch}' has no commits"))
             if msg:
                 print(col.build(col.YELLOW, msg))
             count += 1   # Build upstream commit also
 
     if not count:
-        msg = ("No commits found to process in branch '%s': "
-               "set branch's upstream or use -c flag" % options.branch)
+        msg = (f"No commits found to process in branch '{branch}': "
+               "set branch's upstream or use -c flag")
         sys.exit(col.build(col.RED, msg))
-    if options.work_in_output:
+    return count, has_range
+
+
+def determine_series(selected, col, git_dir, count, branch, work_in_output):
+    """Determine the series which is to be built, if any
+
+    If there is a series, the commits in that series are numbered by setting
+    their sequence value (starting from 0). This is used by tests.
+
+    Args:
+        selected (list of Board): List of Board objects that are marked
+            selected
+        col (Terminal.Color): Color object to use
+        git_dir (str): Git directory to use, e.g. './.git'
+        count (int): Number of commits in branch
+        branch (str): Name of branch to build, or None if none
+        work_in_output (bool): True to work in the output directory
+
+    Returns:
+        Series: Series to build, or None for none
+
+    Read the metadata from the commits. First look at the upstream commit,
+    then the ones in the branch. We would like to do something like
+    upstream/master~..branch but that isn't possible if upstream/master is
+    a merge commit (it will list all the commits that form part of the
+    merge)
+
+    Conflicting tags are not a problem for buildman, since it does not use
+    them. For example, Series-version is not useful for buildman. On the
+    other hand conflicting tags will cause an error. So allow later tags
+    to overwrite earlier ones by setting allow_overwrite=True
+    """
+
+    # Work out how many commits to build. We want to build everything on the
+    # branch. We also build the upstream commit as a control so we can see
+    # problems introduced by the first commit on the branch.
+    count, has_range = count_commits(branch, count, col, git_dir)
+    if work_in_output:
         if len(selected) != 1:
             sys.exit(col.build(col.RED,
                                '-w can only be used with a single board'))
@@ -276,141 +275,405 @@ def DoBuildman(options, args, toolchains=None, make_func=None, brds=None,
             sys.exit(col.build(col.RED,
                                '-w can only be used with a single commit'))
 
-    # Read the metadata from the commits. First look at the upstream commit,
-    # then the ones in the branch. We would like to do something like
-    # upstream/master~..branch but that isn't possible if upstream/master is
-    # a merge commit (it will list all the commits that form part of the
-    # merge)
-    # Conflicting tags are not a problem for buildman, since it does not use
-    # them. For example, Series-version is not useful for buildman. On the
-    # other hand conflicting tags will cause an error. So allow later tags
-    # to overwrite earlier ones by setting allow_overwrite=True
-    if options.branch:
+    if branch:
         if count == -1:
             if has_range:
-                range_expr = options.branch
+                range_expr = branch
             else:
-                range_expr = gitutil.get_range_in_branch(options.git_dir,
-                                                      options.branch)
-            upstream_commit = gitutil.get_upstream(options.git_dir,
-                                                  options.branch)
+                range_expr = gitutil.get_range_in_branch(git_dir, branch)
+            upstream_commit = gitutil.get_upstream(git_dir, branch)
             series = patchstream.get_metadata_for_list(upstream_commit,
-                options.git_dir, 1, series=None, allow_overwrite=True)
+                git_dir, 1, series=None, allow_overwrite=True)
 
             series = patchstream.get_metadata_for_list(range_expr,
-                    options.git_dir, None, series, allow_overwrite=True)
+                    git_dir, None, series, allow_overwrite=True)
         else:
             # Honour the count
-            series = patchstream.get_metadata_for_list(options.branch,
-                    options.git_dir, count, series=None, allow_overwrite=True)
+            series = patchstream.get_metadata_for_list(branch,
+                    git_dir, count, series=None, allow_overwrite=True)
+
+        # Number the commits for test purposes
+        for i, commit in enumerate(series.commits):
+            commit.sequence = i
     else:
         series = None
-        if not options.dry_run:
-            options.verbose = True
-            if not options.summary:
-                options.show_errors = True
+    return series
+
+
+def do_fetch_arch(toolchains, col, fetch_arch):
+    """Handle the --fetch-arch option
+
+    Args:
+        toolchains (Toolchains): Tool chains to use
+        col (terminal.Color): Color object to build
+        fetch_arch (str): Argument passed to the --fetch-arch option
+
+    Returns:
+        int: Return code for buildman
+    """
+    if fetch_arch == 'list':
+        sorted_list = toolchains.ListArchs()
+        print(col.build(
+            col.BLUE,
+            f"Available architectures: {' '.join(sorted_list)}\n"))
+        return 0
+
+    if fetch_arch == 'all':
+        fetch_arch = ','.join(toolchains.ListArchs())
+        print(col.build(col.CYAN,
+                        f'\nDownloading toolchains: {fetch_arch}'))
+    for arch in fetch_arch.split(','):
+        print()
+        ret = toolchains.FetchAndInstall(arch)
+        if ret:
+            return ret
+    return 0
+
+
+def get_toolchains(toolchains, col, override_toolchain, fetch_arch,
+                   list_tool_chains, verbose):
+    """Get toolchains object to use
+
+    Args:
+        toolchains (Toolchains or None): Toolchains to use. If None, then a
+            Toolchains object will be created and scanned
+        col (Terminal.Color): Color object
+        override_toolchain (str or None): Override value for toolchain, or None
+        fetch_arch (bool): True to fetch the toolchain for the architectures
+        list_tool_chains (bool): True to list all tool chains
+        verbose (bool): True for verbose output when listing toolchains
+
+    Returns:
+        Either:
+            int: Operation completed and buildman should exit with exit code
+            Toolchains: Toolchains object to use
+    """
+    no_toolchains = toolchains is None
+    if no_toolchains:
+        toolchains = toolchain.Toolchains(override_toolchain)
+
+    if fetch_arch:
+        return do_fetch_arch(toolchains, col, fetch_arch)
+
+    if no_toolchains:
+        toolchains.GetSettings()
+        toolchains.Scan(list_tool_chains and verbose)
+    if list_tool_chains:
+        toolchains.List()
+        print()
+        return 0
+    return toolchains
+
+
+def get_boards_obj(output_dir, regen_board_list, maintainer_check, full_check,
+                   threads, verbose):
+    """Object the Boards object to use
+
+    Creates the output directory and ensures there is a boards.cfg file, then
+    read it in.
+
+    Args:
+        output_dir (str): Output directory to use
+        regen_board_list (bool): True to just regenerate the board list
+        maintainer_check (bool): True to just run a maintainer check
+        full_check (bool): True to just run a full check of Kconfig and
+            maintainers
+        threads (int or None): Number of threads to use to create boards file
+        verbose (bool): False to suppress output from boards-file generation
+
+    Returns:
+        Either:
+            int: Operation completed and buildman should exit with exit code
+            Boards: Boards object to use
+    """
+    brds = boards.Boards()
+    nr_cpus = threads or multiprocessing.cpu_count()
+    if maintainer_check or full_check:
+        warnings = brds.build_board_list(jobs=nr_cpus,
+                                         warn_targets=full_check)[1]
+        if warnings:
+            for warn in warnings:
+                print(warn, file=sys.stderr)
+            return 2
+        return 0
+
+    if not os.path.exists(output_dir):
+        os.makedirs(output_dir)
+    board_file = os.path.join(output_dir, 'boards.cfg')
+    if regen_board_list and regen_board_list != '-':
+        board_file = regen_board_list
+
+    okay = brds.ensure_board_list(board_file, nr_cpus, force=regen_board_list,
+                                  quiet=not verbose)
+    if regen_board_list:
+        return 0 if okay else 2
+    brds.read_boards(board_file)
+    return brds
+
+
+def determine_boards(brds, args, col, opt_boards, exclude_list):
+    """Determine which boards to build
+
+    Each element of args and exclude can refer to a board name, arch or SoC
+
+    Args:
+        brds (Boards): Boards object
+        args (list of str): Arguments describing boards to build
+        col (Terminal.Color): Color object
+        opt_boards (list of str): Specific boards to build, or None for all
+        exclude_list (list of str): Arguments describing boards to exclude
+
+    Returns:
+        tuple:
+            list of Board: List of Board objects that are marked selected
+            why_selected: Dictionary where each key is a buildman argument
+                    provided by the user, and the value is the list of boards
+                    brought in by that argument. For example, 'arm' might bring
+                    in 400 boards, so in this case the key would be 'arm' and
+                    the value would be a list of board names.
+            board_warnings: List of warnings obtained from board selected
+    """
+    exclude = []
+    if exclude_list:
+        for arg in exclude_list:
+            exclude += arg.split(',')
+
+    if opt_boards:
+        requested_boards = []
+        for brd in opt_boards:
+            requested_boards += brd.split(',')
+    else:
+        requested_boards = None
+    why_selected, board_warnings = brds.select_boards(args, exclude,
+                                                      requested_boards)
+    selected = brds.get_selected()
+    if not selected:
+        sys.exit(col.build(col.RED, 'No matching boards found'))
+    return selected, why_selected, board_warnings
+
+
+def adjust_args(args, series, selected):
+    """Adjust arguments according to various constraints
+
+    Updates verbose, show_errors, threads, jobs and step
+
+    Args:
+        args (Namespace): Namespace object to adjust
+        series (Series): Series being built / summarised
+        selected (list of Board): List of Board objects that are marked
+    """
+    if not series and not args.dry_run:
+        args.verbose = True
+        if not args.summary:
+            args.show_errors = True
 
     # By default we have one thread per CPU. But if there are not enough jobs
     # we can have fewer threads and use a high '-j' value for make.
-    if options.threads is None:
-        options.threads = min(multiprocessing.cpu_count(), len(selected))
-    if not options.jobs:
-        options.jobs = max(1, (multiprocessing.cpu_count() +
+    if args.threads is None:
+        args.threads = min(multiprocessing.cpu_count(), len(selected))
+    if not args.jobs:
+        args.jobs = max(1, (multiprocessing.cpu_count() +
                 len(selected) - 1) // len(selected))
 
-    if not options.step:
-        options.step = len(series.commits) - 1
+    if not args.step:
+        args.step = len(series.commits) - 1
 
-    gnu_make = command.output(os.path.join(options.git,
-            'scripts/show-gnu-make'), raise_on_error=False).rstrip()
-    if not gnu_make:
-        sys.exit('GNU Make not found')
+    # We can't show function sizes without board details at present
+    if args.show_bloat:
+        args.show_detail = True
 
-    allow_missing = get_allow_missing(options.allow_missing,
-                                      options.no_allow_missing, len(selected),
-                                      options.branch)
 
-    # Create a new builder with the selected options.
-    output_dir = options.output_dir
-    if options.branch:
-        dirname = options.branch.replace('/', '_')
+def setup_output_dir(output_dir, work_in_output, branch, no_subdirs, col,
+                     clean_dir):
+    """Set up the output directory
+
+    Args:
+        output_dir (str): Output directory provided by the user, or None if none
+        work_in_output (bool): True to work in the output directory
+        branch (str): Name of branch to build, or None if none
+        no_subdirs (bool): True to put the output in the top-level output dir
+        clean_dir: Used for tests only, indicates that the existing output_dir
+            should be removed before starting the build
+
+    Returns:
+        str: Updated output directory pathname
+    """
+    if not output_dir:
+        if work_in_output:
+            sys.exit(col.build(col.RED, '-w requires that you specify -o'))
+        output_dir = '..'
+    if branch and not no_subdirs:
         # As a special case allow the board directory to be placed in the
         # output directory itself rather than any subdirectory.
-        if not options.no_subdirs:
-            output_dir = os.path.join(options.output_dir, dirname)
+        dirname = branch.replace('/', '_')
+        output_dir = os.path.join(output_dir, dirname)
         if clean_dir and os.path.exists(output_dir):
             shutil.rmtree(output_dir)
-    adjust_cfg = cfgutil.convert_list_to_dict(options.adjust_cfg)
+    return output_dir
+
+
+def run_builder(builder, commits, board_selected, args):
+    """Run the builder or show the summary
+
+    Args:
+        commits (list of Commit): List of commits being built, None if no branch
+        boards_selected (dict): Dict of selected boards:
+            key: target name
+            value: Board object
+        args (Namespace): Namespace to use
+
+    Returns:
+        int: Return code for buildman
+    """
+    gnu_make = command.output(os.path.join(args.git,
+            'scripts/show-gnu-make'), raise_on_error=False).rstrip()
+    if not gnu_make:
+        sys.exit('GNU Make not found')
+    builder.gnu_make = gnu_make
+
+    if not args.ide:
+        commit_count = count_build_commits(commits, args.step)
+        tprint(get_action_summary(args.summary, commit_count, board_selected,
+                                  args.threads, args.jobs))
+
+    builder.set_display_options(
+        args.show_errors, args.show_sizes, args.show_detail, args.show_bloat,
+        args.list_error_boards, args.show_config, args.show_environment,
+        args.filter_dtb_warnings, args.filter_migration_warnings, args.ide)
+    if args.summary:
+        builder.show_summary(commits, board_selected)
+    else:
+        fail, warned, excs = builder.build_boards(
+            commits, board_selected, args.keep_outputs, args.verbose)
+        if excs:
+            return 102
+        if fail:
+            return 100
+        if warned and not args.ignore_warnings:
+            return 101
+    return 0
+
+
+def calc_adjust_cfg(adjust_cfg, reproducible_builds):
+    """Calculate the value to use for adjust_cfg
+
+    Args:
+        adjust_cfg (list of str): List of configuration changes. See cfgutil for
+            details
+        reproducible_builds (bool): True to adjust the configuration to get
+            reproduceable builds
+
+    Returns:
+        adjust_cfg (list of str): List of configuration changes
+    """
+    adjust_cfg = cfgutil.convert_list_to_dict(adjust_cfg)
 
     # Drop LOCALVERSION_AUTO since it changes the version string on every commit
-    if options.reproducible_builds:
+    if reproducible_builds:
         # If these are mentioned, leave the local version alone
         if 'LOCALVERSION' in adjust_cfg or 'LOCALVERSION_AUTO' in adjust_cfg:
             print('Not dropping LOCALVERSION_AUTO for reproducible build')
         else:
             adjust_cfg['LOCALVERSION_AUTO'] = '~'
+    return adjust_cfg
 
-    builder = Builder(toolchains, output_dir, options.git_dir,
-            options.threads, options.jobs, gnu_make=gnu_make, checkout=True,
-            show_unknown=options.show_unknown, step=options.step,
-            no_subdirs=options.no_subdirs, full_path=options.full_path,
-            verbose_build=options.verbose_build,
-            mrproper=options.mrproper,
-            per_board_out_dir=options.per_board_out_dir,
-            config_only=options.config_only,
-            squash_config_y=not options.preserve_config_y,
-            warnings_as_errors=options.warnings_as_errors,
-            work_in_output=options.work_in_output,
-            test_thread_exceptions=test_thread_exceptions,
-            adjust_cfg=adjust_cfg,
-            allow_missing=allow_missing, no_lto=options.no_lto,
-            reproducible_builds=options.reproducible_builds)
-    builder.force_config_on_failure = not options.quick
-    if make_func:
-        builder.do_make = make_func
+
+def do_buildman(args, toolchains=None, make_func=None, brds=None,
+                clean_dir=False, test_thread_exceptions=False):
+    """The main control code for buildman
+
+    Args:
+        args: ArgumentParser object
+        args: Command line arguments (list of strings)
+        toolchains: Toolchains to use - this should be a Toolchains()
+                object. If None, then it will be created and scanned
+        make_func: Make function to use for the builder. This is called
+                to execute 'make'. If this is None, the normal function
+                will be used, which calls the 'make' tool with suitable
+                arguments. This setting is useful for tests.
+        brds: Boards() object to use, containing a list of available
+                boards. If this is None it will be created and scanned.
+        clean_dir: Used for tests only, indicates that the existing output_dir
+            should be removed before starting the build
+        test_thread_exceptions: Uses for tests only, True to make the threads
+            raise an exception instead of reporting their result. This simulates
+            a failure in the code somewhere
+    """
+    # Used so testing can obtain the builder: pylint: disable=W0603
+    global TEST_BUILDER
+
+    gitutil.setup()
+    col = terminal.Color()
+
+    git_dir = os.path.join(args.git, '.git')
+
+    toolchains = get_toolchains(toolchains, col, args.override_toolchain,
+                                args.fetch_arch, args.list_tool_chains,
+                                args.verbose)
+    if isinstance(toolchains, int):
+        return toolchains
+
+    output_dir = setup_output_dir(
+        args.output_dir, args.work_in_output, args.branch,
+        args.no_subdirs, col, clean_dir)
+
+    # Work out what subset of the boards we are building
+    if not brds:
+        brds = get_boards_obj(output_dir, args.regen_board_list,
+                              args.maintainer_check, args.full_check,
+                              args.threads, args.verbose)
+        if isinstance(brds, int):
+            return brds
+
+    selected, why_selected, board_warnings = determine_boards(
+        brds, args.terms, col, args.boards, args.exclude)
+
+    if args.print_prefix:
+        show_toolchain_prefix(brds, toolchains)
+        return 0
+
+    if args.print_arch:
+        show_arch(brds)
+        return 0
+
+    series = determine_series(selected, col, git_dir, args.count,
+                              args.branch, args.work_in_output)
+
+    adjust_args(args, series, selected)
 
     # For a dry run, just show our actions as a sanity check
-    if options.dry_run:
-        ShowActions(series, why_selected, selected, builder, options,
-                    board_warnings)
-    else:
-        builder.force_build = options.force_build
-        builder.force_build_failures = options.force_build_failures
-        builder.force_reconfig = options.force_reconfig
-        builder.in_tree = options.in_tree
-
-        # Work out which boards to build
-        board_selected = brds.get_selected_dict()
-
-        if series:
-            commits = series.commits
-            # Number the commits for test purposes
-            for commit in range(len(commits)):
-                commits[commit].sequence = commit
-        else:
-            commits = None
-
-        if not options.ide:
-            tprint(GetActionSummary(options.summary, commits, board_selected,
-                                    options))
-
-        # We can't show function sizes without board details at present
-        if options.show_bloat:
-            options.show_detail = True
-        builder.SetDisplayOptions(
-            options.show_errors, options.show_sizes, options.show_detail,
-            options.show_bloat, options.list_error_boards, options.show_config,
-            options.show_environment, options.filter_dtb_warnings,
-            options.filter_migration_warnings, options.ide)
-        if options.summary:
-            builder.ShowSummary(commits, board_selected)
-        else:
-            fail, warned, excs = builder.BuildBoards(
-                commits, board_selected, options.keep_outputs, options.verbose)
-            if excs:
-                return 102
-            elif fail:
-                return 100
-            elif warned and not options.ignore_warnings:
-                return 101
-    return 0
+    if args.dry_run:
+        show_actions(series, why_selected, selected, output_dir, board_warnings,
+                     args.step, args.threads, args.jobs,
+                     args.verbose)
+        return 0
+
+    # Create a new builder with the selected args
+    builder = Builder(toolchains, output_dir, git_dir,
+            args.threads, args.jobs, checkout=True,
+            show_unknown=args.show_unknown, step=args.step,
+            no_subdirs=args.no_subdirs, full_path=args.full_path,
+            verbose_build=args.verbose_build,
+            mrproper=args.mrproper,
+            per_board_out_dir=args.per_board_out_dir,
+            config_only=args.config_only,
+            squash_config_y=not args.preserve_config_y,
+            warnings_as_errors=args.warnings_as_errors,
+            work_in_output=args.work_in_output,
+            test_thread_exceptions=test_thread_exceptions,
+            adjust_cfg=calc_adjust_cfg(args.adjust_cfg,
+                                       args.reproducible_builds),
+            allow_missing=get_allow_missing(args.allow_missing,
+                                            args.no_allow_missing,
+                                            len(selected), args.branch),
+            no_lto=args.no_lto,
+            reproducible_builds=args.reproducible_builds,
+            force_build = args.force_build,
+            force_build_failures = args.force_build_failures,
+            force_reconfig = args.force_reconfig, in_tree = args.in_tree,
+            force_config_on_failure=not args.quick, make_func=make_func)
+
+    TEST_BUILDER = builder
+
+    return run_builder(builder, series.commits if series else None,
+                       brds.get_selected_dict(), args)
diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py
index ebd78f225e..55dd494fe8 100644
--- a/tools/buildman/func_test.py
+++ b/tools/buildman/func_test.py
@@ -3,9 +3,11 @@
 #
 
 import os
+from pathlib import Path
 import shutil
 import sys
 import tempfile
+import time
 import unittest
 
 from buildman import board
@@ -38,8 +40,8 @@ chromeos_peach=VBOOT=${chroot}/build/peach_pit/usr ${vboot}
 '''
 
 BOARDS = [
-    ['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 1', 'board0',  ''],
-    ['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 2', 'board1', ''],
+    ['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 0', 'board0',  ''],
+    ['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 1', 'board1', ''],
     ['Active', 'powerpc', 'powerpc', '', 'Tester', 'PowerPC board 1', 'board2', ''],
     ['Active', 'sandbox', 'sandbox', '', 'Tester', 'Sandbox board', 'board4', ''],
 ]
@@ -184,8 +186,8 @@ class TestFunctional(unittest.TestCase):
         self._buildman_pathname = sys.argv[0]
         self._buildman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
         command.test_result = self._HandleCommand
-        bsettings.Setup(None)
-        bsettings.AddFile(settings_data)
+        bsettings.setup(None)
+        bsettings.add_file(settings_data)
         self.setupToolchains()
         self._toolchains.Add('arm-gcc', test=False)
         self._toolchains.Add('powerpc-gcc', test=False)
@@ -209,6 +211,12 @@ class TestFunctional(unittest.TestCase):
         # Set to True to report missing blobs
         self._missing = False
 
+        self._buildman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
+        self._test_dir = os.path.join(self._buildman_dir, 'test')
+
+        # Set up some fake source files
+        shutil.copytree(self._test_dir, self._git_dir)
+
         # Avoid sending any output and clear all terminal output
         terminal.set_print_test_mode()
         terminal.get_print_test_lines()
@@ -225,29 +233,34 @@ class TestFunctional(unittest.TestCase):
         return command.run_pipe([[self._buildman_pathname] + list(args)],
                 capture=True, capture_stderr=True)
 
-    def _RunControl(self, *args, brds=None, clean_dir=False,
-                    test_thread_exceptions=False):
+    def _RunControl(self, *args, brds=False, clean_dir=False,
+                    test_thread_exceptions=False, get_builder=True):
         """Run buildman
 
         Args:
             args: List of arguments to pass
-            brds: Boards object
+            brds: Boards object, or False to pass self._boards, or None to pass
+                None
             clean_dir: Used for tests only, indicates that the existing output_dir
                 should be removed before starting the build
             test_thread_exceptions: Uses for tests only, True to make the threads
                 raise an exception instead of reporting their result. This simulates
                 a failure in the code somewhere
+            get_builder (bool): Set self._builder to the resulting builder
 
         Returns:
             result code from buildman
         """
         sys.argv = [sys.argv[0]] + list(args)
-        options, args = cmdline.ParseArgs()
-        result = control.DoBuildman(options, args, toolchains=self._toolchains,
-                make_func=self._HandleMake, brds=brds or self._boards,
-                clean_dir=clean_dir,
-                test_thread_exceptions=test_thread_exceptions)
-        self._builder = control.builder
+        args = cmdline.parse_args()
+        if brds == False:
+            brds = self._boards
+        result = control.do_buildman(
+            args, toolchains=self._toolchains, make_func=self._HandleMake,
+            brds=brds, clean_dir=clean_dir,
+            test_thread_exceptions=test_thread_exceptions)
+        if get_builder:
+            self._builder = control.TEST_BUILDER
         return result
 
     def testFullHelp(self):
@@ -496,10 +509,12 @@ Some images are invalid'''
         for commit in range(self._commits):
             for brd in self._boards.get_list():
                 if brd.arch != 'sandbox':
-                  errfile = self._builder.GetErrFile(commit, brd.target)
+                  errfile = self._builder.get_err_file(commit, brd.target)
                   fd = open(errfile)
-                  self.assertEqual(fd.readlines(),
-                          ['No tool chain for %s\n' % brd.arch])
+                  self.assertEqual(
+                      fd.readlines(),
+                      [f'Tool chain error for {brd.arch}: '
+                       f"No tool chain found for arch '{brd.arch}'"])
                   fd.close()
 
     def testBranch(self):
@@ -573,7 +588,8 @@ Some images are invalid'''
     def testBranchWithSlash(self):
         """Test building a branch with a '/' in the name"""
         self._test_branch = '/__dev/__testbranch'
-        self._RunControl('-b', self._test_branch, clean_dir=False)
+        self._RunControl('-b', self._test_branch, '-o', self._output_dir,
+                         clean_dir=False)
         self.assertEqual(self._builder.count, self._total_builds)
         self.assertEqual(self._builder.fail, 0)
 
@@ -686,7 +702,7 @@ Some images are invalid'''
 
     def testBlobSettingsAlways(self):
         """Test the 'always' policy"""
-        bsettings.SetItem('global', 'allow-missing', 'always')
+        bsettings.set_item('global', 'allow-missing', 'always')
         self.assertEqual(True,
                          control.get_allow_missing(False, False, 1, False))
         self.assertEqual(False,
@@ -694,7 +710,7 @@ Some images are invalid'''
 
     def testBlobSettingsBranch(self):
         """Test the 'branch' policy"""
-        bsettings.SetItem('global', 'allow-missing', 'branch')
+        bsettings.set_item('global', 'allow-missing', 'branch')
         self.assertEqual(False,
                          control.get_allow_missing(False, False, 1, False))
         self.assertEqual(True,
@@ -704,7 +720,7 @@ Some images are invalid'''
 
     def testBlobSettingsMultiple(self):
         """Test the 'multiple' policy"""
-        bsettings.SetItem('global', 'allow-missing', 'multiple')
+        bsettings.set_item('global', 'allow-missing', 'multiple')
         self.assertEqual(False,
                          control.get_allow_missing(False, False, 1, False))
         self.assertEqual(True,
@@ -714,7 +730,7 @@ Some images are invalid'''
 
     def testBlobSettingsBranchMultiple(self):
         """Test the 'branch multiple' policy"""
-        bsettings.SetItem('global', 'allow-missing', 'branch multiple')
+        bsettings.set_item('global', 'allow-missing', 'branch multiple')
         self.assertEqual(False,
                          control.get_allow_missing(False, False, 1, False))
         self.assertEqual(True,
@@ -779,3 +795,273 @@ Some images are invalid'''
 CONFIG_LOCALVERSION=y
 ''', cfg_data)
         self.assertIn('Not dropping LOCALVERSION_AUTO', stdout.getvalue())
+
+    def test_scan_defconfigs(self):
+        """Test scanning the defconfigs to obtain all the boards"""
+        src = self._git_dir
+
+        # Scan the test directory which contains a Kconfig and some *_defconfig
+        # files
+        params, warnings = self._boards.scan_defconfigs(src, src)
+
+        # We should get two boards
+        self.assertEquals(2, len(params))
+        self.assertFalse(warnings)
+        first = 0 if params[0]['target'] == 'board0' else 1
+        board0 = params[first]
+        board2 = params[1 - first]
+
+        self.assertEquals('arm', board0['arch'])
+        self.assertEquals('armv7', board0['cpu'])
+        self.assertEquals('-', board0['soc'])
+        self.assertEquals('Tester', board0['vendor'])
+        self.assertEquals('ARM Board 0', board0['board'])
+        self.assertEquals('config0', board0['config'])
+        self.assertEquals('board0', board0['target'])
+
+        self.assertEquals('powerpc', board2['arch'])
+        self.assertEquals('ppc', board2['cpu'])
+        self.assertEquals('mpc85xx', board2['soc'])
+        self.assertEquals('Tester', board2['vendor'])
+        self.assertEquals('PowerPC board 1', board2['board'])
+        self.assertEquals('config2', board2['config'])
+        self.assertEquals('board2', board2['target'])
+
+    def test_output_is_new(self):
+        """Test detecting new changes to Kconfig"""
+        base = self._base_dir
+        src = self._git_dir
+        config_dir = os.path.join(src, 'configs')
+        delay = 0.02
+
+        # Create a boards.cfg file
+        boards_cfg = os.path.join(base, 'boards.cfg')
+        content = b'''#
+# List of boards
+#   Automatically generated by buildman/boards.py: don't edit
+#
+# Status, Arch, CPU, SoC, Vendor, Board, Target, Config, Maintainers
+
+Active  aarch64     armv8 - armltd corstone1000 board0
+Active  aarch64     armv8 - armltd total_compute board2
+'''
+        # Check missing file
+        self.assertFalse(boards.output_is_new(boards_cfg, config_dir, src))
+
+        # Check that the board.cfg file is newer
+        time.sleep(delay)
+        tools.write_file(boards_cfg, content)
+        self.assertTrue(boards.output_is_new(boards_cfg, config_dir, src))
+
+        # Touch the Kconfig files after a show delay to avoid a race
+        time.sleep(delay)
+        Path(os.path.join(src, 'Kconfig')).touch()
+        self.assertFalse(boards.output_is_new(boards_cfg, config_dir, src))
+        Path(boards_cfg).touch()
+        self.assertTrue(boards.output_is_new(boards_cfg, config_dir, src))
+
+        # Touch a different Kconfig file
+        time.sleep(delay)
+        Path(os.path.join(src, 'Kconfig.something')).touch()
+        self.assertFalse(boards.output_is_new(boards_cfg, config_dir, src))
+        Path(boards_cfg).touch()
+        self.assertTrue(boards.output_is_new(boards_cfg, config_dir, src))
+
+        # Touch a MAINTAINERS file
+        time.sleep(delay)
+        Path(os.path.join(src, 'MAINTAINERS')).touch()
+        self.assertFalse(boards.output_is_new(boards_cfg, config_dir, src))
+
+        Path(boards_cfg).touch()
+        self.assertTrue(boards.output_is_new(boards_cfg, config_dir, src))
+
+        # Touch a defconfig file
+        time.sleep(delay)
+        Path(os.path.join(config_dir, 'board0_defconfig')).touch()
+        self.assertFalse(boards.output_is_new(boards_cfg, config_dir, src))
+        Path(boards_cfg).touch()
+        self.assertTrue(boards.output_is_new(boards_cfg, config_dir, src))
+
+        # Remove a board and check that the board.cfg file is now older
+        Path(os.path.join(config_dir, 'board0_defconfig')).unlink()
+        self.assertFalse(boards.output_is_new(boards_cfg, config_dir, src))
+
+    def test_maintainers(self):
+        """Test detecting boards without a MAINTAINERS entry"""
+        src = self._git_dir
+        main = os.path.join(src, 'boards', 'board0', 'MAINTAINERS')
+        other = os.path.join(src, 'boards', 'board2', 'MAINTAINERS')
+        kc_file = os.path.join(src, 'Kconfig')
+        config_dir = os.path.join(src, 'configs')
+        params_list, warnings = self._boards.build_board_list(config_dir, src)
+
+        # There should be two boards no warnings
+        self.assertEquals(2, len(params_list))
+        self.assertFalse(warnings)
+
+        # Set an invalid status line in the file
+        orig_data = tools.read_file(main, binary=False)
+        lines = ['S:      Other\n' if line.startswith('S:') else line
+                  for line in orig_data.splitlines(keepends=True)]
+        tools.write_file(main, ''.join(lines), binary=False)
+        params_list, warnings = self._boards.build_board_list(config_dir, src)
+        self.assertEquals(2, len(params_list))
+        params = params_list[0]
+        if params['target'] == 'board2':
+            params = params_list[1]
+        self.assertEquals('-', params['status'])
+        self.assertEquals(["WARNING: Other: unknown status for 'board0'"],
+                          warnings)
+
+        # Remove the status line (S:) from a file
+        lines = [line for line in orig_data.splitlines(keepends=True)
+                 if not line.startswith('S:')]
+        tools.write_file(main, ''.join(lines), binary=False)
+        params_list, warnings = self._boards.build_board_list(config_dir, src)
+        self.assertEquals(2, len(params_list))
+        self.assertEquals(["WARNING: -: unknown status for 'board0'"], warnings)
+
+        # Remove the configs/ line (F:) from a file - this is the last line
+        data = ''.join(orig_data.splitlines(keepends=True)[:-1])
+        tools.write_file(main, data, binary=False)
+        params_list, warnings = self._boards.build_board_list(config_dir, src)
+        self.assertEquals(2, len(params_list))
+        self.assertEquals(["WARNING: no maintainers for 'board0'"], warnings)
+
+        # Mark a board as orphaned - this should give a warning
+        lines = ['S: Orphaned' if line.startswith('S') else line
+                 for line in orig_data.splitlines(keepends=True)]
+        tools.write_file(main, ''.join(lines), binary=False)
+        params_list, warnings = self._boards.build_board_list(config_dir, src)
+        self.assertEquals(2, len(params_list))
+        self.assertEquals(["WARNING: no maintainers for 'board0'"], warnings)
+
+        # Change the maintainer to '-' - this should give a warning
+        lines = ['M: -' if line.startswith('M') else line
+                 for line in orig_data.splitlines(keepends=True)]
+        tools.write_file(main, ''.join(lines), binary=False)
+        params_list, warnings = self._boards.build_board_list(config_dir, src)
+        self.assertEquals(2, len(params_list))
+        self.assertEquals(["WARNING: -: unknown status for 'board0'"], warnings)
+
+        # Remove the maintainer line (M:) from a file
+        lines = [line for line in orig_data.splitlines(keepends=True)
+                 if not line.startswith('M:')]
+        tools.write_file(main, ''.join(lines), binary=False)
+        params_list, warnings = self._boards.build_board_list(config_dir, src)
+        self.assertEquals(2, len(params_list))
+        self.assertEquals(["WARNING: no maintainers for 'board0'"], warnings)
+
+        # Move the contents of the second file into this one, removing the
+        # second file, to check multiple records in a single file.
+        both_data = orig_data + tools.read_file(other, binary=False)
+        tools.write_file(main, both_data, binary=False)
+        os.remove(other)
+        params_list, warnings = self._boards.build_board_list(config_dir, src)
+        self.assertEquals(2, len(params_list))
+        self.assertFalse(warnings)
+
+        # Add another record, this should be ignored with a warning
+        extra = '\n\nAnother\nM: Fred\nF: configs/board9_defconfig\nS: other\n'
+        tools.write_file(main, both_data + extra, binary=False)
+        params_list, warnings = self._boards.build_board_list(config_dir, src)
+        self.assertEquals(2, len(params_list))
+        self.assertFalse(warnings)
+
+        # Add another TARGET to the Kconfig
+        tools.write_file(main, both_data, binary=False)
+        orig_kc_data = tools.read_file(kc_file)
+        extra = (b'''
+if TARGET_BOARD2
+config TARGET_OTHER
+\tbool "other"
+\tdefault y
+endif
+''')
+        tools.write_file(kc_file, orig_kc_data + extra)
+        params_list, warnings = self._boards.build_board_list(config_dir, src,
+                                                              warn_targets=True)
+        self.assertEquals(2, len(params_list))
+        self.assertEquals(
+            ['WARNING: board2_defconfig: Duplicate TARGET_xxx: board2 and other'],
+             warnings)
+
+        # Remove the TARGET_BOARD0 Kconfig option
+        lines = [b'' if line == b'config TARGET_BOARD2\n' else line
+                  for line in orig_kc_data.splitlines(keepends=True)]
+        tools.write_file(kc_file, b''.join(lines))
+        params_list, warnings = self._boards.build_board_list(config_dir, src,
+                                                              warn_targets=True)
+        self.assertEquals(2, len(params_list))
+        self.assertEquals(
+            ['WARNING: board2_defconfig: No TARGET_BOARD2 enabled'],
+             warnings)
+        tools.write_file(kc_file, orig_kc_data)
+
+        # Replace the last F: line of board 2 with an N: line
+        data = ''.join(both_data.splitlines(keepends=True)[:-1])
+        tools.write_file(main, data + 'N: oa.*2\n', binary=False)
+        params_list, warnings = self._boards.build_board_list(config_dir, src)
+        self.assertEquals(2, len(params_list))
+        self.assertFalse(warnings)
+
+    def testRegenBoards(self):
+        """Test that we can regenerate the boards.cfg file"""
+        outfile = os.path.join(self._output_dir, 'test-boards.cfg')
+        if os.path.exists(outfile):
+            os.remove(outfile)
+        with test_util.capture_sys_output() as (stdout, stderr):
+            result = self._RunControl('-R', outfile, brds=None,
+                                      get_builder=False)
+        self.assertTrue(os.path.exists(outfile))
+
+    def test_print_prefix(self):
+        """Test that we can print the toolchain prefix"""
+        with test_util.capture_sys_output() as (stdout, stderr):
+            result = self._RunControl('-A', 'board0')
+        self.assertEqual('arm-\n', stdout.getvalue())
+        self.assertEqual('', stderr.getvalue())
+
+    def test_exclude_one(self):
+        """Test excluding a single board from an arch"""
+        self._RunControl('arm', '-x', 'board1', '-o', self._output_dir)
+        self.assertEqual(['board0'],
+                         [b.target for b in self._boards.get_selected()])
+
+    def test_exclude_arch(self):
+        """Test excluding an arch"""
+        self._RunControl('-x', 'arm', '-o', self._output_dir)
+        self.assertEqual(['board2', 'board4'],
+                         [b.target for b in self._boards.get_selected()])
+
+    def test_exclude_comma(self):
+        """Test excluding a comma-separated list of things"""
+        self._RunControl('-x', 'arm,powerpc', '-o', self._output_dir)
+        self.assertEqual(['board4'],
+                         [b.target for b in self._boards.get_selected()])
+
+    def test_exclude_list(self):
+        """Test excluding a list of things"""
+        self._RunControl('-x', 'board2', '-x' 'board4', '-o', self._output_dir)
+        self.assertEqual(['board0', 'board1'],
+                         [b.target for b in self._boards.get_selected()])
+
+    def test_single_boards(self):
+        """Test building single boards"""
+        self._RunControl('--boards', 'board1', '-o', self._output_dir)
+        self.assertEqual(1, self._builder.count)
+
+        self._RunControl('--boards', 'board1', '--boards', 'board2',
+                         '-o', self._output_dir)
+        self.assertEqual(2, self._builder.count)
+
+        self._RunControl('--boards', 'board1,board2', '--boards', 'board4',
+                         '-o', self._output_dir)
+        self.assertEqual(3, self._builder.count)
+
+    def test_print_arch(self):
+        """Test that we can print the board architecture"""
+        with test_util.capture_sys_output() as (stdout, stderr):
+            result = self._RunControl('--print-arch', 'board0')
+        self.assertEqual('arm\n', stdout.getvalue())
+        self.assertEqual('', stderr.getvalue())
diff --git a/tools/buildman/main.py b/tools/buildman/main.py
index 5e1f68d823..5f42a58ddb 100755
--- a/tools/buildman/main.py
+++ b/tools/buildman/main.py
@@ -6,62 +6,91 @@
 
 """See README for more information"""
 
-import doctest
-import multiprocessing
+try:
+    from importlib.resources import files
+except ImportError:
+    # for Python 3.6
+    import importlib_resources
 import os
-import re
 import sys
 
 # Bring in the patman libraries
+# pylint: disable=C0413
 our_path = os.path.dirname(os.path.realpath(__file__))
 sys.path.insert(1, os.path.join(our_path, '..'))
 
 # Our modules
-from buildman import board
 from buildman import bsettings
-from buildman import builder
 from buildman import cmdline
 from buildman import control
-from buildman import toolchain
-from patman import patchstream
-from patman import gitutil
-from u_boot_pylib import terminal
 from u_boot_pylib import test_util
+from u_boot_pylib import tools
 
-def RunTests(skip_net_tests, verboose, args):
+def run_tests(skip_net_tests, debug, verbose, args):
+    """Run the buildman tests
+
+    Args:
+        skip_net_tests (bool): True to skip tests which need the network
+        debug (bool): True to run in debugging mode (full traceback)
+        verbosity (int): Verbosity level to use (0-4)
+        args (list of str): List of tests to run, empty to run all
+    """
+    # These imports are here since tests are not available when buildman is
+    # installed as a Python module
+    # pylint: disable=C0415
     from buildman import func_test
     from buildman import test
-    import doctest
 
-    test_name = args and args[0] or None
+    test_name = args.terms and args.terms[0] or None
     if skip_net_tests:
         test.use_network = False
 
     # Run the entry tests first ,since these need to be the first to import the
     # 'entry' module.
     result = test_util.run_test_suites(
-        'buildman', False, verboose, False, None, test_name, [],
+        'buildman', debug, verbose, False, args.threads, test_name, [],
         [test.TestBuild, func_test.TestFunctional,
          'buildman.toolchain', 'patman.gitutil'])
 
     return (0 if result.wasSuccessful() else 1)
 
+def run_test_coverage():
+    """Run the tests and check that we get 100% coverage"""
+    test_util.run_test_coverage(
+        'tools/buildman/buildman', None,
+        ['tools/patman/*.py', 'tools/u_boot_pylib/*', '*test_fdt.py',
+         'tools/buildman/kconfiglib.py', 'tools/buildman/*test*.py',
+         'tools/buildman/main.py'],
+        '/tmp/b', single_thread='-T1')
+
+
 def run_buildman():
-    options, args = cmdline.ParseArgs()
+    """Run bulidman
 
-    if not options.debug:
+    This is the main program. It collects arguments and runs either the tests or
+    the control module.
+    """
+    args = cmdline.parse_args()
+
+    if not args.debug:
         sys.tracebacklimit = 0
 
     # Run our meagre tests
-    if cmdline.HAS_TESTS and options.test:
-        RunTests(options.skip_net_tests, options.verbose, args)
+    if cmdline.HAS_TESTS and args.test:
+        return run_tests(args.skip_net_tests, args.debug, args.verbose, args)
+
+    elif cmdline.HAS_TESTS and args.coverage:
+        run_test_coverage()
+
+    elif args.full_help:
+        tools.print_full_help(str(files('buildman').joinpath('README.rst')))
 
     # Build selected commits for selected boards
     else:
-        bsettings.Setup(options.config_file)
-        ret_code = control.DoBuildman(options, args)
-        sys.exit(ret_code)
+        bsettings.setup(args.config_file)
+        ret_code = control.do_buildman(args)
+        return ret_code
 
 
 if __name__ == "__main__":
-    run_buildman()
+    sys.exit(run_buildman())
diff --git a/tools/buildman/requirements.txt b/tools/buildman/requirements.txt
new file mode 100644
index 0000000000..a1efcb9d4b
--- /dev/null
+++ b/tools/buildman/requirements.txt
@@ -0,0 +1,2 @@
+jsonschema==4.17.3
+pyyaml==6.0
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index 9fa6445b79..bdd3d84158 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -138,8 +138,8 @@ class TestBuild(unittest.TestCase):
         self.brds.select_boards([])
 
         # Add some test settings
-        bsettings.Setup(None)
-        bsettings.AddFile(settings_data)
+        bsettings.setup(None)
+        bsettings.add_file(settings_data)
 
         # Set up the toolchains
         self.toolchains = toolchain.Toolchains()
@@ -208,8 +208,8 @@ class TestBuild(unittest.TestCase):
 
         # Build the boards for the pre-defined commits and warnings/errors
         # associated with each. This calls our Make() to inject the fake output.
-        build.BuildBoards(self.commits, board_selected, keep_outputs=False,
-                          verbose=False)
+        build.build_boards(self.commits, board_selected, keep_outputs=False,
+                           verbose=False)
         lines = terminal.get_print_test_lines()
         count = 0
         for line in lines:
@@ -219,8 +219,8 @@ class TestBuild(unittest.TestCase):
         # We should get two starting messages, an update for every commit built
         # and a summary message
         self.assertEqual(count, len(commits) * len(BOARDS) + 3)
-        build.SetDisplayOptions(**kwdisplay_args);
-        build.ShowSummary(self.commits, board_selected)
+        build.set_display_options(**kwdisplay_args);
+        build.show_summary(self.commits, board_selected)
         if echo_lines:
             terminal.echo_print_test_lines()
         return iter(terminal.get_print_test_lines())
@@ -465,7 +465,7 @@ class TestBuild(unittest.TestCase):
         options.show_errors = False
         options.keep_outputs = False
         args = ['tegra20']
-        control.DoBuildman(options, args)
+        control.do_buildman(options, args)
 
     def testBoardSingle(self):
         """Test single board selection"""
@@ -528,17 +528,17 @@ class TestBuild(unittest.TestCase):
                                                    'sandbox']),
                          ({'all': ['board4'], 'sandbox': ['board4']}, []))
     def CheckDirs(self, build, dirname):
-        self.assertEqual('base%s' % dirname, build._GetOutputDir(1))
+        self.assertEqual('base%s' % dirname, build.get_output_dir(1))
         self.assertEqual('base%s/fred' % dirname,
-                         build.GetBuildDir(1, 'fred'))
+                         build.get_build_dir(1, 'fred'))
         self.assertEqual('base%s/fred/done' % dirname,
-                         build.GetDoneFile(1, 'fred'))
+                         build.get_done_file(1, 'fred'))
         self.assertEqual('base%s/fred/u-boot.sizes' % dirname,
-                         build.GetFuncSizesFile(1, 'fred', 'u-boot'))
+                         build.get_func_sizes_file(1, 'fred', 'u-boot'))
         self.assertEqual('base%s/fred/u-boot.objdump' % dirname,
-                         build.GetObjdumpFile(1, 'fred', 'u-boot'))
+                         build.get_objdump_file(1, 'fred', 'u-boot'))
         self.assertEqual('base%s/fred/err' % dirname,
-                         build.GetErrFile(1, 'fred'))
+                         build.get_err_file(1, 'fred'))
 
     def testOutputDir(self):
         build = builder.Builder(self.toolchains, BASE_DIR, None, 1, 2,
@@ -622,7 +622,7 @@ class TestBuild(unittest.TestCase):
         build = builder.Builder(self.toolchains, base_dir, None, 1, 2)
         build.commits = self.commits
         build.commit_count = len(commits)
-        result = set(build._GetOutputSpaceRemovals())
+        result = set(build._get_output_space_removals())
         expected = set([os.path.join(base_dir, f) for f in to_remove])
         self.assertEqual(expected, result)
 
diff --git a/tools/buildman/test/Kconfig b/tools/buildman/test/Kconfig
new file mode 100644
index 0000000000..a87660ce45
--- /dev/null
+++ b/tools/buildman/test/Kconfig
@@ -0,0 +1,72 @@
+# Board properties
+config SYS_ARCH
+	string
+
+config SYS_CPU
+	string
+
+config SYS_SOC
+	string
+
+config SYS_VENDOR
+	string
+
+config SYS_BOARD
+	string
+
+config SYS_CONFIG_NAME
+	string
+
+
+# Available targets
+config TARGET_BOARD0
+	bool "board 9"
+
+config TARGET_BOARD2
+	bool "board 2"
+
+
+# Settings for each board
+if TARGET_BOARD0
+
+config SYS_ARCH
+	default "arm"
+
+config SYS_CPU
+	default "armv7"
+
+#config SYS_SOC
+#	string
+
+config SYS_VENDOR
+	default "Tester"
+
+config SYS_BOARD
+	default "ARM Board 0"
+
+config SYS_CONFIG_NAME
+	default "config0"
+
+endif
+
+if TARGET_BOARD2
+
+config SYS_ARCH
+	default "powerpc"
+
+config SYS_CPU
+	default "ppc"
+
+config SYS_SOC
+	default "mpc85xx"
+
+config SYS_VENDOR
+	default "Tester"
+
+config SYS_BOARD
+	default "PowerPC board 1"
+
+config SYS_CONFIG_NAME
+	default "config2"
+
+endif
diff --git a/tools/buildman/test/boards/board0/MAINTAINERS b/tools/buildman/test/boards/board0/MAINTAINERS
new file mode 100644
index 0000000000..08207ff3f4
--- /dev/null
+++ b/tools/buildman/test/boards/board0/MAINTAINERS
@@ -0,0 +1,5 @@
+ARM Board 0
+M:      Mary Mary <quite@contrary.org>
+S:      Maintained
+F:      boards/board0
+F:      configs/board0_defconfig
diff --git a/tools/buildman/test/boards/board2/MAINTAINERS b/tools/buildman/test/boards/board2/MAINTAINERS
new file mode 100644
index 0000000000..c154782202
--- /dev/null
+++ b/tools/buildman/test/boards/board2/MAINTAINERS
@@ -0,0 +1,5 @@
+ARM Board 2
+M:      Old Mother <hubbard@cupboard.org>
+S:      Maintained
+F:      boards/board2
+F:      configs/board2_defconfig
diff --git a/tools/buildman/test/configs/board0_defconfig b/tools/buildman/test/configs/board0_defconfig
new file mode 100644
index 0000000000..50e562e53b
--- /dev/null
+++ b/tools/buildman/test/configs/board0_defconfig
@@ -0,0 +1 @@
+CONFIG_TARGET_BOARD0=y
diff --git a/tools/buildman/test/configs/board2_defconfig b/tools/buildman/test/configs/board2_defconfig
new file mode 100644
index 0000000000..8b76c0ae1d
--- /dev/null
+++ b/tools/buildman/test/configs/board2_defconfig
@@ -0,0 +1 @@
+CONFIG_TARGET_BOARD2=y
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 0ecd8458b9..b05001194e 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -139,7 +139,7 @@ class Toolchain:
         """Get toolchain wrapper from the setting file.
         """
         value = ''
-        for name, value in bsettings.GetItems('toolchain-wrapper'):
+        for name, value in bsettings.get_items('toolchain-wrapper'):
             if not value:
                 print("Warning: Wrapper not found")
         if value:
@@ -249,7 +249,7 @@ class Toolchains:
         self.prefixes = {}
         self.paths = []
         self.override_toolchain = override_toolchain
-        self._make_flags = dict(bsettings.GetItems('make-flags'))
+        self._make_flags = dict(bsettings.get_items('make-flags'))
 
     def GetPathList(self, show_warning=True):
         """Get a list of available toolchain paths
@@ -261,7 +261,7 @@ class Toolchains:
             List of strings, each a path to a toolchain mentioned in the
             [toolchain] section of the settings file.
         """
-        toolchains = bsettings.GetItems('toolchain')
+        toolchains = bsettings.get_items('toolchain')
         if show_warning and not toolchains:
             print(("Warning: No tool chains. Please run 'buildman "
                    "--fetch-arch all' to download all available toolchains, or "
@@ -283,7 +283,7 @@ class Toolchains:
         Args:
             show_warning: True to show a warning if there are no tool chains.
         """
-        self.prefixes = bsettings.GetItems('toolchain-prefix')
+        self.prefixes = bsettings.get_items('toolchain-prefix')
         self.paths += self.GetPathList(show_warning)
 
     def Add(self, fname, test=True, verbose=False, priority=PRIORITY_CALC,
@@ -399,7 +399,7 @@ class Toolchains:
         returns:
             toolchain object, or None if none found
         """
-        for tag, value in bsettings.GetItems('toolchain-alias'):
+        for tag, value in bsettings.get_items('toolchain-alias'):
             if arch == tag:
                 for alias in value.split():
                     if alias in self.toolchains:
@@ -421,7 +421,7 @@ class Toolchains:
         Returns:
             Resolved string
 
-        >>> bsettings.Setup(None)
+        >>> bsettings.setup(None)
         >>> tcs = Toolchains()
         >>> tcs.Add('fred', False)
         >>> var_dict = {'oblique' : 'OBLIQUE', 'first' : 'fi${second}rst', \
@@ -499,7 +499,7 @@ class Toolchains:
         if arch == 'aarch64':
             arch = 'arm64'
         base = 'https://www.kernel.org/pub/tools/crosstool/files/bin'
-        versions = ['12.2.0', '11.1.0']
+        versions = ['13.1.0', '12.2.0']
         links = []
         for version in versions:
             url = '%s/%s/%s/' % (base, arch, version)
@@ -598,5 +598,5 @@ class Toolchains:
         if not self.TestSettingsHasPath(dirpath):
             print(("Adding 'download' to config file '%s'" %
                    bsettings.config_fname))
-            bsettings.SetItem('toolchain', 'download', '%s/*/*' % dest)
+            bsettings.set_item('toolchain', 'download', '%s/*/*' % dest)
         return 0
diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index 9804b55ddd..3d2b64a355 100644
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -2,7 +2,7 @@
 # This Dockerfile is used to build an image containing basic stuff to be used
 # to build U-Boot and run our test suites.
 
-FROM ubuntu:jammy-20230308
+FROM ubuntu:jammy-20230624
 MAINTAINER Tom Rini <trini@konsulko.com>
 LABEL Description=" This image is for building U-Boot inside a container"
 
@@ -14,22 +14,22 @@ RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib
 RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add -
 RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-16 main | tee /etc/apt/sources.list.d/llvm.list
 
-# Manually install the kernel.org "Crosstool" based toolchains for gcc-12.2.0
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ
+# Manually install the kernel.org "Crosstool" based toolchains for gcc-13.1.0
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-arc-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ
 
 # Manually install other toolchains
 RUN wget -O - https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc233c-elf.tar.gz | tar -C /opt -xz
-RUN wget -O - https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2021.03-release/arc_gnu_2021.03_prebuilt_uclibc_le_archs_linux_install.tar.gz | tar --no-same-owner -C /opt -xz
 
 # Update and install things from apt now
 RUN apt-get update && apt-get install -y \
@@ -77,6 +77,7 @@ RUN apt-get update && apt-get install -y \
 	libsdl1.2-dev \
 	libsdl2-dev \
 	libseccomp-dev \
+	libslirp-dev \
 	libssl-dev \
 	libtool \
 	libudev-dev \
@@ -128,15 +129,16 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \
 	git config --global user.name "GitLab CI Runner" && \
 	git config --global user.email trini@konsulko.com && \
 	git cherry-pick 049efdd72eb7baa7b2bf8884391ee7fe650da5a0 && \
+	git cherry-pick 403d6540cd608b2706cfa0cb4713f7e4b490ff45 && \
 	./bootstrap && \
 	mkdir -p /opt/grub && \
 	./configure --target=aarch64 --with-platform=efi \
 	CC=gcc \
-	TARGET_CC=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc \
-	TARGET_OBJCOPY=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy \
-	TARGET_STRIP=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \
-	TARGET_NM=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \
-	TARGET_RANLIB=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \
+	TARGET_CC=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc \
+	TARGET_OBJCOPY=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy \
+	TARGET_STRIP=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \
+	TARGET_NM=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \
+	TARGET_RANLIB=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \
 	make && \
 	./grub-mkimage -O arm64-efi -o /opt/grub/grubaa64.efi --prefix= -d \
 	grub-core cat chain configfile echo efinet ext2 fat halt help linux \
@@ -146,11 +148,11 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \
 	make clean && \
 	./configure --target=arm --with-platform=efi \
 	CC=gcc \
-	TARGET_CC=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc \
-	TARGET_OBJCOPY=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy \
-	TARGET_STRIP=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \
-	TARGET_NM=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \
-	TARGET_RANLIB=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \
+	TARGET_CC=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc \
+	TARGET_OBJCOPY=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy \
+	TARGET_STRIP=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \
+	TARGET_NM=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \
+	TARGET_RANLIB=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \
 	make && \
 	./grub-mkimage -O arm-efi -o /opt/grub/grubarm.efi --prefix= -d \
 	grub-core cat chain configfile echo efinet ext2 fat halt help linux \
@@ -160,11 +162,11 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \
 	make clean && \
 	./configure --target=riscv64 --with-platform=efi \
 	CC=gcc \
-	TARGET_CC=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc \
-	TARGET_OBJCOPY=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \
-	TARGET_STRIP=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \
-	TARGET_NM=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \
-	TARGET_RANLIB=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \
+	TARGET_CC=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc \
+	TARGET_OBJCOPY=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \
+	TARGET_STRIP=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \
+	TARGET_NM=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \
+	TARGET_RANLIB=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \
 	make && \
 	./grub-mkimage -O riscv64-efi -o /opt/grub/grubriscv64.efi --prefix= -d \
 	grub-core cat chain configfile echo efinet ext2 fat halt help linux \
@@ -175,13 +177,10 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \
 
 RUN git clone https://gitlab.com/qemu-project/qemu.git /tmp/qemu && \
 	cd /tmp/qemu && \
-	git submodule update --init dtc && \
-	git checkout v6.1.0 && \
+	git checkout v8.0.3 && \
 	# config user.name and user.email to make 'git am' happy
 	git config user.name u-boot && \
 	git config user.email u-boot@denx.de && \
-	# manually apply the bug fix for QEMU 6.1.0 Xilinx Zynq UART emulation codes
-	wget -O - http://patchwork.ozlabs.org/project/qemu-devel/patch/20210823020813.25192-2-bmeng.cn@gmail.com/mbox/ | git am && \
 	./configure --prefix=/opt/qemu --target-list="aarch64-softmmu,arm-softmmu,i386-softmmu,m68k-softmmu,mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu,ppc-softmmu,riscv32-softmmu,riscv64-softmmu,sh4-softmmu,x86_64-softmmu,xtensa-softmmu" && \
 	make -j$(nproc) all install && \
 	rm -rf /tmp/qemu
@@ -278,8 +277,7 @@ RUN virtualenv -p /usr/bin/python3 /tmp/venv && \
 
 # Create the buildman config file
 RUN /bin/echo -e "[toolchain]\nroot = /usr" > ~/.buildman
-RUN /bin/echo -e "kernelorg = /opt/gcc-12.2.0-nolibc/*" >> ~/.buildman
-RUN /bin/echo -e "arc = /opt/arc_gnu_2021.03_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
+RUN /bin/echo -e "kernelorg = /opt/gcc-13.1.0-nolibc/*" >> ~/.buildman
 RUN /bin/echo -e "\n[toolchain-prefix]\nxtensa = /opt/2020.07/xtensa-dc233c-elf/bin/xtensa-dc233c-elf-" >> ~/.buildman;
 RUN /bin/echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman
 RUN /bin/echo -e "\nsandbox = x86_64" >> ~/.buildman
diff --git a/tools/dtoc/fdt.py b/tools/dtoc/fdt.py
index a8e05349a7..0b20d52f31 100644
--- a/tools/dtoc/fdt.py
+++ b/tools/dtoc/fdt.py
@@ -13,6 +13,10 @@ from dtoc import fdt_util
 import libfdt
 from libfdt import QUIET_NOTFOUND
 from u_boot_pylib import tools
+from u_boot_pylib import tout
+
+# Temporary hack
+IGNORE_DUP_PHANDLES = False
 
 # This deals with a device tree, presenting it as an assortment of Node and
 # Prop objects, representing nodes and properties, respectively. This file
@@ -248,6 +252,7 @@ class Prop:
         """
         if self.dirty:
             node = self._node
+            tout.debug(f'sync {node.path}: {self.name}')
             fdt_obj = node._fdt._fdt_obj
             node_name = fdt_obj.get_name(node._offset)
             if node_name and node_name != node.name:
@@ -264,6 +269,14 @@ class Prop:
                 fdt_obj.setprop(node.Offset(), self.name, self.bytes)
             self.dirty = False
 
+    def purge(self):
+        """Set a property offset to None
+
+        The property remains in the tree structure and will be recreated when
+        the FDT is synced
+        """
+        self._offset = None
+        self.dirty = True
 
 class Node:
     """A device tree node
@@ -327,7 +340,13 @@ class Node:
         self.props = self._fdt.GetProps(self)
         phandle = fdt_obj.get_phandle(self.Offset())
         if phandle:
-            self._fdt.phandle_to_node[phandle] = self
+            dup = self._fdt.phandle_to_node.get(phandle)
+            if dup:
+                if not IGNORE_DUP_PHANDLES:
+                    raise ValueError(
+                        f'Duplicate phandle {phandle} in nodes {dup.path} and {self.path}')
+            else:
+                self._fdt.phandle_to_node[phandle] = self
 
         offset = fdt_obj.first_subnode(self.Offset(), QUIET_NOTFOUND)
         while offset >= 0:
@@ -534,8 +553,8 @@ class Node:
         """
         return self.AddData(prop_name, struct.pack('>I', val))
 
-    def AddSubnode(self, name):
-        """Add a new subnode to the node
+    def Subnode(self, name):
+        """Create new subnode for the node
 
         Args:
             name: name of node to add
@@ -544,10 +563,72 @@ class Node:
             New subnode that was created
         """
         path = self.path + '/' + name
-        subnode = Node(self._fdt, self, None, name, path)
+        return Node(self._fdt, self, None, name, path)
+
+    def AddSubnode(self, name):
+        """Add a new subnode to the node, after all other subnodes
+
+        Args:
+            name: name of node to add
+
+        Returns:
+            New subnode that was created
+        """
+        subnode = self.Subnode(name)
         self.subnodes.append(subnode)
         return subnode
 
+    def insert_subnode(self, name):
+        """Add a new subnode to the node, before all other subnodes
+
+        This deletes other subnodes and sets their offset to None, so that they
+        will be recreated after this one.
+
+        Args:
+            name: name of node to add
+
+        Returns:
+            New subnode that was created
+        """
+        # Deleting a node invalidates the offsets of all following nodes, so
+        # process in reverse order so that the offset of each node remains valid
+        # until deletion.
+        for subnode in reversed(self.subnodes):
+            subnode.purge(True)
+        subnode = self.Subnode(name)
+        self.subnodes.insert(0, subnode)
+        return subnode
+
+    def purge(self, delete_it=False):
+        """Purge this node, setting offset to None and deleting from FDT"""
+        if self._offset is not None:
+            if delete_it:
+                CheckErr(self._fdt._fdt_obj.del_node(self.Offset()),
+                     "Node '%s': delete" % self.path)
+            self._offset = None
+            self._fdt.Invalidate()
+
+        for prop in self.props.values():
+            prop.purge()
+
+        for subnode in self.subnodes:
+            subnode.purge(False)
+
+    def move_to_first(self):
+        """Move the current node to first in its parent's node list"""
+        parent = self.parent
+        if parent.subnodes and parent.subnodes[0] == self:
+            return
+        for subnode in reversed(parent.subnodes):
+            subnode.purge(True)
+
+        new_subnodes = [self]
+        for subnode in parent.subnodes:
+            #subnode.purge(False)
+            if subnode != self:
+                new_subnodes.append(subnode)
+        parent.subnodes = new_subnodes
+
     def Delete(self):
         """Delete a node
 
@@ -635,6 +716,79 @@ class Node:
             prop.Sync(auto_resize)
         return added
 
+    def merge_props(self, src, copy_phandles):
+        """Copy missing properties (except 'phandle') from another node
+
+        Args:
+            src (Node): Node containing properties to copy
+            copy_phandles (bool): True to copy phandle properties in nodes
+
+        Adds properties which are present in src but not in this node. Any
+        'phandle' property is not copied since this might result in two nodes
+        with the same phandle, thus making phandle references ambiguous.
+        """
+        tout.debug(f'copy to {self.path}: {src.path}')
+        for name, src_prop in src.props.items():
+            done = False
+            if name not in self.props:
+                if copy_phandles or name != 'phandle':
+                    self.props[name] = Prop(self, None, name, src_prop.bytes)
+                    done = True
+            tout.debug(f"  {name}{'' if done else '  - ignored'}")
+
+    def copy_node(self, src, copy_phandles=False):
+        """Copy a node and all its subnodes into this node
+
+        Args:
+            src (Node): Node to copy
+            copy_phandles (bool): True to copy phandle properties in nodes
+
+        Returns:
+            Node: Resulting destination node
+
+        This works recursively, with copy_phandles being set to True for the
+        recursive calls
+
+        The new node is put before all other nodes. If the node already
+        exists, just its subnodes and properties are copied, placing them before
+        any existing subnodes. Properties which exist in the destination node
+        already are not copied.
+        """
+        dst = self.FindNode(src.name)
+        if dst:
+            dst.move_to_first()
+        else:
+            dst = self.insert_subnode(src.name)
+        dst.merge_props(src, copy_phandles)
+
+        # Process in reverse order so that they appear correctly in the result,
+        # since copy_node() puts the node first in the list
+        for node in reversed(src.subnodes):
+            dst.copy_node(node, True)
+        return dst
+
+    def copy_subnodes_from_phandles(self, phandle_list):
+        """Copy subnodes of a list of nodes into another node
+
+        Args:
+            phandle_list (list of int): List of phandles of nodes to copy
+
+        For each node in the phandle list, its subnodes and their properties are
+        copied recursively. Note that it does not copy the node itself, nor its
+        properties.
+        """
+        # Process in reverse order, since new nodes are inserted at the start of
+        # the destination's node list. We want them to appear in order of the
+        # phandle list
+        for phandle in phandle_list.__reversed__():
+            parent = self.GetFdt().LookupPhandle(phandle)
+            tout.debug(f'adding template {parent.path} to node {self.path}')
+            for node in parent.subnodes.__reversed__():
+                dst = self.copy_node(node)
+
+            tout.debug(f'merge props from {parent.path} to {dst.path}')
+            self.merge_props(parent, False)
+
 
 class Fdt:
     """Provides simple access to a flat device tree blob using libfdts.
@@ -694,6 +848,7 @@ class Fdt:
 
         TODO(sjg@chromium.org): Implement the 'root' parameter
         """
+        self.phandle_to_node = {}
         self._cached_offsets = True
         self._root = self.Node(self, None, 0, '/', '/')
         self._root.Scan()
diff --git a/tools/dtoc/test/dtoc_test_copy.dts b/tools/dtoc/test/dtoc_test_copy.dts
new file mode 100644
index 0000000000..8e50c75659
--- /dev/null
+++ b/tools/dtoc/test/dtoc_test_copy.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test device tree file for dtoc
+ *
+ * Copyright 2017 Google, Inc
+ */
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	reference = <&over>;	/* nake sure that the 'over' phandle exists */
+	copy-list = <&another &base>;
+
+	dest {
+		bootph-all;
+		compatible = "sandbox,spl-test";
+		stringarray = "one";
+		longbytearray = [09 0a 0b 0c 0d 0e 0f 10];
+		maybe-empty-int = <1>;
+
+		first@0 {
+			a-prop = <456>;
+			b-prop = <1>;
+		};
+
+		existing {
+		};
+
+		base {
+			second {
+				second3 {
+				};
+
+				second2 {
+					new-prop;
+				};
+
+				second1: second1 {
+					new-prop;
+				};
+
+				second4 {
+					use_second1 = <&second1>;
+				};
+			};
+		};
+	};
+
+	base: base {
+		compatible = "sandbox,i2c";
+		bootph-all;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		over: over {
+			compatible = "sandbox,pmic";
+			bootph-all;
+			reg = <9>;
+			low-power;
+		};
+
+		first@0 {
+			reg = <0>;
+			a-prop = <123>;
+		};
+
+		second: second {
+			second_1_bad: second1 {
+				some-prop;
+			};
+
+			second2 {
+				some-prop;
+				use_second1_bad = <&second_1_bad>;
+			};
+		};
+	};
+
+	another: another {
+		new-prop = "hello";
+		earlier {
+			wibble = <2>;
+		};
+
+		later {
+			fibble = <3>;
+		};
+	};
+};
diff --git a/tools/dtoc/test_fdt.py b/tools/dtoc/test_fdt.py
index 4fe8d12c40..0b01518f3a 100755
--- a/tools/dtoc/test_fdt.py
+++ b/tools/dtoc/test_fdt.py
@@ -32,6 +32,7 @@ from dtoc.fdt import Type, BytesToValue
 import libfdt
 from u_boot_pylib import test_util
 from u_boot_pylib import tools
+from u_boot_pylib import tout
 
 #pylint: disable=protected-access
 
@@ -306,6 +307,142 @@ class TestNode(unittest.TestCase):
         self.assertIn("Internal error, node '/spl-test' name mismatch 'i2c@0'",
                       str(exc.exception))
 
+    def test_copy_node(self):
+        """Test copy_node() function"""
+        def do_copy_checks(dtb, dst, second1_ph_val, expect_none):
+            self.assertEqual(
+                ['/dest/base', '/dest/first@0', '/dest/existing'],
+                [n.path for n in dst.subnodes])
+
+            chk = dtb.GetNode('/dest/base')
+            self.assertTrue(chk)
+            self.assertEqual(
+                {'compatible', 'bootph-all', '#address-cells', '#size-cells'},
+                chk.props.keys())
+
+            # Check the first property
+            prop = chk.props['bootph-all']
+            self.assertEqual('bootph-all', prop.name)
+            self.assertEqual(True, prop.value)
+            self.assertEqual(chk.path, prop._node.path)
+
+            # Check the second property
+            prop2 = chk.props['compatible']
+            self.assertEqual('compatible', prop2.name)
+            self.assertEqual('sandbox,i2c', prop2.value)
+            self.assertEqual(chk.path, prop2._node.path)
+
+            base = chk.FindNode('base')
+            self.assertTrue(chk)
+
+            first = dtb.GetNode('/dest/base/first@0')
+            self.assertTrue(first)
+            over = dtb.GetNode('/dest/base/over')
+            self.assertTrue(over)
+
+            # Make sure that the phandle for 'over' is copied
+            self.assertIn('phandle', over.props.keys())
+
+            second = dtb.GetNode('/dest/base/second')
+            self.assertTrue(second)
+            self.assertEqual([over.name, first.name, second.name],
+                             [n.name for n in chk.subnodes])
+            self.assertEqual(chk, over.parent)
+            self.assertEqual(
+                {'bootph-all', 'compatible', 'reg', 'low-power', 'phandle'},
+                over.props.keys())
+
+            if expect_none:
+                self.assertIsNone(prop._offset)
+                self.assertIsNone(prop2._offset)
+                self.assertIsNone(over._offset)
+            else:
+                self.assertTrue(prop._offset)
+                self.assertTrue(prop2._offset)
+                self.assertTrue(over._offset)
+
+            # Now check ordering of the subnodes
+            self.assertEqual(
+                ['second1', 'second2', 'second3', 'second4'],
+                [n.name for n in second.subnodes])
+
+            # Check the 'second_1_bad' phandle is not copied over
+            second1 = second.FindNode('second1')
+            self.assertTrue(second1)
+            sph = second1.props.get('phandle')
+            self.assertTrue(sph)
+            self.assertEqual(second1_ph_val, sph.bytes)
+
+
+        dtb = fdt.FdtScan(find_dtb_file('dtoc_test_copy.dts'))
+        tmpl = dtb.GetNode('/base')
+        dst = dtb.GetNode('/dest')
+        second1_ph_val = (dtb.GetNode('/dest/base/second/second1').
+                          props['phandle'].bytes)
+        dst.copy_node(tmpl)
+
+        do_copy_checks(dtb, dst, second1_ph_val, expect_none=True)
+
+        dtb.Sync(auto_resize=True)
+
+        # Now check the resulting FDT. It should have duplicate phandles since
+        # 'over' has been copied to 'dest/base/over' but still exists in its old
+        # place
+        new_dtb = fdt.Fdt.FromData(dtb.GetContents())
+        with self.assertRaises(ValueError) as exc:
+            new_dtb.Scan()
+        self.assertIn(
+            'Duplicate phandle 1 in nodes /dest/base/over and /base/over',
+            str(exc.exception))
+
+        # Remove the source nodes for the copy
+        new_dtb.GetNode('/base').Delete()
+
+        # Now it should scan OK
+        new_dtb.Scan()
+
+        dst = new_dtb.GetNode('/dest')
+        do_copy_checks(new_dtb, dst, second1_ph_val, expect_none=False)
+
+    def test_copy_subnodes_from_phandles(self):
+        """Test copy_node() function"""
+        dtb = fdt.FdtScan(find_dtb_file('dtoc_test_copy.dts'))
+
+        orig = dtb.GetNode('/')
+        node_list = fdt_util.GetPhandleList(orig, 'copy-list')
+
+        dst = dtb.GetNode('/dest')
+        dst.copy_subnodes_from_phandles(node_list)
+
+        pmic = dtb.GetNode('/dest/over')
+        self.assertTrue(pmic)
+
+        subn = dtb.GetNode('/dest/first@0')
+        self.assertTrue(subn)
+        self.assertEqual({'a-prop', 'b-prop', 'reg'}, subn.props.keys())
+
+        self.assertEqual(
+            ['/dest/earlier', '/dest/later', '/dest/over', '/dest/first@0',
+             '/dest/second', '/dest/existing', '/dest/base'],
+            [n.path for n in dst.subnodes])
+
+        # Make sure that the phandle for 'over' is not copied
+        over = dst.FindNode('over')
+        tout.debug(f'keys: {over.props.keys()}')
+        self.assertNotIn('phandle', over.props.keys())
+
+        # Check the merged properties, first the base ones in '/dest'
+        expect = {'bootph-all', 'compatible', 'stringarray', 'longbytearray',
+                  'maybe-empty-int'}
+
+        # Properties from 'base'
+        expect.update({'#address-cells', '#size-cells'})
+
+        # Properties from 'another'
+        expect.add('new-prop')
+
+        self.assertEqual(expect, set(dst.props.keys()))
+
 
 class TestProp(unittest.TestCase):
     """Test operation of the Prop class"""
diff --git a/tools/eficapsule.h b/tools/eficapsule.h
index 072a4b5598..2099a2e9b8 100644
--- a/tools/eficapsule.h
+++ b/tools/eficapsule.h
@@ -63,7 +63,7 @@ struct efi_firmware_management_capsule_header {
 	uint32_t version;
 	uint16_t embedded_driver_count;
 	uint16_t payload_item_count;
-	uint32_t item_offset_list[];
+	uint64_t item_offset_list[];
 } __packed;
 
 /* image_capsule_support */
@@ -113,4 +113,34 @@ struct efi_firmware_image_authentication {
 	struct win_certificate_uefi_guid auth_info;
 } __packed;
 
+/* fmp payload header */
+#define SIGNATURE_16(A, B)	((A) | ((B) << 8))
+#define SIGNATURE_32(A, B, C, D)	\
+	(SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16))
+
+#define FMP_PAYLOAD_HDR_SIGNATURE	SIGNATURE_32('M', 'S', 'S', '1')
+
+/**
+ * struct fmp_payload_header - EDK2 header for the FMP payload
+ *
+ * This structure describes the header which is preprended to the
+ * FMP payload by the edk2 capsule generation scripts.
+ *
+ * @signature:			Header signature used to identify the header
+ * @header_size:		Size of the structure
+ * @fw_version:			Firmware versions used
+ * @lowest_supported_version:	Lowest supported version (not used)
+ */
+struct fmp_payload_header {
+	uint32_t signature;
+	uint32_t header_size;
+	uint32_t fw_version;
+	uint32_t lowest_supported_version;
+};
+
+struct fmp_payload_header_params {
+	bool have_header;
+	uint32_t fw_version;
+};
+
 #endif /* _EFI_CAPSULE_H */
diff --git a/tools/env/.gitignore b/tools/env/.gitignore
index 8d28b2b70b..804abacc6e 100644
--- a/tools/env/.gitignore
+++ b/tools/env/.gitignore
@@ -1,3 +1,2 @@
-embedded.c
 fw_printenv
 fw_printenv_unstripped
diff --git a/tools/expo.py b/tools/expo.py
new file mode 100755
index 0000000000..c6eb87aec7
--- /dev/null
+++ b/tools/expo.py
@@ -0,0 +1,130 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0+
+
+"""
+Expo utility - used for testing of expo features
+
+Copyright 2023 Google LLC
+Written by Simon Glass <sjg@chromium.org>
+"""
+
+import argparse
+import collections
+import io
+import re
+import subprocess
+import sys
+
+#from u_boot_pylib import cros_subprocess
+from u_boot_pylib import tools
+
+# Parse:
+#	SCENE1		= 7,
+# or	SCENE2,
+RE_ENUM = re.compile(r'(\S*)(\s*= (\d))?,')
+
+# Parse #define <name>  "string"
+RE_DEF = re.compile(r'#define (\S*)\s*"(.*)"')
+
+def calc_ids(fname):
+    """Figure out the value of the enums in a C file
+
+    Args:
+        fname (str): Filename to parse
+
+    Returns:
+        OrderedDict():
+            key (str): enum name
+            value (int or str):
+                Value of enum, if int
+                Value of #define, if string
+    """
+    vals = collections.OrderedDict()
+    with open(fname, 'r', encoding='utf-8') as inf:
+        in_enum = False
+        cur_id = 0
+        for line in inf.readlines():
+            line = line.strip()
+            if line == 'enum {':
+                in_enum = True
+                continue
+            if in_enum and line == '};':
+                in_enum = False
+
+            if in_enum:
+                if not line or line.startswith('/*'):
+                    continue
+                m_enum = RE_ENUM.match(line)
+                if m_enum.group(3):
+                    cur_id = int(m_enum.group(3))
+                vals[m_enum.group(1)] = cur_id
+                cur_id += 1
+            else:
+                m_def = RE_DEF.match(line)
+                if m_def:
+                    vals[m_def.group(1)] = tools.to_bytes(m_def.group(2))
+
+    return vals
+
+
+def run_expo(args):
+    """Run the expo program"""
+    ids = calc_ids(args.enum_fname)
+
+    indata = tools.read_file(args.layout)
+
+    outf = io.BytesIO()
+
+    for name, val in ids.items():
+        if isinstance(val, int):
+            outval = b'%d' % val
+        else:
+            outval = b'"%s"' % val
+        find_str = r'\b%s\b' % name
+        indata = re.sub(tools.to_bytes(find_str), outval, indata)
+
+    outf.write(indata)
+    data = outf.getvalue()
+
+    with open('/tmp/asc', 'wb') as outf:
+        outf.write(data)
+    proc = subprocess.run('dtc', input=data, capture_output=True, check=True)
+    edtb = proc.stdout
+    if proc.stderr:
+        print(proc.stderr)
+        return 1
+    tools.write_file(args.outfile, edtb)
+    return 0
+
+
+def parse_args(argv):
+    """Parse the command-line arguments
+
+    Args:
+        argv (list of str): List of string arguments
+
+    Returns:
+        tuple: (options, args) with the command-line options and arugments.
+            options provides access to the options (e.g. option.debug)
+            args is a list of string arguments
+    """
+    parser = argparse.ArgumentParser()
+    parser.add_argument('-e', '--enum-fname', type=str,
+        help='C file containing enum declaration for expo items')
+    parser.add_argument('-l', '--layout', type=str,
+        help='Devicetree file source .dts for expo layout')
+    parser.add_argument('-o', '--outfile', type=str,
+        help='Filename to write expo layout dtb')
+
+    return parser.parse_args(argv)
+
+def start_expo():
+    """Start the expo program"""
+    args = parse_args(sys.argv[1:])
+
+    ret_code = run_expo(args)
+    sys.exit(ret_code)
+
+
+if __name__ == "__main__":
+    start_expo()
diff --git a/tools/iot2050-sign-fw.sh b/tools/iot2050-sign-fw.sh
index 4d1d79498c..6b426c854c 100755
--- a/tools/iot2050-sign-fw.sh
+++ b/tools/iot2050-sign-fw.sh
@@ -39,13 +39,10 @@ CERT_X509=$(mktemp XXXXXXXX.crt)
 
 openssl req -new -x509 -key $1 -nodes -outform DER -out $CERT_X509 -config $TEMP_X509 -sha512
 cat $CERT_X509 tispl.bin > tispl.bin_signed
-# currently broken in upstream
-#source/tools/binman/binman replace -i flash.bin -f tispl.bin_signed blob@0x180000
-dd if=tispl.bin_signed of=flash.bin bs=$((0x1000)) seek=$((0x180000/0x1000)) conv=notrunc
+source/tools/binman/binman replace -i flash-pg1.bin -f tispl.bin_signed fit@180000
+source/tools/binman/binman replace -i flash-pg2.bin -f tispl.bin_signed fit@180000
 
 rm $TEMP_X509 $CERT_X509
 
-tools/mkimage -G $1 -r -o sha256,rsa4096 -F fit@0x380000.fit
-# currently broken in upstream
-#source/tools/binman/binman replace -i flash.bin -f fit@0x380000.fit fit@0x380000
-dd if=fit@0x380000.fit of=flash.bin bs=$((0x1000)) seek=$((0x380000/0x1000)) conv=notrunc
+source/tools/binman/binman sign -i flash-pg1.bin -k $1 -a sha256,rsa4096 fit@380000
+source/tools/binman/binman sign -i flash-pg2.bin -k $1 -a sha256,rsa4096 fit@380000
diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh
deleted file mode 100755
index 7bc07ad074..0000000000
--- a/tools/k3_fit_atf.sh
+++ /dev/null
@@ -1,123 +0,0 @@
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0+
-#
-# script to generate FIT image source for K3 Family boards with
-# ATF, OPTEE, SPL and multiple device trees (given on the command line).
-# Inspired from board/sunxi/mksunxi_fit_atf.sh
-#
-# usage: $0 <atf_load_addr> <dt_name> [<dt_name> [<dt_name] ...]
-
-[ -z "$ATF" ] && ATF="bl31.bin"
-
-if [ ! -f $ATF ]; then
-	echo "WARNING ATF file $ATF NOT found, resulting binary is non-functional" >&2
-	ATF=/dev/null
-fi
-
-[ -z "$TEE" ] && TEE="bl32.bin"
-
-if [ ! -f $TEE ]; then
-	echo "WARNING OPTEE file $TEE NOT found, resulting might be non-functional" >&2
-	TEE=/dev/null
-fi
-
-[ -z "$DM" ] && DM="dm.bin"
-
-if [ ! -e $DM ]; then
-	echo "WARNING DM file $DM NOT found, resulting might be non-functional" >&2
-	DM=/dev/null
-fi
-
-if [ ! -z "$IS_HS" ]; then
-	HS_APPEND=_HS
-fi
-
-cat << __HEADER_EOF
-/dts-v1/;
-
-/ {
-	description = "Configuration to load ATF and SPL";
-	#address-cells = <1>;
-
-	images {
-		atf {
-			description = "ARM Trusted Firmware";
-			data = /incbin/("$ATF");
-			type = "firmware";
-			arch = "arm64";
-			compression = "none";
-			os = "arm-trusted-firmware";
-			load = <$1>;
-			entry = <$1>;
-		};
-		tee {
-			description = "OPTEE";
-			data = /incbin/("$TEE");
-			type = "tee";
-			arch = "arm64";
-			compression = "none";
-			os = "tee";
-			load = <0x9e800000>;
-			entry = <0x9e800000>;
-		};
-		dm {
-			description = "DM binary";
-			data = /incbin/("$DM");
-			type = "firmware";
-			arch = "arm32";
-			compression = "none";
-			os = "DM";
-			load = <0x89000000>;
-			entry = <0x89000000>;
-		};
-		spl {
-			description = "SPL (64-bit)";
-			data = /incbin/("spl/u-boot-spl-nodtb.bin$HS_APPEND");
-			type = "standalone";
-			os = "U-Boot";
-			arch = "arm64";
-			compression = "none";
-			load = <0x80080000>;
-			entry = <0x80080000>;
-		};
-__HEADER_EOF
-
-# shift through ATF load address in the command line arguments
-shift
-
-for dtname in $*
-do
-	cat << __FDT_IMAGE_EOF
-		$(basename $dtname) {
-			description = "$(basename $dtname .dtb)";
-			data = /incbin/("$dtname$HS_APPEND");
-			type = "flat_dt";
-			arch = "arm";
-			compression = "none";
-		};
-__FDT_IMAGE_EOF
-done
-
-cat << __CONF_HEADER_EOF
-	};
-	configurations {
-		default = "$(basename $1)";
-
-__CONF_HEADER_EOF
-
-for dtname in $*
-do
-	cat << __CONF_SECTION_EOF
-		$(basename $dtname) {
-			description = "$(basename $dtname .dtb)";
-			firmware = "atf";
-			loadables = "tee", "dm", "spl";
-			fdt = "$(basename $dtname)";
-		};
-__CONF_SECTION_EOF
-done
-
-cat << __ITS_EOF
-	};
-};
-__ITS_EOF
diff --git a/tools/k3_gen_x509_cert.sh b/tools/k3_gen_x509_cert.sh
deleted file mode 100755
index d9cde07417..0000000000
--- a/tools/k3_gen_x509_cert.sh
+++ /dev/null
@@ -1,262 +0,0 @@
-#!/bin/bash
-# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-#
-# Script to add K3 specific x509 cetificate to a binary.
-#
-
-# Variables
-OUTPUT=tiboot3.bin
-TEMP_X509=x509-temp.cert
-CERT=certificate.bin
-RAND_KEY=eckey.pem
-LOADADDR=0x41c00000
-BOOTCORE_OPTS=0
-BOOTCORE=16
-DEBUG_TYPE=0
-SWRV=1
-
-gen_degen_template() {
-cat << 'EOF' > degen-template.txt
-
-asn1=SEQUENCE:rsa_key
-
-[rsa_key]
-version=INTEGER:0
-modulus=INTEGER:0xDEGEN_MODULUS
-pubExp=INTEGER:1
-privExp=INTEGER:1
-p=INTEGER:0xDEGEN_P
-q=INTEGER:0xDEGEN_Q
-e1=INTEGER:1
-e2=INTEGER:1
-coeff=INTEGER:0xDEGEN_COEFF
-EOF
-}
-
-# Generate x509 Template
-gen_template() {
-cat << 'EOF' > x509-template.txt
- [ req ]
- distinguished_name     = req_distinguished_name
- x509_extensions        = v3_ca
- prompt                 = no
- dirstring_type         = nobmp
-
- [ req_distinguished_name ]
- C                      = US
- ST                     = TX
- L                      = Dallas
- O                      = Texas Instruments Incorporated
- OU                     = Processors
- CN                     = TI support
- emailAddress           = support@ti.com
-
- [ v3_ca ]
- basicConstraints = CA:true
- 1.3.6.1.4.1.294.1.1 = ASN1:SEQUENCE:boot_seq
- 1.3.6.1.4.1.294.1.2 = ASN1:SEQUENCE:image_integrity
- 1.3.6.1.4.1.294.1.3 = ASN1:SEQUENCE:swrv
-# 1.3.6.1.4.1.294.1.4 = ASN1:SEQUENCE:encryption
- 1.3.6.1.4.1.294.1.8 = ASN1:SEQUENCE:debug
-
- [ boot_seq ]
- certType = INTEGER:TEST_CERT_TYPE
- bootCore = INTEGER:TEST_BOOT_CORE
- bootCoreOpts = INTEGER:TEST_BOOT_CORE_OPTS
- destAddr = FORMAT:HEX,OCT:TEST_BOOT_ADDR
- imageSize = INTEGER:TEST_IMAGE_LENGTH
-
- [ image_integrity ]
- shaType = OID:2.16.840.1.101.3.4.2.3
- shaValue = FORMAT:HEX,OCT:TEST_IMAGE_SHA_VAL
-
- [ swrv ]
- swrv = INTEGER:TEST_SWRV
-
-# [ encryption ]
-# initalVector = FORMAT:HEX,OCT:TEST_IMAGE_ENC_IV
-# randomString = FORMAT:HEX,OCT:TEST_IMAGE_ENC_RS
-# iterationCnt = INTEGER:TEST_IMAGE_KEY_DERIVE_INDEX
-# salt = FORMAT:HEX,OCT:TEST_IMAGE_KEY_DERIVE_SALT
-
- [ debug ]
- debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000
- debugType = INTEGER:TEST_DEBUG_TYPE
- coreDbgEn = INTEGER:0
- coreDbgSecEn = INTEGER:0
-EOF
-}
-
-parse_key() {
-	sed '/    /s/://g' key.txt | \
-            awk  '!/    / {printf("\n%s\n", $0)}; /    / {printf("%s", $0)}' | \
-            sed 's/    //g' | \
-            awk "/$1:/{getline; print}"
-}
-
-gen_degen_key() {
-# Generate a 4096 bit RSA Key
-	openssl genrsa -out key.pem 1024 >>/dev/null 2>&1
-	openssl rsa -in key.pem -text -out key.txt >>/dev/null 2>&1
-	DEGEN_MODULUS=$( parse_key 'modulus' )
-	DEGEN_P=$( parse_key 'prime1' )
-	DEGEN_Q=$( parse_key 'prime2' )
-	DEGEN_COEFF=$( parse_key 'coefficient' )
-	gen_degen_template
-
-	sed -e "s/DEGEN_MODULUS/$DEGEN_MODULUS/"\
-		-e "s/DEGEN_P/$DEGEN_P/" \
-		-e "s/DEGEN_Q/$DEGEN_Q/" \
-		-e "s/DEGEN_COEFF/$DEGEN_COEFF/" \
-		 degen-template.txt > degenerateKey.txt
-
-	openssl asn1parse -genconf degenerateKey.txt -out degenerateKey.der >>/dev/null 2>&1
-	openssl rsa -in degenerateKey.der -inform DER -outform PEM -out $RAND_KEY >>/dev/null 2>&1
-	KEY=$RAND_KEY
-	rm key.pem key.txt degen-template.txt degenerateKey.txt degenerateKey.der
-}
-
-declare -A options_help
-usage() {
-	if [ -n "$*" ]; then
-		echo "ERROR: $*"
-	fi
-	echo -n "Usage: $0 "
-	for option in "${!options_help[@]}"
-	do
-		arg=`echo ${options_help[$option]}|cut -d ':' -f1`
-		if [ -n "$arg" ]; then
-			arg=" $arg"
-		fi
-		echo -n "[-$option$arg] "
-	done
-	echo
-	echo -e "\nWhere:"
-	for option in "${!options_help[@]}"
-	do
-		arg=`echo ${options_help[$option]}|cut -d ':' -f1`
-		txt=`echo ${options_help[$option]}|cut -d ':' -f2`
-		tb="\t\t\t"
-		if [ -n "$arg" ]; then
-			arg=" $arg"
-			tb="\t"
-		fi
-		echo -e "   -$option$arg:$tb$txt"
-	done
-	echo
-	echo "Examples of usage:-"
-	echo "# Example of signing the SYSFW binary with rsa degenerate key"
-	echo "    $0 -c 0 -b ti-sci-firmware-am6x.bin -o sysfw.bin -l 0x40000"
-	echo "# Example of signing the SPL binary with rsa degenerate key"
-	echo "    $0 -c 16 -b spl/u-boot-spl.bin -o tiboot3.bin -l 0x41c00000"
-}
-
-options_help[b]="bin_file:Bin file that needs to be signed"
-options_help[k]="key_file:file with key inside it. If not provided script generates a rsa degenerate key."
-options_help[o]="output_file:Name of the final output file. default to $OUTPUT"
-options_help[c]="core_id:target core id on which the image would be running. Default to $BOOTCORE"
-options_help[l]="loadaddr: Target load address of the binary in hex. Default to $LOADADDR"
-options_help[d]="debug_type: Debug type, set to 4 to enable early JTAG. Default to $DEBUG_TYPE"
-options_help[r]="SWRV: Software Rev for X509 certificate"
-
-while getopts "b:k:o:c:l:d:h:r:" opt
-do
-	case $opt in
-	b)
-		BIN=$OPTARG
-	;;
-	k)
-		KEY=$OPTARG
-	;;
-	o)
-		OUTPUT=$OPTARG
-	;;
-	l)
-		LOADADDR=$OPTARG
-	;;
-	c)
-		BOOTCORE=$OPTARG
-	;;
-	d)
-		DEBUG_TYPE=$OPTARG
-	;;
-        r)
-		SWRV=$OPTARG
-	;;
-	h)
-		usage
-		exit 0
-	;;
-	\?)
-		usage "Invalid Option '-$OPTARG'"
-		exit 1
-	;;
-	:)
-		usage "Option '-$OPTARG' Needs an argument."
-		exit 1
-	;;
-	esac
-done
-
-if [ "$#" -eq 0 ]; then
-	usage "Arguments missing"
-	exit 1
-fi
-
-if [ -z "$BIN" ]; then
-	usage "Bin file missing in arguments"
-	exit 1
-fi
-
-# Generate rsa degenerate key if user doesn't provide a key
-if [ -z "$KEY" ]; then
-	gen_degen_key
-fi
-
-if [ $BOOTCORE == 0 ]; then	# BOOTCORE M3, loaded by ROM
-	CERTTYPE=2
-elif [ $BOOTCORE == 16 ]; then	# BOOTCORE R5, loaded by ROM
-	CERTTYPE=1
-else				# Non BOOTCORE, loaded by SYSFW
-	BOOTCORE_OPTS_VER=$(printf "%01x" 1)
-	# Add input args option for SET and CLR flags.
-	BOOTCORE_OPTS_SETFLAG=$(printf "%08x" 0)
-	BOOTCORE_OPTS_CLRFLAG=$(printf "%08x" 0x100) # Clear FLAG_ARMV8_AARCH32
-	BOOTCORE_OPTS="0x$BOOTCORE_OPTS_VER$BOOTCORE_OPTS_SETFLAG$BOOTCORE_OPTS_CLRFLAG"
-	# Set the cert type to zero.
-	# We are not using public/private key store now
-	CERTTYPE=$(printf "0x%08x" 0)
-fi
-
-SHA_VAL=`openssl dgst -sha512 -hex $BIN | sed -e "s/^.*= //g"`
-BIN_SIZE=`cat $BIN | wc -c`
-ADDR=`printf "%08x" $LOADADDR`
-
-gen_cert() {
-	#echo "Certificate being generated :"
-	#echo "	LOADADDR = 0x$ADDR"
-	#echo "	IMAGE_SIZE = $BIN_SIZE"
-	#echo "	CERT_TYPE = $CERTTYPE"
-	#echo "	DEBUG_TYPE = $DEBUG_TYPE"
-	#echo " SWRV = $SWRV"
-	sed -e "s/TEST_IMAGE_LENGTH/$BIN_SIZE/"	\
-		-e "s/TEST_IMAGE_SHA_VAL/$SHA_VAL/" \
-		-e "s/TEST_CERT_TYPE/$CERTTYPE/" \
-		-e "s/TEST_BOOT_CORE_OPTS/$BOOTCORE_OPTS/" \
-		-e "s/TEST_BOOT_CORE/$BOOTCORE/" \
-		-e "s/TEST_BOOT_ADDR/$ADDR/" \
-		-e "s/TEST_DEBUG_TYPE/$DEBUG_TYPE/" \
-                -e "s/TEST_SWRV/$SWRV/" \
-		x509-template.txt > $TEMP_X509
-	openssl req -new -x509 -key $KEY -nodes -outform DER -out $CERT -config $TEMP_X509 -sha512
-}
-
-gen_template
-gen_cert
-cat $CERT $BIN > $OUTPUT
-
-# Remove all intermediate files
-rm $TEMP_X509 $CERT x509-template.txt
-if [ "$KEY" == "$RAND_KEY" ]; then
-	rm $RAND_KEY
-fi
diff --git a/tools/logos/st.bmp b/tools/logos/st.bmp
new file mode 100644
index 0000000000..f59d3c5cef
--- /dev/null
+++ b/tools/logos/st.bmp
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index b71537beee..52be1f122e 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -41,6 +41,7 @@ static struct option options[] = {
 	{"guid", required_argument, NULL, 'g'},
 	{"index", required_argument, NULL, 'i'},
 	{"instance", required_argument, NULL, 'I'},
+	{"fw-version", required_argument, NULL, 'v'},
 	{"private-key", required_argument, NULL, 'p'},
 	{"certificate", required_argument, NULL, 'c'},
 	{"monotonic-count", required_argument, NULL, 'm'},
@@ -60,6 +61,7 @@ static void print_usage(void)
 		"\t-g, --guid <guid string>    guid for image blob type\n"
 		"\t-i, --index <index>         update image index\n"
 		"\t-I, --instance <instance>   update hardware instance\n"
+		"\t-v, --fw-version <version>  firmware version\n"
 		"\t-p, --private-key <privkey file>  private key file\n"
 		"\t-c, --certificate <cert file>     signer's certificate file\n"
 		"\t-m, --monotonic-count <count>     monotonic count\n"
@@ -402,6 +404,7 @@ static void free_sig_data(struct auth_context *ctx)
  */
 static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
 			unsigned long index, unsigned long instance,
+			struct fmp_payload_header_params *fmp_ph_params,
 			uint64_t mcount, char *privkey_file, char *cert_file,
 			uint16_t oemflags)
 {
@@ -410,10 +413,11 @@ static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
 	struct efi_firmware_management_capsule_image_header image;
 	struct auth_context auth_context;
 	FILE *f;
-	uint8_t *data;
+	uint8_t *data, *new_data, *buf;
 	off_t bin_size;
 	uint64_t offset;
 	int ret;
+	struct fmp_payload_header payload_header;
 
 #ifdef DEBUG
 	fprintf(stderr, "For output: %s\n", path);
@@ -423,6 +427,7 @@ static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
 	auth_context.sig_size = 0;
 	f = NULL;
 	data = NULL;
+	new_data = NULL;
 	ret = -1;
 
 	/*
@@ -431,12 +436,30 @@ static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
 	if (read_bin_file(bin, &data, &bin_size))
 		goto err;
 
+	buf = data;
+
+	/* insert fmp payload header right before the payload */
+	if (fmp_ph_params->have_header) {
+		new_data = malloc(bin_size + sizeof(payload_header));
+		if (!new_data)
+			goto err;
+
+		payload_header.signature = FMP_PAYLOAD_HDR_SIGNATURE;
+		payload_header.header_size = sizeof(payload_header);
+		payload_header.fw_version = fmp_ph_params->fw_version;
+		payload_header.lowest_supported_version = 0; /* not used */
+		memcpy(new_data, &payload_header, sizeof(payload_header));
+		memcpy(new_data + sizeof(payload_header), data, bin_size);
+		buf = new_data;
+		bin_size += sizeof(payload_header);
+	}
+
 	/* first, calculate signature to determine its size */
 	if (privkey_file && cert_file) {
 		auth_context.key_file = privkey_file;
 		auth_context.cert_file = cert_file;
 		auth_context.auth.monotonic_count = mcount;
-		auth_context.image_data = data;
+		auth_context.image_data = buf;
 		auth_context.image_size = bin_size;
 
 		if (create_auth_data(&auth_context)) {
@@ -536,7 +559,7 @@ static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
 	/*
 	 * firmware binary
 	 */
-	if (write_capsule_file(f, data, bin_size, "Firmware binary"))
+	if (write_capsule_file(f, buf, bin_size, "Firmware binary"))
 		goto err;
 
 	ret = 0;
@@ -545,6 +568,7 @@ err:
 		fclose(f);
 	free_sig_data(&auth_context);
 	free(data);
+	free(new_data);
 
 	return ret;
 }
@@ -644,6 +668,7 @@ int main(int argc, char **argv)
 	unsigned long oemflags;
 	char *privkey_file, *cert_file;
 	int c, idx;
+	struct fmp_payload_header_params fmp_ph_params = { 0 };
 
 	guid = NULL;
 	index = 0;
@@ -679,6 +704,10 @@ int main(int argc, char **argv)
 		case 'I':
 			instance = strtoul(optarg, NULL, 0);
 			break;
+		case 'v':
+			fmp_ph_params.fw_version = strtoul(optarg, NULL, 0);
+			fmp_ph_params.have_header = true;
+			break;
 		case 'p':
 			if (privkey_file) {
 				fprintf(stderr,
@@ -751,7 +780,7 @@ int main(int argc, char **argv)
 			exit(EXIT_FAILURE);
 		}
 	} else 	if (create_fwbin(argv[argc - 1], argv[argc - 2], guid,
-				 index, instance, mcount, privkey_file,
+				 index, instance, &fmp_ph_params, mcount, privkey_file,
 				 cert_file, (uint16_t)oemflags) < 0) {
 		fprintf(stderr, "Creating firmware capsule failed\n");
 		exit(EXIT_FAILURE);
diff --git a/tools/mkfwumdata.c b/tools/mkfwumdata.c
new file mode 100644
index 0000000000..9732a8ddc5
--- /dev/null
+++ b/tools/mkfwumdata.c
@@ -0,0 +1,334 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <errno.h>
+#include <getopt.h>
+#include <limits.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <u-boot/crc.h>
+#include <unistd.h>
+#include <uuid/uuid.h>
+
+/* This will dynamically allocate the fwu_mdata */
+#define CONFIG_FWU_NUM_BANKS		0
+#define CONFIG_FWU_NUM_IMAGES_PER_BANK	0
+
+/* Since we can not include fwu.h, redefine version here. */
+#define FWU_MDATA_VERSION		1
+
+typedef uint8_t u8;
+typedef int16_t s16;
+typedef uint16_t u16;
+typedef uint32_t u32;
+typedef uint64_t u64;
+
+#include <fwu_mdata.h>
+
+/* TODO: Endianness conversion may be required for some arch. */
+
+static const char *opts_short = "b:i:a:p:gh";
+
+static struct option options[] = {
+	{"banks", required_argument, NULL, 'b'},
+	{"images", required_argument, NULL, 'i'},
+	{"guid", required_argument, NULL, 'g'},
+	{"active-bank", required_argument, NULL, 'a'},
+	{"previous-bank", required_argument, NULL, 'p'},
+	{"help", no_argument, NULL, 'h'},
+	{NULL, 0, NULL, 0},
+};
+
+static void print_usage(void)
+{
+	fprintf(stderr, "Usage: mkfwumdata [options] <UUIDs list> <output file>\n");
+	fprintf(stderr, "Options:\n"
+		"\t-i, --images <num>          Number of images (mandatory)\n"
+		"\t-b, --banks  <num>          Number of banks (mandatory)\n"
+		"\t-a, --active-bank  <num>    Active bank (default=0)\n"
+		"\t-p, --previous-bank  <num>  Previous active bank (default=active_bank - 1)\n"
+		"\t-g, --guid                  Use GUID instead of UUID\n"
+		"\t-h, --help                  print a help message\n"
+		);
+	fprintf(stderr, "  UUIDs list syntax:\n"
+		"\t  <location uuid>,<image type uuid>,<images uuid list>\n"
+		"\t     images uuid list syntax:\n"
+		"\t        img_uuid_00,img_uuid_01...img_uuid_0b,\n"
+		"\t        img_uuid_10,img_uuid_11...img_uuid_1b,\n"
+		"\t        ...,\n"
+		"\t        img_uuid_i0,img_uuid_i1...img_uuid_ib,\n"
+		"\t          where 'b' and 'i' are number of banks and number\n"
+		"\t          of images in a bank respectively.\n"
+	       );
+}
+
+struct fwu_mdata_object {
+	size_t images;
+	size_t banks;
+	size_t size;
+	struct fwu_mdata *mdata;
+};
+
+static int previous_bank, active_bank;
+static bool __use_guid;
+
+static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks)
+{
+	struct fwu_mdata_object *mobj;
+
+	mobj = calloc(1, sizeof(*mobj));
+	if (!mobj)
+		return NULL;
+
+	mobj->size = sizeof(struct fwu_mdata) +
+		(sizeof(struct fwu_image_entry) +
+		 sizeof(struct fwu_image_bank_info) * banks) * images;
+	mobj->images = images;
+	mobj->banks = banks;
+
+	mobj->mdata = calloc(1, mobj->size);
+	if (!mobj->mdata) {
+		free(mobj);
+		return NULL;
+	}
+
+	return mobj;
+}
+
+static struct fwu_image_entry *
+fwu_get_image(struct fwu_mdata_object *mobj, size_t idx)
+{
+	size_t offset;
+
+	offset = sizeof(struct fwu_mdata) +
+		(sizeof(struct fwu_image_entry) +
+		 sizeof(struct fwu_image_bank_info) * mobj->banks) * idx;
+
+	return (struct fwu_image_entry *)((char *)mobj->mdata + offset);
+}
+
+static struct fwu_image_bank_info *
+fwu_get_bank(struct fwu_mdata_object *mobj, size_t img_idx, size_t bnk_idx)
+{
+	size_t offset;
+
+	offset = sizeof(struct fwu_mdata) +
+		(sizeof(struct fwu_image_entry) +
+		 sizeof(struct fwu_image_bank_info) * mobj->banks) * img_idx +
+		sizeof(struct fwu_image_entry) +
+		sizeof(struct fwu_image_bank_info) * bnk_idx;
+
+	return (struct fwu_image_bank_info *)((char *)mobj->mdata + offset);
+}
+
+/**
+ * convert_uuid_to_guid() - convert UUID to GUID
+ * @buf:	UUID binary
+ *
+ * UUID and GUID have the same data structure, but their binary
+ * formats are different due to the endianness. See lib/uuid.c.
+ * Since uuid_parse() can handle only UUID, this function must
+ * be called to get correct data for GUID when parsing a string.
+ *
+ * The correct data will be returned in @buf.
+ */
+static void convert_uuid_to_guid(unsigned char *buf)
+{
+	unsigned char c;
+
+	c = buf[0];
+	buf[0] = buf[3];
+	buf[3] = c;
+	c = buf[1];
+	buf[1] = buf[2];
+	buf[2] = c;
+
+	c = buf[4];
+	buf[4] = buf[5];
+	buf[5] = c;
+
+	c = buf[6];
+	buf[6] = buf[7];
+	buf[7] = c;
+}
+
+static int uuid_guid_parse(char *uuidstr, unsigned char *uuid)
+{
+	int ret;
+
+	ret = uuid_parse(uuidstr, uuid);
+	if (ret < 0)
+		return ret;
+
+	if (__use_guid)
+		convert_uuid_to_guid(uuid);
+
+	return ret;
+}
+
+static int
+fwu_parse_fill_image_uuid(struct fwu_mdata_object *mobj,
+			  size_t idx, char *uuids)
+{
+	struct fwu_image_entry *image = fwu_get_image(mobj, idx);
+	struct fwu_image_bank_info *bank;
+	char *p = uuids, *uuid;
+	int i;
+
+	if (!image)
+		return -ENOENT;
+
+	/* Image location UUID */
+	uuid = strsep(&p, ",");
+	if (!uuid)
+		return -EINVAL;
+
+	if (strcmp(uuid, "0") &&
+	    uuid_guid_parse(uuid, (unsigned char *)&image->location_uuid) < 0)
+		return -EINVAL;
+
+	/* Image type UUID */
+	uuid = strsep(&p, ",");
+	if (!uuid)
+		return -EINVAL;
+
+	if (uuid_guid_parse(uuid, (unsigned char *)&image->image_type_uuid) < 0)
+		return -EINVAL;
+
+	/* Fill bank image-UUID */
+	for (i = 0; i < mobj->banks; i++) {
+		bank = fwu_get_bank(mobj, idx, i);
+		if (!bank)
+			return -ENOENT;
+		bank->accepted = 1;
+		uuid = strsep(&p, ",");
+		if (!uuid)
+			return -EINVAL;
+
+		if (strcmp(uuid, "0") &&
+		    uuid_guid_parse(uuid, (unsigned char *)&bank->image_uuid) < 0)
+			return -EINVAL;
+	}
+	return 0;
+}
+
+/* Caller must ensure that @uuids[] has @mobj->images entries. */
+static int fwu_parse_fill_uuids(struct fwu_mdata_object *mobj, char *uuids[])
+{
+	struct fwu_mdata *mdata = mobj->mdata;
+	int i, ret;
+
+	mdata->version = FWU_MDATA_VERSION;
+	mdata->active_index = active_bank;
+	mdata->previous_active_index = previous_bank;
+
+	for (i = 0; i < mobj->images; i++) {
+		ret = fwu_parse_fill_image_uuid(mobj, i, uuids[i]);
+		if (ret < 0)
+			return ret;
+	}
+
+	mdata->crc32 = crc32(0, (const unsigned char *)&mdata->version,
+			     mobj->size - sizeof(uint32_t));
+
+	return 0;
+}
+
+static int
+fwu_make_mdata(size_t images, size_t banks, char *uuids[], char *output)
+{
+	struct fwu_mdata_object *mobj;
+	FILE *file;
+	int ret;
+
+	mobj = fwu_alloc_mdata(images, banks);
+	if (!mobj)
+		return -ENOMEM;
+
+	ret = fwu_parse_fill_uuids(mobj, uuids);
+	if (ret < 0)
+		goto done_make;
+
+	file = fopen(output, "w");
+	if (!file) {
+		ret = -errno;
+		goto done_make;
+	}
+
+	ret = fwrite(mobj->mdata, mobj->size, 1, file);
+	if (ret != mobj->size)
+		ret = -errno;
+	else
+		ret = 0;
+
+	fclose(file);
+
+done_make:
+	free(mobj->mdata);
+	free(mobj);
+
+	return ret;
+}
+
+int main(int argc, char *argv[])
+{
+	unsigned long banks = 0, images = 0;
+	int c, ret;
+
+	/* Explicitly initialize defaults */
+	active_bank = 0;
+	__use_guid = false;
+	previous_bank = INT_MAX;
+
+	do {
+		c = getopt_long(argc, argv, opts_short, options, NULL);
+		switch (c) {
+		case 'h':
+			print_usage();
+			return 0;
+		case 'b':
+			banks = strtoul(optarg, NULL, 0);
+			break;
+		case 'i':
+			images = strtoul(optarg, NULL, 0);
+			break;
+		case 'g':
+			__use_guid = true;
+			break;
+		case 'p':
+			previous_bank = strtoul(optarg, NULL, 0);
+			break;
+		case 'a':
+			active_bank = strtoul(optarg, NULL, 0);
+			break;
+		}
+	} while (c != -1);
+
+	if (!banks || !images) {
+		fprintf(stderr, "Error: The number of banks and images must not be 0.\n");
+		return -EINVAL;
+	}
+
+	/* This command takes UUIDs * images and output file. */
+	if (optind + images + 1 != argc) {
+		fprintf(stderr, "Error: UUID list or output file is not specified or too much.\n");
+		print_usage();
+		return -ERANGE;
+	}
+
+	if (previous_bank == INT_MAX) {
+		/* set to the earlier bank in round-robin scheme */
+		previous_bank = active_bank > 0 ? active_bank - 1 : banks - 1;
+	}
+
+	ret = fwu_make_mdata(images, banks, argv + optind, argv[argc - 1]);
+	if (ret < 0)
+		fprintf(stderr, "Error: Failed to parse and write image: %s\n",
+			strerror(-ret));
+
+	return ret;
+}
diff --git a/tools/mkimage.h b/tools/mkimage.h
index f5ca65e2ed..d92a3ff811 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -17,6 +17,7 @@
 #include <sys/stat.h>
 #include <time.h>
 #include <unistd.h>
+#include <limits.h>
 #include <u-boot/sha1.h>
 #include "fdt_host.h"
 #include "imagetool.h"
@@ -44,7 +45,7 @@ static inline ulong map_to_sysmem(void *ptr)
 #define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) type name[size]
 
 #define MKIMAGE_TMPFILE_SUFFIX		".tmp"
-#define MKIMAGE_MAX_TMPFILE_LEN		256
+#define MKIMAGE_MAX_TMPFILE_LEN		PATH_MAX
 #define MKIMAGE_DEFAULT_DTC_OPTIONS	"-I dts -O dtb -p 500"
 #define MKIMAGE_MAX_DTC_CMDLINE_LEN	2 * MKIMAGE_MAX_TMPFILE_LEN + 35
 
diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index c4d72ede36..6cbecc3d5c 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -2037,7 +2037,7 @@ doc/develop/moveconfig.rst for documentation.'''
 
     if not args.cleanup_headers_only:
         check_clean_directory()
-        bsettings.Setup('')
+        bsettings.setup('')
         toolchains = toolchain.Toolchains()
         toolchains.GetSettings()
         toolchains.Scan(verbose=False)
diff --git a/tools/mtk_image.c b/tools/mtk_image.c
index 30f54c8e8d..1b1aed5992 100644
--- a/tools/mtk_image.c
+++ b/tools/mtk_image.c
@@ -542,11 +542,13 @@ static void put_brom_layout_header(struct brom_layout_header *hdr, int type)
 	hdr->type = cpu_to_le32(type);
 }
 
-static void put_ghf_common_header(struct gfh_common_header *gfh, int size,
-				  int type, int ver)
+static void put_ghf_common_header(struct gfh_common_header *gfh, uint16_t size,
+				  uint16_t type, uint8_t ver)
 {
-	memcpy(gfh->magic, GFH_HEADER_MAGIC, sizeof(gfh->magic));
-	gfh->version = ver;
+	uint32_t magic_version = GFH_HEADER_MAGIC |
+				 (uint32_t)ver << GFH_HEADER_VERSION_SHIFT;
+
+	gfh->magic_version = cpu_to_le32(magic_version);
 	gfh->size = cpu_to_le16(size);
 	gfh->type = cpu_to_le16(type);
 }
diff --git a/tools/mtk_image.h b/tools/mtk_image.h
index fad9372100..54a838de86 100644
--- a/tools/mtk_image.h
+++ b/tools/mtk_image.h
@@ -63,13 +63,13 @@ struct gen_device_header {
 
 /* BootROM header definitions */
 struct gfh_common_header {
-	uint8_t magic[3];
-	uint8_t version;
+	uint32_t magic_version;
 	uint16_t size;
 	uint16_t type;
 };
 
-#define GFH_HEADER_MAGIC	"MMM"
+#define GFH_HEADER_MAGIC		0x4D4D4D
+#define GFH_HEADER_VERSION_SHIFT	24
 
 #define GFH_TYPE_FILE_INFO	0
 #define GFH_TYPE_BL_INFO	1
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index fe8cd6bda9..f230ec5676 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -521,7 +521,7 @@ static int rela_elf32(char **argv, FILE *f)
 		uint32_t pos = rela_start + sizeof(Elf32_Rela) * i;
 		uint32_t addr, pos_dyn;
 
-		debug("\nPossition:\t%d/0x%x\n", i, pos);
+		debug("\nPosition:\t%d/0x%x\n", i, pos);
 
 		if (fseek(f, pos, SEEK_SET) < 0) {
 			fprintf(stderr, "%s: %s: seek to %" PRIx32
diff --git a/tools/renesas_spkgimage.c b/tools/renesas_spkgimage.c
index fa0a468cc4..5cd81dd5bf 100644
--- a/tools/renesas_spkgimage.c
+++ b/tools/renesas_spkgimage.c
@@ -73,7 +73,7 @@ static int spkgimage_parse_config_line(char *line, size_t line_num)
 		conf.padding = check_range(name, value, 1, INT_MAX);
 	} else {
 		fprintf(stderr,
-			"config error: unknown keyword on line %ld\n",
+			"config error: unknown keyword on line %zu\n",
 			line_num);
 		return -EINVAL;
 	}
diff --git a/tools/u_boot_pylib/pyproject.toml b/tools/u_boot_pylib/pyproject.toml
index 3f33caf6f8..037c5d629e 100644
--- a/tools/u_boot_pylib/pyproject.toml
+++ b/tools/u_boot_pylib/pyproject.toml
@@ -9,7 +9,7 @@ authors = [
   { name="Simon Glass", email="sjg@chromium.org" },
 ]
 description = "U-Boot python library"
-readme = "README.md"
+readme = "README.rst"
 requires-python = ">=3.7"
 classifiers = [
     "Programming Language :: Python :: 3",
@@ -20,3 +20,7 @@ classifiers = [
 [project.urls]
 "Homepage" = "https://u-boot.readthedocs.io"
 "Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues"
+
+[tool.setuptools.packages.find]
+where = [".."]
+include = ["u_boot_pylib*"]
diff --git a/tools/u_boot_pylib/test_util.py b/tools/u_boot_pylib/test_util.py
index e7564e10c9..f18d385d99 100644
--- a/tools/u_boot_pylib/test_util.py
+++ b/tools/u_boot_pylib/test_util.py
@@ -24,7 +24,7 @@ except:
 
 
 def run_test_coverage(prog, filter_fname, exclude_list, build_dir, required=None,
-                    extra_args=None):
+                    extra_args=None, single_thread='-P1'):
     """Run tests and check that we get 100% coverage
 
     Args:
@@ -39,6 +39,9 @@ def run_test_coverage(prog, filter_fname, exclude_list, build_dir, required=None
         required: List of modules which must be in the coverage report
         extra_args (str): Extra arguments to pass to the tool before the -t/test
             arg
+        single_thread (str): Argument string to make the tests run
+            single-threaded. This is necessary to get proper coverage results.
+            The default is '-P0'
 
     Raises:
         ValueError if the code coverage is not 100%
@@ -58,8 +61,9 @@ def run_test_coverage(prog, filter_fname, exclude_list, build_dir, required=None
     if build_dir:
         prefix = 'PYTHONPATH=$PYTHONPATH:%s/sandbox_spl/tools ' % build_dir
     cmd = ('%spython3-coverage run '
-           '--omit "%s" %s %s %s -P1' % (prefix, ','.join(glob_list),
-                                         prog, extra_args or '', test_cmd))
+           '--omit "%s" %s %s %s %s' % (prefix, ','.join(glob_list),
+                                        prog, extra_args or '', test_cmd,
+                                        single_thread or '-P1'))
     os.system(cmd)
     stdout = command.output('python3-coverage', 'report')
     lines = stdout.splitlines()
diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh
index 16c622f6ce..5c8b73703b 100755
--- a/tools/zynqmp_psu_init_minimize.sh
+++ b/tools/zynqmp_psu_init_minimize.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 # SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2018 Michal Simek <michal.simek@xilinx.com>
+# Copyright (C) 2018 Michal Simek <michal.simek@amd.com>
 # Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net>
 # Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG
 # Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c
index 5113ba895f..bb54f41a15 100644
--- a/tools/zynqmpimage.c
+++ b/tools/zynqmpimage.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2016 Michal Simek <michals@xilinx.com>
+ * Copyright (C) 2016 Michal Simek <michal.simek@amd.com>
  * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
  *
  * The following Boot Header format/structures and values are defined in the
diff --git a/tools/zynqmpimage.h b/tools/zynqmpimage.h
index 9d526a17cd..ca7489835a 100644
--- a/tools/zynqmpimage.h
+++ b/tools/zynqmpimage.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2016 Michal Simek <michals@xilinx.com>
+ * Copyright (C) 2016 Michal Simek <michal.simek@amd.com>
  * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
  *
  * The following Boot Header format/structures and values are defined in the