diff options
| -rw-r--r-- | arch/x86/Kconfig | 7 | ||||
| -rw-r--r-- | arch/x86/dts/u-boot.dtsi | 6 | ||||
| -rw-r--r-- | configs/chromebox_panther_defconfig | 2 |
3 files changed, 13 insertions, 2 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 01ffaea132..cbca69ef6b 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -594,8 +594,13 @@ config HAVE_REFCODE Various peripherals may fail to work. config HAVE_MICROCODE - bool + bool "Board requires a microcode binary" default y if !FSP_VERSION2 + help + Enable this if the board requires microcode to be loaded on boot. + Typically this is handed by the FSP for modern boards, but for + some older boards, it must be programmed by U-Boot, and that form + part of the image. config SMP bool "Enable Symmetric Multiprocessing" diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 1e0a985b43..fa8106c8b8 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -75,11 +75,15 @@ u-boot { offset = <CONFIG_SYS_TEXT_BASE>; }; -# else +# elif defined(CONFIG_HAVE_MICROCODE) /* If there is no SPL then we need to put microcode in U-Boot */ u-boot-with-ucode-ptr { offset = <CONFIG_X86_OFFSET_U_BOOT>; }; +# else + u-boot-nodtb { + offset = <CONFIG_X86_OFFSET_U_BOOT>; + }; # endif #endif #ifdef CONFIG_HAVE_MICROCODE diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index d559e034b1..701edf0d07 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -8,7 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther" CONFIG_VENDOR_GOOGLE=y CONFIG_TARGET_CHROMEBOX_PANTHER=y CONFIG_HAVE_MRC=y +# CONFIG_HAVE_MICROCODE is not set CONFIG_HAVE_VGA_BIOS=y +CONFIG_X86_OFFSET_U_BOOT=0xffa00000 CONFIG_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y |