diff options
| -rw-r--r-- | arch/arm/include/asm/arch-omap3/dss.h | 37 | ||||
| -rw-r--r-- | drivers/video/Makefile | 2 | ||||
| -rw-r--r-- | drivers/video/omap3_dss.c | 44 |
3 files changed, 80 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h index 4c56e5e9e6..101e8c8e29 100644 --- a/arch/arm/include/asm/arch-omap3/dss.h +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -31,12 +31,18 @@ /* * DSS Base Registers */ -#define OMAP3_DSS_BASE 0x48050040 -#define OMAP3_DISPC_BASE 0x48050440 +#define OMAP3_DSS_BASE 0x48050000 +#define OMAP3_DISPC_BASE 0x48050400 #define OMAP3_VENC_BASE 0x48050C00 /* DSS Registers */ struct dss_regs { + u32 revision; /* 0x00 */ + u8 res1[12]; /* 0x04 */ + u32 sysconfig; /* 0x10 */ + u32 sysstatus; /* 0x14 */ + u32 irqstatus; /* 0x18 */ + u8 res2[36]; /* 0x1C */ u32 control; /* 0x40 */ u32 sdi_control; /* 0x44 */ u32 pll_control; /* 0x48 */ @@ -44,6 +50,13 @@ struct dss_regs { /* DISPC Registers */ struct dispc_regs { + u32 revision; /* 0x00 */ + u8 res1[12]; /* 0x04 */ + u32 sysconfig; /* 0x10 */ + u32 sysstatus; /* 0x14 */ + u32 irqstatus; /* 0x18 */ + u32 irqenable; /* 0x1C */ + u8 res2[32]; /* 0x20 */ u32 control; /* 0x40 */ u32 config; /* 0x44 */ u32 reserve_2; /* 0x48 */ @@ -60,6 +73,18 @@ struct dispc_regs { u32 global_alpha; /* 0x74 */ u32 size_dig; /* 0x78 */ u32 size_lcd; /* 0x7C */ + u32 gfx_ba0; /* 0x80 */ + u32 gfx_ba1; /* 0x84 */ + u32 gfx_position; /* 0x88 */ + u32 gfx_size; /* 0x8C */ + u8 unused[16]; /* 0x90 */ + u32 gfx_attributes; /* 0xA0 */ + u32 gfx_fifo_threshold; /* 0xA4 */ + u32 gfx_fifo_size_status; /* 0xA8 */ + u32 gfx_row_inc; /* 0xAC */ + u32 gfx_pixel_inc; /* 0xB0 */ + u32 gfx_window_skip; /* 0xB4 */ + u32 gfx_table_ba; /* 0xB8 */ }; /* VENC Registers */ @@ -123,6 +148,13 @@ struct venc_regs { #define TFTSTN_SHIFT 3 #define DATALINES_SHIFT 8 +#define GFX_ENABLE 1 +#define GFX_FORMAT_SHIFT 1 +#define LOADMODE_SHIFT 1 + +#define DSS_SOFTRESET (1 << 1) +#define DSS_RESETDONE 1 + /* Enabling Display controller */ #define LCD_ENABLE 1 #define DIG_ENABLE (1 << 1) @@ -161,6 +193,7 @@ struct panel_config { u32 data_lines; u32 load_mode; u32 panel_color; + void *frame_buffer; }; /* diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 4fad20dd6e..842cbdf8ff 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -42,7 +42,7 @@ COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o -COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o videomodes.o +COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o COBJS-$(CONFIG_VIDEO_SM501) += sm501.o COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c index b322cc3579..dfe61b348c 100644 --- a/drivers/video/omap3_dss.c +++ b/drivers/video/omap3_dss.c @@ -28,6 +28,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/dss.h> +#include <video_fb.h> /* * Configure VENC for a given Mode (NTSC / PAL) @@ -105,6 +106,11 @@ void omap3_dss_venc_config(const struct venc_regs *venc_cfg, void omap3_dss_panel_config(const struct panel_config *panel_cfg) { struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE; + + writel(DSS_SOFTRESET, &dss->sysconfig); + while (!(readl(&dss->sysstatus) & DSS_RESETDONE)) + ; writel(panel_cfg->timing_h, &dispc->timing_h); writel(panel_cfg->timing_v, &dispc->timing_v); @@ -115,6 +121,16 @@ void omap3_dss_panel_config(const struct panel_config *panel_cfg) writel(((panel_cfg->panel_type << TFTSTN_SHIFT) | (panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control); writel(panel_cfg->panel_color, &dispc->default_color0); + writel((u32) panel_cfg->frame_buffer, &dispc->gfx_ba0); + + if (!panel_cfg->frame_buffer) + return; + + writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config); + writel(8 << GFX_FORMAT_SHIFT | GFX_ENABLE, &dispc->gfx_attributes); + writel(1, &dispc->gfx_row_inc); + writel(1, &dispc->gfx_pixel_inc); + writel(panel_cfg->lcd_size, &dispc->gfx_size); } /* @@ -129,3 +145,31 @@ void omap3_dss_enable(void) l |= DISPC_ENABLE; writel(l, &dispc->control); } + +#ifdef CONFIG_CFB_CONSOLE +int __board_video_init(void) +{ + return -1; +} + +int board_video_init(void) + __attribute__((weak, alias("__board_video_init"))); + +void *video_hw_init(void) +{ + static GraphicDevice dssfb; + GraphicDevice *pGD = &dssfb; + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + + if (board_video_init() || !readl(&dispc->gfx_ba0)) + return NULL; + + pGD->winSizeX = (readl(&dispc->size_lcd) & 0x7FF) + 1; + pGD->winSizeY = ((readl(&dispc->size_lcd) >> 16) & 0x7FF) + 1; + pGD->gdfBytesPP = 4; + pGD->gdfIndex = GDF_32BIT_X888RGB; + pGD->frameAdrs = readl(&dispc->gfx_ba0); + + return pGD; +} +#endif |