diff options
-rw-r--r-- | arch/mips/dts/Makefile | 1 | ||||
-rw-r--r-- | arch/mips/dts/mrvl,octeon-nic23.dts | 162 | ||||
-rw-r--r-- | arch/mips/mach-octeon/Kconfig | 7 | ||||
-rw-r--r-- | board/Marvell/octeon_nic23/Kconfig | 19 | ||||
-rw-r--r-- | board/Marvell/octeon_nic23/MAINTAINERS | 7 | ||||
-rw-r--r-- | board/Marvell/octeon_nic23/Makefile | 8 | ||||
-rw-r--r-- | board/Marvell/octeon_nic23/board.c | 106 | ||||
-rw-r--r-- | board/Marvell/octeon_nic23/board_ddr.h | 269 | ||||
-rw-r--r-- | configs/octeon_nic23_defconfig | 70 | ||||
-rw-r--r-- | include/configs/octeon_nic23.h | 21 |
10 files changed, 670 insertions, 0 deletions
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 7c42923134..215283cfa0 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -20,6 +20,7 @@ dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb +dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb diff --git a/arch/mips/dts/mrvl,octeon-nic23.dts b/arch/mips/dts/mrvl,octeon-nic23.dts new file mode 100644 index 0000000000..72ef56d834 --- /dev/null +++ b/arch/mips/dts/mrvl,octeon-nic23.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Marvell / Cavium Inc. NIC23 + */ + +/dts-v1/; + +#include "mrvl,cn73xx.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "cavium,nic23"; + compatible = "cavium,nic23"; + + aliases { + mmc0 = &mmc0; + serial0 = &uart0; + spi0 = &spi; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + /* Power on GPIO 8, active high */ + reg_mmc_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "mmc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&bootbus { + /* + * bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000) + * as the initial size is too small for the 8MiB flash device + */ + ranges = <0 0 0 0x1f400000 0xc00000>, + <1 0 0x10000 0x10000000 0>, + <2 0 0x10000 0x20000000 0>, + <3 0 0x10000 0x30000000 0>, + <4 0 0 0x1d020000 0x10000>, + <5 0 0x10000 0x50000000 0>, + <6 0 0x10000 0x60000000 0>, + <7 0 0x10000 0x70000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <10>; + cavium,t-ce = <50>; + cavium,t-oe = <50>; + cavium,t-we = <35>; + cavium,t-rd-hld = <25>; + cavium,t-wr-hld = <35>; + cavium,t-pause = <0>; + cavium,t-wait = <50>; + cavium,t-page = <30>; + cavium,t-rd-dly = <0>; + cavium,page-mode = <1>; + cavium,pages = <8>; + cavium,bus-width = <8>; + }; + + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <10>; + cavium,t-ce = <10>; + cavium,t-oe = <160>; + cavium,t-we = <100>; + cavium,t-rd-hld = <10>; + cavium,t-wr-hld = <0>; + cavium,t-pause = <50>; + cavium,t-wait = <50>; + cavium,t-page = <10>; + cavium,t-rd-dly = <10>; + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "bootloader"; + reg = <0 0x340000>; + read-only; + }; + partition@300000 { + label = "storage"; + reg = <0x340000 0x4be000>; + }; + partition@7fe000 { + label = "environment"; + reg = <0x7fe000 0x2000>; + read-only; + }; + }; +}; + +&uart0 { + clock-frequency = <800000000>; +}; + +&i2c0 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +}; + +&i2c1 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +}; + +&mmc { + status = "okay"; + + mmc0: mmc-slot@0 { + compatible = "cavium,octeon-6130-mmc-slot", "mmc-slot"; + reg = <0>; + vqmmc-supply = <®_mmc_3v3>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <52000000>; + /* bus width can be 1, 4 or 8 */ + bus-width = <8>; /* new std property */ + cavium,bus-max-width = <8>; /* custom property */ + non-removable; + }; +}; + +&soc0 { + pci-console@0 { + compatible = "marvell,pci-console"; + status = "okay"; + }; + + pci-bootcmd@0 { + compatible = "marvell,pci-bootcmd"; + status = "okay"; + }; +}; + +&spi { + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <2000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig index d69408cc27..624039df25 100644 --- a/arch/mips/mach-octeon/Kconfig +++ b/arch/mips/mach-octeon/Kconfig @@ -41,6 +41,12 @@ config TARGET_OCTEON_EBB7304 help Choose this for the Octeon EBB7304 board +config TARGET_OCTEON_NIC23 + bool "Marvell Octeon NIC23" + select OCTEON_CN73XX + help + Choose this for the Octeon NIC23 board + endchoice config SYS_DCACHE_SIZE @@ -60,5 +66,6 @@ config SYS_PCI_64BIT default y source "board/Marvell/octeon_ebb7304/Kconfig" +source "board/Marvell/octeon_nic23/Kconfig" endmenu diff --git a/board/Marvell/octeon_nic23/Kconfig b/board/Marvell/octeon_nic23/Kconfig new file mode 100644 index 0000000000..3c42e8acda --- /dev/null +++ b/board/Marvell/octeon_nic23/Kconfig @@ -0,0 +1,19 @@ +if TARGET_OCTEON_NIC23 + +config SYS_BOARD + string + default "octeon_nic23" + +config SYS_VENDOR + string + default "Marvell" + +config SYS_CONFIG_NAME + string + default "octeon_nic23" + +config DEFAULT_DEVICE_TREE + string + default "mrvl,octeon-nic23" + +endif diff --git a/board/Marvell/octeon_nic23/MAINTAINERS b/board/Marvell/octeon_nic23/MAINTAINERS new file mode 100644 index 0000000000..cd5148dcfe --- /dev/null +++ b/board/Marvell/octeon_nic23/MAINTAINERS @@ -0,0 +1,7 @@ +OCTEON_NIC23 BOARD +M: Aaron Williams <awilliams@marvell.com> +S: Maintained +F: board/Marvell/octeon_nic23/* +F: configs/octeon_nic23_defconfig +F: include/configs/octeon_nic23.h +F: arch/mips/dts/mrvl,octeon-nic23.dts diff --git a/board/Marvell/octeon_nic23/Makefile b/board/Marvell/octeon_nic23/Makefile new file mode 100644 index 0000000000..a79b94ec6f --- /dev/null +++ b/board/Marvell/octeon_nic23/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2021 Stefan Roese <sr@denx.de> +# Copyright (C) 2019-2020 Marvell International Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/Marvell/octeon_nic23/board.c b/board/Marvell/octeon_nic23/board.c new file mode 100644 index 0000000000..9f5eb2e2a1 --- /dev/null +++ b/board/Marvell/octeon_nic23/board.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Stefan Roese <sr@denx.de> + */ + +#include <dm.h> +#include <ram.h> + +#include <mach/octeon_ddr.h> +#include <mach/cvmx-qlm.h> +#include <mach/octeon_qlm.h> +#include <mach/octeon_fdt.h> +#include <mach/cvmx-helper.h> +#include <mach/cvmx-helper-cfg.h> +#include <mach/cvmx-helper-util.h> +#include <mach/cvmx-bgxx-defs.h> + +#include "board_ddr.h" + +#define NIC23_DEF_DRAM_FREQ 800 + +static u8 octeon_nic23_cfg0_spd_values[512] = { + OCTEON_NIC23_CFG0_SPD_VALUES +}; + +static struct ddr_conf board_ddr_conf[] = { + OCTEON_NIC23_DDR_CONFIGURATION +}; + +struct ddr_conf *octeon_ddr_conf_table_get(int *count, int *def_ddr_freq) +{ + *count = ARRAY_SIZE(board_ddr_conf); + *def_ddr_freq = NIC23_DEF_DRAM_FREQ; + + return board_ddr_conf; +} + +int board_fix_fdt(void *fdt) +{ + u32 range_data[5 * 8]; + bool rev4; + int node; + int rc; + + /* + * ToDo: + * Read rev4 info from EEPROM or where the original U-Boot does + * and don't hard-code it here. + */ + rev4 = true; + + debug("%s() rev4: %s\n", __func__, rev4 ? "true" : "false"); + /* Patch the PHY configuration based on board revision */ + rc = octeon_fdt_patch_rename(fdt, + rev4 ? "4,nor-flash" : "4,no-nor-flash", + "cavium,board-trim", false, NULL, NULL); + if (!rev4) { + /* Modify the ranges for CS 0 */ + node = fdt_node_offset_by_compatible(fdt, -1, + "cavium,octeon-3860-bootbus"); + if (node < 0) { + printf("%s: Error: cannot find boot bus in device tree!\n", + __func__); + return -1; + } + + rc = fdtdec_get_int_array(fdt, node, "ranges", + range_data, 5 * 8); + if (rc) { + printf("%s: Error reading ranges from boot bus FDT\n", + __func__); + return -1; + } + range_data[2] = cpu_to_fdt32(0x10000); + range_data[3] = 0; + range_data[4] = 0; + rc = fdt_setprop(fdt, node, "ranges", range_data, + sizeof(range_data)); + if (rc) { + printf("%s: Error updating boot bus ranges in fdt\n", + __func__); + } + } + return rc; +} + +void board_configure_qlms(void) +{ + octeon_configure_qlm(4, 3000, CVMX_QLM_MODE_SATA_2X1, 0, 0, 0, 0); + octeon_configure_qlm(5, 103125, CVMX_QLM_MODE_XFI_1X2, 0, 0, 2, 0); + /* Apply amplitude tuning to 10G interface */ + octeon_qlm_tune_v3(0, 4, 3000, -1, -1, 7, -1); + octeon_qlm_tune_v3(0, 5, 103125, 0x19, 0x0, -1, -1); + octeon_qlm_set_channel_v3(0, 5, 0); + octeon_qlm_dfe_disable(0, 5, -1, 103125, CVMX_QLM_MODE_XFI_1X2); + debug("QLM 4 reference clock: %d\n" + "DLM 5 reference clock: %d\n", + cvmx_qlm_measure_clock(4), cvmx_qlm_measure_clock(5)); +} + +int board_late_init(void) +{ + board_configure_qlms(); + + return 0; +} diff --git a/board/Marvell/octeon_nic23/board_ddr.h b/board/Marvell/octeon_nic23/board_ddr.h new file mode 100644 index 0000000000..eac877faf8 --- /dev/null +++ b/board/Marvell/octeon_nic23/board_ddr.h @@ -0,0 +1,269 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __BOARD_DDR_H__ +#define __BOARD_DDR_H__ + +#define OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0 \ + { {0x0, 0x0}, {octeon_nic23_cfg0_spd_values, NULL} } + +#define NIC23_MTA8ATF51264AZ2G3_SPD_VALUES \ + 0x23, 0x10, 0x0c, 0x02, 0x84, 0x19, 0x00, 0x08, \ + 0x00, 0x00, 0x00, 0x03, 0x01, 0x0b, 0x80, 0x00, \ + 0x00, 0x00, 0x08, 0x0c, 0xf4, 0x1b, 0x00, 0x00, \ + 0x6c, 0x6c, 0x6c, 0x11, 0x08, 0x74, 0x20, 0x08, \ + 0x00, 0x05, 0x70, 0x03, 0x00, 0xa8, 0x1e, 0x2b, \ + 0x2b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x0c, 0x2c, 0x15, 0x35, \ + 0x15, 0x35, 0x0b, 0x2c, 0x15, 0x35, 0x0b, 0x35, \ + 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0xec, 0xb5, 0xce, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x30, 0x0e, \ + 0x11, 0x11, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x2e, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x80, 0x2c, 0x0f, 0x14, 0x50, 0x0e, 0x08, 0x18, \ + 0xc8, 0x31, 0x38, 0x41, 0x53, 0x46, 0x31, 0x47, \ + 0x37, 0x32, 0x41, 0x5a, 0x2d, 0x32, 0x47, 0x31, \ + 0x41, 0x31, 0x20, 0x20, 0x20, 0x31, 0x80, 0x2c, \ + 0x41, 0x44, 0x50, 0x41, 0x45, 0x4e, 0x43, 0x39, \ + 0x30, 0x30, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + +#define OCTEON_NIC23_CFG0_SPD_VALUES NIC23_MTA8ATF51264AZ2G3_SPD_VALUES + +#define OCTEON_NIC23_BOARD_EEPROM_TWSI_ADDR 0x56 + +#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT \ +{ \ + .cn78xx = { \ + .pasr_00 = 0, \ + .asr_00 = 0, \ + .srt_00 = 0, \ + .rtt_wr_00 = ddr4_rttwr_80ohm & 3, \ + .rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \ + .dic_00 = ddr4_dic_34ohm, \ + .rtt_nom_00 = 0, \ + .pasr_01 = 0, \ + .asr_01 = 0, \ + .srt_01 = 0, \ + .rtt_wr_01 = 0, \ + .dic_01 = ddr4_dic_34ohm, \ + .rtt_nom_01 = 0, \ + .pasr_10 = 0, \ + .asr_10 = 0, \ + .srt_10 = 0, \ + .rtt_wr_10 = 0, \ + .dic_10 = ddr4_dic_34ohm, \ + .rtt_nom_10 = 0, \ + .pasr_11 = 0, \ + .asr_11 = 0, \ + .srt_11 = 0, \ + .rtt_wr_11 = 0, \ + .dic_11 = ddr4_dic_34ohm, \ + .rtt_nom_11 = 0, \ + } \ + } + +#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT \ +{ \ + .cn78xx = { \ + .pasr_00 = 0, \ + .asr_00 = 0, \ + .srt_00 = 0, \ + .rtt_wr_00 = ddr4_rttwr_80ohm & 3, \ + .rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \ + .dic_00 = ddr4_dic_34ohm, \ + .rtt_nom_00 = 0, \ + .pasr_01 = 0, \ + .asr_01 = 0, \ + .srt_01 = 0, \ + .rtt_wr_01 = 0, \ + .dic_01 = ddr4_dic_34ohm, \ + .rtt_nom_01 = 0, \ + .pasr_10 = 0, \ + .asr_10 = 0, \ + .srt_10 = 0, \ + .rtt_wr_10 = ddr4_rttwr_80ohm & 3, \ + .rtt_wr_10_ext = (ddr4_rttwr_80ohm >> 2) & 1, \ + .dic_10 = ddr4_dic_34ohm, \ + .rtt_nom_10 = 0, \ + .pasr_11 = 0, \ + .asr_11 = 0, \ + .srt_11 = 0, \ + .rtt_wr_11 = 0, \ + .dic_11 = ddr4_dic_34ohm, \ + .rtt_nom_11 = 0 \ + } \ +} + +#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT \ +{ \ + .cn78xx = { \ + .rtt_park_00 = ddr4_rttpark_60ohm, \ + .vref_value_00 = 0x22, \ + .vref_range_00 = 0, \ + .rtt_park_01 = 0, \ + .vref_value_01 = 0, \ + .vref_range_01 = 0, \ + .rtt_park_10 = 0, \ + .vref_value_10 = 0, \ + .vref_range_10 = 0, \ + .rtt_park_11 = 0, \ + .vref_value_11 = 0, \ + .vref_range_11 = 0 \ + } \ +} + +#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT \ +{ \ + .cn78xx = { \ + .rtt_park_00 = ddr4_rttpark_48ohm, \ + .vref_value_00 = 0x1f, \ + .vref_range_00 = 0, \ + .rtt_park_01 = 0, \ + .vref_value_01 = 0, \ + .vref_range_01 = 0, \ + .rtt_park_10 = ddr4_rttpark_48ohm, \ + .vref_value_10 = 0x1f, \ + .vref_range_10 = 0, \ + .rtt_park_11 = 0, \ + .vref_value_11 = 0, \ + .vref_range_11 = 0 \ + } \ +} + +#define OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION \ + /* 1 */ \ + { \ + ddr4_dqx_driver_34_ohm, \ + 0x00000000ULL, \ + OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT, \ + OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT, \ + ddr4_rodt_ctl_48_ohm, \ + 0x00000000ULL, \ + 0 \ + }, \ + /* 2 */ \ + { \ + ddr4_dqx_driver_34_ohm, \ + 0x00000000ULL, \ + OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT, \ + OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT, \ + ddr4_rodt_ctl_80_ohm, \ + 0x00000000ULL, \ + 0 \ + } + +/* + * Construct a static initializer for the ddr_configuration_t variable that + * holds (almost) all of the information required for DDR initialization. + */ + +/* + * The parameters below make up the custom_lmc_config data structure. + * This structure is used to customize the way that the LMC DRAM + * Controller is configured for a particular board design. + * + * Refer to the file lib_octeon_board_table_entry.h for a description + * of the custom board settings. It is usually kept in the following + * location... arch/mips/include/asm/arch-octeon/ + * + */ + +#define OCTEON_NIC23_DDR_CONFIGURATION \ +/* Interface 0 */ \ +{ \ + .custom_lmc_config = { \ + .min_rtt_nom_idx = 2, \ + .max_rtt_nom_idx = 5, \ + .min_rodt_ctl = 2, \ + .max_rodt_ctl = 4, \ + .ck_ctl = ddr4_driver_34_ohm, \ + .cmd_ctl = ddr4_driver_34_ohm, \ + .ctl_ctl = ddr4_driver_34_ohm, \ + .min_cas_latency = 7, \ + .offset_en = 1, \ + .offset_udimm = 2, \ + .offset_rdimm = 2, \ + .ddr_rtt_nom_auto = 0, \ + .ddr_rodt_ctl_auto = 0, \ + .rlevel_compute = 0, \ + .ddr2t_udimm = 1, \ + .ddr2t_rdimm = 1, \ + .maximum_adjacent_rlevel_delay_increment = 2, \ + .fprch2 = 2, \ + .dll_write_offset = NULL, \ + .dll_read_offset = NULL, \ + .disable_sequential_delay_check = 1, \ + .parity = 0 \ + }, \ + .dimm_config_table = { \ + OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0, \ + DIMM_CONFIG_TERMINATOR \ + }, \ + .unbuffered = { \ + .ddr_board_delay = 0, \ + .lmc_delay_clk = 0, \ + .lmc_delay_cmd = 0, \ + .lmc_delay_dq = 0 \ + }, \ + .registered = { \ + .ddr_board_delay = 0, \ + .lmc_delay_clk = 0, \ + .lmc_delay_cmd = 0, \ + .lmc_delay_dq = 0 \ + }, \ + .odt_1rank_config = { \ + OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION \ + }, \ +}, + +#endif /* __BOARD_DDR_H__ */ diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig new file mode 100644 index 0000000000..f36af437c0 --- /dev/null +++ b/configs/octeon_nic23_defconfig @@ -0,0 +1,70 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0xffffffff80000000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xe000 +CONFIG_ENV_SECT_SIZE=0x100 +CONFIG_DEBUG_UART_BASE=0x8001180000000800 +CONFIG_DEBUG_UART_CLOCK=800000000 +CONFIG_ARCH_OCTEON=y +CONFIG_TARGET_OCTEON_NIC23=y +# CONFIG_MIPS_CACHE_SETUP is not set +# CONFIG_MIPS_CACHE_DISABLE is not set +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_SYS_DEVICE_NULLDEV is not set +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0xe000 +CONFIG_SATA=y +CONFIG_AHCI_MVEBU=y +CONFIG_CLK=y +# CONFIG_INPUT is not set +CONFIG_MISC=y +CONFIG_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_OCTEONTX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_NETDEVICES is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_RAM=y +CONFIG_RAM_OCTEON=y +CONFIG_RAM_OCTEON_DDR4=y +CONFIG_SCSI=y +CONFIG_DEBUG_UART_SHIFT=3 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_OCTEON_SERIAL_BOOTCMD=y +CONFIG_OCTEON_SERIAL_PCIE_CONSOLE=y +CONFIG_SPI=y +CONFIG_OCTEON_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_OCTEON=y +CONFIG_HEXDUMP=y diff --git a/include/configs/octeon_nic23.h b/include/configs/octeon_nic23.h new file mode 100644 index 0000000000..0a7b4d8f93 --- /dev/null +++ b/include/configs/octeon_nic23.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-2020 + * Marvell <www.marvell.com> + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +/* + * SATA/SCSI/AHCI configuration + */ +/* AHCI support Definitions */ +/** Enable 48-bit SATA addressing */ +#define CONFIG_LBA48 +/** Enable 64-bit addressing */ +#define CONFIG_SYS_64BIT_LBA + +#include "octeon_common.h" + +#endif /* __CONFIG_H__ */ |